SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
99.64 | 99.36 | 98.73 | 100.00 | 100.00 | 100.00 | 99.77 |
T509 | /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4218372914 | Aug 08 05:51:08 PM PDT 24 | Aug 08 05:51:08 PM PDT 24 | 12810054 ps | ||
T79 | /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1033348630 | Aug 08 05:51:26 PM PDT 24 | Aug 08 05:51:27 PM PDT 24 | 16192044 ps | ||
T510 | /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.4218723005 | Aug 08 05:51:57 PM PDT 24 | Aug 08 05:51:58 PM PDT 24 | 67551473 ps | ||
T511 | /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3621097237 | Aug 08 05:51:37 PM PDT 24 | Aug 08 05:51:40 PM PDT 24 | 993755201 ps | ||
T512 | /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1952798170 | Aug 08 05:51:59 PM PDT 24 | Aug 08 05:52:00 PM PDT 24 | 47435641 ps | ||
T513 | /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.233625237 | Aug 08 05:50:47 PM PDT 24 | Aug 08 05:50:47 PM PDT 24 | 26570704 ps | ||
T514 | /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.681500504 | Aug 08 05:51:56 PM PDT 24 | Aug 08 05:51:57 PM PDT 24 | 31772117 ps | ||
T515 | /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.4055279898 | Aug 08 05:51:59 PM PDT 24 | Aug 08 05:52:00 PM PDT 24 | 15255297 ps | ||
T516 | /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2598809212 | Aug 08 05:50:49 PM PDT 24 | Aug 08 05:50:50 PM PDT 24 | 27498757 ps | ||
T517 | /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1132660695 | Aug 08 05:51:49 PM PDT 24 | Aug 08 05:51:50 PM PDT 24 | 109523058 ps | ||
T518 | /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4267007949 | Aug 08 05:51:16 PM PDT 24 | Aug 08 05:51:17 PM PDT 24 | 33422734 ps | ||
T80 | /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2046866823 | Aug 08 05:51:26 PM PDT 24 | Aug 08 05:51:26 PM PDT 24 | 26668582 ps | ||
T519 | /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3468858048 | Aug 08 05:51:57 PM PDT 24 | Aug 08 05:51:58 PM PDT 24 | 58266217 ps | ||
T520 | /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2392912612 | Aug 08 05:51:49 PM PDT 24 | Aug 08 05:51:50 PM PDT 24 | 99127720 ps | ||
T521 | /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3413189066 | Aug 08 05:51:36 PM PDT 24 | Aug 08 05:51:36 PM PDT 24 | 38740069 ps | ||
T81 | /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2100619488 | Aug 08 05:51:26 PM PDT 24 | Aug 08 05:51:26 PM PDT 24 | 11378531 ps | ||
T522 | /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4031224740 | Aug 08 05:51:58 PM PDT 24 | Aug 08 05:51:59 PM PDT 24 | 45675921 ps | ||
T523 | /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1052245490 | Aug 08 05:51:26 PM PDT 24 | Aug 08 05:51:27 PM PDT 24 | 391339198 ps | ||
T524 | /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4193767176 | Aug 08 05:52:01 PM PDT 24 | Aug 08 05:52:01 PM PDT 24 | 24049867 ps | ||
T525 | /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3095017844 | Aug 08 05:50:57 PM PDT 24 | Aug 08 05:50:57 PM PDT 24 | 37800652 ps | ||
T526 | /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.4154535274 | Aug 08 05:51:58 PM PDT 24 | Aug 08 05:51:59 PM PDT 24 | 61569062 ps | ||
T527 | /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.887279049 | Aug 08 05:51:07 PM PDT 24 | Aug 08 05:51:08 PM PDT 24 | 54457220 ps | ||
T528 | /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1399420018 | Aug 08 05:51:36 PM PDT 24 | Aug 08 05:51:36 PM PDT 24 | 15255587 ps | ||
T529 | /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1413297611 | Aug 08 05:51:37 PM PDT 24 | Aug 08 05:51:38 PM PDT 24 | 38417909 ps | ||
T530 | /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.348654506 | Aug 08 05:51:48 PM PDT 24 | Aug 08 05:51:49 PM PDT 24 | 92978774 ps | ||
T531 | /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3595376682 | Aug 08 05:50:47 PM PDT 24 | Aug 08 05:50:49 PM PDT 24 | 533867331 ps | ||
T82 | /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2637236447 | Aug 08 05:50:36 PM PDT 24 | Aug 08 05:50:36 PM PDT 24 | 21319936 ps | ||
T532 | /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2258467035 | Aug 08 05:50:48 PM PDT 24 | Aug 08 05:50:49 PM PDT 24 | 88195917 ps | ||
T83 | /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1509035066 | Aug 08 05:50:47 PM PDT 24 | Aug 08 05:50:48 PM PDT 24 | 17832760 ps | ||
T533 | /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.77469042 | Aug 08 05:51:50 PM PDT 24 | Aug 08 05:51:51 PM PDT 24 | 13737748 ps | ||
T534 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1887314299 | Aug 08 05:50:49 PM PDT 24 | Aug 08 05:50:50 PM PDT 24 | 120937771 ps | ||
T535 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1644059000 | Aug 08 05:50:56 PM PDT 24 | Aug 08 05:50:59 PM PDT 24 | 337904401 ps | ||
T536 | /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3162550499 | Aug 08 05:52:49 PM PDT 24 | Aug 08 05:52:50 PM PDT 24 | 498936700 ps | ||
T537 | /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2728661564 | Aug 08 05:51:59 PM PDT 24 | Aug 08 05:52:00 PM PDT 24 | 46585717 ps | ||
T538 | /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3537615049 | Aug 08 05:51:57 PM PDT 24 | Aug 08 05:51:58 PM PDT 24 | 14124338 ps | ||
T539 | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2373242128 | Aug 08 05:51:58 PM PDT 24 | Aug 08 05:51:59 PM PDT 24 | 19064564 ps | ||
T540 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.628352823 | Aug 08 05:50:55 PM PDT 24 | Aug 08 05:50:56 PM PDT 24 | 12395910 ps | ||
T84 | /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.123771947 | Aug 08 05:50:57 PM PDT 24 | Aug 08 05:50:58 PM PDT 24 | 15473676 ps | ||
T541 | /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3611831936 | Aug 08 05:51:24 PM PDT 24 | Aug 08 05:51:25 PM PDT 24 | 57846808 ps | ||
T542 | /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2594133805 | Aug 08 05:51:26 PM PDT 24 | Aug 08 05:51:26 PM PDT 24 | 62470140 ps | ||
T543 | /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2404505968 | Aug 08 05:51:25 PM PDT 24 | Aug 08 05:51:26 PM PDT 24 | 299213236 ps | ||
T85 | /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2757118848 | Aug 08 05:53:03 PM PDT 24 | Aug 08 05:53:04 PM PDT 24 | 48414601 ps | ||
T544 | /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1551305513 | Aug 08 05:53:04 PM PDT 24 | Aug 08 05:53:07 PM PDT 24 | 261289875 ps | ||
T545 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.818159414 | Aug 08 05:50:49 PM PDT 24 | Aug 08 05:50:51 PM PDT 24 | 216922468 ps | ||
T546 | /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1394260059 | Aug 08 05:51:16 PM PDT 24 | Aug 08 05:51:17 PM PDT 24 | 60620118 ps | ||
T547 | /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3071309 | Aug 08 05:51:59 PM PDT 24 | Aug 08 05:51:59 PM PDT 24 | 39525063 ps | ||
T548 | /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2347091047 | Aug 08 05:50:39 PM PDT 24 | Aug 08 05:50:42 PM PDT 24 | 351362552 ps | ||
T549 | /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3730451514 | Aug 08 05:51:20 PM PDT 24 | Aug 08 05:51:21 PM PDT 24 | 46645545 ps | ||
T550 | /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1194734173 | Aug 08 05:51:47 PM PDT 24 | Aug 08 05:51:49 PM PDT 24 | 273486947 ps | ||
T551 | /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2019349514 | Aug 08 05:53:03 PM PDT 24 | Aug 08 05:53:06 PM PDT 24 | 239980765 ps | ||
T552 | /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3213811991 | Aug 08 05:50:47 PM PDT 24 | Aug 08 05:50:48 PM PDT 24 | 14650985 ps | ||
T553 | /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1952062406 | Aug 08 05:51:34 PM PDT 24 | Aug 08 05:51:35 PM PDT 24 | 34003879 ps | ||
T554 | /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.184187751 | Aug 08 05:51:37 PM PDT 24 | Aug 08 05:51:39 PM PDT 24 | 75254274 ps | ||
T555 | /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.539520778 | Aug 08 05:53:04 PM PDT 24 | Aug 08 05:53:05 PM PDT 24 | 54938265 ps | ||
T556 | /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3596777746 | Aug 08 05:51:47 PM PDT 24 | Aug 08 05:51:48 PM PDT 24 | 59832583 ps | ||
T557 | /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3066654946 | Aug 08 05:51:38 PM PDT 24 | Aug 08 05:51:39 PM PDT 24 | 64781800 ps | ||
T558 | /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2731143566 | Aug 08 05:51:36 PM PDT 24 | Aug 08 05:51:37 PM PDT 24 | 94567903 ps | ||
T559 | /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2640182325 | Aug 08 05:51:38 PM PDT 24 | Aug 08 05:51:41 PM PDT 24 | 382481440 ps | ||
T560 | /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.746951552 | Aug 08 05:51:20 PM PDT 24 | Aug 08 05:51:21 PM PDT 24 | 34287402 ps | ||
T561 | /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3652564314 | Aug 08 05:51:50 PM PDT 24 | Aug 08 05:51:51 PM PDT 24 | 79481647 ps | ||
T562 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1771292835 | Aug 08 05:50:48 PM PDT 24 | Aug 08 05:50:49 PM PDT 24 | 11580852 ps | ||
T563 | /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2549893574 | Aug 08 05:51:48 PM PDT 24 | Aug 08 05:51:49 PM PDT 24 | 39676164 ps | ||
T564 | /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3232933509 | Aug 08 05:50:37 PM PDT 24 | Aug 08 05:50:37 PM PDT 24 | 163091804 ps | ||
T565 | /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.657556322 | Aug 08 05:51:38 PM PDT 24 | Aug 08 05:51:39 PM PDT 24 | 26976957 ps | ||
T566 | /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.369017089 | Aug 08 05:50:57 PM PDT 24 | Aug 08 05:50:58 PM PDT 24 | 122939666 ps | ||
T86 | /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3436556458 | Aug 08 05:51:48 PM PDT 24 | Aug 08 05:51:49 PM PDT 24 | 96081347 ps | ||
T567 | /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3515075709 | Aug 08 05:52:01 PM PDT 24 | Aug 08 05:52:02 PM PDT 24 | 50580330 ps | ||
T568 | /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1367563108 | Aug 08 05:51:17 PM PDT 24 | Aug 08 05:51:17 PM PDT 24 | 17828765 ps | ||
T569 | /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1328273403 | Aug 08 05:51:27 PM PDT 24 | Aug 08 05:51:27 PM PDT 24 | 28365333 ps | ||
T570 | /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2099842980 | Aug 08 05:51:58 PM PDT 24 | Aug 08 05:51:59 PM PDT 24 | 32554127 ps | ||
T571 | /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2256707702 | Aug 08 05:51:15 PM PDT 24 | Aug 08 05:51:17 PM PDT 24 | 126554497 ps | ||
T572 | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2626022995 | Aug 08 05:51:58 PM PDT 24 | Aug 08 05:51:59 PM PDT 24 | 165405960 ps | ||
T573 | /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1319323896 | Aug 08 05:51:37 PM PDT 24 | Aug 08 05:51:38 PM PDT 24 | 46708810 ps | ||
T574 | /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3159162976 | Aug 08 05:50:47 PM PDT 24 | Aug 08 05:50:48 PM PDT 24 | 57241506 ps | ||
T575 | /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.5906791 | Aug 08 05:50:47 PM PDT 24 | Aug 08 05:50:48 PM PDT 24 | 141036172 ps | ||
T576 | /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2878627926 | Aug 08 05:50:47 PM PDT 24 | Aug 08 05:50:48 PM PDT 24 | 23350985 ps |
Test location | /workspace/coverage/default/4.rv_timer_random.817280533 |
Short name | T10 |
Test name | |
Test status | |
Simulation time | 261937482110 ps |
CPU time | 145.18 seconds |
Started | Aug 08 05:55:40 PM PDT 24 |
Finished | Aug 08 05:58:05 PM PDT 24 |
Peak memory | 191620 kb |
Host | smart-e163456f-6bff-4e73-a41d-6bf7611fec6a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817280533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.817280533 |
Directory | /workspace/4.rv_timer_random/latest |
Test location | /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.3209553675 |
Short name | T12 |
Test name | |
Test status | |
Simulation time | 99479070669 ps |
CPU time | 101.83 seconds |
Started | Aug 08 05:56:26 PM PDT 24 |
Finished | Aug 08 05:58:08 PM PDT 24 |
Peak memory | 206256 kb |
Host | smart-aa0732d7-a39e-49bb-8f44-beef2e86a7be |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209553675 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.3209553675 |
Directory | /workspace/44.rv_timer_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/11.rv_timer_stress_all.686380176 |
Short name | T35 |
Test name | |
Test status | |
Simulation time | 2906305569662 ps |
CPU time | 2269.3 seconds |
Started | Aug 08 05:55:45 PM PDT 24 |
Finished | Aug 08 06:33:35 PM PDT 24 |
Peak memory | 191668 kb |
Host | smart-d6831ff0-fce3-4a84-9d08-f71e54bd8fd5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686380176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all. 686380176 |
Directory | /workspace/11.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/14.rv_timer_stress_all.3985928421 |
Short name | T144 |
Test name | |
Test status | |
Simulation time | 1887255975542 ps |
CPU time | 5976.59 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 07:35:23 PM PDT 24 |
Peak memory | 197536 kb |
Host | smart-93955091-5308-4789-8ce3-a405167be96a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985928421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all .3985928421 |
Directory | /workspace/14.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/0.rv_timer_sec_cm.4185065712 |
Short name | T19 |
Test name | |
Test status | |
Simulation time | 50724144 ps |
CPU time | 0.74 seconds |
Started | Aug 08 05:55:33 PM PDT 24 |
Finished | Aug 08 05:55:34 PM PDT 24 |
Peak memory | 214096 kb |
Host | smart-a2a22f60-977a-4513-9ac3-b42607e5293b |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185065712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.4185065712 |
Directory | /workspace/0.rv_timer_sec_cm/latest |
Test location | /workspace/coverage/default/40.rv_timer_stress_all.2998447625 |
Short name | T113 |
Test name | |
Test status | |
Simulation time | 1562617582456 ps |
CPU time | 1326.47 seconds |
Started | Aug 08 05:56:22 PM PDT 24 |
Finished | Aug 08 06:18:29 PM PDT 24 |
Peak memory | 191692 kb |
Host | smart-3c626678-73fb-447c-9933-82a812251c8b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998447625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all .2998447625 |
Directory | /workspace/40.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_timer_stress_all.3301760033 |
Short name | T36 |
Test name | |
Test status | |
Simulation time | 558124370577 ps |
CPU time | 1305.54 seconds |
Started | Aug 08 05:55:47 PM PDT 24 |
Finished | Aug 08 06:17:33 PM PDT 24 |
Peak memory | 191556 kb |
Host | smart-3ad8f3f3-7322-4938-8434-51a6fc87aa81 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301760033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all .3301760033 |
Directory | /workspace/10.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_timer_stress_all.762224970 |
Short name | T166 |
Test name | |
Test status | |
Simulation time | 811306166192 ps |
CPU time | 2505.57 seconds |
Started | Aug 08 05:56:39 PM PDT 24 |
Finished | Aug 08 06:38:25 PM PDT 24 |
Peak memory | 191700 kb |
Host | smart-3d64d64f-17f8-4fa4-b7ff-d3e9567b0841 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762224970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all. 762224970 |
Directory | /workspace/48.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/76.rv_timer_random.3027707635 |
Short name | T119 |
Test name | |
Test status | |
Simulation time | 802438436260 ps |
CPU time | 904.29 seconds |
Started | Aug 08 05:56:55 PM PDT 24 |
Finished | Aug 08 06:11:59 PM PDT 24 |
Peak memory | 194436 kb |
Host | smart-937bdf21-ed31-40de-abd3-599faa0ae64a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027707635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3027707635 |
Directory | /workspace/76.rv_timer_random/latest |
Test location | /workspace/coverage/default/25.rv_timer_stress_all.1416888548 |
Short name | T215 |
Test name | |
Test status | |
Simulation time | 2822798603923 ps |
CPU time | 2415.94 seconds |
Started | Aug 08 05:56:05 PM PDT 24 |
Finished | Aug 08 06:36:21 PM PDT 24 |
Peak memory | 191684 kb |
Host | smart-491cd239-5045-4e3d-8df0-cb1836c50a3b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416888548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all .1416888548 |
Directory | /workspace/25.rv_timer_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3133836565 |
Short name | T69 |
Test name | |
Test status | |
Simulation time | 35423461 ps |
CPU time | 0.51 seconds |
Started | Aug 08 05:51:07 PM PDT 24 |
Finished | Aug 08 05:51:07 PM PDT 24 |
Peak memory | 182420 kb |
Host | smart-1b83774c-2c54-47d1-b7ee-79349b56b510 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133836565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r eset.3133836565 |
Directory | /workspace/4.rv_timer_csr_hw_reset/latest |
Test location | /workspace/coverage/default/19.rv_timer_stress_all.1701825465 |
Short name | T168 |
Test name | |
Test status | |
Simulation time | 605488408735 ps |
CPU time | 660.28 seconds |
Started | Aug 08 05:55:54 PM PDT 24 |
Finished | Aug 08 06:06:55 PM PDT 24 |
Peak memory | 195996 kb |
Host | smart-d36cf858-569c-4708-8bc2-920bd96d6fc7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701825465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all .1701825465 |
Directory | /workspace/19.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/33.rv_timer_stress_all.2204765798 |
Short name | T63 |
Test name | |
Test status | |
Simulation time | 5115663785588 ps |
CPU time | 1044.94 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 06:13:40 PM PDT 24 |
Peak memory | 196304 kb |
Host | smart-1b384a84-4ff0-4701-be67-b7b57c298809 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204765798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all .2204765798 |
Directory | /workspace/33.rv_timer_stress_all/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1344246701 |
Short name | T31 |
Test name | |
Test status | |
Simulation time | 107269212 ps |
CPU time | 0.84 seconds |
Started | Aug 08 05:51:37 PM PDT 24 |
Finished | Aug 08 05:51:38 PM PDT 24 |
Peak memory | 194108 kb |
Host | smart-45f4e247-4da8-45de-a9d2-0427b2405f10 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344246701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i ntg_err.1344246701 |
Directory | /workspace/12.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/default/42.rv_timer_stress_all.1759251865 |
Short name | T59 |
Test name | |
Test status | |
Simulation time | 994611757268 ps |
CPU time | 473.23 seconds |
Started | Aug 08 05:56:22 PM PDT 24 |
Finished | Aug 08 06:04:15 PM PDT 24 |
Peak memory | 191656 kb |
Host | smart-17bae55e-7184-423c-980a-3a1ee15043ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759251865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all .1759251865 |
Directory | /workspace/42.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/49.rv_timer_stress_all.3225445221 |
Short name | T118 |
Test name | |
Test status | |
Simulation time | 689698867717 ps |
CPU time | 997.28 seconds |
Started | Aug 08 05:56:46 PM PDT 24 |
Finished | Aug 08 06:13:23 PM PDT 24 |
Peak memory | 196988 kb |
Host | smart-608270f2-f149-4b88-bb2c-1ea36f56d10f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225445221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all .3225445221 |
Directory | /workspace/49.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/30.rv_timer_stress_all.486486864 |
Short name | T253 |
Test name | |
Test status | |
Simulation time | 364480253367 ps |
CPU time | 607.87 seconds |
Started | Aug 08 05:56:12 PM PDT 24 |
Finished | Aug 08 06:06:20 PM PDT 24 |
Peak memory | 191696 kb |
Host | smart-f18b35eb-e046-4333-8819-440014dab67a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486486864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all. 486486864 |
Directory | /workspace/30.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/33.rv_timer_random.988409336 |
Short name | T150 |
Test name | |
Test status | |
Simulation time | 219486077925 ps |
CPU time | 238.17 seconds |
Started | Aug 08 05:56:12 PM PDT 24 |
Finished | Aug 08 06:00:10 PM PDT 24 |
Peak memory | 191688 kb |
Host | smart-37a1dca3-a2b8-4271-825d-867812eb220f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988409336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.988409336 |
Directory | /workspace/33.rv_timer_random/latest |
Test location | /workspace/coverage/default/13.rv_timer_stress_all.2438376033 |
Short name | T225 |
Test name | |
Test status | |
Simulation time | 781355005261 ps |
CPU time | 1812.66 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 06:25:59 PM PDT 24 |
Peak memory | 191512 kb |
Host | smart-c1673594-ec61-4c2d-9a5e-273fb5252244 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438376033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all .2438376033 |
Directory | /workspace/13.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/31.rv_timer_stress_all.4166135016 |
Short name | T148 |
Test name | |
Test status | |
Simulation time | 172184001618 ps |
CPU time | 490.2 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 06:04:25 PM PDT 24 |
Peak memory | 191652 kb |
Host | smart-4414cd0a-beee-4f7c-9731-b5bfe18ac7d6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166135016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all .4166135016 |
Directory | /workspace/31.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/180.rv_timer_random.2505736978 |
Short name | T161 |
Test name | |
Test status | |
Simulation time | 1084129319941 ps |
CPU time | 2422.51 seconds |
Started | Aug 08 05:58:04 PM PDT 24 |
Finished | Aug 08 06:38:26 PM PDT 24 |
Peak memory | 194636 kb |
Host | smart-4bc4b205-a926-4007-8040-a22057f34188 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505736978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2505736978 |
Directory | /workspace/180.rv_timer_random/latest |
Test location | /workspace/coverage/default/193.rv_timer_random.647737166 |
Short name | T184 |
Test name | |
Test status | |
Simulation time | 698037779057 ps |
CPU time | 456.36 seconds |
Started | Aug 08 05:58:13 PM PDT 24 |
Finished | Aug 08 06:05:50 PM PDT 24 |
Peak memory | 191636 kb |
Host | smart-ac4e0a9e-4af1-41e0-bdc2-7dd155906d59 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647737166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.647737166 |
Directory | /workspace/193.rv_timer_random/latest |
Test location | /workspace/coverage/default/21.rv_timer_stress_all.923077837 |
Short name | T61 |
Test name | |
Test status | |
Simulation time | 1919975768135 ps |
CPU time | 1943.1 seconds |
Started | Aug 08 05:55:55 PM PDT 24 |
Finished | Aug 08 06:28:19 PM PDT 24 |
Peak memory | 191704 kb |
Host | smart-38bd6317-8c67-4fa9-926c-97eb1501aec6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923077837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all. 923077837 |
Directory | /workspace/21.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/50.rv_timer_random.2795731217 |
Short name | T234 |
Test name | |
Test status | |
Simulation time | 663993233873 ps |
CPU time | 1279.59 seconds |
Started | Aug 08 05:56:46 PM PDT 24 |
Finished | Aug 08 06:18:05 PM PDT 24 |
Peak memory | 191676 kb |
Host | smart-d295eba1-97f6-4f84-a5d6-f3d62eead2b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795731217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2795731217 |
Directory | /workspace/50.rv_timer_random/latest |
Test location | /workspace/coverage/default/117.rv_timer_random.1486630228 |
Short name | T187 |
Test name | |
Test status | |
Simulation time | 960789770158 ps |
CPU time | 561.65 seconds |
Started | Aug 08 05:57:26 PM PDT 24 |
Finished | Aug 08 06:06:47 PM PDT 24 |
Peak memory | 191604 kb |
Host | smart-347c4c8f-3450-4da0-bbf6-763ac8ba98b5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486630228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1486630228 |
Directory | /workspace/117.rv_timer_random/latest |
Test location | /workspace/coverage/default/11.rv_timer_random.2186259558 |
Short name | T208 |
Test name | |
Test status | |
Simulation time | 634359114525 ps |
CPU time | 319.09 seconds |
Started | Aug 08 05:55:50 PM PDT 24 |
Finished | Aug 08 06:01:10 PM PDT 24 |
Peak memory | 191604 kb |
Host | smart-e01d7e45-394f-4874-99fa-ca2564dbb69f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186259558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2186259558 |
Directory | /workspace/11.rv_timer_random/latest |
Test location | /workspace/coverage/default/181.rv_timer_random.5793897 |
Short name | T147 |
Test name | |
Test status | |
Simulation time | 682532113441 ps |
CPU time | 1443.84 seconds |
Started | Aug 08 05:58:05 PM PDT 24 |
Finished | Aug 08 06:22:10 PM PDT 24 |
Peak memory | 191660 kb |
Host | smart-1e0b3fdf-ba00-4458-8639-82e376c708c7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5793897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.5793897 |
Directory | /workspace/181.rv_timer_random/latest |
Test location | /workspace/coverage/default/195.rv_timer_random.2174115066 |
Short name | T162 |
Test name | |
Test status | |
Simulation time | 138032344015 ps |
CPU time | 215.82 seconds |
Started | Aug 08 05:58:22 PM PDT 24 |
Finished | Aug 08 06:01:58 PM PDT 24 |
Peak memory | 191636 kb |
Host | smart-caf35675-2118-464e-8826-02075cbabd9e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174115066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2174115066 |
Directory | /workspace/195.rv_timer_random/latest |
Test location | /workspace/coverage/default/20.rv_timer_stress_all.1391234506 |
Short name | T272 |
Test name | |
Test status | |
Simulation time | 787065914137 ps |
CPU time | 1832.85 seconds |
Started | Aug 08 05:55:56 PM PDT 24 |
Finished | Aug 08 06:26:29 PM PDT 24 |
Peak memory | 191596 kb |
Host | smart-7d064144-169b-4af0-88de-4d1c7eba3ddb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391234506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all .1391234506 |
Directory | /workspace/20.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_timer_stress_all.2387901746 |
Short name | T269 |
Test name | |
Test status | |
Simulation time | 4099958345806 ps |
CPU time | 3883.38 seconds |
Started | Aug 08 05:56:07 PM PDT 24 |
Finished | Aug 08 07:00:51 PM PDT 24 |
Peak memory | 191444 kb |
Host | smart-e36865e6-4a22-40b7-9c30-209c64012a6b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387901746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all .2387901746 |
Directory | /workspace/24.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/82.rv_timer_random.2680253713 |
Short name | T125 |
Test name | |
Test status | |
Simulation time | 104894112091 ps |
CPU time | 176.86 seconds |
Started | Aug 08 05:57:06 PM PDT 24 |
Finished | Aug 08 06:00:03 PM PDT 24 |
Peak memory | 191596 kb |
Host | smart-43376d06-5b9e-4446-8572-4bc33b7e3df0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680253713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2680253713 |
Directory | /workspace/82.rv_timer_random/latest |
Test location | /workspace/coverage/default/31.rv_timer_random.2822221101 |
Short name | T237 |
Test name | |
Test status | |
Simulation time | 254123960392 ps |
CPU time | 260.69 seconds |
Started | Aug 08 05:56:13 PM PDT 24 |
Finished | Aug 08 06:00:34 PM PDT 24 |
Peak memory | 191660 kb |
Host | smart-b68fbc8c-b09d-435d-818d-bc8b756b0322 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822221101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2822221101 |
Directory | /workspace/31.rv_timer_random/latest |
Test location | /workspace/coverage/default/68.rv_timer_random.2236966885 |
Short name | T96 |
Test name | |
Test status | |
Simulation time | 92867732232 ps |
CPU time | 237.12 seconds |
Started | Aug 08 05:56:54 PM PDT 24 |
Finished | Aug 08 06:00:52 PM PDT 24 |
Peak memory | 191696 kb |
Host | smart-df9369e0-9e33-42f8-b025-31139e42798f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236966885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2236966885 |
Directory | /workspace/68.rv_timer_random/latest |
Test location | /workspace/coverage/default/9.rv_timer_stress_all.3655066594 |
Short name | T198 |
Test name | |
Test status | |
Simulation time | 131138773065 ps |
CPU time | 183.51 seconds |
Started | Aug 08 05:55:47 PM PDT 24 |
Finished | Aug 08 05:58:51 PM PDT 24 |
Peak memory | 191604 kb |
Host | smart-7094b1d3-3515-47b9-973a-74a1bfc1aa38 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655066594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all. 3655066594 |
Directory | /workspace/9.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/12.rv_timer_stress_all.1043164389 |
Short name | T217 |
Test name | |
Test status | |
Simulation time | 372764832743 ps |
CPU time | 1363.86 seconds |
Started | Aug 08 05:55:51 PM PDT 24 |
Finished | Aug 08 06:18:35 PM PDT 24 |
Peak memory | 191680 kb |
Host | smart-60a96cb8-155a-488b-ac21-b120d45452f3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043164389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all .1043164389 |
Directory | /workspace/12.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/149.rv_timer_random.1115317773 |
Short name | T176 |
Test name | |
Test status | |
Simulation time | 205034878581 ps |
CPU time | 560.88 seconds |
Started | Aug 08 05:57:40 PM PDT 24 |
Finished | Aug 08 06:07:02 PM PDT 24 |
Peak memory | 191632 kb |
Host | smart-37dd3d89-9cda-4927-a251-971e8988944d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115317773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1115317773 |
Directory | /workspace/149.rv_timer_random/latest |
Test location | /workspace/coverage/default/29.rv_timer_stress_all.1783224625 |
Short name | T335 |
Test name | |
Test status | |
Simulation time | 2663552876547 ps |
CPU time | 1734.32 seconds |
Started | Aug 08 05:56:16 PM PDT 24 |
Finished | Aug 08 06:25:10 PM PDT 24 |
Peak memory | 191712 kb |
Host | smart-adff4e49-8fdd-46df-b86b-699571c4b170 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783224625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all .1783224625 |
Directory | /workspace/29.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.140605347 |
Short name | T167 |
Test name | |
Test status | |
Simulation time | 304912838944 ps |
CPU time | 161.53 seconds |
Started | Aug 08 05:55:40 PM PDT 24 |
Finished | Aug 08 05:58:22 PM PDT 24 |
Peak memory | 183504 kb |
Host | smart-0d3719ed-5568-43a9-a3db-4f97c548b7bd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140605347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6 .rv_timer_cfg_update_on_fly.140605347 |
Directory | /workspace/6.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/73.rv_timer_random.110877508 |
Short name | T298 |
Test name | |
Test status | |
Simulation time | 457826382283 ps |
CPU time | 801.18 seconds |
Started | Aug 08 05:56:54 PM PDT 24 |
Finished | Aug 08 06:10:15 PM PDT 24 |
Peak memory | 191712 kb |
Host | smart-d4b12ad7-d748-404c-8b9a-d02df308962a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110877508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.110877508 |
Directory | /workspace/73.rv_timer_random/latest |
Test location | /workspace/coverage/default/91.rv_timer_random.2738866713 |
Short name | T196 |
Test name | |
Test status | |
Simulation time | 131788720975 ps |
CPU time | 1094.12 seconds |
Started | Aug 08 05:57:02 PM PDT 24 |
Finished | Aug 08 06:15:17 PM PDT 24 |
Peak memory | 191644 kb |
Host | smart-a657a154-d03f-4d96-aa11-d18f93ad5bad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738866713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2738866713 |
Directory | /workspace/91.rv_timer_random/latest |
Test location | /workspace/coverage/default/14.rv_timer_random.666242147 |
Short name | T116 |
Test name | |
Test status | |
Simulation time | 218067723812 ps |
CPU time | 219.03 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 05:59:25 PM PDT 24 |
Peak memory | 191584 kb |
Host | smart-f0bd2ce6-8ede-4f15-9fc6-2100b1b919b6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666242147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.666242147 |
Directory | /workspace/14.rv_timer_random/latest |
Test location | /workspace/coverage/default/143.rv_timer_random.1998832221 |
Short name | T278 |
Test name | |
Test status | |
Simulation time | 291716696027 ps |
CPU time | 360.23 seconds |
Started | Aug 08 05:57:41 PM PDT 24 |
Finished | Aug 08 06:03:42 PM PDT 24 |
Peak memory | 191564 kb |
Host | smart-aa5f6591-2cec-4d90-b37a-717a2b1e9406 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998832221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1998832221 |
Directory | /workspace/143.rv_timer_random/latest |
Test location | /workspace/coverage/default/185.rv_timer_random.333288324 |
Short name | T285 |
Test name | |
Test status | |
Simulation time | 612305486388 ps |
CPU time | 760.27 seconds |
Started | Aug 08 05:58:11 PM PDT 24 |
Finished | Aug 08 06:10:51 PM PDT 24 |
Peak memory | 191684 kb |
Host | smart-ac4c85fe-4a52-4fe3-a807-2b087c530bee |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333288324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.333288324 |
Directory | /workspace/185.rv_timer_random/latest |
Test location | /workspace/coverage/default/191.rv_timer_random.51374340 |
Short name | T21 |
Test name | |
Test status | |
Simulation time | 98638186244 ps |
CPU time | 782.07 seconds |
Started | Aug 08 05:58:14 PM PDT 24 |
Finished | Aug 08 06:11:16 PM PDT 24 |
Peak memory | 191652 kb |
Host | smart-76a62383-40e2-45a9-9732-f6031e8d7f22 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51374340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.51374340 |
Directory | /workspace/191.rv_timer_random/latest |
Test location | /workspace/coverage/default/27.rv_timer_random.636805422 |
Short name | T149 |
Test name | |
Test status | |
Simulation time | 666643232385 ps |
CPU time | 766.39 seconds |
Started | Aug 08 05:56:03 PM PDT 24 |
Finished | Aug 08 06:08:49 PM PDT 24 |
Peak memory | 191532 kb |
Host | smart-de56c8b1-cc7f-4550-82a1-b4b16ddfe77d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636805422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.636805422 |
Directory | /workspace/27.rv_timer_random/latest |
Test location | /workspace/coverage/default/37.rv_timer_random.2557043452 |
Short name | T219 |
Test name | |
Test status | |
Simulation time | 344895450776 ps |
CPU time | 189.64 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 05:59:25 PM PDT 24 |
Peak memory | 191592 kb |
Host | smart-84037290-3256-4a09-87fd-b3976e164109 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557043452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2557043452 |
Directory | /workspace/37.rv_timer_random/latest |
Test location | /workspace/coverage/default/49.rv_timer_random.2024825856 |
Short name | T107 |
Test name | |
Test status | |
Simulation time | 487909596030 ps |
CPU time | 2161.56 seconds |
Started | Aug 08 05:56:40 PM PDT 24 |
Finished | Aug 08 06:32:41 PM PDT 24 |
Peak memory | 191620 kb |
Host | smart-254471f1-1a98-45b8-b820-b3ff519ca036 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024825856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2024825856 |
Directory | /workspace/49.rv_timer_random/latest |
Test location | /workspace/coverage/default/55.rv_timer_random.553463532 |
Short name | T202 |
Test name | |
Test status | |
Simulation time | 1433938621955 ps |
CPU time | 570.29 seconds |
Started | Aug 08 05:56:45 PM PDT 24 |
Finished | Aug 08 06:06:16 PM PDT 24 |
Peak memory | 191652 kb |
Host | smart-342cba1f-6ad9-4e27-80da-9ea8c5eaa17a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553463532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.553463532 |
Directory | /workspace/55.rv_timer_random/latest |
Test location | /workspace/coverage/default/123.rv_timer_random.3508590672 |
Short name | T135 |
Test name | |
Test status | |
Simulation time | 511840020798 ps |
CPU time | 359.02 seconds |
Started | Aug 08 05:57:26 PM PDT 24 |
Finished | Aug 08 06:03:25 PM PDT 24 |
Peak memory | 191632 kb |
Host | smart-63f3fe7e-7112-40c7-9fd3-8dca14d721b0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508590672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3508590672 |
Directory | /workspace/123.rv_timer_random/latest |
Test location | /workspace/coverage/default/183.rv_timer_random.3494190747 |
Short name | T230 |
Test name | |
Test status | |
Simulation time | 93790137913 ps |
CPU time | 162.62 seconds |
Started | Aug 08 05:58:05 PM PDT 24 |
Finished | Aug 08 06:00:48 PM PDT 24 |
Peak memory | 183468 kb |
Host | smart-53d57749-2607-405f-b6e2-ea7aff5a94fd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494190747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3494190747 |
Directory | /workspace/183.rv_timer_random/latest |
Test location | /workspace/coverage/default/3.rv_timer_stress_all.3744524756 |
Short name | T331 |
Test name | |
Test status | |
Simulation time | 474668807000 ps |
CPU time | 1798.86 seconds |
Started | Aug 08 05:55:40 PM PDT 24 |
Finished | Aug 08 06:25:39 PM PDT 24 |
Peak memory | 195160 kb |
Host | smart-8cbff5d6-956c-4f7e-a466-4362c32a76a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744524756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all. 3744524756 |
Directory | /workspace/3.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/32.rv_timer_stress_all.3398734887 |
Short name | T197 |
Test name | |
Test status | |
Simulation time | 5283962205192 ps |
CPU time | 5593.9 seconds |
Started | Aug 08 05:56:13 PM PDT 24 |
Finished | Aug 08 07:29:28 PM PDT 24 |
Peak memory | 196704 kb |
Host | smart-f009b8d2-c8f5-407c-b16e-83ade3a668cc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398734887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all .3398734887 |
Directory | /workspace/32.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/34.rv_timer_random_reset.3283475602 |
Short name | T307 |
Test name | |
Test status | |
Simulation time | 104139314189 ps |
CPU time | 570 seconds |
Started | Aug 08 05:56:12 PM PDT 24 |
Finished | Aug 08 06:05:43 PM PDT 24 |
Peak memory | 191612 kb |
Host | smart-6e6eae99-44f1-43c4-8bb1-420010441229 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3283475602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3283475602 |
Directory | /workspace/34.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.4260137220 |
Short name | T50 |
Test name | |
Test status | |
Simulation time | 1587577054404 ps |
CPU time | 412.15 seconds |
Started | Aug 08 05:56:22 PM PDT 24 |
Finished | Aug 08 06:03:14 PM PDT 24 |
Peak memory | 183440 kb |
Host | smart-1c0d040b-1ec3-4943-8b07-02de81354680 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260137220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.4260137220 |
Directory | /workspace/40.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/41.rv_timer_random.3653982622 |
Short name | T109 |
Test name | |
Test status | |
Simulation time | 574866925698 ps |
CPU time | 270.82 seconds |
Started | Aug 08 05:56:23 PM PDT 24 |
Finished | Aug 08 06:00:54 PM PDT 24 |
Peak memory | 191652 kb |
Host | smart-da956f03-f28a-4150-8676-e92e75e205b5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653982622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3653982622 |
Directory | /workspace/41.rv_timer_random/latest |
Test location | /workspace/coverage/default/58.rv_timer_random.1209731163 |
Short name | T178 |
Test name | |
Test status | |
Simulation time | 216474414029 ps |
CPU time | 407.22 seconds |
Started | Aug 08 05:56:47 PM PDT 24 |
Finished | Aug 08 06:03:34 PM PDT 24 |
Peak memory | 191688 kb |
Host | smart-12f7b8ac-837f-4e9d-b185-5b7c6ed13baa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209731163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1209731163 |
Directory | /workspace/58.rv_timer_random/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2637236447 |
Short name | T82 |
Test name | |
Test status | |
Simulation time | 21319936 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:50:36 PM PDT 24 |
Finished | Aug 08 05:50:36 PM PDT 24 |
Peak memory | 182704 kb |
Host | smart-27b16cff-8484-4ce8-bb7f-cc2f14595245 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637236447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2637236447 |
Directory | /workspace/0.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3321331455 |
Short name | T70 |
Test name | |
Test status | |
Simulation time | 32288783 ps |
CPU time | 0.75 seconds |
Started | Aug 08 05:50:37 PM PDT 24 |
Finished | Aug 08 05:50:38 PM PDT 24 |
Peak memory | 193628 kb |
Host | smart-fd10b0ec-3c0d-4ad9-9290-916d1fee0e75 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321331455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti mer_same_csr_outstanding.3321331455 |
Directory | /workspace/0.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/default/103.rv_timer_random.1273917987 |
Short name | T294 |
Test name | |
Test status | |
Simulation time | 117343417050 ps |
CPU time | 43.47 seconds |
Started | Aug 08 05:57:16 PM PDT 24 |
Finished | Aug 08 05:57:59 PM PDT 24 |
Peak memory | 183496 kb |
Host | smart-8ba70877-99ac-43eb-87f6-8634a10e615f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273917987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1273917987 |
Directory | /workspace/103.rv_timer_random/latest |
Test location | /workspace/coverage/default/115.rv_timer_random.2816363278 |
Short name | T65 |
Test name | |
Test status | |
Simulation time | 156860487410 ps |
CPU time | 140.03 seconds |
Started | Aug 08 05:57:25 PM PDT 24 |
Finished | Aug 08 05:59:46 PM PDT 24 |
Peak memory | 191692 kb |
Host | smart-9c5685f4-b817-4fe6-8568-908d42324d5f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816363278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2816363278 |
Directory | /workspace/115.rv_timer_random/latest |
Test location | /workspace/coverage/default/122.rv_timer_random.1359872160 |
Short name | T8 |
Test name | |
Test status | |
Simulation time | 229558614918 ps |
CPU time | 178.16 seconds |
Started | Aug 08 05:57:27 PM PDT 24 |
Finished | Aug 08 06:00:25 PM PDT 24 |
Peak memory | 191612 kb |
Host | smart-f62b73a1-8088-4b88-8a0b-80eb991f33f6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359872160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1359872160 |
Directory | /workspace/122.rv_timer_random/latest |
Test location | /workspace/coverage/default/124.rv_timer_random.2193075890 |
Short name | T240 |
Test name | |
Test status | |
Simulation time | 32209377792 ps |
CPU time | 52.48 seconds |
Started | Aug 08 05:57:26 PM PDT 24 |
Finished | Aug 08 05:58:19 PM PDT 24 |
Peak memory | 191624 kb |
Host | smart-ef27b8e8-96ec-4edf-a8c5-bf2f99011fc1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193075890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2193075890 |
Directory | /workspace/124.rv_timer_random/latest |
Test location | /workspace/coverage/default/126.rv_timer_random.3306754275 |
Short name | T142 |
Test name | |
Test status | |
Simulation time | 253462027176 ps |
CPU time | 303.18 seconds |
Started | Aug 08 05:57:33 PM PDT 24 |
Finished | Aug 08 06:02:36 PM PDT 24 |
Peak memory | 191668 kb |
Host | smart-e188987c-6701-481c-bf61-6a1484827aa3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306754275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3306754275 |
Directory | /workspace/126.rv_timer_random/latest |
Test location | /workspace/coverage/default/139.rv_timer_random.2327834192 |
Short name | T247 |
Test name | |
Test status | |
Simulation time | 938328288561 ps |
CPU time | 309.99 seconds |
Started | Aug 08 05:57:41 PM PDT 24 |
Finished | Aug 08 06:02:51 PM PDT 24 |
Peak memory | 191624 kb |
Host | smart-8fe4137a-e017-4571-82cb-3fc2e9da7650 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327834192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2327834192 |
Directory | /workspace/139.rv_timer_random/latest |
Test location | /workspace/coverage/default/15.rv_timer_random.3662886061 |
Short name | T291 |
Test name | |
Test status | |
Simulation time | 99306959391 ps |
CPU time | 828.29 seconds |
Started | Aug 08 05:55:47 PM PDT 24 |
Finished | Aug 08 06:09:36 PM PDT 24 |
Peak memory | 191560 kb |
Host | smart-f3f4496d-81aa-4307-a555-e12de93f26d9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662886061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3662886061 |
Directory | /workspace/15.rv_timer_random/latest |
Test location | /workspace/coverage/default/165.rv_timer_random.1474515774 |
Short name | T153 |
Test name | |
Test status | |
Simulation time | 50852949463 ps |
CPU time | 95.69 seconds |
Started | Aug 08 05:57:57 PM PDT 24 |
Finished | Aug 08 05:59:32 PM PDT 24 |
Peak memory | 191684 kb |
Host | smart-b95fcbcb-7ff7-409c-bc69-988ca3c5d77d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474515774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1474515774 |
Directory | /workspace/165.rv_timer_random/latest |
Test location | /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3430836036 |
Short name | T309 |
Test name | |
Test status | |
Simulation time | 455727906539 ps |
CPU time | 144.52 seconds |
Started | Aug 08 05:56:16 PM PDT 24 |
Finished | Aug 08 05:58:40 PM PDT 24 |
Peak memory | 183424 kb |
Host | smart-d7097e83-5893-495a-94e6-c3ac1f83a5d5 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430836036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.3430836036 |
Directory | /workspace/37.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/37.rv_timer_stress_all.2977436315 |
Short name | T330 |
Test name | |
Test status | |
Simulation time | 452754771954 ps |
CPU time | 763.63 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 06:08:59 PM PDT 24 |
Peak memory | 191696 kb |
Host | smart-4eb21342-f974-4f64-bc76-1ce461dfe530 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977436315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all .2977436315 |
Directory | /workspace/37.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_timer_stress_all.554762582 |
Short name | T239 |
Test name | |
Test status | |
Simulation time | 201028424053 ps |
CPU time | 678.7 seconds |
Started | Aug 08 05:55:38 PM PDT 24 |
Finished | Aug 08 06:06:57 PM PDT 24 |
Peak memory | 191708 kb |
Host | smart-b51b8190-1d35-4161-9e6a-2d193d347d9f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554762582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.554762582 |
Directory | /workspace/4.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_timer_random.1953493402 |
Short name | T160 |
Test name | |
Test status | |
Simulation time | 120191073925 ps |
CPU time | 203.65 seconds |
Started | Aug 08 05:55:42 PM PDT 24 |
Finished | Aug 08 05:59:05 PM PDT 24 |
Peak memory | 191560 kb |
Host | smart-49f54492-b481-4e3a-9329-ca2af4b89bf4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953493402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1953493402 |
Directory | /workspace/5.rv_timer_random/latest |
Test location | /workspace/coverage/default/8.rv_timer_random.4065328644 |
Short name | T210 |
Test name | |
Test status | |
Simulation time | 95928057892 ps |
CPU time | 467.38 seconds |
Started | Aug 08 05:55:44 PM PDT 24 |
Finished | Aug 08 06:03:31 PM PDT 24 |
Peak memory | 191544 kb |
Host | smart-82d36722-6678-41cf-8f81-6bfced667eeb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065328644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.4065328644 |
Directory | /workspace/8.rv_timer_random/latest |
Test location | /workspace/coverage/default/8.rv_timer_stress_all.1891847101 |
Short name | T222 |
Test name | |
Test status | |
Simulation time | 190924507839 ps |
CPU time | 321.27 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 06:01:08 PM PDT 24 |
Peak memory | 191684 kb |
Host | smart-1d351a15-7ef2-4079-bbd0-7f1e52fda83b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891847101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all. 1891847101 |
Directory | /workspace/8.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/87.rv_timer_random.882319836 |
Short name | T229 |
Test name | |
Test status | |
Simulation time | 180172093843 ps |
CPU time | 546.82 seconds |
Started | Aug 08 05:57:02 PM PDT 24 |
Finished | Aug 08 06:06:09 PM PDT 24 |
Peak memory | 191600 kb |
Host | smart-c2042579-6234-45d9-8b3a-22c913bc07e3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882319836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.882319836 |
Directory | /workspace/87.rv_timer_random/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1710298264 |
Short name | T103 |
Test name | |
Test status | |
Simulation time | 166414049 ps |
CPU time | 1.41 seconds |
Started | Aug 08 05:51:26 PM PDT 24 |
Finished | Aug 08 05:51:28 PM PDT 24 |
Peak memory | 195576 kb |
Host | smart-eda502cd-0074-42ea-8f7f-c9e9797aa2e1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710298264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i ntg_err.1710298264 |
Directory | /workspace/10.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1002828231 |
Short name | T102 |
Test name | |
Test status | |
Simulation time | 137197607 ps |
CPU time | 1.09 seconds |
Started | Aug 08 05:51:30 PM PDT 24 |
Finished | Aug 08 05:51:31 PM PDT 24 |
Peak memory | 183328 kb |
Host | smart-a0993793-3b2a-4089-a78c-71f43cd17b4e |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002828231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i ntg_err.1002828231 |
Directory | /workspace/11.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_timer_random_reset.4280672512 |
Short name | T351 |
Test name | |
Test status | |
Simulation time | 101014668515 ps |
CPU time | 58.97 seconds |
Started | Aug 08 05:55:35 PM PDT 24 |
Finished | Aug 08 05:56:35 PM PDT 24 |
Peak memory | 193848 kb |
Host | smart-60cc197d-049e-4c83-a317-1ce20d3f66e6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4280672512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.4280672512 |
Directory | /workspace/0.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/1.rv_timer_random_reset.422496764 |
Short name | T402 |
Test name | |
Test status | |
Simulation time | 8699748411 ps |
CPU time | 6.45 seconds |
Started | Aug 08 05:55:39 PM PDT 24 |
Finished | Aug 08 05:55:46 PM PDT 24 |
Peak memory | 195184 kb |
Host | smart-dd83610d-ba8e-456c-8512-d15a24127b20 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=422496764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.422496764 |
Directory | /workspace/1.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/10.rv_timer_random.1908580600 |
Short name | T405 |
Test name | |
Test status | |
Simulation time | 178849474673 ps |
CPU time | 121.45 seconds |
Started | Aug 08 05:55:44 PM PDT 24 |
Finished | Aug 08 05:57:46 PM PDT 24 |
Peak memory | 183448 kb |
Host | smart-f068b3a0-2c18-4aeb-a988-cb935dc84d71 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908580600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1908580600 |
Directory | /workspace/10.rv_timer_random/latest |
Test location | /workspace/coverage/default/102.rv_timer_random.3391964893 |
Short name | T131 |
Test name | |
Test status | |
Simulation time | 27875566510 ps |
CPU time | 17.61 seconds |
Started | Aug 08 05:57:08 PM PDT 24 |
Finished | Aug 08 05:57:26 PM PDT 24 |
Peak memory | 183244 kb |
Host | smart-aeffbf5f-d435-4794-85aa-97cf46aba031 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391964893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3391964893 |
Directory | /workspace/102.rv_timer_random/latest |
Test location | /workspace/coverage/default/104.rv_timer_random.722812151 |
Short name | T334 |
Test name | |
Test status | |
Simulation time | 514980388084 ps |
CPU time | 291.9 seconds |
Started | Aug 08 05:57:18 PM PDT 24 |
Finished | Aug 08 06:02:10 PM PDT 24 |
Peak memory | 191628 kb |
Host | smart-94396154-0121-4454-ab02-1275ce59e113 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722812151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.722812151 |
Directory | /workspace/104.rv_timer_random/latest |
Test location | /workspace/coverage/default/110.rv_timer_random.1079136987 |
Short name | T282 |
Test name | |
Test status | |
Simulation time | 172874716879 ps |
CPU time | 325.63 seconds |
Started | Aug 08 05:57:17 PM PDT 24 |
Finished | Aug 08 06:02:43 PM PDT 24 |
Peak memory | 191632 kb |
Host | smart-a330ef94-2246-4753-9ef5-dc0808213c5d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079136987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1079136987 |
Directory | /workspace/110.rv_timer_random/latest |
Test location | /workspace/coverage/default/12.rv_timer_random.1047706889 |
Short name | T132 |
Test name | |
Test status | |
Simulation time | 898812217379 ps |
CPU time | 1424.01 seconds |
Started | Aug 08 05:55:45 PM PDT 24 |
Finished | Aug 08 06:19:30 PM PDT 24 |
Peak memory | 191860 kb |
Host | smart-04157bc1-8c63-4dd9-acf1-a05964c81056 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047706889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1047706889 |
Directory | /workspace/12.rv_timer_random/latest |
Test location | /workspace/coverage/default/125.rv_timer_random.2177631882 |
Short name | T325 |
Test name | |
Test status | |
Simulation time | 59208203590 ps |
CPU time | 291.37 seconds |
Started | Aug 08 05:57:25 PM PDT 24 |
Finished | Aug 08 06:02:17 PM PDT 24 |
Peak memory | 191708 kb |
Host | smart-6edb9434-ea8f-4363-b106-bc01639faa8e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177631882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2177631882 |
Directory | /workspace/125.rv_timer_random/latest |
Test location | /workspace/coverage/default/127.rv_timer_random.2718124788 |
Short name | T203 |
Test name | |
Test status | |
Simulation time | 171927633780 ps |
CPU time | 2098.74 seconds |
Started | Aug 08 05:57:33 PM PDT 24 |
Finished | Aug 08 06:32:32 PM PDT 24 |
Peak memory | 191704 kb |
Host | smart-33eae5df-d412-44da-87de-558a4fe91762 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718124788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2718124788 |
Directory | /workspace/127.rv_timer_random/latest |
Test location | /workspace/coverage/default/13.rv_timer_random.3752208294 |
Short name | T97 |
Test name | |
Test status | |
Simulation time | 613118077718 ps |
CPU time | 376.1 seconds |
Started | Aug 08 05:55:50 PM PDT 24 |
Finished | Aug 08 06:02:06 PM PDT 24 |
Peak memory | 191608 kb |
Host | smart-7f62da67-c30b-4b04-b073-af05c42915ef |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752208294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3752208294 |
Directory | /workspace/13.rv_timer_random/latest |
Test location | /workspace/coverage/default/135.rv_timer_random.3495883843 |
Short name | T280 |
Test name | |
Test status | |
Simulation time | 663312048381 ps |
CPU time | 185.39 seconds |
Started | Aug 08 05:57:35 PM PDT 24 |
Finished | Aug 08 06:00:40 PM PDT 24 |
Peak memory | 191636 kb |
Host | smart-8b57dd8b-d12f-47ff-a0fc-57f6926ab643 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495883843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3495883843 |
Directory | /workspace/135.rv_timer_random/latest |
Test location | /workspace/coverage/default/142.rv_timer_random.3037651843 |
Short name | T275 |
Test name | |
Test status | |
Simulation time | 197976519641 ps |
CPU time | 2199.6 seconds |
Started | Aug 08 05:57:41 PM PDT 24 |
Finished | Aug 08 06:34:21 PM PDT 24 |
Peak memory | 191732 kb |
Host | smart-07350e40-270f-41bc-9472-8bc73ca37550 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037651843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3037651843 |
Directory | /workspace/142.rv_timer_random/latest |
Test location | /workspace/coverage/default/151.rv_timer_random.3946145594 |
Short name | T324 |
Test name | |
Test status | |
Simulation time | 1463033501496 ps |
CPU time | 648.42 seconds |
Started | Aug 08 05:57:53 PM PDT 24 |
Finished | Aug 08 06:08:41 PM PDT 24 |
Peak memory | 191596 kb |
Host | smart-62da3b3d-1c45-4378-88ef-ca8dcf952cff |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946145594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3946145594 |
Directory | /workspace/151.rv_timer_random/latest |
Test location | /workspace/coverage/default/169.rv_timer_random.985130618 |
Short name | T327 |
Test name | |
Test status | |
Simulation time | 189801078402 ps |
CPU time | 271.77 seconds |
Started | Aug 08 05:57:57 PM PDT 24 |
Finished | Aug 08 06:02:29 PM PDT 24 |
Peak memory | 191700 kb |
Host | smart-2b29fa07-a604-4591-997e-665a36a45f72 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985130618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.985130618 |
Directory | /workspace/169.rv_timer_random/latest |
Test location | /workspace/coverage/default/179.rv_timer_random.779091450 |
Short name | T332 |
Test name | |
Test status | |
Simulation time | 173521321478 ps |
CPU time | 1065.98 seconds |
Started | Aug 08 05:58:04 PM PDT 24 |
Finished | Aug 08 06:15:50 PM PDT 24 |
Peak memory | 191536 kb |
Host | smart-b0c753a3-4212-49ae-9771-51a033b98de1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779091450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.779091450 |
Directory | /workspace/179.rv_timer_random/latest |
Test location | /workspace/coverage/default/19.rv_timer_random.152282272 |
Short name | T235 |
Test name | |
Test status | |
Simulation time | 739301578112 ps |
CPU time | 252.46 seconds |
Started | Aug 08 05:55:55 PM PDT 24 |
Finished | Aug 08 06:00:07 PM PDT 24 |
Peak memory | 191644 kb |
Host | smart-a5e191ce-dfb0-417c-bf17-0816daf86780 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152282272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.152282272 |
Directory | /workspace/19.rv_timer_random/latest |
Test location | /workspace/coverage/default/192.rv_timer_random.2685115743 |
Short name | T227 |
Test name | |
Test status | |
Simulation time | 118440969008 ps |
CPU time | 176.92 seconds |
Started | Aug 08 05:58:12 PM PDT 24 |
Finished | Aug 08 06:01:09 PM PDT 24 |
Peak memory | 191656 kb |
Host | smart-a2f3ad5c-e9f6-433f-83f4-728bf161b168 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685115743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2685115743 |
Directory | /workspace/192.rv_timer_random/latest |
Test location | /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.4266154366 |
Short name | T271 |
Test name | |
Test status | |
Simulation time | 462208240811 ps |
CPU time | 366.23 seconds |
Started | Aug 08 05:55:44 PM PDT 24 |
Finished | Aug 08 06:01:51 PM PDT 24 |
Peak memory | 183392 kb |
Host | smart-dc7ca695-96fd-49c3-a3d4-624b163cf46a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266154366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.4266154366 |
Directory | /workspace/2.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/23.rv_timer_random.461244501 |
Short name | T199 |
Test name | |
Test status | |
Simulation time | 169318602675 ps |
CPU time | 333.47 seconds |
Started | Aug 08 05:56:05 PM PDT 24 |
Finished | Aug 08 06:01:38 PM PDT 24 |
Peak memory | 191592 kb |
Host | smart-dce9f65e-a0d6-4c59-aad6-3920c12e1b0b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461244501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.461244501 |
Directory | /workspace/23.rv_timer_random/latest |
Test location | /workspace/coverage/default/4.rv_timer_random_reset.799296826 |
Short name | T171 |
Test name | |
Test status | |
Simulation time | 263291316564 ps |
CPU time | 118.27 seconds |
Started | Aug 08 05:55:42 PM PDT 24 |
Finished | Aug 08 05:57:40 PM PDT 24 |
Peak memory | 191572 kb |
Host | smart-32eebb1d-8937-439f-bd42-29c2d25a0ac3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=799296826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.799296826 |
Directory | /workspace/4.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/46.rv_timer_stress_all.3335357702 |
Short name | T92 |
Test name | |
Test status | |
Simulation time | 2182990068489 ps |
CPU time | 748.26 seconds |
Started | Aug 08 05:56:34 PM PDT 24 |
Finished | Aug 08 06:09:02 PM PDT 24 |
Peak memory | 194736 kb |
Host | smart-5ca47870-d4b1-4c1f-b4d6-db74de59357c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335357702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all .3335357702 |
Directory | /workspace/46.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_timer_random.2581854581 |
Short name | T201 |
Test name | |
Test status | |
Simulation time | 458795811962 ps |
CPU time | 1040.43 seconds |
Started | Aug 08 05:56:30 PM PDT 24 |
Finished | Aug 08 06:13:51 PM PDT 24 |
Peak memory | 191660 kb |
Host | smart-83126534-996a-4009-9bab-261b4215a0f5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581854581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2581854581 |
Directory | /workspace/48.rv_timer_random/latest |
Test location | /workspace/coverage/default/53.rv_timer_random.2582432791 |
Short name | T26 |
Test name | |
Test status | |
Simulation time | 51664871388 ps |
CPU time | 85.07 seconds |
Started | Aug 08 05:56:48 PM PDT 24 |
Finished | Aug 08 05:58:13 PM PDT 24 |
Peak memory | 183428 kb |
Host | smart-c2fee954-7e0f-42d8-804a-60595296e8a0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582432791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2582432791 |
Directory | /workspace/53.rv_timer_random/latest |
Test location | /workspace/coverage/default/78.rv_timer_random.2733339970 |
Short name | T320 |
Test name | |
Test status | |
Simulation time | 1394029409862 ps |
CPU time | 758.7 seconds |
Started | Aug 08 05:56:55 PM PDT 24 |
Finished | Aug 08 06:09:34 PM PDT 24 |
Peak memory | 191600 kb |
Host | smart-5eeeb77a-9236-444f-a352-092f3115be5d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733339970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2733339970 |
Directory | /workspace/78.rv_timer_random/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2758930057 |
Short name | T78 |
Test name | |
Test status | |
Simulation time | 62948628 ps |
CPU time | 0.69 seconds |
Started | Aug 08 05:50:37 PM PDT 24 |
Finished | Aug 08 05:50:38 PM PDT 24 |
Peak memory | 182940 kb |
Host | smart-9e08252a-ca63-49ee-81a7-9c7122752059 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758930057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia sing.2758930057 |
Directory | /workspace/0.rv_timer_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2347091047 |
Short name | T548 |
Test name | |
Test status | |
Simulation time | 351362552 ps |
CPU time | 3.06 seconds |
Started | Aug 08 05:50:39 PM PDT 24 |
Finished | Aug 08 05:50:42 PM PDT 24 |
Peak memory | 183268 kb |
Host | smart-4d98074d-bd89-4e77-8f06-3b426724d9ae |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347091047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_ bash.2347091047 |
Directory | /workspace/0.rv_timer_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.506088917 |
Short name | T498 |
Test name | |
Test status | |
Simulation time | 16258471 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:50:37 PM PDT 24 |
Finished | Aug 08 05:50:38 PM PDT 24 |
Peak memory | 182468 kb |
Host | smart-3278a48a-b65a-44a9-a5cf-24ab9bc2b9b6 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506088917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re set.506088917 |
Directory | /workspace/0.rv_timer_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2025834417 |
Short name | T462 |
Test name | |
Test status | |
Simulation time | 49954889 ps |
CPU time | 0.67 seconds |
Started | Aug 08 05:50:39 PM PDT 24 |
Finished | Aug 08 05:50:40 PM PDT 24 |
Peak memory | 194920 kb |
Host | smart-a2524865-56e0-412a-b922-00e666189843 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025834417 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2025834417 |
Directory | /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1025970324 |
Short name | T454 |
Test name | |
Test status | |
Simulation time | 51799157 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:50:38 PM PDT 24 |
Finished | Aug 08 05:50:39 PM PDT 24 |
Peak memory | 182728 kb |
Host | smart-844c4f06-fa96-4eb8-b8da-e751777aadf4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025970324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1025970324 |
Directory | /workspace/0.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2613664309 |
Short name | T470 |
Test name | |
Test status | |
Simulation time | 108572597 ps |
CPU time | 1.47 seconds |
Started | Aug 08 05:50:38 PM PDT 24 |
Finished | Aug 08 05:50:39 PM PDT 24 |
Peak memory | 197864 kb |
Host | smart-61b0e85a-9dae-499d-b9da-b54ea7d0cbe6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613664309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2613664309 |
Directory | /workspace/0.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3232933509 |
Short name | T564 |
Test name | |
Test status | |
Simulation time | 163091804 ps |
CPU time | 0.77 seconds |
Started | Aug 08 05:50:37 PM PDT 24 |
Finished | Aug 08 05:50:37 PM PDT 24 |
Peak memory | 193980 kb |
Host | smart-1a0fe8d9-dfcb-4935-afcd-21b7cd0d8367 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232933509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in tg_err.3232933509 |
Directory | /workspace/0.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1509035066 |
Short name | T83 |
Test name | |
Test status | |
Simulation time | 17832760 ps |
CPU time | 0.81 seconds |
Started | Aug 08 05:50:47 PM PDT 24 |
Finished | Aug 08 05:50:48 PM PDT 24 |
Peak memory | 191140 kb |
Host | smart-413726c5-4881-4eb1-958c-2c8391cefc1d |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509035066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia sing.1509035066 |
Directory | /workspace/1.rv_timer_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.433929731 |
Short name | T484 |
Test name | |
Test status | |
Simulation time | 574873321 ps |
CPU time | 1.62 seconds |
Started | Aug 08 05:50:46 PM PDT 24 |
Finished | Aug 08 05:50:48 PM PDT 24 |
Peak memory | 191372 kb |
Host | smart-1f30c6e8-aabd-4ab8-9ebd-bc91661860a5 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433929731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b ash.433929731 |
Directory | /workspace/1.rv_timer_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.5906791 |
Short name | T575 |
Test name | |
Test status | |
Simulation time | 141036172 ps |
CPU time | 0.56 seconds |
Started | Aug 08 05:50:47 PM PDT 24 |
Finished | Aug 08 05:50:48 PM PDT 24 |
Peak memory | 182896 kb |
Host | smart-8606d7ba-db85-4a24-9d93-dcce00e56aba |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5906791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_rese t.5906791 |
Directory | /workspace/1.rv_timer_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2258467035 |
Short name | T532 |
Test name | |
Test status | |
Simulation time | 88195917 ps |
CPU time | 1.26 seconds |
Started | Aug 08 05:50:48 PM PDT 24 |
Finished | Aug 08 05:50:49 PM PDT 24 |
Peak memory | 197748 kb |
Host | smart-68deca3b-348a-479e-a450-4efa981060a4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258467035 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2258467035 |
Directory | /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.233625237 |
Short name | T513 |
Test name | |
Test status | |
Simulation time | 26570704 ps |
CPU time | 0.56 seconds |
Started | Aug 08 05:50:47 PM PDT 24 |
Finished | Aug 08 05:50:47 PM PDT 24 |
Peak memory | 182628 kb |
Host | smart-4fa31f6d-5d63-48ed-be70-7fa69e6924bd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233625237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.233625237 |
Directory | /workspace/1.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2878627926 |
Short name | T576 |
Test name | |
Test status | |
Simulation time | 23350985 ps |
CPU time | 0.54 seconds |
Started | Aug 08 05:50:47 PM PDT 24 |
Finished | Aug 08 05:50:48 PM PDT 24 |
Peak memory | 182788 kb |
Host | smart-04dd4f6e-d152-4eb9-816e-e5e7b5d0127f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878627926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2878627926 |
Directory | /workspace/1.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3290037111 |
Short name | T490 |
Test name | |
Test status | |
Simulation time | 56482725 ps |
CPU time | 0.73 seconds |
Started | Aug 08 05:50:47 PM PDT 24 |
Finished | Aug 08 05:50:47 PM PDT 24 |
Peak memory | 191908 kb |
Host | smart-e7d55f64-4251-4d60-b648-326b92dd7a4c |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290037111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti mer_same_csr_outstanding.3290037111 |
Directory | /workspace/1.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3595376682 |
Short name | T531 |
Test name | |
Test status | |
Simulation time | 533867331 ps |
CPU time | 1.92 seconds |
Started | Aug 08 05:50:47 PM PDT 24 |
Finished | Aug 08 05:50:49 PM PDT 24 |
Peak memory | 197704 kb |
Host | smart-7eae3893-6aba-47e1-b5e3-d7ed8a822601 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595376682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3595376682 |
Directory | /workspace/1.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1844551012 |
Short name | T29 |
Test name | |
Test status | |
Simulation time | 95571240 ps |
CPU time | 0.81 seconds |
Started | Aug 08 05:50:47 PM PDT 24 |
Finished | Aug 08 05:50:47 PM PDT 24 |
Peak memory | 193844 kb |
Host | smart-944b9697-5363-47aa-b7d7-4487cf13d634 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844551012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in tg_err.1844551012 |
Directory | /workspace/1.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3319696775 |
Short name | T494 |
Test name | |
Test status | |
Simulation time | 28882428 ps |
CPU time | 0.77 seconds |
Started | Aug 08 05:51:25 PM PDT 24 |
Finished | Aug 08 05:51:26 PM PDT 24 |
Peak memory | 195756 kb |
Host | smart-e950edc2-08c9-42de-98ad-c4b5c9188fd9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319696775 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3319696775 |
Directory | /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1033348630 |
Short name | T79 |
Test name | |
Test status | |
Simulation time | 16192044 ps |
CPU time | 0.64 seconds |
Started | Aug 08 05:51:26 PM PDT 24 |
Finished | Aug 08 05:51:27 PM PDT 24 |
Peak memory | 182984 kb |
Host | smart-a24fe826-9c7b-4682-aa59-7e7d5ea44e2f |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033348630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1033348630 |
Directory | /workspace/10.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3413189066 |
Short name | T521 |
Test name | |
Test status | |
Simulation time | 38740069 ps |
CPU time | 0.54 seconds |
Started | Aug 08 05:51:36 PM PDT 24 |
Finished | Aug 08 05:51:36 PM PDT 24 |
Peak memory | 182632 kb |
Host | smart-38808815-1b0e-48e0-b207-3dfc7f2d0e00 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413189066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3413189066 |
Directory | /workspace/10.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1729373019 |
Short name | T72 |
Test name | |
Test status | |
Simulation time | 41353552 ps |
CPU time | 0.69 seconds |
Started | Aug 08 05:51:28 PM PDT 24 |
Finished | Aug 08 05:51:28 PM PDT 24 |
Peak memory | 192204 kb |
Host | smart-541748aa-2589-4c76-b711-0c75ab1a48b3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729373019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t imer_same_csr_outstanding.1729373019 |
Directory | /workspace/10.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1052245490 |
Short name | T523 |
Test name | |
Test status | |
Simulation time | 391339198 ps |
CPU time | 1.34 seconds |
Started | Aug 08 05:51:26 PM PDT 24 |
Finished | Aug 08 05:51:27 PM PDT 24 |
Peak memory | 197672 kb |
Host | smart-028f382a-fc3d-482f-9b9a-4987d3be4cd6 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052245490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1052245490 |
Directory | /workspace/10.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1360395787 |
Short name | T472 |
Test name | |
Test status | |
Simulation time | 16087045 ps |
CPU time | 0.61 seconds |
Started | Aug 08 05:51:26 PM PDT 24 |
Finished | Aug 08 05:51:27 PM PDT 24 |
Peak memory | 194064 kb |
Host | smart-250ee8c0-c37c-493a-aead-e2cd0c51dc12 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360395787 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1360395787 |
Directory | /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2100619488 |
Short name | T81 |
Test name | |
Test status | |
Simulation time | 11378531 ps |
CPU time | 0.57 seconds |
Started | Aug 08 05:51:26 PM PDT 24 |
Finished | Aug 08 05:51:26 PM PDT 24 |
Peak memory | 183016 kb |
Host | smart-396299ef-255b-404b-ad98-9f8b885655da |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100619488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2100619488 |
Directory | /workspace/11.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1328273403 |
Short name | T569 |
Test name | |
Test status | |
Simulation time | 28365333 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:27 PM PDT 24 |
Finished | Aug 08 05:51:27 PM PDT 24 |
Peak memory | 182188 kb |
Host | smart-5220d021-562c-47c2-86ce-6a9f4decdcb0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328273403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1328273403 |
Directory | /workspace/11.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2594133805 |
Short name | T542 |
Test name | |
Test status | |
Simulation time | 62470140 ps |
CPU time | 0.73 seconds |
Started | Aug 08 05:51:26 PM PDT 24 |
Finished | Aug 08 05:51:26 PM PDT 24 |
Peak memory | 193404 kb |
Host | smart-b7e1c2ea-4a9e-4d72-b79d-05823b45eea8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594133805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t imer_same_csr_outstanding.2594133805 |
Directory | /workspace/11.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.567410096 |
Short name | T469 |
Test name | |
Test status | |
Simulation time | 81518923 ps |
CPU time | 1.86 seconds |
Started | Aug 08 05:51:30 PM PDT 24 |
Finished | Aug 08 05:51:32 PM PDT 24 |
Peak memory | 197604 kb |
Host | smart-02dd5962-7cf6-40fe-b8b4-5c9155fc12fa |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567410096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.567410096 |
Directory | /workspace/11.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.539520778 |
Short name | T555 |
Test name | |
Test status | |
Simulation time | 54938265 ps |
CPU time | 0.61 seconds |
Started | Aug 08 05:53:04 PM PDT 24 |
Finished | Aug 08 05:53:05 PM PDT 24 |
Peak memory | 192772 kb |
Host | smart-1c58a6a5-dbd9-4d62-a6e6-f024d19745c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539520778 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.539520778 |
Directory | /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2757118848 |
Short name | T85 |
Test name | |
Test status | |
Simulation time | 48414601 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:53:03 PM PDT 24 |
Finished | Aug 08 05:53:04 PM PDT 24 |
Peak memory | 182716 kb |
Host | smart-9a9e270d-2b76-4f5d-9a01-09d08d31cb23 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757118848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2757118848 |
Directory | /workspace/12.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.4033719206 |
Short name | T482 |
Test name | |
Test status | |
Simulation time | 83293540 ps |
CPU time | 0.52 seconds |
Started | Aug 08 05:51:35 PM PDT 24 |
Finished | Aug 08 05:51:36 PM PDT 24 |
Peak memory | 182228 kb |
Host | smart-6ba3b274-4e5b-4924-a025-5d23816e47a0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033719206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.4033719206 |
Directory | /workspace/12.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1553588497 |
Short name | T502 |
Test name | |
Test status | |
Simulation time | 61699236 ps |
CPU time | 0.71 seconds |
Started | Aug 08 05:51:38 PM PDT 24 |
Finished | Aug 08 05:51:39 PM PDT 24 |
Peak memory | 193472 kb |
Host | smart-5f40fe5d-ad39-4afc-a349-1d3383eab6bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553588497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t imer_same_csr_outstanding.1553588497 |
Directory | /workspace/12.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3621097237 |
Short name | T511 |
Test name | |
Test status | |
Simulation time | 993755201 ps |
CPU time | 2.2 seconds |
Started | Aug 08 05:51:37 PM PDT 24 |
Finished | Aug 08 05:51:40 PM PDT 24 |
Peak memory | 197712 kb |
Host | smart-11608317-d0f4-4fa1-8765-3de78fc42dcc |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621097237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3621097237 |
Directory | /workspace/12.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3066654946 |
Short name | T557 |
Test name | |
Test status | |
Simulation time | 64781800 ps |
CPU time | 0.59 seconds |
Started | Aug 08 05:51:38 PM PDT 24 |
Finished | Aug 08 05:51:39 PM PDT 24 |
Peak memory | 193152 kb |
Host | smart-fc5a7ce9-a685-4a10-80a2-0c2275177635 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066654946 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3066654946 |
Directory | /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1593023527 |
Short name | T57 |
Test name | |
Test status | |
Simulation time | 23923550 ps |
CPU time | 0.56 seconds |
Started | Aug 08 05:51:37 PM PDT 24 |
Finished | Aug 08 05:51:38 PM PDT 24 |
Peak memory | 182912 kb |
Host | smart-f4b1e8fa-e724-4cd1-ad8f-71b29bd9ed34 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593023527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1593023527 |
Directory | /workspace/13.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2062734186 |
Short name | T475 |
Test name | |
Test status | |
Simulation time | 26792651 ps |
CPU time | 0.56 seconds |
Started | Aug 08 05:51:37 PM PDT 24 |
Finished | Aug 08 05:51:37 PM PDT 24 |
Peak memory | 182816 kb |
Host | smart-8cef76ee-e652-4868-a2ac-2b77a9a8f07d |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062734186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2062734186 |
Directory | /workspace/13.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1952062406 |
Short name | T553 |
Test name | |
Test status | |
Simulation time | 34003879 ps |
CPU time | 0.75 seconds |
Started | Aug 08 05:51:34 PM PDT 24 |
Finished | Aug 08 05:51:35 PM PDT 24 |
Peak memory | 191820 kb |
Host | smart-d05b5ef0-4cf1-402e-92a3-3e1e91ca11a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952062406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t imer_same_csr_outstanding.1952062406 |
Directory | /workspace/13.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1860048000 |
Short name | T458 |
Test name | |
Test status | |
Simulation time | 47783288 ps |
CPU time | 2.31 seconds |
Started | Aug 08 05:51:37 PM PDT 24 |
Finished | Aug 08 05:51:40 PM PDT 24 |
Peak memory | 197744 kb |
Host | smart-e4d2a5bd-7f40-4b6f-abf6-9493132c55d5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860048000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1860048000 |
Directory | /workspace/13.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1319323896 |
Short name | T573 |
Test name | |
Test status | |
Simulation time | 46708810 ps |
CPU time | 0.83 seconds |
Started | Aug 08 05:51:37 PM PDT 24 |
Finished | Aug 08 05:51:38 PM PDT 24 |
Peak memory | 193480 kb |
Host | smart-de2ed7a7-1041-4951-a42b-6ae1edd81b44 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319323896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i ntg_err.1319323896 |
Directory | /workspace/13.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.657556322 |
Short name | T565 |
Test name | |
Test status | |
Simulation time | 26976957 ps |
CPU time | 0.96 seconds |
Started | Aug 08 05:51:38 PM PDT 24 |
Finished | Aug 08 05:51:39 PM PDT 24 |
Peak memory | 197528 kb |
Host | smart-0f8e0bc5-0108-4d73-a273-4c788980a8bc |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657556322 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.657556322 |
Directory | /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1054461581 |
Short name | T71 |
Test name | |
Test status | |
Simulation time | 61383317 ps |
CPU time | 0.58 seconds |
Started | Aug 08 05:51:37 PM PDT 24 |
Finished | Aug 08 05:51:38 PM PDT 24 |
Peak memory | 191456 kb |
Host | smart-c5f94e2a-f0b2-440a-a1b1-397a53073035 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054461581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1054461581 |
Directory | /workspace/14.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1413297611 |
Short name | T529 |
Test name | |
Test status | |
Simulation time | 38417909 ps |
CPU time | 0.52 seconds |
Started | Aug 08 05:51:37 PM PDT 24 |
Finished | Aug 08 05:51:38 PM PDT 24 |
Peak memory | 182728 kb |
Host | smart-54fca214-a739-48e9-9a25-d6599275f66e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413297611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1413297611 |
Directory | /workspace/14.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2924202306 |
Short name | T87 |
Test name | |
Test status | |
Simulation time | 88566584 ps |
CPU time | 0.68 seconds |
Started | Aug 08 05:51:38 PM PDT 24 |
Finished | Aug 08 05:51:39 PM PDT 24 |
Peak memory | 192536 kb |
Host | smart-c29c412a-f8ae-44cc-bd99-e026138c9f0e |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924202306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t imer_same_csr_outstanding.2924202306 |
Directory | /workspace/14.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2019349514 |
Short name | T551 |
Test name | |
Test status | |
Simulation time | 239980765 ps |
CPU time | 2.05 seconds |
Started | Aug 08 05:53:03 PM PDT 24 |
Finished | Aug 08 05:53:06 PM PDT 24 |
Peak memory | 197400 kb |
Host | smart-555e743f-1607-4719-aeda-6bf4ab3257bb |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019349514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2019349514 |
Directory | /workspace/14.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3162550499 |
Short name | T536 |
Test name | |
Test status | |
Simulation time | 498936700 ps |
CPU time | 0.82 seconds |
Started | Aug 08 05:52:49 PM PDT 24 |
Finished | Aug 08 05:52:50 PM PDT 24 |
Peak memory | 192848 kb |
Host | smart-680e9175-31af-4f18-bfe1-02bd58c85670 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162550499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i ntg_err.3162550499 |
Directory | /workspace/14.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1399420018 |
Short name | T528 |
Test name | |
Test status | |
Simulation time | 15255587 ps |
CPU time | 0.6 seconds |
Started | Aug 08 05:51:36 PM PDT 24 |
Finished | Aug 08 05:51:36 PM PDT 24 |
Peak memory | 192964 kb |
Host | smart-d25fb1ed-70a6-4a56-a92e-76fbf854735e |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399420018 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1399420018 |
Directory | /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2744614419 |
Short name | T479 |
Test name | |
Test status | |
Simulation time | 27072994 ps |
CPU time | 0.57 seconds |
Started | Aug 08 05:51:36 PM PDT 24 |
Finished | Aug 08 05:51:37 PM PDT 24 |
Peak memory | 182956 kb |
Host | smart-9df39fc3-11c8-4d55-9c50-18763503734c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744614419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2744614419 |
Directory | /workspace/15.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3591138831 |
Short name | T507 |
Test name | |
Test status | |
Simulation time | 12396537 ps |
CPU time | 0.56 seconds |
Started | Aug 08 05:51:37 PM PDT 24 |
Finished | Aug 08 05:51:38 PM PDT 24 |
Peak memory | 181936 kb |
Host | smart-bfb8584f-ee26-4617-9158-e126aab7fa55 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591138831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3591138831 |
Directory | /workspace/15.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.678776037 |
Short name | T91 |
Test name | |
Test status | |
Simulation time | 23252468 ps |
CPU time | 0.63 seconds |
Started | Aug 08 05:51:38 PM PDT 24 |
Finished | Aug 08 05:51:39 PM PDT 24 |
Peak memory | 192228 kb |
Host | smart-4a5ee613-5df0-401f-bcf9-459339f1e554 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678776037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti mer_same_csr_outstanding.678776037 |
Directory | /workspace/15.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.184187751 |
Short name | T554 |
Test name | |
Test status | |
Simulation time | 75254274 ps |
CPU time | 1.53 seconds |
Started | Aug 08 05:51:37 PM PDT 24 |
Finished | Aug 08 05:51:39 PM PDT 24 |
Peak memory | 197652 kb |
Host | smart-b11a22dd-2cc2-4114-be9a-09e5d06b875b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184187751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.184187751 |
Directory | /workspace/15.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2731143566 |
Short name | T558 |
Test name | |
Test status | |
Simulation time | 94567903 ps |
CPU time | 0.81 seconds |
Started | Aug 08 05:51:36 PM PDT 24 |
Finished | Aug 08 05:51:37 PM PDT 24 |
Peak memory | 193692 kb |
Host | smart-79b2d2da-f589-4b96-9dd8-f72aa4fbd481 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731143566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i ntg_err.2731143566 |
Directory | /workspace/15.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3864605993 |
Short name | T32 |
Test name | |
Test status | |
Simulation time | 120149088 ps |
CPU time | 0.76 seconds |
Started | Aug 08 05:51:47 PM PDT 24 |
Finished | Aug 08 05:51:49 PM PDT 24 |
Peak memory | 196116 kb |
Host | smart-8e17058b-24a6-44b3-a5df-a44a0646ed31 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864605993 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3864605993 |
Directory | /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.77469042 |
Short name | T533 |
Test name | |
Test status | |
Simulation time | 13737748 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:51:50 PM PDT 24 |
Finished | Aug 08 05:51:51 PM PDT 24 |
Peak memory | 182928 kb |
Host | smart-51b08768-9f00-4a2d-8c21-48c2f096c89b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77469042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.77469042 |
Directory | /workspace/16.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1626424122 |
Short name | T488 |
Test name | |
Test status | |
Simulation time | 12691620 ps |
CPU time | 0.58 seconds |
Started | Aug 08 05:51:48 PM PDT 24 |
Finished | Aug 08 05:51:48 PM PDT 24 |
Peak memory | 182264 kb |
Host | smart-6fe07fd6-0bbb-4597-afec-a37e655fc46e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626424122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1626424122 |
Directory | /workspace/16.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.348654506 |
Short name | T530 |
Test name | |
Test status | |
Simulation time | 92978774 ps |
CPU time | 0.66 seconds |
Started | Aug 08 05:51:48 PM PDT 24 |
Finished | Aug 08 05:51:49 PM PDT 24 |
Peak memory | 191872 kb |
Host | smart-9ae985b0-d902-4dc4-b73e-e274adccc776 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348654506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti mer_same_csr_outstanding.348654506 |
Directory | /workspace/16.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2640182325 |
Short name | T559 |
Test name | |
Test status | |
Simulation time | 382481440 ps |
CPU time | 2.97 seconds |
Started | Aug 08 05:51:38 PM PDT 24 |
Finished | Aug 08 05:51:41 PM PDT 24 |
Peak memory | 197604 kb |
Host | smart-7a7bb728-5ce7-464e-ab63-aa56e9fa21a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640182325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2640182325 |
Directory | /workspace/16.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2392912612 |
Short name | T520 |
Test name | |
Test status | |
Simulation time | 99127720 ps |
CPU time | 1.32 seconds |
Started | Aug 08 05:51:49 PM PDT 24 |
Finished | Aug 08 05:51:50 PM PDT 24 |
Peak memory | 195724 kb |
Host | smart-23f91a91-71c8-40bd-a097-83d3d6a7e369 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392912612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i ntg_err.2392912612 |
Directory | /workspace/16.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1132660695 |
Short name | T517 |
Test name | |
Test status | |
Simulation time | 109523058 ps |
CPU time | 0.82 seconds |
Started | Aug 08 05:51:49 PM PDT 24 |
Finished | Aug 08 05:51:50 PM PDT 24 |
Peak memory | 197508 kb |
Host | smart-5cc57412-52e0-4390-aa2c-5956a34eec35 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132660695 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1132660695 |
Directory | /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3399861257 |
Short name | T54 |
Test name | |
Test status | |
Simulation time | 126138251 ps |
CPU time | 0.58 seconds |
Started | Aug 08 05:51:47 PM PDT 24 |
Finished | Aug 08 05:51:48 PM PDT 24 |
Peak memory | 182992 kb |
Host | smart-e97a9e47-bf4d-42cd-97cf-0cd112dd3a5c |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399861257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3399861257 |
Directory | /workspace/17.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3652564314 |
Short name | T561 |
Test name | |
Test status | |
Simulation time | 79481647 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:51:50 PM PDT 24 |
Finished | Aug 08 05:51:51 PM PDT 24 |
Peak memory | 182828 kb |
Host | smart-6f5e2f64-f973-4bc2-8b26-d5240b9bdeae |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652564314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3652564314 |
Directory | /workspace/17.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2549893574 |
Short name | T563 |
Test name | |
Test status | |
Simulation time | 39676164 ps |
CPU time | 0.65 seconds |
Started | Aug 08 05:51:48 PM PDT 24 |
Finished | Aug 08 05:51:49 PM PDT 24 |
Peak memory | 193228 kb |
Host | smart-9cf01e45-892e-4a6f-a762-ed42bb069e22 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549893574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t imer_same_csr_outstanding.2549893574 |
Directory | /workspace/17.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2268537266 |
Short name | T499 |
Test name | |
Test status | |
Simulation time | 43507812 ps |
CPU time | 0.98 seconds |
Started | Aug 08 05:51:48 PM PDT 24 |
Finished | Aug 08 05:51:49 PM PDT 24 |
Peak memory | 197112 kb |
Host | smart-b8dbc8bc-6698-468f-abaf-9d866f2b3671 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268537266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2268537266 |
Directory | /workspace/17.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3991109615 |
Short name | T56 |
Test name | |
Test status | |
Simulation time | 49840993 ps |
CPU time | 0.78 seconds |
Started | Aug 08 05:51:48 PM PDT 24 |
Finished | Aug 08 05:51:49 PM PDT 24 |
Peak memory | 193868 kb |
Host | smart-c4d73906-f0ca-4b27-a76d-70c866103255 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991109615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i ntg_err.3991109615 |
Directory | /workspace/17.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2953694396 |
Short name | T486 |
Test name | |
Test status | |
Simulation time | 25783562 ps |
CPU time | 0.68 seconds |
Started | Aug 08 05:53:04 PM PDT 24 |
Finished | Aug 08 05:53:05 PM PDT 24 |
Peak memory | 194452 kb |
Host | smart-d2e836c5-cb0e-4713-8927-ac01063ba6c4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953694396 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2953694396 |
Directory | /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3327048552 |
Short name | T73 |
Test name | |
Test status | |
Simulation time | 32304953 ps |
CPU time | 0.57 seconds |
Started | Aug 08 05:51:47 PM PDT 24 |
Finished | Aug 08 05:51:48 PM PDT 24 |
Peak memory | 182828 kb |
Host | smart-f489d9cf-1473-4f57-b479-dd00bfb2ef1a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327048552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3327048552 |
Directory | /workspace/18.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.53538712 |
Short name | T466 |
Test name | |
Test status | |
Simulation time | 35788107 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:51:48 PM PDT 24 |
Finished | Aug 08 05:51:49 PM PDT 24 |
Peak memory | 182676 kb |
Host | smart-facaa718-e119-46f2-b7cf-bbdeabc3fab3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53538712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.53538712 |
Directory | /workspace/18.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2359037038 |
Short name | T74 |
Test name | |
Test status | |
Simulation time | 68488930 ps |
CPU time | 0.74 seconds |
Started | Aug 08 05:51:47 PM PDT 24 |
Finished | Aug 08 05:51:48 PM PDT 24 |
Peak memory | 193632 kb |
Host | smart-1134d106-2ed4-4e1a-8d9d-3a969d7e28f9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359037038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t imer_same_csr_outstanding.2359037038 |
Directory | /workspace/18.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1551305513 |
Short name | T544 |
Test name | |
Test status | |
Simulation time | 261289875 ps |
CPU time | 2.7 seconds |
Started | Aug 08 05:53:04 PM PDT 24 |
Finished | Aug 08 05:53:07 PM PDT 24 |
Peak memory | 197460 kb |
Host | smart-dc34bb6a-0f7e-4c1b-8097-bcf37dd5435d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551305513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1551305513 |
Directory | /workspace/18.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1194734173 |
Short name | T550 |
Test name | |
Test status | |
Simulation time | 273486947 ps |
CPU time | 1.31 seconds |
Started | Aug 08 05:51:47 PM PDT 24 |
Finished | Aug 08 05:51:49 PM PDT 24 |
Peak memory | 183292 kb |
Host | smart-7b51d88e-1e42-4224-8ec0-cc98ff7065d8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194734173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i ntg_err.1194734173 |
Directory | /workspace/18.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1366397651 |
Short name | T477 |
Test name | |
Test status | |
Simulation time | 20694189 ps |
CPU time | 0.83 seconds |
Started | Aug 08 05:52:01 PM PDT 24 |
Finished | Aug 08 05:52:02 PM PDT 24 |
Peak memory | 196368 kb |
Host | smart-82975eb1-34a6-4e11-a477-d60cc092540a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366397651 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1366397651 |
Directory | /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3436556458 |
Short name | T86 |
Test name | |
Test status | |
Simulation time | 96081347 ps |
CPU time | 0.56 seconds |
Started | Aug 08 05:51:48 PM PDT 24 |
Finished | Aug 08 05:51:49 PM PDT 24 |
Peak memory | 182972 kb |
Host | smart-91726a3c-3f9e-4900-bc6e-a951940e3bb9 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436556458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3436556458 |
Directory | /workspace/19.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3596777746 |
Short name | T556 |
Test name | |
Test status | |
Simulation time | 59832583 ps |
CPU time | 0.58 seconds |
Started | Aug 08 05:51:47 PM PDT 24 |
Finished | Aug 08 05:51:48 PM PDT 24 |
Peak memory | 182784 kb |
Host | smart-5187871b-5a26-42ea-8d32-aabe1b746be7 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596777746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3596777746 |
Directory | /workspace/19.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.567229811 |
Short name | T75 |
Test name | |
Test status | |
Simulation time | 117422990 ps |
CPU time | 0.78 seconds |
Started | Aug 08 05:52:02 PM PDT 24 |
Finished | Aug 08 05:52:03 PM PDT 24 |
Peak memory | 191932 kb |
Host | smart-8d94e472-83ce-4404-b247-73772e9dc501 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567229811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti mer_same_csr_outstanding.567229811 |
Directory | /workspace/19.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3112504822 |
Short name | T53 |
Test name | |
Test status | |
Simulation time | 548067088 ps |
CPU time | 2.05 seconds |
Started | Aug 08 05:51:49 PM PDT 24 |
Finished | Aug 08 05:51:51 PM PDT 24 |
Peak memory | 197664 kb |
Host | smart-2716152d-8fe6-4f36-beb6-571d2feccf8a |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112504822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3112504822 |
Directory | /workspace/19.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3270447538 |
Short name | T473 |
Test name | |
Test status | |
Simulation time | 549620450 ps |
CPU time | 1.08 seconds |
Started | Aug 08 05:53:04 PM PDT 24 |
Finished | Aug 08 05:53:05 PM PDT 24 |
Peak memory | 194892 kb |
Host | smart-11e4c822-d7f2-4f7f-be63-ffe72a96c098 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270447538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i ntg_err.3270447538 |
Directory | /workspace/19.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3159162976 |
Short name | T574 |
Test name | |
Test status | |
Simulation time | 57241506 ps |
CPU time | 0.68 seconds |
Started | Aug 08 05:50:47 PM PDT 24 |
Finished | Aug 08 05:50:48 PM PDT 24 |
Peak memory | 182904 kb |
Host | smart-6fca6d1c-1f27-44bc-b6eb-fc4a70f8362b |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159162976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia sing.3159162976 |
Directory | /workspace/2.rv_timer_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.818159414 |
Short name | T545 |
Test name | |
Test status | |
Simulation time | 216922468 ps |
CPU time | 2.51 seconds |
Started | Aug 08 05:50:49 PM PDT 24 |
Finished | Aug 08 05:50:51 PM PDT 24 |
Peak memory | 191352 kb |
Host | smart-c6aabf42-2574-4121-8969-7801074fa137 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818159414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b ash.818159414 |
Directory | /workspace/2.rv_timer_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2167879556 |
Short name | T77 |
Test name | |
Test status | |
Simulation time | 15527486 ps |
CPU time | 0.59 seconds |
Started | Aug 08 05:50:49 PM PDT 24 |
Finished | Aug 08 05:50:50 PM PDT 24 |
Peak memory | 182980 kb |
Host | smart-192ae53e-4324-4da1-beb8-8d227224584a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167879556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r eset.2167879556 |
Directory | /workspace/2.rv_timer_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1887314299 |
Short name | T534 |
Test name | |
Test status | |
Simulation time | 120937771 ps |
CPU time | 1.54 seconds |
Started | Aug 08 05:50:49 PM PDT 24 |
Finished | Aug 08 05:50:50 PM PDT 24 |
Peak memory | 197744 kb |
Host | smart-01f78521-8746-4178-a161-7b2c86c35b81 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887314299 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1887314299 |
Directory | /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1771292835 |
Short name | T562 |
Test name | |
Test status | |
Simulation time | 11580852 ps |
CPU time | 0.54 seconds |
Started | Aug 08 05:50:48 PM PDT 24 |
Finished | Aug 08 05:50:49 PM PDT 24 |
Peak memory | 182904 kb |
Host | smart-1468e77b-2b75-492f-a0f0-a4e6bc7b6ba7 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771292835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1771292835 |
Directory | /workspace/2.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3213811991 |
Short name | T552 |
Test name | |
Test status | |
Simulation time | 14650985 ps |
CPU time | 0.54 seconds |
Started | Aug 08 05:50:47 PM PDT 24 |
Finished | Aug 08 05:50:48 PM PDT 24 |
Peak memory | 182680 kb |
Host | smart-49a7776b-56c1-4261-b6f9-f12839176f87 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213811991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3213811991 |
Directory | /workspace/2.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2598809212 |
Short name | T516 |
Test name | |
Test status | |
Simulation time | 27498757 ps |
CPU time | 0.7 seconds |
Started | Aug 08 05:50:49 PM PDT 24 |
Finished | Aug 08 05:50:50 PM PDT 24 |
Peak memory | 191952 kb |
Host | smart-58224a38-7cc2-41cc-a731-a0b59b218c13 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598809212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti mer_same_csr_outstanding.2598809212 |
Directory | /workspace/2.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.635867788 |
Short name | T457 |
Test name | |
Test status | |
Simulation time | 36860588 ps |
CPU time | 1.6 seconds |
Started | Aug 08 05:50:47 PM PDT 24 |
Finished | Aug 08 05:50:49 PM PDT 24 |
Peak memory | 197688 kb |
Host | smart-5b5c330f-2543-4c58-9cdc-f6509841fba4 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635867788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.635867788 |
Directory | /workspace/2.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1252078544 |
Short name | T104 |
Test name | |
Test status | |
Simulation time | 236723758 ps |
CPU time | 1.06 seconds |
Started | Aug 08 05:50:48 PM PDT 24 |
Finished | Aug 08 05:50:49 PM PDT 24 |
Peak memory | 195392 kb |
Host | smart-035400fc-92db-438d-9d70-66526a89d252 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252078544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in tg_err.1252078544 |
Directory | /workspace/2.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3071309 |
Short name | T547 |
Test name | |
Test status | |
Simulation time | 39525063 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:59 PM PDT 24 |
Finished | Aug 08 05:51:59 PM PDT 24 |
Peak memory | 182692 kb |
Host | smart-f560ade1-e1da-4896-a6ff-bf38aaf845ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3071309 |
Directory | /workspace/20.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.4154535274 |
Short name | T526 |
Test name | |
Test status | |
Simulation time | 61569062 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:58 PM PDT 24 |
Finished | Aug 08 05:51:59 PM PDT 24 |
Peak memory | 182232 kb |
Host | smart-ac8bbaaf-8fc8-404c-8e48-dd212c975fed |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154535274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.4154535274 |
Directory | /workspace/21.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2138328966 |
Short name | T480 |
Test name | |
Test status | |
Simulation time | 15147800 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:58 PM PDT 24 |
Finished | Aug 08 05:51:58 PM PDT 24 |
Peak memory | 182680 kb |
Host | smart-70165931-348b-415c-bff1-8f597674286e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138328966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2138328966 |
Directory | /workspace/22.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1952798170 |
Short name | T512 |
Test name | |
Test status | |
Simulation time | 47435641 ps |
CPU time | 0.56 seconds |
Started | Aug 08 05:51:59 PM PDT 24 |
Finished | Aug 08 05:52:00 PM PDT 24 |
Peak memory | 182748 kb |
Host | smart-b10bf624-8cfb-4867-9e7b-b0825085fe15 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952798170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1952798170 |
Directory | /workspace/23.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3132869112 |
Short name | T456 |
Test name | |
Test status | |
Simulation time | 43734932 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:51:57 PM PDT 24 |
Finished | Aug 08 05:51:58 PM PDT 24 |
Peak memory | 182800 kb |
Host | smart-e3a1eeca-a611-45a8-8075-e09b27115512 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132869112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3132869112 |
Directory | /workspace/24.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3537615049 |
Short name | T538 |
Test name | |
Test status | |
Simulation time | 14124338 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:57 PM PDT 24 |
Finished | Aug 08 05:51:58 PM PDT 24 |
Peak memory | 182744 kb |
Host | smart-6d003378-c6f3-4f20-94a5-66d2bf5381e0 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537615049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3537615049 |
Directory | /workspace/25.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2626022995 |
Short name | T572 |
Test name | |
Test status | |
Simulation time | 165405960 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:51:58 PM PDT 24 |
Finished | Aug 08 05:51:59 PM PDT 24 |
Peak memory | 182688 kb |
Host | smart-b3d63e98-4072-461f-8207-184677266db9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626022995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2626022995 |
Directory | /workspace/26.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2373242128 |
Short name | T539 |
Test name | |
Test status | |
Simulation time | 19064564 ps |
CPU time | 0.52 seconds |
Started | Aug 08 05:51:58 PM PDT 24 |
Finished | Aug 08 05:51:59 PM PDT 24 |
Peak memory | 182152 kb |
Host | smart-ca0f1988-a528-46e7-81ca-b53ad3ad29d3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373242128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2373242128 |
Directory | /workspace/27.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.4189841978 |
Short name | T478 |
Test name | |
Test status | |
Simulation time | 15796301 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:52:00 PM PDT 24 |
Finished | Aug 08 05:52:01 PM PDT 24 |
Peak memory | 182704 kb |
Host | smart-281da408-c984-47b9-8fc8-23b67884e0f9 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189841978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.4189841978 |
Directory | /workspace/28.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4031224740 |
Short name | T522 |
Test name | |
Test status | |
Simulation time | 45675921 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:51:58 PM PDT 24 |
Finished | Aug 08 05:51:59 PM PDT 24 |
Peak memory | 182224 kb |
Host | smart-ab4782b6-06b2-4a1c-9d7a-f10bb9ff6f48 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031224740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.4031224740 |
Directory | /workspace/29.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.123771947 |
Short name | T84 |
Test name | |
Test status | |
Simulation time | 15473676 ps |
CPU time | 0.7 seconds |
Started | Aug 08 05:50:57 PM PDT 24 |
Finished | Aug 08 05:50:58 PM PDT 24 |
Peak memory | 192132 kb |
Host | smart-68dfe1e3-aca7-443f-b45b-c4e278d94021 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123771947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias ing.123771947 |
Directory | /workspace/3.rv_timer_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1644059000 |
Short name | T535 |
Test name | |
Test status | |
Simulation time | 337904401 ps |
CPU time | 3.09 seconds |
Started | Aug 08 05:50:56 PM PDT 24 |
Finished | Aug 08 05:50:59 PM PDT 24 |
Peak memory | 191324 kb |
Host | smart-9537bac7-b3e6-426c-8a7b-1e31c7ef43fd |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644059000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_ bash.1644059000 |
Directory | /workspace/3.rv_timer_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1150401705 |
Short name | T467 |
Test name | |
Test status | |
Simulation time | 39063702 ps |
CPU time | 0.51 seconds |
Started | Aug 08 05:50:56 PM PDT 24 |
Finished | Aug 08 05:50:57 PM PDT 24 |
Peak memory | 182936 kb |
Host | smart-fe5fc340-e530-43eb-8dae-a14293942c1a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150401705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r eset.1150401705 |
Directory | /workspace/3.rv_timer_csr_hw_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.591028969 |
Short name | T464 |
Test name | |
Test status | |
Simulation time | 20409293 ps |
CPU time | 0.86 seconds |
Started | Aug 08 05:50:58 PM PDT 24 |
Finished | Aug 08 05:50:59 PM PDT 24 |
Peak memory | 196836 kb |
Host | smart-4ec064fb-8fe2-4a80-ab13-9c0bdae87aec |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591028969 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.591028969 |
Directory | /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.628352823 |
Short name | T540 |
Test name | |
Test status | |
Simulation time | 12395910 ps |
CPU time | 0.59 seconds |
Started | Aug 08 05:50:55 PM PDT 24 |
Finished | Aug 08 05:50:56 PM PDT 24 |
Peak memory | 182972 kb |
Host | smart-b5729722-b39c-4e48-8b9a-6f3fdf81963a |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628352823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.628352823 |
Directory | /workspace/3.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.513602463 |
Short name | T459 |
Test name | |
Test status | |
Simulation time | 16517058 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:50:56 PM PDT 24 |
Finished | Aug 08 05:50:57 PM PDT 24 |
Peak memory | 182780 kb |
Host | smart-8a4778cd-d3e7-4970-afb9-e6d2b453601c |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513602463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.513602463 |
Directory | /workspace/3.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3095017844 |
Short name | T525 |
Test name | |
Test status | |
Simulation time | 37800652 ps |
CPU time | 0.77 seconds |
Started | Aug 08 05:50:57 PM PDT 24 |
Finished | Aug 08 05:50:57 PM PDT 24 |
Peak memory | 191804 kb |
Host | smart-09649f85-b154-4771-a21e-4fbe3e225750 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095017844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti mer_same_csr_outstanding.3095017844 |
Directory | /workspace/3.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.751239807 |
Short name | T453 |
Test name | |
Test status | |
Simulation time | 22485009 ps |
CPU time | 1.21 seconds |
Started | Aug 08 05:50:57 PM PDT 24 |
Finished | Aug 08 05:50:58 PM PDT 24 |
Peak memory | 197644 kb |
Host | smart-4555bb2a-19f0-45ad-8f85-d12686eaf45d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751239807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.751239807 |
Directory | /workspace/3.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3347844261 |
Short name | T495 |
Test name | |
Test status | |
Simulation time | 34088214 ps |
CPU time | 0.75 seconds |
Started | Aug 08 05:50:57 PM PDT 24 |
Finished | Aug 08 05:50:58 PM PDT 24 |
Peak memory | 192532 kb |
Host | smart-c92a1a4d-5b1b-4d1d-897d-4fa05300bf69 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347844261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in tg_err.3347844261 |
Directory | /workspace/3.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2099842980 |
Short name | T570 |
Test name | |
Test status | |
Simulation time | 32554127 ps |
CPU time | 0.52 seconds |
Started | Aug 08 05:51:58 PM PDT 24 |
Finished | Aug 08 05:51:59 PM PDT 24 |
Peak memory | 182676 kb |
Host | smart-5b319a5d-5625-4e5e-a2c6-1c52a7ab16bf |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099842980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2099842980 |
Directory | /workspace/30.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.480101668 |
Short name | T506 |
Test name | |
Test status | |
Simulation time | 28407582 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:59 PM PDT 24 |
Finished | Aug 08 05:52:00 PM PDT 24 |
Peak memory | 182668 kb |
Host | smart-c9b470c4-4456-4518-9d11-0f561e35f5fb |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480101668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.480101668 |
Directory | /workspace/31.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4193767176 |
Short name | T524 |
Test name | |
Test status | |
Simulation time | 24049867 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:52:01 PM PDT 24 |
Finished | Aug 08 05:52:01 PM PDT 24 |
Peak memory | 182828 kb |
Host | smart-f12928c8-fec6-4272-bcf8-aba459146be8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193767176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4193767176 |
Directory | /workspace/32.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3073857092 |
Short name | T503 |
Test name | |
Test status | |
Simulation time | 16907319 ps |
CPU time | 0.57 seconds |
Started | Aug 08 05:51:57 PM PDT 24 |
Finished | Aug 08 05:51:58 PM PDT 24 |
Peak memory | 182744 kb |
Host | smart-bc21fc6b-3a15-4eb2-b4ef-95becf913d50 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073857092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3073857092 |
Directory | /workspace/33.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2104360023 |
Short name | T460 |
Test name | |
Test status | |
Simulation time | 55327194 ps |
CPU time | 0.57 seconds |
Started | Aug 08 05:52:02 PM PDT 24 |
Finished | Aug 08 05:52:02 PM PDT 24 |
Peak memory | 182768 kb |
Host | smart-e1184ff8-dc58-420d-9dc1-8ac7de63e920 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104360023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2104360023 |
Directory | /workspace/34.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1355183034 |
Short name | T476 |
Test name | |
Test status | |
Simulation time | 13401656 ps |
CPU time | 0.54 seconds |
Started | Aug 08 05:51:57 PM PDT 24 |
Finished | Aug 08 05:51:57 PM PDT 24 |
Peak memory | 182732 kb |
Host | smart-181876c4-7c1d-49d7-8613-1a663217251a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355183034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1355183034 |
Directory | /workspace/35.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.681500504 |
Short name | T514 |
Test name | |
Test status | |
Simulation time | 31772117 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:56 PM PDT 24 |
Finished | Aug 08 05:51:57 PM PDT 24 |
Peak memory | 182400 kb |
Host | smart-87416f4f-0ea4-4e17-b479-b8802294f1db |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681500504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.681500504 |
Directory | /workspace/36.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.4218723005 |
Short name | T510 |
Test name | |
Test status | |
Simulation time | 67551473 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:51:57 PM PDT 24 |
Finished | Aug 08 05:51:58 PM PDT 24 |
Peak memory | 182700 kb |
Host | smart-9025f845-04f5-4667-bdb6-6cb38112f716 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218723005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.4218723005 |
Directory | /workspace/37.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3857027173 |
Short name | T487 |
Test name | |
Test status | |
Simulation time | 13460392 ps |
CPU time | 0.54 seconds |
Started | Aug 08 05:53:04 PM PDT 24 |
Finished | Aug 08 05:53:05 PM PDT 24 |
Peak memory | 182556 kb |
Host | smart-3a138d28-1a5e-4365-b833-2fd2ee302aea |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857027173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3857027173 |
Directory | /workspace/38.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3926214686 |
Short name | T452 |
Test name | |
Test status | |
Simulation time | 34049984 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:51:58 PM PDT 24 |
Finished | Aug 08 05:51:59 PM PDT 24 |
Peak memory | 182772 kb |
Host | smart-b863516a-b017-4255-9133-ef9d2d19664f |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926214686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3926214686 |
Directory | /workspace/39.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3362954342 |
Short name | T493 |
Test name | |
Test status | |
Simulation time | 126609697 ps |
CPU time | 0.81 seconds |
Started | Aug 08 05:51:08 PM PDT 24 |
Finished | Aug 08 05:51:09 PM PDT 24 |
Peak memory | 182872 kb |
Host | smart-f948a498-ef1b-4ee7-9140-400f4450f966 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362954342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia sing.3362954342 |
Directory | /workspace/4.rv_timer_csr_aliasing/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1061992719 |
Short name | T33 |
Test name | |
Test status | |
Simulation time | 1087349378 ps |
CPU time | 2.53 seconds |
Started | Aug 08 05:51:07 PM PDT 24 |
Finished | Aug 08 05:51:10 PM PDT 24 |
Peak memory | 194080 kb |
Host | smart-dd7a8f56-e398-4ddd-acc9-46a161b7a3e4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061992719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ bash.1061992719 |
Directory | /workspace/4.rv_timer_csr_bit_bash/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2200385671 |
Short name | T461 |
Test name | |
Test status | |
Simulation time | 76916022 ps |
CPU time | 1.77 seconds |
Started | Aug 08 05:51:06 PM PDT 24 |
Finished | Aug 08 05:51:08 PM PDT 24 |
Peak memory | 197744 kb |
Host | smart-8c888274-513d-4f56-824b-d2f8711c4e31 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200385671 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2200385671 |
Directory | /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4218372914 |
Short name | T509 |
Test name | |
Test status | |
Simulation time | 12810054 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:08 PM PDT 24 |
Finished | Aug 08 05:51:08 PM PDT 24 |
Peak memory | 182960 kb |
Host | smart-5ce68f68-a342-427c-b8dd-3e001d840cf4 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218372914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.4218372914 |
Directory | /workspace/4.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.392882736 |
Short name | T500 |
Test name | |
Test status | |
Simulation time | 12722788 ps |
CPU time | 0.52 seconds |
Started | Aug 08 05:50:56 PM PDT 24 |
Finished | Aug 08 05:50:56 PM PDT 24 |
Peak memory | 182432 kb |
Host | smart-70ec22d9-3e9a-447a-8d12-631279e395d2 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392882736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.392882736 |
Directory | /workspace/4.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2111357254 |
Short name | T88 |
Test name | |
Test status | |
Simulation time | 19704410 ps |
CPU time | 0.76 seconds |
Started | Aug 08 05:51:09 PM PDT 24 |
Finished | Aug 08 05:51:10 PM PDT 24 |
Peak memory | 193488 kb |
Host | smart-ee6ef4b9-ed8a-46d2-b067-56fd4b44f121 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111357254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti mer_same_csr_outstanding.2111357254 |
Directory | /workspace/4.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3587178675 |
Short name | T492 |
Test name | |
Test status | |
Simulation time | 157258502 ps |
CPU time | 2.08 seconds |
Started | Aug 08 05:50:56 PM PDT 24 |
Finished | Aug 08 05:50:58 PM PDT 24 |
Peak memory | 197748 kb |
Host | smart-788a77db-982f-4ac8-af45-baab0003906d |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587178675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3587178675 |
Directory | /workspace/4.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.369017089 |
Short name | T566 |
Test name | |
Test status | |
Simulation time | 122939666 ps |
CPU time | 0.8 seconds |
Started | Aug 08 05:50:57 PM PDT 24 |
Finished | Aug 08 05:50:58 PM PDT 24 |
Peak memory | 193868 kb |
Host | smart-738ee8f3-8ed4-457b-8ce6-f754225a5b68 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369017089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int g_err.369017089 |
Directory | /workspace/4.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3515075709 |
Short name | T567 |
Test name | |
Test status | |
Simulation time | 50580330 ps |
CPU time | 0.54 seconds |
Started | Aug 08 05:52:01 PM PDT 24 |
Finished | Aug 08 05:52:02 PM PDT 24 |
Peak memory | 182448 kb |
Host | smart-d85ec3cf-3b62-4119-aa97-9b89fe292a77 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515075709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3515075709 |
Directory | /workspace/40.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3468858048 |
Short name | T519 |
Test name | |
Test status | |
Simulation time | 58266217 ps |
CPU time | 0.56 seconds |
Started | Aug 08 05:51:57 PM PDT 24 |
Finished | Aug 08 05:51:58 PM PDT 24 |
Peak memory | 182748 kb |
Host | smart-eda4282f-6d9c-48c6-9220-be069ad4eb0e |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468858048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3468858048 |
Directory | /workspace/41.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3987120572 |
Short name | T497 |
Test name | |
Test status | |
Simulation time | 33721824 ps |
CPU time | 0.56 seconds |
Started | Aug 08 05:52:00 PM PDT 24 |
Finished | Aug 08 05:52:01 PM PDT 24 |
Peak memory | 182752 kb |
Host | smart-05a1269d-ecbe-4357-b092-7f74f9fbd6cb |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987120572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3987120572 |
Directory | /workspace/42.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2728661564 |
Short name | T537 |
Test name | |
Test status | |
Simulation time | 46585717 ps |
CPU time | 0.54 seconds |
Started | Aug 08 05:51:59 PM PDT 24 |
Finished | Aug 08 05:52:00 PM PDT 24 |
Peak memory | 182712 kb |
Host | smart-0cbda923-a796-43cf-8884-2f1fdbebfbcb |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728661564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2728661564 |
Directory | /workspace/43.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.4055279898 |
Short name | T515 |
Test name | |
Test status | |
Simulation time | 15255297 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:59 PM PDT 24 |
Finished | Aug 08 05:52:00 PM PDT 24 |
Peak memory | 182180 kb |
Host | smart-e6ac8d77-9f21-4434-9aa8-ceabab18dcd5 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055279898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.4055279898 |
Directory | /workspace/44.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.459746054 |
Short name | T504 |
Test name | |
Test status | |
Simulation time | 13105802 ps |
CPU time | 0.51 seconds |
Started | Aug 08 05:51:57 PM PDT 24 |
Finished | Aug 08 05:51:58 PM PDT 24 |
Peak memory | 182264 kb |
Host | smart-68e80d09-75c9-4bbb-904e-5275632b533a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459746054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.459746054 |
Directory | /workspace/45.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2385607506 |
Short name | T491 |
Test name | |
Test status | |
Simulation time | 28891799 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:59 PM PDT 24 |
Finished | Aug 08 05:52:00 PM PDT 24 |
Peak memory | 182468 kb |
Host | smart-52c68d85-3f43-463a-bcc5-fb197f0d79c8 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385607506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2385607506 |
Directory | /workspace/46.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1991552685 |
Short name | T455 |
Test name | |
Test status | |
Simulation time | 45798916 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:51:57 PM PDT 24 |
Finished | Aug 08 05:51:58 PM PDT 24 |
Peak memory | 182808 kb |
Host | smart-baad4188-56ad-425e-8d2c-6524511e84aa |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991552685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1991552685 |
Directory | /workspace/47.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2128857132 |
Short name | T489 |
Test name | |
Test status | |
Simulation time | 18809779 ps |
CPU time | 0.59 seconds |
Started | Aug 08 05:51:59 PM PDT 24 |
Finished | Aug 08 05:51:59 PM PDT 24 |
Peak memory | 182808 kb |
Host | smart-0dda002a-4a79-4abf-9aaf-0e5f230f8271 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128857132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2128857132 |
Directory | /workspace/48.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.4246197201 |
Short name | T505 |
Test name | |
Test status | |
Simulation time | 52424763 ps |
CPU time | 0.56 seconds |
Started | Aug 08 05:51:58 PM PDT 24 |
Finished | Aug 08 05:51:59 PM PDT 24 |
Peak memory | 182788 kb |
Host | smart-2686ba50-61fb-4cd0-b182-5ebd374386be |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246197201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.4246197201 |
Directory | /workspace/49.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2219299719 |
Short name | T34 |
Test name | |
Test status | |
Simulation time | 86155113 ps |
CPU time | 0.76 seconds |
Started | Aug 08 05:51:09 PM PDT 24 |
Finished | Aug 08 05:51:10 PM PDT 24 |
Peak memory | 195524 kb |
Host | smart-4ca9c549-e4ba-4162-acef-cb15353cb352 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219299719 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2219299719 |
Directory | /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1080010555 |
Short name | T76 |
Test name | |
Test status | |
Simulation time | 36329766 ps |
CPU time | 0.52 seconds |
Started | Aug 08 05:51:07 PM PDT 24 |
Finished | Aug 08 05:51:08 PM PDT 24 |
Peak memory | 182664 kb |
Host | smart-39ff5ed2-6364-495d-b664-5b3fcbcd3595 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080010555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1080010555 |
Directory | /workspace/5.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2958305256 |
Short name | T501 |
Test name | |
Test status | |
Simulation time | 15271080 ps |
CPU time | 0.52 seconds |
Started | Aug 08 05:51:08 PM PDT 24 |
Finished | Aug 08 05:51:09 PM PDT 24 |
Peak memory | 182148 kb |
Host | smart-1e4edebd-c1c4-436b-bf9a-9c5802e2d00a |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958305256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2958305256 |
Directory | /workspace/5.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.887279049 |
Short name | T527 |
Test name | |
Test status | |
Simulation time | 54457220 ps |
CPU time | 0.76 seconds |
Started | Aug 08 05:51:07 PM PDT 24 |
Finished | Aug 08 05:51:08 PM PDT 24 |
Peak memory | 193740 kb |
Host | smart-1ae555c9-c742-4188-b14b-1aaa243b4326 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887279049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim er_same_csr_outstanding.887279049 |
Directory | /workspace/5.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2397723288 |
Short name | T508 |
Test name | |
Test status | |
Simulation time | 103994932 ps |
CPU time | 1.71 seconds |
Started | Aug 08 05:51:08 PM PDT 24 |
Finished | Aug 08 05:51:10 PM PDT 24 |
Peak memory | 197716 kb |
Host | smart-55181d1b-b64c-4803-ac0b-bb6999dc151b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397723288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2397723288 |
Directory | /workspace/5.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2787159313 |
Short name | T483 |
Test name | |
Test status | |
Simulation time | 1310728187 ps |
CPU time | 1.02 seconds |
Started | Aug 08 05:51:07 PM PDT 24 |
Finished | Aug 08 05:51:08 PM PDT 24 |
Peak memory | 195020 kb |
Host | smart-2e5a1e09-b362-4c94-9a6f-538beca2e8cd |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787159313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in tg_err.2787159313 |
Directory | /workspace/5.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1394260059 |
Short name | T546 |
Test name | |
Test status | |
Simulation time | 60620118 ps |
CPU time | 0.7 seconds |
Started | Aug 08 05:51:16 PM PDT 24 |
Finished | Aug 08 05:51:17 PM PDT 24 |
Peak memory | 195048 kb |
Host | smart-474ea473-0287-4185-b1a6-272e5d3353ec |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394260059 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1394260059 |
Directory | /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3667050845 |
Short name | T101 |
Test name | |
Test status | |
Simulation time | 13209345 ps |
CPU time | 0.54 seconds |
Started | Aug 08 05:51:18 PM PDT 24 |
Finished | Aug 08 05:51:19 PM PDT 24 |
Peak memory | 182836 kb |
Host | smart-9469c34c-6993-4789-bc63-4dd426416f02 |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667050845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3667050845 |
Directory | /workspace/6.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.998570103 |
Short name | T485 |
Test name | |
Test status | |
Simulation time | 12508690 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:15 PM PDT 24 |
Finished | Aug 08 05:51:16 PM PDT 24 |
Peak memory | 182456 kb |
Host | smart-728bde1b-9916-4a36-932e-55cbd6171883 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998570103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.998570103 |
Directory | /workspace/6.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2091539434 |
Short name | T90 |
Test name | |
Test status | |
Simulation time | 61349427 ps |
CPU time | 0.72 seconds |
Started | Aug 08 05:51:16 PM PDT 24 |
Finished | Aug 08 05:51:17 PM PDT 24 |
Peak memory | 193484 kb |
Host | smart-75d22113-c4d6-4759-8fb6-246b1f839b7a |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091539434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti mer_same_csr_outstanding.2091539434 |
Directory | /workspace/6.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.14844113 |
Short name | T474 |
Test name | |
Test status | |
Simulation time | 183499211 ps |
CPU time | 1.97 seconds |
Started | Aug 08 05:51:16 PM PDT 24 |
Finished | Aug 08 05:51:18 PM PDT 24 |
Peak memory | 197700 kb |
Host | smart-74e66a8b-8bf2-4407-91d0-d542ffa7596b |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14844113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.14844113 |
Directory | /workspace/6.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.480376407 |
Short name | T106 |
Test name | |
Test status | |
Simulation time | 702731479 ps |
CPU time | 1.4 seconds |
Started | Aug 08 05:51:17 PM PDT 24 |
Finished | Aug 08 05:51:18 PM PDT 24 |
Peak memory | 195752 kb |
Host | smart-2bf7cba5-7917-42d4-a0c4-f3c8d80a7264 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480376407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int g_err.480376407 |
Directory | /workspace/6.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3730451514 |
Short name | T549 |
Test name | |
Test status | |
Simulation time | 46645545 ps |
CPU time | 0.72 seconds |
Started | Aug 08 05:51:20 PM PDT 24 |
Finished | Aug 08 05:51:21 PM PDT 24 |
Peak memory | 194940 kb |
Host | smart-122413bc-0889-40a2-9b3e-9886e56d5862 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730451514 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3730451514 |
Directory | /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.746951552 |
Short name | T560 |
Test name | |
Test status | |
Simulation time | 34287402 ps |
CPU time | 0.54 seconds |
Started | Aug 08 05:51:20 PM PDT 24 |
Finished | Aug 08 05:51:21 PM PDT 24 |
Peak memory | 182672 kb |
Host | smart-b026a354-9f9a-4695-b4a2-83463f99acbf |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746951552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.746951552 |
Directory | /workspace/7.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.693686660 |
Short name | T465 |
Test name | |
Test status | |
Simulation time | 34527680 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:16 PM PDT 24 |
Finished | Aug 08 05:51:17 PM PDT 24 |
Peak memory | 182232 kb |
Host | smart-a699185e-c7e7-466c-8e75-8ca7f8b2316b |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693686660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.693686660 |
Directory | /workspace/7.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.65320154 |
Short name | T496 |
Test name | |
Test status | |
Simulation time | 208378543 ps |
CPU time | 0.6 seconds |
Started | Aug 08 05:51:15 PM PDT 24 |
Finished | Aug 08 05:51:16 PM PDT 24 |
Peak memory | 192168 kb |
Host | smart-9d85b52c-6f44-41a7-b5da-2188cbb5bce3 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65320154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_ timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_time r_same_csr_outstanding.65320154 |
Directory | /workspace/7.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2256707702 |
Short name | T571 |
Test name | |
Test status | |
Simulation time | 126554497 ps |
CPU time | 2.3 seconds |
Started | Aug 08 05:51:15 PM PDT 24 |
Finished | Aug 08 05:51:17 PM PDT 24 |
Peak memory | 197604 kb |
Host | smart-62c238c2-b25f-4d0e-91e9-526c634c33a1 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256707702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2256707702 |
Directory | /workspace/7.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.561294916 |
Short name | T105 |
Test name | |
Test status | |
Simulation time | 837250782 ps |
CPU time | 1.25 seconds |
Started | Aug 08 05:51:16 PM PDT 24 |
Finished | Aug 08 05:51:18 PM PDT 24 |
Peak memory | 195552 kb |
Host | smart-94454572-88bd-4a9e-87d0-ed1ea8ee2a38 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561294916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int g_err.561294916 |
Directory | /workspace/7.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4267007949 |
Short name | T518 |
Test name | |
Test status | |
Simulation time | 33422734 ps |
CPU time | 0.84 seconds |
Started | Aug 08 05:51:16 PM PDT 24 |
Finished | Aug 08 05:51:17 PM PDT 24 |
Peak memory | 197476 kb |
Host | smart-66d8dcc3-1878-46e7-9613-3061c6561d0a |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267007949 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.4267007949 |
Directory | /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.194160577 |
Short name | T463 |
Test name | |
Test status | |
Simulation time | 37076044 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:15 PM PDT 24 |
Finished | Aug 08 05:51:15 PM PDT 24 |
Peak memory | 182924 kb |
Host | smart-f1d88a49-a456-4cd1-97fd-8750b3cf94ea |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194160577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.194160577 |
Directory | /workspace/8.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1367563108 |
Short name | T568 |
Test name | |
Test status | |
Simulation time | 17828765 ps |
CPU time | 0.55 seconds |
Started | Aug 08 05:51:17 PM PDT 24 |
Finished | Aug 08 05:51:17 PM PDT 24 |
Peak memory | 182712 kb |
Host | smart-bed96ab9-b8aa-4e68-98b9-a4676cae4f20 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367563108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1367563108 |
Directory | /workspace/8.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.829111429 |
Short name | T55 |
Test name | |
Test status | |
Simulation time | 20188651 ps |
CPU time | 0.61 seconds |
Started | Aug 08 05:51:16 PM PDT 24 |
Finished | Aug 08 05:51:17 PM PDT 24 |
Peak memory | 191888 kb |
Host | smart-e8413681-3114-430b-91d0-6f334fd82a9b |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829111429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv _timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim er_same_csr_outstanding.829111429 |
Directory | /workspace/8.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2026921236 |
Short name | T481 |
Test name | |
Test status | |
Simulation time | 138349729 ps |
CPU time | 2.34 seconds |
Started | Aug 08 05:51:16 PM PDT 24 |
Finished | Aug 08 05:51:19 PM PDT 24 |
Peak memory | 197612 kb |
Host | smart-9d7e556f-6ce6-4e31-ba6d-3451e7467305 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026921236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2026921236 |
Directory | /workspace/8.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1427854762 |
Short name | T30 |
Test name | |
Test status | |
Simulation time | 469583770 ps |
CPU time | 1.3 seconds |
Started | Aug 08 05:51:16 PM PDT 24 |
Finished | Aug 08 05:51:18 PM PDT 24 |
Peak memory | 183280 kb |
Host | smart-b72d2de2-edcd-4344-9c8f-76ef0d88567f |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427854762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in tg_err.1427854762 |
Directory | /workspace/8.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3611831936 |
Short name | T541 |
Test name | |
Test status | |
Simulation time | 57846808 ps |
CPU time | 0.74 seconds |
Started | Aug 08 05:51:24 PM PDT 24 |
Finished | Aug 08 05:51:25 PM PDT 24 |
Peak memory | 195240 kb |
Host | smart-c44e6bc6-e747-4c4a-965a-0a2deb692f49 |
User | root |
Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611831936 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3611831936 |
Directory | /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2046866823 |
Short name | T80 |
Test name | |
Test status | |
Simulation time | 26668582 ps |
CPU time | 0.56 seconds |
Started | Aug 08 05:51:26 PM PDT 24 |
Finished | Aug 08 05:51:26 PM PDT 24 |
Peak memory | 182972 kb |
Host | smart-a205ac0d-290d-4719-962e-540e455d43bb |
User | root |
Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046866823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2046866823 |
Directory | /workspace/9.rv_timer_csr_rw/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1475465226 |
Short name | T471 |
Test name | |
Test status | |
Simulation time | 15732481 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:51:26 PM PDT 24 |
Finished | Aug 08 05:51:27 PM PDT 24 |
Peak memory | 182812 kb |
Host | smart-bed644d4-4b69-4304-9da4-8618d2228264 |
User | root |
Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475465226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1475465226 |
Directory | /workspace/9.rv_timer_intr_test/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2236920688 |
Short name | T89 |
Test name | |
Test status | |
Simulation time | 25353408 ps |
CPU time | 0.67 seconds |
Started | Aug 08 05:51:36 PM PDT 24 |
Finished | Aug 08 05:51:36 PM PDT 24 |
Peak memory | 192212 kb |
Host | smart-4292de5b-90bd-4f40-8386-29bdfd29fe65 |
User | root |
Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236920688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti mer_same_csr_outstanding.2236920688 |
Directory | /workspace/9.rv_timer_same_csr_outstanding/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.83630551 |
Short name | T468 |
Test name | |
Test status | |
Simulation time | 125211435 ps |
CPU time | 1.91 seconds |
Started | Aug 08 05:51:25 PM PDT 24 |
Finished | Aug 08 05:51:27 PM PDT 24 |
Peak memory | 197728 kb |
Host | smart-50663843-d091-4350-ae4b-ac72b7795155 |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83630551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.83630551 |
Directory | /workspace/9.rv_timer_tl_errors/latest |
Test location | /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2404505968 |
Short name | T543 |
Test name | |
Test status | |
Simulation time | 299213236 ps |
CPU time | 1.05 seconds |
Started | Aug 08 05:51:25 PM PDT 24 |
Finished | Aug 08 05:51:26 PM PDT 24 |
Peak memory | 195556 kb |
Host | smart-51daba95-b29f-4b83-8b0c-1969e912154c |
User | root |
Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404505968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in tg_err.2404505968 |
Directory | /workspace/9.rv_timer_tl_intg_err/latest |
Test location | /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.4285903139 |
Short name | T173 |
Test name | |
Test status | |
Simulation time | 109672283671 ps |
CPU time | 170.74 seconds |
Started | Aug 08 05:55:33 PM PDT 24 |
Finished | Aug 08 05:58:24 PM PDT 24 |
Peak memory | 183464 kb |
Host | smart-df3bdf7a-30cf-4615-ba99-de1fb5c65051 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285903139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.4285903139 |
Directory | /workspace/0.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/0.rv_timer_disabled.506757866 |
Short name | T417 |
Test name | |
Test status | |
Simulation time | 615324219095 ps |
CPU time | 93.36 seconds |
Started | Aug 08 05:55:34 PM PDT 24 |
Finished | Aug 08 05:57:08 PM PDT 24 |
Peak memory | 183368 kb |
Host | smart-8d90866d-81e0-49cf-8b89-5c47b252b4d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=506757866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.506757866 |
Directory | /workspace/0.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/0.rv_timer_random.388069738 |
Short name | T49 |
Test name | |
Test status | |
Simulation time | 92815427320 ps |
CPU time | 158.58 seconds |
Started | Aug 08 05:55:36 PM PDT 24 |
Finished | Aug 08 05:58:15 PM PDT 24 |
Peak memory | 191664 kb |
Host | smart-189185e2-7e78-435e-909d-38a03562c21f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388069738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.388069738 |
Directory | /workspace/0.rv_timer_random/latest |
Test location | /workspace/coverage/default/0.rv_timer_stress_all.1789311800 |
Short name | T62 |
Test name | |
Test status | |
Simulation time | 279570326064 ps |
CPU time | 447.81 seconds |
Started | Aug 08 05:55:34 PM PDT 24 |
Finished | Aug 08 06:03:02 PM PDT 24 |
Peak memory | 195744 kb |
Host | smart-8c2f80c7-0f7e-4493-967e-5d81b9dc54cd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789311800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all. 1789311800 |
Directory | /workspace/0.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.4159668190 |
Short name | T7 |
Test name | |
Test status | |
Simulation time | 888276828486 ps |
CPU time | 1217.95 seconds |
Started | Aug 08 05:55:38 PM PDT 24 |
Finished | Aug 08 06:15:56 PM PDT 24 |
Peak memory | 183432 kb |
Host | smart-dd038203-01c8-45ca-8ce1-9cf2bd7148b8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159668190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.4159668190 |
Directory | /workspace/1.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/1.rv_timer_disabled.1070960725 |
Short name | T394 |
Test name | |
Test status | |
Simulation time | 304738844933 ps |
CPU time | 248.31 seconds |
Started | Aug 08 05:55:40 PM PDT 24 |
Finished | Aug 08 05:59:48 PM PDT 24 |
Peak memory | 183440 kb |
Host | smart-0010a61a-4b53-4dba-af7a-336fa6b2b9bf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1070960725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1070960725 |
Directory | /workspace/1.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/1.rv_timer_random.2819996757 |
Short name | T195 |
Test name | |
Test status | |
Simulation time | 285514490516 ps |
CPU time | 203.95 seconds |
Started | Aug 08 05:55:45 PM PDT 24 |
Finished | Aug 08 05:59:09 PM PDT 24 |
Peak memory | 191632 kb |
Host | smart-74d9f6ea-7840-42d1-9de1-34e9c10484f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819996757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2819996757 |
Directory | /workspace/1.rv_timer_random/latest |
Test location | /workspace/coverage/default/1.rv_timer_sec_cm.1546735434 |
Short name | T16 |
Test name | |
Test status | |
Simulation time | 133158798 ps |
CPU time | 0.81 seconds |
Started | Aug 08 05:55:37 PM PDT 24 |
Finished | Aug 08 05:55:38 PM PDT 24 |
Peak memory | 214048 kb |
Host | smart-d5cd75b6-ccf1-4806-b3f3-0400bcefa8ac |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546735434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1546735434 |
Directory | /workspace/1.rv_timer_sec_cm/latest |
Test location | /workspace/coverage/default/1.rv_timer_stress_all.1826564534 |
Short name | T190 |
Test name | |
Test status | |
Simulation time | 564440391550 ps |
CPU time | 210.36 seconds |
Started | Aug 08 05:55:47 PM PDT 24 |
Finished | Aug 08 05:59:17 PM PDT 24 |
Peak memory | 191684 kb |
Host | smart-7cea5ab6-7945-48a5-9b12-441791510b82 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826564534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all. 1826564534 |
Directory | /workspace/1.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.585541421 |
Short name | T437 |
Test name | |
Test status | |
Simulation time | 208532017096 ps |
CPU time | 314.25 seconds |
Started | Aug 08 05:55:45 PM PDT 24 |
Finished | Aug 08 06:00:59 PM PDT 24 |
Peak memory | 183404 kb |
Host | smart-1f175df2-867a-40c5-81ee-bbb4b162d239 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585541421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.rv_timer_cfg_update_on_fly.585541421 |
Directory | /workspace/10.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/10.rv_timer_disabled.2726916990 |
Short name | T412 |
Test name | |
Test status | |
Simulation time | 457131266853 ps |
CPU time | 177.56 seconds |
Started | Aug 08 05:55:48 PM PDT 24 |
Finished | Aug 08 05:58:46 PM PDT 24 |
Peak memory | 183520 kb |
Host | smart-6cc05e0a-5db6-4768-bdaa-52cdefe34011 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2726916990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2726916990 |
Directory | /workspace/10.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/10.rv_timer_random_reset.3041354809 |
Short name | T329 |
Test name | |
Test status | |
Simulation time | 13465815315 ps |
CPU time | 20.09 seconds |
Started | Aug 08 05:55:48 PM PDT 24 |
Finished | Aug 08 05:56:08 PM PDT 24 |
Peak memory | 191612 kb |
Host | smart-013976f9-4137-4e76-9ad9-2cadf95a27a9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3041354809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3041354809 |
Directory | /workspace/10.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/100.rv_timer_random.3010766838 |
Short name | T188 |
Test name | |
Test status | |
Simulation time | 222654619323 ps |
CPU time | 2451.13 seconds |
Started | Aug 08 05:57:09 PM PDT 24 |
Finished | Aug 08 06:38:01 PM PDT 24 |
Peak memory | 191648 kb |
Host | smart-28e8f5be-1588-4b37-a9bd-340d71ed8ff1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010766838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3010766838 |
Directory | /workspace/100.rv_timer_random/latest |
Test location | /workspace/coverage/default/101.rv_timer_random.1935540362 |
Short name | T259 |
Test name | |
Test status | |
Simulation time | 685489276062 ps |
CPU time | 345.38 seconds |
Started | Aug 08 05:57:10 PM PDT 24 |
Finished | Aug 08 06:02:55 PM PDT 24 |
Peak memory | 191704 kb |
Host | smart-c39ca2df-4610-4b24-a407-9632d01e000d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935540362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1935540362 |
Directory | /workspace/101.rv_timer_random/latest |
Test location | /workspace/coverage/default/105.rv_timer_random.3800710926 |
Short name | T403 |
Test name | |
Test status | |
Simulation time | 95507598811 ps |
CPU time | 786.65 seconds |
Started | Aug 08 05:57:21 PM PDT 24 |
Finished | Aug 08 06:10:28 PM PDT 24 |
Peak memory | 191596 kb |
Host | smart-eb85bbf6-2739-4a92-9b85-d8ad2a0b4c78 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800710926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3800710926 |
Directory | /workspace/105.rv_timer_random/latest |
Test location | /workspace/coverage/default/106.rv_timer_random.1665957944 |
Short name | T427 |
Test name | |
Test status | |
Simulation time | 165462889863 ps |
CPU time | 24.62 seconds |
Started | Aug 08 05:57:21 PM PDT 24 |
Finished | Aug 08 05:57:46 PM PDT 24 |
Peak memory | 183388 kb |
Host | smart-db68b67c-a0fb-42ed-a061-9f65f382c6e2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665957944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1665957944 |
Directory | /workspace/106.rv_timer_random/latest |
Test location | /workspace/coverage/default/107.rv_timer_random.4021030413 |
Short name | T205 |
Test name | |
Test status | |
Simulation time | 17922268168 ps |
CPU time | 201.44 seconds |
Started | Aug 08 05:57:17 PM PDT 24 |
Finished | Aug 08 06:00:39 PM PDT 24 |
Peak memory | 183424 kb |
Host | smart-3c7d7ade-7ad9-47ef-ba8d-3a6e9cd2f669 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021030413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.4021030413 |
Directory | /workspace/107.rv_timer_random/latest |
Test location | /workspace/coverage/default/108.rv_timer_random.2828113790 |
Short name | T390 |
Test name | |
Test status | |
Simulation time | 22497449279 ps |
CPU time | 33.11 seconds |
Started | Aug 08 05:57:17 PM PDT 24 |
Finished | Aug 08 05:57:50 PM PDT 24 |
Peak memory | 183484 kb |
Host | smart-162b2f96-626b-433d-9c42-2f9a9899d767 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828113790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2828113790 |
Directory | /workspace/108.rv_timer_random/latest |
Test location | /workspace/coverage/default/109.rv_timer_random.369054605 |
Short name | T448 |
Test name | |
Test status | |
Simulation time | 317635059885 ps |
CPU time | 1896.14 seconds |
Started | Aug 08 05:57:18 PM PDT 24 |
Finished | Aug 08 06:28:54 PM PDT 24 |
Peak memory | 191656 kb |
Host | smart-6a51f29e-dccf-4d91-aad3-7e5c7ba829af |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369054605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.369054605 |
Directory | /workspace/109.rv_timer_random/latest |
Test location | /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.985860930 |
Short name | T232 |
Test name | |
Test status | |
Simulation time | 3445913541749 ps |
CPU time | 851.83 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 06:09:58 PM PDT 24 |
Peak memory | 183472 kb |
Host | smart-fb3aa8d4-60b1-48c3-8b73-c2e0918a423a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985860930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 1.rv_timer_cfg_update_on_fly.985860930 |
Directory | /workspace/11.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/11.rv_timer_disabled.1291644609 |
Short name | T20 |
Test name | |
Test status | |
Simulation time | 833796211066 ps |
CPU time | 253.86 seconds |
Started | Aug 08 05:55:45 PM PDT 24 |
Finished | Aug 08 05:59:58 PM PDT 24 |
Peak memory | 183460 kb |
Host | smart-d8b46501-fabe-492e-9686-26a8f19c6efe |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291644609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1291644609 |
Directory | /workspace/11.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/11.rv_timer_random_reset.3679081299 |
Short name | T381 |
Test name | |
Test status | |
Simulation time | 14836628 ps |
CPU time | 0.53 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 05:55:46 PM PDT 24 |
Peak memory | 183200 kb |
Host | smart-cf9abddb-cc72-4c81-aaa2-10eefd4e5103 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3679081299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3679081299 |
Directory | /workspace/11.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/111.rv_timer_random.3105944763 |
Short name | T263 |
Test name | |
Test status | |
Simulation time | 59312178659 ps |
CPU time | 386.7 seconds |
Started | Aug 08 05:57:17 PM PDT 24 |
Finished | Aug 08 06:03:43 PM PDT 24 |
Peak memory | 191560 kb |
Host | smart-b0af1b79-b8de-4a3c-a1ec-292d93ae0131 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105944763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3105944763 |
Directory | /workspace/111.rv_timer_random/latest |
Test location | /workspace/coverage/default/112.rv_timer_random.1680957036 |
Short name | T339 |
Test name | |
Test status | |
Simulation time | 309780753513 ps |
CPU time | 486.97 seconds |
Started | Aug 08 05:57:18 PM PDT 24 |
Finished | Aug 08 06:05:25 PM PDT 24 |
Peak memory | 191636 kb |
Host | smart-2f4681ec-ce0a-47d0-9471-87c95f08e392 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680957036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1680957036 |
Directory | /workspace/112.rv_timer_random/latest |
Test location | /workspace/coverage/default/113.rv_timer_random.689742617 |
Short name | T313 |
Test name | |
Test status | |
Simulation time | 70411269085 ps |
CPU time | 50.27 seconds |
Started | Aug 08 05:57:17 PM PDT 24 |
Finished | Aug 08 05:58:07 PM PDT 24 |
Peak memory | 191580 kb |
Host | smart-1732b0cb-bcda-4ff0-9c38-9ed11b096557 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689742617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.689742617 |
Directory | /workspace/113.rv_timer_random/latest |
Test location | /workspace/coverage/default/114.rv_timer_random.2827783751 |
Short name | T429 |
Test name | |
Test status | |
Simulation time | 558962270179 ps |
CPU time | 233.25 seconds |
Started | Aug 08 05:57:19 PM PDT 24 |
Finished | Aug 08 06:01:13 PM PDT 24 |
Peak memory | 183468 kb |
Host | smart-62774e14-2093-4915-bdf2-0e583383215f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827783751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2827783751 |
Directory | /workspace/114.rv_timer_random/latest |
Test location | /workspace/coverage/default/116.rv_timer_random.1700883455 |
Short name | T410 |
Test name | |
Test status | |
Simulation time | 404701947662 ps |
CPU time | 57.68 seconds |
Started | Aug 08 05:57:27 PM PDT 24 |
Finished | Aug 08 05:58:25 PM PDT 24 |
Peak memory | 193888 kb |
Host | smart-7a8f5dfc-23f8-4bcb-a84a-eb7d0f3c5fea |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700883455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1700883455 |
Directory | /workspace/116.rv_timer_random/latest |
Test location | /workspace/coverage/default/118.rv_timer_random.2306936642 |
Short name | T115 |
Test name | |
Test status | |
Simulation time | 379916787184 ps |
CPU time | 609.75 seconds |
Started | Aug 08 05:57:26 PM PDT 24 |
Finished | Aug 08 06:07:36 PM PDT 24 |
Peak memory | 183364 kb |
Host | smart-d1b17efa-9aaa-435b-8ece-cb23ed892da5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306936642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2306936642 |
Directory | /workspace/118.rv_timer_random/latest |
Test location | /workspace/coverage/default/119.rv_timer_random.1477600329 |
Short name | T290 |
Test name | |
Test status | |
Simulation time | 237303087570 ps |
CPU time | 317.17 seconds |
Started | Aug 08 05:57:27 PM PDT 24 |
Finished | Aug 08 06:02:44 PM PDT 24 |
Peak memory | 191716 kb |
Host | smart-d04e7156-b630-4db3-a925-5292f81fefbc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477600329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1477600329 |
Directory | /workspace/119.rv_timer_random/latest |
Test location | /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.835786067 |
Short name | T264 |
Test name | |
Test status | |
Simulation time | 150916742970 ps |
CPU time | 127.24 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 05:57:54 PM PDT 24 |
Peak memory | 183432 kb |
Host | smart-34f8618e-4b94-4503-bdab-ba31418456cb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835786067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 2.rv_timer_cfg_update_on_fly.835786067 |
Directory | /workspace/12.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/12.rv_timer_disabled.3622297048 |
Short name | T373 |
Test name | |
Test status | |
Simulation time | 44426823133 ps |
CPU time | 57.14 seconds |
Started | Aug 08 05:55:48 PM PDT 24 |
Finished | Aug 08 05:56:45 PM PDT 24 |
Peak memory | 183428 kb |
Host | smart-0d0aafca-bbe3-425f-a6c6-cd357e0c405e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3622297048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3622297048 |
Directory | /workspace/12.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/12.rv_timer_random_reset.1154597518 |
Short name | T45 |
Test name | |
Test status | |
Simulation time | 127813720646 ps |
CPU time | 458.65 seconds |
Started | Aug 08 05:55:50 PM PDT 24 |
Finished | Aug 08 06:03:29 PM PDT 24 |
Peak memory | 191572 kb |
Host | smart-e96ce69a-f589-44f9-9e73-ed642e4900b1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1154597518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1154597518 |
Directory | /workspace/12.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/120.rv_timer_random.2984353054 |
Short name | T163 |
Test name | |
Test status | |
Simulation time | 347027289818 ps |
CPU time | 146.94 seconds |
Started | Aug 08 05:57:26 PM PDT 24 |
Finished | Aug 08 05:59:53 PM PDT 24 |
Peak memory | 191620 kb |
Host | smart-8a0ecd98-fa34-4a23-ade9-fc31cbba4174 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984353054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2984353054 |
Directory | /workspace/120.rv_timer_random/latest |
Test location | /workspace/coverage/default/121.rv_timer_random.1174242559 |
Short name | T46 |
Test name | |
Test status | |
Simulation time | 217825577312 ps |
CPU time | 783.57 seconds |
Started | Aug 08 05:57:25 PM PDT 24 |
Finished | Aug 08 06:10:29 PM PDT 24 |
Peak memory | 195236 kb |
Host | smart-c6a9dc40-7483-4dae-b0ac-29e206bf0bf8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174242559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1174242559 |
Directory | /workspace/121.rv_timer_random/latest |
Test location | /workspace/coverage/default/128.rv_timer_random.377232907 |
Short name | T348 |
Test name | |
Test status | |
Simulation time | 383857164760 ps |
CPU time | 1398.05 seconds |
Started | Aug 08 05:57:33 PM PDT 24 |
Finished | Aug 08 06:20:51 PM PDT 24 |
Peak memory | 191636 kb |
Host | smart-56ab562f-5146-41a0-8d0d-3abc1b990d03 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377232907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.377232907 |
Directory | /workspace/128.rv_timer_random/latest |
Test location | /workspace/coverage/default/129.rv_timer_random.4208377686 |
Short name | T308 |
Test name | |
Test status | |
Simulation time | 191637136187 ps |
CPU time | 384.33 seconds |
Started | Aug 08 05:57:33 PM PDT 24 |
Finished | Aug 08 06:03:57 PM PDT 24 |
Peak memory | 193520 kb |
Host | smart-ac4770dc-7bfd-44a0-8e80-fd02cd6ce784 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208377686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4208377686 |
Directory | /workspace/129.rv_timer_random/latest |
Test location | /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1122147474 |
Short name | T136 |
Test name | |
Test status | |
Simulation time | 47191300025 ps |
CPU time | 20.64 seconds |
Started | Aug 08 05:55:48 PM PDT 24 |
Finished | Aug 08 05:56:09 PM PDT 24 |
Peak memory | 183452 kb |
Host | smart-e0bf7740-3f03-469b-9d01-27c4567f9af8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122147474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.1122147474 |
Directory | /workspace/13.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/13.rv_timer_disabled.1334951661 |
Short name | T366 |
Test name | |
Test status | |
Simulation time | 217082417785 ps |
CPU time | 141.61 seconds |
Started | Aug 08 05:55:49 PM PDT 24 |
Finished | Aug 08 05:58:11 PM PDT 24 |
Peak memory | 183416 kb |
Host | smart-b4c63302-a996-431f-89e9-e87d2de3683d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1334951661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1334951661 |
Directory | /workspace/13.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/13.rv_timer_random_reset.402285535 |
Short name | T382 |
Test name | |
Test status | |
Simulation time | 90908963 ps |
CPU time | 0.67 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 05:55:47 PM PDT 24 |
Peak memory | 183240 kb |
Host | smart-c707881f-e023-46a2-9e6d-ef06e29ad761 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=402285535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.402285535 |
Directory | /workspace/13.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/130.rv_timer_random.1357470754 |
Short name | T284 |
Test name | |
Test status | |
Simulation time | 99327023007 ps |
CPU time | 80.4 seconds |
Started | Aug 08 05:57:31 PM PDT 24 |
Finished | Aug 08 05:58:52 PM PDT 24 |
Peak memory | 191540 kb |
Host | smart-a5245b1d-40b6-47c1-ad00-9cc651f1c0b8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357470754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1357470754 |
Directory | /workspace/130.rv_timer_random/latest |
Test location | /workspace/coverage/default/131.rv_timer_random.355312420 |
Short name | T207 |
Test name | |
Test status | |
Simulation time | 315664210738 ps |
CPU time | 148.77 seconds |
Started | Aug 08 05:57:33 PM PDT 24 |
Finished | Aug 08 06:00:02 PM PDT 24 |
Peak memory | 195164 kb |
Host | smart-1d6247df-e7af-428f-b2f2-52f4ce044af0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355312420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.355312420 |
Directory | /workspace/131.rv_timer_random/latest |
Test location | /workspace/coverage/default/132.rv_timer_random.3458202670 |
Short name | T425 |
Test name | |
Test status | |
Simulation time | 26007713070 ps |
CPU time | 44.75 seconds |
Started | Aug 08 05:57:33 PM PDT 24 |
Finished | Aug 08 05:58:17 PM PDT 24 |
Peak memory | 183420 kb |
Host | smart-38ced680-1460-4447-9716-f4c75592e131 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458202670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3458202670 |
Directory | /workspace/132.rv_timer_random/latest |
Test location | /workspace/coverage/default/133.rv_timer_random.2357544339 |
Short name | T157 |
Test name | |
Test status | |
Simulation time | 165465833551 ps |
CPU time | 149.17 seconds |
Started | Aug 08 05:57:34 PM PDT 24 |
Finished | Aug 08 06:00:03 PM PDT 24 |
Peak memory | 191644 kb |
Host | smart-d0fd9767-6f85-4302-99f3-4bf296cc0a28 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357544339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2357544339 |
Directory | /workspace/133.rv_timer_random/latest |
Test location | /workspace/coverage/default/134.rv_timer_random.4027816361 |
Short name | T141 |
Test name | |
Test status | |
Simulation time | 538213942822 ps |
CPU time | 289.61 seconds |
Started | Aug 08 05:57:33 PM PDT 24 |
Finished | Aug 08 06:02:23 PM PDT 24 |
Peak memory | 191660 kb |
Host | smart-c1bc2ca1-cb0a-4793-a7d5-790034c7daaa |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027816361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.4027816361 |
Directory | /workspace/134.rv_timer_random/latest |
Test location | /workspace/coverage/default/136.rv_timer_random.1642146037 |
Short name | T393 |
Test name | |
Test status | |
Simulation time | 17820304661 ps |
CPU time | 603.43 seconds |
Started | Aug 08 05:57:32 PM PDT 24 |
Finished | Aug 08 06:07:35 PM PDT 24 |
Peak memory | 183400 kb |
Host | smart-a54e7020-e6ba-4db8-a5e4-c8fc25443209 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642146037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1642146037 |
Directory | /workspace/136.rv_timer_random/latest |
Test location | /workspace/coverage/default/137.rv_timer_random.2327027816 |
Short name | T179 |
Test name | |
Test status | |
Simulation time | 224397589187 ps |
CPU time | 740.02 seconds |
Started | Aug 08 05:57:35 PM PDT 24 |
Finished | Aug 08 06:09:55 PM PDT 24 |
Peak memory | 191636 kb |
Host | smart-f24da58d-d117-4af8-9e16-b76a9b72830b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327027816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2327027816 |
Directory | /workspace/137.rv_timer_random/latest |
Test location | /workspace/coverage/default/138.rv_timer_random.3287845532 |
Short name | T340 |
Test name | |
Test status | |
Simulation time | 169072657260 ps |
CPU time | 98.29 seconds |
Started | Aug 08 05:57:40 PM PDT 24 |
Finished | Aug 08 05:59:18 PM PDT 24 |
Peak memory | 191664 kb |
Host | smart-9dd5d118-9ad7-48dc-878d-ebcec9841022 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287845532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3287845532 |
Directory | /workspace/138.rv_timer_random/latest |
Test location | /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.716049003 |
Short name | T338 |
Test name | |
Test status | |
Simulation time | 1197133879622 ps |
CPU time | 435.62 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 06:03:02 PM PDT 24 |
Peak memory | 183464 kb |
Host | smart-ea6923e1-2b4b-4f35-a383-c230a6a4238a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716049003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 4.rv_timer_cfg_update_on_fly.716049003 |
Directory | /workspace/14.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/14.rv_timer_disabled.3584405611 |
Short name | T364 |
Test name | |
Test status | |
Simulation time | 81668863899 ps |
CPU time | 119.71 seconds |
Started | Aug 08 05:55:48 PM PDT 24 |
Finished | Aug 08 05:57:48 PM PDT 24 |
Peak memory | 183520 kb |
Host | smart-05964c30-5e71-41e1-a767-481b4911fb1b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3584405611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3584405611 |
Directory | /workspace/14.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/14.rv_timer_random_reset.2239984777 |
Short name | T414 |
Test name | |
Test status | |
Simulation time | 12410661797 ps |
CPU time | 5.5 seconds |
Started | Aug 08 05:55:47 PM PDT 24 |
Finished | Aug 08 05:55:53 PM PDT 24 |
Peak memory | 183460 kb |
Host | smart-da4b369e-6eef-437f-9a51-2dd36076db6a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2239984777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2239984777 |
Directory | /workspace/14.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/140.rv_timer_random.2603486804 |
Short name | T192 |
Test name | |
Test status | |
Simulation time | 277670878777 ps |
CPU time | 79.61 seconds |
Started | Aug 08 05:57:41 PM PDT 24 |
Finished | Aug 08 05:59:00 PM PDT 24 |
Peak memory | 191716 kb |
Host | smart-3f5810ba-c980-4fa7-998e-177af92a98dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603486804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2603486804 |
Directory | /workspace/140.rv_timer_random/latest |
Test location | /workspace/coverage/default/141.rv_timer_random.1946564882 |
Short name | T139 |
Test name | |
Test status | |
Simulation time | 397035437600 ps |
CPU time | 1323.14 seconds |
Started | Aug 08 05:57:40 PM PDT 24 |
Finished | Aug 08 06:19:43 PM PDT 24 |
Peak memory | 193732 kb |
Host | smart-6eeaf647-e2b5-49c3-9673-7ea43c464b95 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946564882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1946564882 |
Directory | /workspace/141.rv_timer_random/latest |
Test location | /workspace/coverage/default/144.rv_timer_random.2510231609 |
Short name | T281 |
Test name | |
Test status | |
Simulation time | 128540004662 ps |
CPU time | 848.68 seconds |
Started | Aug 08 05:57:41 PM PDT 24 |
Finished | Aug 08 06:11:49 PM PDT 24 |
Peak memory | 191636 kb |
Host | smart-b608bc4b-48f2-49f9-878a-48f7a317d555 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510231609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2510231609 |
Directory | /workspace/144.rv_timer_random/latest |
Test location | /workspace/coverage/default/145.rv_timer_random.3476357625 |
Short name | T344 |
Test name | |
Test status | |
Simulation time | 748794905111 ps |
CPU time | 837.33 seconds |
Started | Aug 08 05:57:40 PM PDT 24 |
Finished | Aug 08 06:11:37 PM PDT 24 |
Peak memory | 191608 kb |
Host | smart-132f31cc-9b7b-4c0b-86e7-e5d3fbba6840 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476357625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3476357625 |
Directory | /workspace/145.rv_timer_random/latest |
Test location | /workspace/coverage/default/146.rv_timer_random.1718670084 |
Short name | T287 |
Test name | |
Test status | |
Simulation time | 53973557238 ps |
CPU time | 77.86 seconds |
Started | Aug 08 05:57:40 PM PDT 24 |
Finished | Aug 08 05:58:58 PM PDT 24 |
Peak memory | 183496 kb |
Host | smart-112b671b-2f01-47b4-b13b-de044014b17d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718670084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1718670084 |
Directory | /workspace/146.rv_timer_random/latest |
Test location | /workspace/coverage/default/147.rv_timer_random.784801265 |
Short name | T27 |
Test name | |
Test status | |
Simulation time | 26804694584 ps |
CPU time | 343.04 seconds |
Started | Aug 08 05:57:41 PM PDT 24 |
Finished | Aug 08 06:03:24 PM PDT 24 |
Peak memory | 191684 kb |
Host | smart-bac2401d-393a-40ed-9ee2-abe0b7887179 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784801265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.784801265 |
Directory | /workspace/147.rv_timer_random/latest |
Test location | /workspace/coverage/default/148.rv_timer_random.2532272381 |
Short name | T323 |
Test name | |
Test status | |
Simulation time | 152059772723 ps |
CPU time | 411.48 seconds |
Started | Aug 08 05:57:41 PM PDT 24 |
Finished | Aug 08 06:04:32 PM PDT 24 |
Peak memory | 191648 kb |
Host | smart-37d8eb1f-9bf6-439d-90ba-093836c37b41 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532272381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2532272381 |
Directory | /workspace/148.rv_timer_random/latest |
Test location | /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1975803228 |
Short name | T387 |
Test name | |
Test status | |
Simulation time | 2381903929752 ps |
CPU time | 614.47 seconds |
Started | Aug 08 05:55:47 PM PDT 24 |
Finished | Aug 08 06:06:01 PM PDT 24 |
Peak memory | 183424 kb |
Host | smart-486bb5c6-8751-4588-a096-7b6ef326fe6f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975803228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.1975803228 |
Directory | /workspace/15.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/15.rv_timer_disabled.781621673 |
Short name | T399 |
Test name | |
Test status | |
Simulation time | 75180540731 ps |
CPU time | 58.47 seconds |
Started | Aug 08 05:55:48 PM PDT 24 |
Finished | Aug 08 05:56:47 PM PDT 24 |
Peak memory | 183404 kb |
Host | smart-ac46b9b7-6ca3-4e69-9fd5-e21ac6c1d1ae |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=781621673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.781621673 |
Directory | /workspace/15.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/15.rv_timer_random_reset.3636325715 |
Short name | T346 |
Test name | |
Test status | |
Simulation time | 49889736498 ps |
CPU time | 39.88 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 05:56:26 PM PDT 24 |
Peak memory | 183400 kb |
Host | smart-89f68045-026c-4c3a-84af-a82d09c490d2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3636325715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3636325715 |
Directory | /workspace/15.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/15.rv_timer_stress_all.3388008699 |
Short name | T248 |
Test name | |
Test status | |
Simulation time | 1913306455624 ps |
CPU time | 1425.63 seconds |
Started | Aug 08 05:55:45 PM PDT 24 |
Finished | Aug 08 06:19:31 PM PDT 24 |
Peak memory | 191708 kb |
Host | smart-8a4e032b-5b35-4268-b1ad-29d929e57fa9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388008699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all .3388008699 |
Directory | /workspace/15.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/150.rv_timer_random.3596502311 |
Short name | T424 |
Test name | |
Test status | |
Simulation time | 60746269061 ps |
CPU time | 40.09 seconds |
Started | Aug 08 05:57:42 PM PDT 24 |
Finished | Aug 08 05:58:22 PM PDT 24 |
Peak memory | 183404 kb |
Host | smart-2622f0d9-d629-4b2d-bb61-d6361e59b311 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596502311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3596502311 |
Directory | /workspace/150.rv_timer_random/latest |
Test location | /workspace/coverage/default/152.rv_timer_random.808026177 |
Short name | T164 |
Test name | |
Test status | |
Simulation time | 83406437974 ps |
CPU time | 48.37 seconds |
Started | Aug 08 05:57:50 PM PDT 24 |
Finished | Aug 08 05:58:39 PM PDT 24 |
Peak memory | 191700 kb |
Host | smart-5a8c93eb-7c5e-4dc5-8104-5aea7a583f55 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808026177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.808026177 |
Directory | /workspace/152.rv_timer_random/latest |
Test location | /workspace/coverage/default/153.rv_timer_random.1272655898 |
Short name | T93 |
Test name | |
Test status | |
Simulation time | 146846868783 ps |
CPU time | 152.51 seconds |
Started | Aug 08 05:57:50 PM PDT 24 |
Finished | Aug 08 06:00:22 PM PDT 24 |
Peak memory | 191696 kb |
Host | smart-5d6658a8-c5a5-42ab-b568-900be7ae4f56 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272655898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1272655898 |
Directory | /workspace/153.rv_timer_random/latest |
Test location | /workspace/coverage/default/154.rv_timer_random.2596596 |
Short name | T138 |
Test name | |
Test status | |
Simulation time | 556385165193 ps |
CPU time | 385.92 seconds |
Started | Aug 08 05:57:50 PM PDT 24 |
Finished | Aug 08 06:04:16 PM PDT 24 |
Peak memory | 191660 kb |
Host | smart-3109eb6c-8b60-4f4d-8080-a28957b50473 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2596596 |
Directory | /workspace/154.rv_timer_random/latest |
Test location | /workspace/coverage/default/155.rv_timer_random.2293597414 |
Short name | T349 |
Test name | |
Test status | |
Simulation time | 85855367518 ps |
CPU time | 155.77 seconds |
Started | Aug 08 05:57:48 PM PDT 24 |
Finished | Aug 08 06:00:24 PM PDT 24 |
Peak memory | 191568 kb |
Host | smart-e1cda411-40d2-4e27-b247-b8b7e0f08ac8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293597414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2293597414 |
Directory | /workspace/155.rv_timer_random/latest |
Test location | /workspace/coverage/default/156.rv_timer_random.708243003 |
Short name | T315 |
Test name | |
Test status | |
Simulation time | 2358372719020 ps |
CPU time | 460.91 seconds |
Started | Aug 08 05:57:53 PM PDT 24 |
Finished | Aug 08 06:05:34 PM PDT 24 |
Peak memory | 191596 kb |
Host | smart-75a28d70-b649-46bd-adaf-f77d01b23c6b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708243003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.708243003 |
Directory | /workspace/156.rv_timer_random/latest |
Test location | /workspace/coverage/default/157.rv_timer_random.2753628555 |
Short name | T126 |
Test name | |
Test status | |
Simulation time | 91346439386 ps |
CPU time | 148.25 seconds |
Started | Aug 08 05:57:49 PM PDT 24 |
Finished | Aug 08 06:00:18 PM PDT 24 |
Peak memory | 183424 kb |
Host | smart-f52b5803-a4b0-4df4-8616-bb61718f77ab |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753628555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2753628555 |
Directory | /workspace/157.rv_timer_random/latest |
Test location | /workspace/coverage/default/158.rv_timer_random.878420210 |
Short name | T430 |
Test name | |
Test status | |
Simulation time | 46729035010 ps |
CPU time | 150.59 seconds |
Started | Aug 08 05:57:50 PM PDT 24 |
Finished | Aug 08 06:00:20 PM PDT 24 |
Peak memory | 191660 kb |
Host | smart-7418140d-54fb-4843-b1ae-e87c80ed2fe5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878420210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.878420210 |
Directory | /workspace/158.rv_timer_random/latest |
Test location | /workspace/coverage/default/159.rv_timer_random.2082345424 |
Short name | T233 |
Test name | |
Test status | |
Simulation time | 455028074430 ps |
CPU time | 363.7 seconds |
Started | Aug 08 05:57:48 PM PDT 24 |
Finished | Aug 08 06:03:52 PM PDT 24 |
Peak memory | 191552 kb |
Host | smart-4fc4879e-407b-4647-b74f-b478eec2da6c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082345424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2082345424 |
Directory | /workspace/159.rv_timer_random/latest |
Test location | /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1168942815 |
Short name | T321 |
Test name | |
Test status | |
Simulation time | 2089140309361 ps |
CPU time | 992.56 seconds |
Started | Aug 08 05:55:47 PM PDT 24 |
Finished | Aug 08 06:12:20 PM PDT 24 |
Peak memory | 183420 kb |
Host | smart-4f41d425-36d4-4659-a337-ec83f3f52e2e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168942815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.1168942815 |
Directory | /workspace/16.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/16.rv_timer_random.2962363462 |
Short name | T447 |
Test name | |
Test status | |
Simulation time | 181724656242 ps |
CPU time | 94.55 seconds |
Started | Aug 08 05:56:03 PM PDT 24 |
Finished | Aug 08 05:57:38 PM PDT 24 |
Peak memory | 183404 kb |
Host | smart-20dd9164-2086-44b5-9bf2-346af4b27c3b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962363462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2962363462 |
Directory | /workspace/16.rv_timer_random/latest |
Test location | /workspace/coverage/default/16.rv_timer_random_reset.1046690330 |
Short name | T181 |
Test name | |
Test status | |
Simulation time | 93435045175 ps |
CPU time | 37.63 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 05:56:24 PM PDT 24 |
Peak memory | 191704 kb |
Host | smart-d42ce28b-7267-4b49-ac35-7dd9e40fe760 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1046690330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1046690330 |
Directory | /workspace/16.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/16.rv_timer_stress_all.3504446761 |
Short name | T279 |
Test name | |
Test status | |
Simulation time | 360075202034 ps |
CPU time | 1670.95 seconds |
Started | Aug 08 05:55:55 PM PDT 24 |
Finished | Aug 08 06:23:46 PM PDT 24 |
Peak memory | 191704 kb |
Host | smart-b4a90b15-5d2a-4d93-b9b8-26ba2f162867 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504446761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all .3504446761 |
Directory | /workspace/16.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/160.rv_timer_random.1954590262 |
Short name | T322 |
Test name | |
Test status | |
Simulation time | 63122530420 ps |
CPU time | 96.92 seconds |
Started | Aug 08 05:57:48 PM PDT 24 |
Finished | Aug 08 05:59:25 PM PDT 24 |
Peak memory | 191684 kb |
Host | smart-807b0d83-b939-4b8b-8190-58b939af4ee1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954590262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1954590262 |
Directory | /workspace/160.rv_timer_random/latest |
Test location | /workspace/coverage/default/161.rv_timer_random.1868939646 |
Short name | T286 |
Test name | |
Test status | |
Simulation time | 185323189186 ps |
CPU time | 933.97 seconds |
Started | Aug 08 05:57:49 PM PDT 24 |
Finished | Aug 08 06:13:23 PM PDT 24 |
Peak memory | 183408 kb |
Host | smart-1f53bd12-f9c4-4689-bcf4-f652d9a947a1 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868939646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1868939646 |
Directory | /workspace/161.rv_timer_random/latest |
Test location | /workspace/coverage/default/162.rv_timer_random.2071692075 |
Short name | T158 |
Test name | |
Test status | |
Simulation time | 135761117454 ps |
CPU time | 127.24 seconds |
Started | Aug 08 05:57:49 PM PDT 24 |
Finished | Aug 08 05:59:56 PM PDT 24 |
Peak memory | 191684 kb |
Host | smart-26abe1c7-6bd7-4015-8dd9-2e8ebbd45d9f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071692075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2071692075 |
Directory | /workspace/162.rv_timer_random/latest |
Test location | /workspace/coverage/default/163.rv_timer_random.2062821882 |
Short name | T175 |
Test name | |
Test status | |
Simulation time | 150931760869 ps |
CPU time | 242.77 seconds |
Started | Aug 08 05:57:59 PM PDT 24 |
Finished | Aug 08 06:02:02 PM PDT 24 |
Peak memory | 191648 kb |
Host | smart-48e27902-3cd7-4a9c-991a-dd4e31778b0c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062821882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2062821882 |
Directory | /workspace/163.rv_timer_random/latest |
Test location | /workspace/coverage/default/164.rv_timer_random.1589740092 |
Short name | T191 |
Test name | |
Test status | |
Simulation time | 211885953936 ps |
CPU time | 99.2 seconds |
Started | Aug 08 05:57:58 PM PDT 24 |
Finished | Aug 08 05:59:37 PM PDT 24 |
Peak memory | 193820 kb |
Host | smart-3415a2eb-14b5-438e-86ff-85ee0704f71b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589740092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1589740092 |
Directory | /workspace/164.rv_timer_random/latest |
Test location | /workspace/coverage/default/166.rv_timer_random.3983403183 |
Short name | T283 |
Test name | |
Test status | |
Simulation time | 40014482142 ps |
CPU time | 74.28 seconds |
Started | Aug 08 05:57:55 PM PDT 24 |
Finished | Aug 08 05:59:10 PM PDT 24 |
Peak memory | 183496 kb |
Host | smart-9ef669c4-5867-4ae7-a219-d0363a577e46 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983403183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3983403183 |
Directory | /workspace/166.rv_timer_random/latest |
Test location | /workspace/coverage/default/167.rv_timer_random.671338735 |
Short name | T432 |
Test name | |
Test status | |
Simulation time | 5722340056 ps |
CPU time | 9.59 seconds |
Started | Aug 08 05:57:57 PM PDT 24 |
Finished | Aug 08 05:58:07 PM PDT 24 |
Peak memory | 183464 kb |
Host | smart-3f93f25c-3ed8-4bb4-9290-7ee1011c4c40 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671338735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.671338735 |
Directory | /workspace/167.rv_timer_random/latest |
Test location | /workspace/coverage/default/168.rv_timer_random.761609410 |
Short name | T266 |
Test name | |
Test status | |
Simulation time | 399540132284 ps |
CPU time | 242.62 seconds |
Started | Aug 08 05:57:59 PM PDT 24 |
Finished | Aug 08 06:02:02 PM PDT 24 |
Peak memory | 191644 kb |
Host | smart-140a8e3d-f724-46a5-8182-54d9ee84b551 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761609410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.761609410 |
Directory | /workspace/168.rv_timer_random/latest |
Test location | /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3472684241 |
Short name | T446 |
Test name | |
Test status | |
Simulation time | 13960136243 ps |
CPU time | 8.1 seconds |
Started | Aug 08 05:55:56 PM PDT 24 |
Finished | Aug 08 05:56:04 PM PDT 24 |
Peak memory | 183476 kb |
Host | smart-a8dcd2de-5f91-4292-b741-4a00218e216f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472684241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.3472684241 |
Directory | /workspace/17.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/17.rv_timer_disabled.3783710338 |
Short name | T398 |
Test name | |
Test status | |
Simulation time | 108066502873 ps |
CPU time | 147.56 seconds |
Started | Aug 08 05:55:54 PM PDT 24 |
Finished | Aug 08 05:58:21 PM PDT 24 |
Peak memory | 183440 kb |
Host | smart-6152b236-391d-4337-9738-6eaf3f6cd4d7 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3783710338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3783710338 |
Directory | /workspace/17.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/17.rv_timer_random.916888568 |
Short name | T151 |
Test name | |
Test status | |
Simulation time | 340614543636 ps |
CPU time | 523.05 seconds |
Started | Aug 08 05:55:56 PM PDT 24 |
Finished | Aug 08 06:04:40 PM PDT 24 |
Peak memory | 191676 kb |
Host | smart-46ba9603-18a1-4208-9560-06b173e1459d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916888568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.916888568 |
Directory | /workspace/17.rv_timer_random/latest |
Test location | /workspace/coverage/default/17.rv_timer_random_reset.122805434 |
Short name | T337 |
Test name | |
Test status | |
Simulation time | 81172936640 ps |
CPU time | 241.09 seconds |
Started | Aug 08 05:55:59 PM PDT 24 |
Finished | Aug 08 06:00:01 PM PDT 24 |
Peak memory | 191620 kb |
Host | smart-84d64833-fd33-4ae2-a887-c0b5a631b0c5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=122805434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.122805434 |
Directory | /workspace/17.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/17.rv_timer_stress_all.2117800087 |
Short name | T128 |
Test name | |
Test status | |
Simulation time | 896130205810 ps |
CPU time | 1351.47 seconds |
Started | Aug 08 05:55:56 PM PDT 24 |
Finished | Aug 08 06:18:28 PM PDT 24 |
Peak memory | 191684 kb |
Host | smart-fbfa88db-1bda-46d2-9fbe-3e3c7f5f1def |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117800087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all .2117800087 |
Directory | /workspace/17.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/170.rv_timer_random.1312014868 |
Short name | T5 |
Test name | |
Test status | |
Simulation time | 24853905934 ps |
CPU time | 62.9 seconds |
Started | Aug 08 05:57:56 PM PDT 24 |
Finished | Aug 08 05:58:59 PM PDT 24 |
Peak memory | 191684 kb |
Host | smart-7bf8d2ff-965b-4b25-a096-bfc72bbb11de |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312014868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1312014868 |
Directory | /workspace/170.rv_timer_random/latest |
Test location | /workspace/coverage/default/171.rv_timer_random.2512655834 |
Short name | T140 |
Test name | |
Test status | |
Simulation time | 289803349705 ps |
CPU time | 446.25 seconds |
Started | Aug 08 05:57:58 PM PDT 24 |
Finished | Aug 08 06:05:24 PM PDT 24 |
Peak memory | 191636 kb |
Host | smart-be0bf541-8a39-46dc-9457-8a7d6835b54d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512655834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2512655834 |
Directory | /workspace/171.rv_timer_random/latest |
Test location | /workspace/coverage/default/172.rv_timer_random.2550873327 |
Short name | T442 |
Test name | |
Test status | |
Simulation time | 483991732852 ps |
CPU time | 159.29 seconds |
Started | Aug 08 05:58:00 PM PDT 24 |
Finished | Aug 08 06:00:40 PM PDT 24 |
Peak memory | 191652 kb |
Host | smart-51abf78b-db61-4d6f-ab07-4f2bf1e6616a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550873327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2550873327 |
Directory | /workspace/172.rv_timer_random/latest |
Test location | /workspace/coverage/default/173.rv_timer_random.1973081544 |
Short name | T289 |
Test name | |
Test status | |
Simulation time | 171380338125 ps |
CPU time | 273.88 seconds |
Started | Aug 08 05:58:03 PM PDT 24 |
Finished | Aug 08 06:02:37 PM PDT 24 |
Peak memory | 191628 kb |
Host | smart-46a6bd2d-e42e-4d3e-8357-291a04cd29c4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973081544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1973081544 |
Directory | /workspace/173.rv_timer_random/latest |
Test location | /workspace/coverage/default/174.rv_timer_random.2896688435 |
Short name | T296 |
Test name | |
Test status | |
Simulation time | 142003539616 ps |
CPU time | 484.09 seconds |
Started | Aug 08 05:58:03 PM PDT 24 |
Finished | Aug 08 06:06:07 PM PDT 24 |
Peak memory | 191612 kb |
Host | smart-5ea33a90-6f13-454b-a750-617de8f4cfcc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896688435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2896688435 |
Directory | /workspace/174.rv_timer_random/latest |
Test location | /workspace/coverage/default/175.rv_timer_random.2283897708 |
Short name | T293 |
Test name | |
Test status | |
Simulation time | 19126637354 ps |
CPU time | 29.36 seconds |
Started | Aug 08 05:58:03 PM PDT 24 |
Finished | Aug 08 05:58:32 PM PDT 24 |
Peak memory | 183456 kb |
Host | smart-a3745c50-42d8-48cd-ba04-20f94891a1d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283897708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2283897708 |
Directory | /workspace/175.rv_timer_random/latest |
Test location | /workspace/coverage/default/176.rv_timer_random.743691581 |
Short name | T99 |
Test name | |
Test status | |
Simulation time | 296400871984 ps |
CPU time | 233.29 seconds |
Started | Aug 08 05:58:04 PM PDT 24 |
Finished | Aug 08 06:01:58 PM PDT 24 |
Peak memory | 191660 kb |
Host | smart-52eea3fd-3f06-401c-b4c0-0723fbcae202 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743691581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.743691581 |
Directory | /workspace/176.rv_timer_random/latest |
Test location | /workspace/coverage/default/177.rv_timer_random.2314616683 |
Short name | T314 |
Test name | |
Test status | |
Simulation time | 25947172211 ps |
CPU time | 218.01 seconds |
Started | Aug 08 05:58:06 PM PDT 24 |
Finished | Aug 08 06:01:44 PM PDT 24 |
Peak memory | 191648 kb |
Host | smart-868d02cc-1bb3-42cc-aee7-660219520b76 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314616683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2314616683 |
Directory | /workspace/177.rv_timer_random/latest |
Test location | /workspace/coverage/default/178.rv_timer_random.4149815158 |
Short name | T434 |
Test name | |
Test status | |
Simulation time | 9726801313 ps |
CPU time | 71.38 seconds |
Started | Aug 08 05:58:02 PM PDT 24 |
Finished | Aug 08 05:59:14 PM PDT 24 |
Peak memory | 183456 kb |
Host | smart-29112406-c960-4eae-b1f6-a5f09c03f8c6 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149815158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.4149815158 |
Directory | /workspace/178.rv_timer_random/latest |
Test location | /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1189660919 |
Short name | T292 |
Test name | |
Test status | |
Simulation time | 285466413322 ps |
CPU time | 263.67 seconds |
Started | Aug 08 05:55:56 PM PDT 24 |
Finished | Aug 08 06:00:20 PM PDT 24 |
Peak memory | 183508 kb |
Host | smart-847eec69-ceaf-4646-83fe-676d4bee80e8 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189660919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.1189660919 |
Directory | /workspace/18.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/18.rv_timer_random.4187601482 |
Short name | T242 |
Test name | |
Test status | |
Simulation time | 179488771443 ps |
CPU time | 186.38 seconds |
Started | Aug 08 05:55:52 PM PDT 24 |
Finished | Aug 08 05:58:58 PM PDT 24 |
Peak memory | 191576 kb |
Host | smart-75cbbbb2-5e60-4042-b135-a5f2782745ec |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187601482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.4187601482 |
Directory | /workspace/18.rv_timer_random/latest |
Test location | /workspace/coverage/default/18.rv_timer_random_reset.3057893941 |
Short name | T154 |
Test name | |
Test status | |
Simulation time | 91753632424 ps |
CPU time | 301.88 seconds |
Started | Aug 08 05:55:56 PM PDT 24 |
Finished | Aug 08 06:00:58 PM PDT 24 |
Peak memory | 191664 kb |
Host | smart-48c4c537-f690-4fbd-9a50-9e7cb0a7648b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3057893941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3057893941 |
Directory | /workspace/18.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/18.rv_timer_stress_all.2635770930 |
Short name | T193 |
Test name | |
Test status | |
Simulation time | 1129731386799 ps |
CPU time | 2632.51 seconds |
Started | Aug 08 05:55:54 PM PDT 24 |
Finished | Aug 08 06:39:47 PM PDT 24 |
Peak memory | 191588 kb |
Host | smart-8904181e-2b9f-4c02-a29f-9eef0ddf7223 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635770930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all .2635770930 |
Directory | /workspace/18.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.1303911497 |
Short name | T40 |
Test name | |
Test status | |
Simulation time | 47478259229 ps |
CPU time | 358.1 seconds |
Started | Aug 08 05:55:58 PM PDT 24 |
Finished | Aug 08 06:01:56 PM PDT 24 |
Peak memory | 198072 kb |
Host | smart-5a4a879a-37c4-406f-87b9-0b7ac3d0746c |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303911497 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.1303911497 |
Directory | /workspace/18.rv_timer_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/182.rv_timer_random.633659234 |
Short name | T441 |
Test name | |
Test status | |
Simulation time | 76537509962 ps |
CPU time | 38.65 seconds |
Started | Aug 08 05:58:11 PM PDT 24 |
Finished | Aug 08 05:58:49 PM PDT 24 |
Peak memory | 183400 kb |
Host | smart-6a85f2b0-7b66-497c-bde2-5ab8ae3fc524 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633659234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.633659234 |
Directory | /workspace/182.rv_timer_random/latest |
Test location | /workspace/coverage/default/184.rv_timer_random.1737914348 |
Short name | T226 |
Test name | |
Test status | |
Simulation time | 515691589919 ps |
CPU time | 1065.11 seconds |
Started | Aug 08 05:58:11 PM PDT 24 |
Finished | Aug 08 06:15:57 PM PDT 24 |
Peak memory | 191584 kb |
Host | smart-7af19cf6-47ac-4c82-a3b3-22ed172cb454 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737914348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1737914348 |
Directory | /workspace/184.rv_timer_random/latest |
Test location | /workspace/coverage/default/186.rv_timer_random.3484639624 |
Short name | T112 |
Test name | |
Test status | |
Simulation time | 129261962604 ps |
CPU time | 283.65 seconds |
Started | Aug 08 05:58:11 PM PDT 24 |
Finished | Aug 08 06:02:54 PM PDT 24 |
Peak memory | 191644 kb |
Host | smart-e4ad712a-bd6f-4b76-8a03-97f67ac5f9f4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484639624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3484639624 |
Directory | /workspace/186.rv_timer_random/latest |
Test location | /workspace/coverage/default/187.rv_timer_random.3592768178 |
Short name | T251 |
Test name | |
Test status | |
Simulation time | 25143544667 ps |
CPU time | 46.72 seconds |
Started | Aug 08 05:58:04 PM PDT 24 |
Finished | Aug 08 05:58:50 PM PDT 24 |
Peak memory | 191676 kb |
Host | smart-c1896d92-232f-480a-8fdd-0970d381d446 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592768178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3592768178 |
Directory | /workspace/187.rv_timer_random/latest |
Test location | /workspace/coverage/default/188.rv_timer_random.615985047 |
Short name | T297 |
Test name | |
Test status | |
Simulation time | 105973632062 ps |
CPU time | 715.23 seconds |
Started | Aug 08 05:58:11 PM PDT 24 |
Finished | Aug 08 06:10:06 PM PDT 24 |
Peak memory | 191712 kb |
Host | smart-73bb4438-2e74-47a9-8f51-28a12008fb74 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615985047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.615985047 |
Directory | /workspace/188.rv_timer_random/latest |
Test location | /workspace/coverage/default/189.rv_timer_random.2255755611 |
Short name | T121 |
Test name | |
Test status | |
Simulation time | 725903781329 ps |
CPU time | 578.03 seconds |
Started | Aug 08 05:58:14 PM PDT 24 |
Finished | Aug 08 06:07:53 PM PDT 24 |
Peak memory | 194984 kb |
Host | smart-f7cb65a7-175b-4c3a-8e11-5511603f8a1a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255755611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2255755611 |
Directory | /workspace/189.rv_timer_random/latest |
Test location | /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.4191171252 |
Short name | T246 |
Test name | |
Test status | |
Simulation time | 45505572151 ps |
CPU time | 21.94 seconds |
Started | Aug 08 05:55:54 PM PDT 24 |
Finished | Aug 08 05:56:16 PM PDT 24 |
Peak memory | 183460 kb |
Host | smart-abffa99f-1259-46a9-bdfd-77f9c28486db |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191171252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.4191171252 |
Directory | /workspace/19.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/19.rv_timer_disabled.257952465 |
Short name | T391 |
Test name | |
Test status | |
Simulation time | 113374548752 ps |
CPU time | 147.74 seconds |
Started | Aug 08 05:55:54 PM PDT 24 |
Finished | Aug 08 05:58:22 PM PDT 24 |
Peak memory | 183456 kb |
Host | smart-79dc5fe1-d90f-4d66-bd6e-f9d2c2cab9a3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=257952465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.257952465 |
Directory | /workspace/19.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/19.rv_timer_random_reset.57644336 |
Short name | T388 |
Test name | |
Test status | |
Simulation time | 342590039 ps |
CPU time | 0.88 seconds |
Started | Aug 08 05:55:56 PM PDT 24 |
Finished | Aug 08 05:55:57 PM PDT 24 |
Peak memory | 191876 kb |
Host | smart-77c8232c-aae2-44f8-8ca0-e995bd82a61f |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=57644336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.57644336 |
Directory | /workspace/19.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/190.rv_timer_random.2070181793 |
Short name | T274 |
Test name | |
Test status | |
Simulation time | 194397240078 ps |
CPU time | 416.22 seconds |
Started | Aug 08 05:58:15 PM PDT 24 |
Finished | Aug 08 06:05:11 PM PDT 24 |
Peak memory | 183396 kb |
Host | smart-4e867cda-64ef-4ad5-a5e6-2b2e424e2dad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070181793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2070181793 |
Directory | /workspace/190.rv_timer_random/latest |
Test location | /workspace/coverage/default/194.rv_timer_random.2327362748 |
Short name | T212 |
Test name | |
Test status | |
Simulation time | 398301230022 ps |
CPU time | 259.68 seconds |
Started | Aug 08 05:58:14 PM PDT 24 |
Finished | Aug 08 06:02:34 PM PDT 24 |
Peak memory | 191604 kb |
Host | smart-b2c3aee1-b409-443b-94f8-2ad4c8ccdb62 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327362748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2327362748 |
Directory | /workspace/194.rv_timer_random/latest |
Test location | /workspace/coverage/default/196.rv_timer_random.3486163446 |
Short name | T342 |
Test name | |
Test status | |
Simulation time | 450551906787 ps |
CPU time | 514.98 seconds |
Started | Aug 08 05:58:22 PM PDT 24 |
Finished | Aug 08 06:06:58 PM PDT 24 |
Peak memory | 191664 kb |
Host | smart-3fc7679e-2123-46f7-a4b1-28689b578d97 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486163446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3486163446 |
Directory | /workspace/196.rv_timer_random/latest |
Test location | /workspace/coverage/default/197.rv_timer_random.1372008298 |
Short name | T152 |
Test name | |
Test status | |
Simulation time | 151557095715 ps |
CPU time | 1107.7 seconds |
Started | Aug 08 05:58:22 PM PDT 24 |
Finished | Aug 08 06:16:50 PM PDT 24 |
Peak memory | 191532 kb |
Host | smart-9eab2cd8-2d78-4eff-96bf-5da3c73b7f5e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372008298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1372008298 |
Directory | /workspace/197.rv_timer_random/latest |
Test location | /workspace/coverage/default/198.rv_timer_random.2670207533 |
Short name | T155 |
Test name | |
Test status | |
Simulation time | 177185748267 ps |
CPU time | 252.65 seconds |
Started | Aug 08 05:58:22 PM PDT 24 |
Finished | Aug 08 06:02:35 PM PDT 24 |
Peak memory | 191656 kb |
Host | smart-11f99d03-f38e-4756-b5cd-5f67b8a06d46 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670207533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2670207533 |
Directory | /workspace/198.rv_timer_random/latest |
Test location | /workspace/coverage/default/199.rv_timer_random.2866538128 |
Short name | T28 |
Test name | |
Test status | |
Simulation time | 153604618074 ps |
CPU time | 184.23 seconds |
Started | Aug 08 05:58:23 PM PDT 24 |
Finished | Aug 08 06:01:28 PM PDT 24 |
Peak memory | 191604 kb |
Host | smart-09dbca26-73c8-46d4-9a9e-1e81e9a839e5 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866538128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2866538128 |
Directory | /workspace/199.rv_timer_random/latest |
Test location | /workspace/coverage/default/2.rv_timer_disabled.3975690786 |
Short name | T98 |
Test name | |
Test status | |
Simulation time | 964780485469 ps |
CPU time | 348.95 seconds |
Started | Aug 08 05:55:38 PM PDT 24 |
Finished | Aug 08 06:01:27 PM PDT 24 |
Peak memory | 183340 kb |
Host | smart-d0fc0b20-883c-4f8e-bc9f-200e9813d788 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3975690786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3975690786 |
Directory | /workspace/2.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/2.rv_timer_random.3151660977 |
Short name | T183 |
Test name | |
Test status | |
Simulation time | 220863030212 ps |
CPU time | 506.42 seconds |
Started | Aug 08 05:55:37 PM PDT 24 |
Finished | Aug 08 06:04:04 PM PDT 24 |
Peak memory | 191868 kb |
Host | smart-3c7f413d-bf57-4ac7-9cd1-8361385606a3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151660977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3151660977 |
Directory | /workspace/2.rv_timer_random/latest |
Test location | /workspace/coverage/default/2.rv_timer_random_reset.3982748894 |
Short name | T11 |
Test name | |
Test status | |
Simulation time | 4222551753 ps |
CPU time | 4.63 seconds |
Started | Aug 08 05:55:40 PM PDT 24 |
Finished | Aug 08 05:55:45 PM PDT 24 |
Peak memory | 191552 kb |
Host | smart-a41dcafd-b244-4cfa-868f-71213d0fa1cf |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3982748894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3982748894 |
Directory | /workspace/2.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/2.rv_timer_sec_cm.476760843 |
Short name | T15 |
Test name | |
Test status | |
Simulation time | 117222150 ps |
CPU time | 0.87 seconds |
Started | Aug 08 05:55:40 PM PDT 24 |
Finished | Aug 08 05:55:41 PM PDT 24 |
Peak memory | 214104 kb |
Host | smart-77e24f68-647c-403a-b394-3dee345d9f8d |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476760843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.476760843 |
Directory | /workspace/2.rv_timer_sec_cm/latest |
Test location | /workspace/coverage/default/2.rv_timer_stress_all.4050124942 |
Short name | T228 |
Test name | |
Test status | |
Simulation time | 759093037906 ps |
CPU time | 1071.29 seconds |
Started | Aug 08 05:55:44 PM PDT 24 |
Finished | Aug 08 06:13:36 PM PDT 24 |
Peak memory | 191536 kb |
Host | smart-8191a355-8d81-4f6f-ae41-4d19d1976e1d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050124942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all. 4050124942 |
Directory | /workspace/2.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2685695107 |
Short name | T450 |
Test name | |
Test status | |
Simulation time | 523751850634 ps |
CPU time | 464.54 seconds |
Started | Aug 08 05:55:55 PM PDT 24 |
Finished | Aug 08 06:03:39 PM PDT 24 |
Peak memory | 183384 kb |
Host | smart-8fb0d6e9-cb43-470a-935b-c0c2eda9865f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685695107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.2685695107 |
Directory | /workspace/20.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/20.rv_timer_disabled.1200512670 |
Short name | T23 |
Test name | |
Test status | |
Simulation time | 947635370178 ps |
CPU time | 263.31 seconds |
Started | Aug 08 05:55:54 PM PDT 24 |
Finished | Aug 08 06:00:18 PM PDT 24 |
Peak memory | 183408 kb |
Host | smart-32439150-02c5-476d-b573-159537bbbc9e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1200512670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1200512670 |
Directory | /workspace/20.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/20.rv_timer_random.2503435712 |
Short name | T347 |
Test name | |
Test status | |
Simulation time | 81052255740 ps |
CPU time | 316.06 seconds |
Started | Aug 08 05:55:53 PM PDT 24 |
Finished | Aug 08 06:01:10 PM PDT 24 |
Peak memory | 191612 kb |
Host | smart-63fb69be-23bb-42a2-b51f-3f0a2b7e5334 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503435712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2503435712 |
Directory | /workspace/20.rv_timer_random/latest |
Test location | /workspace/coverage/default/20.rv_timer_random_reset.3613778025 |
Short name | T133 |
Test name | |
Test status | |
Simulation time | 75003172654 ps |
CPU time | 561.68 seconds |
Started | Aug 08 05:55:54 PM PDT 24 |
Finished | Aug 08 06:05:16 PM PDT 24 |
Peak memory | 193672 kb |
Host | smart-4fccf0c8-4833-44dc-be5e-8ce580aa1b69 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3613778025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3613778025 |
Directory | /workspace/20.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2301002401 |
Short name | T270 |
Test name | |
Test status | |
Simulation time | 397843983216 ps |
CPU time | 677.83 seconds |
Started | Aug 08 05:55:56 PM PDT 24 |
Finished | Aug 08 06:07:14 PM PDT 24 |
Peak memory | 183448 kb |
Host | smart-37325e38-c6a5-4959-9558-871a53a44c4c |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301002401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.2301002401 |
Directory | /workspace/21.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/21.rv_timer_disabled.3826904195 |
Short name | T361 |
Test name | |
Test status | |
Simulation time | 127918444233 ps |
CPU time | 151.72 seconds |
Started | Aug 08 05:55:55 PM PDT 24 |
Finished | Aug 08 05:58:27 PM PDT 24 |
Peak memory | 183452 kb |
Host | smart-134933a2-ef6c-49c9-98a7-25f20f3cee1e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3826904195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3826904195 |
Directory | /workspace/21.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/21.rv_timer_random.269174744 |
Short name | T243 |
Test name | |
Test status | |
Simulation time | 336646509617 ps |
CPU time | 312.6 seconds |
Started | Aug 08 05:55:55 PM PDT 24 |
Finished | Aug 08 06:01:08 PM PDT 24 |
Peak memory | 191660 kb |
Host | smart-b650711a-0a57-4954-8aef-b05b45d69782 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269174744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.269174744 |
Directory | /workspace/21.rv_timer_random/latest |
Test location | /workspace/coverage/default/21.rv_timer_random_reset.2575764243 |
Short name | T51 |
Test name | |
Test status | |
Simulation time | 71479328562 ps |
CPU time | 61.96 seconds |
Started | Aug 08 05:55:56 PM PDT 24 |
Finished | Aug 08 05:56:58 PM PDT 24 |
Peak memory | 191632 kb |
Host | smart-9f08bb4b-defa-4de5-a717-a6bca811ebc6 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2575764243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2575764243 |
Directory | /workspace/21.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.2864260800 |
Short name | T39 |
Test name | |
Test status | |
Simulation time | 17112301027 ps |
CPU time | 126.46 seconds |
Started | Aug 08 05:55:56 PM PDT 24 |
Finished | Aug 08 05:58:03 PM PDT 24 |
Peak memory | 196748 kb |
Host | smart-2bc3dead-26a0-4a0e-a813-5c2f479f7230 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864260800 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.2864260800 |
Directory | /workspace/21.rv_timer_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.524967689 |
Short name | T433 |
Test name | |
Test status | |
Simulation time | 1074236844745 ps |
CPU time | 581.71 seconds |
Started | Aug 08 05:56:05 PM PDT 24 |
Finished | Aug 08 06:05:47 PM PDT 24 |
Peak memory | 183488 kb |
Host | smart-761160c9-4e4a-42a9-8aea-f913c048db53 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524967689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 2.rv_timer_cfg_update_on_fly.524967689 |
Directory | /workspace/22.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/22.rv_timer_disabled.1387145033 |
Short name | T423 |
Test name | |
Test status | |
Simulation time | 79842033419 ps |
CPU time | 18.8 seconds |
Started | Aug 08 05:56:03 PM PDT 24 |
Finished | Aug 08 05:56:22 PM PDT 24 |
Peak memory | 183504 kb |
Host | smart-ae9ca2a0-85ad-49fa-a4b3-01c9e4072fbc |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1387145033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1387145033 |
Directory | /workspace/22.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/22.rv_timer_random.2848012651 |
Short name | T143 |
Test name | |
Test status | |
Simulation time | 473599586186 ps |
CPU time | 2138.32 seconds |
Started | Aug 08 05:56:00 PM PDT 24 |
Finished | Aug 08 06:31:38 PM PDT 24 |
Peak memory | 191620 kb |
Host | smart-363f0875-c2c3-4d6c-9619-dce292ef08f9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848012651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2848012651 |
Directory | /workspace/22.rv_timer_random/latest |
Test location | /workspace/coverage/default/22.rv_timer_random_reset.3398723268 |
Short name | T295 |
Test name | |
Test status | |
Simulation time | 31299468654 ps |
CPU time | 43.62 seconds |
Started | Aug 08 05:56:05 PM PDT 24 |
Finished | Aug 08 05:56:49 PM PDT 24 |
Peak memory | 183432 kb |
Host | smart-1d3445dd-ad06-40b3-9295-069785ef207c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3398723268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3398723268 |
Directory | /workspace/22.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/22.rv_timer_stress_all.3435255361 |
Short name | T301 |
Test name | |
Test status | |
Simulation time | 1646367827559 ps |
CPU time | 1027.9 seconds |
Started | Aug 08 05:56:03 PM PDT 24 |
Finished | Aug 08 06:13:11 PM PDT 24 |
Peak memory | 191748 kb |
Host | smart-e231fa38-c729-4cc2-81c0-e61ae8c25e1c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435255361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all .3435255361 |
Directory | /workspace/22.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2425074883 |
Short name | T204 |
Test name | |
Test status | |
Simulation time | 226019338154 ps |
CPU time | 203.91 seconds |
Started | Aug 08 05:56:03 PM PDT 24 |
Finished | Aug 08 05:59:27 PM PDT 24 |
Peak memory | 183360 kb |
Host | smart-c7186214-0ef2-4c25-a651-12201ec5073b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425074883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.2425074883 |
Directory | /workspace/23.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/23.rv_timer_disabled.140729089 |
Short name | T409 |
Test name | |
Test status | |
Simulation time | 621061799618 ps |
CPU time | 187.02 seconds |
Started | Aug 08 05:56:04 PM PDT 24 |
Finished | Aug 08 05:59:11 PM PDT 24 |
Peak memory | 183472 kb |
Host | smart-60d53bf3-cfb4-4adb-84cb-c65c2bd0d723 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=140729089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.140729089 |
Directory | /workspace/23.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/23.rv_timer_random_reset.1304972688 |
Short name | T413 |
Test name | |
Test status | |
Simulation time | 234963328655 ps |
CPU time | 95.46 seconds |
Started | Aug 08 05:56:03 PM PDT 24 |
Finished | Aug 08 05:57:39 PM PDT 24 |
Peak memory | 194712 kb |
Host | smart-3048b0a5-66c8-4365-905e-fa18ad247a94 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1304972688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1304972688 |
Directory | /workspace/23.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/23.rv_timer_stress_all.2080189131 |
Short name | T60 |
Test name | |
Test status | |
Simulation time | 21495393 ps |
CPU time | 0.54 seconds |
Started | Aug 08 05:56:05 PM PDT 24 |
Finished | Aug 08 05:56:06 PM PDT 24 |
Peak memory | 182788 kb |
Host | smart-bcd05b6d-e521-4649-9437-facc7aecbf8f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080189131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all .2080189131 |
Directory | /workspace/23.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2791910969 |
Short name | T110 |
Test name | |
Test status | |
Simulation time | 247724632951 ps |
CPU time | 375.26 seconds |
Started | Aug 08 05:56:05 PM PDT 24 |
Finished | Aug 08 06:02:20 PM PDT 24 |
Peak memory | 183448 kb |
Host | smart-72941617-8247-41c3-bc99-6c9a3a1ed6eb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791910969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.2791910969 |
Directory | /workspace/24.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/24.rv_timer_disabled.4038016939 |
Short name | T44 |
Test name | |
Test status | |
Simulation time | 459723718704 ps |
CPU time | 303.25 seconds |
Started | Aug 08 05:56:05 PM PDT 24 |
Finished | Aug 08 06:01:09 PM PDT 24 |
Peak memory | 183492 kb |
Host | smart-b1f10459-c1dd-4852-b828-e97d36350157 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4038016939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4038016939 |
Directory | /workspace/24.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/24.rv_timer_random.3505195475 |
Short name | T317 |
Test name | |
Test status | |
Simulation time | 272581745073 ps |
CPU time | 58.88 seconds |
Started | Aug 08 05:56:06 PM PDT 24 |
Finished | Aug 08 05:57:05 PM PDT 24 |
Peak memory | 183364 kb |
Host | smart-d26556ed-81d2-4623-9a32-eb01db199eba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505195475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3505195475 |
Directory | /workspace/24.rv_timer_random/latest |
Test location | /workspace/coverage/default/24.rv_timer_random_reset.614986710 |
Short name | T406 |
Test name | |
Test status | |
Simulation time | 14464040216 ps |
CPU time | 28.91 seconds |
Started | Aug 08 05:56:05 PM PDT 24 |
Finished | Aug 08 05:56:34 PM PDT 24 |
Peak memory | 183424 kb |
Host | smart-ba72630b-6bbf-4d63-89b4-39f157a8c870 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=614986710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.614986710 |
Directory | /workspace/24.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.420764414 |
Short name | T48 |
Test name | |
Test status | |
Simulation time | 386288666530 ps |
CPU time | 325.68 seconds |
Started | Aug 08 05:56:04 PM PDT 24 |
Finished | Aug 08 06:01:29 PM PDT 24 |
Peak memory | 183440 kb |
Host | smart-6ff5c49c-4d05-4958-8702-c1baa44212eb |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420764414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 5.rv_timer_cfg_update_on_fly.420764414 |
Directory | /workspace/25.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/25.rv_timer_disabled.674730629 |
Short name | T368 |
Test name | |
Test status | |
Simulation time | 32344364021 ps |
CPU time | 52.43 seconds |
Started | Aug 08 05:56:04 PM PDT 24 |
Finished | Aug 08 05:56:57 PM PDT 24 |
Peak memory | 183464 kb |
Host | smart-dc1a9e04-fdcb-4fc7-9812-f3ef19a0e8d0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=674730629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.674730629 |
Directory | /workspace/25.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/25.rv_timer_random.2809234459 |
Short name | T170 |
Test name | |
Test status | |
Simulation time | 355464838427 ps |
CPU time | 591.51 seconds |
Started | Aug 08 05:56:04 PM PDT 24 |
Finished | Aug 08 06:05:56 PM PDT 24 |
Peak memory | 191600 kb |
Host | smart-d62262d9-957b-4b1a-b075-244fbeb37e02 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809234459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2809234459 |
Directory | /workspace/25.rv_timer_random/latest |
Test location | /workspace/coverage/default/25.rv_timer_random_reset.2597421652 |
Short name | T67 |
Test name | |
Test status | |
Simulation time | 15173197620 ps |
CPU time | 10.03 seconds |
Started | Aug 08 05:56:02 PM PDT 24 |
Finished | Aug 08 05:56:12 PM PDT 24 |
Peak memory | 183328 kb |
Host | smart-fc109240-5b3f-495e-9c2c-87fb9da9afd2 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2597421652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2597421652 |
Directory | /workspace/25.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.334639388 |
Short name | T41 |
Test name | |
Test status | |
Simulation time | 96830725423 ps |
CPU time | 528.56 seconds |
Started | Aug 08 05:56:04 PM PDT 24 |
Finished | Aug 08 06:04:53 PM PDT 24 |
Peak memory | 198004 kb |
Host | smart-81202de9-14f0-4680-913b-22b962c81ac4 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334639388 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.334639388 |
Directory | /workspace/25.rv_timer_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.656999736 |
Short name | T397 |
Test name | |
Test status | |
Simulation time | 5405941451 ps |
CPU time | 9.28 seconds |
Started | Aug 08 05:56:03 PM PDT 24 |
Finished | Aug 08 05:56:13 PM PDT 24 |
Peak memory | 183432 kb |
Host | smart-7a071392-4f8f-41c8-a076-a3eac2600487 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656999736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 6.rv_timer_cfg_update_on_fly.656999736 |
Directory | /workspace/26.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/26.rv_timer_disabled.455748336 |
Short name | T374 |
Test name | |
Test status | |
Simulation time | 201696347885 ps |
CPU time | 287.65 seconds |
Started | Aug 08 05:56:04 PM PDT 24 |
Finished | Aug 08 06:00:52 PM PDT 24 |
Peak memory | 183520 kb |
Host | smart-3f4d174f-9158-4b1a-bcea-92810cd7b7d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=455748336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.455748336 |
Directory | /workspace/26.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/26.rv_timer_random.935295453 |
Short name | T159 |
Test name | |
Test status | |
Simulation time | 793252603679 ps |
CPU time | 259.79 seconds |
Started | Aug 08 05:56:07 PM PDT 24 |
Finished | Aug 08 06:00:27 PM PDT 24 |
Peak memory | 191560 kb |
Host | smart-692c27d9-1fea-4e7a-aa06-8028ae69ecd3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935295453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.935295453 |
Directory | /workspace/26.rv_timer_random/latest |
Test location | /workspace/coverage/default/26.rv_timer_random_reset.1140188110 |
Short name | T186 |
Test name | |
Test status | |
Simulation time | 98373661475 ps |
CPU time | 29.41 seconds |
Started | Aug 08 05:56:06 PM PDT 24 |
Finished | Aug 08 05:56:36 PM PDT 24 |
Peak memory | 183496 kb |
Host | smart-d1f50b72-4bc2-4c7f-94eb-b77034707955 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1140188110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1140188110 |
Directory | /workspace/26.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/26.rv_timer_stress_all.502066621 |
Short name | T174 |
Test name | |
Test status | |
Simulation time | 408544154348 ps |
CPU time | 726.57 seconds |
Started | Aug 08 05:56:04 PM PDT 24 |
Finished | Aug 08 06:08:11 PM PDT 24 |
Peak memory | 196212 kb |
Host | smart-cd7e86b6-2292-41cc-a810-080a4ff109d3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502066621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all. 502066621 |
Directory | /workspace/26.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3386538569 |
Short name | T302 |
Test name | |
Test status | |
Simulation time | 1028749191905 ps |
CPU time | 379.07 seconds |
Started | Aug 08 05:56:05 PM PDT 24 |
Finished | Aug 08 06:02:25 PM PDT 24 |
Peak memory | 183420 kb |
Host | smart-cc67b80f-d9d2-4161-996a-d0a5d52c1f24 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386538569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.3386538569 |
Directory | /workspace/27.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/27.rv_timer_disabled.3921326253 |
Short name | T407 |
Test name | |
Test status | |
Simulation time | 182829768108 ps |
CPU time | 67.4 seconds |
Started | Aug 08 05:56:05 PM PDT 24 |
Finished | Aug 08 05:57:13 PM PDT 24 |
Peak memory | 183324 kb |
Host | smart-4847c66d-c294-4227-a2e3-2ecc6c243b6a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3921326253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3921326253 |
Directory | /workspace/27.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/27.rv_timer_random_reset.1080048803 |
Short name | T276 |
Test name | |
Test status | |
Simulation time | 41594306702 ps |
CPU time | 80.23 seconds |
Started | Aug 08 05:56:06 PM PDT 24 |
Finished | Aug 08 05:57:26 PM PDT 24 |
Peak memory | 183436 kb |
Host | smart-b0783205-4066-4748-a412-61be8cdbeba9 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1080048803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1080048803 |
Directory | /workspace/27.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/27.rv_timer_stress_all.3890052121 |
Short name | T24 |
Test name | |
Test status | |
Simulation time | 97095691471 ps |
CPU time | 72.5 seconds |
Started | Aug 08 05:56:04 PM PDT 24 |
Finished | Aug 08 05:57:17 PM PDT 24 |
Peak memory | 183376 kb |
Host | smart-986bc6ad-7cbd-42cc-8f2b-2b2655f7520d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890052121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all .3890052121 |
Directory | /workspace/27.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.3864166874 |
Short name | T37 |
Test name | |
Test status | |
Simulation time | 99779417504 ps |
CPU time | 267.97 seconds |
Started | Aug 08 05:56:06 PM PDT 24 |
Finished | Aug 08 06:00:34 PM PDT 24 |
Peak memory | 206316 kb |
Host | smart-6cd99d73-5593-416f-a458-ce9332493dc5 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864166874 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.3864166874 |
Directory | /workspace/27.rv_timer_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1078832145 |
Short name | T66 |
Test name | |
Test status | |
Simulation time | 475347916594 ps |
CPU time | 788.57 seconds |
Started | Aug 08 05:56:07 PM PDT 24 |
Finished | Aug 08 06:09:16 PM PDT 24 |
Peak memory | 183304 kb |
Host | smart-bf8bdaae-9da1-43a6-8050-07b48ff2ac36 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078832145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.1078832145 |
Directory | /workspace/28.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/28.rv_timer_disabled.1816087057 |
Short name | T371 |
Test name | |
Test status | |
Simulation time | 402761064669 ps |
CPU time | 176.2 seconds |
Started | Aug 08 05:56:06 PM PDT 24 |
Finished | Aug 08 05:59:02 PM PDT 24 |
Peak memory | 183496 kb |
Host | smart-f8637639-f50c-42d1-bf9c-df2c81660d55 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1816087057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1816087057 |
Directory | /workspace/28.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/28.rv_timer_random.2864069009 |
Short name | T333 |
Test name | |
Test status | |
Simulation time | 367780013723 ps |
CPU time | 543.71 seconds |
Started | Aug 08 05:56:04 PM PDT 24 |
Finished | Aug 08 06:05:07 PM PDT 24 |
Peak memory | 191668 kb |
Host | smart-cb6e7209-f20f-470c-bf87-3d820740a5e4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864069009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2864069009 |
Directory | /workspace/28.rv_timer_random/latest |
Test location | /workspace/coverage/default/28.rv_timer_random_reset.4180814583 |
Short name | T185 |
Test name | |
Test status | |
Simulation time | 77738613612 ps |
CPU time | 89.45 seconds |
Started | Aug 08 05:56:05 PM PDT 24 |
Finished | Aug 08 05:57:35 PM PDT 24 |
Peak memory | 195276 kb |
Host | smart-c944f07d-4165-46f7-b04e-6897a681514e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4180814583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.4180814583 |
Directory | /workspace/28.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/28.rv_timer_stress_all.3927062888 |
Short name | T436 |
Test name | |
Test status | |
Simulation time | 142171347149 ps |
CPU time | 183.52 seconds |
Started | Aug 08 05:56:04 PM PDT 24 |
Finished | Aug 08 05:59:08 PM PDT 24 |
Peak memory | 194288 kb |
Host | smart-f2105882-05f8-412f-b4f6-08fcd34d72d9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927062888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all .3927062888 |
Directory | /workspace/28.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3570093299 |
Short name | T354 |
Test name | |
Test status | |
Simulation time | 229649925352 ps |
CPU time | 113.89 seconds |
Started | Aug 08 05:56:14 PM PDT 24 |
Finished | Aug 08 05:58:08 PM PDT 24 |
Peak memory | 183420 kb |
Host | smart-8a7cf84f-48f9-43d8-a9dc-b2eb5bae5a60 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570093299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.3570093299 |
Directory | /workspace/29.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/29.rv_timer_disabled.10913419 |
Short name | T431 |
Test name | |
Test status | |
Simulation time | 160613625742 ps |
CPU time | 244.53 seconds |
Started | Aug 08 05:56:05 PM PDT 24 |
Finished | Aug 08 06:00:09 PM PDT 24 |
Peak memory | 183480 kb |
Host | smart-b3b2711d-c33e-4b77-995f-9241f8039719 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=10913419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.10913419 |
Directory | /workspace/29.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/29.rv_timer_random.3791024249 |
Short name | T389 |
Test name | |
Test status | |
Simulation time | 10174191709 ps |
CPU time | 13.5 seconds |
Started | Aug 08 05:56:05 PM PDT 24 |
Finished | Aug 08 05:56:18 PM PDT 24 |
Peak memory | 183400 kb |
Host | smart-dbe3c926-cf4f-4711-b4c5-be6caffca221 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791024249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3791024249 |
Directory | /workspace/29.rv_timer_random/latest |
Test location | /workspace/coverage/default/29.rv_timer_random_reset.2214786190 |
Short name | T273 |
Test name | |
Test status | |
Simulation time | 54069029397 ps |
CPU time | 94.01 seconds |
Started | Aug 08 05:56:13 PM PDT 24 |
Finished | Aug 08 05:57:47 PM PDT 24 |
Peak memory | 183452 kb |
Host | smart-ac2c34e2-b5da-4a53-832f-36e0b1e64f32 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2214786190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2214786190 |
Directory | /workspace/29.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3381932480 |
Short name | T111 |
Test name | |
Test status | |
Simulation time | 846827907974 ps |
CPU time | 437.3 seconds |
Started | Aug 08 05:55:37 PM PDT 24 |
Finished | Aug 08 06:02:55 PM PDT 24 |
Peak memory | 183456 kb |
Host | smart-dfe9007d-e70b-4214-b157-91e931e1f659 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381932480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.3381932480 |
Directory | /workspace/3.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/3.rv_timer_disabled.768664302 |
Short name | T372 |
Test name | |
Test status | |
Simulation time | 102879315634 ps |
CPU time | 126.7 seconds |
Started | Aug 08 05:55:38 PM PDT 24 |
Finished | Aug 08 05:57:45 PM PDT 24 |
Peak memory | 183488 kb |
Host | smart-1b167dc5-e9c5-45e9-ae33-0252b30337fb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=768664302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.768664302 |
Directory | /workspace/3.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/3.rv_timer_random.560860681 |
Short name | T318 |
Test name | |
Test status | |
Simulation time | 448832993383 ps |
CPU time | 574.6 seconds |
Started | Aug 08 05:55:38 PM PDT 24 |
Finished | Aug 08 06:05:13 PM PDT 24 |
Peak memory | 191660 kb |
Host | smart-fccef4f6-4873-4063-9d5e-7f0ab3536f89 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560860681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.560860681 |
Directory | /workspace/3.rv_timer_random/latest |
Test location | /workspace/coverage/default/3.rv_timer_random_reset.1754805246 |
Short name | T265 |
Test name | |
Test status | |
Simulation time | 99620708986 ps |
CPU time | 306.18 seconds |
Started | Aug 08 05:55:37 PM PDT 24 |
Finished | Aug 08 06:00:44 PM PDT 24 |
Peak memory | 183472 kb |
Host | smart-72e69a4a-f7af-4875-9b75-e3f05df3a20c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1754805246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1754805246 |
Directory | /workspace/3.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/3.rv_timer_sec_cm.3885595226 |
Short name | T18 |
Test name | |
Test status | |
Simulation time | 400936259 ps |
CPU time | 0.82 seconds |
Started | Aug 08 05:55:44 PM PDT 24 |
Finished | Aug 08 05:55:45 PM PDT 24 |
Peak memory | 213936 kb |
Host | smart-65ba393b-5e47-42c2-b96e-d71f6c907baa |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885595226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3885595226 |
Directory | /workspace/3.rv_timer_sec_cm/latest |
Test location | /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.3985109597 |
Short name | T38 |
Test name | |
Test status | |
Simulation time | 13605017974 ps |
CPU time | 87.58 seconds |
Started | Aug 08 05:55:41 PM PDT 24 |
Finished | Aug 08 05:57:08 PM PDT 24 |
Peak memory | 198108 kb |
Host | smart-01c23ea7-ec68-499f-8367-42b3a6f3281f |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985109597 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.3985109597 |
Directory | /workspace/3.rv_timer_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2422211367 |
Short name | T114 |
Test name | |
Test status | |
Simulation time | 1025936025271 ps |
CPU time | 431.82 seconds |
Started | Aug 08 05:56:11 PM PDT 24 |
Finished | Aug 08 06:03:23 PM PDT 24 |
Peak memory | 183344 kb |
Host | smart-e5c64abc-0d41-4add-8a5b-f97e8022b7e0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422211367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.2422211367 |
Directory | /workspace/30.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/30.rv_timer_disabled.3645468681 |
Short name | T384 |
Test name | |
Test status | |
Simulation time | 96293252071 ps |
CPU time | 14.95 seconds |
Started | Aug 08 05:56:16 PM PDT 24 |
Finished | Aug 08 05:56:31 PM PDT 24 |
Peak memory | 183432 kb |
Host | smart-118ae4c3-49d2-49bb-b8a3-e68ef75e97b8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3645468681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3645468681 |
Directory | /workspace/30.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/30.rv_timer_random.3275010788 |
Short name | T95 |
Test name | |
Test status | |
Simulation time | 78718337102 ps |
CPU time | 262.33 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 06:00:38 PM PDT 24 |
Peak memory | 191656 kb |
Host | smart-1a52444f-9d4c-4f71-b990-d2e8a7ee85b7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275010788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3275010788 |
Directory | /workspace/30.rv_timer_random/latest |
Test location | /workspace/coverage/default/30.rv_timer_random_reset.1052138657 |
Short name | T218 |
Test name | |
Test status | |
Simulation time | 255217096192 ps |
CPU time | 84.4 seconds |
Started | Aug 08 05:56:13 PM PDT 24 |
Finished | Aug 08 05:57:37 PM PDT 24 |
Peak memory | 191712 kb |
Host | smart-94aa79da-805f-4de9-b3f2-ca24ccd489c4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1052138657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1052138657 |
Directory | /workspace/30.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2562877533 |
Short name | T194 |
Test name | |
Test status | |
Simulation time | 83346594655 ps |
CPU time | 141.29 seconds |
Started | Aug 08 05:56:13 PM PDT 24 |
Finished | Aug 08 05:58:35 PM PDT 24 |
Peak memory | 183476 kb |
Host | smart-a9851b3d-7e7d-4d1d-a169-810880906981 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562877533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.2562877533 |
Directory | /workspace/31.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/31.rv_timer_disabled.3130541870 |
Short name | T370 |
Test name | |
Test status | |
Simulation time | 128068903254 ps |
CPU time | 52.12 seconds |
Started | Aug 08 05:56:14 PM PDT 24 |
Finished | Aug 08 05:57:06 PM PDT 24 |
Peak memory | 183480 kb |
Host | smart-7f623e6b-9cb6-4973-b657-ff72a4329d68 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130541870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3130541870 |
Directory | /workspace/31.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/31.rv_timer_random_reset.1408803735 |
Short name | T449 |
Test name | |
Test status | |
Simulation time | 34965357369 ps |
CPU time | 6.55 seconds |
Started | Aug 08 05:56:13 PM PDT 24 |
Finished | Aug 08 05:56:19 PM PDT 24 |
Peak memory | 183436 kb |
Host | smart-36aa22fe-0913-4a64-850b-de9c3a56f1ff |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1408803735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1408803735 |
Directory | /workspace/31.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1178606035 |
Short name | T213 |
Test name | |
Test status | |
Simulation time | 188181549919 ps |
CPU time | 57.62 seconds |
Started | Aug 08 05:56:14 PM PDT 24 |
Finished | Aug 08 05:57:12 PM PDT 24 |
Peak memory | 183364 kb |
Host | smart-a6542098-bb49-425f-ad2f-ca54b6342cd7 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178606035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.1178606035 |
Directory | /workspace/32.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/32.rv_timer_disabled.4112327126 |
Short name | T362 |
Test name | |
Test status | |
Simulation time | 234965277364 ps |
CPU time | 156.49 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 05:58:52 PM PDT 24 |
Peak memory | 183452 kb |
Host | smart-8bf2d09f-7e72-4ec0-9156-0ca1be41f84a |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4112327126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.4112327126 |
Directory | /workspace/32.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/32.rv_timer_random.2856392031 |
Short name | T440 |
Test name | |
Test status | |
Simulation time | 244609550250 ps |
CPU time | 1995.72 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 06:29:31 PM PDT 24 |
Peak memory | 191656 kb |
Host | smart-541d0378-2a8a-4a2d-ba6a-a58f28d8076a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856392031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2856392031 |
Directory | /workspace/32.rv_timer_random/latest |
Test location | /workspace/coverage/default/32.rv_timer_random_reset.3309075049 |
Short name | T363 |
Test name | |
Test status | |
Simulation time | 78330694 ps |
CPU time | 0.56 seconds |
Started | Aug 08 05:56:16 PM PDT 24 |
Finished | Aug 08 05:56:16 PM PDT 24 |
Peak memory | 183220 kb |
Host | smart-9fb60c8f-bf4d-4a2b-84cb-6c4be386abd0 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3309075049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3309075049 |
Directory | /workspace/32.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1323838617 |
Short name | T257 |
Test name | |
Test status | |
Simulation time | 176983449947 ps |
CPU time | 230.26 seconds |
Started | Aug 08 05:56:12 PM PDT 24 |
Finished | Aug 08 06:00:03 PM PDT 24 |
Peak memory | 183544 kb |
Host | smart-5bb32b92-9027-4011-9f0a-38fd023788f0 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323838617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.1323838617 |
Directory | /workspace/33.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/33.rv_timer_disabled.2661197684 |
Short name | T47 |
Test name | |
Test status | |
Simulation time | 58675461399 ps |
CPU time | 88.08 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 05:57:43 PM PDT 24 |
Peak memory | 183500 kb |
Host | smart-b023f774-d04b-445b-8e2a-82bc9df070d3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2661197684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2661197684 |
Directory | /workspace/33.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/33.rv_timer_random_reset.391969209 |
Short name | T369 |
Test name | |
Test status | |
Simulation time | 169490503 ps |
CPU time | 0.69 seconds |
Started | Aug 08 05:56:12 PM PDT 24 |
Finished | Aug 08 05:56:13 PM PDT 24 |
Peak memory | 191656 kb |
Host | smart-1ec5b91d-011f-4e26-b529-959eebffbbbd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=391969209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.391969209 |
Directory | /workspace/33.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1331472869 |
Short name | T422 |
Test name | |
Test status | |
Simulation time | 1303768062008 ps |
CPU time | 378.06 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 06:02:34 PM PDT 24 |
Peak memory | 183364 kb |
Host | smart-ffdd3610-b463-4681-8005-c3b15c0ed6dd |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331472869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.1331472869 |
Directory | /workspace/34.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/34.rv_timer_disabled.2012455614 |
Short name | T380 |
Test name | |
Test status | |
Simulation time | 96434629146 ps |
CPU time | 90.59 seconds |
Started | Aug 08 05:56:13 PM PDT 24 |
Finished | Aug 08 05:57:44 PM PDT 24 |
Peak memory | 183500 kb |
Host | smart-ded5e33a-1c6e-4294-9c0a-8442b409022b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2012455614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2012455614 |
Directory | /workspace/34.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/34.rv_timer_random.1444075569 |
Short name | T249 |
Test name | |
Test status | |
Simulation time | 41223632945 ps |
CPU time | 264.61 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 06:00:40 PM PDT 24 |
Peak memory | 191592 kb |
Host | smart-013ea087-6c38-4008-b24c-5f1d7232f182 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444075569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1444075569 |
Directory | /workspace/34.rv_timer_random/latest |
Test location | /workspace/coverage/default/34.rv_timer_stress_all.1288420168 |
Short name | T124 |
Test name | |
Test status | |
Simulation time | 143695289230 ps |
CPU time | 2037.23 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 06:30:13 PM PDT 24 |
Peak memory | 191656 kb |
Host | smart-9856a6f3-f535-4a66-a63b-4615237d8299 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288420168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all .1288420168 |
Directory | /workspace/34.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2749845418 |
Short name | T438 |
Test name | |
Test status | |
Simulation time | 5244040013229 ps |
CPU time | 1115.19 seconds |
Started | Aug 08 05:56:14 PM PDT 24 |
Finished | Aug 08 06:14:49 PM PDT 24 |
Peak memory | 183408 kb |
Host | smart-8293f84b-ac14-42f8-aa9b-d7b0fef96a39 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749845418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.2749845418 |
Directory | /workspace/35.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/35.rv_timer_disabled.1077154171 |
Short name | T356 |
Test name | |
Test status | |
Simulation time | 315196248557 ps |
CPU time | 201.08 seconds |
Started | Aug 08 05:56:12 PM PDT 24 |
Finished | Aug 08 05:59:34 PM PDT 24 |
Peak memory | 183404 kb |
Host | smart-d684dff6-1492-4077-bb66-b288dc2d55f1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1077154171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1077154171 |
Directory | /workspace/35.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/35.rv_timer_random.1209085131 |
Short name | T311 |
Test name | |
Test status | |
Simulation time | 472700063936 ps |
CPU time | 216.33 seconds |
Started | Aug 08 05:56:16 PM PDT 24 |
Finished | Aug 08 05:59:52 PM PDT 24 |
Peak memory | 193396 kb |
Host | smart-d5ac605f-5a5a-4226-b2f5-41c3177595a7 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209085131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1209085131 |
Directory | /workspace/35.rv_timer_random/latest |
Test location | /workspace/coverage/default/35.rv_timer_random_reset.4212309947 |
Short name | T416 |
Test name | |
Test status | |
Simulation time | 80148232006 ps |
CPU time | 177.76 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 05:59:13 PM PDT 24 |
Peak memory | 183400 kb |
Host | smart-6e30448d-7a77-4c9f-9121-e272be9d5bce |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4212309947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4212309947 |
Directory | /workspace/35.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/35.rv_timer_stress_all.765055120 |
Short name | T120 |
Test name | |
Test status | |
Simulation time | 1330188960528 ps |
CPU time | 692.67 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 06:07:48 PM PDT 24 |
Peak memory | 191720 kb |
Host | smart-12cbf3c8-3a73-4d8a-ac05-543950a07c27 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765055120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress _all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all. 765055120 |
Directory | /workspace/35.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1918268804 |
Short name | T172 |
Test name | |
Test status | |
Simulation time | 27564269604 ps |
CPU time | 24.69 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 05:56:40 PM PDT 24 |
Peak memory | 183340 kb |
Host | smart-a5035aa9-5a3b-4b15-aeac-3fbd47a6e289 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918268804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.1918268804 |
Directory | /workspace/36.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/36.rv_timer_disabled.4118070367 |
Short name | T358 |
Test name | |
Test status | |
Simulation time | 89739933793 ps |
CPU time | 72.42 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 05:57:27 PM PDT 24 |
Peak memory | 183496 kb |
Host | smart-a047fc14-8123-4c66-9f69-fed014ee227e |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4118070367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.4118070367 |
Directory | /workspace/36.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/36.rv_timer_random.183865467 |
Short name | T255 |
Test name | |
Test status | |
Simulation time | 249927743989 ps |
CPU time | 531.38 seconds |
Started | Aug 08 05:56:14 PM PDT 24 |
Finished | Aug 08 06:05:06 PM PDT 24 |
Peak memory | 191624 kb |
Host | smart-77517c33-c2f7-474f-97d4-4d29cdc63659 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183865467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.183865467 |
Directory | /workspace/36.rv_timer_random/latest |
Test location | /workspace/coverage/default/36.rv_timer_random_reset.1600471763 |
Short name | T180 |
Test name | |
Test status | |
Simulation time | 20758418966 ps |
CPU time | 34.83 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 05:56:50 PM PDT 24 |
Peak memory | 195244 kb |
Host | smart-6db977e2-d613-4781-bfec-719e036f125c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1600471763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1600471763 |
Directory | /workspace/36.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/36.rv_timer_stress_all.4115529590 |
Short name | T367 |
Test name | |
Test status | |
Simulation time | 544365982127 ps |
CPU time | 377.07 seconds |
Started | Aug 08 05:56:12 PM PDT 24 |
Finished | Aug 08 06:02:29 PM PDT 24 |
Peak memory | 195132 kb |
Host | smart-b459fc45-c2e6-4912-9c0d-0ee86a62199c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115529590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all .4115529590 |
Directory | /workspace/36.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/37.rv_timer_disabled.3344789686 |
Short name | T365 |
Test name | |
Test status | |
Simulation time | 146123303329 ps |
CPU time | 215.72 seconds |
Started | Aug 08 05:56:15 PM PDT 24 |
Finished | Aug 08 05:59:51 PM PDT 24 |
Peak memory | 183388 kb |
Host | smart-8f2ac3d7-4cf5-4a96-91e6-95a6a1d94a7d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3344789686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3344789686 |
Directory | /workspace/37.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/37.rv_timer_random_reset.2384851494 |
Short name | T4 |
Test name | |
Test status | |
Simulation time | 66179132489 ps |
CPU time | 485.58 seconds |
Started | Aug 08 05:56:16 PM PDT 24 |
Finished | Aug 08 06:04:21 PM PDT 24 |
Peak memory | 191688 kb |
Host | smart-1f3fbe8b-b621-489d-896a-7d7d17b3c478 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2384851494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2384851494 |
Directory | /workspace/37.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1297710953 |
Short name | T25 |
Test name | |
Test status | |
Simulation time | 164004143619 ps |
CPU time | 141.19 seconds |
Started | Aug 08 05:56:13 PM PDT 24 |
Finished | Aug 08 05:58:34 PM PDT 24 |
Peak memory | 183448 kb |
Host | smart-7efe897d-9767-4831-8fba-311fd4bddeae |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297710953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.1297710953 |
Directory | /workspace/38.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/38.rv_timer_disabled.3740136922 |
Short name | T404 |
Test name | |
Test status | |
Simulation time | 267646749179 ps |
CPU time | 197.13 seconds |
Started | Aug 08 05:56:13 PM PDT 24 |
Finished | Aug 08 05:59:30 PM PDT 24 |
Peak memory | 183472 kb |
Host | smart-15de7ee4-0d3a-4786-a57a-4797425216cd |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3740136922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3740136922 |
Directory | /workspace/38.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/38.rv_timer_random.2980031459 |
Short name | T177 |
Test name | |
Test status | |
Simulation time | 552077577391 ps |
CPU time | 1315.46 seconds |
Started | Aug 08 05:56:14 PM PDT 24 |
Finished | Aug 08 06:18:09 PM PDT 24 |
Peak memory | 191672 kb |
Host | smart-830b17c5-bd1d-47e0-bea0-ffb94fc1e394 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980031459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2980031459 |
Directory | /workspace/38.rv_timer_random/latest |
Test location | /workspace/coverage/default/38.rv_timer_random_reset.1038005396 |
Short name | T439 |
Test name | |
Test status | |
Simulation time | 188543848880 ps |
CPU time | 83.49 seconds |
Started | Aug 08 05:56:13 PM PDT 24 |
Finished | Aug 08 05:57:37 PM PDT 24 |
Peak memory | 195260 kb |
Host | smart-67edef3c-5229-4bf7-9c8f-6f0933f44852 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1038005396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1038005396 |
Directory | /workspace/38.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/38.rv_timer_stress_all.1104915124 |
Short name | T355 |
Test name | |
Test status | |
Simulation time | 97236882979 ps |
CPU time | 40.91 seconds |
Started | Aug 08 05:56:24 PM PDT 24 |
Finished | Aug 08 05:57:05 PM PDT 24 |
Peak memory | 183456 kb |
Host | smart-4f8a9411-97c0-4af5-ac4a-f1590af348dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104915124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all .1104915124 |
Directory | /workspace/38.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3652035337 |
Short name | T117 |
Test name | |
Test status | |
Simulation time | 405922191679 ps |
CPU time | 175.6 seconds |
Started | Aug 08 05:56:23 PM PDT 24 |
Finished | Aug 08 05:59:19 PM PDT 24 |
Peak memory | 183404 kb |
Host | smart-03819b0c-76fd-47ec-80fb-a2e66facc2c1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652035337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.3652035337 |
Directory | /workspace/39.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/39.rv_timer_disabled.2758639889 |
Short name | T386 |
Test name | |
Test status | |
Simulation time | 136241465692 ps |
CPU time | 104.51 seconds |
Started | Aug 08 05:56:22 PM PDT 24 |
Finished | Aug 08 05:58:07 PM PDT 24 |
Peak memory | 183412 kb |
Host | smart-b851819f-eec5-4524-9658-3286bca465e5 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2758639889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2758639889 |
Directory | /workspace/39.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/39.rv_timer_random.1161390861 |
Short name | T216 |
Test name | |
Test status | |
Simulation time | 75913982067 ps |
CPU time | 148.44 seconds |
Started | Aug 08 05:56:21 PM PDT 24 |
Finished | Aug 08 05:58:50 PM PDT 24 |
Peak memory | 183420 kb |
Host | smart-47c77942-0c64-444d-80d7-d89163a9e559 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161390861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1161390861 |
Directory | /workspace/39.rv_timer_random/latest |
Test location | /workspace/coverage/default/39.rv_timer_random_reset.39090724 |
Short name | T353 |
Test name | |
Test status | |
Simulation time | 46073478431 ps |
CPU time | 52.23 seconds |
Started | Aug 08 05:56:26 PM PDT 24 |
Finished | Aug 08 05:57:18 PM PDT 24 |
Peak memory | 183412 kb |
Host | smart-1d4b6404-3e4f-47a0-9716-4d75342b7ffa |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=39090724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.39090724 |
Directory | /workspace/39.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/39.rv_timer_stress_all.2756757970 |
Short name | T58 |
Test name | |
Test status | |
Simulation time | 552261953194 ps |
CPU time | 1172.58 seconds |
Started | Aug 08 05:56:22 PM PDT 24 |
Finished | Aug 08 06:15:55 PM PDT 24 |
Peak memory | 196480 kb |
Host | smart-3240d6f5-ee99-49d4-9686-422998999a11 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756757970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all .2756757970 |
Directory | /workspace/39.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2773267271 |
Short name | T385 |
Test name | |
Test status | |
Simulation time | 1453489180023 ps |
CPU time | 770.09 seconds |
Started | Aug 08 05:55:37 PM PDT 24 |
Finished | Aug 08 06:08:28 PM PDT 24 |
Peak memory | 183468 kb |
Host | smart-695dc6cc-844b-485d-83da-1fd09407d153 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773267271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.2773267271 |
Directory | /workspace/4.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/4.rv_timer_disabled.519852526 |
Short name | T379 |
Test name | |
Test status | |
Simulation time | 42595288422 ps |
CPU time | 63.52 seconds |
Started | Aug 08 05:55:38 PM PDT 24 |
Finished | Aug 08 05:56:41 PM PDT 24 |
Peak memory | 183496 kb |
Host | smart-c5f388a5-24b4-45f4-bfb7-3946b59b3403 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=519852526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.519852526 |
Directory | /workspace/4.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/4.rv_timer_sec_cm.1772961440 |
Short name | T17 |
Test name | |
Test status | |
Simulation time | 130856864 ps |
CPU time | 0.74 seconds |
Started | Aug 08 05:55:37 PM PDT 24 |
Finished | Aug 08 05:55:38 PM PDT 24 |
Peak memory | 213924 kb |
Host | smart-62463a64-85ff-402e-b044-09814ceacec6 |
User | root |
Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772961440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1772961440 |
Directory | /workspace/4.rv_timer_sec_cm/latest |
Test location | /workspace/coverage/default/40.rv_timer_disabled.1391743094 |
Short name | T443 |
Test name | |
Test status | |
Simulation time | 946333370180 ps |
CPU time | 243.94 seconds |
Started | Aug 08 05:56:22 PM PDT 24 |
Finished | Aug 08 06:00:26 PM PDT 24 |
Peak memory | 183408 kb |
Host | smart-646e75c5-a01f-49c4-a7ea-ed1c140a6d3b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1391743094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1391743094 |
Directory | /workspace/40.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/40.rv_timer_random.3490798229 |
Short name | T310 |
Test name | |
Test status | |
Simulation time | 771613852580 ps |
CPU time | 594.74 seconds |
Started | Aug 08 05:56:24 PM PDT 24 |
Finished | Aug 08 06:06:19 PM PDT 24 |
Peak memory | 193920 kb |
Host | smart-2972fbd5-a13a-4a86-9ac9-7404fb269ad3 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490798229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3490798229 |
Directory | /workspace/40.rv_timer_random/latest |
Test location | /workspace/coverage/default/40.rv_timer_random_reset.3363817293 |
Short name | T189 |
Test name | |
Test status | |
Simulation time | 722995447954 ps |
CPU time | 175.34 seconds |
Started | Aug 08 05:56:19 PM PDT 24 |
Finished | Aug 08 05:59:15 PM PDT 24 |
Peak memory | 194436 kb |
Host | smart-d4ec2125-bac3-45a9-b7bd-c462acb1ee1b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3363817293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3363817293 |
Directory | /workspace/40.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1354311388 |
Short name | T9 |
Test name | |
Test status | |
Simulation time | 751709626768 ps |
CPU time | 246.97 seconds |
Started | Aug 08 05:56:22 PM PDT 24 |
Finished | Aug 08 06:00:29 PM PDT 24 |
Peak memory | 183340 kb |
Host | smart-6ee786fa-7bef-4a83-afed-40ed24c5b01e |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354311388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.1354311388 |
Directory | /workspace/41.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/41.rv_timer_disabled.2607480323 |
Short name | T2 |
Test name | |
Test status | |
Simulation time | 184709251806 ps |
CPU time | 275.6 seconds |
Started | Aug 08 05:56:22 PM PDT 24 |
Finished | Aug 08 06:00:58 PM PDT 24 |
Peak memory | 183472 kb |
Host | smart-7557434b-d1f7-4286-b23d-ca7d7bfcedbb |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2607480323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2607480323 |
Directory | /workspace/41.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/41.rv_timer_random_reset.3803558437 |
Short name | T134 |
Test name | |
Test status | |
Simulation time | 132775449569 ps |
CPU time | 67.12 seconds |
Started | Aug 08 05:56:23 PM PDT 24 |
Finished | Aug 08 05:57:30 PM PDT 24 |
Peak memory | 191664 kb |
Host | smart-84b2ea06-7c70-48c6-a040-afbad7de0193 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803558437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3803558437 |
Directory | /workspace/41.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/41.rv_timer_stress_all.3556506528 |
Short name | T6 |
Test name | |
Test status | |
Simulation time | 135636265045 ps |
CPU time | 208.16 seconds |
Started | Aug 08 05:56:21 PM PDT 24 |
Finished | Aug 08 05:59:50 PM PDT 24 |
Peak memory | 183376 kb |
Host | smart-a97d3c47-6b08-4d13-9ff8-c5b93bb18f9c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556506528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all .3556506528 |
Directory | /workspace/41.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.3949997241 |
Short name | T42 |
Test name | |
Test status | |
Simulation time | 24927880497 ps |
CPU time | 183.56 seconds |
Started | Aug 08 05:56:23 PM PDT 24 |
Finished | Aug 08 05:59:27 PM PDT 24 |
Peak memory | 198160 kb |
Host | smart-942da1a2-c8be-491b-92d9-771f3487e01d |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949997241 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.3949997241 |
Directory | /workspace/41.rv_timer_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1159914159 |
Short name | T52 |
Test name | |
Test status | |
Simulation time | 104741166144 ps |
CPU time | 174.37 seconds |
Started | Aug 08 05:56:24 PM PDT 24 |
Finished | Aug 08 05:59:18 PM PDT 24 |
Peak memory | 183436 kb |
Host | smart-77b57d3c-909c-4fd1-8a4d-6261453fd225 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159914159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.1159914159 |
Directory | /workspace/42.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/42.rv_timer_disabled.3703457402 |
Short name | T378 |
Test name | |
Test status | |
Simulation time | 126571885208 ps |
CPU time | 102.08 seconds |
Started | Aug 08 05:56:24 PM PDT 24 |
Finished | Aug 08 05:58:06 PM PDT 24 |
Peak memory | 183440 kb |
Host | smart-c160e20f-0b14-4c2d-abeb-51204fe4d20b |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3703457402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3703457402 |
Directory | /workspace/42.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/42.rv_timer_random.3659878397 |
Short name | T299 |
Test name | |
Test status | |
Simulation time | 44513156375 ps |
CPU time | 64.03 seconds |
Started | Aug 08 05:56:22 PM PDT 24 |
Finished | Aug 08 05:57:26 PM PDT 24 |
Peak memory | 191524 kb |
Host | smart-ed8ef144-33ff-41ac-872a-5cb82298e574 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659878397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3659878397 |
Directory | /workspace/42.rv_timer_random/latest |
Test location | /workspace/coverage/default/42.rv_timer_random_reset.236614340 |
Short name | T375 |
Test name | |
Test status | |
Simulation time | 372280589 ps |
CPU time | 0.66 seconds |
Started | Aug 08 05:56:21 PM PDT 24 |
Finished | Aug 08 05:56:22 PM PDT 24 |
Peak memory | 183216 kb |
Host | smart-59a5c90d-8b20-445a-99f1-805907525cd3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=236614340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.236614340 |
Directory | /workspace/42.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3160452531 |
Short name | T306 |
Test name | |
Test status | |
Simulation time | 285033389880 ps |
CPU time | 416.8 seconds |
Started | Aug 08 05:56:24 PM PDT 24 |
Finished | Aug 08 06:03:21 PM PDT 24 |
Peak memory | 183448 kb |
Host | smart-7a69638f-4fcd-4616-8bef-f98320184f7f |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160452531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.3160452531 |
Directory | /workspace/43.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/43.rv_timer_disabled.3217996027 |
Short name | T376 |
Test name | |
Test status | |
Simulation time | 52686216748 ps |
CPU time | 81.3 seconds |
Started | Aug 08 05:56:22 PM PDT 24 |
Finished | Aug 08 05:57:44 PM PDT 24 |
Peak memory | 183472 kb |
Host | smart-7573900b-ca91-44fd-b5a7-d5ec101a9d0c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3217996027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3217996027 |
Directory | /workspace/43.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/43.rv_timer_random.1410554613 |
Short name | T123 |
Test name | |
Test status | |
Simulation time | 1021122570732 ps |
CPU time | 926.41 seconds |
Started | Aug 08 05:56:23 PM PDT 24 |
Finished | Aug 08 06:11:50 PM PDT 24 |
Peak memory | 191656 kb |
Host | smart-e73d5982-5eb5-4088-9f4c-515c232ce5ed |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410554613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1410554613 |
Directory | /workspace/43.rv_timer_random/latest |
Test location | /workspace/coverage/default/43.rv_timer_random_reset.1398319505 |
Short name | T418 |
Test name | |
Test status | |
Simulation time | 36562429350 ps |
CPU time | 219.58 seconds |
Started | Aug 08 05:56:24 PM PDT 24 |
Finished | Aug 08 06:00:04 PM PDT 24 |
Peak memory | 191564 kb |
Host | smart-3d99a066-1bf2-4c60-b337-094e6c7f2982 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1398319505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1398319505 |
Directory | /workspace/43.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/43.rv_timer_stress_all.1327274048 |
Short name | T419 |
Test name | |
Test status | |
Simulation time | 1028176546444 ps |
CPU time | 240.43 seconds |
Started | Aug 08 05:56:24 PM PDT 24 |
Finished | Aug 08 06:00:25 PM PDT 24 |
Peak memory | 191648 kb |
Host | smart-dd4d098e-c9a7-4105-b3c5-3c7722973ed2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327274048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all .1327274048 |
Directory | /workspace/43.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.24074356 |
Short name | T1 |
Test name | |
Test status | |
Simulation time | 8481396688 ps |
CPU time | 13.95 seconds |
Started | Aug 08 05:56:22 PM PDT 24 |
Finished | Aug 08 05:56:36 PM PDT 24 |
Peak memory | 183380 kb |
Host | smart-93b79242-93ac-4ab8-bb29-ca573aa5dbdc |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24074356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44 .rv_timer_cfg_update_on_fly.24074356 |
Directory | /workspace/44.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/44.rv_timer_random.827410025 |
Short name | T408 |
Test name | |
Test status | |
Simulation time | 80949470802 ps |
CPU time | 60.64 seconds |
Started | Aug 08 05:56:24 PM PDT 24 |
Finished | Aug 08 05:57:25 PM PDT 24 |
Peak memory | 191600 kb |
Host | smart-7e7829bb-1327-41ff-acc0-db58faafb923 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827410025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.827410025 |
Directory | /workspace/44.rv_timer_random/latest |
Test location | /workspace/coverage/default/44.rv_timer_random_reset.154845235 |
Short name | T420 |
Test name | |
Test status | |
Simulation time | 7387090659 ps |
CPU time | 41.53 seconds |
Started | Aug 08 05:56:23 PM PDT 24 |
Finished | Aug 08 05:57:05 PM PDT 24 |
Peak memory | 195252 kb |
Host | smart-c0737970-73d0-4ca4-baaa-d3217853007c |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=154845235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.154845235 |
Directory | /workspace/44.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/44.rv_timer_stress_all.2934655149 |
Short name | T395 |
Test name | |
Test status | |
Simulation time | 514547476516 ps |
CPU time | 658.95 seconds |
Started | Aug 08 05:56:33 PM PDT 24 |
Finished | Aug 08 06:07:32 PM PDT 24 |
Peak memory | 191620 kb |
Host | smart-a93f8531-7c66-44e0-97f4-78aa9bef7669 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934655149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all .2934655149 |
Directory | /workspace/44.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1869179248 |
Short name | T252 |
Test name | |
Test status | |
Simulation time | 364804238646 ps |
CPU time | 641.8 seconds |
Started | Aug 08 05:56:31 PM PDT 24 |
Finished | Aug 08 06:07:13 PM PDT 24 |
Peak memory | 183444 kb |
Host | smart-265edee7-7004-4870-80dd-5adecba1f62b |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869179248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.1869179248 |
Directory | /workspace/45.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/45.rv_timer_disabled.693609699 |
Short name | T435 |
Test name | |
Test status | |
Simulation time | 255322902958 ps |
CPU time | 176.59 seconds |
Started | Aug 08 05:56:31 PM PDT 24 |
Finished | Aug 08 05:59:28 PM PDT 24 |
Peak memory | 183444 kb |
Host | smart-7d3f45f8-b3f6-4b9c-90e9-aa0f2db38fc3 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=693609699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.693609699 |
Directory | /workspace/45.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/45.rv_timer_random.3917199509 |
Short name | T328 |
Test name | |
Test status | |
Simulation time | 70483546841 ps |
CPU time | 228.34 seconds |
Started | Aug 08 05:56:35 PM PDT 24 |
Finished | Aug 08 06:00:23 PM PDT 24 |
Peak memory | 191628 kb |
Host | smart-9f5c76a8-fbb6-403d-8f8c-662a819dd95a |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917199509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3917199509 |
Directory | /workspace/45.rv_timer_random/latest |
Test location | /workspace/coverage/default/45.rv_timer_random_reset.1432086211 |
Short name | T130 |
Test name | |
Test status | |
Simulation time | 610698549371 ps |
CPU time | 130.42 seconds |
Started | Aug 08 05:56:32 PM PDT 24 |
Finished | Aug 08 05:58:42 PM PDT 24 |
Peak memory | 191660 kb |
Host | smart-058c97df-ed9f-41a5-88e7-491a1272a959 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1432086211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1432086211 |
Directory | /workspace/45.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/45.rv_timer_stress_all.1616885905 |
Short name | T256 |
Test name | |
Test status | |
Simulation time | 204410997558 ps |
CPU time | 171.26 seconds |
Started | Aug 08 05:56:31 PM PDT 24 |
Finished | Aug 08 05:59:23 PM PDT 24 |
Peak memory | 191664 kb |
Host | smart-9d00e7f3-9b78-40c9-94d4-64fad726d137 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616885905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all .1616885905 |
Directory | /workspace/45.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.560186469 |
Short name | T43 |
Test name | |
Test status | |
Simulation time | 20939928614 ps |
CPU time | 189.65 seconds |
Started | Aug 08 05:56:31 PM PDT 24 |
Finished | Aug 08 05:59:41 PM PDT 24 |
Peak memory | 197948 kb |
Host | smart-75692580-466d-4164-9230-b75ca895cae9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560186469 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.560186469 |
Directory | /workspace/45.rv_timer_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.297913520 |
Short name | T343 |
Test name | |
Test status | |
Simulation time | 356309810234 ps |
CPU time | 132.97 seconds |
Started | Aug 08 05:56:30 PM PDT 24 |
Finished | Aug 08 05:58:43 PM PDT 24 |
Peak memory | 183656 kb |
Host | smart-70c3f0d5-645d-489e-8934-529c333b4998 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297913520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.rv_timer_cfg_update_on_fly.297913520 |
Directory | /workspace/46.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/46.rv_timer_disabled.1851935084 |
Short name | T360 |
Test name | |
Test status | |
Simulation time | 286434446966 ps |
CPU time | 163.8 seconds |
Started | Aug 08 05:56:33 PM PDT 24 |
Finished | Aug 08 05:59:17 PM PDT 24 |
Peak memory | 182216 kb |
Host | smart-fd2c014e-7e79-433f-b1f0-e35bad4307d8 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1851935084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1851935084 |
Directory | /workspace/46.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/46.rv_timer_random.4146231885 |
Short name | T122 |
Test name | |
Test status | |
Simulation time | 140718757774 ps |
CPU time | 199.72 seconds |
Started | Aug 08 05:56:31 PM PDT 24 |
Finished | Aug 08 05:59:50 PM PDT 24 |
Peak memory | 191596 kb |
Host | smart-81d260ae-d4b3-4796-a273-48a644dfbc77 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146231885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.4146231885 |
Directory | /workspace/46.rv_timer_random/latest |
Test location | /workspace/coverage/default/46.rv_timer_random_reset.396343710 |
Short name | T261 |
Test name | |
Test status | |
Simulation time | 62227201911 ps |
CPU time | 1003.04 seconds |
Started | Aug 08 05:56:31 PM PDT 24 |
Finished | Aug 08 06:13:15 PM PDT 24 |
Peak memory | 191648 kb |
Host | smart-078acecb-ddbc-466e-be8e-71fe4eb54c72 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=396343710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.396343710 |
Directory | /workspace/46.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3810406030 |
Short name | T211 |
Test name | |
Test status | |
Simulation time | 221226306737 ps |
CPU time | 362.62 seconds |
Started | Aug 08 05:56:34 PM PDT 24 |
Finished | Aug 08 06:02:36 PM PDT 24 |
Peak memory | 183420 kb |
Host | smart-3cb31021-73d5-4d92-8dd7-96a4cea28fd2 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810406030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.3810406030 |
Directory | /workspace/47.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/47.rv_timer_disabled.1932717525 |
Short name | T3 |
Test name | |
Test status | |
Simulation time | 70471366518 ps |
CPU time | 14.44 seconds |
Started | Aug 08 05:56:32 PM PDT 24 |
Finished | Aug 08 05:56:46 PM PDT 24 |
Peak memory | 183404 kb |
Host | smart-ba54ef02-2577-4514-b489-c1264fcfbe35 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1932717525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1932717525 |
Directory | /workspace/47.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/47.rv_timer_random.286514063 |
Short name | T137 |
Test name | |
Test status | |
Simulation time | 298633809402 ps |
CPU time | 163.11 seconds |
Started | Aug 08 05:56:30 PM PDT 24 |
Finished | Aug 08 05:59:13 PM PDT 24 |
Peak memory | 191600 kb |
Host | smart-9441149b-4c08-41bb-b2f2-57639623a2e2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286514063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.286514063 |
Directory | /workspace/47.rv_timer_random/latest |
Test location | /workspace/coverage/default/47.rv_timer_random_reset.3955049750 |
Short name | T396 |
Test name | |
Test status | |
Simulation time | 41436336827 ps |
CPU time | 20.76 seconds |
Started | Aug 08 05:56:32 PM PDT 24 |
Finished | Aug 08 05:56:53 PM PDT 24 |
Peak memory | 191636 kb |
Host | smart-9166c1a2-2d4f-456c-a518-c92b97a84b59 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3955049750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3955049750 |
Directory | /workspace/47.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/47.rv_timer_stress_all.3753041082 |
Short name | T428 |
Test name | |
Test status | |
Simulation time | 1339917242126 ps |
CPU time | 543.79 seconds |
Started | Aug 08 05:56:35 PM PDT 24 |
Finished | Aug 08 06:05:39 PM PDT 24 |
Peak memory | 191624 kb |
Host | smart-0fa27406-2a90-4b9d-8dc5-4de39fd32601 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753041082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all .3753041082 |
Directory | /workspace/47.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.370711374 |
Short name | T169 |
Test name | |
Test status | |
Simulation time | 737634220576 ps |
CPU time | 710.46 seconds |
Started | Aug 08 05:56:33 PM PDT 24 |
Finished | Aug 08 06:08:23 PM PDT 24 |
Peak memory | 182204 kb |
Host | smart-7636f721-d872-4f2a-875a-44f636bc9d73 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370711374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4 8.rv_timer_cfg_update_on_fly.370711374 |
Directory | /workspace/48.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/48.rv_timer_disabled.560381018 |
Short name | T383 |
Test name | |
Test status | |
Simulation time | 295435399535 ps |
CPU time | 209.22 seconds |
Started | Aug 08 05:56:31 PM PDT 24 |
Finished | Aug 08 06:00:00 PM PDT 24 |
Peak memory | 183432 kb |
Host | smart-1e77a40a-296c-48ad-b8f5-44d6b1987c35 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=560381018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.560381018 |
Directory | /workspace/48.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/48.rv_timer_random_reset.2721768865 |
Short name | T341 |
Test name | |
Test status | |
Simulation time | 95806648316 ps |
CPU time | 84.49 seconds |
Started | Aug 08 05:56:38 PM PDT 24 |
Finished | Aug 08 05:58:03 PM PDT 24 |
Peak memory | 191600 kb |
Host | smart-69faa56d-e126-4567-9226-998c94734fa4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2721768865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2721768865 |
Directory | /workspace/48.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1686026869 |
Short name | T224 |
Test name | |
Test status | |
Simulation time | 694539190456 ps |
CPU time | 322.41 seconds |
Started | Aug 08 05:56:40 PM PDT 24 |
Finished | Aug 08 06:02:02 PM PDT 24 |
Peak memory | 183404 kb |
Host | smart-fa74473a-9ac9-44b9-bf11-edf367c67398 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686026869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.1686026869 |
Directory | /workspace/49.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/49.rv_timer_disabled.94094863 |
Short name | T400 |
Test name | |
Test status | |
Simulation time | 92724643987 ps |
CPU time | 60.85 seconds |
Started | Aug 08 05:56:39 PM PDT 24 |
Finished | Aug 08 05:57:40 PM PDT 24 |
Peak memory | 183392 kb |
Host | smart-c882400f-7dc0-4562-8275-293851a94d38 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=94094863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.94094863 |
Directory | /workspace/49.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/49.rv_timer_random_reset.2661894717 |
Short name | T214 |
Test name | |
Test status | |
Simulation time | 14792034347 ps |
CPU time | 528.07 seconds |
Started | Aug 08 05:56:39 PM PDT 24 |
Finished | Aug 08 06:05:27 PM PDT 24 |
Peak memory | 183404 kb |
Host | smart-e71fc239-80a7-40c5-91c1-199d135de622 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2661894717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2661894717 |
Directory | /workspace/49.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.4138012148 |
Short name | T146 |
Test name | |
Test status | |
Simulation time | 787214620202 ps |
CPU time | 443.52 seconds |
Started | Aug 08 05:55:37 PM PDT 24 |
Finished | Aug 08 06:03:01 PM PDT 24 |
Peak memory | 183432 kb |
Host | smart-106de76a-46f1-4ce2-8e0f-e5c0c42dae3a |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138012148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.4138012148 |
Directory | /workspace/5.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/5.rv_timer_disabled.2862490223 |
Short name | T421 |
Test name | |
Test status | |
Simulation time | 374360326593 ps |
CPU time | 263.57 seconds |
Started | Aug 08 05:55:40 PM PDT 24 |
Finished | Aug 08 06:00:03 PM PDT 24 |
Peak memory | 183408 kb |
Host | smart-2eb30574-65a7-433c-8492-5b9cba70f185 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2862490223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2862490223 |
Directory | /workspace/5.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/5.rv_timer_random_reset.191757159 |
Short name | T377 |
Test name | |
Test status | |
Simulation time | 41652741826 ps |
CPU time | 18.15 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 05:56:05 PM PDT 24 |
Peak memory | 191652 kb |
Host | smart-58710997-9e82-44f6-8678-bc21b2bf451d |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=191757159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.191757159 |
Directory | /workspace/5.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/5.rv_timer_stress_all.2667441045 |
Short name | T254 |
Test name | |
Test status | |
Simulation time | 80562200177 ps |
CPU time | 125.98 seconds |
Started | Aug 08 05:55:42 PM PDT 24 |
Finished | Aug 08 05:57:48 PM PDT 24 |
Peak memory | 191696 kb |
Host | smart-836742a8-214a-4115-9494-a0f81931bfda |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667441045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all. 2667441045 |
Directory | /workspace/5.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.350999331 |
Short name | T14 |
Test name | |
Test status | |
Simulation time | 22033321351 ps |
CPU time | 185.26 seconds |
Started | Aug 08 05:55:40 PM PDT 24 |
Finished | Aug 08 05:58:45 PM PDT 24 |
Peak memory | 197908 kb |
Host | smart-82ec8e48-e5f9-46b3-8ff7-bcdb4e6b0ad9 |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350999331 -assert nopo stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.350999331 |
Directory | /workspace/5.rv_timer_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/51.rv_timer_random.613125661 |
Short name | T220 |
Test name | |
Test status | |
Simulation time | 48124546547 ps |
CPU time | 90.17 seconds |
Started | Aug 08 05:56:45 PM PDT 24 |
Finished | Aug 08 05:58:15 PM PDT 24 |
Peak memory | 194240 kb |
Host | smart-2dd3e9ac-0fcc-4cee-b725-73cec8f034cb |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613125661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.613125661 |
Directory | /workspace/51.rv_timer_random/latest |
Test location | /workspace/coverage/default/52.rv_timer_random.2282761148 |
Short name | T209 |
Test name | |
Test status | |
Simulation time | 522776196862 ps |
CPU time | 1162.02 seconds |
Started | Aug 08 05:56:47 PM PDT 24 |
Finished | Aug 08 06:16:09 PM PDT 24 |
Peak memory | 191644 kb |
Host | smart-bf8b2e27-2f6d-40d3-ac49-bd542a129c7c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282761148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2282761148 |
Directory | /workspace/52.rv_timer_random/latest |
Test location | /workspace/coverage/default/54.rv_timer_random.1630620573 |
Short name | T316 |
Test name | |
Test status | |
Simulation time | 34828757973 ps |
CPU time | 1239.77 seconds |
Started | Aug 08 05:56:47 PM PDT 24 |
Finished | Aug 08 06:17:27 PM PDT 24 |
Peak memory | 183428 kb |
Host | smart-a9963868-88d6-4902-b7c7-e2a0d16a3205 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630620573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1630620573 |
Directory | /workspace/54.rv_timer_random/latest |
Test location | /workspace/coverage/default/56.rv_timer_random.1175473821 |
Short name | T304 |
Test name | |
Test status | |
Simulation time | 12307410785 ps |
CPU time | 17.71 seconds |
Started | Aug 08 05:56:46 PM PDT 24 |
Finished | Aug 08 05:57:04 PM PDT 24 |
Peak memory | 191632 kb |
Host | smart-47a7fa7c-a76b-4ff8-af4a-457679385994 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175473821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1175473821 |
Directory | /workspace/56.rv_timer_random/latest |
Test location | /workspace/coverage/default/57.rv_timer_random.4116330799 |
Short name | T100 |
Test name | |
Test status | |
Simulation time | 89939171138 ps |
CPU time | 365.09 seconds |
Started | Aug 08 05:56:45 PM PDT 24 |
Finished | Aug 08 06:02:51 PM PDT 24 |
Peak memory | 191668 kb |
Host | smart-262e1b25-78ca-42e9-bd25-1610d12c40dd |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116330799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.4116330799 |
Directory | /workspace/57.rv_timer_random/latest |
Test location | /workspace/coverage/default/59.rv_timer_random.1691663506 |
Short name | T326 |
Test name | |
Test status | |
Simulation time | 239844799655 ps |
CPU time | 540.21 seconds |
Started | Aug 08 05:56:46 PM PDT 24 |
Finished | Aug 08 06:05:47 PM PDT 24 |
Peak memory | 191696 kb |
Host | smart-206ec4de-8048-4fc4-9a01-ea95f48b8544 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691663506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1691663506 |
Directory | /workspace/59.rv_timer_random/latest |
Test location | /workspace/coverage/default/6.rv_timer_disabled.3570441684 |
Short name | T444 |
Test name | |
Test status | |
Simulation time | 97355670100 ps |
CPU time | 35.95 seconds |
Started | Aug 08 05:55:40 PM PDT 24 |
Finished | Aug 08 05:56:16 PM PDT 24 |
Peak memory | 183436 kb |
Host | smart-55386240-47a6-4ba0-b781-7519ffae5eea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3570441684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3570441684 |
Directory | /workspace/6.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/6.rv_timer_random.3596110609 |
Short name | T127 |
Test name | |
Test status | |
Simulation time | 15949022128 ps |
CPU time | 2.64 seconds |
Started | Aug 08 05:55:47 PM PDT 24 |
Finished | Aug 08 05:55:50 PM PDT 24 |
Peak memory | 183276 kb |
Host | smart-b7e629cf-9605-4fde-af63-4a8681e52086 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596110609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3596110609 |
Directory | /workspace/6.rv_timer_random/latest |
Test location | /workspace/coverage/default/6.rv_timer_random_reset.255977654 |
Short name | T108 |
Test name | |
Test status | |
Simulation time | 191206992369 ps |
CPU time | 152.41 seconds |
Started | Aug 08 05:55:40 PM PDT 24 |
Finished | Aug 08 05:58:12 PM PDT 24 |
Peak memory | 191608 kb |
Host | smart-38e0aeec-14fa-4382-b6e6-5bd0349aab28 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=255977654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.255977654 |
Directory | /workspace/6.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/6.rv_timer_stress_all.2581874276 |
Short name | T303 |
Test name | |
Test status | |
Simulation time | 202049161838 ps |
CPU time | 95.47 seconds |
Started | Aug 08 05:55:37 PM PDT 24 |
Finished | Aug 08 05:57:13 PM PDT 24 |
Peak memory | 191656 kb |
Host | smart-375b9bb5-cc48-4008-91f8-819417b2f746 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581874276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all. 2581874276 |
Directory | /workspace/6.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/60.rv_timer_random.3802702987 |
Short name | T22 |
Test name | |
Test status | |
Simulation time | 333529851966 ps |
CPU time | 352.54 seconds |
Started | Aug 08 05:56:49 PM PDT 24 |
Finished | Aug 08 06:02:42 PM PDT 24 |
Peak memory | 191620 kb |
Host | smart-29a1f402-a83d-40b3-b056-a7a8f6fca170 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802702987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3802702987 |
Directory | /workspace/60.rv_timer_random/latest |
Test location | /workspace/coverage/default/61.rv_timer_random.1599833331 |
Short name | T350 |
Test name | |
Test status | |
Simulation time | 48052743035 ps |
CPU time | 178.98 seconds |
Started | Aug 08 05:56:45 PM PDT 24 |
Finished | Aug 08 05:59:44 PM PDT 24 |
Peak memory | 191576 kb |
Host | smart-21d6f552-1ae4-48f1-81e9-f6c05b8e4768 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599833331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1599833331 |
Directory | /workspace/61.rv_timer_random/latest |
Test location | /workspace/coverage/default/62.rv_timer_random.542747327 |
Short name | T445 |
Test name | |
Test status | |
Simulation time | 142844287496 ps |
CPU time | 133.38 seconds |
Started | Aug 08 05:56:46 PM PDT 24 |
Finished | Aug 08 05:59:00 PM PDT 24 |
Peak memory | 191532 kb |
Host | smart-c89ba7fc-7788-41c3-8505-64a5b0c43ed2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542747327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.542747327 |
Directory | /workspace/62.rv_timer_random/latest |
Test location | /workspace/coverage/default/63.rv_timer_random.52944268 |
Short name | T352 |
Test name | |
Test status | |
Simulation time | 6359265036 ps |
CPU time | 10.95 seconds |
Started | Aug 08 05:56:49 PM PDT 24 |
Finished | Aug 08 05:57:00 PM PDT 24 |
Peak memory | 183416 kb |
Host | smart-0d4cb018-78cb-4089-8e13-f99fdf6b1441 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52944268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.52944268 |
Directory | /workspace/63.rv_timer_random/latest |
Test location | /workspace/coverage/default/64.rv_timer_random.3952358016 |
Short name | T312 |
Test name | |
Test status | |
Simulation time | 759488935387 ps |
CPU time | 475.12 seconds |
Started | Aug 08 05:56:49 PM PDT 24 |
Finished | Aug 08 06:04:44 PM PDT 24 |
Peak memory | 193664 kb |
Host | smart-f0ce4eb0-2d78-4f6e-acc0-5f5510e5f643 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952358016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3952358016 |
Directory | /workspace/64.rv_timer_random/latest |
Test location | /workspace/coverage/default/65.rv_timer_random.3998650367 |
Short name | T336 |
Test name | |
Test status | |
Simulation time | 8779573817 ps |
CPU time | 17.16 seconds |
Started | Aug 08 05:56:56 PM PDT 24 |
Finished | Aug 08 05:57:13 PM PDT 24 |
Peak memory | 183484 kb |
Host | smart-72fb3728-4eed-421b-8371-b2e1c9f21368 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998650367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3998650367 |
Directory | /workspace/65.rv_timer_random/latest |
Test location | /workspace/coverage/default/66.rv_timer_random.2076999839 |
Short name | T238 |
Test name | |
Test status | |
Simulation time | 759687778842 ps |
CPU time | 243.58 seconds |
Started | Aug 08 05:56:56 PM PDT 24 |
Finished | Aug 08 06:01:00 PM PDT 24 |
Peak memory | 191636 kb |
Host | smart-4471d93d-4241-4a79-a4ff-1715d8af13c0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076999839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2076999839 |
Directory | /workspace/66.rv_timer_random/latest |
Test location | /workspace/coverage/default/67.rv_timer_random.4043354570 |
Short name | T392 |
Test name | |
Test status | |
Simulation time | 182639075656 ps |
CPU time | 35.11 seconds |
Started | Aug 08 05:56:55 PM PDT 24 |
Finished | Aug 08 05:57:30 PM PDT 24 |
Peak memory | 191584 kb |
Host | smart-b62fe754-4498-4ed0-8f37-fc4b61673413 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043354570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4043354570 |
Directory | /workspace/67.rv_timer_random/latest |
Test location | /workspace/coverage/default/69.rv_timer_random.2948024816 |
Short name | T206 |
Test name | |
Test status | |
Simulation time | 119631187394 ps |
CPU time | 192.57 seconds |
Started | Aug 08 05:57:00 PM PDT 24 |
Finished | Aug 08 06:00:12 PM PDT 24 |
Peak memory | 191636 kb |
Host | smart-fd9b934e-f6ea-4133-b4b6-1b53b95bf49b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948024816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2948024816 |
Directory | /workspace/69.rv_timer_random/latest |
Test location | /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1185633858 |
Short name | T182 |
Test name | |
Test status | |
Simulation time | 578984256029 ps |
CPU time | 470.63 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 06:03:36 PM PDT 24 |
Peak memory | 183456 kb |
Host | smart-a97d74a6-c7f7-4d0a-a259-43624f82ec3d |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185633858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ =rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.1185633858 |
Directory | /workspace/7.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/7.rv_timer_disabled.1677390601 |
Short name | T68 |
Test name | |
Test status | |
Simulation time | 587244710803 ps |
CPU time | 233.93 seconds |
Started | Aug 08 05:55:42 PM PDT 24 |
Finished | Aug 08 05:59:36 PM PDT 24 |
Peak memory | 183368 kb |
Host | smart-0a94921f-04b9-49a6-937c-b48fee4525ea |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1677390601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1677390601 |
Directory | /workspace/7.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/7.rv_timer_random.163929370 |
Short name | T262 |
Test name | |
Test status | |
Simulation time | 291350876013 ps |
CPU time | 199.99 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 05:59:06 PM PDT 24 |
Peak memory | 191656 kb |
Host | smart-955593c9-616c-46c5-bc34-25a5611c9eb0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163929370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.163929370 |
Directory | /workspace/7.rv_timer_random/latest |
Test location | /workspace/coverage/default/7.rv_timer_random_reset.4013740328 |
Short name | T357 |
Test name | |
Test status | |
Simulation time | 29890548657 ps |
CPU time | 14.12 seconds |
Started | Aug 08 05:55:37 PM PDT 24 |
Finished | Aug 08 05:55:52 PM PDT 24 |
Peak memory | 183392 kb |
Host | smart-71918863-3f16-45c1-b99d-de47bcf78df4 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4013740328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.4013740328 |
Directory | /workspace/7.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/7.rv_timer_stress_all.3028314001 |
Short name | T221 |
Test name | |
Test status | |
Simulation time | 177790100701 ps |
CPU time | 274.68 seconds |
Started | Aug 08 05:55:42 PM PDT 24 |
Finished | Aug 08 06:00:17 PM PDT 24 |
Peak memory | 195876 kb |
Host | smart-b7341556-67b6-4c20-b9e3-c9279370cb3b |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028314001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all. 3028314001 |
Directory | /workspace/7.rv_timer_stress_all/latest |
Test location | /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.3762585832 |
Short name | T13 |
Test name | |
Test status | |
Simulation time | 33952081738 ps |
CPU time | 338.07 seconds |
Started | Aug 08 05:55:40 PM PDT 24 |
Finished | Aug 08 06:01:18 PM PDT 24 |
Peak memory | 206324 kb |
Host | smart-7d1ca50f-9651-465f-b409-50722343663e |
User | root |
Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762585832 -assert nop ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.3762585832 |
Directory | /workspace/7.rv_timer_stress_all_with_rand_reset/latest |
Test location | /workspace/coverage/default/70.rv_timer_random.3959601526 |
Short name | T305 |
Test name | |
Test status | |
Simulation time | 200801088287 ps |
CPU time | 1806.44 seconds |
Started | Aug 08 05:56:55 PM PDT 24 |
Finished | Aug 08 06:27:02 PM PDT 24 |
Peak memory | 191628 kb |
Host | smart-3c3d6cb7-74e7-4689-9e25-a3a0213eb416 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959601526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3959601526 |
Directory | /workspace/70.rv_timer_random/latest |
Test location | /workspace/coverage/default/71.rv_timer_random.1843815781 |
Short name | T245 |
Test name | |
Test status | |
Simulation time | 380078536422 ps |
CPU time | 214.47 seconds |
Started | Aug 08 05:56:55 PM PDT 24 |
Finished | Aug 08 06:00:30 PM PDT 24 |
Peak memory | 191596 kb |
Host | smart-f570e959-c6fb-4112-a80d-ef07259accc0 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843815781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1843815781 |
Directory | /workspace/71.rv_timer_random/latest |
Test location | /workspace/coverage/default/72.rv_timer_random.4249941394 |
Short name | T241 |
Test name | |
Test status | |
Simulation time | 215715947933 ps |
CPU time | 188.64 seconds |
Started | Aug 08 05:56:56 PM PDT 24 |
Finished | Aug 08 06:00:04 PM PDT 24 |
Peak memory | 191572 kb |
Host | smart-81a73b5d-86ee-4ba3-9849-ae2484907c51 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249941394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.4249941394 |
Directory | /workspace/72.rv_timer_random/latest |
Test location | /workspace/coverage/default/74.rv_timer_random.93066565 |
Short name | T300 |
Test name | |
Test status | |
Simulation time | 32828629926 ps |
CPU time | 48.04 seconds |
Started | Aug 08 05:56:56 PM PDT 24 |
Finished | Aug 08 05:57:44 PM PDT 24 |
Peak memory | 191688 kb |
Host | smart-33b537ac-6856-4d69-b10b-f97b00c48d63 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93066565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.93066565 |
Directory | /workspace/74.rv_timer_random/latest |
Test location | /workspace/coverage/default/75.rv_timer_random.1873870651 |
Short name | T426 |
Test name | |
Test status | |
Simulation time | 329139919699 ps |
CPU time | 251.25 seconds |
Started | Aug 08 05:56:55 PM PDT 24 |
Finished | Aug 08 06:01:07 PM PDT 24 |
Peak memory | 191644 kb |
Host | smart-e1ce4353-97fa-41a0-b999-b30ebd4bd7d4 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873870651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1873870651 |
Directory | /workspace/75.rv_timer_random/latest |
Test location | /workspace/coverage/default/77.rv_timer_random.1638916225 |
Short name | T94 |
Test name | |
Test status | |
Simulation time | 182433659050 ps |
CPU time | 450.12 seconds |
Started | Aug 08 05:56:56 PM PDT 24 |
Finished | Aug 08 06:04:26 PM PDT 24 |
Peak memory | 191268 kb |
Host | smart-68742851-81db-4ce5-8bda-0239e3f6e08e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638916225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1638916225 |
Directory | /workspace/77.rv_timer_random/latest |
Test location | /workspace/coverage/default/79.rv_timer_random.2194248235 |
Short name | T267 |
Test name | |
Test status | |
Simulation time | 62881695104 ps |
CPU time | 416.05 seconds |
Started | Aug 08 05:56:56 PM PDT 24 |
Finished | Aug 08 06:03:52 PM PDT 24 |
Peak memory | 191696 kb |
Host | smart-00ddef57-603a-454f-9205-97130aa1ea61 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194248235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2194248235 |
Directory | /workspace/79.rv_timer_random/latest |
Test location | /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.41883559 |
Short name | T451 |
Test name | |
Test status | |
Simulation time | 84552288487 ps |
CPU time | 45.93 seconds |
Started | Aug 08 05:55:40 PM PDT 24 |
Finished | Aug 08 05:56:26 PM PDT 24 |
Peak memory | 183412 kb |
Host | smart-2f70bb51-1537-47b2-89ff-6b30d3f150d1 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41883559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8. rv_timer_cfg_update_on_fly.41883559 |
Directory | /workspace/8.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/8.rv_timer_disabled.523224827 |
Short name | T359 |
Test name | |
Test status | |
Simulation time | 449921006505 ps |
CPU time | 164.02 seconds |
Started | Aug 08 05:55:40 PM PDT 24 |
Finished | Aug 08 05:58:24 PM PDT 24 |
Peak memory | 183396 kb |
Host | smart-7b301513-2c46-49de-b387-88872e678ace |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=523224827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.523224827 |
Directory | /workspace/8.rv_timer_disabled/latest |
Test location | /workspace/coverage/default/8.rv_timer_random_reset.3931764399 |
Short name | T288 |
Test name | |
Test status | |
Simulation time | 56635836858 ps |
CPU time | 174.98 seconds |
Started | Aug 08 05:55:46 PM PDT 24 |
Finished | Aug 08 05:58:41 PM PDT 24 |
Peak memory | 191688 kb |
Host | smart-0dd5455e-0c15-4a81-8e7d-6c5c532164d1 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3931764399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3931764399 |
Directory | /workspace/8.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/80.rv_timer_random.1017056907 |
Short name | T277 |
Test name | |
Test status | |
Simulation time | 685223636415 ps |
CPU time | 336.65 seconds |
Started | Aug 08 05:56:54 PM PDT 24 |
Finished | Aug 08 06:02:31 PM PDT 24 |
Peak memory | 191624 kb |
Host | smart-54de961d-c8de-4184-a848-a4691b90d46e |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017056907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1017056907 |
Directory | /workspace/80.rv_timer_random/latest |
Test location | /workspace/coverage/default/81.rv_timer_random.37105162 |
Short name | T411 |
Test name | |
Test status | |
Simulation time | 120995273581 ps |
CPU time | 27.97 seconds |
Started | Aug 08 05:56:56 PM PDT 24 |
Finished | Aug 08 05:57:24 PM PDT 24 |
Peak memory | 183008 kb |
Host | smart-ba2b280c-9602-416f-b067-2ac41be9d053 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37105162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.37105162 |
Directory | /workspace/81.rv_timer_random/latest |
Test location | /workspace/coverage/default/83.rv_timer_random.336375294 |
Short name | T258 |
Test name | |
Test status | |
Simulation time | 213063615597 ps |
CPU time | 97.41 seconds |
Started | Aug 08 05:57:02 PM PDT 24 |
Finished | Aug 08 05:58:39 PM PDT 24 |
Peak memory | 191700 kb |
Host | smart-8fa69fbd-339a-4dfe-a80b-ea43de60c94f |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336375294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.336375294 |
Directory | /workspace/83.rv_timer_random/latest |
Test location | /workspace/coverage/default/84.rv_timer_random.3111813734 |
Short name | T401 |
Test name | |
Test status | |
Simulation time | 15218651731 ps |
CPU time | 22.6 seconds |
Started | Aug 08 05:57:02 PM PDT 24 |
Finished | Aug 08 05:57:24 PM PDT 24 |
Peak memory | 183488 kb |
Host | smart-b7cadfa2-8421-4889-93e1-6583fce0987c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111813734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3111813734 |
Directory | /workspace/84.rv_timer_random/latest |
Test location | /workspace/coverage/default/85.rv_timer_random.3068560462 |
Short name | T165 |
Test name | |
Test status | |
Simulation time | 828802931137 ps |
CPU time | 949.84 seconds |
Started | Aug 08 05:57:02 PM PDT 24 |
Finished | Aug 08 06:12:52 PM PDT 24 |
Peak memory | 191648 kb |
Host | smart-49b59c41-c580-49b8-973e-80ab138450fc |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068560462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3068560462 |
Directory | /workspace/85.rv_timer_random/latest |
Test location | /workspace/coverage/default/86.rv_timer_random.1909456581 |
Short name | T319 |
Test name | |
Test status | |
Simulation time | 98711650954 ps |
CPU time | 519.09 seconds |
Started | Aug 08 05:57:02 PM PDT 24 |
Finished | Aug 08 06:05:42 PM PDT 24 |
Peak memory | 191568 kb |
Host | smart-4dfa9553-2387-45d8-9447-97b667cd7638 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909456581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1909456581 |
Directory | /workspace/86.rv_timer_random/latest |
Test location | /workspace/coverage/default/88.rv_timer_random.1260306568 |
Short name | T244 |
Test name | |
Test status | |
Simulation time | 126438075439 ps |
CPU time | 135.73 seconds |
Started | Aug 08 05:57:02 PM PDT 24 |
Finished | Aug 08 05:59:18 PM PDT 24 |
Peak memory | 191600 kb |
Host | smart-e3caed56-3fcc-432f-9637-e8335e1eb972 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260306568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1260306568 |
Directory | /workspace/88.rv_timer_random/latest |
Test location | /workspace/coverage/default/89.rv_timer_random.3053891830 |
Short name | T223 |
Test name | |
Test status | |
Simulation time | 76472326476 ps |
CPU time | 118.63 seconds |
Started | Aug 08 05:57:02 PM PDT 24 |
Finished | Aug 08 05:59:01 PM PDT 24 |
Peak memory | 191644 kb |
Host | smart-0f83758e-fe03-4ea3-92ea-6dc458878438 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053891830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3053891830 |
Directory | /workspace/89.rv_timer_random/latest |
Test location | /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.444143229 |
Short name | T250 |
Test name | |
Test status | |
Simulation time | 27070373126 ps |
CPU time | 43.88 seconds |
Started | Aug 08 05:55:42 PM PDT 24 |
Finished | Aug 08 05:56:26 PM PDT 24 |
Peak memory | 183340 kb |
Host | smart-f4f79f78-09c1-4a59-98d9-0b6fa7b3f115 |
User | root |
Command | /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444143229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ= rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9 .rv_timer_cfg_update_on_fly.444143229 |
Directory | /workspace/9.rv_timer_cfg_update_on_fly/latest |
Test location | /workspace/coverage/default/9.rv_timer_random.2945053107 |
Short name | T345 |
Test name | |
Test status | |
Simulation time | 255278552939 ps |
CPU time | 642.12 seconds |
Started | Aug 08 05:55:41 PM PDT 24 |
Finished | Aug 08 06:06:23 PM PDT 24 |
Peak memory | 191552 kb |
Host | smart-99bedafb-0faf-4279-b2a2-f5fead9c4260 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945053107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2945053107 |
Directory | /workspace/9.rv_timer_random/latest |
Test location | /workspace/coverage/default/9.rv_timer_random_reset.2031659545 |
Short name | T236 |
Test name | |
Test status | |
Simulation time | 13799428038 ps |
CPU time | 18.63 seconds |
Started | Aug 08 05:55:39 PM PDT 24 |
Finished | Aug 08 05:55:58 PM PDT 24 |
Peak memory | 183244 kb |
Host | smart-a1c1595a-b907-4255-8e7a-593223384585 |
User | root |
Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2031659545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2031659545 |
Directory | /workspace/9.rv_timer_random_reset/latest |
Test location | /workspace/coverage/default/90.rv_timer_random.3004712370 |
Short name | T200 |
Test name | |
Test status | |
Simulation time | 2720676172983 ps |
CPU time | 1067.33 seconds |
Started | Aug 08 05:57:03 PM PDT 24 |
Finished | Aug 08 06:14:50 PM PDT 24 |
Peak memory | 191596 kb |
Host | smart-c48692d1-f0b6-4d88-9bba-f1c07e272aa8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004712370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3004712370 |
Directory | /workspace/90.rv_timer_random/latest |
Test location | /workspace/coverage/default/92.rv_timer_random.3584935933 |
Short name | T231 |
Test name | |
Test status | |
Simulation time | 107640653184 ps |
CPU time | 136.95 seconds |
Started | Aug 08 05:57:00 PM PDT 24 |
Finished | Aug 08 05:59:17 PM PDT 24 |
Peak memory | 191868 kb |
Host | smart-d73441e0-9949-4e07-9ab8-5fb5bd06a937 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584935933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3584935933 |
Directory | /workspace/92.rv_timer_random/latest |
Test location | /workspace/coverage/default/93.rv_timer_random.1081309941 |
Short name | T64 |
Test name | |
Test status | |
Simulation time | 493764257981 ps |
CPU time | 694.95 seconds |
Started | Aug 08 05:57:06 PM PDT 24 |
Finished | Aug 08 06:08:42 PM PDT 24 |
Peak memory | 191608 kb |
Host | smart-d86a78b5-dbe3-4413-aaf5-962217f26fd8 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081309941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1081309941 |
Directory | /workspace/93.rv_timer_random/latest |
Test location | /workspace/coverage/default/94.rv_timer_random.3043040544 |
Short name | T415 |
Test name | |
Test status | |
Simulation time | 137810152961 ps |
CPU time | 395.67 seconds |
Started | Aug 08 05:57:03 PM PDT 24 |
Finished | Aug 08 06:03:38 PM PDT 24 |
Peak memory | 191668 kb |
Host | smart-dcca4637-0672-458f-9e9b-db775f7b3fba |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043040544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3043040544 |
Directory | /workspace/94.rv_timer_random/latest |
Test location | /workspace/coverage/default/95.rv_timer_random.2946466380 |
Short name | T260 |
Test name | |
Test status | |
Simulation time | 480376294766 ps |
CPU time | 710 seconds |
Started | Aug 08 05:57:03 PM PDT 24 |
Finished | Aug 08 06:08:53 PM PDT 24 |
Peak memory | 191700 kb |
Host | smart-6d875250-9556-4274-9d59-9490f8fd78a2 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946466380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2946466380 |
Directory | /workspace/95.rv_timer_random/latest |
Test location | /workspace/coverage/default/96.rv_timer_random.2673501211 |
Short name | T145 |
Test name | |
Test status | |
Simulation time | 737506498552 ps |
CPU time | 1051.87 seconds |
Started | Aug 08 05:57:06 PM PDT 24 |
Finished | Aug 08 06:14:38 PM PDT 24 |
Peak memory | 191596 kb |
Host | smart-56b6089c-f0b7-4b24-8abc-30c90d42626c |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673501211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2673501211 |
Directory | /workspace/96.rv_timer_random/latest |
Test location | /workspace/coverage/default/97.rv_timer_random.1283974274 |
Short name | T268 |
Test name | |
Test status | |
Simulation time | 26069777746 ps |
CPU time | 25.7 seconds |
Started | Aug 08 05:57:09 PM PDT 24 |
Finished | Aug 08 05:57:35 PM PDT 24 |
Peak memory | 183444 kb |
Host | smart-cb2c066b-69f3-4e07-9733-769f453bc4a9 |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283974274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1283974274 |
Directory | /workspace/97.rv_timer_random/latest |
Test location | /workspace/coverage/default/98.rv_timer_random.2694794951 |
Short name | T156 |
Test name | |
Test status | |
Simulation time | 710302611569 ps |
CPU time | 503.28 seconds |
Started | Aug 08 05:57:10 PM PDT 24 |
Finished | Aug 08 06:05:33 PM PDT 24 |
Peak memory | 191676 kb |
Host | smart-32fb3049-d385-4490-a179-4d90b5fce42d |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694794951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2694794951 |
Directory | /workspace/98.rv_timer_random/latest |
Test location | /workspace/coverage/default/99.rv_timer_random.3845585538 |
Short name | T129 |
Test name | |
Test status | |
Simulation time | 577066507904 ps |
CPU time | 812.28 seconds |
Started | Aug 08 05:57:09 PM PDT 24 |
Finished | Aug 08 06:10:41 PM PDT 24 |
Peak memory | 191688 kb |
Host | smart-f2e2c88f-fa96-4ba7-8786-248e747adcad |
User | root |
Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845585538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3845585538 |
Directory | /workspace/99.rv_timer_random/latest |
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