Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.36 98.73 100.00 100.00 100.00 99.77


Total test records in report: 578
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T511 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2864883914 Aug 09 05:34:21 PM PDT 24 Aug 09 05:34:23 PM PDT 24 143141556 ps
T512 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1979106414 Aug 09 05:34:20 PM PDT 24 Aug 09 05:34:21 PM PDT 24 168362104 ps
T513 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3516506284 Aug 09 05:34:06 PM PDT 24 Aug 09 05:34:07 PM PDT 24 50057470 ps
T514 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1055313236 Aug 09 05:34:25 PM PDT 24 Aug 09 05:34:26 PM PDT 24 83166843 ps
T515 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1651528445 Aug 09 05:34:16 PM PDT 24 Aug 09 05:34:16 PM PDT 24 15615366 ps
T516 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.629243663 Aug 09 05:33:59 PM PDT 24 Aug 09 05:33:59 PM PDT 24 12678124 ps
T517 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2342977561 Aug 09 05:34:10 PM PDT 24 Aug 09 05:34:11 PM PDT 24 15615057 ps
T518 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.523084388 Aug 09 05:34:29 PM PDT 24 Aug 09 05:34:30 PM PDT 24 39696660 ps
T519 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2012676970 Aug 09 05:34:19 PM PDT 24 Aug 09 05:34:20 PM PDT 24 79415563 ps
T520 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.4064088295 Aug 09 05:34:47 PM PDT 24 Aug 09 05:34:48 PM PDT 24 91166132 ps
T521 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2083689494 Aug 09 05:34:29 PM PDT 24 Aug 09 05:34:30 PM PDT 24 38420697 ps
T522 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2496462950 Aug 09 05:34:40 PM PDT 24 Aug 09 05:34:40 PM PDT 24 14947833 ps
T523 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1274155407 Aug 09 05:34:13 PM PDT 24 Aug 09 05:34:14 PM PDT 24 18181949 ps
T524 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2185814890 Aug 09 05:34:12 PM PDT 24 Aug 09 05:34:12 PM PDT 24 46257613 ps
T93 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3712501866 Aug 09 05:34:06 PM PDT 24 Aug 09 05:34:07 PM PDT 24 13513486 ps
T525 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2929391242 Aug 09 05:34:03 PM PDT 24 Aug 09 05:34:05 PM PDT 24 285744848 ps
T526 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1950306455 Aug 09 05:34:32 PM PDT 24 Aug 09 05:34:32 PM PDT 24 21655766 ps
T527 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2926667697 Aug 09 05:34:29 PM PDT 24 Aug 09 05:34:30 PM PDT 24 33836976 ps
T528 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3289505447 Aug 09 05:34:19 PM PDT 24 Aug 09 05:34:20 PM PDT 24 31150567 ps
T529 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1088371731 Aug 09 05:34:11 PM PDT 24 Aug 09 05:34:12 PM PDT 24 262483532 ps
T530 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2277544568 Aug 09 05:34:23 PM PDT 24 Aug 09 05:34:24 PM PDT 24 30933327 ps
T94 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3188294824 Aug 09 05:34:15 PM PDT 24 Aug 09 05:34:15 PM PDT 24 14155716 ps
T531 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1891699313 Aug 09 05:34:16 PM PDT 24 Aug 09 05:34:18 PM PDT 24 162151803 ps
T532 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2322545590 Aug 09 05:34:11 PM PDT 24 Aug 09 05:34:12 PM PDT 24 26579003 ps
T533 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2546217257 Aug 09 05:34:34 PM PDT 24 Aug 09 05:34:34 PM PDT 24 24400433 ps
T534 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3401802862 Aug 09 05:34:14 PM PDT 24 Aug 09 05:34:14 PM PDT 24 16702340 ps
T535 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4213559799 Aug 09 05:34:22 PM PDT 24 Aug 09 05:34:23 PM PDT 24 58231398 ps
T536 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.183994251 Aug 09 05:34:13 PM PDT 24 Aug 09 05:34:14 PM PDT 24 67388195 ps
T537 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1929009633 Aug 09 05:34:30 PM PDT 24 Aug 09 05:34:31 PM PDT 24 33300513 ps
T538 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3073512063 Aug 09 05:33:58 PM PDT 24 Aug 09 05:33:59 PM PDT 24 35914850 ps
T539 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3883856595 Aug 09 05:33:53 PM PDT 24 Aug 09 05:33:54 PM PDT 24 203794539 ps
T114 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2821616134 Aug 09 05:34:13 PM PDT 24 Aug 09 05:34:15 PM PDT 24 123124226 ps
T540 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4247797605 Aug 09 05:34:18 PM PDT 24 Aug 09 05:34:19 PM PDT 24 129593218 ps
T541 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3778342138 Aug 09 05:34:31 PM PDT 24 Aug 09 05:34:34 PM PDT 24 711262460 ps
T542 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.652671610 Aug 09 05:34:02 PM PDT 24 Aug 09 05:34:03 PM PDT 24 24535999 ps
T543 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.51095202 Aug 09 05:34:40 PM PDT 24 Aug 09 05:34:41 PM PDT 24 14662028 ps
T544 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3230631439 Aug 09 05:34:13 PM PDT 24 Aug 09 05:34:13 PM PDT 24 14755938 ps
T545 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1688160425 Aug 09 05:34:22 PM PDT 24 Aug 09 05:34:24 PM PDT 24 686656714 ps
T546 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2473453509 Aug 09 05:34:09 PM PDT 24 Aug 09 05:34:10 PM PDT 24 46420438 ps
T547 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3300240988 Aug 09 05:34:23 PM PDT 24 Aug 09 05:34:24 PM PDT 24 44599866 ps
T548 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1934652826 Aug 09 05:34:26 PM PDT 24 Aug 09 05:34:27 PM PDT 24 19815718 ps
T549 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1421548602 Aug 09 05:34:31 PM PDT 24 Aug 09 05:34:31 PM PDT 24 126522492 ps
T550 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3197391327 Aug 09 05:34:22 PM PDT 24 Aug 09 05:34:23 PM PDT 24 249191894 ps
T551 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3749890665 Aug 09 05:34:23 PM PDT 24 Aug 09 05:34:24 PM PDT 24 20130887 ps
T552 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2030056733 Aug 09 05:34:20 PM PDT 24 Aug 09 05:34:21 PM PDT 24 190049852 ps
T553 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1801012358 Aug 09 05:34:43 PM PDT 24 Aug 09 05:34:44 PM PDT 24 13007348 ps
T95 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3841433913 Aug 09 05:33:57 PM PDT 24 Aug 09 05:33:58 PM PDT 24 27736838 ps
T554 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1497576709 Aug 09 05:34:14 PM PDT 24 Aug 09 05:34:15 PM PDT 24 162491016 ps
T555 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3252777078 Aug 09 05:34:11 PM PDT 24 Aug 09 05:34:12 PM PDT 24 41398465 ps
T556 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2471123521 Aug 09 05:34:20 PM PDT 24 Aug 09 05:34:21 PM PDT 24 324602380 ps
T557 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1421206770 Aug 09 05:34:13 PM PDT 24 Aug 09 05:34:14 PM PDT 24 33494228 ps
T558 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2127979965 Aug 09 05:34:25 PM PDT 24 Aug 09 05:34:26 PM PDT 24 14300472 ps
T559 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4185144253 Aug 09 05:34:33 PM PDT 24 Aug 09 05:34:33 PM PDT 24 20275769 ps
T560 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2793786856 Aug 09 05:34:20 PM PDT 24 Aug 09 05:34:21 PM PDT 24 29340059 ps
T561 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2362334681 Aug 09 05:34:27 PM PDT 24 Aug 09 05:34:27 PM PDT 24 13731853 ps
T562 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.585542698 Aug 09 05:34:17 PM PDT 24 Aug 09 05:34:18 PM PDT 24 112737515 ps
T563 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3660750531 Aug 09 05:34:22 PM PDT 24 Aug 09 05:34:23 PM PDT 24 19816805 ps
T98 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2407920172 Aug 09 05:34:08 PM PDT 24 Aug 09 05:34:11 PM PDT 24 232175719 ps
T564 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1114540350 Aug 09 05:34:00 PM PDT 24 Aug 09 05:34:02 PM PDT 24 45970564 ps
T565 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3363595053 Aug 09 05:34:26 PM PDT 24 Aug 09 05:34:27 PM PDT 24 40255646 ps
T566 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3086828135 Aug 09 05:34:26 PM PDT 24 Aug 09 05:34:26 PM PDT 24 155268290 ps
T96 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3114089908 Aug 09 05:34:06 PM PDT 24 Aug 09 05:34:06 PM PDT 24 20340438 ps
T102 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3332003823 Aug 09 05:34:02 PM PDT 24 Aug 09 05:34:03 PM PDT 24 18165859 ps
T567 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.964646299 Aug 09 05:34:04 PM PDT 24 Aug 09 05:34:06 PM PDT 24 450788068 ps
T568 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1381246192 Aug 09 05:34:14 PM PDT 24 Aug 09 05:34:15 PM PDT 24 13542443 ps
T569 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.774502967 Aug 09 05:34:25 PM PDT 24 Aug 09 05:34:26 PM PDT 24 17349894 ps
T570 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3641890186 Aug 09 05:34:25 PM PDT 24 Aug 09 05:34:26 PM PDT 24 13343823 ps
T571 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3273857712 Aug 09 05:34:25 PM PDT 24 Aug 09 05:34:25 PM PDT 24 12827134 ps
T572 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2568238266 Aug 09 05:34:37 PM PDT 24 Aug 09 05:34:40 PM PDT 24 49441375 ps
T99 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1856711094 Aug 09 05:34:24 PM PDT 24 Aug 09 05:34:25 PM PDT 24 14564408 ps
T100 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3639401633 Aug 09 05:34:24 PM PDT 24 Aug 09 05:34:25 PM PDT 24 51989262 ps
T573 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2708920585 Aug 09 05:34:12 PM PDT 24 Aug 09 05:34:13 PM PDT 24 82658171 ps
T101 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3446242279 Aug 09 05:34:20 PM PDT 24 Aug 09 05:34:20 PM PDT 24 34588085 ps
T574 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2054859099 Aug 09 05:34:14 PM PDT 24 Aug 09 05:34:16 PM PDT 24 138434333 ps
T575 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1950129924 Aug 09 05:34:09 PM PDT 24 Aug 09 05:34:10 PM PDT 24 463676580 ps
T576 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.509981443 Aug 09 05:34:13 PM PDT 24 Aug 09 05:34:14 PM PDT 24 60841047 ps
T577 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2884644102 Aug 09 05:34:24 PM PDT 24 Aug 09 05:34:26 PM PDT 24 215962269 ps
T578 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3670785371 Aug 09 05:34:34 PM PDT 24 Aug 09 05:34:35 PM PDT 24 184009159 ps

Test location /workspace/coverage/default/11.rv_timer_stress_all.25845491
Short name T9
Test name
Test status
Simulation time 443829611305 ps
CPU time 2581.91 seconds
Started Aug 09 04:32:34 PM PDT 24
Finished Aug 09 05:15:36 PM PDT 24
Peak memory 196108 kb
Host smart-94ad6de9-b947-4cde-b96d-da1bb538f45d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25845491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.25845491
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.4205158797
Short name T34
Test name
Test status
Simulation time 91084461756 ps
CPU time 347.51 seconds
Started Aug 09 04:33:00 PM PDT 24
Finished Aug 09 04:38:47 PM PDT 24
Peak memory 206144 kb
Host smart-148291c3-b176-44a4-85d5-2c5c96487032
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205158797 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.4205158797
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1675260985
Short name T8
Test name
Test status
Simulation time 1018580595951 ps
CPU time 1835.54 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 05:03:42 PM PDT 24
Peak memory 191472 kb
Host smart-c75521fb-fbd2-408c-acac-5e0647b1f1f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675260985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1675260985
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2993070959
Short name T28
Test name
Test status
Simulation time 150319730 ps
CPU time 1.17 seconds
Started Aug 09 05:34:21 PM PDT 24
Finished Aug 09 05:34:23 PM PDT 24
Peak memory 195380 kb
Host smart-31aa7362-affd-4ae4-af20-691c75043ded
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993070959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2993070959
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3613975954
Short name T61
Test name
Test status
Simulation time 519062163431 ps
CPU time 1584.7 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:59:41 PM PDT 24
Peak memory 190512 kb
Host smart-e1e0abc4-ae6d-4ad7-a41c-8e485da18b68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613975954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3613975954
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1847510273
Short name T172
Test name
Test status
Simulation time 2066295790203 ps
CPU time 2001.76 seconds
Started Aug 09 04:32:30 PM PDT 24
Finished Aug 09 05:05:52 PM PDT 24
Peak memory 195412 kb
Host smart-0e2937e7-b929-4904-9031-0901bdc5ac02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847510273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1847510273
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2904770448
Short name T63
Test name
Test status
Simulation time 381566787112 ps
CPU time 1422.65 seconds
Started Aug 09 04:32:18 PM PDT 24
Finished Aug 09 04:56:01 PM PDT 24
Peak memory 191456 kb
Host smart-82d40920-9c1d-41cb-bae7-2b8c7e582a07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904770448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2904770448
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2073540135
Short name T202
Test name
Test status
Simulation time 957969242881 ps
CPU time 1879.7 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 05:04:26 PM PDT 24
Peak memory 191436 kb
Host smart-b247c478-e640-4f72-8133-5aa69b9332af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073540135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2073540135
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3586532772
Short name T142
Test name
Test status
Simulation time 480294456379 ps
CPU time 1914.95 seconds
Started Aug 09 04:32:54 PM PDT 24
Finished Aug 09 05:04:49 PM PDT 24
Peak memory 195236 kb
Host smart-7afc946a-8fa9-41a6-ab6c-d92b8cc583a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586532772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3586532772
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.900948738
Short name T276
Test name
Test status
Simulation time 892740719247 ps
CPU time 974.81 seconds
Started Aug 09 04:32:38 PM PDT 24
Finished Aug 09 04:48:53 PM PDT 24
Peak memory 191420 kb
Host smart-c445f467-596f-4bc0-a453-48ffb06b0347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900948738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.900948738
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.268507188
Short name T177
Test name
Test status
Simulation time 1255749932459 ps
CPU time 927.71 seconds
Started Aug 09 04:32:41 PM PDT 24
Finished Aug 09 04:48:09 PM PDT 24
Peak memory 191408 kb
Host smart-cbd64f36-d829-4c85-a68a-fdad30c1f91f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268507188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.268507188
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3003622876
Short name T131
Test name
Test status
Simulation time 1426710025276 ps
CPU time 952.75 seconds
Started Aug 09 04:32:37 PM PDT 24
Finished Aug 09 04:48:30 PM PDT 24
Peak memory 195804 kb
Host smart-46ec048a-28de-439d-88d6-e66c3e8be958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003622876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3003622876
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.885306220
Short name T151
Test name
Test status
Simulation time 816046740273 ps
CPU time 1314.85 seconds
Started Aug 09 04:33:03 PM PDT 24
Finished Aug 09 04:54:58 PM PDT 24
Peak memory 196000 kb
Host smart-87623d1b-60a4-4e22-aec3-6c60972505e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885306220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
885306220
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2434762969
Short name T14
Test name
Test status
Simulation time 251698196 ps
CPU time 0.81 seconds
Started Aug 09 04:32:24 PM PDT 24
Finished Aug 09 04:32:25 PM PDT 24
Peak memory 213784 kb
Host smart-09f6430b-1448-4885-ba4d-059fa8dfd145
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434762969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2434762969
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3980719333
Short name T186
Test name
Test status
Simulation time 2742345820423 ps
CPU time 1239.17 seconds
Started Aug 09 04:32:45 PM PDT 24
Finished Aug 09 04:53:24 PM PDT 24
Peak memory 191464 kb
Host smart-e5e59c7f-63b1-4429-ba89-da333ecac916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980719333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3980719333
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/188.rv_timer_random.3641059070
Short name T115
Test name
Test status
Simulation time 649581319261 ps
CPU time 1078 seconds
Started Aug 09 04:33:34 PM PDT 24
Finished Aug 09 04:51:32 PM PDT 24
Peak memory 191508 kb
Host smart-603e414c-dc0f-4c87-9376-e5fa075dcc33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641059070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3641059070
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1173680172
Short name T128
Test name
Test status
Simulation time 497118652929 ps
CPU time 1281.78 seconds
Started Aug 09 04:32:49 PM PDT 24
Finished Aug 09 04:54:11 PM PDT 24
Peak memory 191428 kb
Host smart-46baa815-051d-4fbd-95c3-22844e357fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173680172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1173680172
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2234637470
Short name T242
Test name
Test status
Simulation time 625995521572 ps
CPU time 4202.7 seconds
Started Aug 09 04:33:59 PM PDT 24
Finished Aug 09 05:44:02 PM PDT 24
Peak memory 195164 kb
Host smart-2837590b-7b2a-470d-b9ac-597f7ac49b26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234637470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2234637470
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.500547011
Short name T304
Test name
Test status
Simulation time 1671650413574 ps
CPU time 2860.06 seconds
Started Aug 09 04:32:54 PM PDT 24
Finished Aug 09 05:20:35 PM PDT 24
Peak memory 191472 kb
Host smart-91a8b879-6639-47bf-ba60-962fcebda120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500547011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
500547011
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/169.rv_timer_random.4235712121
Short name T118
Test name
Test status
Simulation time 150154200035 ps
CPU time 255.7 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:37:33 PM PDT 24
Peak memory 194848 kb
Host smart-b58971db-7ebb-4bfd-a2e0-cb29e016dbfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235712121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4235712121
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random.2098587791
Short name T236
Test name
Test status
Simulation time 179633103382 ps
CPU time 491.85 seconds
Started Aug 09 04:33:09 PM PDT 24
Finished Aug 09 04:41:21 PM PDT 24
Peak memory 191608 kb
Host smart-7ef317de-5f73-4778-86a9-eb2ba774a393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098587791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2098587791
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1779091795
Short name T171
Test name
Test status
Simulation time 185833371553 ps
CPU time 434.4 seconds
Started Aug 09 04:33:23 PM PDT 24
Finished Aug 09 04:40:38 PM PDT 24
Peak memory 191464 kb
Host smart-84fcf8b1-ba9c-425b-b1bf-96aaae7aae5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779091795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1779091795
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.383133981
Short name T27
Test name
Test status
Simulation time 1481567287336 ps
CPU time 1399.37 seconds
Started Aug 09 04:33:59 PM PDT 24
Finished Aug 09 04:57:19 PM PDT 24
Peak memory 195680 kb
Host smart-1fc88e3d-fc4e-4334-bec7-42c7fabd26d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383133981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
383133981
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/98.rv_timer_random.1545100371
Short name T140
Test name
Test status
Simulation time 706354481743 ps
CPU time 447.2 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:40:44 PM PDT 24
Peak memory 192512 kb
Host smart-caa6e427-86dc-4f2a-af6d-0980b4891852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545100371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1545100371
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.857068213
Short name T184
Test name
Test status
Simulation time 532809643174 ps
CPU time 411.4 seconds
Started Aug 09 04:33:18 PM PDT 24
Finished Aug 09 04:40:10 PM PDT 24
Peak memory 191460 kb
Host smart-728b2ad8-b195-4694-bb18-3fa354d01140
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857068213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.857068213
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3245410602
Short name T211
Test name
Test status
Simulation time 990028009733 ps
CPU time 427.86 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:40:20 PM PDT 24
Peak memory 191472 kb
Host smart-9ce6daee-e542-4b53-906e-6e18edbb49c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245410602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3245410602
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3242367610
Short name T66
Test name
Test status
Simulation time 586413879047 ps
CPU time 512.03 seconds
Started Aug 09 04:33:15 PM PDT 24
Finished Aug 09 04:41:48 PM PDT 24
Peak memory 191432 kb
Host smart-c67cb83c-5225-4517-9794-98b6b6d3714f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242367610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3242367610
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/51.rv_timer_random.2935160868
Short name T74
Test name
Test status
Simulation time 479436676050 ps
CPU time 716.51 seconds
Started Aug 09 04:33:07 PM PDT 24
Finished Aug 09 04:45:04 PM PDT 24
Peak memory 191416 kb
Host smart-38fc09df-74b5-40b7-9bbf-df65d09933eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935160868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2935160868
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.3177888961
Short name T136
Test name
Test status
Simulation time 642636722516 ps
CPU time 631.28 seconds
Started Aug 09 04:33:03 PM PDT 24
Finished Aug 09 04:43:34 PM PDT 24
Peak memory 191484 kb
Host smart-3e0322c9-1003-4286-b63d-2f6d3c15857f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177888961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3177888961
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2547974052
Short name T147
Test name
Test status
Simulation time 844247025080 ps
CPU time 1785.31 seconds
Started Aug 09 04:32:21 PM PDT 24
Finished Aug 09 05:02:07 PM PDT 24
Peak memory 191476 kb
Host smart-c673f9e3-234e-4dd6-9501-661dbff443d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547974052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2547974052
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.4237094539
Short name T91
Test name
Test status
Simulation time 11754391 ps
CPU time 0.56 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:05 PM PDT 24
Peak memory 192172 kb
Host smart-6d900718-35cb-4982-9384-5b0fa9cab6e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237094539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.4237094539
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/100.rv_timer_random.1075666217
Short name T249
Test name
Test status
Simulation time 702306496636 ps
CPU time 1333.76 seconds
Started Aug 09 04:33:23 PM PDT 24
Finished Aug 09 04:55:37 PM PDT 24
Peak memory 191492 kb
Host smart-8e06d8ac-18f0-40aa-ab70-ec578cd3137d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075666217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1075666217
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1978460939
Short name T164
Test name
Test status
Simulation time 532172288941 ps
CPU time 228.08 seconds
Started Aug 09 04:33:10 PM PDT 24
Finished Aug 09 04:36:58 PM PDT 24
Peak memory 191444 kb
Host smart-5cefa141-408f-429c-8f5d-24c927f05847
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978460939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1978460939
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3640259141
Short name T230
Test name
Test status
Simulation time 1516688757221 ps
CPU time 3039.61 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 05:23:52 PM PDT 24
Peak memory 194604 kb
Host smart-fb605f60-c050-4313-b392-c02b8be0ac8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640259141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3640259141
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3630877176
Short name T152
Test name
Test status
Simulation time 333449443717 ps
CPU time 598.83 seconds
Started Aug 09 04:33:23 PM PDT 24
Finished Aug 09 04:43:22 PM PDT 24
Peak memory 191428 kb
Host smart-f69548c0-f8bd-4ad6-a1de-e038cf1b0974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630877176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3630877176
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.157368750
Short name T198
Test name
Test status
Simulation time 154120316932 ps
CPU time 757.54 seconds
Started Aug 09 04:33:18 PM PDT 24
Finished Aug 09 04:45:56 PM PDT 24
Peak memory 191508 kb
Host smart-006827da-78d2-4f49-9aac-066c18fd85b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157368750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.157368750
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2604679164
Short name T21
Test name
Test status
Simulation time 108953711101 ps
CPU time 585.36 seconds
Started Aug 09 04:33:18 PM PDT 24
Finished Aug 09 04:43:03 PM PDT 24
Peak memory 191548 kb
Host smart-4a8cac23-387c-47a0-8f2c-2a2944a1947d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604679164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2604679164
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.462461406
Short name T57
Test name
Test status
Simulation time 441171267423 ps
CPU time 369.78 seconds
Started Aug 09 04:33:14 PM PDT 24
Finished Aug 09 04:39:23 PM PDT 24
Peak memory 183300 kb
Host smart-b42cfac4-348e-4f15-99f0-adbcaab8c8ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462461406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.462461406
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.653547983
Short name T284
Test name
Test status
Simulation time 288559250277 ps
CPU time 712.25 seconds
Started Aug 09 04:32:50 PM PDT 24
Finished Aug 09 04:44:42 PM PDT 24
Peak memory 191448 kb
Host smart-21e68bef-3a88-44e2-af7f-86ebf68f738b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653547983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
653547983
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3044880146
Short name T182
Test name
Test status
Simulation time 452937213322 ps
CPU time 706.89 seconds
Started Aug 09 04:32:41 PM PDT 24
Finished Aug 09 04:44:28 PM PDT 24
Peak memory 195324 kb
Host smart-61543e35-752f-4d55-8ba1-c93455fd1819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044880146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3044880146
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/183.rv_timer_random.4229430466
Short name T190
Test name
Test status
Simulation time 145553914195 ps
CPU time 431.69 seconds
Started Aug 09 04:33:29 PM PDT 24
Finished Aug 09 04:40:41 PM PDT 24
Peak memory 191464 kb
Host smart-c776dc89-6828-4376-9aef-0d9c41a55a90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229430466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.4229430466
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1920969178
Short name T243
Test name
Test status
Simulation time 786025777352 ps
CPU time 1148.62 seconds
Started Aug 09 04:33:58 PM PDT 24
Finished Aug 09 04:53:07 PM PDT 24
Peak memory 191156 kb
Host smart-2081a585-8f0e-4fcd-8d03-9507c7acda3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920969178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1920969178
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2134481638
Short name T263
Test name
Test status
Simulation time 816364010607 ps
CPU time 1245.44 seconds
Started Aug 09 04:33:08 PM PDT 24
Finished Aug 09 04:53:54 PM PDT 24
Peak memory 191884 kb
Host smart-1b3d3e02-cf3c-486f-bfd4-28c686c88012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134481638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2134481638
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/88.rv_timer_random.1483100628
Short name T209
Test name
Test status
Simulation time 303615014620 ps
CPU time 325.48 seconds
Started Aug 09 04:33:19 PM PDT 24
Finished Aug 09 04:38:44 PM PDT 24
Peak memory 191600 kb
Host smart-d90cab2d-591e-4c68-a025-986abaed6142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483100628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1483100628
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.3416590250
Short name T224
Test name
Test status
Simulation time 513908673859 ps
CPU time 413.72 seconds
Started Aug 09 04:33:13 PM PDT 24
Finished Aug 09 04:40:07 PM PDT 24
Peak memory 191508 kb
Host smart-c16c3f50-13db-4f9c-8d8d-8bf9935cea81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416590250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3416590250
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1084540494
Short name T167
Test name
Test status
Simulation time 202785845739 ps
CPU time 170.37 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:36:13 PM PDT 24
Peak memory 191468 kb
Host smart-0a2e16ac-3846-4619-abf6-112e33e9db09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084540494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1084540494
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.359018215
Short name T234
Test name
Test status
Simulation time 186743478070 ps
CPU time 1396.42 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:56:34 PM PDT 24
Peak memory 191484 kb
Host smart-661b88c3-870a-4848-a0c5-12a49adfc248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359018215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.359018215
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.1643715684
Short name T287
Test name
Test status
Simulation time 1778057614150 ps
CPU time 1907.11 seconds
Started Aug 09 04:32:43 PM PDT 24
Finished Aug 09 05:04:30 PM PDT 24
Peak memory 191496 kb
Host smart-4ed8e808-d672-4833-86b5-22f55318657e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643715684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1643715684
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1043355980
Short name T155
Test name
Test status
Simulation time 676264596274 ps
CPU time 307.19 seconds
Started Aug 09 04:33:15 PM PDT 24
Finished Aug 09 04:38:23 PM PDT 24
Peak memory 191468 kb
Host smart-ef460537-347e-4fcb-822e-3bbe9ea8a0c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043355980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1043355980
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.251386957
Short name T47
Test name
Test status
Simulation time 87799705314 ps
CPU time 145.68 seconds
Started Aug 09 04:33:32 PM PDT 24
Finished Aug 09 04:35:58 PM PDT 24
Peak memory 191492 kb
Host smart-e52f1830-072e-4530-b80e-c4d7cf95df7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251386957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.251386957
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.16063103
Short name T197
Test name
Test status
Simulation time 34963792470 ps
CPU time 51.62 seconds
Started Aug 09 04:33:39 PM PDT 24
Finished Aug 09 04:34:30 PM PDT 24
Peak memory 191592 kb
Host smart-0cd0b408-536e-4754-a3d3-19657263bbf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16063103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.16063103
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2223093722
Short name T256
Test name
Test status
Simulation time 302344498787 ps
CPU time 611.26 seconds
Started Aug 09 04:33:29 PM PDT 24
Finished Aug 09 04:43:41 PM PDT 24
Peak memory 191508 kb
Host smart-9a681160-80b3-43a1-b803-73d6ac47368c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223093722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2223093722
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.201448461
Short name T123
Test name
Test status
Simulation time 764849205187 ps
CPU time 334.56 seconds
Started Aug 09 04:33:27 PM PDT 24
Finished Aug 09 04:39:01 PM PDT 24
Peak memory 191472 kb
Host smart-4feba8c9-c93d-42bb-8386-ec60c42d7a84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201448461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.201448461
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.991405209
Short name T251
Test name
Test status
Simulation time 179655117971 ps
CPU time 296.33 seconds
Started Aug 09 04:32:58 PM PDT 24
Finished Aug 09 04:37:54 PM PDT 24
Peak memory 183204 kb
Host smart-50faf61f-f3ce-406c-9b83-26749bf09ece
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991405209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.991405209
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_random.153853600
Short name T26
Test name
Test status
Simulation time 116924279838 ps
CPU time 254.87 seconds
Started Aug 09 04:33:05 PM PDT 24
Finished Aug 09 04:37:20 PM PDT 24
Peak memory 191492 kb
Host smart-133043a1-0d72-4b69-b19a-c77e6d497cc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153853600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.153853600
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3389230289
Short name T270
Test name
Test status
Simulation time 762338956107 ps
CPU time 1227.81 seconds
Started Aug 09 04:33:04 PM PDT 24
Finished Aug 09 04:53:32 PM PDT 24
Peak memory 191468 kb
Host smart-fc64e258-f496-415e-9411-a8b87c5c29ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389230289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3389230289
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1306864111
Short name T206
Test name
Test status
Simulation time 185515375660 ps
CPU time 596.83 seconds
Started Aug 09 04:32:56 PM PDT 24
Finished Aug 09 04:42:53 PM PDT 24
Peak memory 191500 kb
Host smart-7675b443-2671-4d82-a658-90a2f4071e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306864111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1306864111
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.501978129
Short name T124
Test name
Test status
Simulation time 78266279810 ps
CPU time 314.93 seconds
Started Aug 09 04:32:49 PM PDT 24
Finished Aug 09 04:38:04 PM PDT 24
Peak memory 191424 kb
Host smart-5ea3b5b9-1357-4e8b-98b7-8b2ea2b088ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501978129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.501978129
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.4196957354
Short name T232
Test name
Test status
Simulation time 59759819656 ps
CPU time 100.79 seconds
Started Aug 09 04:32:48 PM PDT 24
Finished Aug 09 04:34:29 PM PDT 24
Peak memory 194868 kb
Host smart-029d38f4-2d48-4ff0-9886-913bbaa17bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196957354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.4196957354
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/113.rv_timer_random.2229950380
Short name T312
Test name
Test status
Simulation time 18102235170 ps
CPU time 148.4 seconds
Started Aug 09 04:33:09 PM PDT 24
Finished Aug 09 04:35:38 PM PDT 24
Peak memory 191484 kb
Host smart-4f05e798-058c-44f7-9703-3ccd20169cb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229950380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2229950380
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.909636277
Short name T5
Test name
Test status
Simulation time 107924488828 ps
CPU time 77.96 seconds
Started Aug 09 04:33:08 PM PDT 24
Finished Aug 09 04:34:26 PM PDT 24
Peak memory 183360 kb
Host smart-752348be-e111-4ecd-936a-f1fc473355c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909636277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.909636277
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2147660313
Short name T175
Test name
Test status
Simulation time 504456670279 ps
CPU time 473.84 seconds
Started Aug 09 04:33:28 PM PDT 24
Finished Aug 09 04:41:22 PM PDT 24
Peak memory 191388 kb
Host smart-5c93f4bc-78ad-4dce-a6c9-c5a4e7f439a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147660313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2147660313
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.3956607011
Short name T122
Test name
Test status
Simulation time 145630493216 ps
CPU time 237.14 seconds
Started Aug 09 04:32:31 PM PDT 24
Finished Aug 09 04:36:28 PM PDT 24
Peak memory 191440 kb
Host smart-222e8562-874c-4bc9-9ec6-35cb09da6fe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956607011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3956607011
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2050212379
Short name T165
Test name
Test status
Simulation time 231689619191 ps
CPU time 887.95 seconds
Started Aug 09 04:34:37 PM PDT 24
Finished Aug 09 04:49:25 PM PDT 24
Peak memory 194968 kb
Host smart-765b8e89-5d99-4417-b8f9-aa0e960c1619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050212379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2050212379
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.1487156634
Short name T281
Test name
Test status
Simulation time 99720858847 ps
CPU time 92.44 seconds
Started Aug 09 04:34:37 PM PDT 24
Finished Aug 09 04:36:10 PM PDT 24
Peak memory 191392 kb
Host smart-f779d1c4-83b1-4ad7-a9a3-aa7bfd8cbe5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487156634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1487156634
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1817941558
Short name T40
Test name
Test status
Simulation time 111556039939 ps
CPU time 250.43 seconds
Started Aug 09 04:33:18 PM PDT 24
Finished Aug 09 04:37:28 PM PDT 24
Peak memory 191568 kb
Host smart-5486a38d-a948-4565-88c6-97c7f804e660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817941558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1817941558
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2070750154
Short name T82
Test name
Test status
Simulation time 1269036019415 ps
CPU time 289.94 seconds
Started Aug 09 04:33:21 PM PDT 24
Finished Aug 09 04:38:11 PM PDT 24
Peak memory 191456 kb
Host smart-23d8cf89-1367-4725-9a8d-9037b51ef4a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070750154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2070750154
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.411812317
Short name T187
Test name
Test status
Simulation time 370525843157 ps
CPU time 265.79 seconds
Started Aug 09 04:32:43 PM PDT 24
Finished Aug 09 04:37:09 PM PDT 24
Peak memory 195632 kb
Host smart-9eaf2a5f-628e-4d8b-b5f9-155014c2f26f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411812317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
411812317
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_random.1724042336
Short name T45
Test name
Test status
Simulation time 69025701964 ps
CPU time 114.12 seconds
Started Aug 09 04:33:01 PM PDT 24
Finished Aug 09 04:34:55 PM PDT 24
Peak memory 191456 kb
Host smart-9b8685cc-e3c3-4a51-874d-e53611aeba15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724042336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1724042336
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random.1976059742
Short name T1
Test name
Test status
Simulation time 86204405721 ps
CPU time 1012.93 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:50:10 PM PDT 24
Peak memory 191460 kb
Host smart-f829cb6c-726d-459d-96c6-0f0161ccc4f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976059742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1976059742
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1044439969
Short name T267
Test name
Test status
Simulation time 853902978515 ps
CPU time 464.88 seconds
Started Aug 09 04:32:20 PM PDT 24
Finished Aug 09 04:40:05 PM PDT 24
Peak memory 183324 kb
Host smart-4445eb88-285b-46dc-acd5-4b0ef9fe26a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044439969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1044439969
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/55.rv_timer_random.1403937042
Short name T188
Test name
Test status
Simulation time 486617604732 ps
CPU time 330.91 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:38:37 PM PDT 24
Peak memory 191500 kb
Host smart-81848445-b149-499b-b1a4-d7d6e13a8929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403937042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1403937042
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1333870729
Short name T25
Test name
Test status
Simulation time 627711647892 ps
CPU time 1595.15 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:59:52 PM PDT 24
Peak memory 191396 kb
Host smart-48769921-fae6-45f2-8471-8089f5765efe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333870729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1333870729
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3214073256
Short name T19
Test name
Test status
Simulation time 218186332959 ps
CPU time 319.76 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:38:32 PM PDT 24
Peak memory 191500 kb
Host smart-2d359cad-ada5-4130-880d-8a4ce3fa0e8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214073256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3214073256
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.964646299
Short name T567
Test name
Test status
Simulation time 450788068 ps
CPU time 1.35 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 183372 kb
Host smart-d6d7a011-eab9-4039-ad8e-dc32eb8b2389
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964646299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.964646299
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3809978350
Short name T259
Test name
Test status
Simulation time 54056862263 ps
CPU time 102.18 seconds
Started Aug 09 04:32:41 PM PDT 24
Finished Aug 09 04:34:23 PM PDT 24
Peak memory 191456 kb
Host smart-a8e87493-6bfb-4244-a50b-f4571af966a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809978350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3809978350
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.1070404533
Short name T75
Test name
Test status
Simulation time 151788760016 ps
CPU time 139.71 seconds
Started Aug 09 04:33:22 PM PDT 24
Finished Aug 09 04:35:41 PM PDT 24
Peak memory 191424 kb
Host smart-b442cef4-2228-4944-bf31-80c95cb544af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070404533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1070404533
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3934942312
Short name T317
Test name
Test status
Simulation time 12819648661 ps
CPU time 22.07 seconds
Started Aug 09 04:33:19 PM PDT 24
Finished Aug 09 04:33:41 PM PDT 24
Peak memory 191528 kb
Host smart-4f8fd4f8-faf0-41f6-98ea-dc24832a811d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934942312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3934942312
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.641267437
Short name T297
Test name
Test status
Simulation time 253654099408 ps
CPU time 232.76 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:37:09 PM PDT 24
Peak memory 191412 kb
Host smart-cef17294-4306-468c-b4fa-c57ebb5b87cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641267437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.641267437
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.1343646044
Short name T191
Test name
Test status
Simulation time 151445801015 ps
CPU time 559.33 seconds
Started Aug 09 04:32:59 PM PDT 24
Finished Aug 09 04:42:18 PM PDT 24
Peak memory 191864 kb
Host smart-2cd485ea-187c-4573-90e4-2aafae3135b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343646044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1343646044
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3500953716
Short name T216
Test name
Test status
Simulation time 260668941392 ps
CPU time 623.47 seconds
Started Aug 09 04:32:53 PM PDT 24
Finished Aug 09 04:43:16 PM PDT 24
Peak memory 191536 kb
Host smart-a5d06965-7a06-48a1-bf44-0603ced2fd35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500953716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3500953716
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/182.rv_timer_random.1246571178
Short name T332
Test name
Test status
Simulation time 71583001608 ps
CPU time 147.43 seconds
Started Aug 09 04:34:37 PM PDT 24
Finished Aug 09 04:37:05 PM PDT 24
Peak memory 194676 kb
Host smart-2c0a39d9-1edc-43f7-abf7-3740d16da65c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246571178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1246571178
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2734650622
Short name T143
Test name
Test status
Simulation time 670466084339 ps
CPU time 1200.67 seconds
Started Aug 09 04:33:31 PM PDT 24
Finished Aug 09 04:53:32 PM PDT 24
Peak memory 191444 kb
Host smart-6e5e7cf9-71e5-43d8-a578-613dbbe14209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734650622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2734650622
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1617375049
Short name T84
Test name
Test status
Simulation time 43615945301 ps
CPU time 104.98 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:35:02 PM PDT 24
Peak memory 191484 kb
Host smart-ea39aa17-af19-4817-8999-299ff04135f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617375049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1617375049
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1689926042
Short name T311
Test name
Test status
Simulation time 41057447614 ps
CPU time 143.29 seconds
Started Aug 09 04:33:20 PM PDT 24
Finished Aug 09 04:35:43 PM PDT 24
Peak memory 191436 kb
Host smart-99b209e1-6e82-4253-88a9-bb915516990e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689926042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1689926042
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2080779173
Short name T321
Test name
Test status
Simulation time 1681456573 ps
CPU time 1.8 seconds
Started Aug 09 04:33:58 PM PDT 24
Finished Aug 09 04:34:00 PM PDT 24
Peak memory 182716 kb
Host smart-bf8ce053-c247-4947-aca5-bb84c860337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080779173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2080779173
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3964246666
Short name T336
Test name
Test status
Simulation time 47132018079 ps
CPU time 93.03 seconds
Started Aug 09 04:32:25 PM PDT 24
Finished Aug 09 04:33:59 PM PDT 24
Peak memory 191508 kb
Host smart-386bee2a-755f-4cc7-95bf-0f9a88bbbd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964246666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3964246666
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_random.3868419199
Short name T173
Test name
Test status
Simulation time 533301972339 ps
CPU time 250.9 seconds
Started Aug 09 04:32:15 PM PDT 24
Finished Aug 09 04:36:26 PM PDT 24
Peak memory 191896 kb
Host smart-f2b52008-e7bf-4365-9d92-4ce5b69a7a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868419199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3868419199
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.4278950282
Short name T337
Test name
Test status
Simulation time 417083550394 ps
CPU time 124.43 seconds
Started Aug 09 04:33:59 PM PDT 24
Finished Aug 09 04:36:04 PM PDT 24
Peak memory 191188 kb
Host smart-f9cec135-95e6-48ce-bafa-3c9881e4597e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278950282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.4278950282
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_random.3967853524
Short name T160
Test name
Test status
Simulation time 2361612419060 ps
CPU time 770.29 seconds
Started Aug 09 04:33:03 PM PDT 24
Finished Aug 09 04:45:53 PM PDT 24
Peak memory 191544 kb
Host smart-343f4989-d5bf-414d-a640-43414d7e59a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967853524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3967853524
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.771343279
Short name T35
Test name
Test status
Simulation time 116979413228 ps
CPU time 879.77 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:47:46 PM PDT 24
Peak memory 210480 kb
Host smart-57853dc0-33f7-4a7d-a235-92161b0cf19d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771343279 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.771343279
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_random.1255203616
Short name T44
Test name
Test status
Simulation time 60633121598 ps
CPU time 104.09 seconds
Started Aug 09 04:33:11 PM PDT 24
Finished Aug 09 04:34:55 PM PDT 24
Peak memory 191388 kb
Host smart-ba7955e5-6b67-4e23-a401-dc8a24bf0855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255203616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1255203616
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1131753383
Short name T54
Test name
Test status
Simulation time 474778070859 ps
CPU time 572.95 seconds
Started Aug 09 04:33:09 PM PDT 24
Finished Aug 09 04:42:42 PM PDT 24
Peak memory 191448 kb
Host smart-df16de8f-53d9-4cd0-986d-00dc8d48992f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131753383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1131753383
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1607255936
Short name T218
Test name
Test status
Simulation time 181606495607 ps
CPU time 187.11 seconds
Started Aug 09 04:33:18 PM PDT 24
Finished Aug 09 04:36:26 PM PDT 24
Peak memory 191500 kb
Host smart-0e8ed086-3419-4c63-b179-e258c3e03e6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607255936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1607255936
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1916097547
Short name T80
Test name
Test status
Simulation time 119999104 ps
CPU time 0.79 seconds
Started Aug 09 05:34:03 PM PDT 24
Finished Aug 09 05:34:04 PM PDT 24
Peak memory 192732 kb
Host smart-11a4bd4d-964b-4d55-b982-87e5078d0e3c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916097547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1916097547
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2407920172
Short name T98
Test name
Test status
Simulation time 232175719 ps
CPU time 2.31 seconds
Started Aug 09 05:34:08 PM PDT 24
Finished Aug 09 05:34:11 PM PDT 24
Peak memory 183024 kb
Host smart-7c05df0a-a943-4c64-9d9c-abef1bf0c721
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407920172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2407920172
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3841433913
Short name T95
Test name
Test status
Simulation time 27736838 ps
CPU time 0.56 seconds
Started Aug 09 05:33:57 PM PDT 24
Finished Aug 09 05:33:58 PM PDT 24
Peak memory 182864 kb
Host smart-a39d53c7-f68e-4e86-8d98-3ade777ecdfd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841433913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3841433913
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3883856595
Short name T539
Test name
Test status
Simulation time 203794539 ps
CPU time 1.03 seconds
Started Aug 09 05:33:53 PM PDT 24
Finished Aug 09 05:33:54 PM PDT 24
Peak memory 197404 kb
Host smart-830b3009-89a9-4c78-8e86-2b04dc915077
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883856595 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3883856595
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3712501866
Short name T93
Test name
Test status
Simulation time 13513486 ps
CPU time 0.54 seconds
Started Aug 09 05:34:06 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 182548 kb
Host smart-97e48d32-b9e6-4b92-bd69-b4542dbc8f82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712501866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3712501866
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.629243663
Short name T516
Test name
Test status
Simulation time 12678124 ps
CPU time 0.53 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:33:59 PM PDT 24
Peak memory 182108 kb
Host smart-e6dec5fa-c197-4d0c-92c6-92ea9feb7eab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629243663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.629243663
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2277544568
Short name T530
Test name
Test status
Simulation time 30933327 ps
CPU time 0.78 seconds
Started Aug 09 05:34:23 PM PDT 24
Finished Aug 09 05:34:24 PM PDT 24
Peak memory 193540 kb
Host smart-1261cb53-4611-4ccc-9028-705045b86642
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277544568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2277544568
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2778654872
Short name T459
Test name
Test status
Simulation time 48240455 ps
CPU time 2.24 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:02 PM PDT 24
Peak memory 197524 kb
Host smart-167291e6-0513-44df-83b1-fa927cc08a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778654872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2778654872
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2797047534
Short name T81
Test name
Test status
Simulation time 24556063 ps
CPU time 0.63 seconds
Started Aug 09 05:34:10 PM PDT 24
Finished Aug 09 05:34:10 PM PDT 24
Peak memory 192168 kb
Host smart-539c3784-c91a-41b8-97e2-d053e2a08242
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797047534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2797047534
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2668030423
Short name T478
Test name
Test status
Simulation time 276608544 ps
CPU time 2.53 seconds
Started Aug 09 05:34:01 PM PDT 24
Finished Aug 09 05:34:04 PM PDT 24
Peak memory 183152 kb
Host smart-2f4c6210-5315-4adb-8af7-e6b0e05b11c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668030423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2668030423
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.507830175
Short name T79
Test name
Test status
Simulation time 37998468 ps
CPU time 0.58 seconds
Started Aug 09 05:34:12 PM PDT 24
Finished Aug 09 05:34:13 PM PDT 24
Peak memory 182916 kb
Host smart-664cbda2-9f55-403d-bb33-c42f1ee66808
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507830175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.507830175
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3037378183
Short name T469
Test name
Test status
Simulation time 137433629 ps
CPU time 0.7 seconds
Started Aug 09 05:34:10 PM PDT 24
Finished Aug 09 05:34:11 PM PDT 24
Peak memory 194968 kb
Host smart-59bf045c-84c7-4d57-af3c-908875f8c746
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037378183 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3037378183
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.502226185
Short name T489
Test name
Test status
Simulation time 33557346 ps
CPU time 0.54 seconds
Started Aug 09 05:34:06 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 182952 kb
Host smart-550ba0c5-963f-46a8-8522-5a1a4bb1a8fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502226185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.502226185
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3751224678
Short name T495
Test name
Test status
Simulation time 33752055 ps
CPU time 0.54 seconds
Started Aug 09 05:33:48 PM PDT 24
Finished Aug 09 05:33:49 PM PDT 24
Peak memory 182696 kb
Host smart-ade6ed1b-e44d-4b33-9bae-55ed0de6387f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751224678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3751224678
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.217135645
Short name T109
Test name
Test status
Simulation time 23008679 ps
CPU time 0.77 seconds
Started Aug 09 05:33:59 PM PDT 24
Finished Aug 09 05:34:00 PM PDT 24
Peak memory 191936 kb
Host smart-c9163b77-f119-4868-bbc5-ffccb2598875
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217135645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.217135645
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.119351772
Short name T501
Test name
Test status
Simulation time 37753337 ps
CPU time 1.8 seconds
Started Aug 09 05:34:33 PM PDT 24
Finished Aug 09 05:34:35 PM PDT 24
Peak memory 197568 kb
Host smart-8815c706-1f8e-435a-99e8-fc3f2d3c6de2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119351772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.119351772
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1950129924
Short name T575
Test name
Test status
Simulation time 463676580 ps
CPU time 0.83 seconds
Started Aug 09 05:34:09 PM PDT 24
Finished Aug 09 05:34:10 PM PDT 24
Peak memory 183432 kb
Host smart-d0d8ded4-da53-4ef3-9eb5-46058c20a9e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950129924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1950129924
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1421206770
Short name T557
Test name
Test status
Simulation time 33494228 ps
CPU time 1.29 seconds
Started Aug 09 05:34:13 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 197580 kb
Host smart-b88201c9-b8bc-4dd2-ad19-5d29911d991c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421206770 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1421206770
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3300240988
Short name T547
Test name
Test status
Simulation time 44599866 ps
CPU time 0.58 seconds
Started Aug 09 05:34:23 PM PDT 24
Finished Aug 09 05:34:24 PM PDT 24
Peak memory 182836 kb
Host smart-3e71a2c5-4719-4986-b079-22918881544f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300240988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3300240988
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1934652826
Short name T548
Test name
Test status
Simulation time 19815718 ps
CPU time 0.55 seconds
Started Aug 09 05:34:26 PM PDT 24
Finished Aug 09 05:34:27 PM PDT 24
Peak memory 182428 kb
Host smart-c7633353-7cc8-46ba-8dc2-20a206edb36e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934652826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1934652826
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3749890665
Short name T551
Test name
Test status
Simulation time 20130887 ps
CPU time 0.62 seconds
Started Aug 09 05:34:23 PM PDT 24
Finished Aug 09 05:34:24 PM PDT 24
Peak memory 192296 kb
Host smart-9b8cd997-49bd-484b-803a-7d4fb509f740
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749890665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3749890665
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2929391242
Short name T525
Test name
Test status
Simulation time 285744848 ps
CPU time 2.54 seconds
Started Aug 09 05:34:03 PM PDT 24
Finished Aug 09 05:34:05 PM PDT 24
Peak memory 197584 kb
Host smart-e96cadde-8859-4ec2-9459-0ea1b5ffea1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929391242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2929391242
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2821616134
Short name T114
Test name
Test status
Simulation time 123124226 ps
CPU time 1.31 seconds
Started Aug 09 05:34:13 PM PDT 24
Finished Aug 09 05:34:15 PM PDT 24
Peak memory 183500 kb
Host smart-86465e76-0b4c-429b-a709-375b137ab756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821616134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2821616134
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.523084388
Short name T518
Test name
Test status
Simulation time 39696660 ps
CPU time 1.07 seconds
Started Aug 09 05:34:29 PM PDT 24
Finished Aug 09 05:34:30 PM PDT 24
Peak memory 197420 kb
Host smart-8cff8c0a-c072-4772-b699-cf9bad24652e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523084388 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.523084388
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3446242279
Short name T101
Test name
Test status
Simulation time 34588085 ps
CPU time 0.55 seconds
Started Aug 09 05:34:20 PM PDT 24
Finished Aug 09 05:34:20 PM PDT 24
Peak memory 182948 kb
Host smart-6acc9bdb-bb75-4315-a04e-aeb513945402
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446242279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3446242279
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2249066277
Short name T479
Test name
Test status
Simulation time 21667998 ps
CPU time 0.53 seconds
Started Aug 09 05:34:19 PM PDT 24
Finished Aug 09 05:34:20 PM PDT 24
Peak memory 182720 kb
Host smart-87bd4419-27c4-4605-805c-d1caed95d58c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249066277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2249066277
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2039096471
Short name T108
Test name
Test status
Simulation time 176873358 ps
CPU time 0.84 seconds
Started Aug 09 05:34:27 PM PDT 24
Finished Aug 09 05:34:28 PM PDT 24
Peak memory 191904 kb
Host smart-b0e09b7a-0476-4faa-adf5-dd767838fd6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039096471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2039096471
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1088371731
Short name T529
Test name
Test status
Simulation time 262483532 ps
CPU time 1.05 seconds
Started Aug 09 05:34:11 PM PDT 24
Finished Aug 09 05:34:12 PM PDT 24
Peak memory 197412 kb
Host smart-6a4217f5-5bc1-4c05-970d-50930a5a3f30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088371731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1088371731
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2984449296
Short name T480
Test name
Test status
Simulation time 146900092 ps
CPU time 1.04 seconds
Started Aug 09 05:34:13 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 183324 kb
Host smart-b5634a54-f760-4160-9423-f45b95fff379
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984449296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2984449296
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2793786856
Short name T560
Test name
Test status
Simulation time 29340059 ps
CPU time 0.79 seconds
Started Aug 09 05:34:20 PM PDT 24
Finished Aug 09 05:34:21 PM PDT 24
Peak memory 195912 kb
Host smart-f8d42977-cd50-4624-b29c-cd078cdfd943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793786856 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2793786856
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1477996969
Short name T78
Test name
Test status
Simulation time 11985300 ps
CPU time 0.58 seconds
Started Aug 09 05:34:22 PM PDT 24
Finished Aug 09 05:34:23 PM PDT 24
Peak memory 182868 kb
Host smart-bc6d4a46-be20-4eed-97e1-376bf4295d7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477996969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1477996969
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1381246192
Short name T568
Test name
Test status
Simulation time 13542443 ps
CPU time 0.55 seconds
Started Aug 09 05:34:14 PM PDT 24
Finished Aug 09 05:34:15 PM PDT 24
Peak memory 182592 kb
Host smart-3ee96026-de6e-4772-8428-311d86108e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381246192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1381246192
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.774502967
Short name T569
Test name
Test status
Simulation time 17349894 ps
CPU time 0.74 seconds
Started Aug 09 05:34:25 PM PDT 24
Finished Aug 09 05:34:26 PM PDT 24
Peak memory 192096 kb
Host smart-f324743c-bd18-4df9-9b5c-68869a742aa8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774502967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.774502967
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.585542698
Short name T562
Test name
Test status
Simulation time 112737515 ps
CPU time 1.39 seconds
Started Aug 09 05:34:17 PM PDT 24
Finished Aug 09 05:34:18 PM PDT 24
Peak memory 197512 kb
Host smart-9e27ed47-a2dd-4525-9cc3-3bcb7e7fb5ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585542698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.585542698
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.147906393
Short name T29
Test name
Test status
Simulation time 331585168 ps
CPU time 1.06 seconds
Started Aug 09 05:34:17 PM PDT 24
Finished Aug 09 05:34:19 PM PDT 24
Peak memory 191344 kb
Host smart-3cba9179-d008-45a1-a274-fe009b598a0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147906393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.147906393
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3645880289
Short name T456
Test name
Test status
Simulation time 39847243 ps
CPU time 1.04 seconds
Started Aug 09 05:34:22 PM PDT 24
Finished Aug 09 05:34:23 PM PDT 24
Peak memory 197580 kb
Host smart-0379266f-d212-4731-afe5-1b4e67779284
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645880289 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3645880289
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.589960873
Short name T503
Test name
Test status
Simulation time 41801737 ps
CPU time 0.56 seconds
Started Aug 09 05:34:19 PM PDT 24
Finished Aug 09 05:34:19 PM PDT 24
Peak memory 182824 kb
Host smart-d6e34a91-1d6d-4020-965d-567115540f8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589960873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.589960873
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3943553083
Short name T484
Test name
Test status
Simulation time 41938921 ps
CPU time 0.55 seconds
Started Aug 09 05:34:22 PM PDT 24
Finished Aug 09 05:34:22 PM PDT 24
Peak memory 182592 kb
Host smart-62d2c21c-adf3-4dcb-bc94-fdae69687d4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943553083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3943553083
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.453150639
Short name T507
Test name
Test status
Simulation time 20604111 ps
CPU time 0.8 seconds
Started Aug 09 05:34:15 PM PDT 24
Finished Aug 09 05:34:16 PM PDT 24
Peak memory 193552 kb
Host smart-9adc7b4f-028f-4367-bc51-49f1b3eea2a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453150639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.453150639
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1114540350
Short name T564
Test name
Test status
Simulation time 45970564 ps
CPU time 1.3 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:02 PM PDT 24
Peak memory 197440 kb
Host smart-83702e56-5b1a-44e5-ad93-96f89e371e0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114540350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1114540350
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3175198823
Short name T473
Test name
Test status
Simulation time 84328722 ps
CPU time 1.15 seconds
Started Aug 09 05:34:29 PM PDT 24
Finished Aug 09 05:34:30 PM PDT 24
Peak memory 194320 kb
Host smart-b626cc67-cb6e-409d-8b90-abe98e129e4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175198823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3175198823
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2646907411
Short name T496
Test name
Test status
Simulation time 43244372 ps
CPU time 0.97 seconds
Started Aug 09 05:34:29 PM PDT 24
Finished Aug 09 05:34:30 PM PDT 24
Peak memory 197788 kb
Host smart-b4336a61-a358-4173-bad2-fe868ee96163
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646907411 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2646907411
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3332003823
Short name T102
Test name
Test status
Simulation time 18165859 ps
CPU time 0.65 seconds
Started Aug 09 05:34:02 PM PDT 24
Finished Aug 09 05:34:03 PM PDT 24
Peak memory 182908 kb
Host smart-5fba4057-6794-4c0b-8870-bc2d8cb88bab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332003823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3332003823
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2321220159
Short name T481
Test name
Test status
Simulation time 169199729 ps
CPU time 0.56 seconds
Started Aug 09 05:34:09 PM PDT 24
Finished Aug 09 05:34:10 PM PDT 24
Peak memory 182644 kb
Host smart-153e2c27-9dbc-4d19-89da-2cfa3622433b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321220159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2321220159
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.437166270
Short name T509
Test name
Test status
Simulation time 33685183 ps
CPU time 0.61 seconds
Started Aug 09 05:34:19 PM PDT 24
Finished Aug 09 05:34:19 PM PDT 24
Peak memory 191308 kb
Host smart-0417b895-e9b8-4638-b8b8-77d184ac22d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437166270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.437166270
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1891699313
Short name T531
Test name
Test status
Simulation time 162151803 ps
CPU time 2.12 seconds
Started Aug 09 05:34:16 PM PDT 24
Finished Aug 09 05:34:18 PM PDT 24
Peak memory 197572 kb
Host smart-d21e9253-60d5-4329-a2af-3c7b48ce3864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891699313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1891699313
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2926667697
Short name T527
Test name
Test status
Simulation time 33836976 ps
CPU time 0.8 seconds
Started Aug 09 05:34:29 PM PDT 24
Finished Aug 09 05:34:30 PM PDT 24
Peak memory 195720 kb
Host smart-985aa87b-b531-4584-999a-61d62d6514f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926667697 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2926667697
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3252777078
Short name T555
Test name
Test status
Simulation time 41398465 ps
CPU time 0.54 seconds
Started Aug 09 05:34:11 PM PDT 24
Finished Aug 09 05:34:12 PM PDT 24
Peak memory 182848 kb
Host smart-63eac3c2-730f-45ae-9b36-5afbe66d4afd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252777078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3252777078
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3793378169
Short name T471
Test name
Test status
Simulation time 49641739 ps
CPU time 0.54 seconds
Started Aug 09 05:34:22 PM PDT 24
Finished Aug 09 05:34:23 PM PDT 24
Peak memory 182712 kb
Host smart-96f35a69-964e-41c2-aaea-d20d049a2eef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793378169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3793378169
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.456812443
Short name T59
Test name
Test status
Simulation time 51159719 ps
CPU time 0.74 seconds
Started Aug 09 05:34:20 PM PDT 24
Finished Aug 09 05:34:21 PM PDT 24
Peak memory 193276 kb
Host smart-09cd0b42-4886-4236-bdb1-a3988a51df87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456812443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.456812443
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1811224439
Short name T48
Test name
Test status
Simulation time 183278582 ps
CPU time 1.68 seconds
Started Aug 09 05:34:19 PM PDT 24
Finished Aug 09 05:34:21 PM PDT 24
Peak memory 197664 kb
Host smart-5278c5b4-7af4-4f3b-b5ca-eac5e43595d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811224439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1811224439
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2471123521
Short name T556
Test name
Test status
Simulation time 324602380 ps
CPU time 1.11 seconds
Started Aug 09 05:34:20 PM PDT 24
Finished Aug 09 05:34:21 PM PDT 24
Peak memory 195436 kb
Host smart-3af3dbae-f763-491a-885b-0c17d11fa6e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471123521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2471123521
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2546217257
Short name T533
Test name
Test status
Simulation time 24400433 ps
CPU time 0.7 seconds
Started Aug 09 05:34:34 PM PDT 24
Finished Aug 09 05:34:34 PM PDT 24
Peak memory 194420 kb
Host smart-2db6e34d-9251-4b20-b292-f9e2a42fa5d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546217257 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2546217257
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1856711094
Short name T99
Test name
Test status
Simulation time 14564408 ps
CPU time 0.57 seconds
Started Aug 09 05:34:24 PM PDT 24
Finished Aug 09 05:34:25 PM PDT 24
Peak memory 182800 kb
Host smart-46d4f048-40cd-44ee-9bf3-bf694343a1a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856711094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1856711094
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1670561713
Short name T464
Test name
Test status
Simulation time 13672160 ps
CPU time 0.55 seconds
Started Aug 09 05:34:15 PM PDT 24
Finished Aug 09 05:34:23 PM PDT 24
Peak memory 182596 kb
Host smart-92dce742-57bb-4140-af22-41428b500f33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670561713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1670561713
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1519169847
Short name T106
Test name
Test status
Simulation time 68581632 ps
CPU time 0.61 seconds
Started Aug 09 05:34:28 PM PDT 24
Finished Aug 09 05:34:29 PM PDT 24
Peak memory 191536 kb
Host smart-bac4d1c0-c4f1-4388-bf16-9158299d3ed4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519169847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1519169847
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.421016403
Short name T463
Test name
Test status
Simulation time 63327132 ps
CPU time 1.41 seconds
Started Aug 09 05:34:21 PM PDT 24
Finished Aug 09 05:34:23 PM PDT 24
Peak memory 197652 kb
Host smart-6f828875-9546-4149-8065-019223649197
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421016403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.421016403
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.990097928
Short name T111
Test name
Test status
Simulation time 320287438 ps
CPU time 1.13 seconds
Started Aug 09 05:34:17 PM PDT 24
Finished Aug 09 05:34:18 PM PDT 24
Peak memory 195100 kb
Host smart-4b4e32ec-5a06-463d-a301-5688c30378ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990097928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.990097928
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.466391110
Short name T504
Test name
Test status
Simulation time 211828824 ps
CPU time 0.69 seconds
Started Aug 09 05:34:18 PM PDT 24
Finished Aug 09 05:34:19 PM PDT 24
Peak memory 194260 kb
Host smart-282b616e-7be2-49f4-9112-b7e051ab40fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466391110 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.466391110
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1937821934
Short name T92
Test name
Test status
Simulation time 14192003 ps
CPU time 0.6 seconds
Started Aug 09 05:34:27 PM PDT 24
Finished Aug 09 05:34:28 PM PDT 24
Peak memory 182844 kb
Host smart-1068cf44-9845-44c9-b4a6-1c958070d4ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937821934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1937821934
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.883036813
Short name T476
Test name
Test status
Simulation time 11182036 ps
CPU time 0.53 seconds
Started Aug 09 05:34:24 PM PDT 24
Finished Aug 09 05:34:25 PM PDT 24
Peak memory 182144 kb
Host smart-e2c530d8-e833-42fe-a633-a571898a2be1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883036813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.883036813
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3363595053
Short name T565
Test name
Test status
Simulation time 40255646 ps
CPU time 0.82 seconds
Started Aug 09 05:34:26 PM PDT 24
Finished Aug 09 05:34:27 PM PDT 24
Peak memory 193548 kb
Host smart-973ffdb2-1ff6-4af1-add4-e4b270cc9f06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363595053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3363595053
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3730284277
Short name T461
Test name
Test status
Simulation time 54954430 ps
CPU time 2.63 seconds
Started Aug 09 05:34:32 PM PDT 24
Finished Aug 09 05:34:35 PM PDT 24
Peak memory 197564 kb
Host smart-002336b1-b3dd-4acc-b922-23302f207875
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730284277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3730284277
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.4064088295
Short name T520
Test name
Test status
Simulation time 91166132 ps
CPU time 1.11 seconds
Started Aug 09 05:34:47 PM PDT 24
Finished Aug 09 05:34:48 PM PDT 24
Peak memory 195460 kb
Host smart-17865d04-975e-4cf5-91bb-c69613dacce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064088295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.4064088295
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4247797605
Short name T540
Test name
Test status
Simulation time 129593218 ps
CPU time 0.69 seconds
Started Aug 09 05:34:18 PM PDT 24
Finished Aug 09 05:34:19 PM PDT 24
Peak memory 194564 kb
Host smart-7126552b-9836-489f-9601-6d4ac5a511f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247797605 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4247797605
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3188294824
Short name T94
Test name
Test status
Simulation time 14155716 ps
CPU time 0.56 seconds
Started Aug 09 05:34:15 PM PDT 24
Finished Aug 09 05:34:15 PM PDT 24
Peak memory 182868 kb
Host smart-b467a29b-e20d-4710-b2b4-253d41cff7ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188294824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3188294824
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2362334681
Short name T561
Test name
Test status
Simulation time 13731853 ps
CPU time 0.56 seconds
Started Aug 09 05:34:27 PM PDT 24
Finished Aug 09 05:34:27 PM PDT 24
Peak memory 182280 kb
Host smart-7400da59-7dd4-469c-96df-0505b4775249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362334681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2362334681
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2235845364
Short name T105
Test name
Test status
Simulation time 78759203 ps
CPU time 0.62 seconds
Started Aug 09 05:34:25 PM PDT 24
Finished Aug 09 05:34:26 PM PDT 24
Peak memory 191708 kb
Host smart-13ba2664-0e5d-4383-aec1-fb0cef3892cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235845364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2235845364
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.38550371
Short name T490
Test name
Test status
Simulation time 166259418 ps
CPU time 2.17 seconds
Started Aug 09 05:34:24 PM PDT 24
Finished Aug 09 05:34:26 PM PDT 24
Peak memory 197604 kb
Host smart-395e084d-29f4-4380-9526-078a5c37ab7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38550371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.38550371
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.647164146
Short name T112
Test name
Test status
Simulation time 227532059 ps
CPU time 1 seconds
Started Aug 09 05:34:24 PM PDT 24
Finished Aug 09 05:34:25 PM PDT 24
Peak memory 183284 kb
Host smart-6e366808-b50d-4378-8abd-63d6a2b1c790
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647164146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.647164146
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1055313236
Short name T514
Test name
Test status
Simulation time 83166843 ps
CPU time 0.91 seconds
Started Aug 09 05:34:25 PM PDT 24
Finished Aug 09 05:34:26 PM PDT 24
Peak memory 197456 kb
Host smart-31a19f78-07d9-4c92-823c-d50b9481fa9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055313236 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1055313236
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3045778876
Short name T466
Test name
Test status
Simulation time 17497847 ps
CPU time 0.55 seconds
Started Aug 09 05:34:25 PM PDT 24
Finished Aug 09 05:34:25 PM PDT 24
Peak memory 182924 kb
Host smart-af734191-b268-47f6-b86d-2b14a6bd0a0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045778876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3045778876
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2185814890
Short name T524
Test name
Test status
Simulation time 46257613 ps
CPU time 0.52 seconds
Started Aug 09 05:34:12 PM PDT 24
Finished Aug 09 05:34:12 PM PDT 24
Peak memory 182236 kb
Host smart-8b5044f0-2716-44fb-b3bc-966d7e8edd7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185814890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2185814890
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2475382552
Short name T32
Test name
Test status
Simulation time 63802724 ps
CPU time 0.69 seconds
Started Aug 09 05:34:13 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 193648 kb
Host smart-f2d1397d-4d1c-4838-96dd-49315e06e119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475382552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2475382552
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3778342138
Short name T541
Test name
Test status
Simulation time 711262460 ps
CPU time 2.34 seconds
Started Aug 09 05:34:31 PM PDT 24
Finished Aug 09 05:34:34 PM PDT 24
Peak memory 197580 kb
Host smart-1cce8d19-f3a2-48ba-835d-0fecf5b92f27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778342138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3778342138
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2884644102
Short name T577
Test name
Test status
Simulation time 215962269 ps
CPU time 1.41 seconds
Started Aug 09 05:34:24 PM PDT 24
Finished Aug 09 05:34:26 PM PDT 24
Peak memory 183688 kb
Host smart-5c1f5650-8247-4574-a5ae-0dd547479831
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884644102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2884644102
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1088151819
Short name T492
Test name
Test status
Simulation time 31933420 ps
CPU time 0.62 seconds
Started Aug 09 05:34:22 PM PDT 24
Finished Aug 09 05:34:23 PM PDT 24
Peak memory 182764 kb
Host smart-ad1cf01b-17e3-4799-a3e4-b8c22447218c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088151819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1088151819
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.750286260
Short name T499
Test name
Test status
Simulation time 533503015 ps
CPU time 3.47 seconds
Started Aug 09 05:33:57 PM PDT 24
Finished Aug 09 05:34:01 PM PDT 24
Peak memory 194228 kb
Host smart-e47ea676-dea3-498b-982e-8051d289edd3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750286260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.750286260
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3230631439
Short name T544
Test name
Test status
Simulation time 14755938 ps
CPU time 0.56 seconds
Started Aug 09 05:34:13 PM PDT 24
Finished Aug 09 05:34:13 PM PDT 24
Peak memory 182444 kb
Host smart-0b073bae-ab7a-4442-8ead-2ccfbe241a89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230631439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3230631439
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1389556987
Short name T452
Test name
Test status
Simulation time 22063279 ps
CPU time 1.1 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 197540 kb
Host smart-6a99f980-6218-4ad8-bf5d-9c7df9e05b00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389556987 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1389556987
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.596854820
Short name T505
Test name
Test status
Simulation time 14437283 ps
CPU time 0.6 seconds
Started Aug 09 05:34:08 PM PDT 24
Finished Aug 09 05:34:08 PM PDT 24
Peak memory 182952 kb
Host smart-7807a966-a490-41dc-9e58-e6584aefd362
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596854820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.596854820
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3992223822
Short name T457
Test name
Test status
Simulation time 41834887 ps
CPU time 0.52 seconds
Started Aug 09 05:33:58 PM PDT 24
Finished Aug 09 05:33:59 PM PDT 24
Peak memory 182232 kb
Host smart-3baaf6ea-5215-4b3f-a893-fbf5b5b33829
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992223822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3992223822
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2779935482
Short name T500
Test name
Test status
Simulation time 28418637 ps
CPU time 0.71 seconds
Started Aug 09 05:34:07 PM PDT 24
Finished Aug 09 05:34:08 PM PDT 24
Peak memory 192576 kb
Host smart-6d1c44b9-210f-4616-9016-605e5b9e59b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779935482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2779935482
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.281229460
Short name T508
Test name
Test status
Simulation time 235192525 ps
CPU time 2.51 seconds
Started Aug 09 05:34:05 PM PDT 24
Finished Aug 09 05:34:08 PM PDT 24
Peak memory 197672 kb
Host smart-a7abceb9-d633-491b-bcc5-8ebc880eedb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281229460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.281229460
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2030056733
Short name T552
Test name
Test status
Simulation time 190049852 ps
CPU time 0.85 seconds
Started Aug 09 05:34:20 PM PDT 24
Finished Aug 09 05:34:21 PM PDT 24
Peak memory 193928 kb
Host smart-8c1dc740-526c-41b7-8c87-b4b2f57adde3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030056733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2030056733
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1979106414
Short name T512
Test name
Test status
Simulation time 168362104 ps
CPU time 0.54 seconds
Started Aug 09 05:34:20 PM PDT 24
Finished Aug 09 05:34:21 PM PDT 24
Peak memory 182936 kb
Host smart-c9f61c79-d50d-4bb4-a48a-01b4ce2fd823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979106414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1979106414
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3362362269
Short name T470
Test name
Test status
Simulation time 45957514 ps
CPU time 0.53 seconds
Started Aug 09 05:34:33 PM PDT 24
Finished Aug 09 05:34:33 PM PDT 24
Peak memory 182696 kb
Host smart-f43bb41b-47e7-4013-901b-560211b744aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362362269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3362362269
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3321131613
Short name T454
Test name
Test status
Simulation time 24683480 ps
CPU time 0.56 seconds
Started Aug 09 05:34:23 PM PDT 24
Finished Aug 09 05:34:24 PM PDT 24
Peak memory 182608 kb
Host smart-d0fe5fb7-80dd-459a-aa92-9fc7bdc97c90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321131613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3321131613
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.531632870
Short name T491
Test name
Test status
Simulation time 78025918 ps
CPU time 0.55 seconds
Started Aug 09 05:34:24 PM PDT 24
Finished Aug 09 05:34:25 PM PDT 24
Peak memory 182724 kb
Host smart-8f6ff185-5fa4-41f3-950a-b322f3e35933
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531632870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.531632870
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3273857712
Short name T571
Test name
Test status
Simulation time 12827134 ps
CPU time 0.58 seconds
Started Aug 09 05:34:25 PM PDT 24
Finished Aug 09 05:34:25 PM PDT 24
Peak memory 182148 kb
Host smart-a90daaff-2dd1-424b-97db-491dea7f7a7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273857712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3273857712
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4185144253
Short name T559
Test name
Test status
Simulation time 20275769 ps
CPU time 0.56 seconds
Started Aug 09 05:34:33 PM PDT 24
Finished Aug 09 05:34:33 PM PDT 24
Peak memory 182664 kb
Host smart-d69817b8-1a42-400f-beda-7547575d3a52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185144253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4185144253
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3660750531
Short name T563
Test name
Test status
Simulation time 19816805 ps
CPU time 0.54 seconds
Started Aug 09 05:34:22 PM PDT 24
Finished Aug 09 05:34:23 PM PDT 24
Peak memory 182688 kb
Host smart-206982e4-e962-4c55-b9ec-90dd7ff1f5a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660750531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3660750531
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1274155407
Short name T523
Test name
Test status
Simulation time 18181949 ps
CPU time 0.54 seconds
Started Aug 09 05:34:13 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 182568 kb
Host smart-e0476103-4444-4946-b42d-53357a72254f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274155407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1274155407
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2496462950
Short name T522
Test name
Test status
Simulation time 14947833 ps
CPU time 0.57 seconds
Started Aug 09 05:34:40 PM PDT 24
Finished Aug 09 05:34:40 PM PDT 24
Peak memory 182772 kb
Host smart-94d5009f-ace7-4fc8-9a51-13d9abad0a9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496462950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2496462950
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.327701356
Short name T487
Test name
Test status
Simulation time 40518340 ps
CPU time 0.52 seconds
Started Aug 09 05:34:47 PM PDT 24
Finished Aug 09 05:34:47 PM PDT 24
Peak memory 182404 kb
Host smart-516064e6-22e9-41e7-9cbc-c7fed39d3069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327701356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.327701356
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3114089908
Short name T96
Test name
Test status
Simulation time 20340438 ps
CPU time 0.59 seconds
Started Aug 09 05:34:06 PM PDT 24
Finished Aug 09 05:34:06 PM PDT 24
Peak memory 182872 kb
Host smart-c9c69e41-0a70-4f43-95df-be4f1a43c581
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114089908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3114089908
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1275317717
Short name T97
Test name
Test status
Simulation time 1604475589 ps
CPU time 3.47 seconds
Started Aug 09 05:34:12 PM PDT 24
Finished Aug 09 05:34:15 PM PDT 24
Peak memory 192564 kb
Host smart-f0e0a817-c3fa-4702-ae51-8e49bb5330ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275317717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1275317717
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2342977561
Short name T517
Test name
Test status
Simulation time 15615057 ps
CPU time 0.6 seconds
Started Aug 09 05:34:10 PM PDT 24
Finished Aug 09 05:34:11 PM PDT 24
Peak memory 182780 kb
Host smart-ef8e3063-340a-451a-b506-ed42990461d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342977561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2342977561
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2322545590
Short name T532
Test name
Test status
Simulation time 26579003 ps
CPU time 0.82 seconds
Started Aug 09 05:34:11 PM PDT 24
Finished Aug 09 05:34:12 PM PDT 24
Peak memory 196652 kb
Host smart-0c330eca-cda0-4815-b18d-20abaf35a6f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322545590 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2322545590
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2831053753
Short name T104
Test name
Test status
Simulation time 28083121 ps
CPU time 0.57 seconds
Started Aug 09 05:34:25 PM PDT 24
Finished Aug 09 05:34:26 PM PDT 24
Peak memory 182952 kb
Host smart-96f31427-4102-4f96-bec7-fb1c4e7b3414
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831053753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2831053753
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1285298790
Short name T453
Test name
Test status
Simulation time 76735788 ps
CPU time 0.55 seconds
Started Aug 09 05:34:24 PM PDT 24
Finished Aug 09 05:34:25 PM PDT 24
Peak memory 182640 kb
Host smart-eea223ba-78a6-49d7-9ca1-a6f0f04a0b03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285298790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1285298790
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1497576709
Short name T554
Test name
Test status
Simulation time 162491016 ps
CPU time 0.86 seconds
Started Aug 09 05:34:14 PM PDT 24
Finished Aug 09 05:34:15 PM PDT 24
Peak memory 191804 kb
Host smart-9cde34be-39b5-4305-bb8c-84d9a3c9bb10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497576709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1497576709
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1497174480
Short name T468
Test name
Test status
Simulation time 102955859 ps
CPU time 1.18 seconds
Started Aug 09 05:34:18 PM PDT 24
Finished Aug 09 05:34:19 PM PDT 24
Peak memory 195396 kb
Host smart-492995d3-bfac-465e-8d50-8d0475e7b7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497174480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1497174480
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.183994251
Short name T536
Test name
Test status
Simulation time 67388195 ps
CPU time 0.85 seconds
Started Aug 09 05:34:13 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 193800 kb
Host smart-5a51cacd-e118-48b6-8519-70128340826f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183994251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.183994251
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3641890186
Short name T570
Test name
Test status
Simulation time 13343823 ps
CPU time 0.59 seconds
Started Aug 09 05:34:25 PM PDT 24
Finished Aug 09 05:34:26 PM PDT 24
Peak memory 182732 kb
Host smart-1568db8c-2019-4577-83b6-059b17b28b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641890186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3641890186
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.51095202
Short name T543
Test name
Test status
Simulation time 14662028 ps
CPU time 0.58 seconds
Started Aug 09 05:34:40 PM PDT 24
Finished Aug 09 05:34:41 PM PDT 24
Peak memory 182212 kb
Host smart-306e1864-0dd2-4206-95a0-e7938afc1837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51095202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.51095202
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.365823506
Short name T502
Test name
Test status
Simulation time 13297887 ps
CPU time 0.54 seconds
Started Aug 09 05:34:27 PM PDT 24
Finished Aug 09 05:34:28 PM PDT 24
Peak memory 182236 kb
Host smart-aae4d997-5201-4346-b78e-a4f8ea1aba9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365823506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.365823506
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2105537856
Short name T510
Test name
Test status
Simulation time 85609042 ps
CPU time 0.53 seconds
Started Aug 09 05:34:31 PM PDT 24
Finished Aug 09 05:34:31 PM PDT 24
Peak memory 182696 kb
Host smart-88f90159-f802-4804-9fb3-9164a943ea39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105537856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2105537856
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.114049902
Short name T462
Test name
Test status
Simulation time 34518036 ps
CPU time 0.53 seconds
Started Aug 09 05:34:17 PM PDT 24
Finished Aug 09 05:34:18 PM PDT 24
Peak memory 182660 kb
Host smart-7b24b281-8e30-4935-bcf3-983f81df1b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114049902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.114049902
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3828885685
Short name T482
Test name
Test status
Simulation time 55076700 ps
CPU time 0.54 seconds
Started Aug 09 05:34:16 PM PDT 24
Finished Aug 09 05:34:16 PM PDT 24
Peak memory 182692 kb
Host smart-0cc5319f-c08e-49c3-9765-bc290b3ef75e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828885685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3828885685
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2619856444
Short name T494
Test name
Test status
Simulation time 10453345 ps
CPU time 0.53 seconds
Started Aug 09 05:34:38 PM PDT 24
Finished Aug 09 05:34:38 PM PDT 24
Peak memory 182224 kb
Host smart-6b78c410-16c2-4d5e-bc10-dd1512f15a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619856444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2619856444
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1929009633
Short name T537
Test name
Test status
Simulation time 33300513 ps
CPU time 0.56 seconds
Started Aug 09 05:34:30 PM PDT 24
Finished Aug 09 05:34:31 PM PDT 24
Peak memory 182676 kb
Host smart-4880d278-8100-4bcd-907c-46542a8bd369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929009633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1929009633
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1895800571
Short name T450
Test name
Test status
Simulation time 22593490 ps
CPU time 0.59 seconds
Started Aug 09 05:35:19 PM PDT 24
Finished Aug 09 05:35:20 PM PDT 24
Peak memory 181252 kb
Host smart-f9b2fbf7-d719-4cce-b4a7-c1d8066ef7c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895800571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1895800571
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3670785371
Short name T578
Test name
Test status
Simulation time 184009159 ps
CPU time 0.56 seconds
Started Aug 09 05:34:34 PM PDT 24
Finished Aug 09 05:34:35 PM PDT 24
Peak memory 182772 kb
Host smart-021bb5df-529e-4f16-b466-16b6d4fbd4cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670785371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3670785371
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3639401633
Short name T100
Test name
Test status
Simulation time 51989262 ps
CPU time 0.81 seconds
Started Aug 09 05:34:24 PM PDT 24
Finished Aug 09 05:34:25 PM PDT 24
Peak memory 182848 kb
Host smart-b4751aaa-65e5-4757-a85d-a47614c755f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639401633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3639401633
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3682893322
Short name T485
Test name
Test status
Simulation time 300852689 ps
CPU time 1.73 seconds
Started Aug 09 05:34:25 PM PDT 24
Finished Aug 09 05:34:27 PM PDT 24
Peak memory 191304 kb
Host smart-7bc739a9-68ba-4adc-be6a-b22c6f8e9e4a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682893322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3682893322
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2505224507
Short name T110
Test name
Test status
Simulation time 97503878 ps
CPU time 0.56 seconds
Started Aug 09 05:34:27 PM PDT 24
Finished Aug 09 05:34:27 PM PDT 24
Peak memory 182880 kb
Host smart-210cf767-b48e-496c-b7af-359c4b53d1c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505224507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2505224507
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2127979965
Short name T558
Test name
Test status
Simulation time 14300472 ps
CPU time 0.69 seconds
Started Aug 09 05:34:25 PM PDT 24
Finished Aug 09 05:34:26 PM PDT 24
Peak memory 194800 kb
Host smart-61ebbd3b-8469-44fd-9614-3ac6390d5daf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127979965 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2127979965
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3146554192
Short name T475
Test name
Test status
Simulation time 14283584 ps
CPU time 0.55 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:05 PM PDT 24
Peak memory 182916 kb
Host smart-9fc70349-6a87-48b8-b741-93ffaa29506f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146554192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3146554192
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.509981443
Short name T576
Test name
Test status
Simulation time 60841047 ps
CPU time 0.56 seconds
Started Aug 09 05:34:13 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 182616 kb
Host smart-9c5ae547-fdc5-410b-b517-a684848dd54f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509981443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.509981443
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.6431199
Short name T103
Test name
Test status
Simulation time 55872617 ps
CPU time 0.72 seconds
Started Aug 09 05:34:14 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 191784 kb
Host smart-7b2a6ccb-19b0-4483-9c7e-b495cc7e6fc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6431199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_t
imer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer
_same_csr_outstanding.6431199
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3073512063
Short name T538
Test name
Test status
Simulation time 35914850 ps
CPU time 1.34 seconds
Started Aug 09 05:33:58 PM PDT 24
Finished Aug 09 05:33:59 PM PDT 24
Peak memory 197652 kb
Host smart-11259afc-4758-42f7-8b67-79855898bea1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073512063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3073512063
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2054859099
Short name T574
Test name
Test status
Simulation time 138434333 ps
CPU time 1.33 seconds
Started Aug 09 05:34:14 PM PDT 24
Finished Aug 09 05:34:16 PM PDT 24
Peak memory 183592 kb
Host smart-d10a4ca6-c7eb-4d4d-8f9f-366c1c6494e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054859099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2054859099
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1421548602
Short name T549
Test name
Test status
Simulation time 126522492 ps
CPU time 0.62 seconds
Started Aug 09 05:34:31 PM PDT 24
Finished Aug 09 05:34:31 PM PDT 24
Peak memory 182696 kb
Host smart-160147e8-a43b-4fbc-93cc-a2390754c0a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421548602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1421548602
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.4096393214
Short name T455
Test name
Test status
Simulation time 15026917 ps
CPU time 0.55 seconds
Started Aug 09 05:34:37 PM PDT 24
Finished Aug 09 05:34:38 PM PDT 24
Peak memory 182232 kb
Host smart-93b0ae80-fce3-4a5a-bd66-a6ca45c7701d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096393214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.4096393214
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1651528445
Short name T515
Test name
Test status
Simulation time 15615366 ps
CPU time 0.53 seconds
Started Aug 09 05:34:16 PM PDT 24
Finished Aug 09 05:34:16 PM PDT 24
Peak memory 182272 kb
Host smart-49a4a3d3-e479-466d-9c2b-a9f9f630da62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651528445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1651528445
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3289505447
Short name T528
Test name
Test status
Simulation time 31150567 ps
CPU time 0.54 seconds
Started Aug 09 05:34:19 PM PDT 24
Finished Aug 09 05:34:20 PM PDT 24
Peak memory 182676 kb
Host smart-094037e1-f6fd-4906-99bc-8e0b1608cbe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289505447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3289505447
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1801012358
Short name T553
Test name
Test status
Simulation time 13007348 ps
CPU time 0.53 seconds
Started Aug 09 05:34:43 PM PDT 24
Finished Aug 09 05:34:44 PM PDT 24
Peak memory 182208 kb
Host smart-19e19fca-8aea-4a8d-8c69-634ec754e38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801012358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1801012358
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1950306455
Short name T526
Test name
Test status
Simulation time 21655766 ps
CPU time 0.55 seconds
Started Aug 09 05:34:32 PM PDT 24
Finished Aug 09 05:34:32 PM PDT 24
Peak memory 182424 kb
Host smart-e644890e-f071-41f8-8194-8421ca4853d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950306455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1950306455
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3197391327
Short name T550
Test name
Test status
Simulation time 249191894 ps
CPU time 0.61 seconds
Started Aug 09 05:34:22 PM PDT 24
Finished Aug 09 05:34:23 PM PDT 24
Peak memory 182668 kb
Host smart-997148cf-a0dd-4914-b3b4-b18ae49e4566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197391327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3197391327
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2153703082
Short name T486
Test name
Test status
Simulation time 43888621 ps
CPU time 0.54 seconds
Started Aug 09 05:34:44 PM PDT 24
Finished Aug 09 05:34:45 PM PDT 24
Peak memory 182608 kb
Host smart-631e4b7e-2251-410c-a3ad-5dd9282bc0bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153703082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2153703082
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3086828135
Short name T566
Test name
Test status
Simulation time 155268290 ps
CPU time 0.54 seconds
Started Aug 09 05:34:26 PM PDT 24
Finished Aug 09 05:34:26 PM PDT 24
Peak memory 182124 kb
Host smart-66af4c1d-0542-4b2a-abab-a501d9104220
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086828135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3086828135
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2083689494
Short name T521
Test name
Test status
Simulation time 38420697 ps
CPU time 0.57 seconds
Started Aug 09 05:34:29 PM PDT 24
Finished Aug 09 05:34:30 PM PDT 24
Peak memory 182764 kb
Host smart-d3504159-c84d-44c6-99f5-a8bb2402ff06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083689494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2083689494
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1383943211
Short name T498
Test name
Test status
Simulation time 16211754 ps
CPU time 0.77 seconds
Started Aug 09 05:34:15 PM PDT 24
Finished Aug 09 05:34:16 PM PDT 24
Peak memory 195620 kb
Host smart-7f443772-b241-4bbc-aa85-b3fe92d65290
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383943211 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1383943211
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3401802862
Short name T534
Test name
Test status
Simulation time 16702340 ps
CPU time 0.55 seconds
Started Aug 09 05:34:14 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 182564 kb
Host smart-d1414707-0db2-4fb2-a9b4-a5c082ee5133
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401802862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3401802862
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2012676970
Short name T519
Test name
Test status
Simulation time 79415563 ps
CPU time 0.58 seconds
Started Aug 09 05:34:19 PM PDT 24
Finished Aug 09 05:34:20 PM PDT 24
Peak memory 182256 kb
Host smart-d6409b45-9c2e-4486-ba83-c7303093af8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012676970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2012676970
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3198026616
Short name T107
Test name
Test status
Simulation time 20093818 ps
CPU time 0.77 seconds
Started Aug 09 05:34:13 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 193516 kb
Host smart-b3a05e85-69c1-4d56-8b16-8150e897b622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198026616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3198026616
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2568238266
Short name T572
Test name
Test status
Simulation time 49441375 ps
CPU time 2.35 seconds
Started Aug 09 05:34:37 PM PDT 24
Finished Aug 09 05:34:40 PM PDT 24
Peak memory 197584 kb
Host smart-16fb8169-a5e3-4148-98be-311cb61c36c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568238266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2568238266
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.22787772
Short name T460
Test name
Test status
Simulation time 105671453 ps
CPU time 0.9 seconds
Started Aug 09 05:34:12 PM PDT 24
Finished Aug 09 05:34:13 PM PDT 24
Peak memory 193804 kb
Host smart-59115a40-0c24-463e-9719-4c89e4f665ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22787772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg
_err.22787772
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.979977293
Short name T31
Test name
Test status
Simulation time 30354261 ps
CPU time 0.76 seconds
Started Aug 09 05:34:22 PM PDT 24
Finished Aug 09 05:34:23 PM PDT 24
Peak memory 195660 kb
Host smart-2c29df46-c9d6-4d65-80db-d9455fb7952c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979977293 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.979977293
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.888285653
Short name T477
Test name
Test status
Simulation time 88164252 ps
CPU time 0.57 seconds
Started Aug 09 05:34:25 PM PDT 24
Finished Aug 09 05:34:26 PM PDT 24
Peak memory 182824 kb
Host smart-e8487882-73df-4cb4-8b31-523d7f48d449
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888285653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.888285653
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1973648756
Short name T506
Test name
Test status
Simulation time 28170009 ps
CPU time 0.56 seconds
Started Aug 09 05:34:15 PM PDT 24
Finished Aug 09 05:34:15 PM PDT 24
Peak memory 182676 kb
Host smart-aed39793-44e2-4cfa-8f92-f63b4516fa87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973648756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1973648756
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3516506284
Short name T513
Test name
Test status
Simulation time 50057470 ps
CPU time 0.68 seconds
Started Aug 09 05:34:06 PM PDT 24
Finished Aug 09 05:34:07 PM PDT 24
Peak memory 191748 kb
Host smart-45bba623-ac00-414a-b2c7-377092fbdc33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516506284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3516506284
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.967324970
Short name T451
Test name
Test status
Simulation time 40760883 ps
CPU time 0.99 seconds
Started Aug 09 05:34:24 PM PDT 24
Finished Aug 09 05:34:25 PM PDT 24
Peak memory 197064 kb
Host smart-86e797f9-5168-40ae-8ec0-3bf694ae3da8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967324970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.967324970
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2221995562
Short name T474
Test name
Test status
Simulation time 87468073 ps
CPU time 1.04 seconds
Started Aug 09 05:34:24 PM PDT 24
Finished Aug 09 05:34:25 PM PDT 24
Peak memory 183508 kb
Host smart-44755f5c-3e31-4118-a43e-89b4a6e7bc31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221995562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2221995562
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2473453509
Short name T546
Test name
Test status
Simulation time 46420438 ps
CPU time 0.86 seconds
Started Aug 09 05:34:09 PM PDT 24
Finished Aug 09 05:34:10 PM PDT 24
Peak memory 196876 kb
Host smart-fa500fa3-c431-4d66-825f-f32c0a70001d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473453509 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2473453509
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1828364728
Short name T493
Test name
Test status
Simulation time 12585136 ps
CPU time 0.51 seconds
Started Aug 09 05:34:16 PM PDT 24
Finished Aug 09 05:34:16 PM PDT 24
Peak memory 182208 kb
Host smart-5bf1ff82-3d26-495f-923b-00cb21369396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828364728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1828364728
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2528701118
Short name T497
Test name
Test status
Simulation time 106140033 ps
CPU time 0.74 seconds
Started Aug 09 05:34:07 PM PDT 24
Finished Aug 09 05:34:08 PM PDT 24
Peak memory 191816 kb
Host smart-21c46643-45d4-4bf9-a430-ede7f6197bb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528701118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2528701118
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1255467096
Short name T488
Test name
Test status
Simulation time 58297292 ps
CPU time 2.84 seconds
Started Aug 09 05:34:12 PM PDT 24
Finished Aug 09 05:34:15 PM PDT 24
Peak memory 197680 kb
Host smart-10542c25-ea93-4584-8a39-bac01cac47b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255467096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1255467096
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3652733687
Short name T113
Test name
Test status
Simulation time 608484184 ps
CPU time 1.35 seconds
Started Aug 09 05:34:00 PM PDT 24
Finished Aug 09 05:34:02 PM PDT 24
Peak memory 195428 kb
Host smart-53ceef4b-e2c1-444b-98d6-a1c04b6cdcf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652733687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3652733687
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3916727689
Short name T465
Test name
Test status
Simulation time 17185299 ps
CPU time 0.65 seconds
Started Aug 09 05:34:13 PM PDT 24
Finished Aug 09 05:34:14 PM PDT 24
Peak memory 194700 kb
Host smart-aa17cad6-57fa-4e55-ad50-fbedd9f43793
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916727689 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3916727689
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.187251322
Short name T49
Test name
Test status
Simulation time 97955205 ps
CPU time 0.61 seconds
Started Aug 09 05:34:14 PM PDT 24
Finished Aug 09 05:34:15 PM PDT 24
Peak memory 182972 kb
Host smart-9ec613a7-9616-4ccf-b791-869fc751b947
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187251322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.187251322
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4115413538
Short name T467
Test name
Test status
Simulation time 13248154 ps
CPU time 0.54 seconds
Started Aug 09 05:34:26 PM PDT 24
Finished Aug 09 05:34:27 PM PDT 24
Peak memory 182724 kb
Host smart-9c5bdc08-9d31-4192-a403-f9c0d71222fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115413538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.4115413538
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4213559799
Short name T535
Test name
Test status
Simulation time 58231398 ps
CPU time 0.72 seconds
Started Aug 09 05:34:22 PM PDT 24
Finished Aug 09 05:34:23 PM PDT 24
Peak memory 193516 kb
Host smart-eeb930c0-c237-4bb2-a41f-45a2d60799b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213559799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.4213559799
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3508325572
Short name T472
Test name
Test status
Simulation time 136683513 ps
CPU time 2.16 seconds
Started Aug 09 05:34:06 PM PDT 24
Finished Aug 09 05:34:08 PM PDT 24
Peak memory 197564 kb
Host smart-6a788b72-085b-4dcc-a01b-40ec37ad4056
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508325572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3508325572
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1324060874
Short name T30
Test name
Test status
Simulation time 414257829 ps
CPU time 1.4 seconds
Started Aug 09 05:34:17 PM PDT 24
Finished Aug 09 05:34:18 PM PDT 24
Peak memory 195416 kb
Host smart-4f9ea3b6-1a3e-4526-9159-479647d0b683
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324060874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1324060874
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.652671610
Short name T542
Test name
Test status
Simulation time 24535999 ps
CPU time 1.09 seconds
Started Aug 09 05:34:02 PM PDT 24
Finished Aug 09 05:34:03 PM PDT 24
Peak memory 197668 kb
Host smart-2016c68b-52c7-4a63-8132-e3679746cb8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652671610 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.652671610
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.291604419
Short name T483
Test name
Test status
Simulation time 43293636 ps
CPU time 0.56 seconds
Started Aug 09 05:34:09 PM PDT 24
Finished Aug 09 05:34:10 PM PDT 24
Peak memory 182972 kb
Host smart-dc07b897-0c7b-4d65-acc4-c02e9eb5c043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291604419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.291604419
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1689155994
Short name T458
Test name
Test status
Simulation time 24813641 ps
CPU time 0.53 seconds
Started Aug 09 05:34:04 PM PDT 24
Finished Aug 09 05:34:10 PM PDT 24
Peak memory 182748 kb
Host smart-3b566ff9-e9e9-4c82-aef2-e4b36ca0a572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689155994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1689155994
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2708920585
Short name T573
Test name
Test status
Simulation time 82658171 ps
CPU time 0.82 seconds
Started Aug 09 05:34:12 PM PDT 24
Finished Aug 09 05:34:13 PM PDT 24
Peak memory 191124 kb
Host smart-17012576-99f1-41aa-9642-b7a559ec549e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708920585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2708920585
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2864883914
Short name T511
Test name
Test status
Simulation time 143141556 ps
CPU time 1.44 seconds
Started Aug 09 05:34:21 PM PDT 24
Finished Aug 09 05:34:23 PM PDT 24
Peak memory 197348 kb
Host smart-06fa0d83-6140-404a-a7cc-101b01338ce7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864883914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2864883914
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1688160425
Short name T545
Test name
Test status
Simulation time 686656714 ps
CPU time 1.06 seconds
Started Aug 09 05:34:22 PM PDT 24
Finished Aug 09 05:34:24 PM PDT 24
Peak memory 183272 kb
Host smart-b75addbf-31dd-42a9-8c79-16e32e2f7c71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688160425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1688160425
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3276560573
Short name T170
Test name
Test status
Simulation time 51164764706 ps
CPU time 79.93 seconds
Started Aug 09 04:32:18 PM PDT 24
Finished Aug 09 04:33:38 PM PDT 24
Peak memory 183256 kb
Host smart-fb4b4b9f-91eb-4d0f-8b5a-e630d18bc166
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276560573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3276560573
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.528689679
Short name T365
Test name
Test status
Simulation time 364740567370 ps
CPU time 160.04 seconds
Started Aug 09 04:32:27 PM PDT 24
Finished Aug 09 04:35:08 PM PDT 24
Peak memory 183280 kb
Host smart-bfa6837c-3682-4443-a2ae-e5753829b8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528689679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.528689679
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.36931597
Short name T85
Test name
Test status
Simulation time 219415445264 ps
CPU time 231.2 seconds
Started Aug 09 04:32:59 PM PDT 24
Finished Aug 09 04:36:50 PM PDT 24
Peak memory 183224 kb
Host smart-e1fd45b4-bfe4-401c-84b5-3c2cdfcd1874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36931597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.36931597
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2553808722
Short name T178
Test name
Test status
Simulation time 350719321668 ps
CPU time 322 seconds
Started Aug 09 04:32:43 PM PDT 24
Finished Aug 09 04:38:05 PM PDT 24
Peak memory 183276 kb
Host smart-85761c6c-dd3e-4bfa-92bb-b45228e5a9c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553808722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2553808722
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3549641295
Short name T401
Test name
Test status
Simulation time 137855410429 ps
CPU time 201.17 seconds
Started Aug 09 04:32:23 PM PDT 24
Finished Aug 09 04:35:45 PM PDT 24
Peak memory 183276 kb
Host smart-07e8107d-5511-46d2-a8df-d2ee1d2ff64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549641295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3549641295
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.966985227
Short name T181
Test name
Test status
Simulation time 113351992870 ps
CPU time 166.37 seconds
Started Aug 09 04:32:18 PM PDT 24
Finished Aug 09 04:35:05 PM PDT 24
Peak memory 191460 kb
Host smart-8d9e20b7-9624-4769-a661-380762a97cc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966985227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.966985227
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2205148341
Short name T15
Test name
Test status
Simulation time 271861140 ps
CPU time 0.94 seconds
Started Aug 09 04:32:32 PM PDT 24
Finished Aug 09 04:32:43 PM PDT 24
Peak memory 214880 kb
Host smart-25910202-f579-4b1f-ab19-05c55c1e86da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205148341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2205148341
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2793889881
Short name T38
Test name
Test status
Simulation time 208679435172 ps
CPU time 742.48 seconds
Started Aug 09 04:32:25 PM PDT 24
Finished Aug 09 04:44:47 PM PDT 24
Peak memory 211488 kb
Host smart-7e678820-21bd-4baf-a879-4f451c590256
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793889881 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2793889881
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1370237196
Short name T385
Test name
Test status
Simulation time 28931771063 ps
CPU time 48.02 seconds
Started Aug 09 04:32:45 PM PDT 24
Finished Aug 09 04:33:33 PM PDT 24
Peak memory 183220 kb
Host smart-86f85a43-fe38-402f-be07-5ba81223ce7e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370237196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1370237196
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.60597484
Short name T443
Test name
Test status
Simulation time 448546912375 ps
CPU time 205.24 seconds
Started Aug 09 04:33:02 PM PDT 24
Finished Aug 09 04:36:27 PM PDT 24
Peak memory 183264 kb
Host smart-1b85ae34-050d-4bcd-a8db-52aa1664875f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60597484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.60597484
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.721774839
Short name T257
Test name
Test status
Simulation time 26506648881 ps
CPU time 247.71 seconds
Started Aug 09 04:32:39 PM PDT 24
Finished Aug 09 04:36:47 PM PDT 24
Peak memory 183284 kb
Host smart-6ea2959c-3662-4562-8967-d0b71ae3c739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721774839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.721774839
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2983764402
Short name T12
Test name
Test status
Simulation time 154971354299 ps
CPU time 556.22 seconds
Started Aug 09 04:32:35 PM PDT 24
Finished Aug 09 04:41:51 PM PDT 24
Peak memory 206264 kb
Host smart-45674823-62b0-4cfc-b2cc-eea2f1189427
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983764402 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2983764402
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.3685967282
Short name T338
Test name
Test status
Simulation time 231991381730 ps
CPU time 218.48 seconds
Started Aug 09 04:33:15 PM PDT 24
Finished Aug 09 04:36:54 PM PDT 24
Peak memory 191512 kb
Host smart-53bb5980-fdd1-4a35-a0bd-8059fb937892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685967282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3685967282
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.246480040
Short name T428
Test name
Test status
Simulation time 209853130733 ps
CPU time 336.28 seconds
Started Aug 09 04:33:09 PM PDT 24
Finished Aug 09 04:38:46 PM PDT 24
Peak memory 191476 kb
Host smart-4872e50d-5c51-4b08-a760-623098941ebb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246480040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.246480040
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.892415812
Short name T20
Test name
Test status
Simulation time 226848130899 ps
CPU time 381.27 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:39:34 PM PDT 24
Peak memory 191496 kb
Host smart-894df31e-5f58-467d-951e-5bc6fbafbe21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892415812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.892415812
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3414487031
Short name T324
Test name
Test status
Simulation time 105626210094 ps
CPU time 174.73 seconds
Started Aug 09 04:33:14 PM PDT 24
Finished Aug 09 04:36:09 PM PDT 24
Peak memory 191548 kb
Host smart-6d77883f-6769-43b9-9305-9706f8fb0a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414487031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3414487031
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3103594807
Short name T290
Test name
Test status
Simulation time 83876141555 ps
CPU time 284.82 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:38:01 PM PDT 24
Peak memory 191476 kb
Host smart-8ccbf1ea-ee30-4a31-8d71-999893593504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103594807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3103594807
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.419315922
Short name T228
Test name
Test status
Simulation time 12823137331 ps
CPU time 75.08 seconds
Started Aug 09 04:33:22 PM PDT 24
Finished Aug 09 04:34:37 PM PDT 24
Peak memory 191516 kb
Host smart-21b95fa9-c652-44ec-a834-e387055105f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419315922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.419315922
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1155966499
Short name T7
Test name
Test status
Simulation time 85148998864 ps
CPU time 91.4 seconds
Started Aug 09 04:33:14 PM PDT 24
Finished Aug 09 04:34:45 PM PDT 24
Peak memory 191516 kb
Host smart-4eb86bab-cff1-4f0e-b660-dc0a1c937b1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155966499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1155966499
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1164540192
Short name T369
Test name
Test status
Simulation time 9402538113 ps
CPU time 14.7 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:33:31 PM PDT 24
Peak memory 183260 kb
Host smart-fed40873-3880-4f21-8641-9511d395950d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164540192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1164540192
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3658433056
Short name T179
Test name
Test status
Simulation time 666790822073 ps
CPU time 1002.7 seconds
Started Aug 09 04:32:43 PM PDT 24
Finished Aug 09 04:49:26 PM PDT 24
Peak memory 183228 kb
Host smart-5343b15b-7686-4267-be34-d553351d30fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658433056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3658433056
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.915855911
Short name T381
Test name
Test status
Simulation time 47675011523 ps
CPU time 68.04 seconds
Started Aug 09 04:33:04 PM PDT 24
Finished Aug 09 04:34:13 PM PDT 24
Peak memory 183416 kb
Host smart-8a694fb7-6b1b-4fc6-b89d-bd412a08e2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915855911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.915855911
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.738375244
Short name T268
Test name
Test status
Simulation time 379697424136 ps
CPU time 243.1 seconds
Started Aug 09 04:32:29 PM PDT 24
Finished Aug 09 04:36:33 PM PDT 24
Peak memory 191464 kb
Host smart-82232b6e-1658-4c9a-a306-856a22b183f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738375244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.738375244
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3230032327
Short name T323
Test name
Test status
Simulation time 58467422742 ps
CPU time 99.12 seconds
Started Aug 09 04:32:41 PM PDT 24
Finished Aug 09 04:34:21 PM PDT 24
Peak memory 191500 kb
Host smart-f5d56a6d-d637-46de-805c-be4a93391669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230032327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3230032327
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/112.rv_timer_random.3746948162
Short name T333
Test name
Test status
Simulation time 22608682926 ps
CPU time 178.66 seconds
Started Aug 09 04:33:23 PM PDT 24
Finished Aug 09 04:36:22 PM PDT 24
Peak memory 183308 kb
Host smart-d04514b0-1521-4246-8f55-0af40664e8ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746948162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3746948162
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1221257430
Short name T203
Test name
Test status
Simulation time 80547408536 ps
CPU time 128 seconds
Started Aug 09 04:33:29 PM PDT 24
Finished Aug 09 04:35:37 PM PDT 24
Peak memory 191380 kb
Host smart-c6f586d0-491b-4634-846a-039ea35676a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221257430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1221257430
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3877859294
Short name T448
Test name
Test status
Simulation time 95339644526 ps
CPU time 144.29 seconds
Started Aug 09 04:33:35 PM PDT 24
Finished Aug 09 04:36:00 PM PDT 24
Peak memory 194472 kb
Host smart-fda32edd-843f-489c-b7d9-374f61e672a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877859294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3877859294
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3539878104
Short name T199
Test name
Test status
Simulation time 291042395329 ps
CPU time 498.14 seconds
Started Aug 09 04:33:19 PM PDT 24
Finished Aug 09 04:41:37 PM PDT 24
Peak memory 191448 kb
Host smart-0b818d5f-f27e-4fc0-a314-35b1a73b0c89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539878104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3539878104
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3551900019
Short name T438
Test name
Test status
Simulation time 873660262349 ps
CPU time 272.39 seconds
Started Aug 09 04:33:18 PM PDT 24
Finished Aug 09 04:37:50 PM PDT 24
Peak memory 191500 kb
Host smart-5a5913ff-9dc9-4bb2-9f0c-3e0d311b786a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551900019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3551900019
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1442505740
Short name T43
Test name
Test status
Simulation time 228193134121 ps
CPU time 139.54 seconds
Started Aug 09 04:33:09 PM PDT 24
Finished Aug 09 04:35:29 PM PDT 24
Peak memory 191528 kb
Host smart-1d65377a-8ff6-4d7c-9634-ff67762e9694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442505740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1442505740
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3304127218
Short name T245
Test name
Test status
Simulation time 173223828571 ps
CPU time 282.82 seconds
Started Aug 09 04:32:44 PM PDT 24
Finished Aug 09 04:37:27 PM PDT 24
Peak memory 183212 kb
Host smart-becd85da-944c-4a59-8d46-e71afbebad48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304127218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3304127218
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3930313850
Short name T373
Test name
Test status
Simulation time 196296701182 ps
CPU time 130.29 seconds
Started Aug 09 04:32:35 PM PDT 24
Finished Aug 09 04:34:46 PM PDT 24
Peak memory 183236 kb
Host smart-d8203eaf-f1cb-4e1c-a912-fb92911ccb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930313850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3930313850
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3001171604
Short name T55
Test name
Test status
Simulation time 107942653625 ps
CPU time 417.7 seconds
Started Aug 09 04:32:32 PM PDT 24
Finished Aug 09 04:39:30 PM PDT 24
Peak memory 191548 kb
Host smart-1996451f-8fd4-410d-be06-8e9879d001da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001171604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3001171604
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.2431256082
Short name T347
Test name
Test status
Simulation time 29615963983 ps
CPU time 280.97 seconds
Started Aug 09 04:33:18 PM PDT 24
Finished Aug 09 04:37:59 PM PDT 24
Peak memory 191496 kb
Host smart-b89e55b2-72e7-42c7-a64b-97aa0a1dc328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431256082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2431256082
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3801515562
Short name T439
Test name
Test status
Simulation time 31255958022 ps
CPU time 403.25 seconds
Started Aug 09 04:33:22 PM PDT 24
Finished Aug 09 04:40:05 PM PDT 24
Peak memory 183280 kb
Host smart-fb8f1891-26b7-4477-96f5-a9a4080d3efc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801515562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3801515562
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3599860563
Short name T288
Test name
Test status
Simulation time 48838788540 ps
CPU time 106.37 seconds
Started Aug 09 04:33:29 PM PDT 24
Finished Aug 09 04:35:16 PM PDT 24
Peak memory 191552 kb
Host smart-5d021fb4-6d14-4f3b-b01c-2fb19e7234db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599860563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3599860563
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1956299087
Short name T341
Test name
Test status
Simulation time 45146188765 ps
CPU time 66.24 seconds
Started Aug 09 04:33:34 PM PDT 24
Finished Aug 09 04:34:40 PM PDT 24
Peak memory 183416 kb
Host smart-38abc210-d3e9-4908-b6b2-75d2a2b08848
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956299087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1956299087
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3274709929
Short name T150
Test name
Test status
Simulation time 365893467626 ps
CPU time 595 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:43:12 PM PDT 24
Peak memory 191480 kb
Host smart-a2e72be9-b863-4622-a129-f26e3339cd9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274709929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3274709929
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.616713424
Short name T410
Test name
Test status
Simulation time 960051443104 ps
CPU time 530.96 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:42:03 PM PDT 24
Peak memory 191560 kb
Host smart-a7142ce3-aee5-4df6-9047-2fb0735dbd25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616713424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.616713424
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.227679793
Short name T325
Test name
Test status
Simulation time 167962037127 ps
CPU time 217.64 seconds
Started Aug 09 04:33:27 PM PDT 24
Finished Aug 09 04:37:05 PM PDT 24
Peak memory 191472 kb
Host smart-279c0007-18c2-4000-a001-33faa706f5d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227679793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.227679793
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2044937415
Short name T296
Test name
Test status
Simulation time 3824047525 ps
CPU time 6.25 seconds
Started Aug 09 04:33:10 PM PDT 24
Finished Aug 09 04:33:16 PM PDT 24
Peak memory 183072 kb
Host smart-7201af35-0915-4e31-8f94-7c8d2d97f168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044937415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2044937415
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1063049770
Short name T308
Test name
Test status
Simulation time 39627316926 ps
CPU time 48.66 seconds
Started Aug 09 04:32:50 PM PDT 24
Finished Aug 09 04:33:39 PM PDT 24
Peak memory 183260 kb
Host smart-1591e4d5-0198-4071-8be5-0cacf09aa0ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063049770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1063049770
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1115836934
Short name T420
Test name
Test status
Simulation time 62681332475 ps
CPU time 95.34 seconds
Started Aug 09 04:33:13 PM PDT 24
Finished Aug 09 04:34:49 PM PDT 24
Peak memory 183252 kb
Host smart-f9af9b96-3628-4486-a6f8-dd27236552c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115836934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1115836934
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.56995624
Short name T129
Test name
Test status
Simulation time 31912505393 ps
CPU time 330.96 seconds
Started Aug 09 04:32:48 PM PDT 24
Finished Aug 09 04:38:20 PM PDT 24
Peak memory 195272 kb
Host smart-ee9de315-a67f-4732-9faa-8ac7eb4b2816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56995624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.56995624
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.4235287037
Short name T279
Test name
Test status
Simulation time 58486490709 ps
CPU time 32.97 seconds
Started Aug 09 04:33:01 PM PDT 24
Finished Aug 09 04:33:34 PM PDT 24
Peak memory 183308 kb
Host smart-6cd20364-89c7-4bd4-ac48-8624b6eff4c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235287037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.4235287037
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.258325277
Short name T193
Test name
Test status
Simulation time 55113072014 ps
CPU time 271.13 seconds
Started Aug 09 04:33:18 PM PDT 24
Finished Aug 09 04:37:49 PM PDT 24
Peak memory 191520 kb
Host smart-a6970a06-8c92-483f-b437-97f1116e3ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258325277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.258325277
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.182670850
Short name T277
Test name
Test status
Simulation time 110044118709 ps
CPU time 80.11 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:34:26 PM PDT 24
Peak memory 191500 kb
Host smart-e8a2620c-af06-480d-988d-8ee3ee2d168f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182670850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.182670850
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1855806987
Short name T10
Test name
Test status
Simulation time 37196507993 ps
CPU time 65.68 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:34:22 PM PDT 24
Peak memory 191456 kb
Host smart-801b4d35-122b-46da-bf8b-7bdbea5cebbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855806987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1855806987
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2049853912
Short name T212
Test name
Test status
Simulation time 718755463059 ps
CPU time 1793.61 seconds
Started Aug 09 04:33:32 PM PDT 24
Finished Aug 09 05:03:26 PM PDT 24
Peak memory 191536 kb
Host smart-6fdc916a-a401-4fb6-9710-3fc9e8150e2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049853912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2049853912
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.195799821
Short name T432
Test name
Test status
Simulation time 59983358044 ps
CPU time 83.77 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:34:36 PM PDT 24
Peak memory 183304 kb
Host smart-a319aa60-152b-45c5-ae87-b5908f9bd9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195799821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.195799821
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1216879319
Short name T265
Test name
Test status
Simulation time 20180698660 ps
CPU time 11.82 seconds
Started Aug 09 04:32:43 PM PDT 24
Finished Aug 09 04:32:55 PM PDT 24
Peak memory 183324 kb
Host smart-a68e76f2-1e5f-41d6-8385-5c4bfdf725f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216879319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1216879319
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.3406936959
Short name T13
Test name
Test status
Simulation time 49690439915 ps
CPU time 388.14 seconds
Started Aug 09 04:32:54 PM PDT 24
Finished Aug 09 04:39:22 PM PDT 24
Peak memory 206224 kb
Host smart-5e9794f4-646e-4615-b701-6c7288b5ddc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406936959 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.3406936959
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.1631083126
Short name T379
Test name
Test status
Simulation time 30899510316 ps
CPU time 29.35 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:33:45 PM PDT 24
Peak memory 183328 kb
Host smart-a654c90d-cafe-4942-b308-ea88fbd3b9ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631083126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1631083126
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1826193378
Short name T204
Test name
Test status
Simulation time 589805700369 ps
CPU time 622.4 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:43:35 PM PDT 24
Peak memory 191896 kb
Host smart-4572301c-ee12-4367-abcb-3a6ce89ee074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826193378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1826193378
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.892095052
Short name T158
Test name
Test status
Simulation time 130299222117 ps
CPU time 107.9 seconds
Started Aug 09 04:33:29 PM PDT 24
Finished Aug 09 04:35:17 PM PDT 24
Peak memory 191424 kb
Host smart-9820f730-10d2-49a4-85f0-20e2dfd57d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892095052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.892095052
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.452887783
Short name T238
Test name
Test status
Simulation time 517349265946 ps
CPU time 267.02 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:37:44 PM PDT 24
Peak memory 191428 kb
Host smart-0e90fa43-9aca-4985-93a7-735e0305947c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452887783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.452887783
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1051432044
Short name T215
Test name
Test status
Simulation time 185012563929 ps
CPU time 708.75 seconds
Started Aug 09 04:33:33 PM PDT 24
Finished Aug 09 04:45:22 PM PDT 24
Peak memory 191480 kb
Host smart-353aa3fa-4432-405f-bd61-39547e031739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051432044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1051432044
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3705470244
Short name T120
Test name
Test status
Simulation time 147103525811 ps
CPU time 1060.59 seconds
Started Aug 09 04:33:15 PM PDT 24
Finished Aug 09 04:50:56 PM PDT 24
Peak memory 191468 kb
Host smart-d170f0d1-12eb-474e-8749-b03f0074ddba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705470244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3705470244
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2157431502
Short name T166
Test name
Test status
Simulation time 790404539018 ps
CPU time 384.33 seconds
Started Aug 09 04:33:19 PM PDT 24
Finished Aug 09 04:39:44 PM PDT 24
Peak memory 191484 kb
Host smart-5267a45c-2ccc-4ab9-a409-953a7b1772da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157431502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2157431502
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.4213880082
Short name T208
Test name
Test status
Simulation time 359093790406 ps
CPU time 458.49 seconds
Started Aug 09 04:34:37 PM PDT 24
Finished Aug 09 04:42:16 PM PDT 24
Peak memory 191392 kb
Host smart-e073ebe9-9674-4c54-a6c3-24bc1e9999b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213880082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.4213880082
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1131291777
Short name T436
Test name
Test status
Simulation time 359222549503 ps
CPU time 139.54 seconds
Started Aug 09 04:34:23 PM PDT 24
Finished Aug 09 04:36:43 PM PDT 24
Peak memory 182200 kb
Host smart-e72c55da-fb86-4d8f-9a9d-c5ebeea1f268
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131291777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1131291777
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2131524
Short name T274
Test name
Test status
Simulation time 355548642988 ps
CPU time 329.26 seconds
Started Aug 09 04:33:05 PM PDT 24
Finished Aug 09 04:38:34 PM PDT 24
Peak memory 183260 kb
Host smart-2bb941d5-ec82-4f15-bc78-6b0092d2db3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
rv_timer_cfg_update_on_fly.2131524
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1002142477
Short name T376
Test name
Test status
Simulation time 427451370109 ps
CPU time 335.03 seconds
Started Aug 09 04:32:37 PM PDT 24
Finished Aug 09 04:38:12 PM PDT 24
Peak memory 183320 kb
Host smart-9114df99-3aa6-4036-8f12-eb082a81edcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002142477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1002142477
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2239840733
Short name T361
Test name
Test status
Simulation time 79267856 ps
CPU time 0.58 seconds
Started Aug 09 04:32:44 PM PDT 24
Finished Aug 09 04:32:44 PM PDT 24
Peak memory 182948 kb
Host smart-7209090a-cfde-4190-8143-d4c240e6dadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239840733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2239840733
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.2048843664
Short name T126
Test name
Test status
Simulation time 281213063640 ps
CPU time 220.46 seconds
Started Aug 09 04:33:26 PM PDT 24
Finished Aug 09 04:37:07 PM PDT 24
Peak memory 191460 kb
Host smart-e8a0b8b9-7689-4c12-b18f-c5480d18435e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048843664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2048843664
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.4258267041
Short name T283
Test name
Test status
Simulation time 143832854167 ps
CPU time 600.7 seconds
Started Aug 09 04:34:37 PM PDT 24
Finished Aug 09 04:44:38 PM PDT 24
Peak memory 191012 kb
Host smart-b5bc6a53-cb92-473b-9b61-158a16a5bfbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258267041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.4258267041
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.4129572808
Short name T320
Test name
Test status
Simulation time 196460359315 ps
CPU time 98.94 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:34:56 PM PDT 24
Peak memory 191472 kb
Host smart-05bb24a9-f071-423e-b67d-603e17ca6182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129572808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.4129572808
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1663501760
Short name T306
Test name
Test status
Simulation time 1511428315855 ps
CPU time 258.15 seconds
Started Aug 09 04:33:23 PM PDT 24
Finished Aug 09 04:37:41 PM PDT 24
Peak memory 191460 kb
Host smart-88b92f2d-f897-4801-a6ab-e687796d94a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663501760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1663501760
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.147219685
Short name T157
Test name
Test status
Simulation time 420165447620 ps
CPU time 677.93 seconds
Started Aug 09 04:34:37 PM PDT 24
Finished Aug 09 04:45:55 PM PDT 24
Peak memory 191104 kb
Host smart-dab7a73e-7dc1-418e-8d76-0865c3034fa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147219685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.147219685
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3238306589
Short name T313
Test name
Test status
Simulation time 174535041813 ps
CPU time 536.75 seconds
Started Aug 09 04:33:18 PM PDT 24
Finished Aug 09 04:42:15 PM PDT 24
Peak memory 191516 kb
Host smart-6356cbb3-1d67-4191-877a-de45fd15506f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238306589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3238306589
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3502851109
Short name T293
Test name
Test status
Simulation time 28918200823 ps
CPU time 44.71 seconds
Started Aug 09 04:33:19 PM PDT 24
Finished Aug 09 04:34:04 PM PDT 24
Peak memory 191496 kb
Host smart-539838af-c8b6-4607-bf3d-a3c16f988daf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502851109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3502851109
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2692558146
Short name T255
Test name
Test status
Simulation time 100539671196 ps
CPU time 202.98 seconds
Started Aug 09 04:33:21 PM PDT 24
Finished Aug 09 04:36:44 PM PDT 24
Peak memory 193824 kb
Host smart-a805cda2-9a01-45a9-ad5c-18fcbca2099a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692558146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2692558146
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3732004920
Short name T292
Test name
Test status
Simulation time 81651444067 ps
CPU time 83.03 seconds
Started Aug 09 04:33:35 PM PDT 24
Finished Aug 09 04:34:58 PM PDT 24
Peak memory 183304 kb
Host smart-83878404-af96-4f14-a2c9-27263adf9c3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732004920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3732004920
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.359067422
Short name T291
Test name
Test status
Simulation time 487115108976 ps
CPU time 820.49 seconds
Started Aug 09 04:32:17 PM PDT 24
Finished Aug 09 04:45:57 PM PDT 24
Peak memory 183256 kb
Host smart-75dea838-8689-40dc-8657-2f339d123f17
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359067422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.359067422
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3509308814
Short name T431
Test name
Test status
Simulation time 239330844773 ps
CPU time 191.6 seconds
Started Aug 09 04:32:26 PM PDT 24
Finished Aug 09 04:35:38 PM PDT 24
Peak memory 183320 kb
Host smart-45287b24-f95c-4d4d-ade4-44e4a0efe2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509308814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3509308814
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.321553062
Short name T266
Test name
Test status
Simulation time 144208400800 ps
CPU time 115.56 seconds
Started Aug 09 04:32:39 PM PDT 24
Finished Aug 09 04:34:34 PM PDT 24
Peak memory 191496 kb
Host smart-f2fb2ab9-8d3b-4f85-9809-c2fa85fe4ed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321553062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.321553062
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1478868358
Short name T261
Test name
Test status
Simulation time 175770846292 ps
CPU time 70.7 seconds
Started Aug 09 04:32:38 PM PDT 24
Finished Aug 09 04:33:49 PM PDT 24
Peak memory 191468 kb
Host smart-9e8d91f0-b219-4117-a64a-52919c238e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478868358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1478868358
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.2974296813
Short name T37
Test name
Test status
Simulation time 96140402868 ps
CPU time 196.16 seconds
Started Aug 09 04:32:41 PM PDT 24
Finished Aug 09 04:35:57 PM PDT 24
Peak memory 197980 kb
Host smart-5c5efcf9-bb08-430c-8144-0c807fc6c102
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974296813 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.2974296813
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.2160879807
Short name T133
Test name
Test status
Simulation time 3852695756 ps
CPU time 5.88 seconds
Started Aug 09 04:34:23 PM PDT 24
Finished Aug 09 04:34:29 PM PDT 24
Peak memory 180916 kb
Host smart-8ea0deda-98d3-4903-b154-f8084925b669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160879807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2160879807
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2982371972
Short name T407
Test name
Test status
Simulation time 181194381179 ps
CPU time 98.11 seconds
Started Aug 09 04:33:15 PM PDT 24
Finished Aug 09 04:34:53 PM PDT 24
Peak memory 191484 kb
Host smart-09bfa4c6-69f1-4786-8b56-2305524a6ea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982371972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2982371972
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.996425990
Short name T71
Test name
Test status
Simulation time 19562223875 ps
CPU time 10.24 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:33:28 PM PDT 24
Peak memory 183272 kb
Host smart-219ad7fd-3a2c-45c0-9b2e-a8b5cd966e44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996425990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.996425990
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1771280293
Short name T433
Test name
Test status
Simulation time 156242174922 ps
CPU time 115.37 seconds
Started Aug 09 04:33:15 PM PDT 24
Finished Aug 09 04:35:11 PM PDT 24
Peak memory 191496 kb
Host smart-660b59e8-30f7-421e-9eb9-96587a40bac9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771280293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1771280293
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1091540392
Short name T273
Test name
Test status
Simulation time 257843021551 ps
CPU time 186.99 seconds
Started Aug 09 04:33:19 PM PDT 24
Finished Aug 09 04:36:26 PM PDT 24
Peak memory 191500 kb
Host smart-87a378d1-bf94-4a65-a23f-3823003fda74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091540392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1091540392
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2594993285
Short name T319
Test name
Test status
Simulation time 52913979405 ps
CPU time 110.24 seconds
Started Aug 09 04:33:24 PM PDT 24
Finished Aug 09 04:35:14 PM PDT 24
Peak memory 183260 kb
Host smart-f7c2f0e1-0676-4c34-bc0c-b558e7980d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594993285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2594993285
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.4180541553
Short name T318
Test name
Test status
Simulation time 2857433051 ps
CPU time 1.79 seconds
Started Aug 09 04:32:37 PM PDT 24
Finished Aug 09 04:32:39 PM PDT 24
Peak memory 183288 kb
Host smart-e574e0c6-d72d-4b50-b316-d71fb8e33f57
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180541553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.4180541553
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1698857623
Short name T352
Test name
Test status
Simulation time 61948913697 ps
CPU time 97.83 seconds
Started Aug 09 04:33:04 PM PDT 24
Finished Aug 09 04:34:42 PM PDT 24
Peak memory 183268 kb
Host smart-de26f701-8f4f-4845-8c0c-0d3cd27b9a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698857623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1698857623
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1723062082
Short name T264
Test name
Test status
Simulation time 40434309402 ps
CPU time 44.9 seconds
Started Aug 09 04:32:38 PM PDT 24
Finished Aug 09 04:33:23 PM PDT 24
Peak memory 183244 kb
Host smart-d6395a0d-877e-4fb7-8958-6a5572fd0aaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723062082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1723062082
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1805809345
Short name T271
Test name
Test status
Simulation time 35709153353 ps
CPU time 65.87 seconds
Started Aug 09 04:32:54 PM PDT 24
Finished Aug 09 04:34:00 PM PDT 24
Peak memory 183252 kb
Host smart-221da7d7-3dea-4960-a6e0-f8a9d87e4ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805809345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1805809345
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.3929602368
Short name T244
Test name
Test status
Simulation time 229485611515 ps
CPU time 510.01 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:41:42 PM PDT 24
Peak memory 191460 kb
Host smart-2d431ad2-19ca-4df7-83d9-dd0043e33e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929602368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3929602368
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3047388633
Short name T50
Test name
Test status
Simulation time 173269108916 ps
CPU time 1610.82 seconds
Started Aug 09 04:33:24 PM PDT 24
Finished Aug 09 05:00:15 PM PDT 24
Peak memory 193248 kb
Host smart-85366fcc-a0f3-4085-ba19-d47f80a53403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047388633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3047388633
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2541880912
Short name T53
Test name
Test status
Simulation time 41134492777 ps
CPU time 21.41 seconds
Started Aug 09 04:34:23 PM PDT 24
Finished Aug 09 04:34:45 PM PDT 24
Peak memory 182104 kb
Host smart-ba2c0b85-da73-4e0a-b257-61c4d990f87d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541880912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2541880912
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2710579951
Short name T315
Test name
Test status
Simulation time 148171951377 ps
CPU time 308.23 seconds
Started Aug 09 04:33:23 PM PDT 24
Finished Aug 09 04:38:31 PM PDT 24
Peak memory 191488 kb
Host smart-0797d734-ef8d-473e-afb8-42bd8e14693e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710579951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2710579951
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2155621762
Short name T77
Test name
Test status
Simulation time 265335995816 ps
CPU time 660.87 seconds
Started Aug 09 04:33:15 PM PDT 24
Finished Aug 09 04:44:16 PM PDT 24
Peak memory 191548 kb
Host smart-bc654737-9572-468b-af51-ac6f7c267ff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155621762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2155621762
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.4143003471
Short name T174
Test name
Test status
Simulation time 608544129384 ps
CPU time 220.24 seconds
Started Aug 09 04:33:25 PM PDT 24
Finished Aug 09 04:37:05 PM PDT 24
Peak memory 191516 kb
Host smart-1f889a13-4ffc-4704-89c0-8dfebece5f48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143003471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.4143003471
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2565304358
Short name T280
Test name
Test status
Simulation time 138205982674 ps
CPU time 844.69 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:47:21 PM PDT 24
Peak memory 191516 kb
Host smart-dab2665b-3c23-4129-9d78-9c8d05811c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565304358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2565304358
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3474701221
Short name T219
Test name
Test status
Simulation time 41772340187 ps
CPU time 54.6 seconds
Started Aug 09 04:33:22 PM PDT 24
Finished Aug 09 04:34:17 PM PDT 24
Peak memory 183316 kb
Host smart-bb27d2ed-9621-41d6-9763-42fd3f8ab73c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474701221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3474701221
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3843189069
Short name T384
Test name
Test status
Simulation time 457324891161 ps
CPU time 253.87 seconds
Started Aug 09 04:33:01 PM PDT 24
Finished Aug 09 04:37:15 PM PDT 24
Peak memory 183228 kb
Host smart-7a3f30b8-9332-406a-bfde-a89c2efbac03
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843189069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3843189069
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.938810387
Short name T364
Test name
Test status
Simulation time 185708548154 ps
CPU time 69.23 seconds
Started Aug 09 04:32:41 PM PDT 24
Finished Aug 09 04:33:50 PM PDT 24
Peak memory 183280 kb
Host smart-3ced95ad-d36e-4a89-97a9-cf17ab6db2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938810387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.938810387
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2806286494
Short name T185
Test name
Test status
Simulation time 41187769934 ps
CPU time 79.55 seconds
Started Aug 09 04:32:57 PM PDT 24
Finished Aug 09 04:34:16 PM PDT 24
Peak memory 183224 kb
Host smart-97c7e5a5-e720-4267-a9cc-b155d47e0967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806286494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2806286494
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.788511268
Short name T36
Test name
Test status
Simulation time 125842682852 ps
CPU time 759.76 seconds
Started Aug 09 04:32:53 PM PDT 24
Finished Aug 09 04:45:33 PM PDT 24
Peak memory 207160 kb
Host smart-30140ba6-2c62-4830-94b2-b1cc120552a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788511268 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.788511268
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.1006688722
Short name T135
Test name
Test status
Simulation time 266941765668 ps
CPU time 173.03 seconds
Started Aug 09 04:34:23 PM PDT 24
Finished Aug 09 04:37:17 PM PDT 24
Peak memory 188988 kb
Host smart-074ed974-99d4-414f-b7d0-2940c70e888c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006688722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1006688722
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3503465591
Short name T254
Test name
Test status
Simulation time 102798584137 ps
CPU time 86.21 seconds
Started Aug 09 04:34:23 PM PDT 24
Finished Aug 09 04:35:50 PM PDT 24
Peak memory 190236 kb
Host smart-7102b8c0-d7b9-41f0-924d-e8a7b1aa1f1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503465591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3503465591
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3710060217
Short name T169
Test name
Test status
Simulation time 400213053805 ps
CPU time 325.54 seconds
Started Aug 09 04:33:15 PM PDT 24
Finished Aug 09 04:38:41 PM PDT 24
Peak memory 191508 kb
Host smart-20efe300-673b-4107-b7c8-60881b903100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710060217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3710060217
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.327161452
Short name T303
Test name
Test status
Simulation time 1526502818697 ps
CPU time 310.1 seconds
Started Aug 09 04:32:54 PM PDT 24
Finished Aug 09 04:38:04 PM PDT 24
Peak memory 183256 kb
Host smart-e12200bb-8866-442b-968f-3bb23542f406
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327161452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.327161452
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1184144396
Short name T372
Test name
Test status
Simulation time 69107591561 ps
CPU time 57.32 seconds
Started Aug 09 04:32:44 PM PDT 24
Finished Aug 09 04:33:41 PM PDT 24
Peak memory 183292 kb
Host smart-f45f332a-2829-48c5-b33b-4f2affc90028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184144396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1184144396
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.731979033
Short name T424
Test name
Test status
Simulation time 48607769093 ps
CPU time 72.75 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:34:30 PM PDT 24
Peak memory 183248 kb
Host smart-69cf85d2-ab78-4070-9b07-66bbf97959ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731979033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.731979033
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1168526874
Short name T331
Test name
Test status
Simulation time 8369859828 ps
CPU time 10.49 seconds
Started Aug 09 04:33:15 PM PDT 24
Finished Aug 09 04:33:26 PM PDT 24
Peak memory 183032 kb
Host smart-c8eea439-d380-4f3d-aa73-8f7cd4789559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168526874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1168526874
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.660232942
Short name T233
Test name
Test status
Simulation time 456857337152 ps
CPU time 374.99 seconds
Started Aug 09 04:33:27 PM PDT 24
Finished Aug 09 04:39:42 PM PDT 24
Peak memory 191536 kb
Host smart-1b9b0501-3625-4c09-998f-65d05d762cd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660232942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.660232942
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3671812663
Short name T52
Test name
Test status
Simulation time 570487889992 ps
CPU time 1679.07 seconds
Started Aug 09 04:33:18 PM PDT 24
Finished Aug 09 05:01:17 PM PDT 24
Peak memory 191496 kb
Host smart-833d8c10-efa6-4c3e-9a77-a61f179dd288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671812663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3671812663
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.186404852
Short name T192
Test name
Test status
Simulation time 93808288126 ps
CPU time 187.31 seconds
Started Aug 09 04:33:30 PM PDT 24
Finished Aug 09 04:36:37 PM PDT 24
Peak memory 191464 kb
Host smart-9f5633b8-ccec-4fee-82ee-62ea3f7c6fb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186404852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.186404852
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2975307043
Short name T183
Test name
Test status
Simulation time 35216690403 ps
CPU time 45.45 seconds
Started Aug 09 04:33:18 PM PDT 24
Finished Aug 09 04:34:04 PM PDT 24
Peak memory 183348 kb
Host smart-151fe678-5f21-4f6d-bbc1-b499785f725d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975307043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2975307043
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3478963257
Short name T76
Test name
Test status
Simulation time 148650798612 ps
CPU time 241.1 seconds
Started Aug 09 04:33:30 PM PDT 24
Finished Aug 09 04:37:31 PM PDT 24
Peak memory 183352 kb
Host smart-cb720a6a-0b21-4836-a2c7-73a2206e1bc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478963257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3478963257
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1808551882
Short name T149
Test name
Test status
Simulation time 498317783798 ps
CPU time 272.42 seconds
Started Aug 09 04:33:37 PM PDT 24
Finished Aug 09 04:38:09 PM PDT 24
Peak memory 191504 kb
Host smart-3f010cb7-454e-4702-ac7f-81543cb4f1bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808551882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1808551882
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.30792502
Short name T305
Test name
Test status
Simulation time 534243910843 ps
CPU time 495.94 seconds
Started Aug 09 04:32:33 PM PDT 24
Finished Aug 09 04:40:49 PM PDT 24
Peak memory 183232 kb
Host smart-418aa573-0b26-4604-8358-332db29b25f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30792502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
rv_timer_cfg_update_on_fly.30792502
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1479694716
Short name T390
Test name
Test status
Simulation time 139386422503 ps
CPU time 200.43 seconds
Started Aug 09 04:32:49 PM PDT 24
Finished Aug 09 04:36:09 PM PDT 24
Peak memory 183288 kb
Host smart-9b6d2314-e23b-4c72-9aef-9b2816dbe4bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479694716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1479694716
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1294642339
Short name T375
Test name
Test status
Simulation time 38126736965 ps
CPU time 34.34 seconds
Started Aug 09 04:32:45 PM PDT 24
Finished Aug 09 04:33:20 PM PDT 24
Peak memory 183272 kb
Host smart-332c2e62-f43f-4642-9af4-4df07b9da501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294642339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1294642339
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1430530709
Short name T302
Test name
Test status
Simulation time 153486367260 ps
CPU time 258.17 seconds
Started Aug 09 04:33:07 PM PDT 24
Finished Aug 09 04:37:25 PM PDT 24
Peak memory 183260 kb
Host smart-c49b3c4f-e8c8-4415-a0e6-8dc55e46c0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430530709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1430530709
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.880953073
Short name T16
Test name
Test status
Simulation time 56193013 ps
CPU time 0.75 seconds
Started Aug 09 04:32:33 PM PDT 24
Finished Aug 09 04:32:39 PM PDT 24
Peak memory 213796 kb
Host smart-abadb9ef-49c1-4a3a-b903-173fa598c7b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880953073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.880953073
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.787536096
Short name T132
Test name
Test status
Simulation time 326288038774 ps
CPU time 164.18 seconds
Started Aug 09 04:32:35 PM PDT 24
Finished Aug 09 04:35:19 PM PDT 24
Peak memory 191476 kb
Host smart-73b44e73-6787-47d0-a48b-20bf58c141da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787536096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.787536096
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.480644930
Short name T382
Test name
Test status
Simulation time 10583009009 ps
CPU time 16.21 seconds
Started Aug 09 04:32:52 PM PDT 24
Finished Aug 09 04:33:09 PM PDT 24
Peak memory 183272 kb
Host smart-ca7afcd9-94d4-4ec0-b59e-c7f1795bc4a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480644930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.480644930
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2390999588
Short name T367
Test name
Test status
Simulation time 154769138982 ps
CPU time 67.72 seconds
Started Aug 09 04:32:59 PM PDT 24
Finished Aug 09 04:34:06 PM PDT 24
Peak memory 183200 kb
Host smart-01fd741e-f1d4-41bb-9599-b65631fa0c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390999588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2390999588
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.329170399
Short name T134
Test name
Test status
Simulation time 71975694331 ps
CPU time 170.11 seconds
Started Aug 09 04:32:42 PM PDT 24
Finished Aug 09 04:35:32 PM PDT 24
Peak memory 191528 kb
Host smart-a5155f7e-e2dc-4e39-a1ae-3c2581eb389f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329170399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.329170399
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.849968237
Short name T22
Test name
Test status
Simulation time 345444562 ps
CPU time 0.8 seconds
Started Aug 09 04:32:41 PM PDT 24
Finished Aug 09 04:32:42 PM PDT 24
Peak memory 183024 kb
Host smart-918ce8c2-9ac6-47b8-bb97-c5f2079a8bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849968237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.849968237
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3339587459
Short name T422
Test name
Test status
Simulation time 128903340222 ps
CPU time 215.43 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:36:51 PM PDT 24
Peak memory 183276 kb
Host smart-732da6af-d0fa-434e-bc4b-b3600ab06e7f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339587459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3339587459
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1196838685
Short name T389
Test name
Test status
Simulation time 260918750024 ps
CPU time 107.86 seconds
Started Aug 09 04:32:41 PM PDT 24
Finished Aug 09 04:34:29 PM PDT 24
Peak memory 183288 kb
Host smart-258d8933-1726-4bf7-9cb6-32cca2e2c661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196838685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1196838685
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.520843878
Short name T260
Test name
Test status
Simulation time 23102890187 ps
CPU time 37.23 seconds
Started Aug 09 04:33:11 PM PDT 24
Finished Aug 09 04:33:48 PM PDT 24
Peak memory 183264 kb
Host smart-f64e417d-4b7b-4b7a-8f1f-5150f97cc512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520843878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.520843878
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2077409102
Short name T426
Test name
Test status
Simulation time 205969516189 ps
CPU time 246.49 seconds
Started Aug 09 04:32:51 PM PDT 24
Finished Aug 09 04:36:58 PM PDT 24
Peak memory 183692 kb
Host smart-cc9fd026-c022-4613-a205-2c6dfdfe4906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077409102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2077409102
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.837080088
Short name T446
Test name
Test status
Simulation time 619708971553 ps
CPU time 489.33 seconds
Started Aug 09 04:32:46 PM PDT 24
Finished Aug 09 04:40:56 PM PDT 24
Peak memory 191460 kb
Host smart-07743ac3-3edb-4e47-8b59-56049c384836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837080088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
837080088
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1838201707
Short name T326
Test name
Test status
Simulation time 27329235027 ps
CPU time 25.29 seconds
Started Aug 09 04:32:52 PM PDT 24
Finished Aug 09 04:33:17 PM PDT 24
Peak memory 183192 kb
Host smart-2d8ee185-986a-4acd-b0d4-203233540ffa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838201707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1838201707
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2663423016
Short name T368
Test name
Test status
Simulation time 111371889356 ps
CPU time 46.1 seconds
Started Aug 09 04:33:04 PM PDT 24
Finished Aug 09 04:33:50 PM PDT 24
Peak memory 183268 kb
Host smart-ab9eff9d-5a51-4890-8a79-11cca96eb4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663423016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2663423016
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3942685864
Short name T241
Test name
Test status
Simulation time 109234595702 ps
CPU time 61.86 seconds
Started Aug 09 04:32:48 PM PDT 24
Finished Aug 09 04:33:50 PM PDT 24
Peak memory 191472 kb
Host smart-0ef27ead-6426-47e9-b9d0-399b5b87987e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942685864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3942685864
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3247412172
Short name T343
Test name
Test status
Simulation time 374223360622 ps
CPU time 523.91 seconds
Started Aug 09 04:33:26 PM PDT 24
Finished Aug 09 04:42:10 PM PDT 24
Peak memory 191444 kb
Host smart-f21e9448-4412-4718-925c-d188c4be8a8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247412172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3247412172
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.172332310
Short name T146
Test name
Test status
Simulation time 644824912380 ps
CPU time 519.36 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:41:52 PM PDT 24
Peak memory 183256 kb
Host smart-f3dda1b1-be32-48ab-bd58-6973a669889d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172332310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.172332310
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2153225820
Short name T354
Test name
Test status
Simulation time 126446915899 ps
CPU time 176.9 seconds
Started Aug 09 04:32:41 PM PDT 24
Finished Aug 09 04:35:38 PM PDT 24
Peak memory 183268 kb
Host smart-904083c2-0977-40e5-a5a7-5f6f6814da57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153225820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2153225820
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2324318938
Short name T252
Test name
Test status
Simulation time 199661846948 ps
CPU time 71.91 seconds
Started Aug 09 04:32:44 PM PDT 24
Finished Aug 09 04:33:56 PM PDT 24
Peak memory 191504 kb
Host smart-085dc69e-7635-4d30-ac76-0ec1586e462b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324318938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2324318938
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.240504646
Short name T335
Test name
Test status
Simulation time 331895582089 ps
CPU time 227.57 seconds
Started Aug 09 04:32:47 PM PDT 24
Finished Aug 09 04:36:35 PM PDT 24
Peak memory 195040 kb
Host smart-a9e70047-aa19-4e5c-8b13-7a610b420098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240504646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.240504646
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.950886207
Short name T235
Test name
Test status
Simulation time 207280754584 ps
CPU time 338.34 seconds
Started Aug 09 04:32:44 PM PDT 24
Finished Aug 09 04:38:22 PM PDT 24
Peak memory 183208 kb
Host smart-422b9494-a27f-4893-9c02-c5531a4d92a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950886207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.950886207
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2327242181
Short name T383
Test name
Test status
Simulation time 391284022442 ps
CPU time 141.72 seconds
Started Aug 09 04:33:08 PM PDT 24
Finished Aug 09 04:35:30 PM PDT 24
Peak memory 183260 kb
Host smart-ffbce79f-d2a1-4e17-9b69-3511d097f431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327242181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2327242181
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.762833292
Short name T70
Test name
Test status
Simulation time 175125723382 ps
CPU time 555.66 seconds
Started Aug 09 04:33:59 PM PDT 24
Finished Aug 09 04:43:15 PM PDT 24
Peak memory 190520 kb
Host smart-cf2cb0dd-d0fd-4b7b-8da2-887d4349a718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762833292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.762833292
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2076326953
Short name T440
Test name
Test status
Simulation time 4690011408 ps
CPU time 7.51 seconds
Started Aug 09 04:32:40 PM PDT 24
Finished Aug 09 04:32:48 PM PDT 24
Peak memory 191508 kb
Host smart-546176d4-3640-4d02-968c-4a3d0dc60918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076326953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2076326953
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.757097270
Short name T87
Test name
Test status
Simulation time 756013331742 ps
CPU time 1352.49 seconds
Started Aug 09 04:32:47 PM PDT 24
Finished Aug 09 04:55:20 PM PDT 24
Peak memory 191532 kb
Host smart-7d09c631-14cd-4cf4-a809-ec36b8145734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757097270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
757097270
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.1324245981
Short name T33
Test name
Test status
Simulation time 126202514745 ps
CPU time 1274.05 seconds
Started Aug 09 04:32:53 PM PDT 24
Finished Aug 09 04:54:07 PM PDT 24
Peak memory 209412 kb
Host smart-eb85c2f0-329c-41f0-b65a-db9fa2ef9c66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324245981 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.1324245981
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3829544217
Short name T141
Test name
Test status
Simulation time 1533228258269 ps
CPU time 754.21 seconds
Started Aug 09 04:32:40 PM PDT 24
Finished Aug 09 04:45:14 PM PDT 24
Peak memory 183228 kb
Host smart-9a84b853-dc85-488d-976f-ff41fd62dc31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829544217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3829544217
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_random.2663517633
Short name T138
Test name
Test status
Simulation time 519832730597 ps
CPU time 128.3 seconds
Started Aug 09 04:33:09 PM PDT 24
Finished Aug 09 04:35:17 PM PDT 24
Peak memory 183280 kb
Host smart-fe6174a1-a95a-481d-a942-1ff5161810e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663517633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2663517633
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.401699248
Short name T301
Test name
Test status
Simulation time 33724890303 ps
CPU time 22.8 seconds
Started Aug 09 04:32:39 PM PDT 24
Finished Aug 09 04:33:02 PM PDT 24
Peak memory 191504 kb
Host smart-c974b1cd-5ca7-4e7a-8564-dd227151aacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401699248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.401699248
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.535849032
Short name T11
Test name
Test status
Simulation time 44737612737 ps
CPU time 354.83 seconds
Started Aug 09 04:32:42 PM PDT 24
Finished Aug 09 04:38:37 PM PDT 24
Peak memory 206212 kb
Host smart-a40fc3b7-b6c5-4297-bbd7-2468f688ac1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535849032 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.535849032
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2661141187
Short name T417
Test name
Test status
Simulation time 617014555783 ps
CPU time 564.38 seconds
Started Aug 09 04:33:00 PM PDT 24
Finished Aug 09 04:42:24 PM PDT 24
Peak memory 183216 kb
Host smart-748f82be-a614-49a2-a48a-118d8d9dbbed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661141187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2661141187
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2054409492
Short name T396
Test name
Test status
Simulation time 968394179546 ps
CPU time 164.47 seconds
Started Aug 09 04:33:10 PM PDT 24
Finished Aug 09 04:35:55 PM PDT 24
Peak memory 183296 kb
Host smart-e118e3ed-4b5a-4056-91f1-b71db406af7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054409492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2054409492
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1204638793
Short name T2
Test name
Test status
Simulation time 395051555840 ps
CPU time 516.26 seconds
Started Aug 09 04:33:01 PM PDT 24
Finished Aug 09 04:41:38 PM PDT 24
Peak memory 191428 kb
Host smart-62133b8e-2d97-487a-9d30-4430d9ff8de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204638793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1204638793
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.930513028
Short name T413
Test name
Test status
Simulation time 283041773 ps
CPU time 0.64 seconds
Started Aug 09 04:32:49 PM PDT 24
Finished Aug 09 04:32:54 PM PDT 24
Peak memory 183024 kb
Host smart-91d50c82-de05-4b4b-88e6-836a66208713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930513028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.930513028
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.4194048785
Short name T201
Test name
Test status
Simulation time 1498972879050 ps
CPU time 676.44 seconds
Started Aug 09 04:33:15 PM PDT 24
Finished Aug 09 04:44:31 PM PDT 24
Peak memory 195264 kb
Host smart-4644ada8-9c24-4050-91cc-2956892299fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194048785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.4194048785
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.4076688800
Short name T69
Test name
Test status
Simulation time 13708697703 ps
CPU time 13.5 seconds
Started Aug 09 04:32:56 PM PDT 24
Finished Aug 09 04:33:09 PM PDT 24
Peak memory 183640 kb
Host smart-fcc31991-38b4-4e77-ae67-92ef4e821611
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076688800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.4076688800
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2634283558
Short name T399
Test name
Test status
Simulation time 145060663769 ps
CPU time 230.73 seconds
Started Aug 09 04:33:02 PM PDT 24
Finished Aug 09 04:36:53 PM PDT 24
Peak memory 183248 kb
Host smart-8b6652ba-621d-4550-a761-cdcb8f6af7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634283558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2634283558
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.680358719
Short name T418
Test name
Test status
Simulation time 3370318271 ps
CPU time 9.81 seconds
Started Aug 09 04:33:11 PM PDT 24
Finished Aug 09 04:33:20 PM PDT 24
Peak memory 183300 kb
Host smart-e1772784-8f8d-4683-bd2c-5ce5e2035036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680358719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.680358719
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3558944586
Short name T176
Test name
Test status
Simulation time 51729152808 ps
CPU time 81.79 seconds
Started Aug 09 04:32:44 PM PDT 24
Finished Aug 09 04:34:06 PM PDT 24
Peak memory 183248 kb
Host smart-0de5bf10-7846-4624-a03f-b126fa35fb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558944586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3558944586
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2304532047
Short name T227
Test name
Test status
Simulation time 246249485937 ps
CPU time 293.99 seconds
Started Aug 09 04:32:58 PM PDT 24
Finished Aug 09 04:37:52 PM PDT 24
Peak memory 191452 kb
Host smart-c51be893-a0e8-438f-a8e4-7c41478cd8ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304532047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2304532047
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2728496101
Short name T46
Test name
Test status
Simulation time 1103493169089 ps
CPU time 568.39 seconds
Started Aug 09 04:32:53 PM PDT 24
Finished Aug 09 04:42:22 PM PDT 24
Peak memory 183212 kb
Host smart-0bc666de-ca27-4664-8a86-8a2d291d380a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728496101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2728496101
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1689995787
Short name T4
Test name
Test status
Simulation time 157860009964 ps
CPU time 123.92 seconds
Started Aug 09 04:32:50 PM PDT 24
Finished Aug 09 04:34:54 PM PDT 24
Peak memory 183316 kb
Host smart-0cab7857-a302-4fb2-8513-2b3b050ae2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689995787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1689995787
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.571283451
Short name T314
Test name
Test status
Simulation time 101142935471 ps
CPU time 159.12 seconds
Started Aug 09 04:33:00 PM PDT 24
Finished Aug 09 04:35:39 PM PDT 24
Peak memory 191460 kb
Host smart-d99ed945-e296-4f99-a899-b8005517882f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571283451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.571283451
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3373964579
Short name T272
Test name
Test status
Simulation time 80227116182 ps
CPU time 103.36 seconds
Started Aug 09 04:32:57 PM PDT 24
Finished Aug 09 04:34:40 PM PDT 24
Peak memory 183248 kb
Host smart-45c48db4-797d-49f3-8fc3-ada0c9990d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373964579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3373964579
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1052934736
Short name T217
Test name
Test status
Simulation time 229615827653 ps
CPU time 1946.6 seconds
Started Aug 09 04:33:09 PM PDT 24
Finished Aug 09 05:05:36 PM PDT 24
Peak memory 191484 kb
Host smart-b7050ad2-0028-46b6-8d50-09d196687f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052934736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1052934736
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2516427644
Short name T416
Test name
Test status
Simulation time 201238820350 ps
CPU time 80.34 seconds
Started Aug 09 04:33:02 PM PDT 24
Finished Aug 09 04:34:22 PM PDT 24
Peak memory 183260 kb
Host smart-ae273ac6-f57e-4d7a-a56f-65da4cfff96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516427644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2516427644
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3146916613
Short name T237
Test name
Test status
Simulation time 108743883175 ps
CPU time 184.29 seconds
Started Aug 09 04:32:54 PM PDT 24
Finished Aug 09 04:35:58 PM PDT 24
Peak memory 191460 kb
Host smart-3e7e4705-ed19-4534-98e7-ae6787953751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146916613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3146916613
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1267705398
Short name T205
Test name
Test status
Simulation time 126356739343 ps
CPU time 326.57 seconds
Started Aug 09 04:32:57 PM PDT 24
Finished Aug 09 04:38:24 PM PDT 24
Peak memory 191436 kb
Host smart-eac4ddb2-863c-4c2e-a437-2f3fdedcb759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267705398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1267705398
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2224094555
Short name T64
Test name
Test status
Simulation time 41643120 ps
CPU time 0.58 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:33:16 PM PDT 24
Peak memory 182968 kb
Host smart-a184d18a-7ff6-4c80-8e22-ac397b0ede6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224094555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2224094555
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2786516782
Short name T278
Test name
Test status
Simulation time 302780217553 ps
CPU time 531.05 seconds
Started Aug 09 04:33:00 PM PDT 24
Finished Aug 09 04:41:51 PM PDT 24
Peak memory 183228 kb
Host smart-285a7db5-12b6-4e43-a96b-88e4fd22a224
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786516782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2786516782
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.4141669818
Short name T357
Test name
Test status
Simulation time 121240382254 ps
CPU time 184.12 seconds
Started Aug 09 04:32:39 PM PDT 24
Finished Aug 09 04:35:43 PM PDT 24
Peak memory 183260 kb
Host smart-a2dca1cb-2684-4865-ad49-e74db842fe5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141669818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.4141669818
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.685085062
Short name T18
Test name
Test status
Simulation time 39240299 ps
CPU time 0.74 seconds
Started Aug 09 04:32:40 PM PDT 24
Finished Aug 09 04:32:41 PM PDT 24
Peak memory 213752 kb
Host smart-8bd13cb9-541b-40fa-8e6f-6a0df517ed21
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685085062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.685085062
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3713250991
Short name T366
Test name
Test status
Simulation time 139986204971 ps
CPU time 189.27 seconds
Started Aug 09 04:32:38 PM PDT 24
Finished Aug 09 04:35:48 PM PDT 24
Peak memory 194108 kb
Host smart-fa2e9fdb-1d93-4d06-9880-d62ebdba9b60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713250991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3713250991
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3497484341
Short name T220
Test name
Test status
Simulation time 165502800305 ps
CPU time 275.71 seconds
Started Aug 09 04:32:54 PM PDT 24
Finished Aug 09 04:37:30 PM PDT 24
Peak memory 183272 kb
Host smart-8307a0ee-60c4-4e1d-807b-ec274f078f89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497484341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3497484341
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1582985043
Short name T371
Test name
Test status
Simulation time 98310762921 ps
CPU time 133.12 seconds
Started Aug 09 04:32:54 PM PDT 24
Finished Aug 09 04:35:07 PM PDT 24
Peak memory 183204 kb
Host smart-44823744-6863-43d9-9aad-2aaf9c089874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582985043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1582985043
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2218197940
Short name T180
Test name
Test status
Simulation time 116347751366 ps
CPU time 81.26 seconds
Started Aug 09 04:33:04 PM PDT 24
Finished Aug 09 04:34:25 PM PDT 24
Peak memory 191464 kb
Host smart-2bb118b3-a8b1-4541-bb7c-1dd41972adcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218197940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2218197940
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1196841685
Short name T403
Test name
Test status
Simulation time 39217794274 ps
CPU time 37.67 seconds
Started Aug 09 04:32:55 PM PDT 24
Finished Aug 09 04:33:33 PM PDT 24
Peak memory 191472 kb
Host smart-a0336b58-eb06-4e0a-8a91-6c694a5bc7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196841685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1196841685
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2652849600
Short name T430
Test name
Test status
Simulation time 623268242956 ps
CPU time 345.02 seconds
Started Aug 09 04:33:00 PM PDT 24
Finished Aug 09 04:38:45 PM PDT 24
Peak memory 183220 kb
Host smart-685ba8ba-26bb-45f5-aa82-7f8ac4d9eae1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652849600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2652849600
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.499103657
Short name T408
Test name
Test status
Simulation time 87653113804 ps
CPU time 123.96 seconds
Started Aug 09 04:32:46 PM PDT 24
Finished Aug 09 04:34:50 PM PDT 24
Peak memory 183212 kb
Host smart-004c33a5-ac50-4fe4-80c3-de16c0a0956d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499103657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.499103657
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2347301962
Short name T437
Test name
Test status
Simulation time 130530206105 ps
CPU time 98.46 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:34:44 PM PDT 24
Peak memory 191500 kb
Host smart-d73bd02c-16d6-4ff6-b6cb-0c6e5435597f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347301962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2347301962
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.65068689
Short name T23
Test name
Test status
Simulation time 32872589930 ps
CPU time 108.82 seconds
Started Aug 09 04:32:54 PM PDT 24
Finished Aug 09 04:34:43 PM PDT 24
Peak memory 183272 kb
Host smart-7b8493f7-1e7e-437f-9fe6-11bab9c5abcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65068689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.65068689
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.57055754
Short name T65
Test name
Test status
Simulation time 189903311130 ps
CPU time 592.25 seconds
Started Aug 09 04:33:20 PM PDT 24
Finished Aug 09 04:43:13 PM PDT 24
Peak memory 191508 kb
Host smart-89174ca6-a90e-43ad-b9ad-2131082c0fb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57055754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.57055754
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1338634124
Short name T412
Test name
Test status
Simulation time 271275788678 ps
CPU time 486.55 seconds
Started Aug 09 04:32:51 PM PDT 24
Finished Aug 09 04:40:57 PM PDT 24
Peak memory 183212 kb
Host smart-a72bd3ef-9d21-4c30-9fb1-2c84a3506dd1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338634124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1338634124
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3381186591
Short name T386
Test name
Test status
Simulation time 116365887079 ps
CPU time 79.76 seconds
Started Aug 09 04:32:50 PM PDT 24
Finished Aug 09 04:34:10 PM PDT 24
Peak memory 183248 kb
Host smart-3c55bdaa-9bfa-46c0-ae8d-b70674e4a3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381186591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3381186591
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1695521987
Short name T223
Test name
Test status
Simulation time 50732932231 ps
CPU time 46.25 seconds
Started Aug 09 04:33:09 PM PDT 24
Finished Aug 09 04:33:56 PM PDT 24
Peak memory 183288 kb
Host smart-4d575c2a-108d-4f68-815a-dacc696980ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695521987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1695521987
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2484015179
Short name T404
Test name
Test status
Simulation time 93017531 ps
CPU time 2.01 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:33:08 PM PDT 24
Peak memory 191392 kb
Host smart-596ec5a8-3de7-42cd-9a9a-7b8ef1cfcefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484015179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2484015179
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3649560665
Short name T449
Test name
Test status
Simulation time 99967905527 ps
CPU time 146.12 seconds
Started Aug 09 04:32:51 PM PDT 24
Finished Aug 09 04:35:17 PM PDT 24
Peak memory 191420 kb
Host smart-460f217b-2b19-4d5f-a8b1-f4e78a7e48ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649560665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3649560665
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1466398723
Short name T222
Test name
Test status
Simulation time 461168694882 ps
CPU time 201.59 seconds
Started Aug 09 04:33:09 PM PDT 24
Finished Aug 09 04:36:30 PM PDT 24
Peak memory 183308 kb
Host smart-71dc37d7-415e-4384-a81f-1f53ae2b461f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466398723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1466398723
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3121862202
Short name T353
Test name
Test status
Simulation time 137999679552 ps
CPU time 188.73 seconds
Started Aug 09 04:32:51 PM PDT 24
Finished Aug 09 04:36:00 PM PDT 24
Peak memory 183184 kb
Host smart-ee385392-36de-4797-9033-245be3878ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121862202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3121862202
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1161636873
Short name T328
Test name
Test status
Simulation time 231991072361 ps
CPU time 445.09 seconds
Started Aug 09 04:32:57 PM PDT 24
Finished Aug 09 04:40:22 PM PDT 24
Peak memory 191480 kb
Host smart-14a3fdae-9c2c-42d3-a30b-263475e68106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161636873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1161636873
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2007735085
Short name T350
Test name
Test status
Simulation time 805252560 ps
CPU time 4.45 seconds
Started Aug 09 04:32:59 PM PDT 24
Finished Aug 09 04:33:04 PM PDT 24
Peak memory 191340 kb
Host smart-e55a2b2c-47f3-41be-8490-be895027342f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007735085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2007735085
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1121096794
Short name T442
Test name
Test status
Simulation time 265485860054 ps
CPU time 511.42 seconds
Started Aug 09 04:32:59 PM PDT 24
Finished Aug 09 04:41:31 PM PDT 24
Peak memory 195512 kb
Host smart-084595e4-3e44-4b57-8143-ec28b589fb97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121096794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1121096794
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2972984552
Short name T163
Test name
Test status
Simulation time 1555542651753 ps
CPU time 544.15 seconds
Started Aug 09 04:32:51 PM PDT 24
Finished Aug 09 04:41:55 PM PDT 24
Peak memory 183292 kb
Host smart-b482273c-263a-4caf-a6a0-6671e6b4941e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972984552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2972984552
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.4091603310
Short name T360
Test name
Test status
Simulation time 336674239989 ps
CPU time 95.58 seconds
Started Aug 09 04:32:44 PM PDT 24
Finished Aug 09 04:34:20 PM PDT 24
Peak memory 183268 kb
Host smart-1192a597-99cc-4fe5-8ce1-309d7495764b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091603310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.4091603310
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2056173014
Short name T340
Test name
Test status
Simulation time 461086184651 ps
CPU time 255.43 seconds
Started Aug 09 04:32:57 PM PDT 24
Finished Aug 09 04:37:13 PM PDT 24
Peak memory 191468 kb
Host smart-e3a7f498-1a60-4e0f-92e4-a20f4c6d8626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056173014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2056173014
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.178117021
Short name T405
Test name
Test status
Simulation time 79521828 ps
CPU time 0.63 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:33:07 PM PDT 24
Peak memory 183104 kb
Host smart-4c518cec-b50a-4dc9-bdc6-bf59955b6af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178117021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.178117021
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.966784203
Short name T86
Test name
Test status
Simulation time 445400598978 ps
CPU time 671.3 seconds
Started Aug 09 04:32:54 PM PDT 24
Finished Aug 09 04:44:06 PM PDT 24
Peak memory 191428 kb
Host smart-49b8bb62-5650-468f-baf7-8b662a87f564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966784203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
966784203
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.702905093
Short name T329
Test name
Test status
Simulation time 1216906421700 ps
CPU time 680.53 seconds
Started Aug 09 04:32:55 PM PDT 24
Finished Aug 09 04:44:16 PM PDT 24
Peak memory 183260 kb
Host smart-05a8f8b6-56b6-4c0b-af29-8766c300dbdd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702905093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.702905093
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.545667682
Short name T363
Test name
Test status
Simulation time 92619566815 ps
CPU time 115.72 seconds
Started Aug 09 04:32:57 PM PDT 24
Finished Aug 09 04:34:53 PM PDT 24
Peak memory 183216 kb
Host smart-13830b7f-c7e9-4923-99a2-55e73a88da20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545667682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.545667682
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2436217791
Short name T434
Test name
Test status
Simulation time 697452207274 ps
CPU time 334.54 seconds
Started Aug 09 04:33:02 PM PDT 24
Finished Aug 09 04:38:37 PM PDT 24
Peak memory 191536 kb
Host smart-aa24a856-44e1-4331-b6b5-1faa8f242249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436217791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2436217791
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3751277584
Short name T447
Test name
Test status
Simulation time 24361001051 ps
CPU time 19.78 seconds
Started Aug 09 04:32:50 PM PDT 24
Finished Aug 09 04:33:10 PM PDT 24
Peak memory 183244 kb
Host smart-3b25176f-4c89-4e6e-b045-b81d9daaeff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751277584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3751277584
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1819208791
Short name T42
Test name
Test status
Simulation time 455649268602 ps
CPU time 692.77 seconds
Started Aug 09 04:32:53 PM PDT 24
Finished Aug 09 04:44:26 PM PDT 24
Peak memory 191476 kb
Host smart-44b48b52-822c-4a69-9de8-267c3e973223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819208791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1819208791
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3223570063
Short name T289
Test name
Test status
Simulation time 40626727242 ps
CPU time 62.88 seconds
Started Aug 09 04:32:44 PM PDT 24
Finished Aug 09 04:33:47 PM PDT 24
Peak memory 183256 kb
Host smart-b7f018c1-c976-4dd3-8393-aa2e865b4b22
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223570063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3223570063
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1120480544
Short name T359
Test name
Test status
Simulation time 80469226951 ps
CPU time 54.1 seconds
Started Aug 09 04:32:51 PM PDT 24
Finished Aug 09 04:33:45 PM PDT 24
Peak memory 183268 kb
Host smart-4d046499-6441-4ae0-abef-602569bf9f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120480544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1120480544
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.348295579
Short name T294
Test name
Test status
Simulation time 115170449404 ps
CPU time 197.79 seconds
Started Aug 09 04:32:56 PM PDT 24
Finished Aug 09 04:36:14 PM PDT 24
Peak memory 191528 kb
Host smart-605846f2-fdca-457c-85dd-d15b8c8d0a7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348295579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.348295579
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.4002714485
Short name T240
Test name
Test status
Simulation time 42347167342 ps
CPU time 344.65 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:38:57 PM PDT 24
Peak memory 191412 kb
Host smart-a0744c9c-d29c-4801-bdc2-b195589067d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002714485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.4002714485
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3945853027
Short name T60
Test name
Test status
Simulation time 145416419316 ps
CPU time 237.76 seconds
Started Aug 09 04:33:02 PM PDT 24
Finished Aug 09 04:37:00 PM PDT 24
Peak memory 183312 kb
Host smart-751fae8c-ead3-4e06-a2e7-5c1341f9d00f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945853027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3945853027
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.515446759
Short name T330
Test name
Test status
Simulation time 244434802236 ps
CPU time 362.33 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:39:14 PM PDT 24
Peak memory 183332 kb
Host smart-cec00f96-b682-41c0-80a9-e66a99ca360a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515446759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.515446759
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1465407035
Short name T395
Test name
Test status
Simulation time 176045446987 ps
CPU time 262.82 seconds
Started Aug 09 04:33:11 PM PDT 24
Finished Aug 09 04:37:34 PM PDT 24
Peak memory 183308 kb
Host smart-df97be94-6e2c-44c5-a3e3-bdcccb4cc4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465407035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1465407035
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.342327298
Short name T144
Test name
Test status
Simulation time 49017047289 ps
CPU time 199.67 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:36:32 PM PDT 24
Peak memory 191608 kb
Host smart-71c7073c-c07d-497c-8a81-f23fe0a77fa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342327298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.342327298
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3985021689
Short name T346
Test name
Test status
Simulation time 67024493559 ps
CPU time 15.63 seconds
Started Aug 09 04:32:53 PM PDT 24
Finished Aug 09 04:33:09 PM PDT 24
Peak memory 183096 kb
Host smart-5f909562-2d81-4da7-8659-43591617c413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985021689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3985021689
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1417017412
Short name T300
Test name
Test status
Simulation time 434500160185 ps
CPU time 713.58 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:45:10 PM PDT 24
Peak memory 183256 kb
Host smart-ad1710a2-4c6f-4a24-8760-62217a9133db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417017412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1417017412
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3982681719
Short name T58
Test name
Test status
Simulation time 373065912100 ps
CPU time 132.07 seconds
Started Aug 09 04:33:59 PM PDT 24
Finished Aug 09 04:36:11 PM PDT 24
Peak memory 182928 kb
Host smart-ab74ac2c-d19a-460f-950e-e364bf19d126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982681719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3982681719
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.648398355
Short name T56
Test name
Test status
Simulation time 30815602739 ps
CPU time 65.06 seconds
Started Aug 09 04:33:07 PM PDT 24
Finished Aug 09 04:34:12 PM PDT 24
Peak memory 191444 kb
Host smart-61aaff1a-3e23-43d9-ae1e-a9029154be55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648398355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.648398355
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1090408951
Short name T298
Test name
Test status
Simulation time 17976083070 ps
CPU time 28.55 seconds
Started Aug 09 04:33:01 PM PDT 24
Finished Aug 09 04:33:29 PM PDT 24
Peak memory 183196 kb
Host smart-b47b1cf7-2489-4a19-9a50-bae1a562c84b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090408951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1090408951
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3408127988
Short name T51
Test name
Test status
Simulation time 108436907034 ps
CPU time 175.7 seconds
Started Aug 09 04:33:13 PM PDT 24
Finished Aug 09 04:36:09 PM PDT 24
Peak memory 183344 kb
Host smart-fe18d91e-08a8-49ab-8d02-1b9390b694f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408127988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3408127988
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.838574748
Short name T322
Test name
Test status
Simulation time 65049303390 ps
CPU time 123.4 seconds
Started Aug 09 04:32:55 PM PDT 24
Finished Aug 09 04:34:59 PM PDT 24
Peak memory 191492 kb
Host smart-79073ed9-b445-4f93-8793-2ab8686bb477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838574748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.838574748
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1078505365
Short name T362
Test name
Test status
Simulation time 40866451 ps
CPU time 0.55 seconds
Started Aug 09 04:33:00 PM PDT 24
Finished Aug 09 04:33:01 PM PDT 24
Peak memory 183016 kb
Host smart-3e8462cb-d5bc-4918-a67a-547e467311b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078505365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1078505365
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3081968378
Short name T213
Test name
Test status
Simulation time 1334676354467 ps
CPU time 595.65 seconds
Started Aug 09 04:32:56 PM PDT 24
Finished Aug 09 04:42:52 PM PDT 24
Peak memory 191472 kb
Host smart-e67a9a28-83aa-4c9e-ad3d-75ae722c38b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081968378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3081968378
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1122143362
Short name T145
Test name
Test status
Simulation time 1497681729103 ps
CPU time 461.91 seconds
Started Aug 09 04:32:20 PM PDT 24
Finished Aug 09 04:40:02 PM PDT 24
Peak memory 183248 kb
Host smart-48dc84d1-57f6-4298-a53f-f6458f25e539
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122143362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1122143362
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.433522847
Short name T441
Test name
Test status
Simulation time 92994715985 ps
CPU time 68.85 seconds
Started Aug 09 04:32:40 PM PDT 24
Finished Aug 09 04:33:49 PM PDT 24
Peak memory 183328 kb
Host smart-3fe57cad-9adf-4a99-ab06-008de53f0b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433522847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.433522847
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3459055894
Short name T339
Test name
Test status
Simulation time 125149274048 ps
CPU time 116 seconds
Started Aug 09 04:33:00 PM PDT 24
Finished Aug 09 04:34:56 PM PDT 24
Peak memory 183276 kb
Host smart-b172f1fd-7b0c-49b4-8600-f150b9a65e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459055894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3459055894
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.564912840
Short name T17
Test name
Test status
Simulation time 680587155 ps
CPU time 0.87 seconds
Started Aug 09 04:33:10 PM PDT 24
Finished Aug 09 04:33:11 PM PDT 24
Peak memory 214496 kb
Host smart-cb18d644-ede9-427c-ab2d-241d2933e945
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564912840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.564912840
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2635986045
Short name T374
Test name
Test status
Simulation time 68169530174 ps
CPU time 51.71 seconds
Started Aug 09 04:32:39 PM PDT 24
Finished Aug 09 04:33:30 PM PDT 24
Peak memory 194992 kb
Host smart-35ca4c26-ae9b-4db2-a5d4-03e66d863950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635986045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2635986045
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3200549794
Short name T258
Test name
Test status
Simulation time 4344931801506 ps
CPU time 2158.19 seconds
Started Aug 09 04:32:56 PM PDT 24
Finished Aug 09 05:08:54 PM PDT 24
Peak memory 183256 kb
Host smart-dd4f32aa-00b9-442a-8ee0-e2ed9bbde564
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200549794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3200549794
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2265947579
Short name T421
Test name
Test status
Simulation time 314366344899 ps
CPU time 112.51 seconds
Started Aug 09 04:33:59 PM PDT 24
Finished Aug 09 04:35:52 PM PDT 24
Peak memory 182976 kb
Host smart-6f4e987a-6179-47be-8bce-84ff3e4f5730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265947579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2265947579
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1766548172
Short name T194
Test name
Test status
Simulation time 135029186788 ps
CPU time 168.85 seconds
Started Aug 09 04:33:14 PM PDT 24
Finished Aug 09 04:36:03 PM PDT 24
Peak memory 191424 kb
Host smart-a6b7be2b-9121-4601-8ab8-ec092fb2240b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766548172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1766548172
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.73395335
Short name T393
Test name
Test status
Simulation time 20501372 ps
CPU time 0.55 seconds
Started Aug 09 04:33:02 PM PDT 24
Finished Aug 09 04:33:03 PM PDT 24
Peak memory 183444 kb
Host smart-1e926fbc-2025-4abf-8ccf-94b09fae28be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73395335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.73395335
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2374267630
Short name T429
Test name
Test status
Simulation time 265164101961 ps
CPU time 436.18 seconds
Started Aug 09 04:33:00 PM PDT 24
Finished Aug 09 04:40:16 PM PDT 24
Peak memory 183204 kb
Host smart-020ed657-a212-41c4-9506-d935f83850ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374267630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2374267630
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1049285661
Short name T355
Test name
Test status
Simulation time 69149671883 ps
CPU time 26.79 seconds
Started Aug 09 04:33:02 PM PDT 24
Finished Aug 09 04:33:29 PM PDT 24
Peak memory 183272 kb
Host smart-c4998a96-01ba-4de8-bdfa-87392160bf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049285661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1049285661
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.4182351943
Short name T90
Test name
Test status
Simulation time 489993618631 ps
CPU time 102.48 seconds
Started Aug 09 04:33:02 PM PDT 24
Finished Aug 09 04:34:45 PM PDT 24
Peak memory 191512 kb
Host smart-c44f2035-cb3b-47a3-ac47-d944cbcd38ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182351943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4182351943
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1997947848
Short name T116
Test name
Test status
Simulation time 50299506261 ps
CPU time 43.69 seconds
Started Aug 09 04:32:59 PM PDT 24
Finished Aug 09 04:33:43 PM PDT 24
Peak memory 194932 kb
Host smart-e9cbc2fa-6a5e-43be-b790-ba92bb25405a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997947848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1997947848
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1672378515
Short name T62
Test name
Test status
Simulation time 24137615 ps
CPU time 0.61 seconds
Started Aug 09 04:33:13 PM PDT 24
Finished Aug 09 04:33:14 PM PDT 24
Peak memory 183040 kb
Host smart-f9cf7e3b-0f8e-4eb3-b7a3-a48c4e186ad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672378515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1672378515
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.28661056
Short name T435
Test name
Test status
Simulation time 176348225879 ps
CPU time 261.32 seconds
Started Aug 09 04:33:00 PM PDT 24
Finished Aug 09 04:37:21 PM PDT 24
Peak memory 183228 kb
Host smart-aad8c0fd-b5f8-43f1-89f0-c303ab09e13c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28661056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.rv_timer_cfg_update_on_fly.28661056
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.912593635
Short name T398
Test name
Test status
Simulation time 131331088924 ps
CPU time 177.17 seconds
Started Aug 09 04:33:08 PM PDT 24
Finished Aug 09 04:36:05 PM PDT 24
Peak memory 183316 kb
Host smart-c35815c6-8cd2-4922-9465-0017463c2e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912593635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.912593635
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.326455404
Short name T246
Test name
Test status
Simulation time 86329988797 ps
CPU time 128.87 seconds
Started Aug 09 04:33:50 PM PDT 24
Finished Aug 09 04:36:00 PM PDT 24
Peak memory 190604 kb
Host smart-a5d7462b-b255-4af4-9cf9-0267437b99d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326455404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.326455404
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2540604527
Short name T156
Test name
Test status
Simulation time 73350728565 ps
CPU time 108.32 seconds
Started Aug 09 04:33:09 PM PDT 24
Finished Aug 09 04:34:58 PM PDT 24
Peak memory 183332 kb
Host smart-1dd3d92f-b973-48b0-a6d9-a6e8ad17536c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540604527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2540604527
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.4278637483
Short name T394
Test name
Test status
Simulation time 54428662841 ps
CPU time 84.42 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:34:42 PM PDT 24
Peak memory 183188 kb
Host smart-404222a6-9075-4139-805a-de8efa78e90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278637483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.4278637483
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3787383048
Short name T119
Test name
Test status
Simulation time 265920958062 ps
CPU time 264.44 seconds
Started Aug 09 04:32:52 PM PDT 24
Finished Aug 09 04:37:17 PM PDT 24
Peak memory 191492 kb
Host smart-64c5fc33-2d6d-4a10-be63-946bb54f6fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787383048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3787383048
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2159850583
Short name T307
Test name
Test status
Simulation time 539150543722 ps
CPU time 146.74 seconds
Started Aug 09 04:32:56 PM PDT 24
Finished Aug 09 04:35:23 PM PDT 24
Peak memory 195012 kb
Host smart-415addf6-a1b3-4e40-acfd-afaacb63ebde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159850583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2159850583
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3886365812
Short name T427
Test name
Test status
Simulation time 70863369 ps
CPU time 0.54 seconds
Started Aug 09 04:33:07 PM PDT 24
Finished Aug 09 04:33:07 PM PDT 24
Peak memory 182580 kb
Host smart-ce752e04-f9ea-4fff-9a6a-a5a3afc10f5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886365812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3886365812
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.808179557
Short name T400
Test name
Test status
Simulation time 18382591188 ps
CPU time 22.2 seconds
Started Aug 09 04:32:57 PM PDT 24
Finished Aug 09 04:33:19 PM PDT 24
Peak memory 183276 kb
Host smart-d7af0769-9a2a-447c-b6ad-93db158ac22b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808179557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.808179557
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2070252840
Short name T358
Test name
Test status
Simulation time 61083204742 ps
CPU time 85.18 seconds
Started Aug 09 04:33:57 PM PDT 24
Finished Aug 09 04:35:23 PM PDT 24
Peak memory 182992 kb
Host smart-8b5b1a7e-7239-4bd0-9e9b-930e4c4688ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070252840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2070252840
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3818189001
Short name T327
Test name
Test status
Simulation time 85136345899 ps
CPU time 92.89 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:34:45 PM PDT 24
Peak memory 191428 kb
Host smart-9ffaf177-4ad3-4aa3-a272-e11fdb74b6ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818189001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3818189001
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1163105016
Short name T88
Test name
Test status
Simulation time 904236967 ps
CPU time 1.13 seconds
Started Aug 09 04:33:01 PM PDT 24
Finished Aug 09 04:33:02 PM PDT 24
Peak memory 193596 kb
Host smart-120426df-49b6-4416-923f-4e4088290997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163105016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1163105016
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.2094307674
Short name T39
Test name
Test status
Simulation time 192693147304 ps
CPU time 618.57 seconds
Started Aug 09 04:33:08 PM PDT 24
Finished Aug 09 04:43:26 PM PDT 24
Peak memory 212352 kb
Host smart-23a1d5fd-adb3-4c4d-ab21-58aaab026759
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094307674 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.2094307674
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.292819559
Short name T239
Test name
Test status
Simulation time 129406051635 ps
CPU time 67.92 seconds
Started Aug 09 04:33:08 PM PDT 24
Finished Aug 09 04:34:16 PM PDT 24
Peak memory 183328 kb
Host smart-2b8793e2-87f1-4018-9dc6-2b0230829113
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292819559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.292819559
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3650835480
Short name T391
Test name
Test status
Simulation time 132472695782 ps
CPU time 92.97 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:34:39 PM PDT 24
Peak memory 183276 kb
Host smart-b28bc23a-4606-4f28-9b14-733c6f32447d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650835480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3650835480
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.143185114
Short name T356
Test name
Test status
Simulation time 45784578 ps
CPU time 0.59 seconds
Started Aug 09 04:33:13 PM PDT 24
Finished Aug 09 04:33:13 PM PDT 24
Peak memory 183012 kb
Host smart-5355c98d-7027-469a-8bfd-aefab80f5c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143185114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.143185114
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1007435641
Short name T225
Test name
Test status
Simulation time 3390175740 ps
CPU time 5.93 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:33:12 PM PDT 24
Peak memory 183244 kb
Host smart-5a8a3314-2198-4380-a2e1-0e1c6fdb9842
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007435641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1007435641
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.829309078
Short name T406
Test name
Test status
Simulation time 85011423265 ps
CPU time 109.16 seconds
Started Aug 09 04:33:14 PM PDT 24
Finished Aug 09 04:35:03 PM PDT 24
Peak memory 183300 kb
Host smart-61523117-56e1-4a04-873c-e9426671d7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829309078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.829309078
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2233978484
Short name T161
Test name
Test status
Simulation time 738973822764 ps
CPU time 370.67 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:39:28 PM PDT 24
Peak memory 191388 kb
Host smart-76a6b52d-6c03-4903-9d8b-ab8cc0d7ac7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233978484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2233978484
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2098286416
Short name T334
Test name
Test status
Simulation time 103337270424 ps
CPU time 507.07 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:41:34 PM PDT 24
Peak memory 183244 kb
Host smart-e83c21a3-10ce-499e-9bd4-bbf0e6dceeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098286416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2098286416
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.551091775
Short name T41
Test name
Test status
Simulation time 303827137365 ps
CPU time 236.2 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:37:12 PM PDT 24
Peak memory 183244 kb
Host smart-8c73f82c-de83-4b4e-9a62-d5513592b247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551091775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
551091775
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2639364171
Short name T148
Test name
Test status
Simulation time 293698638434 ps
CPU time 456.67 seconds
Started Aug 09 04:33:13 PM PDT 24
Finished Aug 09 04:40:50 PM PDT 24
Peak memory 183228 kb
Host smart-a208a676-eab6-4caa-a590-915b695594cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639364171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2639364171
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.4211511469
Short name T392
Test name
Test status
Simulation time 649598517086 ps
CPU time 244.35 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:37:11 PM PDT 24
Peak memory 183260 kb
Host smart-3c21bb25-b2c8-413a-a5fe-020b9c874587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211511469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.4211511469
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3469410715
Short name T415
Test name
Test status
Simulation time 301395769 ps
CPU time 0.73 seconds
Started Aug 09 04:33:18 PM PDT 24
Finished Aug 09 04:33:19 PM PDT 24
Peak memory 183024 kb
Host smart-23223ef3-a136-46a7-8783-2607f6923984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469410715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3469410715
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1031668216
Short name T299
Test name
Test status
Simulation time 61703526548 ps
CPU time 35.87 seconds
Started Aug 09 04:33:05 PM PDT 24
Finished Aug 09 04:33:41 PM PDT 24
Peak memory 183260 kb
Host smart-e04667b0-dfc7-474f-817a-3fb0bf231282
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031668216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1031668216
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.4232704692
Short name T387
Test name
Test status
Simulation time 121010599498 ps
CPU time 80.17 seconds
Started Aug 09 04:32:54 PM PDT 24
Finished Aug 09 04:34:14 PM PDT 24
Peak memory 183280 kb
Host smart-df6099ec-bd2d-48d7-b6eb-e08e023131a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232704692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4232704692
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1234616595
Short name T445
Test name
Test status
Simulation time 57388177890 ps
CPU time 86.35 seconds
Started Aug 09 04:32:57 PM PDT 24
Finished Aug 09 04:34:23 PM PDT 24
Peak memory 191472 kb
Host smart-6f9a95cd-eb1c-4c66-90ac-c35615a27812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234616595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1234616595
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2642782969
Short name T207
Test name
Test status
Simulation time 1048614988387 ps
CPU time 638.78 seconds
Started Aug 09 04:32:58 PM PDT 24
Finished Aug 09 04:43:42 PM PDT 24
Peak memory 183196 kb
Host smart-3fe6c9ed-6eb5-4ec7-83fb-3e75b65568b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642782969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2642782969
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3120909958
Short name T444
Test name
Test status
Simulation time 157390591890 ps
CPU time 60.27 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:34:12 PM PDT 24
Peak memory 183268 kb
Host smart-a49a8819-38c4-4cfa-8bc1-c9f0f75af122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120909958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3120909958
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3417161691
Short name T419
Test name
Test status
Simulation time 1391516649 ps
CPU time 2.84 seconds
Started Aug 09 04:33:01 PM PDT 24
Finished Aug 09 04:33:04 PM PDT 24
Peak memory 182968 kb
Host smart-cf78c4d8-672e-496b-af78-b31d7983daf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417161691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3417161691
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.364468461
Short name T342
Test name
Test status
Simulation time 1388567214381 ps
CPU time 1057.94 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:50:44 PM PDT 24
Peak memory 191472 kb
Host smart-93ed8560-e1c4-459b-ac04-d0169899d3b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364468461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
364468461
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1171045863
Short name T378
Test name
Test status
Simulation time 246425567797 ps
CPU time 100.81 seconds
Started Aug 09 04:32:17 PM PDT 24
Finished Aug 09 04:33:58 PM PDT 24
Peak memory 183316 kb
Host smart-921afa18-af67-45b6-b843-30bd19afbe53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171045863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1171045863
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3580545239
Short name T397
Test name
Test status
Simulation time 27641489944 ps
CPU time 38.35 seconds
Started Aug 09 04:32:34 PM PDT 24
Finished Aug 09 04:33:12 PM PDT 24
Peak memory 183336 kb
Host smart-32839292-1343-45d4-8284-abc0f8c3ed52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580545239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3580545239
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3387619881
Short name T139
Test name
Test status
Simulation time 253899419098 ps
CPU time 126.47 seconds
Started Aug 09 04:32:24 PM PDT 24
Finished Aug 09 04:34:31 PM PDT 24
Peak memory 191476 kb
Host smart-49530d7b-38c3-4463-b190-07518463113f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387619881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3387619881
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.3392190037
Short name T89
Test name
Test status
Simulation time 124816717557 ps
CPU time 106.38 seconds
Started Aug 09 04:33:04 PM PDT 24
Finished Aug 09 04:34:50 PM PDT 24
Peak memory 191556 kb
Host smart-2505af62-ba4d-44fe-852d-e4b1aba80f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392190037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3392190037
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.570199308
Short name T127
Test name
Test status
Simulation time 737746025447 ps
CPU time 567.53 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:42:40 PM PDT 24
Peak memory 191540 kb
Host smart-7d730cc5-1386-48eb-9be9-bf2184947c1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570199308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.570199308
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2816795421
Short name T348
Test name
Test status
Simulation time 159410891243 ps
CPU time 186.9 seconds
Started Aug 09 04:33:25 PM PDT 24
Finished Aug 09 04:36:32 PM PDT 24
Peak memory 191608 kb
Host smart-fc4540e6-ddaa-4794-b0b9-9c14ccd6adaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816795421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2816795421
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1484396479
Short name T200
Test name
Test status
Simulation time 220536564634 ps
CPU time 83.18 seconds
Started Aug 09 04:33:03 PM PDT 24
Finished Aug 09 04:34:26 PM PDT 24
Peak memory 195176 kb
Host smart-d88e220e-b4ba-477b-a46b-64304b279e2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484396479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1484396479
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1337622966
Short name T411
Test name
Test status
Simulation time 106588979365 ps
CPU time 227.41 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:36:54 PM PDT 24
Peak memory 183364 kb
Host smart-f9c490dc-cab3-4763-af15-77b3f6f65966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337622966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1337622966
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3270569938
Short name T196
Test name
Test status
Simulation time 219547361494 ps
CPU time 115.07 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:35:07 PM PDT 24
Peak memory 191496 kb
Host smart-5238cac1-0aba-430d-bd8d-4dbef7c7842f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270569938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3270569938
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1007955122
Short name T189
Test name
Test status
Simulation time 308150819079 ps
CPU time 434.25 seconds
Started Aug 09 04:33:10 PM PDT 24
Finished Aug 09 04:40:25 PM PDT 24
Peak memory 183228 kb
Host smart-b19fb58c-f636-43c5-89be-f3154afa82fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007955122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1007955122
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3477675373
Short name T370
Test name
Test status
Simulation time 119420374103 ps
CPU time 169.22 seconds
Started Aug 09 04:32:23 PM PDT 24
Finished Aug 09 04:35:12 PM PDT 24
Peak memory 183320 kb
Host smart-52cf83ce-4271-4aa1-a0c9-e88335af325b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477675373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3477675373
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.523665182
Short name T285
Test name
Test status
Simulation time 312287124048 ps
CPU time 179.14 seconds
Started Aug 09 04:33:12 PM PDT 24
Finished Aug 09 04:36:12 PM PDT 24
Peak memory 191436 kb
Host smart-91411d7a-5b8b-4e3d-917c-7b3378401d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523665182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.523665182
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.177857403
Short name T231
Test name
Test status
Simulation time 32932920675 ps
CPU time 30.93 seconds
Started Aug 09 04:33:01 PM PDT 24
Finished Aug 09 04:33:32 PM PDT 24
Peak memory 194424 kb
Host smart-09e646ea-8560-46cc-9ff5-1980308ee6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177857403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.177857403
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2129784756
Short name T125
Test name
Test status
Simulation time 459595698458 ps
CPU time 186.95 seconds
Started Aug 09 04:32:43 PM PDT 24
Finished Aug 09 04:35:50 PM PDT 24
Peak memory 191468 kb
Host smart-1c4c36bd-578f-4345-a7a1-05e3109875ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129784756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2129784756
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.3243572573
Short name T214
Test name
Test status
Simulation time 266256024045 ps
CPU time 895.84 seconds
Started Aug 09 04:32:57 PM PDT 24
Finished Aug 09 04:47:53 PM PDT 24
Peak memory 191480 kb
Host smart-48507756-d511-426b-8a47-3ebe886b4687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243572573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3243572573
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2272090469
Short name T72
Test name
Test status
Simulation time 1400221438359 ps
CPU time 441.33 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:40:38 PM PDT 24
Peak memory 191444 kb
Host smart-c4265388-64cb-49ed-9141-4a87d22f25f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272090469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2272090469
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2399856456
Short name T168
Test name
Test status
Simulation time 235938428339 ps
CPU time 128.53 seconds
Started Aug 09 04:33:11 PM PDT 24
Finished Aug 09 04:35:20 PM PDT 24
Peak memory 191504 kb
Host smart-b5d54742-d4a8-4a40-b615-ded317c8560f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399856456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2399856456
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2015583501
Short name T154
Test name
Test status
Simulation time 151595487996 ps
CPU time 335.19 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 04:38:52 PM PDT 24
Peak memory 191424 kb
Host smart-83b24df3-58f7-4791-ae85-afe7b2de3312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015583501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2015583501
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2428412813
Short name T345
Test name
Test status
Simulation time 88813491892 ps
CPU time 170.32 seconds
Started Aug 09 04:32:57 PM PDT 24
Finished Aug 09 04:35:47 PM PDT 24
Peak memory 191504 kb
Host smart-55eb0f8c-6b6b-4d37-8077-83b20ad3f663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428412813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2428412813
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2085100661
Short name T262
Test name
Test status
Simulation time 737365111203 ps
CPU time 328.47 seconds
Started Aug 09 04:33:14 PM PDT 24
Finished Aug 09 04:38:43 PM PDT 24
Peak memory 191492 kb
Host smart-98b90e91-4c2f-46bf-bb64-fb365d927fc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085100661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2085100661
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1543422952
Short name T229
Test name
Test status
Simulation time 81409756593 ps
CPU time 60.01 seconds
Started Aug 09 04:33:11 PM PDT 24
Finished Aug 09 04:34:11 PM PDT 24
Peak memory 183300 kb
Host smart-e9fd423b-5df6-48b9-b319-59ac3b73d690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543422952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1543422952
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.918363745
Short name T137
Test name
Test status
Simulation time 100145104609 ps
CPU time 586.38 seconds
Started Aug 09 04:33:04 PM PDT 24
Finished Aug 09 04:42:50 PM PDT 24
Peak memory 191420 kb
Host smart-9c1fa0ad-ce0e-4ee7-b357-65f98a268e27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918363745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.918363745
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1143493855
Short name T248
Test name
Test status
Simulation time 73939449960 ps
CPU time 122.31 seconds
Started Aug 09 04:32:46 PM PDT 24
Finished Aug 09 04:34:54 PM PDT 24
Peak memory 183260 kb
Host smart-d641a4a9-9374-475d-ada4-470a5011b290
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143493855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1143493855
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.926681676
Short name T414
Test name
Test status
Simulation time 745489642829 ps
CPU time 138 seconds
Started Aug 09 04:32:58 PM PDT 24
Finished Aug 09 04:35:16 PM PDT 24
Peak memory 183276 kb
Host smart-d25de144-552f-4192-96a8-7c1ae3f55cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926681676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.926681676
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3502363861
Short name T117
Test name
Test status
Simulation time 118542453304 ps
CPU time 203.83 seconds
Started Aug 09 04:32:39 PM PDT 24
Finished Aug 09 04:36:03 PM PDT 24
Peak memory 191496 kb
Host smart-5031d4b6-9e33-48f4-87ef-371780ee285c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502363861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3502363861
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3701957016
Short name T380
Test name
Test status
Simulation time 226545728 ps
CPU time 0.76 seconds
Started Aug 09 04:32:49 PM PDT 24
Finished Aug 09 04:32:50 PM PDT 24
Peak memory 191572 kb
Host smart-7e400325-eb3f-4dfc-9040-f4f1d13d25ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701957016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3701957016
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.654728891
Short name T3
Test name
Test status
Simulation time 986631398266 ps
CPU time 378.85 seconds
Started Aug 09 04:32:27 PM PDT 24
Finished Aug 09 04:38:46 PM PDT 24
Peak memory 191452 kb
Host smart-01e348ab-1512-4d50-b01d-de8620b230d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654728891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.654728891
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.1005330566
Short name T286
Test name
Test status
Simulation time 556582284307 ps
CPU time 502.01 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:41:38 PM PDT 24
Peak memory 191464 kb
Host smart-c381541d-be02-421c-bf99-61e72e75f871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005330566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1005330566
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3992976487
Short name T195
Test name
Test status
Simulation time 94037515285 ps
CPU time 409.77 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:40:06 PM PDT 24
Peak memory 191484 kb
Host smart-94003bac-1fa9-42a5-b638-c99c3997a103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992976487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3992976487
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3314508856
Short name T309
Test name
Test status
Simulation time 428772897948 ps
CPU time 116.26 seconds
Started Aug 09 04:33:13 PM PDT 24
Finished Aug 09 04:35:09 PM PDT 24
Peak memory 191444 kb
Host smart-7268727e-d0eb-481a-bbe7-2d275a07bd83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314508856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3314508856
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2543337399
Short name T282
Test name
Test status
Simulation time 451925265397 ps
CPU time 628.34 seconds
Started Aug 09 04:33:27 PM PDT 24
Finished Aug 09 04:43:56 PM PDT 24
Peak memory 191476 kb
Host smart-14c5400c-95ea-4714-9b38-551ad529c515
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543337399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2543337399
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2589756504
Short name T344
Test name
Test status
Simulation time 42957947400 ps
CPU time 67.51 seconds
Started Aug 09 04:33:20 PM PDT 24
Finished Aug 09 04:34:28 PM PDT 24
Peak memory 183264 kb
Host smart-b3c84832-c509-47fd-91d1-b8df0818ccfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589756504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2589756504
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3499254883
Short name T253
Test name
Test status
Simulation time 99868603839 ps
CPU time 46.36 seconds
Started Aug 09 04:33:14 PM PDT 24
Finished Aug 09 04:34:01 PM PDT 24
Peak memory 183264 kb
Host smart-21112b05-3a5c-4c0f-9e66-2f68dc6b9219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499254883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3499254883
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1582023188
Short name T402
Test name
Test status
Simulation time 14692450444 ps
CPU time 48.87 seconds
Started Aug 09 04:33:19 PM PDT 24
Finished Aug 09 04:34:08 PM PDT 24
Peak memory 183248 kb
Host smart-82d7a592-303f-406d-9890-85ee2b61b50f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582023188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1582023188
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3225537121
Short name T250
Test name
Test status
Simulation time 298965760936 ps
CPU time 138.75 seconds
Started Aug 09 04:33:20 PM PDT 24
Finished Aug 09 04:35:39 PM PDT 24
Peak memory 191460 kb
Host smart-8e9b27cc-b81b-4c8d-95a3-7e8ef8134662
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225537121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3225537121
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2404789685
Short name T425
Test name
Test status
Simulation time 85822848603 ps
CPU time 67.12 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:34:13 PM PDT 24
Peak memory 183260 kb
Host smart-3f17081d-165e-446b-b4be-9c26ac0fd8dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404789685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2404789685
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.844371470
Short name T269
Test name
Test status
Simulation time 56401189625 ps
CPU time 533.38 seconds
Started Aug 09 04:33:14 PM PDT 24
Finished Aug 09 04:42:08 PM PDT 24
Peak memory 191484 kb
Host smart-e4d55a3c-cab9-4e54-a092-45110adc1044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844371470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.844371470
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1004675182
Short name T275
Test name
Test status
Simulation time 2756777799 ps
CPU time 3.15 seconds
Started Aug 09 04:32:41 PM PDT 24
Finished Aug 09 04:32:44 PM PDT 24
Peak memory 183316 kb
Host smart-85eebd3e-c1fc-4a65-8753-9f1ee436045b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004675182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1004675182
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2560798421
Short name T351
Test name
Test status
Simulation time 261012092901 ps
CPU time 189.63 seconds
Started Aug 09 04:32:50 PM PDT 24
Finished Aug 09 04:35:59 PM PDT 24
Peak memory 183336 kb
Host smart-591545e1-94b9-4728-9a13-554ce376fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560798421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2560798421
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2500290221
Short name T159
Test name
Test status
Simulation time 720739220669 ps
CPU time 1094.83 seconds
Started Aug 09 04:32:46 PM PDT 24
Finished Aug 09 04:51:01 PM PDT 24
Peak memory 191492 kb
Host smart-844f3c4f-f9fd-4854-b353-dd46e62e2b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500290221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2500290221
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.882151629
Short name T409
Test name
Test status
Simulation time 1565863959 ps
CPU time 0.88 seconds
Started Aug 09 04:33:24 PM PDT 24
Finished Aug 09 04:33:25 PM PDT 24
Peak memory 192808 kb
Host smart-d8b355aa-88da-4481-b8a7-c0994b551f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882151629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.882151629
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3580889693
Short name T377
Test name
Test status
Simulation time 436263363742 ps
CPU time 161.56 seconds
Started Aug 09 04:32:43 PM PDT 24
Finished Aug 09 04:35:25 PM PDT 24
Peak memory 193988 kb
Host smart-f9efa7bb-8f93-4a06-a262-cb0ac9bfc1a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580889693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3580889693
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/81.rv_timer_random.1284784644
Short name T121
Test name
Test status
Simulation time 311746373910 ps
CPU time 185.48 seconds
Started Aug 09 04:33:07 PM PDT 24
Finished Aug 09 04:36:12 PM PDT 24
Peak memory 191428 kb
Host smart-3c4767f1-1516-4c4d-af0f-ce2718e2413e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284784644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1284784644
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2804476973
Short name T295
Test name
Test status
Simulation time 53306328985 ps
CPU time 1272.51 seconds
Started Aug 09 04:33:21 PM PDT 24
Finished Aug 09 04:54:34 PM PDT 24
Peak memory 191452 kb
Host smart-8670fa50-5976-45ba-8780-a036ff6102e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804476973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2804476973
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1990041798
Short name T247
Test name
Test status
Simulation time 278075757982 ps
CPU time 134.33 seconds
Started Aug 09 04:33:15 PM PDT 24
Finished Aug 09 04:35:30 PM PDT 24
Peak memory 191476 kb
Host smart-57ab3f78-4bde-4f54-9149-c42c4340d189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990041798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1990041798
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2209102999
Short name T310
Test name
Test status
Simulation time 114690079812 ps
CPU time 200.97 seconds
Started Aug 09 04:33:35 PM PDT 24
Finished Aug 09 04:36:56 PM PDT 24
Peak memory 191492 kb
Host smart-bb1c151e-0a35-4dbc-8900-4f1d2d550206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209102999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2209102999
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1509569003
Short name T67
Test name
Test status
Simulation time 113465947994 ps
CPU time 122.04 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:35:18 PM PDT 24
Peak memory 191516 kb
Host smart-99067206-3574-4d79-8bcd-1463ba62b024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509569003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1509569003
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2048667513
Short name T153
Test name
Test status
Simulation time 77327582970 ps
CPU time 115.15 seconds
Started Aug 09 04:33:59 PM PDT 24
Finished Aug 09 04:35:54 PM PDT 24
Peak memory 191184 kb
Host smart-205af4d5-2bcc-415f-a11c-c2dbec13c77c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048667513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2048667513
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3863182043
Short name T68
Test name
Test status
Simulation time 35873202191 ps
CPU time 60.76 seconds
Started Aug 09 04:33:23 PM PDT 24
Finished Aug 09 04:34:24 PM PDT 24
Peak memory 183272 kb
Host smart-2abf2b97-e072-40c2-aee2-391433316a55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863182043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3863182043
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2973963373
Short name T6
Test name
Test status
Simulation time 520625527012 ps
CPU time 260.55 seconds
Started Aug 09 04:32:55 PM PDT 24
Finished Aug 09 04:37:15 PM PDT 24
Peak memory 183280 kb
Host smart-34910ee3-1155-490d-abe9-5c165c9f4303
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973963373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2973963373
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1128060258
Short name T388
Test name
Test status
Simulation time 299918502832 ps
CPU time 288.3 seconds
Started Aug 09 04:32:39 PM PDT 24
Finished Aug 09 04:37:28 PM PDT 24
Peak memory 183272 kb
Host smart-99cbfd01-bd4a-4066-b9a4-64574832c9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128060258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1128060258
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2145277469
Short name T162
Test name
Test status
Simulation time 616168584140 ps
CPU time 386.56 seconds
Started Aug 09 04:32:44 PM PDT 24
Finished Aug 09 04:39:11 PM PDT 24
Peak memory 191520 kb
Host smart-93bb00bc-8e77-45cb-bda1-05afe1225d75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145277469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2145277469
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1353629437
Short name T221
Test name
Test status
Simulation time 379702184134 ps
CPU time 259.7 seconds
Started Aug 09 04:32:41 PM PDT 24
Finished Aug 09 04:37:01 PM PDT 24
Peak memory 191512 kb
Host smart-aaaed8e4-0140-4d53-82a8-e055a5cf8531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353629437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1353629437
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.148404459
Short name T316
Test name
Test status
Simulation time 850980530740 ps
CPU time 684.83 seconds
Started Aug 09 04:32:59 PM PDT 24
Finished Aug 09 04:44:24 PM PDT 24
Peak memory 191488 kb
Host smart-ad181ee1-2371-4f68-a9a1-b7de052448f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148404459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.148404459
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.2841643794
Short name T24
Test name
Test status
Simulation time 183474350454 ps
CPU time 150.22 seconds
Started Aug 09 04:33:09 PM PDT 24
Finished Aug 09 04:35:40 PM PDT 24
Peak memory 191484 kb
Host smart-1de5d9b4-57b6-4933-bc00-88dae64c8fb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841643794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2841643794
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.4272697039
Short name T130
Test name
Test status
Simulation time 1440112174062 ps
CPU time 808.73 seconds
Started Aug 09 04:33:06 PM PDT 24
Finished Aug 09 04:46:35 PM PDT 24
Peak memory 194508 kb
Host smart-d0841643-7cab-496c-9a0b-9d451b6e4cd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272697039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.4272697039
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1849986017
Short name T73
Test name
Test status
Simulation time 48110075611 ps
CPU time 72.57 seconds
Started Aug 09 04:33:08 PM PDT 24
Finished Aug 09 04:34:20 PM PDT 24
Peak memory 195204 kb
Host smart-25c669c5-0c73-44c2-9774-8bf95bca4d96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849986017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1849986017
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2129164609
Short name T226
Test name
Test status
Simulation time 74692194529 ps
CPU time 277.45 seconds
Started Aug 09 04:33:14 PM PDT 24
Finished Aug 09 04:37:52 PM PDT 24
Peak memory 191520 kb
Host smart-17bfce2f-3b44-41eb-aeb7-0d2dd49ff9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129164609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2129164609
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2599186211
Short name T423
Test name
Test status
Simulation time 66052282988 ps
CPU time 2397.18 seconds
Started Aug 09 04:33:17 PM PDT 24
Finished Aug 09 05:13:15 PM PDT 24
Peak memory 191460 kb
Host smart-8e9a6a49-0b52-4338-bfcd-62cb0d223bca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599186211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2599186211
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3379522252
Short name T210
Test name
Test status
Simulation time 347787908010 ps
CPU time 133.72 seconds
Started Aug 09 04:33:22 PM PDT 24
Finished Aug 09 04:35:36 PM PDT 24
Peak memory 191492 kb
Host smart-f1571b3a-5fc2-4785-a856-f4a7e6d03511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379522252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3379522252
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3377975320
Short name T349
Test name
Test status
Simulation time 85430067018 ps
CPU time 77.57 seconds
Started Aug 09 04:33:18 PM PDT 24
Finished Aug 09 04:34:41 PM PDT 24
Peak memory 183252 kb
Host smart-68a26a03-a8d8-48a3-81f1-51518e80ff67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377975320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3377975320
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2314555739
Short name T83
Test name
Test status
Simulation time 512589894640 ps
CPU time 259.95 seconds
Started Aug 09 04:33:16 PM PDT 24
Finished Aug 09 04:37:36 PM PDT 24
Peak memory 191504 kb
Host smart-85a71188-9b81-4cad-8b9b-9ae8bc2fe539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314555739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2314555739
Directory /workspace/99.rv_timer_random/latest
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