Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.55 99.36 98.73 100.00 100.00 100.00 99.21


Total test records in report: 579
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T509 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1310701760 Aug 10 05:23:36 PM PDT 24 Aug 10 05:23:37 PM PDT 24 38811298 ps
T510 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.4028434811 Aug 10 05:23:41 PM PDT 24 Aug 10 05:23:42 PM PDT 24 46318524 ps
T511 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.585765653 Aug 10 05:23:30 PM PDT 24 Aug 10 05:23:32 PM PDT 24 119284916 ps
T82 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1156871911 Aug 10 05:23:30 PM PDT 24 Aug 10 05:23:31 PM PDT 24 148108568 ps
T512 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3377268096 Aug 10 05:23:42 PM PDT 24 Aug 10 05:23:42 PM PDT 24 34731688 ps
T513 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1930558261 Aug 10 05:23:35 PM PDT 24 Aug 10 05:23:36 PM PDT 24 12966632 ps
T514 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3065042410 Aug 10 05:23:38 PM PDT 24 Aug 10 05:23:39 PM PDT 24 70043779 ps
T515 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4127067399 Aug 10 05:23:46 PM PDT 24 Aug 10 05:23:46 PM PDT 24 17296719 ps
T516 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1914014043 Aug 10 05:23:47 PM PDT 24 Aug 10 05:23:47 PM PDT 24 42442707 ps
T517 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3083948366 Aug 10 05:23:46 PM PDT 24 Aug 10 05:23:47 PM PDT 24 103127581 ps
T518 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3826166046 Aug 10 05:23:45 PM PDT 24 Aug 10 05:23:47 PM PDT 24 637398076 ps
T83 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3272803616 Aug 10 05:23:47 PM PDT 24 Aug 10 05:23:47 PM PDT 24 18930713 ps
T519 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.662275543 Aug 10 05:23:43 PM PDT 24 Aug 10 05:23:44 PM PDT 24 13072185 ps
T520 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.261843469 Aug 10 05:23:37 PM PDT 24 Aug 10 05:23:38 PM PDT 24 25928333 ps
T521 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1128725823 Aug 10 05:23:41 PM PDT 24 Aug 10 05:23:42 PM PDT 24 47163712 ps
T522 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3749741823 Aug 10 05:23:44 PM PDT 24 Aug 10 05:23:46 PM PDT 24 33728667 ps
T523 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1729510092 Aug 10 05:23:47 PM PDT 24 Aug 10 05:23:47 PM PDT 24 240787547 ps
T524 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2096888177 Aug 10 05:23:45 PM PDT 24 Aug 10 05:23:46 PM PDT 24 409537575 ps
T525 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3403308219 Aug 10 05:23:45 PM PDT 24 Aug 10 05:23:46 PM PDT 24 65179368 ps
T526 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.122990389 Aug 10 05:24:27 PM PDT 24 Aug 10 05:24:29 PM PDT 24 18024812 ps
T527 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4090679993 Aug 10 05:23:41 PM PDT 24 Aug 10 05:23:42 PM PDT 24 51513953 ps
T528 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3505721243 Aug 10 05:23:40 PM PDT 24 Aug 10 05:23:41 PM PDT 24 34343306 ps
T529 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1266234095 Aug 10 05:24:41 PM PDT 24 Aug 10 05:24:41 PM PDT 24 14153931 ps
T530 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.337587394 Aug 10 05:23:40 PM PDT 24 Aug 10 05:23:41 PM PDT 24 39429318 ps
T531 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.185231817 Aug 10 05:23:30 PM PDT 24 Aug 10 05:23:30 PM PDT 24 43356945 ps
T532 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1630696895 Aug 10 05:23:35 PM PDT 24 Aug 10 05:23:36 PM PDT 24 11642847 ps
T533 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.505589872 Aug 10 05:23:46 PM PDT 24 Aug 10 05:23:47 PM PDT 24 37375100 ps
T534 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2755278528 Aug 10 05:23:38 PM PDT 24 Aug 10 05:23:39 PM PDT 24 29720989 ps
T535 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3806024506 Aug 10 05:23:38 PM PDT 24 Aug 10 05:23:39 PM PDT 24 18220268 ps
T536 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.7700578 Aug 10 05:23:36 PM PDT 24 Aug 10 05:23:37 PM PDT 24 31445414 ps
T537 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3951586248 Aug 10 05:23:43 PM PDT 24 Aug 10 05:23:44 PM PDT 24 51871135 ps
T538 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.936223092 Aug 10 05:23:39 PM PDT 24 Aug 10 05:23:40 PM PDT 24 45818863 ps
T539 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2337812921 Aug 10 05:23:37 PM PDT 24 Aug 10 05:23:39 PM PDT 24 430006124 ps
T540 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.893102767 Aug 10 05:23:45 PM PDT 24 Aug 10 05:23:46 PM PDT 24 21360110 ps
T541 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1639952558 Aug 10 05:23:46 PM PDT 24 Aug 10 05:23:47 PM PDT 24 29974167 ps
T542 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3106337866 Aug 10 05:23:38 PM PDT 24 Aug 10 05:23:39 PM PDT 24 115261672 ps
T543 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3474020025 Aug 10 05:23:38 PM PDT 24 Aug 10 05:23:41 PM PDT 24 51474654 ps
T544 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1255882987 Aug 10 05:23:32 PM PDT 24 Aug 10 05:23:33 PM PDT 24 25020176 ps
T545 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2921418307 Aug 10 05:23:41 PM PDT 24 Aug 10 05:23:44 PM PDT 24 562732302 ps
T546 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4232363419 Aug 10 05:23:33 PM PDT 24 Aug 10 05:23:34 PM PDT 24 24101777 ps
T547 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1087815017 Aug 10 05:23:43 PM PDT 24 Aug 10 05:23:44 PM PDT 24 234612133 ps
T548 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3540213976 Aug 10 05:23:46 PM PDT 24 Aug 10 05:23:47 PM PDT 24 17225401 ps
T549 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3934914746 Aug 10 05:24:28 PM PDT 24 Aug 10 05:24:29 PM PDT 24 180168440 ps
T550 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2247748025 Aug 10 05:23:43 PM PDT 24 Aug 10 05:23:44 PM PDT 24 14158229 ps
T551 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2037450768 Aug 10 05:24:00 PM PDT 24 Aug 10 05:24:00 PM PDT 24 18354966 ps
T100 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2029276898 Aug 10 05:23:35 PM PDT 24 Aug 10 05:23:36 PM PDT 24 151614665 ps
T552 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2784981902 Aug 10 05:23:36 PM PDT 24 Aug 10 05:23:36 PM PDT 24 15269580 ps
T553 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2660720872 Aug 10 05:24:27 PM PDT 24 Aug 10 05:24:29 PM PDT 24 82302116 ps
T554 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1442945511 Aug 10 05:23:33 PM PDT 24 Aug 10 05:23:34 PM PDT 24 367569602 ps
T555 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.48887251 Aug 10 05:23:37 PM PDT 24 Aug 10 05:23:38 PM PDT 24 65783677 ps
T84 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1613995295 Aug 10 05:23:21 PM PDT 24 Aug 10 05:23:24 PM PDT 24 1380567601 ps
T556 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.51252468 Aug 10 05:23:35 PM PDT 24 Aug 10 05:23:37 PM PDT 24 38996482 ps
T557 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.329876733 Aug 10 05:23:38 PM PDT 24 Aug 10 05:23:39 PM PDT 24 13645854 ps
T558 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1610702385 Aug 10 05:23:34 PM PDT 24 Aug 10 05:23:35 PM PDT 24 15893817 ps
T559 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.224270058 Aug 10 05:23:44 PM PDT 24 Aug 10 05:23:44 PM PDT 24 38701189 ps
T560 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1371906189 Aug 10 05:23:34 PM PDT 24 Aug 10 05:23:34 PM PDT 24 36994261 ps
T85 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.474742088 Aug 10 05:23:41 PM PDT 24 Aug 10 05:23:42 PM PDT 24 25280534 ps
T561 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.4239831444 Aug 10 05:23:35 PM PDT 24 Aug 10 05:23:36 PM PDT 24 41037381 ps
T562 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2673179749 Aug 10 05:23:30 PM PDT 24 Aug 10 05:23:30 PM PDT 24 15413328 ps
T563 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1145510983 Aug 10 05:23:47 PM PDT 24 Aug 10 05:23:48 PM PDT 24 84681204 ps
T564 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.4065585285 Aug 10 05:23:41 PM PDT 24 Aug 10 05:23:43 PM PDT 24 251917992 ps
T565 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1938673786 Aug 10 05:23:34 PM PDT 24 Aug 10 05:23:35 PM PDT 24 36895248 ps
T86 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1825571183 Aug 10 05:23:37 PM PDT 24 Aug 10 05:23:38 PM PDT 24 36929796 ps
T566 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1054644028 Aug 10 05:23:43 PM PDT 24 Aug 10 05:23:43 PM PDT 24 28010772 ps
T567 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2745925316 Aug 10 05:23:41 PM PDT 24 Aug 10 05:23:42 PM PDT 24 770833923 ps
T568 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1917108088 Aug 10 05:23:46 PM PDT 24 Aug 10 05:23:54 PM PDT 24 187472152 ps
T569 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1891281694 Aug 10 05:23:42 PM PDT 24 Aug 10 05:23:43 PM PDT 24 96173098 ps
T570 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.277674956 Aug 10 05:23:40 PM PDT 24 Aug 10 05:23:41 PM PDT 24 86160058 ps
T87 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.649216643 Aug 10 05:23:34 PM PDT 24 Aug 10 05:23:34 PM PDT 24 68975807 ps
T571 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2225268770 Aug 10 05:23:37 PM PDT 24 Aug 10 05:23:38 PM PDT 24 13237998 ps
T572 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.244873444 Aug 10 05:23:45 PM PDT 24 Aug 10 05:23:46 PM PDT 24 69396284 ps
T573 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.170658104 Aug 10 05:23:34 PM PDT 24 Aug 10 05:23:35 PM PDT 24 58408478 ps
T574 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3034421608 Aug 10 05:23:44 PM PDT 24 Aug 10 05:23:45 PM PDT 24 29135037 ps
T575 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3534895617 Aug 10 05:23:42 PM PDT 24 Aug 10 05:23:43 PM PDT 24 59357892 ps
T576 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2127309080 Aug 10 05:23:35 PM PDT 24 Aug 10 05:23:36 PM PDT 24 88381755 ps
T577 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2849632294 Aug 10 05:23:31 PM PDT 24 Aug 10 05:23:32 PM PDT 24 119112116 ps
T578 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.764643901 Aug 10 05:23:43 PM PDT 24 Aug 10 05:23:44 PM PDT 24 36522051 ps
T88 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1138040787 Aug 10 05:23:40 PM PDT 24 Aug 10 05:23:43 PM PDT 24 5496785288 ps
T579 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1623481154 Aug 10 05:23:27 PM PDT 24 Aug 10 05:23:28 PM PDT 24 14958987 ps

Test location /workspace/coverage/default/0.rv_timer_stress_all.2040782519
Short name T1
Test name
Test status
Simulation time 423566771661 ps
CPU time 759.2 seconds
Started Aug 10 06:04:25 PM PDT 24
Finished Aug 10 06:17:04 PM PDT 24
Peak memory 191660 kb
Host smart-608fae17-6f2b-41a7-beac-428505c1d5a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040782519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2040782519
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.3704675760
Short name T15
Test name
Test status
Simulation time 56696423614 ps
CPU time 308.39 seconds
Started Aug 10 06:04:38 PM PDT 24
Finished Aug 10 06:09:46 PM PDT 24
Peak memory 206368 kb
Host smart-540c9ab7-8abd-4cc7-ab8a-9ba4ff162799
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704675760 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.3704675760
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3172615076
Short name T101
Test name
Test status
Simulation time 2187190357790 ps
CPU time 1518.09 seconds
Started Aug 10 06:05:56 PM PDT 24
Finished Aug 10 06:31:14 PM PDT 24
Peak memory 191656 kb
Host smart-683dedb7-e57b-4aa9-9cb5-c0528e1e8709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172615076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3172615076
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2091758194
Short name T31
Test name
Test status
Simulation time 296397729 ps
CPU time 1.15 seconds
Started Aug 10 05:23:32 PM PDT 24
Finished Aug 10 05:23:33 PM PDT 24
Peak memory 195236 kb
Host smart-d11319aa-c8b9-4069-9095-eadf22b11e41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091758194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2091758194
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3753980899
Short name T65
Test name
Test status
Simulation time 1013372320880 ps
CPU time 1789.27 seconds
Started Aug 10 06:04:39 PM PDT 24
Finished Aug 10 06:34:29 PM PDT 24
Peak memory 191624 kb
Host smart-4b927064-e8d8-4425-9a3f-f36ac0b6d0d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753980899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3753980899
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3358163985
Short name T138
Test name
Test status
Simulation time 483391108639 ps
CPU time 970.4 seconds
Started Aug 10 06:06:36 PM PDT 24
Finished Aug 10 06:22:47 PM PDT 24
Peak memory 191528 kb
Host smart-88c19b43-5c77-4c97-897d-1d3a78df19cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358163985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3358163985
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3897916827
Short name T34
Test name
Test status
Simulation time 13599618 ps
CPU time 0.58 seconds
Started Aug 10 05:23:47 PM PDT 24
Finished Aug 10 05:23:48 PM PDT 24
Peak memory 182956 kb
Host smart-9f471e00-a218-474c-8b1d-383297dff385
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897916827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3897916827
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1658604552
Short name T102
Test name
Test status
Simulation time 390072519031 ps
CPU time 627.18 seconds
Started Aug 10 06:05:48 PM PDT 24
Finished Aug 10 06:16:15 PM PDT 24
Peak memory 191656 kb
Host smart-d4679def-f3a0-46c8-be4b-6b453f037aaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658604552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1658604552
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2808567807
Short name T229
Test name
Test status
Simulation time 7944932083727 ps
CPU time 2353.28 seconds
Started Aug 10 06:05:02 PM PDT 24
Finished Aug 10 06:44:16 PM PDT 24
Peak memory 191636 kb
Host smart-24e7ccaa-a379-4861-98dc-a8a390824196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808567807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2808567807
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1836409987
Short name T126
Test name
Test status
Simulation time 560266922645 ps
CPU time 1841.46 seconds
Started Aug 10 06:05:49 PM PDT 24
Finished Aug 10 06:36:31 PM PDT 24
Peak memory 191660 kb
Host smart-727b8827-827e-4506-8df8-8c6ca9f5324a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836409987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1836409987
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.405410628
Short name T219
Test name
Test status
Simulation time 663492821312 ps
CPU time 737.57 seconds
Started Aug 10 06:05:29 PM PDT 24
Finished Aug 10 06:17:47 PM PDT 24
Peak memory 196448 kb
Host smart-3f4f9f85-3e4b-4c0c-8224-cfd6c0654f4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405410628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
405410628
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1633149477
Short name T151
Test name
Test status
Simulation time 2204037072678 ps
CPU time 1357.26 seconds
Started Aug 10 06:04:42 PM PDT 24
Finished Aug 10 06:27:20 PM PDT 24
Peak memory 191608 kb
Host smart-8a92f2aa-1a3d-4dde-a4d9-37ec6e6b7694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633149477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1633149477
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1374261395
Short name T258
Test name
Test status
Simulation time 1788308526534 ps
CPU time 1323.13 seconds
Started Aug 10 06:06:38 PM PDT 24
Finished Aug 10 06:28:41 PM PDT 24
Peak memory 196616 kb
Host smart-92475e13-b1ae-4eeb-9b85-9c5e8ec1079e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374261395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1374261395
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1137433683
Short name T263
Test name
Test status
Simulation time 2374946085745 ps
CPU time 1219.41 seconds
Started Aug 10 06:06:06 PM PDT 24
Finished Aug 10 06:26:26 PM PDT 24
Peak memory 191644 kb
Host smart-c65c794e-cf38-4312-bd0a-03fa8ac1e267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137433683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1137433683
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2282544924
Short name T19
Test name
Test status
Simulation time 221678373 ps
CPU time 0.92 seconds
Started Aug 10 06:04:25 PM PDT 24
Finished Aug 10 06:04:26 PM PDT 24
Peak memory 215136 kb
Host smart-4325b993-c28d-4790-94fb-0abb0809693a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282544924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2282544924
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2851923201
Short name T204
Test name
Test status
Simulation time 1373702173007 ps
CPU time 864.23 seconds
Started Aug 10 06:04:35 PM PDT 24
Finished Aug 10 06:19:00 PM PDT 24
Peak memory 196864 kb
Host smart-15a957e3-adc9-4a5a-a616-19acb75f1ace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851923201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2851923201
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/147.rv_timer_random.1905227670
Short name T108
Test name
Test status
Simulation time 365043285771 ps
CPU time 1054.59 seconds
Started Aug 10 06:07:44 PM PDT 24
Finished Aug 10 06:25:19 PM PDT 24
Peak memory 191684 kb
Host smart-4dec8ec2-11c3-4ae1-b66c-a995364dd114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905227670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1905227670
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3833369563
Short name T221
Test name
Test status
Simulation time 465632157857 ps
CPU time 1320.3 seconds
Started Aug 10 06:04:51 PM PDT 24
Finished Aug 10 06:26:52 PM PDT 24
Peak memory 191684 kb
Host smart-b2a43c7b-9f44-449c-911b-fd5a88a4f9d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833369563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3833369563
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.405583899
Short name T141
Test name
Test status
Simulation time 513890941305 ps
CPU time 750.04 seconds
Started Aug 10 06:05:03 PM PDT 24
Finished Aug 10 06:17:34 PM PDT 24
Peak memory 196008 kb
Host smart-1ca8cbaa-f78c-4fdb-be73-f60516a81d96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405583899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
405583899
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.859783959
Short name T125
Test name
Test status
Simulation time 2941172478138 ps
CPU time 904.03 seconds
Started Aug 10 06:07:18 PM PDT 24
Finished Aug 10 06:22:23 PM PDT 24
Peak memory 191676 kb
Host smart-37a74268-9228-495f-be59-edc91cd726a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859783959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.859783959
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1448974749
Short name T196
Test name
Test status
Simulation time 550820416592 ps
CPU time 823.7 seconds
Started Aug 10 06:06:14 PM PDT 24
Finished Aug 10 06:19:58 PM PDT 24
Peak memory 195848 kb
Host smart-933d0d4f-12bc-439c-95c4-a6323dd6adaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448974749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1448974749
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2154319865
Short name T123
Test name
Test status
Simulation time 3269189595000 ps
CPU time 2462.79 seconds
Started Aug 10 06:06:20 PM PDT 24
Finished Aug 10 06:47:23 PM PDT 24
Peak memory 191672 kb
Host smart-7255896f-d23c-4bae-89a1-1172b3503c26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154319865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2154319865
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.97539666
Short name T37
Test name
Test status
Simulation time 1124141844117 ps
CPU time 1251.59 seconds
Started Aug 10 06:04:35 PM PDT 24
Finished Aug 10 06:25:27 PM PDT 24
Peak memory 191664 kb
Host smart-af9ba4d3-33dc-4683-82f7-82cf9017156a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97539666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.97539666
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.255133150
Short name T253
Test name
Test status
Simulation time 1571404458220 ps
CPU time 832.79 seconds
Started Aug 10 06:06:32 PM PDT 24
Finished Aug 10 06:20:26 PM PDT 24
Peak memory 196328 kb
Host smart-9e2f459f-ab47-4741-b6fa-6d8267dc12f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255133150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
255133150
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/59.rv_timer_random.867436432
Short name T175
Test name
Test status
Simulation time 160900113447 ps
CPU time 685.35 seconds
Started Aug 10 06:06:55 PM PDT 24
Finished Aug 10 06:18:21 PM PDT 24
Peak memory 191680 kb
Host smart-bea31e4a-3be3-492b-b86b-0a7a50592023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867436432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.867436432
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.658328734
Short name T209
Test name
Test status
Simulation time 1251414984561 ps
CPU time 1123.87 seconds
Started Aug 10 06:05:14 PM PDT 24
Finished Aug 10 06:23:58 PM PDT 24
Peak memory 191672 kb
Host smart-76c2f1b3-1bae-4a99-93ec-bfac4be2558b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658328734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.658328734
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.679808981
Short name T140
Test name
Test status
Simulation time 2658396812964 ps
CPU time 1276.22 seconds
Started Aug 10 06:04:36 PM PDT 24
Finished Aug 10 06:25:52 PM PDT 24
Peak memory 191644 kb
Host smart-8bafa5f1-82ac-4298-b439-7aeb7b0480bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679808981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.679808981
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.4062438955
Short name T149
Test name
Test status
Simulation time 94237839922 ps
CPU time 540.67 seconds
Started Aug 10 06:07:18 PM PDT 24
Finished Aug 10 06:16:19 PM PDT 24
Peak memory 191676 kb
Host smart-fe388f98-6a0c-498c-9eb7-51dd1c4af6a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062438955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.4062438955
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.62520004
Short name T223
Test name
Test status
Simulation time 149058812221 ps
CPU time 392.28 seconds
Started Aug 10 06:07:29 PM PDT 24
Finished Aug 10 06:14:01 PM PDT 24
Peak memory 191700 kb
Host smart-a5b73863-00c5-481a-b4ca-d88d9a2d1276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62520004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.62520004
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.600125756
Short name T332
Test name
Test status
Simulation time 1058951144045 ps
CPU time 1969.4 seconds
Started Aug 10 06:04:28 PM PDT 24
Finished Aug 10 06:37:18 PM PDT 24
Peak memory 191660 kb
Host smart-54c3d799-061e-462b-a03c-49f0003b8f7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600125756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.600125756
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.4023664167
Short name T143
Test name
Test status
Simulation time 151278338729 ps
CPU time 633.98 seconds
Started Aug 10 06:05:04 PM PDT 24
Finished Aug 10 06:15:38 PM PDT 24
Peak memory 191624 kb
Host smart-bdc008ad-5733-4d2c-951f-2ba7c1600106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023664167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.4023664167
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3598489271
Short name T252
Test name
Test status
Simulation time 956618715108 ps
CPU time 549.23 seconds
Started Aug 10 06:04:27 PM PDT 24
Finished Aug 10 06:13:36 PM PDT 24
Peak memory 183472 kb
Host smart-b4a97787-be87-4bc6-a2c5-eb80d0f88473
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598489271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3598489271
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/98.rv_timer_random.1975555129
Short name T194
Test name
Test status
Simulation time 203949448635 ps
CPU time 271.88 seconds
Started Aug 10 06:07:20 PM PDT 24
Finished Aug 10 06:11:52 PM PDT 24
Peak memory 191684 kb
Host smart-faee8bb7-267c-4704-8938-9acb84c5b0ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975555129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1975555129
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2163981709
Short name T308
Test name
Test status
Simulation time 1322130598167 ps
CPU time 849.25 seconds
Started Aug 10 06:07:28 PM PDT 24
Finished Aug 10 06:21:38 PM PDT 24
Peak memory 191672 kb
Host smart-8dc1089c-9b22-4a12-9f90-2bc63c188b26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163981709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2163981709
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.2346073927
Short name T201
Test name
Test status
Simulation time 302090857281 ps
CPU time 541.92 seconds
Started Aug 10 06:07:26 PM PDT 24
Finished Aug 10 06:16:29 PM PDT 24
Peak memory 191616 kb
Host smart-acad97d4-2369-4bec-a4c3-eb62873a365a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346073927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2346073927
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3374738683
Short name T133
Test name
Test status
Simulation time 396397088521 ps
CPU time 698.9 seconds
Started Aug 10 06:07:34 PM PDT 24
Finished Aug 10 06:19:13 PM PDT 24
Peak memory 191644 kb
Host smart-2a3af25e-829d-4fb2-a364-4a16af293d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374738683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3374738683
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1399761281
Short name T321
Test name
Test status
Simulation time 204161897516 ps
CPU time 1165.18 seconds
Started Aug 10 06:07:37 PM PDT 24
Finished Aug 10 06:27:02 PM PDT 24
Peak memory 191544 kb
Host smart-092cc1f1-d3d5-4376-8aa9-0627f8cc9df7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399761281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1399761281
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.3248265662
Short name T124
Test name
Test status
Simulation time 397269635332 ps
CPU time 2040.11 seconds
Started Aug 10 06:04:43 PM PDT 24
Finished Aug 10 06:38:44 PM PDT 24
Peak memory 191644 kb
Host smart-7b6ea79d-ab7a-4ef4-a68c-3862b24893df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248265662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3248265662
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1954720952
Short name T161
Test name
Test status
Simulation time 242581089688 ps
CPU time 219.56 seconds
Started Aug 10 06:07:09 PM PDT 24
Finished Aug 10 06:10:49 PM PDT 24
Peak memory 191680 kb
Host smart-baa5c1d9-6826-47bc-a56a-aef0dd9125be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954720952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1954720952
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1810378012
Short name T260
Test name
Test status
Simulation time 675935705876 ps
CPU time 982.08 seconds
Started Aug 10 06:07:25 PM PDT 24
Finished Aug 10 06:23:48 PM PDT 24
Peak memory 191468 kb
Host smart-7b78fdbf-7fe3-4216-a026-2e4e3fa39365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810378012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1810378012
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2783265321
Short name T178
Test name
Test status
Simulation time 115094930252 ps
CPU time 639.33 seconds
Started Aug 10 06:07:34 PM PDT 24
Finished Aug 10 06:18:13 PM PDT 24
Peak memory 191620 kb
Host smart-1c0ec2ec-936c-48cb-800d-b3318506fb0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783265321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2783265321
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2756775521
Short name T425
Test name
Test status
Simulation time 92744763390 ps
CPU time 166.05 seconds
Started Aug 10 06:07:57 PM PDT 24
Finished Aug 10 06:10:43 PM PDT 24
Peak memory 191676 kb
Host smart-09e6c3c2-5103-4a91-97f4-731d156dd8e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756775521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2756775521
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.937572436
Short name T237
Test name
Test status
Simulation time 348398996329 ps
CPU time 244.74 seconds
Started Aug 10 06:07:56 PM PDT 24
Finished Aug 10 06:12:00 PM PDT 24
Peak memory 191664 kb
Host smart-05041378-6367-4dd9-8f0a-4c307216bf15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937572436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.937572436
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.1547997349
Short name T139
Test name
Test status
Simulation time 777264097217 ps
CPU time 652.71 seconds
Started Aug 10 06:08:04 PM PDT 24
Finished Aug 10 06:18:57 PM PDT 24
Peak memory 191676 kb
Host smart-f0155bb7-2b19-4c6d-a064-653679b7b2e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547997349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1547997349
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2480136355
Short name T190
Test name
Test status
Simulation time 155977257047 ps
CPU time 1185.2 seconds
Started Aug 10 06:08:06 PM PDT 24
Finished Aug 10 06:27:51 PM PDT 24
Peak memory 191636 kb
Host smart-007690b0-dfb1-4776-aee7-21411f0aad59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480136355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2480136355
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.993450401
Short name T267
Test name
Test status
Simulation time 113865681897 ps
CPU time 352.8 seconds
Started Aug 10 06:08:03 PM PDT 24
Finished Aug 10 06:13:56 PM PDT 24
Peak memory 191608 kb
Host smart-552a513f-9c5b-4f66-802b-8324cc891258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993450401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.993450401
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.210788700
Short name T14
Test name
Test status
Simulation time 1002473130037 ps
CPU time 313.74 seconds
Started Aug 10 06:05:37 PM PDT 24
Finished Aug 10 06:10:51 PM PDT 24
Peak memory 183352 kb
Host smart-131d3bf9-0829-419b-8095-6f9fb90be731
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210788700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.210788700
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_random.217606406
Short name T301
Test name
Test status
Simulation time 87291692752 ps
CPU time 328.77 seconds
Started Aug 10 06:04:25 PM PDT 24
Finished Aug 10 06:09:54 PM PDT 24
Peak memory 195080 kb
Host smart-c31568af-75d2-4a29-9185-5a4e7bb8dc8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217606406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.217606406
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3630520598
Short name T266
Test name
Test status
Simulation time 624389687922 ps
CPU time 1408.86 seconds
Started Aug 10 06:07:19 PM PDT 24
Finished Aug 10 06:30:48 PM PDT 24
Peak memory 191612 kb
Host smart-6ab145f6-c114-4279-b760-59498f0ac0d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630520598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3630520598
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.4267741267
Short name T357
Test name
Test status
Simulation time 423547250194 ps
CPU time 448.04 seconds
Started Aug 10 06:07:27 PM PDT 24
Finished Aug 10 06:14:55 PM PDT 24
Peak memory 191748 kb
Host smart-121ee56b-4711-43d5-8990-0a4ce06bcf4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267741267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4267741267
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3676466327
Short name T354
Test name
Test status
Simulation time 176391105472 ps
CPU time 206.31 seconds
Started Aug 10 06:08:11 PM PDT 24
Finished Aug 10 06:11:38 PM PDT 24
Peak memory 191576 kb
Host smart-60e3f699-5840-4167-b0c3-6614d094f631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676466327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3676466327
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1163922089
Short name T107
Test name
Test status
Simulation time 366914844095 ps
CPU time 264.71 seconds
Started Aug 10 06:08:14 PM PDT 24
Finished Aug 10 06:12:38 PM PDT 24
Peak memory 191708 kb
Host smart-a9a1bc5b-78ad-4fd1-8d16-db46a0ba3d2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163922089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1163922089
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1989530436
Short name T103
Test name
Test status
Simulation time 622657982978 ps
CPU time 280.76 seconds
Started Aug 10 06:05:48 PM PDT 24
Finished Aug 10 06:10:29 PM PDT 24
Peak memory 191652 kb
Host smart-32c1ff86-65ee-4ce7-acc3-53daafec0312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989530436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1989530436
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3667399303
Short name T273
Test name
Test status
Simulation time 43647088803 ps
CPU time 37.2 seconds
Started Aug 10 06:04:35 PM PDT 24
Finished Aug 10 06:05:13 PM PDT 24
Peak memory 183492 kb
Host smart-988bcfa1-c21a-4d8c-9d3f-72c71e54ba10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667399303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3667399303
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/51.rv_timer_random.1809992480
Short name T286
Test name
Test status
Simulation time 340256946893 ps
CPU time 163.22 seconds
Started Aug 10 06:06:55 PM PDT 24
Finished Aug 10 06:09:39 PM PDT 24
Peak memory 191672 kb
Host smart-8449d08d-56cd-42c1-964b-47c82db787e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809992480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1809992480
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.517806695
Short name T45
Test name
Test status
Simulation time 975380065822 ps
CPU time 501.94 seconds
Started Aug 10 06:04:39 PM PDT 24
Finished Aug 10 06:13:01 PM PDT 24
Peak memory 183232 kb
Host smart-277195fe-948d-4de5-b682-f96f20a5270c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517806695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.517806695
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/71.rv_timer_random.2280211711
Short name T9
Test name
Test status
Simulation time 103939967961 ps
CPU time 153.75 seconds
Started Aug 10 06:07:08 PM PDT 24
Finished Aug 10 06:09:42 PM PDT 24
Peak memory 191680 kb
Host smart-22a5a13d-5af4-4584-b1e8-5feb0648c800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280211711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2280211711
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1145510983
Short name T563
Test name
Test status
Simulation time 84681204 ps
CPU time 0.81 seconds
Started Aug 10 05:23:47 PM PDT 24
Finished Aug 10 05:23:48 PM PDT 24
Peak memory 193592 kb
Host smart-36b185f1-f414-4bd5-b2e1-f14b82318277
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145510983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1145510983
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3798937829
Short name T272
Test name
Test status
Simulation time 892161130267 ps
CPU time 662.77 seconds
Started Aug 10 06:04:20 PM PDT 24
Finished Aug 10 06:15:23 PM PDT 24
Peak memory 183472 kb
Host smart-9d7ec4f0-c613-44c0-a8db-c08af1cf76a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798937829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3798937829
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2989648094
Short name T116
Test name
Test status
Simulation time 1310730774660 ps
CPU time 579.41 seconds
Started Aug 10 06:04:26 PM PDT 24
Finished Aug 10 06:14:06 PM PDT 24
Peak memory 191604 kb
Host smart-f8aff987-26e5-4fa8-adb7-efb1d7908e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989648094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2989648094
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2738394843
Short name T322
Test name
Test status
Simulation time 135870598987 ps
CPU time 211.32 seconds
Started Aug 10 06:04:36 PM PDT 24
Finished Aug 10 06:08:07 PM PDT 24
Peak memory 183412 kb
Host smart-fa9d7b6e-1989-4668-8ac1-21f617a27bd8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738394843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2738394843
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.118548761
Short name T104
Test name
Test status
Simulation time 1463831094258 ps
CPU time 714.12 seconds
Started Aug 10 06:04:42 PM PDT 24
Finished Aug 10 06:16:36 PM PDT 24
Peak memory 183464 kb
Host smart-50757610-a23d-4218-851d-6e0d3ebcc8a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118548761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.118548761
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/114.rv_timer_random.2699408298
Short name T271
Test name
Test status
Simulation time 231458141172 ps
CPU time 201.64 seconds
Started Aug 10 06:07:28 PM PDT 24
Finished Aug 10 06:10:50 PM PDT 24
Peak memory 191672 kb
Host smart-f51ba340-d1f9-4f17-b9c4-1ceea90e937d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699408298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2699408298
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3141564389
Short name T294
Test name
Test status
Simulation time 187785381348 ps
CPU time 505.62 seconds
Started Aug 10 06:07:25 PM PDT 24
Finished Aug 10 06:15:51 PM PDT 24
Peak memory 193956 kb
Host smart-3c9cd9e0-f7a3-41f5-8ac2-0ac49e6bc9e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141564389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3141564389
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.426099085
Short name T52
Test name
Test status
Simulation time 586676453401 ps
CPU time 1843.41 seconds
Started Aug 10 06:07:51 PM PDT 24
Finished Aug 10 06:38:34 PM PDT 24
Peak memory 191460 kb
Host smart-2738b776-56f1-4271-acf7-b5b5d911b1d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426099085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.426099085
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2684993403
Short name T156
Test name
Test status
Simulation time 29595747844 ps
CPU time 21.45 seconds
Started Aug 10 06:04:51 PM PDT 24
Finished Aug 10 06:05:13 PM PDT 24
Peak memory 192496 kb
Host smart-697e4923-2e2a-4968-801e-82297f4f1bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684993403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2684993403
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2818685524
Short name T212
Test name
Test status
Simulation time 214354575188 ps
CPU time 357.43 seconds
Started Aug 10 06:05:04 PM PDT 24
Finished Aug 10 06:11:01 PM PDT 24
Peak memory 183448 kb
Host smart-6e8e3049-59bf-4bf5-8dc0-c60961074f79
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818685524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2818685524
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/77.rv_timer_random.1837759536
Short name T249
Test name
Test status
Simulation time 164981001749 ps
CPU time 364.07 seconds
Started Aug 10 06:07:00 PM PDT 24
Finished Aug 10 06:13:04 PM PDT 24
Peak memory 191648 kb
Host smart-888f4331-5757-42e2-b91a-c971ec91fc54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837759536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1837759536
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.696673529
Short name T159
Test name
Test status
Simulation time 1348477696454 ps
CPU time 498.99 seconds
Started Aug 10 06:04:25 PM PDT 24
Finished Aug 10 06:12:44 PM PDT 24
Peak memory 183496 kb
Host smart-7411794c-2540-4ba0-b726-05010cc5d9b4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696673529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.696673529
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_random.293342694
Short name T142
Test name
Test status
Simulation time 2339730207764 ps
CPU time 441.79 seconds
Started Aug 10 06:04:37 PM PDT 24
Finished Aug 10 06:11:59 PM PDT 24
Peak memory 191212 kb
Host smart-193defcb-900d-4daf-9611-d1c1d0815643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293342694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.293342694
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3905817963
Short name T173
Test name
Test status
Simulation time 263751299462 ps
CPU time 174.98 seconds
Started Aug 10 06:07:17 PM PDT 24
Finished Aug 10 06:10:12 PM PDT 24
Peak memory 191608 kb
Host smart-a1752541-6603-4b58-b41d-e12a699b15b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905817963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3905817963
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2764002602
Short name T434
Test name
Test status
Simulation time 39192646817 ps
CPU time 64.57 seconds
Started Aug 10 06:07:19 PM PDT 24
Finished Aug 10 06:08:23 PM PDT 24
Peak memory 183464 kb
Host smart-55877dbb-bbbd-4ab7-9d26-cdec0c98f2fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764002602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2764002602
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3715287786
Short name T250
Test name
Test status
Simulation time 151300869464 ps
CPU time 1199.87 seconds
Started Aug 10 06:07:18 PM PDT 24
Finished Aug 10 06:27:18 PM PDT 24
Peak memory 191604 kb
Host smart-d026c0ae-7ba7-445c-ba4b-2cdb66d3e812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715287786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3715287786
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.247445923
Short name T310
Test name
Test status
Simulation time 145929660263 ps
CPU time 72.51 seconds
Started Aug 10 06:07:20 PM PDT 24
Finished Aug 10 06:08:33 PM PDT 24
Peak memory 183336 kb
Host smart-17e3323f-8970-4ce5-aa50-dffd069b77b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247445923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.247445923
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2629297984
Short name T319
Test name
Test status
Simulation time 7078840905344 ps
CPU time 1535.54 seconds
Started Aug 10 06:04:45 PM PDT 24
Finished Aug 10 06:30:21 PM PDT 24
Peak memory 191640 kb
Host smart-02174e79-8a98-4bc0-a012-5f9db12d42c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629297984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2629297984
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/113.rv_timer_random.4183074431
Short name T349
Test name
Test status
Simulation time 52805588025 ps
CPU time 1322.21 seconds
Started Aug 10 06:07:26 PM PDT 24
Finished Aug 10 06:29:28 PM PDT 24
Peak memory 191696 kb
Host smart-365425df-23de-45bf-83bb-d188b4e5e8f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183074431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.4183074431
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2191020968
Short name T109
Test name
Test status
Simulation time 152768062361 ps
CPU time 695.33 seconds
Started Aug 10 06:07:29 PM PDT 24
Finished Aug 10 06:19:05 PM PDT 24
Peak memory 191676 kb
Host smart-a9d82e86-eb24-46c2-98f3-a724928fad83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191020968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2191020968
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1383354938
Short name T189
Test name
Test status
Simulation time 301111566338 ps
CPU time 147.48 seconds
Started Aug 10 06:04:42 PM PDT 24
Finished Aug 10 06:07:09 PM PDT 24
Peak memory 183396 kb
Host smart-6c54f9a6-02b3-479a-ad38-fe3e2f68089c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383354938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1383354938
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/129.rv_timer_random.3138455186
Short name T220
Test name
Test status
Simulation time 1137267721123 ps
CPU time 545.84 seconds
Started Aug 10 06:07:34 PM PDT 24
Finished Aug 10 06:16:40 PM PDT 24
Peak memory 191672 kb
Host smart-74344fdc-4c70-4f89-9e3a-74df9f84e3d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138455186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3138455186
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3475929601
Short name T184
Test name
Test status
Simulation time 55377895259 ps
CPU time 288.83 seconds
Started Aug 10 06:04:43 PM PDT 24
Finished Aug 10 06:09:32 PM PDT 24
Peak memory 206216 kb
Host smart-c165f899-5320-4a2c-9be4-8e35d2e7a45e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475929601 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.3475929601
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.617233519
Short name T147
Test name
Test status
Simulation time 235891315211 ps
CPU time 210.73 seconds
Started Aug 10 06:07:35 PM PDT 24
Finished Aug 10 06:11:06 PM PDT 24
Peak memory 191620 kb
Host smart-2d97cf5e-c7db-465b-96df-62361d78ae74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617233519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.617233519
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.4070862753
Short name T205
Test name
Test status
Simulation time 1025987528703 ps
CPU time 380.23 seconds
Started Aug 10 06:07:34 PM PDT 24
Finished Aug 10 06:13:54 PM PDT 24
Peak memory 191624 kb
Host smart-e7f81d1e-be70-45d0-9ae6-c8861a4afb55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070862753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4070862753
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1465652047
Short name T240
Test name
Test status
Simulation time 116643888229 ps
CPU time 2127.57 seconds
Started Aug 10 06:07:35 PM PDT 24
Finished Aug 10 06:43:02 PM PDT 24
Peak memory 191664 kb
Host smart-486192f3-00f7-41ce-a72d-34a456cc7431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465652047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1465652047
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2121162043
Short name T293
Test name
Test status
Simulation time 232827673395 ps
CPU time 605.88 seconds
Started Aug 10 06:07:36 PM PDT 24
Finished Aug 10 06:17:42 PM PDT 24
Peak memory 191676 kb
Host smart-da84d9d2-f865-4517-b5b8-18883e9e961d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121162043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2121162043
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3849210146
Short name T278
Test name
Test status
Simulation time 253368350279 ps
CPU time 414.57 seconds
Started Aug 10 06:04:52 PM PDT 24
Finished Aug 10 06:11:47 PM PDT 24
Peak memory 195148 kb
Host smart-10cf934b-6a4d-4055-9f72-7ad0d71ddc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849210146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3849210146
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/143.rv_timer_random.3133867447
Short name T68
Test name
Test status
Simulation time 288115834017 ps
CPU time 181.14 seconds
Started Aug 10 06:07:43 PM PDT 24
Finished Aug 10 06:10:44 PM PDT 24
Peak memory 191600 kb
Host smart-a690ab23-a47b-4f05-a0a7-35345d3f76c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133867447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3133867447
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.127044122
Short name T10
Test name
Test status
Simulation time 79366085033 ps
CPU time 488.94 seconds
Started Aug 10 06:07:42 PM PDT 24
Finished Aug 10 06:15:51 PM PDT 24
Peak memory 191716 kb
Host smart-455be5eb-252c-470b-9741-d6de10773a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127044122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.127044122
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2440699732
Short name T144
Test name
Test status
Simulation time 59552372400 ps
CPU time 91.07 seconds
Started Aug 10 06:07:49 PM PDT 24
Finished Aug 10 06:09:20 PM PDT 24
Peak memory 191668 kb
Host smart-56e7ac38-9cfe-49ab-a0c6-e326bb0be900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440699732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2440699732
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.465262665
Short name T119
Test name
Test status
Simulation time 224434434358 ps
CPU time 212.42 seconds
Started Aug 10 06:08:04 PM PDT 24
Finished Aug 10 06:11:37 PM PDT 24
Peak memory 191832 kb
Host smart-0a92d4db-1487-4fe6-9301-6d982bfbecc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465262665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.465262665
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.943905369
Short name T312
Test name
Test status
Simulation time 1286943672973 ps
CPU time 501.48 seconds
Started Aug 10 06:05:15 PM PDT 24
Finished Aug 10 06:13:37 PM PDT 24
Peak memory 183444 kb
Host smart-13d3253a-179d-4737-a9e9-7587d8acf858
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943905369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.943905369
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.2129692156
Short name T268
Test name
Test status
Simulation time 88318635064 ps
CPU time 330.58 seconds
Started Aug 10 06:05:48 PM PDT 24
Finished Aug 10 06:11:19 PM PDT 24
Peak memory 183444 kb
Host smart-970bd83f-2aa8-4cb5-982d-5e27cf06c622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129692156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2129692156
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3890990397
Short name T120
Test name
Test status
Simulation time 565352872220 ps
CPU time 750.02 seconds
Started Aug 10 06:05:56 PM PDT 24
Finished Aug 10 06:18:27 PM PDT 24
Peak memory 195824 kb
Host smart-aeae9a88-fd89-4952-8250-83e55ca309a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890990397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3890990397
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3266276820
Short name T200
Test name
Test status
Simulation time 331309187383 ps
CPU time 1100.38 seconds
Started Aug 10 06:06:05 PM PDT 24
Finished Aug 10 06:24:25 PM PDT 24
Peak memory 191652 kb
Host smart-8ddf0555-290a-4b11-b866-d3a3529df8a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266276820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3266276820
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.30966368
Short name T218
Test name
Test status
Simulation time 4222678162775 ps
CPU time 1080.81 seconds
Started Aug 10 06:06:23 PM PDT 24
Finished Aug 10 06:24:24 PM PDT 24
Peak memory 196052 kb
Host smart-f90668dc-95a4-4ae7-ab33-7a74f580fd7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30966368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.30966368
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/52.rv_timer_random.4007281178
Short name T316
Test name
Test status
Simulation time 65677154018 ps
CPU time 117.41 seconds
Started Aug 10 06:06:44 PM PDT 24
Finished Aug 10 06:08:42 PM PDT 24
Peak memory 191664 kb
Host smart-c667c4de-d84e-4c7f-b09f-5954ecca139f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007281178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.4007281178
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1494381460
Short name T217
Test name
Test status
Simulation time 259107329732 ps
CPU time 208.7 seconds
Started Aug 10 06:06:45 PM PDT 24
Finished Aug 10 06:10:14 PM PDT 24
Peak memory 191636 kb
Host smart-a919f6dd-acba-49d6-975f-a594b3eddc0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494381460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1494381460
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.764541818
Short name T166
Test name
Test status
Simulation time 162893575824 ps
CPU time 807.38 seconds
Started Aug 10 06:07:00 PM PDT 24
Finished Aug 10 06:20:27 PM PDT 24
Peak memory 194692 kb
Host smart-08307d02-47c8-4f8d-a758-2502b069268e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764541818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.764541818
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2225177809
Short name T213
Test name
Test status
Simulation time 398718676965 ps
CPU time 554.36 seconds
Started Aug 10 06:07:00 PM PDT 24
Finished Aug 10 06:16:15 PM PDT 24
Peak memory 194048 kb
Host smart-439ad36a-bf6d-4e7e-b57c-2fc479ba3473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225177809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2225177809
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3637692743
Short name T148
Test name
Test status
Simulation time 155431122706 ps
CPU time 55.16 seconds
Started Aug 10 06:04:35 PM PDT 24
Finished Aug 10 06:05:30 PM PDT 24
Peak memory 191824 kb
Host smart-e76320c6-97cc-4d6d-8d50-c014d2260f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637692743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3637692743
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1591230897
Short name T78
Test name
Test status
Simulation time 17306183 ps
CPU time 0.72 seconds
Started Aug 10 05:23:25 PM PDT 24
Finished Aug 10 05:23:26 PM PDT 24
Peak memory 192740 kb
Host smart-7c730cf0-ec77-48d7-a250-92639c909301
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591230897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1591230897
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1613995295
Short name T84
Test name
Test status
Simulation time 1380567601 ps
CPU time 2.76 seconds
Started Aug 10 05:23:21 PM PDT 24
Finished Aug 10 05:23:24 PM PDT 24
Peak memory 183124 kb
Host smart-11e6412b-7dac-472e-b46d-55a1db708373
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613995295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1613995295
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2166741429
Short name T456
Test name
Test status
Simulation time 13227411 ps
CPU time 0.54 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:35 PM PDT 24
Peak memory 182308 kb
Host smart-1a0d8a30-49dd-4d0a-8099-b059be82361b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166741429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2166741429
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.997106522
Short name T63
Test name
Test status
Simulation time 19881437 ps
CPU time 0.62 seconds
Started Aug 10 05:23:25 PM PDT 24
Finished Aug 10 05:23:26 PM PDT 24
Peak memory 192996 kb
Host smart-a017f7d2-e5d8-4d62-bf86-b1c1d510ea55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997106522 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.997106522
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.791901851
Short name T79
Test name
Test status
Simulation time 37095898 ps
CPU time 0.54 seconds
Started Aug 10 05:23:39 PM PDT 24
Finished Aug 10 05:23:40 PM PDT 24
Peak memory 182564 kb
Host smart-624929f8-66fb-47e0-9f05-c7d99bab14d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791901851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.791901851
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.185231817
Short name T531
Test name
Test status
Simulation time 43356945 ps
CPU time 0.53 seconds
Started Aug 10 05:23:30 PM PDT 24
Finished Aug 10 05:23:30 PM PDT 24
Peak memory 182164 kb
Host smart-d1509542-c1b6-4c21-8ab0-08f4e2215dc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185231817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.185231817
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3877689923
Short name T93
Test name
Test status
Simulation time 28400133 ps
CPU time 0.73 seconds
Started Aug 10 05:23:36 PM PDT 24
Finished Aug 10 05:23:37 PM PDT 24
Peak memory 191792 kb
Host smart-a803e2f9-46ca-416b-a6cd-593226c7c7af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877689923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3877689923
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3934914746
Short name T549
Test name
Test status
Simulation time 180168440 ps
CPU time 0.96 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:29 PM PDT 24
Peak memory 196616 kb
Host smart-35e48938-3b2f-414e-b2d2-ed6924cb1bda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934914746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3934914746
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2029276898
Short name T100
Test name
Test status
Simulation time 151614665 ps
CPU time 1.08 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 183228 kb
Host smart-69bd5928-602f-43f5-9b82-b639ab46aebf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029276898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2029276898
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1156871911
Short name T82
Test name
Test status
Simulation time 148108568 ps
CPU time 0.88 seconds
Started Aug 10 05:23:30 PM PDT 24
Finished Aug 10 05:23:31 PM PDT 24
Peak memory 182844 kb
Host smart-7d0a76bf-6ecd-4425-ae1b-3d5194d71da7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156871911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1156871911
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.51252468
Short name T556
Test name
Test status
Simulation time 38996482 ps
CPU time 1.51 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:37 PM PDT 24
Peak memory 191316 kb
Host smart-66a68c36-a13d-4bcd-8b53-8da937fd1c71
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51252468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_ba
sh.51252468
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.19141320
Short name T80
Test name
Test status
Simulation time 21747192 ps
CPU time 0.56 seconds
Started Aug 10 05:23:38 PM PDT 24
Finished Aug 10 05:23:39 PM PDT 24
Peak memory 182436 kb
Host smart-ba0f7286-0616-4eae-8622-7e4dc49d715e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19141320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_res
et.19141320
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3928834231
Short name T459
Test name
Test status
Simulation time 124942261 ps
CPU time 0.9 seconds
Started Aug 10 05:23:40 PM PDT 24
Finished Aug 10 05:23:41 PM PDT 24
Peak memory 197540 kb
Host smart-d13f3f2f-0776-4602-8c8c-d1cf3bc5df49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928834231 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3928834231
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.503309659
Short name T484
Test name
Test status
Simulation time 81624355 ps
CPU time 0.55 seconds
Started Aug 10 05:23:37 PM PDT 24
Finished Aug 10 05:23:38 PM PDT 24
Peak memory 182896 kb
Host smart-30722063-22f2-4163-8970-08012c5158c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503309659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.503309659
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4245622516
Short name T479
Test name
Test status
Simulation time 21412562 ps
CPU time 0.57 seconds
Started Aug 10 05:23:36 PM PDT 24
Finished Aug 10 05:23:37 PM PDT 24
Peak memory 182760 kb
Host smart-1aba45c1-ac0a-4418-937e-1e6c9ef464fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245622516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.4245622516
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1054644028
Short name T566
Test name
Test status
Simulation time 28010772 ps
CPU time 0.66 seconds
Started Aug 10 05:23:43 PM PDT 24
Finished Aug 10 05:23:43 PM PDT 24
Peak memory 191852 kb
Host smart-a1df78b6-d665-40a8-b71f-e65485da7bb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054644028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1054644028
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1120393622
Short name T62
Test name
Test status
Simulation time 254696007 ps
CPU time 1.45 seconds
Started Aug 10 05:23:36 PM PDT 24
Finished Aug 10 05:23:38 PM PDT 24
Peak memory 197604 kb
Host smart-f73233d6-5c1b-42f7-87ef-4b4b9f581d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120393622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1120393622
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1326656246
Short name T33
Test name
Test status
Simulation time 97430556 ps
CPU time 1.1 seconds
Started Aug 10 05:23:33 PM PDT 24
Finished Aug 10 05:23:34 PM PDT 24
Peak memory 195128 kb
Host smart-8bd2b223-9015-4092-a49a-5dd750469a4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326656246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1326656246
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3065042410
Short name T514
Test name
Test status
Simulation time 70043779 ps
CPU time 1.03 seconds
Started Aug 10 05:23:38 PM PDT 24
Finished Aug 10 05:23:39 PM PDT 24
Peak memory 197284 kb
Host smart-45b997d8-e61d-4ca9-a343-4bdf3ec53612
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065042410 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3065042410
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1930558261
Short name T513
Test name
Test status
Simulation time 12966632 ps
CPU time 0.55 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 181860 kb
Host smart-6772fec0-6f42-4a36-8920-1742be077a3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930558261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1930558261
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.329876733
Short name T557
Test name
Test status
Simulation time 13645854 ps
CPU time 0.63 seconds
Started Aug 10 05:23:38 PM PDT 24
Finished Aug 10 05:23:39 PM PDT 24
Peak memory 182584 kb
Host smart-5daec14a-1d37-4ae3-9346-757178107539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329876733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.329876733
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4029141604
Short name T504
Test name
Test status
Simulation time 76329728 ps
CPU time 0.84 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 192488 kb
Host smart-97e90914-4188-4d7e-9f7d-7cffc12103b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029141604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4029141604
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1211516900
Short name T455
Test name
Test status
Simulation time 1281837677 ps
CPU time 1.83 seconds
Started Aug 10 05:23:37 PM PDT 24
Finished Aug 10 05:23:39 PM PDT 24
Peak memory 197496 kb
Host smart-067b8995-b028-4a7e-a0f1-2009f6a4226f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211516900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1211516900
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1891281694
Short name T569
Test name
Test status
Simulation time 96173098 ps
CPU time 1.27 seconds
Started Aug 10 05:23:42 PM PDT 24
Finished Aug 10 05:23:43 PM PDT 24
Peak memory 194648 kb
Host smart-7c485b1c-bbce-4948-8fe5-36f6aa9dde6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891281694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1891281694
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2288680114
Short name T454
Test name
Test status
Simulation time 32209935 ps
CPU time 1.37 seconds
Started Aug 10 05:23:38 PM PDT 24
Finished Aug 10 05:23:39 PM PDT 24
Peak memory 197736 kb
Host smart-f70ffe9c-318c-41fb-a6d6-d0065ceefb79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288680114 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2288680114
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.434452245
Short name T505
Test name
Test status
Simulation time 85699235 ps
CPU time 0.54 seconds
Started Aug 10 05:23:46 PM PDT 24
Finished Aug 10 05:23:46 PM PDT 24
Peak memory 182556 kb
Host smart-a3b66032-4024-4671-9dc1-8b46ec51b9c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434452245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.434452245
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3941439653
Short name T475
Test name
Test status
Simulation time 11062875 ps
CPU time 0.54 seconds
Started Aug 10 05:23:47 PM PDT 24
Finished Aug 10 05:23:48 PM PDT 24
Peak memory 182240 kb
Host smart-0dcc5042-eb3a-4ecc-8245-64de7ba285a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941439653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3941439653
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2755278528
Short name T534
Test name
Test status
Simulation time 29720989 ps
CPU time 0.68 seconds
Started Aug 10 05:23:38 PM PDT 24
Finished Aug 10 05:23:39 PM PDT 24
Peak memory 191960 kb
Host smart-ea604e64-085e-4825-a903-1fb8065f7619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755278528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2755278528
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3534895617
Short name T575
Test name
Test status
Simulation time 59357892 ps
CPU time 1.26 seconds
Started Aug 10 05:23:42 PM PDT 24
Finished Aug 10 05:23:43 PM PDT 24
Peak memory 197316 kb
Host smart-a5fb6038-9be1-4d72-b56e-b69afa0256e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534895617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3534895617
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4118138529
Short name T487
Test name
Test status
Simulation time 135145064 ps
CPU time 1.08 seconds
Started Aug 10 05:23:37 PM PDT 24
Finished Aug 10 05:23:39 PM PDT 24
Peak memory 195224 kb
Host smart-4adf56d0-214d-422d-b966-3f6f95821f7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118138529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.4118138529
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.261843469
Short name T520
Test name
Test status
Simulation time 25928333 ps
CPU time 0.82 seconds
Started Aug 10 05:23:37 PM PDT 24
Finished Aug 10 05:23:38 PM PDT 24
Peak memory 197104 kb
Host smart-52ed5f55-d82d-4221-9054-4706d6146245
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261843469 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.261843469
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1296779187
Short name T36
Test name
Test status
Simulation time 15136596 ps
CPU time 0.57 seconds
Started Aug 10 05:23:43 PM PDT 24
Finished Aug 10 05:23:44 PM PDT 24
Peak memory 182780 kb
Host smart-4a6a428c-a6a8-4be6-a9a2-4dbdd73924da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296779187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1296779187
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1282219959
Short name T478
Test name
Test status
Simulation time 62993998 ps
CPU time 0.52 seconds
Started Aug 10 05:23:36 PM PDT 24
Finished Aug 10 05:23:37 PM PDT 24
Peak memory 182436 kb
Host smart-b9b2e850-3f1b-4050-a991-625d47563ed2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282219959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1282219959
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3403308219
Short name T525
Test name
Test status
Simulation time 65179368 ps
CPU time 0.6 seconds
Started Aug 10 05:23:45 PM PDT 24
Finished Aug 10 05:23:46 PM PDT 24
Peak memory 191812 kb
Host smart-611f6b75-d58a-4340-b5c6-34bd95a46fe5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403308219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3403308219
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3932247307
Short name T500
Test name
Test status
Simulation time 161505913 ps
CPU time 2.5 seconds
Started Aug 10 05:23:33 PM PDT 24
Finished Aug 10 05:23:35 PM PDT 24
Peak memory 197696 kb
Host smart-de4c4c7e-6524-4921-8fe0-a6eb55aa2caa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932247307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3932247307
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3106337866
Short name T542
Test name
Test status
Simulation time 115261672 ps
CPU time 1.4 seconds
Started Aug 10 05:23:38 PM PDT 24
Finished Aug 10 05:23:39 PM PDT 24
Peak memory 195676 kb
Host smart-f82227a4-2ac7-4b00-a4ed-456474cbb8cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106337866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3106337866
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.63807195
Short name T483
Test name
Test status
Simulation time 122966185 ps
CPU time 0.81 seconds
Started Aug 10 05:23:36 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 196368 kb
Host smart-359d4e57-4e1b-4097-897d-88e26c219b5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63807195 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.63807195
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3951586248
Short name T537
Test name
Test status
Simulation time 51871135 ps
CPU time 0.56 seconds
Started Aug 10 05:23:43 PM PDT 24
Finished Aug 10 05:23:44 PM PDT 24
Peak memory 182988 kb
Host smart-31c51b2b-fe86-4cc6-bd85-8d4c62bf43b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951586248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3951586248
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4127067399
Short name T515
Test name
Test status
Simulation time 17296719 ps
CPU time 0.54 seconds
Started Aug 10 05:23:46 PM PDT 24
Finished Aug 10 05:23:46 PM PDT 24
Peak memory 182564 kb
Host smart-9e5273d0-a715-43ea-85ef-e9767fc59343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127067399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.4127067399
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.764643901
Short name T578
Test name
Test status
Simulation time 36522051 ps
CPU time 0.76 seconds
Started Aug 10 05:23:43 PM PDT 24
Finished Aug 10 05:23:44 PM PDT 24
Peak memory 193720 kb
Host smart-6bb864a2-c200-4cdf-b09a-911035e60869
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764643901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.764643901
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1742735422
Short name T476
Test name
Test status
Simulation time 124412822 ps
CPU time 2.09 seconds
Started Aug 10 05:23:38 PM PDT 24
Finished Aug 10 05:23:40 PM PDT 24
Peak memory 197532 kb
Host smart-c39e20f4-781f-4252-97cc-170992c959f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742735422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1742735422
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3169638318
Short name T99
Test name
Test status
Simulation time 102977977 ps
CPU time 1.38 seconds
Started Aug 10 05:23:51 PM PDT 24
Finished Aug 10 05:23:52 PM PDT 24
Peak memory 194568 kb
Host smart-0c20cae2-5812-4f3b-87bf-8456077d02b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169638318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3169638318
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.337587394
Short name T530
Test name
Test status
Simulation time 39429318 ps
CPU time 0.98 seconds
Started Aug 10 05:23:40 PM PDT 24
Finished Aug 10 05:23:41 PM PDT 24
Peak memory 196848 kb
Host smart-4ff5a5e7-4d3f-4abe-9d6a-4c71443666b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337587394 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.337587394
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1128725823
Short name T521
Test name
Test status
Simulation time 47163712 ps
CPU time 0.55 seconds
Started Aug 10 05:23:41 PM PDT 24
Finished Aug 10 05:23:42 PM PDT 24
Peak memory 182292 kb
Host smart-9c1588c6-509d-41e5-97ef-f628fd192f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128725823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1128725823
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.491612584
Short name T77
Test name
Test status
Simulation time 120101803 ps
CPU time 0.63 seconds
Started Aug 10 05:23:37 PM PDT 24
Finished Aug 10 05:23:38 PM PDT 24
Peak memory 192388 kb
Host smart-aa8719df-ce5f-45fe-9af5-b18df82a5803
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491612584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.491612584
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3749741823
Short name T522
Test name
Test status
Simulation time 33728667 ps
CPU time 1.75 seconds
Started Aug 10 05:23:44 PM PDT 24
Finished Aug 10 05:23:46 PM PDT 24
Peak memory 197540 kb
Host smart-9aebc42f-8dc9-4cc7-a773-80e6d965bcbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749741823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3749741823
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1272558691
Short name T32
Test name
Test status
Simulation time 47436264 ps
CPU time 0.78 seconds
Started Aug 10 05:23:46 PM PDT 24
Finished Aug 10 05:23:47 PM PDT 24
Peak memory 193556 kb
Host smart-68d67285-c027-4fd0-98ca-2513075b5278
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272558691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1272558691
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3253318666
Short name T460
Test name
Test status
Simulation time 85262624 ps
CPU time 0.98 seconds
Started Aug 10 05:23:36 PM PDT 24
Finished Aug 10 05:23:37 PM PDT 24
Peak memory 197480 kb
Host smart-f939618b-77ab-4606-b487-0783d9923640
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253318666 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3253318666
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1498079608
Short name T507
Test name
Test status
Simulation time 13639570 ps
CPU time 0.56 seconds
Started Aug 10 05:23:41 PM PDT 24
Finished Aug 10 05:23:42 PM PDT 24
Peak memory 182896 kb
Host smart-2df490fb-04a7-4bb9-b263-c79bee767205
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498079608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1498079608
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.7700578
Short name T536
Test name
Test status
Simulation time 31445414 ps
CPU time 0.57 seconds
Started Aug 10 05:23:36 PM PDT 24
Finished Aug 10 05:23:37 PM PDT 24
Peak memory 182588 kb
Host smart-f546b0c7-fc91-4bc4-97cc-585e72613b07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7700578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.7700578
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.835507681
Short name T67
Test name
Test status
Simulation time 17066364 ps
CPU time 0.68 seconds
Started Aug 10 05:23:41 PM PDT 24
Finished Aug 10 05:23:42 PM PDT 24
Peak memory 192492 kb
Host smart-a4b38809-d6b1-4b7e-9c5c-a5ced092da87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835507681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.835507681
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1917108088
Short name T568
Test name
Test status
Simulation time 187472152 ps
CPU time 2.33 seconds
Started Aug 10 05:23:46 PM PDT 24
Finished Aug 10 05:23:54 PM PDT 24
Peak memory 197688 kb
Host smart-79464d61-95c6-4edb-a133-b8bcadcd1620
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917108088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1917108088
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.4239831444
Short name T561
Test name
Test status
Simulation time 41037381 ps
CPU time 0.62 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 192920 kb
Host smart-7b0897aa-51e8-4a18-9079-eb93c7f69767
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239831444 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.4239831444
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.893102767
Short name T540
Test name
Test status
Simulation time 21360110 ps
CPU time 0.54 seconds
Started Aug 10 05:23:45 PM PDT 24
Finished Aug 10 05:23:46 PM PDT 24
Peak memory 182564 kb
Host smart-e540de8b-1339-420e-83e7-77c4348631a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893102767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.893102767
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3158879716
Short name T464
Test name
Test status
Simulation time 17214721 ps
CPU time 0.59 seconds
Started Aug 10 05:23:48 PM PDT 24
Finished Aug 10 05:23:48 PM PDT 24
Peak memory 182732 kb
Host smart-17efc00c-9e78-410c-b7c7-1c8c86cdb632
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158879716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3158879716
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.4028434811
Short name T510
Test name
Test status
Simulation time 46318524 ps
CPU time 0.65 seconds
Started Aug 10 05:23:41 PM PDT 24
Finished Aug 10 05:23:42 PM PDT 24
Peak memory 192404 kb
Host smart-764d2f4f-0cd1-4cac-856c-f1911c8b4bb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028434811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.4028434811
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1027386131
Short name T466
Test name
Test status
Simulation time 195134027 ps
CPU time 2.62 seconds
Started Aug 10 05:23:40 PM PDT 24
Finished Aug 10 05:23:43 PM PDT 24
Peak memory 197624 kb
Host smart-168880b4-b612-4250-b92f-0095a5cff60a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027386131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1027386131
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2127309080
Short name T576
Test name
Test status
Simulation time 88381755 ps
CPU time 0.85 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 193716 kb
Host smart-0470da99-1df4-4eef-a25b-f61f24b6b514
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127309080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2127309080
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3826166046
Short name T518
Test name
Test status
Simulation time 637398076 ps
CPU time 1.53 seconds
Started Aug 10 05:23:45 PM PDT 24
Finished Aug 10 05:23:47 PM PDT 24
Peak memory 197784 kb
Host smart-ff226c51-3645-4593-aaf9-5855446c723e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826166046 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3826166046
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1285408193
Short name T61
Test name
Test status
Simulation time 151777108 ps
CPU time 0.55 seconds
Started Aug 10 05:23:39 PM PDT 24
Finished Aug 10 05:23:40 PM PDT 24
Peak memory 182864 kb
Host smart-04bb6696-a933-4849-b9de-09b5bd2062c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285408193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1285408193
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3540213976
Short name T548
Test name
Test status
Simulation time 17225401 ps
CPU time 0.56 seconds
Started Aug 10 05:23:46 PM PDT 24
Finished Aug 10 05:23:47 PM PDT 24
Peak memory 182720 kb
Host smart-d0f3fa8a-463a-4a5c-97af-939086af0e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540213976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3540213976
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2201380517
Short name T89
Test name
Test status
Simulation time 17464228 ps
CPU time 0.68 seconds
Started Aug 10 05:23:49 PM PDT 24
Finished Aug 10 05:23:50 PM PDT 24
Peak memory 191832 kb
Host smart-42b029f8-e0f5-4ab8-9554-853601f8bc17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201380517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2201380517
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3474020025
Short name T543
Test name
Test status
Simulation time 51474654 ps
CPU time 2.65 seconds
Started Aug 10 05:23:38 PM PDT 24
Finished Aug 10 05:23:41 PM PDT 24
Peak memory 197692 kb
Host smart-d4aaa195-a44c-41a9-9c63-1f7f9c5253a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474020025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3474020025
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2745925316
Short name T567
Test name
Test status
Simulation time 770833923 ps
CPU time 0.82 seconds
Started Aug 10 05:23:41 PM PDT 24
Finished Aug 10 05:23:42 PM PDT 24
Peak memory 183340 kb
Host smart-414e1d61-f6cf-4d21-9b73-7255cc0da4dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745925316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2745925316
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1938673786
Short name T565
Test name
Test status
Simulation time 36895248 ps
CPU time 0.59 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:35 PM PDT 24
Peak memory 193124 kb
Host smart-500e6426-0616-492e-8bdc-f5d0d45bf59a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938673786 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1938673786
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.895389204
Short name T489
Test name
Test status
Simulation time 14739085 ps
CPU time 0.55 seconds
Started Aug 10 05:23:47 PM PDT 24
Finished Aug 10 05:23:48 PM PDT 24
Peak memory 182616 kb
Host smart-800d5b52-150a-45b8-b54d-15e5d1638343
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895389204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.895389204
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.563649617
Short name T501
Test name
Test status
Simulation time 16664988 ps
CPU time 0.55 seconds
Started Aug 10 05:23:44 PM PDT 24
Finished Aug 10 05:23:45 PM PDT 24
Peak memory 182712 kb
Host smart-3740655a-2ea6-4c66-b9fd-76e660b9f7d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563649617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.563649617
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3034421608
Short name T574
Test name
Test status
Simulation time 29135037 ps
CPU time 0.74 seconds
Started Aug 10 05:23:44 PM PDT 24
Finished Aug 10 05:23:45 PM PDT 24
Peak memory 192444 kb
Host smart-8bae9a30-5cc5-41b7-9d97-88c2f56b49cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034421608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3034421608
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3133444238
Short name T473
Test name
Test status
Simulation time 98652261 ps
CPU time 1.12 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 196400 kb
Host smart-0d6b086a-97da-4d0d-ab2d-f028fb63757e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133444238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3133444238
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1795193206
Short name T477
Test name
Test status
Simulation time 154366639 ps
CPU time 1.11 seconds
Started Aug 10 05:23:39 PM PDT 24
Finished Aug 10 05:23:41 PM PDT 24
Peak memory 183504 kb
Host smart-9b1bb87e-b271-4388-821d-748612ca976f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795193206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1795193206
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.85251092
Short name T463
Test name
Test status
Simulation time 26442555 ps
CPU time 1.1 seconds
Started Aug 10 05:23:45 PM PDT 24
Finished Aug 10 05:23:47 PM PDT 24
Peak memory 197588 kb
Host smart-344b7d13-13b1-4906-93b4-40ec3d6521d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85251092 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.85251092
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.505589872
Short name T533
Test name
Test status
Simulation time 37375100 ps
CPU time 0.58 seconds
Started Aug 10 05:23:46 PM PDT 24
Finished Aug 10 05:23:47 PM PDT 24
Peak memory 182916 kb
Host smart-7ed48b02-0680-457b-b1e3-1063db6428e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505589872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.505589872
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2316173772
Short name T453
Test name
Test status
Simulation time 19792920 ps
CPU time 0.55 seconds
Started Aug 10 05:23:44 PM PDT 24
Finished Aug 10 05:23:45 PM PDT 24
Peak memory 182744 kb
Host smart-344d28b2-c298-4961-8e46-4db1dae127ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316173772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2316173772
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3083948366
Short name T517
Test name
Test status
Simulation time 103127581 ps
CPU time 0.68 seconds
Started Aug 10 05:23:46 PM PDT 24
Finished Aug 10 05:23:47 PM PDT 24
Peak memory 191832 kb
Host smart-8fd847f3-b7cb-4817-953f-5067b76948ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083948366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3083948366
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.4065585285
Short name T564
Test name
Test status
Simulation time 251917992 ps
CPU time 1.25 seconds
Started Aug 10 05:23:41 PM PDT 24
Finished Aug 10 05:23:43 PM PDT 24
Peak memory 197344 kb
Host smart-6a73cf70-1754-4f4b-8b86-822dd66c562f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065585285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.4065585285
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2096888177
Short name T524
Test name
Test status
Simulation time 409537575 ps
CPU time 1.31 seconds
Started Aug 10 05:23:45 PM PDT 24
Finished Aug 10 05:23:46 PM PDT 24
Peak memory 195480 kb
Host smart-918b35a4-88e4-4c87-9dd2-ba318e93cc94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096888177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2096888177
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.244873444
Short name T572
Test name
Test status
Simulation time 69396284 ps
CPU time 0.63 seconds
Started Aug 10 05:23:45 PM PDT 24
Finished Aug 10 05:23:46 PM PDT 24
Peak memory 182880 kb
Host smart-1b8417d7-0ac0-46c3-946a-d3e842b17a6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244873444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.244873444
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.729930532
Short name T96
Test name
Test status
Simulation time 105896945 ps
CPU time 1.55 seconds
Started Aug 10 05:23:47 PM PDT 24
Finished Aug 10 05:23:48 PM PDT 24
Peak memory 191348 kb
Host smart-4f7649b7-63fd-4e03-a823-07c22d0a1b07
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729930532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.729930532
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.649216643
Short name T87
Test name
Test status
Simulation time 68975807 ps
CPU time 0.57 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:34 PM PDT 24
Peak memory 182960 kb
Host smart-41460b16-27a7-4e81-a722-81e425f564bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649216643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.649216643
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3572755045
Short name T468
Test name
Test status
Simulation time 195576613 ps
CPU time 0.97 seconds
Started Aug 10 05:23:42 PM PDT 24
Finished Aug 10 05:23:43 PM PDT 24
Peak memory 197516 kb
Host smart-698649e1-096f-483e-af34-1967b62185c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572755045 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3572755045
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1825571183
Short name T86
Test name
Test status
Simulation time 36929796 ps
CPU time 0.61 seconds
Started Aug 10 05:23:37 PM PDT 24
Finished Aug 10 05:23:38 PM PDT 24
Peak memory 182972 kb
Host smart-c8095cf3-b39e-4357-b133-9edff1ac3776
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825571183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1825571183
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2637004536
Short name T508
Test name
Test status
Simulation time 14369030 ps
CPU time 0.52 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:35 PM PDT 24
Peak memory 182156 kb
Host smart-860f098b-82b2-4cd6-818d-5146931558ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637004536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2637004536
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3799118724
Short name T494
Test name
Test status
Simulation time 25322141 ps
CPU time 0.79 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:45 PM PDT 24
Peak memory 191904 kb
Host smart-8d2191b1-c21d-4c60-a992-cc153dc28eac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799118724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3799118724
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.195100760
Short name T55
Test name
Test status
Simulation time 63300444 ps
CPU time 1.25 seconds
Started Aug 10 05:23:33 PM PDT 24
Finished Aug 10 05:23:34 PM PDT 24
Peak memory 197540 kb
Host smart-044c157a-3511-4388-b8de-2cdf58bc0f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195100760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.195100760
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.465339897
Short name T485
Test name
Test status
Simulation time 596762095 ps
CPU time 1.13 seconds
Started Aug 10 05:23:29 PM PDT 24
Finished Aug 10 05:23:31 PM PDT 24
Peak memory 194352 kb
Host smart-7194880c-b120-4452-a41d-f0af74a62386
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465339897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.465339897
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1644446516
Short name T480
Test name
Test status
Simulation time 15007107 ps
CPU time 0.6 seconds
Started Aug 10 05:23:33 PM PDT 24
Finished Aug 10 05:23:33 PM PDT 24
Peak memory 182248 kb
Host smart-56d157ea-3cec-48ce-82de-e927d50fc15f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644446516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1644446516
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1630696895
Short name T532
Test name
Test status
Simulation time 11642847 ps
CPU time 0.55 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 181996 kb
Host smart-ba720228-7c59-4cad-99fb-72db140659ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630696895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1630696895
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.936223092
Short name T538
Test name
Test status
Simulation time 45818863 ps
CPU time 0.56 seconds
Started Aug 10 05:23:39 PM PDT 24
Finished Aug 10 05:23:40 PM PDT 24
Peak memory 182692 kb
Host smart-e520d57b-f79a-4d41-a6c8-837dd2edd784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936223092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.936223092
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2123410003
Short name T502
Test name
Test status
Simulation time 39329881 ps
CPU time 0.56 seconds
Started Aug 10 05:23:52 PM PDT 24
Finished Aug 10 05:23:53 PM PDT 24
Peak memory 182260 kb
Host smart-0b0dec01-432d-4ed2-8242-9c9bf3eaa6a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123410003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2123410003
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1310701760
Short name T509
Test name
Test status
Simulation time 38811298 ps
CPU time 0.55 seconds
Started Aug 10 05:23:36 PM PDT 24
Finished Aug 10 05:23:37 PM PDT 24
Peak memory 182804 kb
Host smart-c4282f8e-d7c7-4fb6-964f-53459a3f4064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310701760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1310701760
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1729510092
Short name T523
Test name
Test status
Simulation time 240787547 ps
CPU time 0.52 seconds
Started Aug 10 05:23:47 PM PDT 24
Finished Aug 10 05:23:47 PM PDT 24
Peak memory 182712 kb
Host smart-e9d278a9-4922-46c9-a8d0-ef8d35464135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729510092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1729510092
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2225268770
Short name T571
Test name
Test status
Simulation time 13237998 ps
CPU time 0.53 seconds
Started Aug 10 05:23:37 PM PDT 24
Finished Aug 10 05:23:38 PM PDT 24
Peak memory 182176 kb
Host smart-d2224899-953f-441f-9ede-1cd16d91eda0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225268770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2225268770
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2165195089
Short name T449
Test name
Test status
Simulation time 23485840 ps
CPU time 0.61 seconds
Started Aug 10 05:23:51 PM PDT 24
Finished Aug 10 05:23:52 PM PDT 24
Peak memory 182764 kb
Host smart-0265709e-a7de-42e8-becb-d18075f83cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165195089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2165195089
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3254307266
Short name T503
Test name
Test status
Simulation time 17047486 ps
CPU time 0.55 seconds
Started Aug 10 05:23:38 PM PDT 24
Finished Aug 10 05:23:39 PM PDT 24
Peak memory 182692 kb
Host smart-3c14fab2-e72f-49d7-b149-cf3f650565e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254307266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3254307266
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1087815017
Short name T547
Test name
Test status
Simulation time 234612133 ps
CPU time 0.55 seconds
Started Aug 10 05:23:43 PM PDT 24
Finished Aug 10 05:23:44 PM PDT 24
Peak memory 182740 kb
Host smart-52012d6a-de0f-4e11-b4b3-fd7554d9ff27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087815017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1087815017
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3518971143
Short name T496
Test name
Test status
Simulation time 57640012 ps
CPU time 0.67 seconds
Started Aug 10 05:23:45 PM PDT 24
Finished Aug 10 05:23:45 PM PDT 24
Peak memory 182888 kb
Host smart-42720db8-46b4-45e7-8563-53e35d13b002
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518971143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3518971143
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1138040787
Short name T88
Test name
Test status
Simulation time 5496785288 ps
CPU time 2.62 seconds
Started Aug 10 05:23:40 PM PDT 24
Finished Aug 10 05:23:43 PM PDT 24
Peak memory 183192 kb
Host smart-b0145384-46f7-4c65-93be-7057a595f352
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138040787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1138040787
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2009613424
Short name T472
Test name
Test status
Simulation time 13386297 ps
CPU time 0.54 seconds
Started Aug 10 05:23:37 PM PDT 24
Finished Aug 10 05:23:38 PM PDT 24
Peak memory 182912 kb
Host smart-1cc71776-93aa-4f04-ae55-5f1d2408c095
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009613424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2009613424
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2673179749
Short name T562
Test name
Test status
Simulation time 15413328 ps
CPU time 0.61 seconds
Started Aug 10 05:23:30 PM PDT 24
Finished Aug 10 05:23:30 PM PDT 24
Peak memory 193060 kb
Host smart-ec8c3875-be66-4f39-a0f3-6f3442363a64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673179749 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2673179749
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.4047020874
Short name T499
Test name
Test status
Simulation time 60516570 ps
CPU time 0.53 seconds
Started Aug 10 05:24:49 PM PDT 24
Finished Aug 10 05:24:49 PM PDT 24
Peak memory 182752 kb
Host smart-0bc9dbb1-cb06-45b6-8f43-d7c13d60abee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047020874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.4047020874
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1610702385
Short name T558
Test name
Test status
Simulation time 15893817 ps
CPU time 0.56 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:35 PM PDT 24
Peak memory 182756 kb
Host smart-731b8b1b-68aa-4363-aade-6cf175bf5e64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610702385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1610702385
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2784981902
Short name T552
Test name
Test status
Simulation time 15269580 ps
CPU time 0.6 seconds
Started Aug 10 05:23:36 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 192048 kb
Host smart-ec76eefe-dcc2-4c11-8bf8-c24fbccc5070
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784981902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2784981902
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1214996896
Short name T467
Test name
Test status
Simulation time 39915381 ps
CPU time 1.1 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:35 PM PDT 24
Peak memory 197504 kb
Host smart-8d0775d9-0a3c-4c62-8da4-1195ee2336dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214996896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1214996896
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.585765653
Short name T511
Test name
Test status
Simulation time 119284916 ps
CPU time 1.07 seconds
Started Aug 10 05:23:30 PM PDT 24
Finished Aug 10 05:23:32 PM PDT 24
Peak memory 195216 kb
Host smart-8ddf73f6-0707-4edc-ac13-790c1d84f74c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585765653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.585765653
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2623102996
Short name T490
Test name
Test status
Simulation time 23085668 ps
CPU time 0.54 seconds
Started Aug 10 05:23:47 PM PDT 24
Finished Aug 10 05:23:48 PM PDT 24
Peak memory 182224 kb
Host smart-9b317540-b725-46ca-99f0-5b525f09fdf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623102996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2623102996
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2923338341
Short name T493
Test name
Test status
Simulation time 13801895 ps
CPU time 0.62 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 182772 kb
Host smart-9387a350-4e96-4f26-b3cf-ece04b793813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923338341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2923338341
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.170658104
Short name T573
Test name
Test status
Simulation time 58408478 ps
CPU time 0.59 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:35 PM PDT 24
Peak memory 182752 kb
Host smart-ec18e7fe-4717-4a0d-8538-fffa32001a4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170658104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.170658104
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1266234095
Short name T529
Test name
Test status
Simulation time 14153931 ps
CPU time 0.52 seconds
Started Aug 10 05:24:41 PM PDT 24
Finished Aug 10 05:24:41 PM PDT 24
Peak memory 182528 kb
Host smart-3589f34a-b31a-4e82-a69b-13cbd2232a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266234095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1266234095
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.662275543
Short name T519
Test name
Test status
Simulation time 13072185 ps
CPU time 0.53 seconds
Started Aug 10 05:23:43 PM PDT 24
Finished Aug 10 05:23:44 PM PDT 24
Peak memory 182748 kb
Host smart-6ce74aef-82e8-4b38-b821-dcbb64538e39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662275543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.662275543
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1914014043
Short name T516
Test name
Test status
Simulation time 42442707 ps
CPU time 0.57 seconds
Started Aug 10 05:23:47 PM PDT 24
Finished Aug 10 05:23:47 PM PDT 24
Peak memory 182648 kb
Host smart-8a65bd1d-196d-4d33-959b-c5cc1e9fb4c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914014043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1914014043
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4245120514
Short name T498
Test name
Test status
Simulation time 11258164 ps
CPU time 0.55 seconds
Started Aug 10 05:23:39 PM PDT 24
Finished Aug 10 05:23:40 PM PDT 24
Peak memory 182240 kb
Host smart-72f95003-d12a-4a72-a655-e6d15e0792f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245120514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4245120514
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.224270058
Short name T559
Test name
Test status
Simulation time 38701189 ps
CPU time 0.54 seconds
Started Aug 10 05:23:44 PM PDT 24
Finished Aug 10 05:23:44 PM PDT 24
Peak memory 182296 kb
Host smart-a88107d0-a71c-4bb6-a122-fa26cb498e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224270058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.224270058
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3377268096
Short name T512
Test name
Test status
Simulation time 34731688 ps
CPU time 0.54 seconds
Started Aug 10 05:23:42 PM PDT 24
Finished Aug 10 05:23:42 PM PDT 24
Peak memory 182592 kb
Host smart-0a03d7f2-9d43-4049-a783-1e0c3dc3deab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377268096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3377268096
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4184132635
Short name T451
Test name
Test status
Simulation time 41338753 ps
CPU time 0.6 seconds
Started Aug 10 05:23:41 PM PDT 24
Finished Aug 10 05:23:42 PM PDT 24
Peak memory 182944 kb
Host smart-b973b6f5-2cb0-4ef4-a459-c4f7f9f59ecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184132635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4184132635
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3272803616
Short name T83
Test name
Test status
Simulation time 18930713 ps
CPU time 0.7 seconds
Started Aug 10 05:23:47 PM PDT 24
Finished Aug 10 05:23:47 PM PDT 24
Peak memory 192788 kb
Host smart-7d19fe43-6c3b-4cbb-8a2d-ef02818d9f66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272803616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3272803616
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2337812921
Short name T539
Test name
Test status
Simulation time 430006124 ps
CPU time 1.48 seconds
Started Aug 10 05:23:37 PM PDT 24
Finished Aug 10 05:23:39 PM PDT 24
Peak memory 191344 kb
Host smart-4891ff5a-85af-4c75-86ce-8a467d5fb095
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337812921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2337812921
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1255882987
Short name T544
Test name
Test status
Simulation time 25020176 ps
CPU time 0.58 seconds
Started Aug 10 05:23:32 PM PDT 24
Finished Aug 10 05:23:33 PM PDT 24
Peak memory 182928 kb
Host smart-0cde42d4-70ad-4d8f-ac77-623249684158
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255882987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1255882987
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.48887251
Short name T555
Test name
Test status
Simulation time 65783677 ps
CPU time 0.8 seconds
Started Aug 10 05:23:37 PM PDT 24
Finished Aug 10 05:23:38 PM PDT 24
Peak memory 197532 kb
Host smart-0893c5fe-3881-4a23-9ddf-6675593b6edd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48887251 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.48887251
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4090679993
Short name T527
Test name
Test status
Simulation time 51513953 ps
CPU time 0.57 seconds
Started Aug 10 05:23:41 PM PDT 24
Finished Aug 10 05:23:42 PM PDT 24
Peak memory 182820 kb
Host smart-d8f05406-4e1d-4289-8ef1-d36d4314ac32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090679993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.4090679993
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2065580179
Short name T486
Test name
Test status
Simulation time 13661425 ps
CPU time 0.54 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:34 PM PDT 24
Peak memory 182028 kb
Host smart-02e9dc59-7705-41be-a899-74503338a72c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065580179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2065580179
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1940682233
Short name T91
Test name
Test status
Simulation time 67031733 ps
CPU time 0.58 seconds
Started Aug 10 05:23:37 PM PDT 24
Finished Aug 10 05:23:37 PM PDT 24
Peak memory 192076 kb
Host smart-93d57b84-9bbe-4c5a-adf9-69d5777bd0ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940682233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1940682233
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2936748041
Short name T497
Test name
Test status
Simulation time 411107900 ps
CPU time 2.25 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 197168 kb
Host smart-13a19e50-0461-49e2-a531-49c9fd8060d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936748041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2936748041
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2849632294
Short name T577
Test name
Test status
Simulation time 119112116 ps
CPU time 1.35 seconds
Started Aug 10 05:23:31 PM PDT 24
Finished Aug 10 05:23:32 PM PDT 24
Peak memory 195600 kb
Host smart-33b08181-ecd8-4309-b132-c244626e7830
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849632294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2849632294
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.4259037748
Short name T492
Test name
Test status
Simulation time 29124068 ps
CPU time 0.56 seconds
Started Aug 10 05:23:48 PM PDT 24
Finished Aug 10 05:23:49 PM PDT 24
Peak memory 182764 kb
Host smart-e654533c-64c0-4582-a887-ca333841d573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259037748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.4259037748
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1439782656
Short name T457
Test name
Test status
Simulation time 12338421 ps
CPU time 0.56 seconds
Started Aug 10 05:23:43 PM PDT 24
Finished Aug 10 05:23:43 PM PDT 24
Peak memory 182204 kb
Host smart-1c3e6a38-f592-4181-a312-de3339ce32a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439782656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1439782656
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1776175067
Short name T488
Test name
Test status
Simulation time 31425071 ps
CPU time 0.52 seconds
Started Aug 10 05:23:44 PM PDT 24
Finished Aug 10 05:23:45 PM PDT 24
Peak memory 182444 kb
Host smart-9ae91277-ce42-434c-b58b-9397ce724bff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776175067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1776175067
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.696063061
Short name T469
Test name
Test status
Simulation time 14680134 ps
CPU time 0.55 seconds
Started Aug 10 05:23:58 PM PDT 24
Finished Aug 10 05:23:58 PM PDT 24
Peak memory 182732 kb
Host smart-6a2a8703-e684-4e87-96f4-1a4d216315e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696063061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.696063061
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2247748025
Short name T550
Test name
Test status
Simulation time 14158229 ps
CPU time 0.54 seconds
Started Aug 10 05:23:43 PM PDT 24
Finished Aug 10 05:23:44 PM PDT 24
Peak memory 182720 kb
Host smart-288b48ad-fd57-4b3a-9612-34721cb0e048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247748025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2247748025
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3804272116
Short name T491
Test name
Test status
Simulation time 42817416 ps
CPU time 0.56 seconds
Started Aug 10 05:23:54 PM PDT 24
Finished Aug 10 05:23:54 PM PDT 24
Peak memory 182604 kb
Host smart-9d4b0dd1-1eae-43c9-8ea9-59bcc9348efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804272116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3804272116
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.834793173
Short name T474
Test name
Test status
Simulation time 43591079 ps
CPU time 0.53 seconds
Started Aug 10 05:23:50 PM PDT 24
Finished Aug 10 05:23:51 PM PDT 24
Peak memory 182296 kb
Host smart-32b03301-ba0f-43db-8d5a-eaa683e2523b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834793173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.834793173
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3145471274
Short name T482
Test name
Test status
Simulation time 14133628 ps
CPU time 0.56 seconds
Started Aug 10 05:23:40 PM PDT 24
Finished Aug 10 05:23:40 PM PDT 24
Peak memory 182684 kb
Host smart-7024f8f5-69ec-4067-aeac-a25359b51faa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145471274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3145471274
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3735910786
Short name T450
Test name
Test status
Simulation time 16289325 ps
CPU time 0.56 seconds
Started Aug 10 05:23:42 PM PDT 24
Finished Aug 10 05:23:43 PM PDT 24
Peak memory 182656 kb
Host smart-7717b981-6dd0-402d-baf2-dde76fda97b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735910786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3735910786
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2037450768
Short name T551
Test name
Test status
Simulation time 18354966 ps
CPU time 0.57 seconds
Started Aug 10 05:24:00 PM PDT 24
Finished Aug 10 05:24:00 PM PDT 24
Peak memory 182128 kb
Host smart-c79ea711-7f12-400e-b8c1-824e0e8b8326
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037450768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2037450768
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1330227113
Short name T452
Test name
Test status
Simulation time 151537815 ps
CPU time 1.04 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:29 PM PDT 24
Peak memory 194552 kb
Host smart-da427288-2aeb-49ab-8486-643ade584ec4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330227113 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1330227113
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2325286468
Short name T81
Test name
Test status
Simulation time 14499493 ps
CPU time 0.55 seconds
Started Aug 10 05:24:41 PM PDT 24
Finished Aug 10 05:24:41 PM PDT 24
Peak memory 182700 kb
Host smart-058fb20b-d985-4ad7-bf1e-6c04a38c8938
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325286468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2325286468
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1623481154
Short name T579
Test name
Test status
Simulation time 14958987 ps
CPU time 0.55 seconds
Started Aug 10 05:23:27 PM PDT 24
Finished Aug 10 05:23:28 PM PDT 24
Peak memory 182720 kb
Host smart-dbdc3a93-6c87-422d-8a28-d6efed6438ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623481154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1623481154
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2162574946
Short name T35
Test name
Test status
Simulation time 27325786 ps
CPU time 0.71 seconds
Started Aug 10 05:23:20 PM PDT 24
Finished Aug 10 05:23:21 PM PDT 24
Peak memory 193160 kb
Host smart-70513ad1-cbd4-47ff-b398-0fcd691b818f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162574946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2162574946
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2806604033
Short name T481
Test name
Test status
Simulation time 451360889 ps
CPU time 2.6 seconds
Started Aug 10 05:23:38 PM PDT 24
Finished Aug 10 05:23:41 PM PDT 24
Peak memory 197624 kb
Host smart-3af4b9a3-03d3-4fdb-9949-6b2913a8476f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806604033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2806604033
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1442945511
Short name T554
Test name
Test status
Simulation time 367569602 ps
CPU time 1.33 seconds
Started Aug 10 05:23:33 PM PDT 24
Finished Aug 10 05:23:34 PM PDT 24
Peak memory 183420 kb
Host smart-cd9e98ae-85e9-4960-9ee6-0d5637be2ee5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442945511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1442945511
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.717673583
Short name T461
Test name
Test status
Simulation time 50096229 ps
CPU time 0.78 seconds
Started Aug 10 05:23:39 PM PDT 24
Finished Aug 10 05:23:40 PM PDT 24
Peak memory 195220 kb
Host smart-cce59d76-0b1e-47ce-8228-99668642754d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717673583 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.717673583
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1371906189
Short name T560
Test name
Test status
Simulation time 36994261 ps
CPU time 0.56 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:34 PM PDT 24
Peak memory 182804 kb
Host smart-10950643-423b-4a56-8ea3-842c2a698fe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371906189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1371906189
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4232363419
Short name T546
Test name
Test status
Simulation time 24101777 ps
CPU time 0.56 seconds
Started Aug 10 05:23:33 PM PDT 24
Finished Aug 10 05:23:34 PM PDT 24
Peak memory 182852 kb
Host smart-19a8470d-eb6a-4f90-92db-7323d57ac128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232363419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4232363419
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3505721243
Short name T528
Test name
Test status
Simulation time 34343306 ps
CPU time 0.72 seconds
Started Aug 10 05:23:40 PM PDT 24
Finished Aug 10 05:23:41 PM PDT 24
Peak memory 193568 kb
Host smart-a36ef8c0-8548-42c2-83fa-35453afe92c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505721243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3505721243
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3163040649
Short name T471
Test name
Test status
Simulation time 122995525 ps
CPU time 1.71 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 197704 kb
Host smart-d5576bad-74c3-4e86-ad5a-346da9945647
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163040649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3163040649
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.4131167544
Short name T506
Test name
Test status
Simulation time 113333024 ps
CPU time 0.99 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 197348 kb
Host smart-dc093e31-0116-4609-9510-5a3c8c011d16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131167544 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.4131167544
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3156401551
Short name T462
Test name
Test status
Simulation time 13171592 ps
CPU time 0.56 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:35 PM PDT 24
Peak memory 182884 kb
Host smart-c84cc66f-6876-460e-9274-ff6bffeff34e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156401551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3156401551
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3806024506
Short name T535
Test name
Test status
Simulation time 18220268 ps
CPU time 0.58 seconds
Started Aug 10 05:23:38 PM PDT 24
Finished Aug 10 05:23:39 PM PDT 24
Peak memory 182760 kb
Host smart-e3e12dd4-9083-4505-b195-099182450aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806024506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3806024506
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.892815211
Short name T90
Test name
Test status
Simulation time 223099464 ps
CPU time 0.64 seconds
Started Aug 10 05:23:39 PM PDT 24
Finished Aug 10 05:23:40 PM PDT 24
Peak memory 192068 kb
Host smart-de091211-8432-4536-a2da-59d5a62e5c95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892815211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.892815211
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1149846555
Short name T458
Test name
Test status
Simulation time 204488696 ps
CPU time 1.04 seconds
Started Aug 10 05:23:37 PM PDT 24
Finished Aug 10 05:23:38 PM PDT 24
Peak memory 197092 kb
Host smart-2d03bafc-eef0-4b14-a906-eb8fe8a48d02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149846555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1149846555
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.277674956
Short name T570
Test name
Test status
Simulation time 86160058 ps
CPU time 1.11 seconds
Started Aug 10 05:23:40 PM PDT 24
Finished Aug 10 05:23:41 PM PDT 24
Peak memory 195332 kb
Host smart-37cde6eb-8065-452c-a86a-187d56813eac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277674956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.277674956
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1639952558
Short name T541
Test name
Test status
Simulation time 29974167 ps
CPU time 0.74 seconds
Started Aug 10 05:23:46 PM PDT 24
Finished Aug 10 05:23:47 PM PDT 24
Peak memory 195920 kb
Host smart-551052dd-c623-4d19-af76-f752b95ea81e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639952558 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1639952558
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.474742088
Short name T85
Test name
Test status
Simulation time 25280534 ps
CPU time 0.62 seconds
Started Aug 10 05:23:41 PM PDT 24
Finished Aug 10 05:23:42 PM PDT 24
Peak memory 182896 kb
Host smart-a056f806-f188-4715-bbcb-94d60c87e75b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474742088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.474742088
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2660720872
Short name T553
Test name
Test status
Simulation time 82302116 ps
CPU time 0.6 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:29 PM PDT 24
Peak memory 179628 kb
Host smart-c981bb1a-341c-4e42-af33-91b569405a79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660720872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2660720872
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.122990389
Short name T526
Test name
Test status
Simulation time 18024812 ps
CPU time 0.75 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:29 PM PDT 24
Peak memory 190576 kb
Host smart-3979a88b-a659-48db-b777-5d5d7db994fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122990389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.122990389
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2921418307
Short name T545
Test name
Test status
Simulation time 562732302 ps
CPU time 2.4 seconds
Started Aug 10 05:23:41 PM PDT 24
Finished Aug 10 05:23:44 PM PDT 24
Peak memory 197648 kb
Host smart-e417d896-abf4-4d33-aba3-bd0b2054d504
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921418307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2921418307
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1725140152
Short name T97
Test name
Test status
Simulation time 88436480 ps
CPU time 1.06 seconds
Started Aug 10 05:23:34 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 195184 kb
Host smart-af213d66-02a1-4fa3-9ca3-a567a711839e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725140152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1725140152
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.891342284
Short name T465
Test name
Test status
Simulation time 281913272 ps
CPU time 0.82 seconds
Started Aug 10 05:23:35 PM PDT 24
Finished Aug 10 05:23:36 PM PDT 24
Peak memory 196624 kb
Host smart-de7530a5-cf0b-401c-b340-60f85ace51bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891342284 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.891342284
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.324545317
Short name T94
Test name
Test status
Simulation time 12404296 ps
CPU time 0.54 seconds
Started Aug 10 05:24:59 PM PDT 24
Finished Aug 10 05:24:59 PM PDT 24
Peak memory 182684 kb
Host smart-1f1e183e-5fbb-4fff-b757-090c20c1e42e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324545317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.324545317
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.920466500
Short name T495
Test name
Test status
Simulation time 161471594 ps
CPU time 0.6 seconds
Started Aug 10 05:23:41 PM PDT 24
Finished Aug 10 05:23:42 PM PDT 24
Peak memory 182688 kb
Host smart-782dc855-b5ce-4df7-a4c3-a2c16c042fa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920466500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.920466500
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2084621529
Short name T92
Test name
Test status
Simulation time 57720118 ps
CPU time 0.8 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:29 PM PDT 24
Peak memory 190728 kb
Host smart-37c5eb85-0aa1-4e6a-9c36-302ee10b008d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084621529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2084621529
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.794985129
Short name T470
Test name
Test status
Simulation time 162428098 ps
CPU time 2.01 seconds
Started Aug 10 05:23:36 PM PDT 24
Finished Aug 10 05:23:38 PM PDT 24
Peak memory 191236 kb
Host smart-a0de8bc1-f4d4-47f7-b98d-9f2606d3d4b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794985129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.794985129
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3998554842
Short name T98
Test name
Test status
Simulation time 187251582 ps
CPU time 1.04 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:29 PM PDT 24
Peak memory 194908 kb
Host smart-b53c5b10-5136-47a1-a6f6-4c2c7e9ff423
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998554842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3998554842
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2400370781
Short name T371
Test name
Test status
Simulation time 20228278358 ps
CPU time 14.95 seconds
Started Aug 10 06:04:19 PM PDT 24
Finished Aug 10 06:04:34 PM PDT 24
Peak memory 183464 kb
Host smart-2513478a-c4b1-4c81-b903-7c6b6c94193b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400370781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2400370781
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2986377900
Short name T70
Test name
Test status
Simulation time 445918249 ps
CPU time 0.72 seconds
Started Aug 10 06:04:20 PM PDT 24
Finished Aug 10 06:04:20 PM PDT 24
Peak memory 183160 kb
Host smart-0c695d8a-c87c-4f47-8f82-250d6a906ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986377900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2986377900
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.376136750
Short name T407
Test name
Test status
Simulation time 188859931164 ps
CPU time 147.92 seconds
Started Aug 10 06:04:25 PM PDT 24
Finished Aug 10 06:06:53 PM PDT 24
Peak memory 183416 kb
Host smart-5dd0434b-f862-4f4d-8f9e-a6673ae2d39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376136750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.376136750
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.587201125
Short name T401
Test name
Test status
Simulation time 53365687 ps
CPU time 0.54 seconds
Started Aug 10 06:04:35 PM PDT 24
Finished Aug 10 06:04:36 PM PDT 24
Peak memory 183016 kb
Host smart-b7fa5d10-d8ef-49c8-926a-427198191f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587201125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.587201125
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3318900236
Short name T22
Test name
Test status
Simulation time 66781241 ps
CPU time 0.8 seconds
Started Aug 10 06:04:25 PM PDT 24
Finished Aug 10 06:04:26 PM PDT 24
Peak memory 214052 kb
Host smart-859052cc-b168-4e2e-87b4-163e90f0f5f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318900236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3318900236
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.3706152377
Short name T95
Test name
Test status
Simulation time 19382199573 ps
CPU time 126.74 seconds
Started Aug 10 06:04:26 PM PDT 24
Finished Aug 10 06:06:32 PM PDT 24
Peak memory 198064 kb
Host smart-b857be87-5384-490f-b7f0-b2a6f015430d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706152377 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.3706152377
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2156819503
Short name T442
Test name
Test status
Simulation time 178018659317 ps
CPU time 272.02 seconds
Started Aug 10 06:04:36 PM PDT 24
Finished Aug 10 06:09:08 PM PDT 24
Peak memory 183472 kb
Host smart-1f7b93a7-886a-4726-a0ca-7f403a3d0ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156819503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2156819503
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1029864185
Short name T215
Test name
Test status
Simulation time 128636116299 ps
CPU time 737.01 seconds
Started Aug 10 06:04:36 PM PDT 24
Finished Aug 10 06:16:53 PM PDT 24
Peak memory 191680 kb
Host smart-1dd64570-b30e-4dc7-bf72-5d53212c7e7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029864185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1029864185
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2854649182
Short name T239
Test name
Test status
Simulation time 78477721438 ps
CPU time 716.12 seconds
Started Aug 10 06:04:37 PM PDT 24
Finished Aug 10 06:16:33 PM PDT 24
Peak memory 191672 kb
Host smart-8927e501-424b-4a97-95d1-bc886dda687c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854649182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2854649182
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1193914349
Short name T105
Test name
Test status
Simulation time 504346475708 ps
CPU time 700.54 seconds
Started Aug 10 06:04:43 PM PDT 24
Finished Aug 10 06:16:24 PM PDT 24
Peak memory 191604 kb
Host smart-92350908-6972-4796-84f7-1725aab803d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193914349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1193914349
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.798580519
Short name T75
Test name
Test status
Simulation time 152684599813 ps
CPU time 230.03 seconds
Started Aug 10 06:07:17 PM PDT 24
Finished Aug 10 06:11:07 PM PDT 24
Peak memory 191576 kb
Host smart-184b1494-2ee7-4167-98d2-a3f3d223cb15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798580519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.798580519
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.870684069
Short name T405
Test name
Test status
Simulation time 23818710303 ps
CPU time 19.81 seconds
Started Aug 10 06:07:19 PM PDT 24
Finished Aug 10 06:07:39 PM PDT 24
Peak memory 183428 kb
Host smart-dd5d4ed9-6192-40aa-9514-0140e0696214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870684069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.870684069
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3268778106
Short name T188
Test name
Test status
Simulation time 667350302866 ps
CPU time 411.88 seconds
Started Aug 10 06:07:20 PM PDT 24
Finished Aug 10 06:14:12 PM PDT 24
Peak memory 194952 kb
Host smart-bd06fec3-2ef8-4e4d-b39b-4e26b7f1d7e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268778106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3268778106
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1428504169
Short name T398
Test name
Test status
Simulation time 5317030358 ps
CPU time 5.95 seconds
Started Aug 10 06:07:18 PM PDT 24
Finished Aug 10 06:07:24 PM PDT 24
Peak memory 183392 kb
Host smart-a1568052-fad2-4e37-a23c-f3874dec3bf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428504169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1428504169
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.450045547
Short name T58
Test name
Test status
Simulation time 155164401896 ps
CPU time 120.2 seconds
Started Aug 10 06:04:42 PM PDT 24
Finished Aug 10 06:06:42 PM PDT 24
Peak memory 183476 kb
Host smart-9a148863-ad34-45dd-a23d-1a239fdad4f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450045547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.450045547
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1729509230
Short name T416
Test name
Test status
Simulation time 41326539756 ps
CPU time 455.57 seconds
Started Aug 10 06:04:46 PM PDT 24
Finished Aug 10 06:12:21 PM PDT 24
Peak memory 183456 kb
Host smart-d1817e4d-33be-4b25-91cb-b458afbdf115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729509230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1729509230
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.375907500
Short name T328
Test name
Test status
Simulation time 159515353950 ps
CPU time 769.31 seconds
Started Aug 10 06:04:43 PM PDT 24
Finished Aug 10 06:17:33 PM PDT 24
Peak memory 191636 kb
Host smart-401c0a6a-5899-4302-875e-2ac235ea35d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375907500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.375907500
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.4266686464
Short name T296
Test name
Test status
Simulation time 103848857440 ps
CPU time 262.8 seconds
Started Aug 10 06:07:18 PM PDT 24
Finished Aug 10 06:11:41 PM PDT 24
Peak memory 191644 kb
Host smart-b4174a08-7508-47e0-a564-cddad127ebd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266686464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.4266686464
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2064560722
Short name T12
Test name
Test status
Simulation time 334549176467 ps
CPU time 448.53 seconds
Started Aug 10 06:07:25 PM PDT 24
Finished Aug 10 06:14:54 PM PDT 24
Peak memory 191632 kb
Host smart-f0ca7c8f-279b-434c-977e-f72300e4db19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064560722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2064560722
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3846328864
Short name T413
Test name
Test status
Simulation time 37805174855 ps
CPU time 46.8 seconds
Started Aug 10 06:04:43 PM PDT 24
Finished Aug 10 06:05:30 PM PDT 24
Peak memory 183448 kb
Host smart-244fb33e-1356-494e-8363-b609468e0a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846328864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3846328864
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2662387874
Short name T46
Test name
Test status
Simulation time 4700052644 ps
CPU time 5.95 seconds
Started Aug 10 06:04:43 PM PDT 24
Finished Aug 10 06:04:49 PM PDT 24
Peak memory 183308 kb
Host smart-0fba1671-39a6-4b9c-9309-b3673c2e9bad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662387874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2662387874
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2869310631
Short name T327
Test name
Test status
Simulation time 775384586037 ps
CPU time 263.27 seconds
Started Aug 10 06:04:45 PM PDT 24
Finished Aug 10 06:09:09 PM PDT 24
Peak memory 191644 kb
Host smart-8af916a1-1413-402b-afa4-d6208d431422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869310631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2869310631
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2296409098
Short name T443
Test name
Test status
Simulation time 183766497490 ps
CPU time 143.16 seconds
Started Aug 10 06:04:43 PM PDT 24
Finished Aug 10 06:07:06 PM PDT 24
Peak memory 183432 kb
Host smart-b3c43079-efea-4703-9fd3-57f9dcf46dbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296409098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2296409098
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.342365857
Short name T214
Test name
Test status
Simulation time 291511892192 ps
CPU time 143.62 seconds
Started Aug 10 06:07:26 PM PDT 24
Finished Aug 10 06:09:49 PM PDT 24
Peak memory 191636 kb
Host smart-5526d271-f054-444d-9ccc-2f4e2302855a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342365857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.342365857
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3092059040
Short name T115
Test name
Test status
Simulation time 139798464374 ps
CPU time 244.81 seconds
Started Aug 10 06:07:27 PM PDT 24
Finished Aug 10 06:11:32 PM PDT 24
Peak memory 191604 kb
Host smart-e0127a51-9b5b-4416-b9fa-830000719d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092059040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3092059040
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.882663545
Short name T5
Test name
Test status
Simulation time 131437165786 ps
CPU time 135.72 seconds
Started Aug 10 06:07:34 PM PDT 24
Finished Aug 10 06:09:49 PM PDT 24
Peak memory 191688 kb
Host smart-d0da6683-ddbb-432c-b17c-e70b0c160e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882663545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.882663545
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.4094920366
Short name T404
Test name
Test status
Simulation time 193347345003 ps
CPU time 555.24 seconds
Started Aug 10 06:07:35 PM PDT 24
Finished Aug 10 06:16:51 PM PDT 24
Peak memory 183428 kb
Host smart-e8f51b56-1b0e-43db-9495-555dbc31f7a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094920366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.4094920366
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2989462563
Short name T339
Test name
Test status
Simulation time 33469831058 ps
CPU time 15.9 seconds
Started Aug 10 06:07:32 PM PDT 24
Finished Aug 10 06:07:48 PM PDT 24
Peak memory 183512 kb
Host smart-dd354e2c-1f17-404d-9c2d-9f4112a34677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989462563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2989462563
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3413443011
Short name T56
Test name
Test status
Simulation time 11087490962 ps
CPU time 5.62 seconds
Started Aug 10 06:04:44 PM PDT 24
Finished Aug 10 06:04:49 PM PDT 24
Peak memory 183352 kb
Host smart-e104b7d8-6d99-4258-804a-59594b18361f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413443011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3413443011
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.517465404
Short name T2
Test name
Test status
Simulation time 66525164652 ps
CPU time 100.82 seconds
Started Aug 10 06:04:42 PM PDT 24
Finished Aug 10 06:06:23 PM PDT 24
Peak memory 183420 kb
Host smart-ae993f14-1f32-4958-a0e6-f956a427e315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517465404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.517465404
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.300942438
Short name T157
Test name
Test status
Simulation time 109056773129 ps
CPU time 454.85 seconds
Started Aug 10 06:04:47 PM PDT 24
Finished Aug 10 06:12:22 PM PDT 24
Peak memory 191648 kb
Host smart-70170b9f-f5b7-456f-ae2c-4ef074beaff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300942438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.300942438
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2584077592
Short name T441
Test name
Test status
Simulation time 24660379182 ps
CPU time 30.07 seconds
Started Aug 10 06:04:46 PM PDT 24
Finished Aug 10 06:05:16 PM PDT 24
Peak memory 194780 kb
Host smart-1b1d2377-598a-4d50-9c5f-8ef221e2040c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584077592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2584077592
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.133414541
Short name T244
Test name
Test status
Simulation time 50935038147 ps
CPU time 405.29 seconds
Started Aug 10 06:07:34 PM PDT 24
Finished Aug 10 06:14:20 PM PDT 24
Peak memory 191628 kb
Host smart-99bad5a8-1a1b-4396-beec-5c767ee4c893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133414541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.133414541
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3298898096
Short name T350
Test name
Test status
Simulation time 855578636967 ps
CPU time 769.36 seconds
Started Aug 10 06:07:37 PM PDT 24
Finished Aug 10 06:20:26 PM PDT 24
Peak memory 191544 kb
Host smart-622b3742-e8e1-4b68-8078-82991dabaf9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298898096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3298898096
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3343469039
Short name T246
Test name
Test status
Simulation time 172882573465 ps
CPU time 555.92 seconds
Started Aug 10 06:07:37 PM PDT 24
Finished Aug 10 06:16:53 PM PDT 24
Peak memory 191544 kb
Host smart-39696c86-1a1e-4dc2-9020-0d68e716ecaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343469039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3343469039
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.401403077
Short name T290
Test name
Test status
Simulation time 203106495933 ps
CPU time 400.33 seconds
Started Aug 10 06:07:34 PM PDT 24
Finished Aug 10 06:14:14 PM PDT 24
Peak memory 191660 kb
Host smart-2f59a42d-3db6-4702-b34e-1fca60c5b788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401403077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.401403077
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1187724884
Short name T420
Test name
Test status
Simulation time 30010921945 ps
CPU time 46.51 seconds
Started Aug 10 06:07:37 PM PDT 24
Finished Aug 10 06:08:23 PM PDT 24
Peak memory 183484 kb
Host smart-7caf8fcb-b1c1-47ae-a637-60bccf6e02ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187724884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1187724884
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2931065388
Short name T135
Test name
Test status
Simulation time 424656650699 ps
CPU time 335.97 seconds
Started Aug 10 06:04:42 PM PDT 24
Finished Aug 10 06:10:18 PM PDT 24
Peak memory 183460 kb
Host smart-33e42099-80b0-4381-89bf-d529b5c024dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931065388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2931065388
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.87197662
Short name T367
Test name
Test status
Simulation time 591854133657 ps
CPU time 293.8 seconds
Started Aug 10 06:04:45 PM PDT 24
Finished Aug 10 06:09:39 PM PDT 24
Peak memory 183444 kb
Host smart-8223bc40-7713-4a0e-96c5-543d13e8ad33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87197662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.87197662
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2497376158
Short name T131
Test name
Test status
Simulation time 276032492632 ps
CPU time 905.99 seconds
Started Aug 10 06:04:51 PM PDT 24
Finished Aug 10 06:19:57 PM PDT 24
Peak memory 191604 kb
Host smart-0c907d7c-93e1-496e-a0c1-5512e5541562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497376158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2497376158
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.331805907
Short name T47
Test name
Test status
Simulation time 18016622159 ps
CPU time 23.91 seconds
Started Aug 10 06:07:32 PM PDT 24
Finished Aug 10 06:07:56 PM PDT 24
Peak memory 183512 kb
Host smart-d913ef29-428d-492b-8cb2-340eb40bda60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331805907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.331805907
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3124192935
Short name T154
Test name
Test status
Simulation time 1407367449072 ps
CPU time 1746.86 seconds
Started Aug 10 06:07:42 PM PDT 24
Finished Aug 10 06:36:49 PM PDT 24
Peak memory 191832 kb
Host smart-f2580553-c9ad-4dda-974a-e94dc7f2474d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124192935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3124192935
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3956723763
Short name T162
Test name
Test status
Simulation time 110760817390 ps
CPU time 219.75 seconds
Started Aug 10 06:07:43 PM PDT 24
Finished Aug 10 06:11:23 PM PDT 24
Peak memory 191756 kb
Host smart-490795a0-51dc-41da-baba-9e365ea8571d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956723763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3956723763
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2453033433
Short name T415
Test name
Test status
Simulation time 74886605160 ps
CPU time 1745.71 seconds
Started Aug 10 06:07:44 PM PDT 24
Finished Aug 10 06:36:50 PM PDT 24
Peak memory 191756 kb
Host smart-734645a1-58a3-4b93-bcfd-c97f4a2b52de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453033433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2453033433
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2220231783
Short name T51
Test name
Test status
Simulation time 629128819554 ps
CPU time 284 seconds
Started Aug 10 06:07:42 PM PDT 24
Finished Aug 10 06:12:27 PM PDT 24
Peak memory 191648 kb
Host smart-e0046a9c-628f-45d6-aa7d-05e914dd02ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220231783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2220231783
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.169480913
Short name T74
Test name
Test status
Simulation time 45950407318 ps
CPU time 79.91 seconds
Started Aug 10 06:07:41 PM PDT 24
Finished Aug 10 06:09:01 PM PDT 24
Peak memory 183412 kb
Host smart-ace47c18-804c-4f4d-a265-9bd45d25c3de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169480913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.169480913
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1459334607
Short name T243
Test name
Test status
Simulation time 150861354062 ps
CPU time 74.05 seconds
Started Aug 10 06:07:44 PM PDT 24
Finished Aug 10 06:08:58 PM PDT 24
Peak memory 194988 kb
Host smart-e6797bbf-7c3f-493c-8bc3-c1df36c96fab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459334607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1459334607
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3446379570
Short name T326
Test name
Test status
Simulation time 70939948678 ps
CPU time 126.74 seconds
Started Aug 10 06:07:42 PM PDT 24
Finished Aug 10 06:09:49 PM PDT 24
Peak memory 191716 kb
Host smart-e0fa4108-928a-4bda-bcc1-6abf94288197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446379570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3446379570
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3382257883
Short name T414
Test name
Test status
Simulation time 1343409812482 ps
CPU time 699.9 seconds
Started Aug 10 06:04:51 PM PDT 24
Finished Aug 10 06:16:31 PM PDT 24
Peak memory 183448 kb
Host smart-3be945d6-9cbc-449c-9196-6d0661286da9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382257883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3382257883
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2426451602
Short name T3
Test name
Test status
Simulation time 368818550965 ps
CPU time 156.66 seconds
Started Aug 10 06:04:50 PM PDT 24
Finished Aug 10 06:07:27 PM PDT 24
Peak memory 183448 kb
Host smart-e1b72c6a-7cff-4716-bbba-b869c5f29126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426451602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2426451602
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2775047615
Short name T233
Test name
Test status
Simulation time 73160080964 ps
CPU time 1593.53 seconds
Started Aug 10 06:04:51 PM PDT 24
Finished Aug 10 06:31:25 PM PDT 24
Peak memory 191716 kb
Host smart-a962d0ce-4dc0-41d1-9f3e-66cc3b7a3833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775047615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2775047615
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2655155863
Short name T426
Test name
Test status
Simulation time 1511959585 ps
CPU time 0.81 seconds
Started Aug 10 06:04:51 PM PDT 24
Finished Aug 10 06:04:52 PM PDT 24
Peak memory 183228 kb
Host smart-0b0ceda3-0115-46fb-8dac-e239fb7adcdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655155863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2655155863
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.79434992
Short name T49
Test name
Test status
Simulation time 5418470521 ps
CPU time 8.75 seconds
Started Aug 10 06:04:50 PM PDT 24
Finished Aug 10 06:04:59 PM PDT 24
Peak memory 183428 kb
Host smart-7d7f657a-067a-4fc5-a34d-77e698eb2b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79434992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.79434992
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.3668830567
Short name T323
Test name
Test status
Simulation time 1057000512747 ps
CPU time 819.93 seconds
Started Aug 10 06:07:42 PM PDT 24
Finished Aug 10 06:21:23 PM PDT 24
Peak memory 193688 kb
Host smart-9530dc64-690a-477a-a2c2-4e273003103c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668830567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3668830567
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2706766424
Short name T352
Test name
Test status
Simulation time 561254449109 ps
CPU time 249.42 seconds
Started Aug 10 06:07:41 PM PDT 24
Finished Aug 10 06:11:50 PM PDT 24
Peak memory 191636 kb
Host smart-65f4ff9a-341a-46f0-a7e9-f2d11b846196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706766424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2706766424
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3286595288
Short name T44
Test name
Test status
Simulation time 716616149852 ps
CPU time 360.28 seconds
Started Aug 10 06:07:41 PM PDT 24
Finished Aug 10 06:13:42 PM PDT 24
Peak memory 191584 kb
Host smart-b17b86bc-ecb9-44d8-ae2c-dd618beed6df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286595288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3286595288
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.855366240
Short name T287
Test name
Test status
Simulation time 79585499835 ps
CPU time 126.03 seconds
Started Aug 10 06:07:42 PM PDT 24
Finished Aug 10 06:09:48 PM PDT 24
Peak memory 191648 kb
Host smart-14bc02b5-1fd6-4367-8944-691aafc3a369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855366240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.855366240
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1711434246
Short name T111
Test name
Test status
Simulation time 150279330705 ps
CPU time 389.89 seconds
Started Aug 10 06:07:44 PM PDT 24
Finished Aug 10 06:14:14 PM PDT 24
Peak memory 191684 kb
Host smart-98d9fdc1-fc81-42a3-beaf-0eac2b795c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711434246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1711434246
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1670580312
Short name T121
Test name
Test status
Simulation time 1293107059156 ps
CPU time 3464.12 seconds
Started Aug 10 06:07:48 PM PDT 24
Finished Aug 10 07:05:32 PM PDT 24
Peak memory 191524 kb
Host smart-01127767-c467-40d5-bf0e-3d349a3a3695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670580312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1670580312
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2728051661
Short name T345
Test name
Test status
Simulation time 193490782235 ps
CPU time 104.58 seconds
Started Aug 10 06:07:49 PM PDT 24
Finished Aug 10 06:09:33 PM PDT 24
Peak memory 191660 kb
Host smart-bc752676-05f8-4f84-834e-62e993825de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728051661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2728051661
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2371318970
Short name T185
Test name
Test status
Simulation time 387898692482 ps
CPU time 202.08 seconds
Started Aug 10 06:04:52 PM PDT 24
Finished Aug 10 06:08:14 PM PDT 24
Peak memory 183452 kb
Host smart-0831f634-82fc-4e89-b669-9c301ee50acd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371318970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2371318970
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1659683173
Short name T431
Test name
Test status
Simulation time 660218690800 ps
CPU time 170.33 seconds
Started Aug 10 06:04:52 PM PDT 24
Finished Aug 10 06:07:43 PM PDT 24
Peak memory 183428 kb
Host smart-eb4f69df-33e4-42d1-a58c-7abf473bb401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659683173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1659683173
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.380657024
Short name T216
Test name
Test status
Simulation time 41432152860 ps
CPU time 18.96 seconds
Started Aug 10 06:04:52 PM PDT 24
Finished Aug 10 06:05:11 PM PDT 24
Peak memory 183480 kb
Host smart-90f62e79-c939-4724-a9ac-60676a667fb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380657024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.380657024
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.765981440
Short name T38
Test name
Test status
Simulation time 16902642068 ps
CPU time 175.9 seconds
Started Aug 10 06:04:53 PM PDT 24
Finished Aug 10 06:07:49 PM PDT 24
Peak memory 198164 kb
Host smart-8c67ea1c-8e2f-4245-8374-66ee6c35ea20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765981440 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.765981440
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.14926231
Short name T447
Test name
Test status
Simulation time 57481839720 ps
CPU time 1421.97 seconds
Started Aug 10 06:07:50 PM PDT 24
Finished Aug 10 06:31:33 PM PDT 24
Peak memory 192776 kb
Host smart-51c5de3d-de71-4778-a84b-0010903ba75e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14926231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.14926231
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.433383989
Short name T334
Test name
Test status
Simulation time 412466985903 ps
CPU time 429.74 seconds
Started Aug 10 06:07:49 PM PDT 24
Finished Aug 10 06:14:58 PM PDT 24
Peak memory 191664 kb
Host smart-31cc3a42-67ab-4b3f-b988-5d62bfb1af6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433383989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.433383989
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3717484019
Short name T295
Test name
Test status
Simulation time 48838442044 ps
CPU time 67.47 seconds
Started Aug 10 06:07:58 PM PDT 24
Finished Aug 10 06:09:05 PM PDT 24
Peak memory 191620 kb
Host smart-f2c88c84-b542-435d-8cbf-70156fabcfbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717484019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3717484019
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.4082518449
Short name T129
Test name
Test status
Simulation time 30114770882 ps
CPU time 46.29 seconds
Started Aug 10 06:07:56 PM PDT 24
Finished Aug 10 06:08:42 PM PDT 24
Peak memory 183492 kb
Host smart-c183421a-b828-40cc-8c34-dba9ed69bf45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082518449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.4082518449
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2111971068
Short name T320
Test name
Test status
Simulation time 842635440885 ps
CPU time 269.98 seconds
Started Aug 10 06:07:58 PM PDT 24
Finished Aug 10 06:12:28 PM PDT 24
Peak memory 191632 kb
Host smart-fe69e44d-f2c8-431d-a08b-3b42b02b4213
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111971068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2111971068
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2228065839
Short name T193
Test name
Test status
Simulation time 61153348146 ps
CPU time 45.85 seconds
Started Aug 10 06:07:56 PM PDT 24
Finished Aug 10 06:08:42 PM PDT 24
Peak memory 191612 kb
Host smart-d2c71f62-c175-46bf-9f7c-d8ef288c7881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228065839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2228065839
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.54199305
Short name T279
Test name
Test status
Simulation time 304697733136 ps
CPU time 237.1 seconds
Started Aug 10 06:07:56 PM PDT 24
Finished Aug 10 06:11:53 PM PDT 24
Peak memory 191680 kb
Host smart-f9a054b6-e90c-43f6-a6bc-291094ea9a01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54199305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.54199305
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3722012326
Short name T336
Test name
Test status
Simulation time 532054498701 ps
CPU time 240.62 seconds
Started Aug 10 06:07:58 PM PDT 24
Finished Aug 10 06:11:59 PM PDT 24
Peak memory 191632 kb
Host smart-742c157d-0fce-40ea-8368-081e73b24f22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722012326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3722012326
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.2632241705
Short name T446
Test name
Test status
Simulation time 302391270303 ps
CPU time 247.75 seconds
Started Aug 10 06:04:52 PM PDT 24
Finished Aug 10 06:09:00 PM PDT 24
Peak memory 183472 kb
Host smart-1ccf47f8-80c5-4ac8-8b39-401e1341f57c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632241705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.2632241705
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.947608847
Short name T408
Test name
Test status
Simulation time 77568921828 ps
CPU time 101.23 seconds
Started Aug 10 06:04:52 PM PDT 24
Finished Aug 10 06:06:33 PM PDT 24
Peak memory 183460 kb
Host smart-299b254e-00bb-4422-bf92-72c639785e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947608847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.947608847
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.4124400056
Short name T130
Test name
Test status
Simulation time 115251724063 ps
CPU time 426.31 seconds
Started Aug 10 06:04:52 PM PDT 24
Finished Aug 10 06:11:59 PM PDT 24
Peak memory 191688 kb
Host smart-31541856-4c8a-4f0e-8a67-3dd115c9c269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124400056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.4124400056
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2919540781
Short name T24
Test name
Test status
Simulation time 436047561217 ps
CPU time 163.91 seconds
Started Aug 10 06:04:53 PM PDT 24
Finished Aug 10 06:07:37 PM PDT 24
Peak memory 194844 kb
Host smart-d1cecc94-129e-4015-acfc-69ddd18b8b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919540781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2919540781
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.242264014
Short name T165
Test name
Test status
Simulation time 1105971597925 ps
CPU time 329.11 seconds
Started Aug 10 06:07:56 PM PDT 24
Finished Aug 10 06:13:26 PM PDT 24
Peak memory 191668 kb
Host smart-bfa8e791-342a-4c8d-8df7-97af5c00f8e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242264014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.242264014
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1115065926
Short name T380
Test name
Test status
Simulation time 19750194941 ps
CPU time 31.17 seconds
Started Aug 10 06:07:58 PM PDT 24
Finished Aug 10 06:08:29 PM PDT 24
Peak memory 183488 kb
Host smart-6eba2aea-3a4e-4dd7-9a30-56386d0c2411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115065926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1115065926
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1482509768
Short name T331
Test name
Test status
Simulation time 626573650287 ps
CPU time 462.56 seconds
Started Aug 10 06:07:56 PM PDT 24
Finished Aug 10 06:15:39 PM PDT 24
Peak memory 191692 kb
Host smart-a2b9ea24-cfdd-4f88-aef8-94d07e556c49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482509768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1482509768
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3382326061
Short name T236
Test name
Test status
Simulation time 207841785503 ps
CPU time 36.87 seconds
Started Aug 10 06:07:56 PM PDT 24
Finished Aug 10 06:08:33 PM PDT 24
Peak memory 183464 kb
Host smart-bdbfbb61-8c13-4e02-935e-8ed314fa9030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382326061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3382326061
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3606049781
Short name T57
Test name
Test status
Simulation time 44883063294 ps
CPU time 76.97 seconds
Started Aug 10 06:07:57 PM PDT 24
Finished Aug 10 06:09:14 PM PDT 24
Peak memory 183480 kb
Host smart-93cf9ce4-6c22-4e0f-9441-c3bd1d16e7e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606049781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3606049781
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1471885291
Short name T172
Test name
Test status
Simulation time 77509878972 ps
CPU time 174.21 seconds
Started Aug 10 06:07:57 PM PDT 24
Finished Aug 10 06:10:51 PM PDT 24
Peak memory 191672 kb
Host smart-cb3d9897-ca69-46c2-84c8-93a95fe6c085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471885291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1471885291
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.724620872
Short name T155
Test name
Test status
Simulation time 265066243132 ps
CPU time 738.34 seconds
Started Aug 10 06:07:57 PM PDT 24
Finished Aug 10 06:20:15 PM PDT 24
Peak memory 191704 kb
Host smart-64d87104-acef-4e95-b6cc-b16097a2b917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724620872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.724620872
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.13409252
Short name T228
Test name
Test status
Simulation time 467910291984 ps
CPU time 1086.31 seconds
Started Aug 10 06:07:57 PM PDT 24
Finished Aug 10 06:26:03 PM PDT 24
Peak memory 191648 kb
Host smart-f5ff82b4-bd4b-4830-b03d-cee3217607a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13409252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.13409252
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3214353872
Short name T387
Test name
Test status
Simulation time 95920861235 ps
CPU time 1778.66 seconds
Started Aug 10 06:08:04 PM PDT 24
Finished Aug 10 06:37:43 PM PDT 24
Peak memory 183464 kb
Host smart-40859127-3de4-4fc2-9936-433e09e587ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214353872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3214353872
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3018331229
Short name T335
Test name
Test status
Simulation time 332197256021 ps
CPU time 1482.57 seconds
Started Aug 10 06:08:05 PM PDT 24
Finished Aug 10 06:32:48 PM PDT 24
Peak memory 191708 kb
Host smart-b9aac1eb-bf09-4cfb-a696-d8e3e61bf6c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018331229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3018331229
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3090992624
Short name T262
Test name
Test status
Simulation time 949304213440 ps
CPU time 490.78 seconds
Started Aug 10 06:05:04 PM PDT 24
Finished Aug 10 06:13:15 PM PDT 24
Peak memory 183492 kb
Host smart-5a56b83e-7d34-40d4-994f-2fc8bbaf32da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090992624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3090992624
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.44264418
Short name T373
Test name
Test status
Simulation time 16417020072 ps
CPU time 6.72 seconds
Started Aug 10 06:05:03 PM PDT 24
Finished Aug 10 06:05:09 PM PDT 24
Peak memory 183484 kb
Host smart-f0f74a8e-4759-4015-be09-adf6f4cedd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44264418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.44264418
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.824795150
Short name T197
Test name
Test status
Simulation time 718632961026 ps
CPU time 1044.66 seconds
Started Aug 10 06:04:53 PM PDT 24
Finished Aug 10 06:22:18 PM PDT 24
Peak memory 194228 kb
Host smart-54891910-5dc1-4571-8037-a54f458681b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824795150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.824795150
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3673660738
Short name T207
Test name
Test status
Simulation time 163384793149 ps
CPU time 84.12 seconds
Started Aug 10 06:05:03 PM PDT 24
Finished Aug 10 06:06:27 PM PDT 24
Peak memory 191584 kb
Host smart-63a45450-f542-461f-b92b-3277a9148395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673660738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3673660738
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.4043079468
Short name T388
Test name
Test status
Simulation time 18154796 ps
CPU time 0.56 seconds
Started Aug 10 06:05:04 PM PDT 24
Finished Aug 10 06:05:05 PM PDT 24
Peak memory 183212 kb
Host smart-9487e17e-c3d8-44fa-8568-84f27baf4be0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043079468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.4043079468
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.686299132
Short name T16
Test name
Test status
Simulation time 53383643297 ps
CPU time 591.13 seconds
Started Aug 10 06:05:06 PM PDT 24
Finished Aug 10 06:14:58 PM PDT 24
Peak memory 206368 kb
Host smart-9c5dbcd4-45ac-488b-b470-96f37792c0df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686299132 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.686299132
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.3889086523
Short name T418
Test name
Test status
Simulation time 144779661527 ps
CPU time 1197.76 seconds
Started Aug 10 06:08:04 PM PDT 24
Finished Aug 10 06:28:02 PM PDT 24
Peak memory 191712 kb
Host smart-96d5dbe5-ef43-4d84-bc85-a9ea01ba1550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889086523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3889086523
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.390787414
Short name T289
Test name
Test status
Simulation time 90463389905 ps
CPU time 181.97 seconds
Started Aug 10 06:08:06 PM PDT 24
Finished Aug 10 06:11:08 PM PDT 24
Peak memory 191680 kb
Host smart-c400ebea-4bc3-4189-b130-bddcdeac8122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390787414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.390787414
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.39529760
Short name T174
Test name
Test status
Simulation time 164023618024 ps
CPU time 122.76 seconds
Started Aug 10 06:08:06 PM PDT 24
Finished Aug 10 06:10:09 PM PDT 24
Peak memory 191660 kb
Host smart-86367972-9ce5-4738-b4ed-01d644bb2eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39529760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.39529760
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3500978417
Short name T211
Test name
Test status
Simulation time 72638628831 ps
CPU time 186.86 seconds
Started Aug 10 06:08:04 PM PDT 24
Finished Aug 10 06:11:11 PM PDT 24
Peak memory 191600 kb
Host smart-151e0beb-e7a4-44a0-8c27-7796c2621785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500978417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3500978417
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.92022694
Short name T259
Test name
Test status
Simulation time 50218867602 ps
CPU time 81.39 seconds
Started Aug 10 06:08:03 PM PDT 24
Finished Aug 10 06:09:25 PM PDT 24
Peak memory 191664 kb
Host smart-635a8378-0cab-431c-9fd5-85daa9f3db71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92022694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.92022694
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2626827356
Short name T281
Test name
Test status
Simulation time 23602322488 ps
CPU time 34.16 seconds
Started Aug 10 06:08:05 PM PDT 24
Finished Aug 10 06:08:39 PM PDT 24
Peak memory 183244 kb
Host smart-39041d8e-65f1-469d-81df-e528bb7b753b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626827356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2626827356
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2618116059
Short name T227
Test name
Test status
Simulation time 11021002207 ps
CPU time 16.63 seconds
Started Aug 10 06:05:06 PM PDT 24
Finished Aug 10 06:05:22 PM PDT 24
Peak memory 183476 kb
Host smart-46addf40-4bc2-46ca-bffd-c470f4dbca58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618116059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2618116059
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1732299551
Short name T395
Test name
Test status
Simulation time 10062249999 ps
CPU time 4.39 seconds
Started Aug 10 06:05:05 PM PDT 24
Finished Aug 10 06:05:10 PM PDT 24
Peak memory 183232 kb
Host smart-440d8a7f-2559-458b-b632-13cd9794eb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732299551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1732299551
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.211388212
Short name T226
Test name
Test status
Simulation time 362612235826 ps
CPU time 1200.06 seconds
Started Aug 10 06:05:05 PM PDT 24
Finished Aug 10 06:25:05 PM PDT 24
Peak memory 191628 kb
Host smart-80033357-ab40-4a7d-928c-b4c420754608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211388212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.211388212
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2102427487
Short name T128
Test name
Test status
Simulation time 103459970908 ps
CPU time 341.68 seconds
Started Aug 10 06:05:06 PM PDT 24
Finished Aug 10 06:10:48 PM PDT 24
Peak memory 183456 kb
Host smart-f0c87b37-15e3-4709-b2da-8d6b7ce79ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102427487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2102427487
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.4071536156
Short name T43
Test name
Test status
Simulation time 17008581586 ps
CPU time 125.72 seconds
Started Aug 10 06:05:05 PM PDT 24
Finished Aug 10 06:07:11 PM PDT 24
Peak memory 196996 kb
Host smart-41a0d9e9-899b-4840-97b7-39a880062a7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071536156 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.4071536156
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.2695175971
Short name T71
Test name
Test status
Simulation time 113529864563 ps
CPU time 1235.17 seconds
Started Aug 10 06:08:04 PM PDT 24
Finished Aug 10 06:28:39 PM PDT 24
Peak memory 194460 kb
Host smart-0dac4d2e-5c34-4353-98e9-ae459ce9ec01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695175971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2695175971
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.4078351220
Short name T117
Test name
Test status
Simulation time 247416649090 ps
CPU time 86.86 seconds
Started Aug 10 06:08:03 PM PDT 24
Finished Aug 10 06:09:30 PM PDT 24
Peak memory 183464 kb
Host smart-c5962a20-0c74-4179-8a88-d05c94d09100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078351220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.4078351220
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.675559210
Short name T318
Test name
Test status
Simulation time 736659204723 ps
CPU time 635.77 seconds
Started Aug 10 06:08:06 PM PDT 24
Finished Aug 10 06:18:42 PM PDT 24
Peak memory 191648 kb
Host smart-0c710a6f-31ca-4a81-ba6f-11a9ff062d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675559210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.675559210
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2062708617
Short name T430
Test name
Test status
Simulation time 166574624401 ps
CPU time 144.86 seconds
Started Aug 10 06:08:14 PM PDT 24
Finished Aug 10 06:10:39 PM PDT 24
Peak memory 195196 kb
Host smart-a1fe55e2-9738-495e-a26d-041db6e93e42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062708617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2062708617
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1301360252
Short name T73
Test name
Test status
Simulation time 88155584466 ps
CPU time 162.65 seconds
Started Aug 10 06:08:14 PM PDT 24
Finished Aug 10 06:10:56 PM PDT 24
Peak memory 191640 kb
Host smart-213a59a1-fab5-4223-bf7b-d11803c01d9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301360252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1301360252
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.283695897
Short name T29
Test name
Test status
Simulation time 272060489661 ps
CPU time 530.34 seconds
Started Aug 10 06:08:13 PM PDT 24
Finished Aug 10 06:17:04 PM PDT 24
Peak memory 183488 kb
Host smart-5f8a1458-6360-4c89-8ae6-75fbb1b9235c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283695897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.283695897
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2586191853
Short name T192
Test name
Test status
Simulation time 486529266159 ps
CPU time 471.5 seconds
Started Aug 10 06:08:12 PM PDT 24
Finished Aug 10 06:16:03 PM PDT 24
Peak memory 191616 kb
Host smart-2025ef9b-09a9-4a98-a9fb-e16a47273580
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586191853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2586191853
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3526328326
Short name T297
Test name
Test status
Simulation time 832126532111 ps
CPU time 956.54 seconds
Started Aug 10 06:08:13 PM PDT 24
Finished Aug 10 06:24:10 PM PDT 24
Peak memory 191676 kb
Host smart-9216e29f-9fd7-42a1-90cf-9bdb04d06d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526328326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3526328326
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2063679295
Short name T245
Test name
Test status
Simulation time 478776175651 ps
CPU time 173.38 seconds
Started Aug 10 06:04:24 PM PDT 24
Finished Aug 10 06:07:18 PM PDT 24
Peak memory 183468 kb
Host smart-e275193f-b6f2-494d-bf69-52d608b6faaf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063679295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2063679295
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1701968442
Short name T411
Test name
Test status
Simulation time 135716266492 ps
CPU time 90.62 seconds
Started Aug 10 06:04:25 PM PDT 24
Finished Aug 10 06:05:56 PM PDT 24
Peak memory 183484 kb
Host smart-1f5feed2-dedb-4f5e-bf37-ed1d2d4463b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701968442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1701968442
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3928116262
Short name T160
Test name
Test status
Simulation time 32679422358 ps
CPU time 58.48 seconds
Started Aug 10 06:04:37 PM PDT 24
Finished Aug 10 06:05:36 PM PDT 24
Peak memory 191460 kb
Host smart-24adf987-ea5e-42b0-9b17-a8a0c0739fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928116262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3928116262
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3437979945
Short name T18
Test name
Test status
Simulation time 91518205 ps
CPU time 0.88 seconds
Started Aug 10 06:04:26 PM PDT 24
Finished Aug 10 06:04:27 PM PDT 24
Peak memory 215024 kb
Host smart-23063a37-d34c-4d61-930a-10c891b3b454
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437979945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3437979945
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3709063198
Short name T392
Test name
Test status
Simulation time 65591030 ps
CPU time 0.54 seconds
Started Aug 10 06:04:36 PM PDT 24
Finished Aug 10 06:04:37 PM PDT 24
Peak memory 183020 kb
Host smart-4d8f3e5f-707a-441d-9cf8-34169d46c84d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709063198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3709063198
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2177942232
Short name T361
Test name
Test status
Simulation time 197984378190 ps
CPU time 144.78 seconds
Started Aug 10 06:05:03 PM PDT 24
Finished Aug 10 06:07:28 PM PDT 24
Peak memory 183436 kb
Host smart-571e80af-a4be-4932-91e5-d29f53abbf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177942232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2177942232
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1583284426
Short name T300
Test name
Test status
Simulation time 69882107613 ps
CPU time 139.82 seconds
Started Aug 10 06:05:04 PM PDT 24
Finished Aug 10 06:07:24 PM PDT 24
Peak memory 191628 kb
Host smart-3f4d1e90-96ff-4833-8f02-181874506420
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583284426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1583284426
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2544696456
Short name T342
Test name
Test status
Simulation time 528925813223 ps
CPU time 275.64 seconds
Started Aug 10 06:05:05 PM PDT 24
Finished Aug 10 06:09:41 PM PDT 24
Peak memory 191596 kb
Host smart-ece2b26f-3257-4850-bfad-55fd9da9f553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544696456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2544696456
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3109614110
Short name T41
Test name
Test status
Simulation time 21223520454 ps
CPU time 103.49 seconds
Started Aug 10 06:05:05 PM PDT 24
Finished Aug 10 06:06:49 PM PDT 24
Peak memory 195968 kb
Host smart-a70935a0-c705-4be4-954c-2eefa1284ebd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109614110 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3109614110
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3987341055
Short name T292
Test name
Test status
Simulation time 93864523610 ps
CPU time 81.6 seconds
Started Aug 10 06:05:04 PM PDT 24
Finished Aug 10 06:06:25 PM PDT 24
Peak memory 183468 kb
Host smart-cf9233b5-2e18-4d7a-a024-a93c463edd1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987341055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3987341055
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.835495858
Short name T444
Test name
Test status
Simulation time 206441721416 ps
CPU time 88.93 seconds
Started Aug 10 06:05:03 PM PDT 24
Finished Aug 10 06:06:32 PM PDT 24
Peak memory 183464 kb
Host smart-085a54fc-706c-41de-8ae5-fb56a00416d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835495858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.835495858
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3215277246
Short name T48
Test name
Test status
Simulation time 868279714 ps
CPU time 0.65 seconds
Started Aug 10 06:05:04 PM PDT 24
Finished Aug 10 06:05:04 PM PDT 24
Peak memory 183136 kb
Host smart-88285ec3-06aa-4e6a-b7c0-13ed8900faac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215277246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3215277246
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2202975385
Short name T368
Test name
Test status
Simulation time 301998002 ps
CPU time 0.76 seconds
Started Aug 10 06:05:03 PM PDT 24
Finished Aug 10 06:05:04 PM PDT 24
Peak memory 183144 kb
Host smart-9839c9d8-edd2-4f4c-8b94-5bc04943dce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202975385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2202975385
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3295482594
Short name T280
Test name
Test status
Simulation time 277191467050 ps
CPU time 382.16 seconds
Started Aug 10 06:05:06 PM PDT 24
Finished Aug 10 06:11:28 PM PDT 24
Peak memory 183456 kb
Host smart-874c93c8-0082-4f67-bcea-4fd9a56fc9c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295482594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3295482594
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.315073614
Short name T403
Test name
Test status
Simulation time 663051735766 ps
CPU time 247.03 seconds
Started Aug 10 06:05:07 PM PDT 24
Finished Aug 10 06:09:14 PM PDT 24
Peak memory 183460 kb
Host smart-aa4276b7-f5e3-4cb0-8c6b-d2e7f7d9b569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315073614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.315073614
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3325392874
Short name T285
Test name
Test status
Simulation time 165581571345 ps
CPU time 167.77 seconds
Started Aug 10 06:05:03 PM PDT 24
Finished Aug 10 06:07:51 PM PDT 24
Peak memory 191656 kb
Host smart-373b6068-59d3-4d9f-b8b8-f2183b6c32bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325392874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3325392874
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.729985892
Short name T72
Test name
Test status
Simulation time 164081618601 ps
CPU time 407.49 seconds
Started Aug 10 06:05:03 PM PDT 24
Finished Aug 10 06:11:51 PM PDT 24
Peak memory 183412 kb
Host smart-fb52c71e-12bd-467a-ade8-cf92e0ea85c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729985892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.729985892
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1090938927
Short name T64
Test name
Test status
Simulation time 18076593 ps
CPU time 0.56 seconds
Started Aug 10 06:05:03 PM PDT 24
Finished Aug 10 06:05:04 PM PDT 24
Peak memory 183088 kb
Host smart-0efdc5e3-0451-4a94-8309-358159ac0976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090938927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1090938927
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3531414280
Short name T210
Test name
Test status
Simulation time 62373502464 ps
CPU time 98.8 seconds
Started Aug 10 06:05:13 PM PDT 24
Finished Aug 10 06:06:52 PM PDT 24
Peak memory 183448 kb
Host smart-a17d0df0-3c9a-4b0d-b2ca-7da066e8860a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531414280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3531414280
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1560323488
Short name T394
Test name
Test status
Simulation time 366248464054 ps
CPU time 143.04 seconds
Started Aug 10 06:05:23 PM PDT 24
Finished Aug 10 06:07:46 PM PDT 24
Peak memory 183460 kb
Host smart-ee3023d0-2767-4930-97b6-e5be538ddfa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560323488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1560323488
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2462624194
Short name T340
Test name
Test status
Simulation time 22996178906 ps
CPU time 13.14 seconds
Started Aug 10 06:05:15 PM PDT 24
Finished Aug 10 06:05:28 PM PDT 24
Peak memory 183420 kb
Host smart-6aa63c03-e398-4be7-a2ed-a81c68f2b3d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462624194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2462624194
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2175269069
Short name T277
Test name
Test status
Simulation time 32452808381 ps
CPU time 165.04 seconds
Started Aug 10 06:05:13 PM PDT 24
Finished Aug 10 06:07:58 PM PDT 24
Peak memory 183632 kb
Host smart-e1c995bd-40ce-4019-b9eb-b93a33ac22d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175269069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2175269069
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.562196984
Short name T30
Test name
Test status
Simulation time 493436579499 ps
CPU time 237.57 seconds
Started Aug 10 06:05:13 PM PDT 24
Finished Aug 10 06:09:10 PM PDT 24
Peak memory 183464 kb
Host smart-5513c50d-f501-4311-8185-19943517e794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562196984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
562196984
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2356134254
Short name T39
Test name
Test status
Simulation time 107240597439 ps
CPU time 740.91 seconds
Started Aug 10 06:05:13 PM PDT 24
Finished Aug 10 06:17:34 PM PDT 24
Peak memory 206384 kb
Host smart-39e6110a-aa84-49ad-8e33-6660e952594e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356134254 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2356134254
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2802510316
Short name T402
Test name
Test status
Simulation time 98516733757 ps
CPU time 41.46 seconds
Started Aug 10 06:05:21 PM PDT 24
Finished Aug 10 06:06:02 PM PDT 24
Peak memory 183460 kb
Host smart-4c0f32e7-dd59-443b-82bd-61775127cdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802510316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2802510316
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1665171643
Short name T241
Test name
Test status
Simulation time 1346555943222 ps
CPU time 1376.67 seconds
Started Aug 10 06:05:14 PM PDT 24
Finished Aug 10 06:28:11 PM PDT 24
Peak memory 191672 kb
Host smart-6caa1d61-396f-400f-8a0e-84f6ccc58e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665171643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1665171643
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.378123284
Short name T337
Test name
Test status
Simulation time 19079445179 ps
CPU time 125.39 seconds
Started Aug 10 06:05:16 PM PDT 24
Finished Aug 10 06:07:22 PM PDT 24
Peak memory 191656 kb
Host smart-f98a34af-66e7-447a-8829-603805329f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378123284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.378123284
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2943492637
Short name T112
Test name
Test status
Simulation time 119909751289 ps
CPU time 1487.1 seconds
Started Aug 10 06:05:16 PM PDT 24
Finished Aug 10 06:30:03 PM PDT 24
Peak memory 191464 kb
Host smart-f6d7494b-e0e3-40ee-a35f-b342ebfb6ac8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943492637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2943492637
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2883353483
Short name T222
Test name
Test status
Simulation time 133909793129 ps
CPU time 66.83 seconds
Started Aug 10 06:05:23 PM PDT 24
Finished Aug 10 06:06:30 PM PDT 24
Peak memory 183464 kb
Host smart-0c6dc1e7-73bf-4d9b-bc0a-df111bff5e02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883353483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2883353483
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.139925254
Short name T375
Test name
Test status
Simulation time 90153224133 ps
CPU time 133.14 seconds
Started Aug 10 06:05:12 PM PDT 24
Finished Aug 10 06:07:26 PM PDT 24
Peak memory 183444 kb
Host smart-3b78ea29-6316-42ed-a9d0-bdf14fb33cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139925254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.139925254
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2205206379
Short name T177
Test name
Test status
Simulation time 144617482058 ps
CPU time 487.89 seconds
Started Aug 10 06:05:14 PM PDT 24
Finished Aug 10 06:13:22 PM PDT 24
Peak memory 191668 kb
Host smart-c249913e-543b-4d8f-8c1c-33e3226f55a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205206379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2205206379
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3260235313
Short name T183
Test name
Test status
Simulation time 412346558975 ps
CPU time 476.25 seconds
Started Aug 10 06:05:13 PM PDT 24
Finished Aug 10 06:13:09 PM PDT 24
Peak memory 183484 kb
Host smart-26c2312c-bb0d-45eb-9ed8-841bd241116c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260235313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3260235313
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.816770080
Short name T25
Test name
Test status
Simulation time 364193833570 ps
CPU time 448.76 seconds
Started Aug 10 06:05:17 PM PDT 24
Finished Aug 10 06:12:46 PM PDT 24
Peak memory 191460 kb
Host smart-f3ca9618-a34e-4eb1-ace4-0641a3b71bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816770080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
816770080
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3073477943
Short name T347
Test name
Test status
Simulation time 164971341143 ps
CPU time 144.15 seconds
Started Aug 10 06:05:16 PM PDT 24
Finished Aug 10 06:07:41 PM PDT 24
Peak memory 183456 kb
Host smart-f9657998-443d-401b-97f5-9d2ac31c8cf7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073477943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3073477943
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3027798754
Short name T406
Test name
Test status
Simulation time 310414295704 ps
CPU time 258.05 seconds
Started Aug 10 06:05:13 PM PDT 24
Finished Aug 10 06:09:31 PM PDT 24
Peak memory 183476 kb
Host smart-7b82ee82-c123-45f7-b578-baad8eb26d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027798754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3027798754
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3611950561
Short name T409
Test name
Test status
Simulation time 77912671501 ps
CPU time 29.27 seconds
Started Aug 10 06:05:13 PM PDT 24
Finished Aug 10 06:05:43 PM PDT 24
Peak memory 183400 kb
Host smart-1335483e-5234-4041-82c0-46a7e0ad2d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611950561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3611950561
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2086675235
Short name T4
Test name
Test status
Simulation time 681883592238 ps
CPU time 292.02 seconds
Started Aug 10 06:05:27 PM PDT 24
Finished Aug 10 06:10:19 PM PDT 24
Peak memory 191660 kb
Host smart-e72f9bdd-03da-4403-9682-7ed28a742c48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086675235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2086675235
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.461248611
Short name T410
Test name
Test status
Simulation time 254289095375 ps
CPU time 117.89 seconds
Started Aug 10 06:05:22 PM PDT 24
Finished Aug 10 06:07:20 PM PDT 24
Peak memory 183416 kb
Host smart-6e129a4b-123d-4dd2-bb15-37affe37442e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461248611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.461248611
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2381164097
Short name T6
Test name
Test status
Simulation time 123650025220 ps
CPU time 190.8 seconds
Started Aug 10 06:05:26 PM PDT 24
Finished Aug 10 06:08:37 PM PDT 24
Peak memory 183460 kb
Host smart-a62d2bb1-f5f5-4e06-8c27-3a1ff47489e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381164097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2381164097
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1768260729
Short name T343
Test name
Test status
Simulation time 201089630635 ps
CPU time 721.62 seconds
Started Aug 10 06:05:20 PM PDT 24
Finished Aug 10 06:17:22 PM PDT 24
Peak memory 191664 kb
Host smart-4c88e16b-49b9-4890-8c3a-aec161df3abb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768260729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1768260729
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3712175662
Short name T362
Test name
Test status
Simulation time 63195295 ps
CPU time 0.61 seconds
Started Aug 10 06:05:27 PM PDT 24
Finished Aug 10 06:05:27 PM PDT 24
Peak memory 183212 kb
Host smart-b751d7c8-0dda-4a6f-9ebc-a99e62369b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712175662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3712175662
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.479383527
Short name T256
Test name
Test status
Simulation time 1107054671264 ps
CPU time 685.5 seconds
Started Aug 10 06:05:21 PM PDT 24
Finished Aug 10 06:16:47 PM PDT 24
Peak memory 191672 kb
Host smart-2e5f0297-0bee-435d-b900-3c64319fc85e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479383527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
479383527
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.642313241
Short name T132
Test name
Test status
Simulation time 11323275235 ps
CPU time 20.27 seconds
Started Aug 10 06:05:27 PM PDT 24
Finished Aug 10 06:05:48 PM PDT 24
Peak memory 183468 kb
Host smart-0775afb2-172b-4804-8284-43b833204839
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642313241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.642313241
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_random.813061808
Short name T137
Test name
Test status
Simulation time 114635412573 ps
CPU time 172.28 seconds
Started Aug 10 06:05:22 PM PDT 24
Finished Aug 10 06:08:14 PM PDT 24
Peak memory 191716 kb
Host smart-b09dec61-dde8-4468-b28f-4f6f837f556a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813061808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.813061808
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3899092122
Short name T114
Test name
Test status
Simulation time 469857914330 ps
CPU time 154.15 seconds
Started Aug 10 06:05:23 PM PDT 24
Finished Aug 10 06:07:57 PM PDT 24
Peak memory 191672 kb
Host smart-890d7c9a-9953-4ab3-b577-7cf969164161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899092122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3899092122
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.434670710
Short name T365
Test name
Test status
Simulation time 95095664601 ps
CPU time 36.32 seconds
Started Aug 10 06:05:22 PM PDT 24
Finished Aug 10 06:05:59 PM PDT 24
Peak memory 195116 kb
Host smart-0b34ea2e-9562-4747-a1fe-e112a59b2077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434670710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
434670710
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1929434432
Short name T163
Test name
Test status
Simulation time 296144373301 ps
CPU time 445.28 seconds
Started Aug 10 06:05:20 PM PDT 24
Finished Aug 10 06:12:46 PM PDT 24
Peak memory 183460 kb
Host smart-0d820b95-8575-4d1d-bcda-8e65998f9669
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929434432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1929434432
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3572460577
Short name T366
Test name
Test status
Simulation time 159568436345 ps
CPU time 217.94 seconds
Started Aug 10 06:05:21 PM PDT 24
Finished Aug 10 06:08:59 PM PDT 24
Peak memory 183332 kb
Host smart-b5feafa4-2591-432f-bf50-89331bf29ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572460577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3572460577
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3415069679
Short name T254
Test name
Test status
Simulation time 1183929408725 ps
CPU time 935.01 seconds
Started Aug 10 06:05:21 PM PDT 24
Finished Aug 10 06:20:57 PM PDT 24
Peak memory 191672 kb
Host smart-b7639cae-a4f4-4340-a185-7b6b51f595b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415069679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3415069679
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1823803388
Short name T344
Test name
Test status
Simulation time 42484408289 ps
CPU time 207.37 seconds
Started Aug 10 06:05:26 PM PDT 24
Finished Aug 10 06:08:53 PM PDT 24
Peak memory 191648 kb
Host smart-313b6f00-a922-48ad-9d66-186e688d8765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823803388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1823803388
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2103886279
Short name T393
Test name
Test status
Simulation time 149246901472 ps
CPU time 214.4 seconds
Started Aug 10 06:04:25 PM PDT 24
Finished Aug 10 06:08:00 PM PDT 24
Peak memory 183456 kb
Host smart-1cad6255-bd1b-4f43-b5b9-513b6d75b019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103886279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2103886279
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.221252290
Short name T353
Test name
Test status
Simulation time 63034301757 ps
CPU time 109.31 seconds
Started Aug 10 06:04:26 PM PDT 24
Finished Aug 10 06:06:15 PM PDT 24
Peak memory 191612 kb
Host smart-e147b062-c8be-4bf5-954b-443f785fc334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221252290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.221252290
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.814924471
Short name T378
Test name
Test status
Simulation time 115425708 ps
CPU time 3.86 seconds
Started Aug 10 06:04:28 PM PDT 24
Finished Aug 10 06:04:32 PM PDT 24
Peak memory 192012 kb
Host smart-1991c98f-840f-4adb-859f-6cb1ca729de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814924471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.814924471
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.919674756
Short name T20
Test name
Test status
Simulation time 117483142 ps
CPU time 0.83 seconds
Started Aug 10 06:04:26 PM PDT 24
Finished Aug 10 06:04:27 PM PDT 24
Peak memory 214064 kb
Host smart-8b6fb02c-48da-4267-9a8f-df0499cab25a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919674756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.919674756
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.604758414
Short name T400
Test name
Test status
Simulation time 365322975216 ps
CPU time 136.55 seconds
Started Aug 10 06:04:37 PM PDT 24
Finished Aug 10 06:06:54 PM PDT 24
Peak memory 194440 kb
Host smart-9f6d8a10-7462-4180-a0ac-6cb989b4ce8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604758414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.604758414
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.3558279994
Short name T42
Test name
Test status
Simulation time 113487771720 ps
CPU time 169.5 seconds
Started Aug 10 06:04:26 PM PDT 24
Finished Aug 10 06:07:16 PM PDT 24
Peak memory 206284 kb
Host smart-98804cd2-95a6-4e54-8fa9-a2c8617d4249
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558279994 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.3558279994
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1480755172
Short name T134
Test name
Test status
Simulation time 53917126467 ps
CPU time 20.89 seconds
Started Aug 10 06:05:30 PM PDT 24
Finished Aug 10 06:05:51 PM PDT 24
Peak memory 183488 kb
Host smart-f24f437b-66c9-4eb7-9147-dcd7ce613dca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480755172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1480755172
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_random.486217950
Short name T247
Test name
Test status
Simulation time 360294696485 ps
CPU time 479.37 seconds
Started Aug 10 06:05:30 PM PDT 24
Finished Aug 10 06:13:30 PM PDT 24
Peak memory 194676 kb
Host smart-1da93e40-b5e6-436e-9706-e86080ca74ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486217950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.486217950
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3961230394
Short name T448
Test name
Test status
Simulation time 13481988173 ps
CPU time 11.46 seconds
Started Aug 10 06:05:33 PM PDT 24
Finished Aug 10 06:05:45 PM PDT 24
Peak memory 195096 kb
Host smart-12d6a999-811c-47e3-a941-b052f392290a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961230394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3961230394
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2497638782
Short name T232
Test name
Test status
Simulation time 14852285935 ps
CPU time 23.13 seconds
Started Aug 10 06:05:30 PM PDT 24
Finished Aug 10 06:05:54 PM PDT 24
Peak memory 194668 kb
Host smart-4ab0704e-1788-42ed-8eb1-201a22b05d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497638782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2497638782
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1165182630
Short name T275
Test name
Test status
Simulation time 526749142935 ps
CPU time 457.2 seconds
Started Aug 10 06:05:30 PM PDT 24
Finished Aug 10 06:13:07 PM PDT 24
Peak memory 183488 kb
Host smart-fe222608-be08-4a49-b0a7-615a913d3182
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165182630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1165182630
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1741724943
Short name T435
Test name
Test status
Simulation time 311418659028 ps
CPU time 107.33 seconds
Started Aug 10 06:05:30 PM PDT 24
Finished Aug 10 06:07:17 PM PDT 24
Peak memory 183456 kb
Host smart-8ddeccc5-04bd-4022-a3be-91f9b88836fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741724943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1741724943
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.4156904682
Short name T432
Test name
Test status
Simulation time 46784022471 ps
CPU time 209.27 seconds
Started Aug 10 06:05:30 PM PDT 24
Finished Aug 10 06:09:00 PM PDT 24
Peak memory 183404 kb
Host smart-aec60603-6bc3-4ed6-aebe-461d30f78a06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156904682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.4156904682
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.957261479
Short name T364
Test name
Test status
Simulation time 2800466429 ps
CPU time 18.74 seconds
Started Aug 10 06:05:31 PM PDT 24
Finished Aug 10 06:05:50 PM PDT 24
Peak memory 183392 kb
Host smart-21a7793a-3a5e-4686-870e-b054be85f4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957261479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.957261479
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1790705946
Short name T313
Test name
Test status
Simulation time 328723793991 ps
CPU time 449.18 seconds
Started Aug 10 06:05:33 PM PDT 24
Finished Aug 10 06:13:02 PM PDT 24
Peak memory 194912 kb
Host smart-4403d988-5c76-41f2-bd6a-62a1f40d1597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790705946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1790705946
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3733964742
Short name T396
Test name
Test status
Simulation time 701844699693 ps
CPU time 292.28 seconds
Started Aug 10 06:05:40 PM PDT 24
Finished Aug 10 06:10:32 PM PDT 24
Peak memory 183472 kb
Host smart-b1ebf405-e24c-4398-b603-7d04c8943509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733964742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3733964742
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.4267330039
Short name T176
Test name
Test status
Simulation time 304204709186 ps
CPU time 439.03 seconds
Started Aug 10 06:05:30 PM PDT 24
Finished Aug 10 06:12:50 PM PDT 24
Peak memory 191672 kb
Host smart-cf32dc2b-467d-450a-b3ba-212546646b1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267330039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4267330039
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.759295253
Short name T374
Test name
Test status
Simulation time 897386591 ps
CPU time 0.67 seconds
Started Aug 10 06:05:37 PM PDT 24
Finished Aug 10 06:05:38 PM PDT 24
Peak memory 183092 kb
Host smart-39d8e731-e1a3-4dfd-9f68-4ad087cbdd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759295253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.759295253
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3980112233
Short name T66
Test name
Test status
Simulation time 2915525057264 ps
CPU time 420.53 seconds
Started Aug 10 06:05:39 PM PDT 24
Finished Aug 10 06:12:40 PM PDT 24
Peak memory 195312 kb
Host smart-25282034-dee7-49ee-822e-9582e9d88519
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980112233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3980112233
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3828443792
Short name T324
Test name
Test status
Simulation time 246714668924 ps
CPU time 127.04 seconds
Started Aug 10 06:05:47 PM PDT 24
Finished Aug 10 06:07:54 PM PDT 24
Peak memory 183432 kb
Host smart-ad9275b6-5d8e-4946-a758-5233a5e55c21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828443792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3828443792
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2196610719
Short name T370
Test name
Test status
Simulation time 104839088648 ps
CPU time 148.81 seconds
Started Aug 10 06:05:48 PM PDT 24
Finished Aug 10 06:08:17 PM PDT 24
Peak memory 183444 kb
Host smart-5ff7a20b-dba0-4307-a51f-3778bdba10ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196610719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2196610719
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1401718552
Short name T106
Test name
Test status
Simulation time 2007305381360 ps
CPU time 894.28 seconds
Started Aug 10 06:05:40 PM PDT 24
Finished Aug 10 06:20:34 PM PDT 24
Peak memory 191688 kb
Host smart-8fe179bc-2ab3-449d-b7da-5b2f2c7baa99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401718552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1401718552
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2375761066
Short name T412
Test name
Test status
Simulation time 37609498 ps
CPU time 0.51 seconds
Started Aug 10 06:05:46 PM PDT 24
Finished Aug 10 06:05:47 PM PDT 24
Peak memory 183232 kb
Host smart-9a1beb45-fb93-401f-9e49-59814b5d5ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375761066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2375761066
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3646051943
Short name T311
Test name
Test status
Simulation time 1368942157329 ps
CPU time 660.42 seconds
Started Aug 10 06:05:47 PM PDT 24
Finished Aug 10 06:16:47 PM PDT 24
Peak memory 183484 kb
Host smart-4a72a055-7bfe-4479-95ff-2a7436a5c7a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646051943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3646051943
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3777127023
Short name T363
Test name
Test status
Simulation time 119757976810 ps
CPU time 154.61 seconds
Started Aug 10 06:05:47 PM PDT 24
Finished Aug 10 06:08:22 PM PDT 24
Peak memory 183436 kb
Host smart-2e39162e-1a26-43c4-b2d7-5b877249bd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777127023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3777127023
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.344008953
Short name T417
Test name
Test status
Simulation time 49712741429 ps
CPU time 114.92 seconds
Started Aug 10 06:05:47 PM PDT 24
Finished Aug 10 06:07:42 PM PDT 24
Peak memory 183408 kb
Host smart-0828063e-d93d-4d3e-8c00-16d61347641e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344008953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.344008953
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2660272759
Short name T338
Test name
Test status
Simulation time 136890255592 ps
CPU time 240.65 seconds
Started Aug 10 06:05:46 PM PDT 24
Finished Aug 10 06:09:46 PM PDT 24
Peak memory 183396 kb
Host smart-b910d5e9-a4e9-4be8-b73f-f32526e0b93f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660272759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2660272759
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2280400477
Short name T419
Test name
Test status
Simulation time 13710432030 ps
CPU time 14.09 seconds
Started Aug 10 06:05:47 PM PDT 24
Finished Aug 10 06:06:01 PM PDT 24
Peak memory 183460 kb
Host smart-6f295465-db44-4b04-86af-40a3af247682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280400477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2280400477
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3894428557
Short name T333
Test name
Test status
Simulation time 133272103973 ps
CPU time 421.33 seconds
Started Aug 10 06:05:47 PM PDT 24
Finished Aug 10 06:12:49 PM PDT 24
Peak memory 191716 kb
Host smart-73e03d4a-97a3-4be9-913a-7036ed6de0ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894428557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3894428557
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.525100238
Short name T437
Test name
Test status
Simulation time 225253296143 ps
CPU time 105.78 seconds
Started Aug 10 06:05:46 PM PDT 24
Finished Aug 10 06:07:32 PM PDT 24
Peak memory 192256 kb
Host smart-4220dc0b-78ef-4698-bbe9-215814f93260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525100238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.525100238
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.1511157863
Short name T28
Test name
Test status
Simulation time 113183333663 ps
CPU time 428.61 seconds
Started Aug 10 06:05:48 PM PDT 24
Finished Aug 10 06:12:56 PM PDT 24
Peak memory 206300 kb
Host smart-4d64f216-54bf-4703-a5a6-b06c1bc681ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511157863 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.1511157863
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.992363518
Short name T317
Test name
Test status
Simulation time 6158345851 ps
CPU time 11.35 seconds
Started Aug 10 06:05:58 PM PDT 24
Finished Aug 10 06:06:09 PM PDT 24
Peak memory 183416 kb
Host smart-72244f2e-0ce6-45f6-8358-da3cccb2c57b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992363518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.992363518
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.304194532
Short name T376
Test name
Test status
Simulation time 105745235126 ps
CPU time 138.38 seconds
Started Aug 10 06:05:49 PM PDT 24
Finished Aug 10 06:08:07 PM PDT 24
Peak memory 183444 kb
Host smart-51a5ba57-a92e-436d-9a0c-5507acff97fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304194532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.304194532
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.4133705980
Short name T7
Test name
Test status
Simulation time 49322498329 ps
CPU time 293.27 seconds
Started Aug 10 06:05:47 PM PDT 24
Finished Aug 10 06:10:41 PM PDT 24
Peak memory 191624 kb
Host smart-e39f3e7e-fae2-4ab2-a730-61c04c303af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133705980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.4133705980
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3064942303
Short name T391
Test name
Test status
Simulation time 326997151 ps
CPU time 0.64 seconds
Started Aug 10 06:05:58 PM PDT 24
Finished Aug 10 06:05:59 PM PDT 24
Peak memory 183236 kb
Host smart-d78caa8a-a0ce-495e-831f-c79e711b7df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064942303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3064942303
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2820384648
Short name T113
Test name
Test status
Simulation time 1479633347760 ps
CPU time 858.45 seconds
Started Aug 10 06:05:54 PM PDT 24
Finished Aug 10 06:20:13 PM PDT 24
Peak memory 183464 kb
Host smart-2222793f-0c66-4c04-90d1-e3bc2250743d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820384648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2820384648
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.4012627067
Short name T386
Test name
Test status
Simulation time 289415167625 ps
CPU time 121.66 seconds
Started Aug 10 06:05:55 PM PDT 24
Finished Aug 10 06:07:57 PM PDT 24
Peak memory 183324 kb
Host smart-54e176c5-6e74-4fde-9adf-dfecb55f0204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012627067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.4012627067
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1017522344
Short name T202
Test name
Test status
Simulation time 172429005405 ps
CPU time 149.04 seconds
Started Aug 10 06:05:57 PM PDT 24
Finished Aug 10 06:08:26 PM PDT 24
Peak memory 191676 kb
Host smart-e9cb9f69-0860-4c23-9d74-552a62dcda4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017522344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1017522344
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1735784843
Short name T136
Test name
Test status
Simulation time 151004548322 ps
CPU time 90.28 seconds
Started Aug 10 06:05:55 PM PDT 24
Finished Aug 10 06:07:25 PM PDT 24
Peak memory 194940 kb
Host smart-2c4770dd-ec55-4de1-a8c8-7a5d4ead8e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735784843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1735784843
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.2810176975
Short name T54
Test name
Test status
Simulation time 72279178568 ps
CPU time 487.22 seconds
Started Aug 10 06:05:58 PM PDT 24
Finished Aug 10 06:14:05 PM PDT 24
Peak memory 206324 kb
Host smart-a3071ccf-d40d-4284-868c-8ca8d0e30edb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810176975 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.2810176975
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3228782626
Short name T255
Test name
Test status
Simulation time 1502559324666 ps
CPU time 793.32 seconds
Started Aug 10 06:05:57 PM PDT 24
Finished Aug 10 06:19:10 PM PDT 24
Peak memory 183352 kb
Host smart-acd35fe4-5541-405c-8c5c-69397803500f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228782626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3228782626
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2048929474
Short name T438
Test name
Test status
Simulation time 95784262897 ps
CPU time 41.76 seconds
Started Aug 10 06:05:57 PM PDT 24
Finished Aug 10 06:06:39 PM PDT 24
Peak memory 183416 kb
Host smart-264b6011-22ae-466e-b833-1a210ad66357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048929474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2048929474
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2536183949
Short name T231
Test name
Test status
Simulation time 45273539682 ps
CPU time 82.48 seconds
Started Aug 10 06:05:55 PM PDT 24
Finished Aug 10 06:07:17 PM PDT 24
Peak memory 191620 kb
Host smart-86dd00f6-1479-419b-88d4-eb92205cd349
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536183949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2536183949
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.4236453383
Short name T360
Test name
Test status
Simulation time 1405218273 ps
CPU time 1.21 seconds
Started Aug 10 06:05:58 PM PDT 24
Finished Aug 10 06:06:00 PM PDT 24
Peak memory 183416 kb
Host smart-58b42d40-8592-4f66-a9e7-59821118f62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236453383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.4236453383
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.85764832
Short name T306
Test name
Test status
Simulation time 30174236874 ps
CPU time 53.04 seconds
Started Aug 10 06:06:06 PM PDT 24
Finished Aug 10 06:06:59 PM PDT 24
Peak memory 183484 kb
Host smart-9b56f4e7-5ef8-43c8-9e84-a9b72d5552b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85764832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.rv_timer_cfg_update_on_fly.85764832
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3401327403
Short name T422
Test name
Test status
Simulation time 716907277491 ps
CPU time 223.92 seconds
Started Aug 10 06:06:04 PM PDT 24
Finished Aug 10 06:09:48 PM PDT 24
Peak memory 183412 kb
Host smart-8d59dc8d-24d8-4122-86f0-6acb87d53ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401327403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3401327403
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1624768304
Short name T153
Test name
Test status
Simulation time 617627525271 ps
CPU time 669.8 seconds
Started Aug 10 06:06:06 PM PDT 24
Finished Aug 10 06:17:16 PM PDT 24
Peak memory 191704 kb
Host smart-2afe539e-7174-4f7f-b5f5-1aeaceca6921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624768304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1624768304
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3940273576
Short name T170
Test name
Test status
Simulation time 28631287870 ps
CPU time 35.28 seconds
Started Aug 10 06:06:06 PM PDT 24
Finished Aug 10 06:06:41 PM PDT 24
Peak memory 183400 kb
Host smart-b3319d7c-4c07-48c5-8a5b-9cc91f369e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940273576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3940273576
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2504751613
Short name T397
Test name
Test status
Simulation time 85246743 ps
CPU time 0.52 seconds
Started Aug 10 06:06:04 PM PDT 24
Finished Aug 10 06:06:05 PM PDT 24
Peak memory 182824 kb
Host smart-46a5a542-35ed-474d-b3c8-e303894eeed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504751613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2504751613
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.237546803
Short name T315
Test name
Test status
Simulation time 66892263444 ps
CPU time 95.03 seconds
Started Aug 10 06:04:36 PM PDT 24
Finished Aug 10 06:06:11 PM PDT 24
Peak memory 183480 kb
Host smart-2485a84e-3d9e-47ba-bbce-8ead0f67dda3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237546803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.237546803
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_random.1450037663
Short name T76
Test name
Test status
Simulation time 178254608745 ps
CPU time 222.59 seconds
Started Aug 10 06:04:26 PM PDT 24
Finished Aug 10 06:08:09 PM PDT 24
Peak memory 191560 kb
Host smart-a32e59ac-6263-47f1-832a-bc74e2152176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450037663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1450037663
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.258388833
Short name T284
Test name
Test status
Simulation time 33552965695 ps
CPU time 60.79 seconds
Started Aug 10 06:04:39 PM PDT 24
Finished Aug 10 06:05:40 PM PDT 24
Peak memory 191640 kb
Host smart-6a9aae5c-d0ab-450e-9301-cc6fc2c522a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258388833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.258388833
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3207683433
Short name T21
Test name
Test status
Simulation time 127744636 ps
CPU time 0.75 seconds
Started Aug 10 06:04:37 PM PDT 24
Finished Aug 10 06:04:37 PM PDT 24
Peak memory 214124 kb
Host smart-e2febfcf-5884-4ec7-8794-54f305cc0463
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207683433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3207683433
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2772883224
Short name T235
Test name
Test status
Simulation time 528173192571 ps
CPU time 175.91 seconds
Started Aug 10 06:06:05 PM PDT 24
Finished Aug 10 06:09:02 PM PDT 24
Peak memory 183448 kb
Host smart-e43fbc51-757d-440c-bfe8-05a0a4923a90
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772883224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2772883224
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2535482347
Short name T399
Test name
Test status
Simulation time 7164183637 ps
CPU time 10.88 seconds
Started Aug 10 06:06:07 PM PDT 24
Finished Aug 10 06:06:18 PM PDT 24
Peak memory 183444 kb
Host smart-35aa46a6-fa7c-40c3-9c7d-c5091d516e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535482347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2535482347
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3407681700
Short name T127
Test name
Test status
Simulation time 883300201259 ps
CPU time 2571.86 seconds
Started Aug 10 06:06:06 PM PDT 24
Finished Aug 10 06:48:58 PM PDT 24
Peak memory 191636 kb
Host smart-898cf407-50b7-4e91-b61f-278fa81c7ba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407681700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3407681700
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.685470376
Short name T274
Test name
Test status
Simulation time 52203310428 ps
CPU time 74.16 seconds
Started Aug 10 06:06:06 PM PDT 24
Finished Aug 10 06:07:20 PM PDT 24
Peak memory 183272 kb
Host smart-42dab1d0-e80e-4f82-9e6f-a16b9feba3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685470376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.685470376
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3151645031
Short name T445
Test name
Test status
Simulation time 7587667289 ps
CPU time 59.81 seconds
Started Aug 10 06:06:05 PM PDT 24
Finished Aug 10 06:07:05 PM PDT 24
Peak memory 198128 kb
Host smart-a6508117-b437-4ebf-b887-bc815ad1b9c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151645031 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.3151645031
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1063002525
Short name T257
Test name
Test status
Simulation time 2709728658049 ps
CPU time 727 seconds
Started Aug 10 06:06:06 PM PDT 24
Finished Aug 10 06:18:13 PM PDT 24
Peak memory 183452 kb
Host smart-0f8d0b79-a405-4e8e-8324-affe5ac780bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063002525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1063002525
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.4293781550
Short name T369
Test name
Test status
Simulation time 509318056141 ps
CPU time 181.96 seconds
Started Aug 10 06:06:05 PM PDT 24
Finished Aug 10 06:09:07 PM PDT 24
Peak memory 183436 kb
Host smart-507cc22e-70d5-4760-a7ea-143f3a84af77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293781550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.4293781550
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3507708618
Short name T8
Test name
Test status
Simulation time 37047841061 ps
CPU time 62.16 seconds
Started Aug 10 06:06:04 PM PDT 24
Finished Aug 10 06:07:07 PM PDT 24
Peak memory 191832 kb
Host smart-64e09312-191f-4298-a316-cf808e7988bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507708618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3507708618
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.4158068780
Short name T384
Test name
Test status
Simulation time 436648077 ps
CPU time 0.74 seconds
Started Aug 10 06:06:06 PM PDT 24
Finished Aug 10 06:06:06 PM PDT 24
Peak memory 183192 kb
Host smart-7946b4a2-6f10-4dc5-ba70-598624d6fa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158068780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.4158068780
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2844169296
Short name T171
Test name
Test status
Simulation time 359814486198 ps
CPU time 224.8 seconds
Started Aug 10 06:06:14 PM PDT 24
Finished Aug 10 06:09:59 PM PDT 24
Peak memory 196316 kb
Host smart-b5a9b0ce-d36b-4f54-8e88-f768d3aa339a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844169296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2844169296
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2934969374
Short name T145
Test name
Test status
Simulation time 48138632897 ps
CPU time 23.5 seconds
Started Aug 10 06:06:16 PM PDT 24
Finished Aug 10 06:06:39 PM PDT 24
Peak memory 183428 kb
Host smart-7127351f-3176-45c3-8f6f-3e07baa24b52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934969374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2934969374
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.995446766
Short name T436
Test name
Test status
Simulation time 686531447 ps
CPU time 1.43 seconds
Started Aug 10 06:06:14 PM PDT 24
Finished Aug 10 06:06:16 PM PDT 24
Peak memory 183044 kb
Host smart-1a0d784b-03f3-4e13-a3df-5762c033cd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995446766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.995446766
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2019059703
Short name T168
Test name
Test status
Simulation time 744538985720 ps
CPU time 650.06 seconds
Started Aug 10 06:06:16 PM PDT 24
Finished Aug 10 06:17:06 PM PDT 24
Peak memory 191676 kb
Host smart-51ecabad-bfc7-4333-8c68-bb56a111141a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019059703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2019059703
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1935867124
Short name T152
Test name
Test status
Simulation time 9349989395 ps
CPU time 13.89 seconds
Started Aug 10 06:06:14 PM PDT 24
Finished Aug 10 06:06:28 PM PDT 24
Peak memory 183232 kb
Host smart-47c7e471-9ffc-4710-a9d7-3f4c45c04020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935867124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1935867124
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.22961388
Short name T351
Test name
Test status
Simulation time 20900691305 ps
CPU time 10.78 seconds
Started Aug 10 06:06:13 PM PDT 24
Finished Aug 10 06:06:24 PM PDT 24
Peak memory 183348 kb
Host smart-e2d397c5-8f5b-47c7-b198-f8ac24d1c038
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22961388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.rv_timer_cfg_update_on_fly.22961388
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1969991998
Short name T382
Test name
Test status
Simulation time 403546778348 ps
CPU time 107.78 seconds
Started Aug 10 06:06:15 PM PDT 24
Finished Aug 10 06:08:03 PM PDT 24
Peak memory 183444 kb
Host smart-d7da1485-02f8-4eb7-94d2-638fc6455fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969991998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1969991998
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3212786257
Short name T26
Test name
Test status
Simulation time 54972788598 ps
CPU time 383.84 seconds
Started Aug 10 06:06:14 PM PDT 24
Finished Aug 10 06:12:38 PM PDT 24
Peak memory 191676 kb
Host smart-843d942b-3867-45bf-8f10-d0f8b98f8cdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212786257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3212786257
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2044307437
Short name T358
Test name
Test status
Simulation time 23646962695 ps
CPU time 52.26 seconds
Started Aug 10 06:06:24 PM PDT 24
Finished Aug 10 06:07:16 PM PDT 24
Peak memory 183440 kb
Host smart-7af65a4b-9cff-4e71-9f5f-ff4197525945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044307437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2044307437
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.173608760
Short name T359
Test name
Test status
Simulation time 299303075960 ps
CPU time 462.77 seconds
Started Aug 10 06:06:29 PM PDT 24
Finished Aug 10 06:14:12 PM PDT 24
Peak memory 183496 kb
Host smart-cc06332a-45da-474e-9f70-897d1d1569be
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173608760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.173608760
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2042633975
Short name T390
Test name
Test status
Simulation time 83721432523 ps
CPU time 62.36 seconds
Started Aug 10 06:06:21 PM PDT 24
Finished Aug 10 06:07:23 PM PDT 24
Peak memory 183408 kb
Host smart-3dfb50ff-1c11-442d-861d-74e694dfc486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042633975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2042633975
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.698245263
Short name T303
Test name
Test status
Simulation time 132725359368 ps
CPU time 95.66 seconds
Started Aug 10 06:06:22 PM PDT 24
Finished Aug 10 06:07:58 PM PDT 24
Peak memory 191648 kb
Host smart-8237c70e-ac8d-4ce6-acbc-a6c81f94c588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698245263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.698245263
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2214715672
Short name T146
Test name
Test status
Simulation time 55307580991 ps
CPU time 29.87 seconds
Started Aug 10 06:06:24 PM PDT 24
Finished Aug 10 06:06:54 PM PDT 24
Peak memory 183480 kb
Host smart-2d2fd9d3-7bc0-422a-aee2-b04a9f740120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214715672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2214715672
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2211093701
Short name T69
Test name
Test status
Simulation time 346801910478 ps
CPU time 273.34 seconds
Started Aug 10 06:06:30 PM PDT 24
Finished Aug 10 06:11:03 PM PDT 24
Peak memory 183384 kb
Host smart-cc6124b4-a9e5-466b-9bc7-9d5fa427e588
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211093701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2211093701
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3425026446
Short name T372
Test name
Test status
Simulation time 23829157201 ps
CPU time 9.39 seconds
Started Aug 10 06:06:23 PM PDT 24
Finished Aug 10 06:06:33 PM PDT 24
Peak memory 183440 kb
Host smart-aa0752ad-ebcb-4ea1-af7e-4476e9b43bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425026446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3425026446
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2988992225
Short name T307
Test name
Test status
Simulation time 141986049364 ps
CPU time 1685.3 seconds
Started Aug 10 06:06:22 PM PDT 24
Finished Aug 10 06:34:27 PM PDT 24
Peak memory 191652 kb
Host smart-7b13cca1-5ce3-4bc4-9571-8396eaedc52a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988992225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2988992225
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2507092777
Short name T423
Test name
Test status
Simulation time 59123381369 ps
CPU time 85.2 seconds
Started Aug 10 06:06:44 PM PDT 24
Finished Aug 10 06:08:10 PM PDT 24
Peak memory 191684 kb
Host smart-d27b642a-7468-4387-b2d7-8f8c85a09ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507092777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2507092777
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2410215767
Short name T421
Test name
Test status
Simulation time 194272410200 ps
CPU time 308.09 seconds
Started Aug 10 06:06:44 PM PDT 24
Finished Aug 10 06:11:53 PM PDT 24
Peak memory 191684 kb
Host smart-5cac4032-c1d0-4b9b-ba53-096971050b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410215767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2410215767
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1385607402
Short name T230
Test name
Test status
Simulation time 2818882438909 ps
CPU time 1004.95 seconds
Started Aug 10 06:06:32 PM PDT 24
Finished Aug 10 06:23:17 PM PDT 24
Peak memory 183488 kb
Host smart-828bd44a-9dd6-43f8-8dd0-eec321d72537
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385607402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1385607402
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2860932809
Short name T377
Test name
Test status
Simulation time 210501665667 ps
CPU time 147.22 seconds
Started Aug 10 06:06:30 PM PDT 24
Finished Aug 10 06:08:57 PM PDT 24
Peak memory 183452 kb
Host smart-0a8ee6c6-17a4-4a2d-94d9-2996976d4366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860932809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2860932809
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3090049294
Short name T122
Test name
Test status
Simulation time 118015682292 ps
CPU time 224.98 seconds
Started Aug 10 06:06:31 PM PDT 24
Finished Aug 10 06:10:16 PM PDT 24
Peak memory 191680 kb
Host smart-c75989d2-8f44-4e4a-8333-efb26c1a3e9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090049294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3090049294
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.928598926
Short name T59
Test name
Test status
Simulation time 201968317320 ps
CPU time 74.14 seconds
Started Aug 10 06:06:43 PM PDT 24
Finished Aug 10 06:07:58 PM PDT 24
Peak memory 191700 kb
Host smart-f9319f38-62ad-434f-a812-a4d4aa216cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928598926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.928598926
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.820913018
Short name T288
Test name
Test status
Simulation time 823655261893 ps
CPU time 385.34 seconds
Started Aug 10 06:06:45 PM PDT 24
Finished Aug 10 06:13:11 PM PDT 24
Peak memory 183492 kb
Host smart-d6b82bbf-85d3-45a9-aebf-b8be2e6e1518
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820913018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.820913018
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_random.239550429
Short name T164
Test name
Test status
Simulation time 2410858716400 ps
CPU time 624.31 seconds
Started Aug 10 06:06:43 PM PDT 24
Finished Aug 10 06:17:07 PM PDT 24
Peak memory 191716 kb
Host smart-16ca7953-19fb-4826-97d1-889c91ef3b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239550429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.239550429
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3608174384
Short name T383
Test name
Test status
Simulation time 177307171 ps
CPU time 0.86 seconds
Started Aug 10 06:06:36 PM PDT 24
Finished Aug 10 06:06:37 PM PDT 24
Peak memory 183204 kb
Host smart-e4b6187d-6909-41cf-9968-9226a756ad8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608174384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3608174384
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3416855508
Short name T329
Test name
Test status
Simulation time 184007831980 ps
CPU time 231.76 seconds
Started Aug 10 06:06:44 PM PDT 24
Finished Aug 10 06:10:36 PM PDT 24
Peak memory 183492 kb
Host smart-11dff754-4b85-45b6-8b63-89d9bce5fc2e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416855508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3416855508
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2440209278
Short name T60
Test name
Test status
Simulation time 57842001976 ps
CPU time 23.08 seconds
Started Aug 10 06:06:36 PM PDT 24
Finished Aug 10 06:06:59 PM PDT 24
Peak memory 183400 kb
Host smart-ba206ade-f88f-4fdb-8c76-5120c638b637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440209278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2440209278
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.556767005
Short name T302
Test name
Test status
Simulation time 26481814738 ps
CPU time 9.32 seconds
Started Aug 10 06:06:44 PM PDT 24
Finished Aug 10 06:06:53 PM PDT 24
Peak memory 183332 kb
Host smart-758fa7d6-6883-4e9b-a382-d701701892b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556767005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.556767005
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1569145156
Short name T187
Test name
Test status
Simulation time 64215244827 ps
CPU time 838.77 seconds
Started Aug 10 06:06:39 PM PDT 24
Finished Aug 10 06:20:38 PM PDT 24
Peak memory 183480 kb
Host smart-30a036ca-ab8a-4d65-94c3-d831ff08629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569145156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1569145156
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.3689364015
Short name T53
Test name
Test status
Simulation time 97416199799 ps
CPU time 189.57 seconds
Started Aug 10 06:06:41 PM PDT 24
Finished Aug 10 06:09:51 PM PDT 24
Peak memory 198128 kb
Host smart-a5cfdfa3-d253-475c-b429-850960364b14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689364015 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.3689364015
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.534307392
Short name T355
Test name
Test status
Simulation time 1084076759120 ps
CPU time 456.71 seconds
Started Aug 10 06:06:36 PM PDT 24
Finished Aug 10 06:14:13 PM PDT 24
Peak memory 183480 kb
Host smart-3f508842-a16b-49e3-a829-44987ff32f96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534307392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.534307392
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_random.1279622379
Short name T385
Test name
Test status
Simulation time 44904661054 ps
CPU time 189.84 seconds
Started Aug 10 06:06:45 PM PDT 24
Finished Aug 10 06:09:55 PM PDT 24
Peak memory 183508 kb
Host smart-ca7dacf6-d147-4414-b04c-64303b80712a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279622379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1279622379
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.577612169
Short name T348
Test name
Test status
Simulation time 35412950176 ps
CPU time 34.53 seconds
Started Aug 10 06:06:41 PM PDT 24
Finished Aug 10 06:07:16 PM PDT 24
Peak memory 194068 kb
Host smart-d859474c-7acf-45db-916c-647812ac962a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577612169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.577612169
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.972670739
Short name T203
Test name
Test status
Simulation time 2466085864266 ps
CPU time 816.86 seconds
Started Aug 10 06:06:45 PM PDT 24
Finished Aug 10 06:20:22 PM PDT 24
Peak memory 191660 kb
Host smart-e0377fc7-917a-4e5e-aeb2-af5eaf19b45e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972670739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
972670739
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3891062235
Short name T13
Test name
Test status
Simulation time 783559910199 ps
CPU time 326.1 seconds
Started Aug 10 06:04:34 PM PDT 24
Finished Aug 10 06:10:00 PM PDT 24
Peak memory 183376 kb
Host smart-53dd2d6e-ef95-4468-9f4a-ce68dc4aeb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891062235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3891062235
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1596264177
Short name T50
Test name
Test status
Simulation time 173247993200 ps
CPU time 2105.32 seconds
Started Aug 10 06:04:37 PM PDT 24
Finished Aug 10 06:39:42 PM PDT 24
Peak memory 191656 kb
Host smart-9e5dc72b-e0bb-491f-8039-9a2776d54de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596264177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1596264177
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3466423311
Short name T428
Test name
Test status
Simulation time 157607159 ps
CPU time 0.74 seconds
Started Aug 10 06:04:35 PM PDT 24
Finished Aug 10 06:04:36 PM PDT 24
Peak memory 183092 kb
Host smart-c5374c78-ea5b-4667-8c53-ed75c4ffc676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466423311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3466423311
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3728376739
Short name T248
Test name
Test status
Simulation time 702339020720 ps
CPU time 368.94 seconds
Started Aug 10 06:04:34 PM PDT 24
Finished Aug 10 06:10:43 PM PDT 24
Peak memory 191608 kb
Host smart-6332f61d-7f7f-4544-8439-1c081c61e195
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728376739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3728376739
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.1853977779
Short name T234
Test name
Test status
Simulation time 64067963519 ps
CPU time 720.21 seconds
Started Aug 10 06:06:43 PM PDT 24
Finished Aug 10 06:18:44 PM PDT 24
Peak memory 191712 kb
Host smart-88cde423-b31c-4ff2-ba64-1576f2dff5a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853977779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1853977779
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2399169918
Short name T341
Test name
Test status
Simulation time 48581198942 ps
CPU time 88.92 seconds
Started Aug 10 06:06:55 PM PDT 24
Finished Aug 10 06:08:24 PM PDT 24
Peak memory 191680 kb
Host smart-ceacff69-61f7-415e-ae48-fa8280cc2f31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399169918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2399169918
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2459743555
Short name T346
Test name
Test status
Simulation time 490845655299 ps
CPU time 854.76 seconds
Started Aug 10 06:06:44 PM PDT 24
Finished Aug 10 06:20:59 PM PDT 24
Peak memory 194212 kb
Host smart-66c5f50c-e9e1-4828-866a-4340cd9a8935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459743555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2459743555
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.4170288582
Short name T424
Test name
Test status
Simulation time 51868335449 ps
CPU time 112.91 seconds
Started Aug 10 06:06:55 PM PDT 24
Finished Aug 10 06:08:48 PM PDT 24
Peak memory 183480 kb
Host smart-baaec9a1-0b33-4290-bd17-421bd40c7f83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170288582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.4170288582
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.4001372443
Short name T264
Test name
Test status
Simulation time 216889947387 ps
CPU time 233.91 seconds
Started Aug 10 06:06:45 PM PDT 24
Finished Aug 10 06:10:39 PM PDT 24
Peak memory 191660 kb
Host smart-5f08f29c-bf38-44cd-a21d-c2fa825b4b42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001372443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.4001372443
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2244387944
Short name T291
Test name
Test status
Simulation time 504991405742 ps
CPU time 156.5 seconds
Started Aug 10 06:06:46 PM PDT 24
Finished Aug 10 06:09:22 PM PDT 24
Peak memory 191688 kb
Host smart-93d95aaa-7381-4dda-a8ca-90f92ef5a575
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244387944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2244387944
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2592981037
Short name T427
Test name
Test status
Simulation time 729817321708 ps
CPU time 292.16 seconds
Started Aug 10 06:04:34 PM PDT 24
Finished Aug 10 06:09:26 PM PDT 24
Peak memory 183436 kb
Host smart-105f5c71-3756-4056-b37d-33c0f7824afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592981037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2592981037
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3892981025
Short name T269
Test name
Test status
Simulation time 359824062744 ps
CPU time 443.38 seconds
Started Aug 10 06:04:33 PM PDT 24
Finished Aug 10 06:11:57 PM PDT 24
Peak memory 191636 kb
Host smart-1249f391-6b1f-40a3-90b8-34a3a9337735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892981025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3892981025
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2148403646
Short name T309
Test name
Test status
Simulation time 97787100744 ps
CPU time 43.5 seconds
Started Aug 10 06:04:35 PM PDT 24
Finished Aug 10 06:05:19 PM PDT 24
Peak memory 191664 kb
Host smart-9793cfa2-bdac-4c59-a12e-e5f05646332c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148403646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2148403646
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.1593780457
Short name T17
Test name
Test status
Simulation time 60388084960 ps
CPU time 181.18 seconds
Started Aug 10 06:04:34 PM PDT 24
Finished Aug 10 06:07:36 PM PDT 24
Peak memory 198156 kb
Host smart-81fdb26a-7cfe-4716-8036-0a84b3c868ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593780457 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.1593780457
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.594969690
Short name T110
Test name
Test status
Simulation time 350053844433 ps
CPU time 787.92 seconds
Started Aug 10 06:06:52 PM PDT 24
Finished Aug 10 06:20:00 PM PDT 24
Peak memory 191636 kb
Host smart-209d64cc-c1f0-4dc6-96a5-933a8fd19f62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594969690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.594969690
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1251777305
Short name T180
Test name
Test status
Simulation time 429544695092 ps
CPU time 2527.7 seconds
Started Aug 10 06:06:52 PM PDT 24
Finished Aug 10 06:49:00 PM PDT 24
Peak memory 191628 kb
Host smart-3dcb0caf-4011-4ea8-bb75-12123cb6c673
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251777305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1251777305
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1015852853
Short name T330
Test name
Test status
Simulation time 44159202350 ps
CPU time 13.99 seconds
Started Aug 10 06:06:53 PM PDT 24
Finished Aug 10 06:07:07 PM PDT 24
Peak memory 183444 kb
Host smart-ae002027-2af2-4ab5-a27d-d7514dfbb03d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015852853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1015852853
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3282906600
Short name T283
Test name
Test status
Simulation time 85280350504 ps
CPU time 539.06 seconds
Started Aug 10 06:06:50 PM PDT 24
Finished Aug 10 06:15:50 PM PDT 24
Peak memory 191684 kb
Host smart-53b182d9-c9fd-4f1d-bb27-c15b3c13b327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282906600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3282906600
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1349787051
Short name T282
Test name
Test status
Simulation time 326558939080 ps
CPU time 1284.31 seconds
Started Aug 10 06:06:52 PM PDT 24
Finished Aug 10 06:28:17 PM PDT 24
Peak memory 191672 kb
Host smart-0030616a-8256-4432-9534-f8d12c4ee1fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349787051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1349787051
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2103554707
Short name T238
Test name
Test status
Simulation time 107354933252 ps
CPU time 784.58 seconds
Started Aug 10 06:06:53 PM PDT 24
Finished Aug 10 06:19:57 PM PDT 24
Peak memory 191688 kb
Host smart-205925a7-b94f-4a37-9e23-a3ddb821357a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103554707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2103554707
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3089103318
Short name T179
Test name
Test status
Simulation time 455397430188 ps
CPU time 498.35 seconds
Started Aug 10 06:06:54 PM PDT 24
Finished Aug 10 06:15:12 PM PDT 24
Peak memory 191660 kb
Host smart-ccfbe959-a718-40c1-afe8-f968303527f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089103318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3089103318
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1337959966
Short name T433
Test name
Test status
Simulation time 117718670897 ps
CPU time 193.23 seconds
Started Aug 10 06:06:51 PM PDT 24
Finished Aug 10 06:10:05 PM PDT 24
Peak memory 191708 kb
Host smart-e6f7a126-2d5c-4d50-b78d-2196959939e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337959966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1337959966
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.74509077
Short name T208
Test name
Test status
Simulation time 260867215076 ps
CPU time 234.05 seconds
Started Aug 10 06:06:52 PM PDT 24
Finished Aug 10 06:10:46 PM PDT 24
Peak memory 194876 kb
Host smart-23e9ca2e-6c1b-4e65-b3b7-759c99e3122b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74509077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.74509077
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3111090197
Short name T299
Test name
Test status
Simulation time 101983879832 ps
CPU time 2590.2 seconds
Started Aug 10 06:06:53 PM PDT 24
Finished Aug 10 06:50:03 PM PDT 24
Peak memory 191648 kb
Host smart-6a7502eb-8079-478d-8480-5030db4e296e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111090197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3111090197
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1041359688
Short name T305
Test name
Test status
Simulation time 512320106359 ps
CPU time 279.31 seconds
Started Aug 10 06:04:35 PM PDT 24
Finished Aug 10 06:09:15 PM PDT 24
Peak memory 183444 kb
Host smart-3c55d39d-2c61-4cda-99a9-d75105be8c58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041359688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1041359688
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1197629222
Short name T440
Test name
Test status
Simulation time 112375044412 ps
CPU time 158.94 seconds
Started Aug 10 06:04:34 PM PDT 24
Finished Aug 10 06:07:13 PM PDT 24
Peak memory 183412 kb
Host smart-c182780c-495b-479b-b38c-69350211444f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197629222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1197629222
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2141709350
Short name T182
Test name
Test status
Simulation time 291711130621 ps
CPU time 330.42 seconds
Started Aug 10 06:04:32 PM PDT 24
Finished Aug 10 06:10:03 PM PDT 24
Peak memory 191612 kb
Host smart-6ccab5d8-f544-429d-94e3-2a455c26de2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141709350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2141709350
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2567519037
Short name T381
Test name
Test status
Simulation time 416724780 ps
CPU time 0.7 seconds
Started Aug 10 06:04:33 PM PDT 24
Finished Aug 10 06:04:34 PM PDT 24
Peak memory 191828 kb
Host smart-d4d4ba7c-8d19-4b5b-92ea-1892f752a998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567519037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2567519037
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.255208559
Short name T195
Test name
Test status
Simulation time 167421680335 ps
CPU time 500.9 seconds
Started Aug 10 06:04:34 PM PDT 24
Finished Aug 10 06:12:55 PM PDT 24
Peak memory 191596 kb
Host smart-c7483c30-3ef7-41a2-a65b-422423383b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255208559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.255208559
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1853668605
Short name T40
Test name
Test status
Simulation time 13473560410 ps
CPU time 140.86 seconds
Started Aug 10 06:04:36 PM PDT 24
Finished Aug 10 06:06:57 PM PDT 24
Peak memory 196924 kb
Host smart-08cd5986-1db8-40f6-a331-c32391023190
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853668605 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1853668605
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.743770772
Short name T276
Test name
Test status
Simulation time 383125228531 ps
CPU time 428.32 seconds
Started Aug 10 06:07:00 PM PDT 24
Finished Aug 10 06:14:09 PM PDT 24
Peak memory 191644 kb
Host smart-c3019548-fe73-4071-8484-9973822853ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743770772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.743770772
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.366582962
Short name T167
Test name
Test status
Simulation time 65854145188 ps
CPU time 35.21 seconds
Started Aug 10 06:07:09 PM PDT 24
Finished Aug 10 06:07:44 PM PDT 24
Peak memory 183472 kb
Host smart-eae77173-b72b-4b9f-9e0b-0980d9436564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366582962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.366582962
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3152545766
Short name T298
Test name
Test status
Simulation time 3675882250 ps
CPU time 6.16 seconds
Started Aug 10 06:07:00 PM PDT 24
Finished Aug 10 06:07:06 PM PDT 24
Peak memory 183260 kb
Host smart-d66f3406-e3d2-4f30-9e57-ffa3f27fb40c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152545766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3152545766
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.513655502
Short name T181
Test name
Test status
Simulation time 62091365681 ps
CPU time 103.45 seconds
Started Aug 10 06:07:10 PM PDT 24
Finished Aug 10 06:08:53 PM PDT 24
Peak memory 191672 kb
Host smart-68627095-cded-474e-8828-4a61c23efe5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513655502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.513655502
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.647890806
Short name T356
Test name
Test status
Simulation time 40591274193 ps
CPU time 35.84 seconds
Started Aug 10 06:07:00 PM PDT 24
Finished Aug 10 06:07:36 PM PDT 24
Peak memory 183492 kb
Host smart-57e7080a-fc2d-4703-b0b4-4b0e492cf0da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647890806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.647890806
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.133153000
Short name T429
Test name
Test status
Simulation time 330509914683 ps
CPU time 237.7 seconds
Started Aug 10 06:07:00 PM PDT 24
Finished Aug 10 06:10:58 PM PDT 24
Peak memory 191660 kb
Host smart-2885e930-40c6-4142-8d2d-535ea5e01953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133153000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.133153000
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1013810692
Short name T325
Test name
Test status
Simulation time 6404722010 ps
CPU time 2.72 seconds
Started Aug 10 06:07:00 PM PDT 24
Finished Aug 10 06:07:03 PM PDT 24
Peak memory 183304 kb
Host smart-ba9a50e8-b6d5-4cc3-82dd-24c27037de08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013810692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1013810692
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2241597554
Short name T23
Test name
Test status
Simulation time 37661403893 ps
CPU time 29.52 seconds
Started Aug 10 06:04:35 PM PDT 24
Finished Aug 10 06:05:05 PM PDT 24
Peak memory 183456 kb
Host smart-e53ab83b-8f43-439a-a05f-62fdb6be0bad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241597554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2241597554
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2539959317
Short name T379
Test name
Test status
Simulation time 91245180846 ps
CPU time 140.71 seconds
Started Aug 10 06:04:39 PM PDT 24
Finished Aug 10 06:06:59 PM PDT 24
Peak memory 183228 kb
Host smart-f06d7e74-6f6c-465d-a734-8ff9dfc3f55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539959317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2539959317
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3224990268
Short name T206
Test name
Test status
Simulation time 868299658485 ps
CPU time 3005.89 seconds
Started Aug 10 06:04:34 PM PDT 24
Finished Aug 10 06:54:40 PM PDT 24
Peak memory 191676 kb
Host smart-df308fc8-d8cb-470b-bd8c-a672535886dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224990268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3224990268
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.359681838
Short name T11
Test name
Test status
Simulation time 26377796265 ps
CPU time 42.52 seconds
Started Aug 10 06:04:36 PM PDT 24
Finished Aug 10 06:05:19 PM PDT 24
Peak memory 183480 kb
Host smart-49609ee3-cf88-4e12-84f8-fff3c7a211f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359681838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.359681838
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3096060684
Short name T169
Test name
Test status
Simulation time 58146111640 ps
CPU time 95.89 seconds
Started Aug 10 06:07:08 PM PDT 24
Finished Aug 10 06:08:44 PM PDT 24
Peak memory 191680 kb
Host smart-2e0f2f74-9635-4024-820e-250e859e4cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096060684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3096060684
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3832236678
Short name T265
Test name
Test status
Simulation time 662279890327 ps
CPU time 231.83 seconds
Started Aug 10 06:07:01 PM PDT 24
Finished Aug 10 06:10:53 PM PDT 24
Peak memory 191612 kb
Host smart-26debbcd-e14d-4947-ab07-5c7fe3feb04a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832236678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3832236678
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1406442585
Short name T225
Test name
Test status
Simulation time 142973634555 ps
CPU time 1735.2 seconds
Started Aug 10 06:06:58 PM PDT 24
Finished Aug 10 06:35:53 PM PDT 24
Peak memory 191620 kb
Host smart-1ca47f25-a87b-4c00-bb44-f1ba58145fdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406442585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1406442585
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3503911745
Short name T186
Test name
Test status
Simulation time 258593195733 ps
CPU time 549.27 seconds
Started Aug 10 06:07:10 PM PDT 24
Finished Aug 10 06:16:20 PM PDT 24
Peak memory 191716 kb
Host smart-af6fa90f-17c0-419d-8e57-7620c29194ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503911745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3503911745
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2800005953
Short name T198
Test name
Test status
Simulation time 538700650173 ps
CPU time 276.42 seconds
Started Aug 10 06:07:08 PM PDT 24
Finished Aug 10 06:11:44 PM PDT 24
Peak memory 191688 kb
Host smart-b07d9524-85cb-445a-8ba7-6015a6f3c43d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800005953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2800005953
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4092193078
Short name T439
Test name
Test status
Simulation time 235002467899 ps
CPU time 72.04 seconds
Started Aug 10 06:07:09 PM PDT 24
Finished Aug 10 06:08:21 PM PDT 24
Peak memory 183444 kb
Host smart-2c3ff7f0-adcb-4a1b-a9d1-a17eebe28265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092193078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4092193078
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2820305734
Short name T150
Test name
Test status
Simulation time 781267371571 ps
CPU time 1326.24 seconds
Started Aug 10 06:07:10 PM PDT 24
Finished Aug 10 06:29:16 PM PDT 24
Peak memory 191664 kb
Host smart-5854ec37-bbe4-4fde-8174-1c72e4066e40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820305734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2820305734
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2458975188
Short name T270
Test name
Test status
Simulation time 108143125770 ps
CPU time 1162.84 seconds
Started Aug 10 06:07:08 PM PDT 24
Finished Aug 10 06:26:31 PM PDT 24
Peak memory 183268 kb
Host smart-9d307523-7995-442d-be29-44ea971f1f14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458975188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2458975188
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2782914658
Short name T314
Test name
Test status
Simulation time 45930565418 ps
CPU time 48.21 seconds
Started Aug 10 06:07:08 PM PDT 24
Finished Aug 10 06:07:56 PM PDT 24
Peak memory 191688 kb
Host smart-e241074e-bbdb-4624-a9b7-b12dc216a469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782914658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2782914658
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3799774885
Short name T191
Test name
Test status
Simulation time 101761949089 ps
CPU time 172.85 seconds
Started Aug 10 06:04:36 PM PDT 24
Finished Aug 10 06:07:29 PM PDT 24
Peak memory 183472 kb
Host smart-5409f281-644d-4deb-93b9-cb6d78795f4d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799774885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3799774885
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.161968513
Short name T27
Test name
Test status
Simulation time 406823481387 ps
CPU time 143.56 seconds
Started Aug 10 06:04:34 PM PDT 24
Finished Aug 10 06:06:57 PM PDT 24
Peak memory 183484 kb
Host smart-3a759465-2059-42bd-980d-962f9f19639a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161968513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.161968513
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3836186311
Short name T251
Test name
Test status
Simulation time 412811227893 ps
CPU time 193.21 seconds
Started Aug 10 06:04:36 PM PDT 24
Finished Aug 10 06:07:50 PM PDT 24
Peak memory 191536 kb
Host smart-a77404fa-81ab-419c-b33b-efe335f0db21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836186311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3836186311
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.2492372907
Short name T199
Test name
Test status
Simulation time 215148615472 ps
CPU time 122.41 seconds
Started Aug 10 06:07:09 PM PDT 24
Finished Aug 10 06:09:11 PM PDT 24
Peak memory 191716 kb
Host smart-88c2847a-ab96-4a7f-9cae-468d58bac576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492372907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2492372907
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2284304994
Short name T118
Test name
Test status
Simulation time 176469034806 ps
CPU time 397.78 seconds
Started Aug 10 06:07:10 PM PDT 24
Finished Aug 10 06:13:48 PM PDT 24
Peak memory 191584 kb
Host smart-191b8b49-0860-4ea0-81fa-692fc33347e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284304994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2284304994
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.864447105
Short name T242
Test name
Test status
Simulation time 145514040102 ps
CPU time 389.5 seconds
Started Aug 10 06:07:09 PM PDT 24
Finished Aug 10 06:13:39 PM PDT 24
Peak memory 191664 kb
Host smart-a47eeb60-4a74-4c1b-8133-6ad1b2ee2869
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864447105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.864447105
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3318020231
Short name T261
Test name
Test status
Simulation time 803140534944 ps
CPU time 896.21 seconds
Started Aug 10 06:07:10 PM PDT 24
Finished Aug 10 06:22:06 PM PDT 24
Peak memory 191668 kb
Host smart-e3294c52-e1b2-438f-ac6d-8e92ae617032
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318020231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3318020231
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2954691701
Short name T158
Test name
Test status
Simulation time 393953017574 ps
CPU time 331.59 seconds
Started Aug 10 06:07:10 PM PDT 24
Finished Aug 10 06:12:42 PM PDT 24
Peak memory 191624 kb
Host smart-d6384fc0-7761-4886-b1e8-9197d9dbcadf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954691701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2954691701
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.685708720
Short name T304
Test name
Test status
Simulation time 252958965207 ps
CPU time 429.38 seconds
Started Aug 10 06:07:08 PM PDT 24
Finished Aug 10 06:14:18 PM PDT 24
Peak memory 191664 kb
Host smart-1b2b1c54-693a-4e0f-906c-353df3acb78d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685708720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.685708720
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2328578974
Short name T224
Test name
Test status
Simulation time 5874818068 ps
CPU time 16.05 seconds
Started Aug 10 06:07:09 PM PDT 24
Finished Aug 10 06:07:25 PM PDT 24
Peak memory 191660 kb
Host smart-8d1e3e2b-a639-4eee-8c6e-2742658f1e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328578974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2328578974
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2434328072
Short name T389
Test name
Test status
Simulation time 118445121482 ps
CPU time 67.48 seconds
Started Aug 10 06:07:19 PM PDT 24
Finished Aug 10 06:08:27 PM PDT 24
Peak memory 183412 kb
Host smart-07c0735a-3e8f-4803-b32a-2b47ee420b68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434328072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2434328072
Directory /workspace/99.rv_timer_random/latest
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