Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 578
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T508 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.490529917 Aug 11 06:09:35 PM PDT 24 Aug 11 06:09:36 PM PDT 24 226927773 ps
T509 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2349271661 Aug 11 06:09:48 PM PDT 24 Aug 11 06:09:49 PM PDT 24 168401690 ps
T510 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.407445399 Aug 11 06:09:31 PM PDT 24 Aug 11 06:09:32 PM PDT 24 79888116 ps
T511 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.691114822 Aug 11 06:09:47 PM PDT 24 Aug 11 06:09:47 PM PDT 24 41413344 ps
T512 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1194185372 Aug 11 06:09:46 PM PDT 24 Aug 11 06:09:47 PM PDT 24 30209021 ps
T513 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2926460712 Aug 11 06:09:41 PM PDT 24 Aug 11 06:09:42 PM PDT 24 47834533 ps
T514 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.535665364 Aug 11 06:09:37 PM PDT 24 Aug 11 06:09:38 PM PDT 24 37513782 ps
T515 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1409842897 Aug 11 06:09:54 PM PDT 24 Aug 11 06:09:55 PM PDT 24 21462464 ps
T516 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2057180432 Aug 11 06:09:47 PM PDT 24 Aug 11 06:09:50 PM PDT 24 103469986 ps
T517 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.504565902 Aug 11 06:09:56 PM PDT 24 Aug 11 06:09:57 PM PDT 24 120810908 ps
T518 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1786912802 Aug 11 06:09:49 PM PDT 24 Aug 11 06:09:50 PM PDT 24 16482803 ps
T519 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2018290374 Aug 11 06:09:44 PM PDT 24 Aug 11 06:09:48 PM PDT 24 1114992358 ps
T520 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3552811900 Aug 11 06:10:00 PM PDT 24 Aug 11 06:10:00 PM PDT 24 62510900 ps
T521 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1444809553 Aug 11 06:09:30 PM PDT 24 Aug 11 06:09:30 PM PDT 24 32170117 ps
T108 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3464895846 Aug 11 06:09:36 PM PDT 24 Aug 11 06:09:37 PM PDT 24 481052032 ps
T109 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.929902520 Aug 11 06:09:47 PM PDT 24 Aug 11 06:09:48 PM PDT 24 618496815 ps
T91 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.613131326 Aug 11 06:09:48 PM PDT 24 Aug 11 06:09:49 PM PDT 24 13689732 ps
T522 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2634405135 Aug 11 06:09:44 PM PDT 24 Aug 11 06:09:45 PM PDT 24 28635648 ps
T523 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1502492587 Aug 11 06:09:38 PM PDT 24 Aug 11 06:09:38 PM PDT 24 20236970 ps
T524 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.829068139 Aug 11 06:09:39 PM PDT 24 Aug 11 06:09:40 PM PDT 24 15027392 ps
T525 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3916442928 Aug 11 06:09:47 PM PDT 24 Aug 11 06:09:49 PM PDT 24 157642840 ps
T526 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1966052037 Aug 11 06:10:03 PM PDT 24 Aug 11 06:10:03 PM PDT 24 17576771 ps
T527 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.494762708 Aug 11 06:09:41 PM PDT 24 Aug 11 06:09:42 PM PDT 24 38373046 ps
T528 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1607995526 Aug 11 06:09:48 PM PDT 24 Aug 11 06:09:49 PM PDT 24 22990189 ps
T529 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.526066941 Aug 11 06:09:50 PM PDT 24 Aug 11 06:09:51 PM PDT 24 14615881 ps
T530 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2581684568 Aug 11 06:09:37 PM PDT 24 Aug 11 06:09:38 PM PDT 24 28148532 ps
T531 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.464259887 Aug 11 06:09:44 PM PDT 24 Aug 11 06:09:45 PM PDT 24 23921527 ps
T532 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1188492646 Aug 11 06:09:48 PM PDT 24 Aug 11 06:09:49 PM PDT 24 71499393 ps
T533 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.439666211 Aug 11 06:09:44 PM PDT 24 Aug 11 06:09:45 PM PDT 24 15131233 ps
T534 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2553606946 Aug 11 06:09:34 PM PDT 24 Aug 11 06:09:34 PM PDT 24 48763259 ps
T535 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2516426635 Aug 11 06:09:27 PM PDT 24 Aug 11 06:09:28 PM PDT 24 12537879 ps
T536 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1158113815 Aug 11 06:09:38 PM PDT 24 Aug 11 06:09:40 PM PDT 24 42105752 ps
T537 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1665596747 Aug 11 06:09:55 PM PDT 24 Aug 11 06:09:55 PM PDT 24 27416207 ps
T538 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1506647590 Aug 11 06:09:41 PM PDT 24 Aug 11 06:09:42 PM PDT 24 157748122 ps
T92 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1550300766 Aug 11 06:09:54 PM PDT 24 Aug 11 06:09:54 PM PDT 24 22268308 ps
T539 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.871156719 Aug 11 06:09:28 PM PDT 24 Aug 11 06:09:28 PM PDT 24 16273318 ps
T540 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1390801304 Aug 11 06:09:53 PM PDT 24 Aug 11 06:09:53 PM PDT 24 48262876 ps
T93 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1602164760 Aug 11 06:09:45 PM PDT 24 Aug 11 06:09:46 PM PDT 24 75473708 ps
T94 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.233609269 Aug 11 06:09:27 PM PDT 24 Aug 11 06:09:27 PM PDT 24 11608488 ps
T541 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2439677501 Aug 11 06:09:37 PM PDT 24 Aug 11 06:09:37 PM PDT 24 62220416 ps
T542 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1034487753 Aug 11 06:09:38 PM PDT 24 Aug 11 06:09:39 PM PDT 24 25927299 ps
T543 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.656790443 Aug 11 06:09:42 PM PDT 24 Aug 11 06:09:43 PM PDT 24 107139742 ps
T544 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.755188892 Aug 11 06:09:50 PM PDT 24 Aug 11 06:09:51 PM PDT 24 50254675 ps
T545 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3798387793 Aug 11 06:10:00 PM PDT 24 Aug 11 06:10:01 PM PDT 24 64938637 ps
T546 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3130196629 Aug 11 06:09:51 PM PDT 24 Aug 11 06:09:52 PM PDT 24 147252685 ps
T547 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1399893882 Aug 11 06:09:52 PM PDT 24 Aug 11 06:09:52 PM PDT 24 22194466 ps
T548 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.713194105 Aug 11 06:09:50 PM PDT 24 Aug 11 06:09:51 PM PDT 24 13406867 ps
T549 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.547055802 Aug 11 06:09:51 PM PDT 24 Aug 11 06:09:52 PM PDT 24 96189271 ps
T95 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.30763817 Aug 11 06:09:39 PM PDT 24 Aug 11 06:09:43 PM PDT 24 1626709437 ps
T550 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2196440549 Aug 11 06:09:29 PM PDT 24 Aug 11 06:09:30 PM PDT 24 120314420 ps
T551 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.497408880 Aug 11 06:09:56 PM PDT 24 Aug 11 06:09:57 PM PDT 24 105887596 ps
T552 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2408147073 Aug 11 06:09:41 PM PDT 24 Aug 11 06:09:41 PM PDT 24 14651006 ps
T553 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2674232868 Aug 11 06:09:58 PM PDT 24 Aug 11 06:09:59 PM PDT 24 203795888 ps
T554 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1827244178 Aug 11 06:09:46 PM PDT 24 Aug 11 06:09:47 PM PDT 24 94938280 ps
T555 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.697306408 Aug 11 06:09:41 PM PDT 24 Aug 11 06:09:41 PM PDT 24 66400198 ps
T556 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1078991278 Aug 11 06:09:54 PM PDT 24 Aug 11 06:09:55 PM PDT 24 19849429 ps
T557 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.384608402 Aug 11 06:09:40 PM PDT 24 Aug 11 06:09:41 PM PDT 24 3869002403 ps
T558 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2669693558 Aug 11 06:09:50 PM PDT 24 Aug 11 06:09:51 PM PDT 24 25228733 ps
T559 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.273483503 Aug 11 06:09:35 PM PDT 24 Aug 11 06:09:36 PM PDT 24 93798427 ps
T560 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.135097637 Aug 11 06:09:44 PM PDT 24 Aug 11 06:09:45 PM PDT 24 30807244 ps
T561 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3053471328 Aug 11 06:09:44 PM PDT 24 Aug 11 06:09:45 PM PDT 24 143527101 ps
T562 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2916039607 Aug 11 06:09:49 PM PDT 24 Aug 11 06:09:50 PM PDT 24 95647453 ps
T563 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2164026311 Aug 11 06:09:57 PM PDT 24 Aug 11 06:09:57 PM PDT 24 52481200 ps
T564 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3138492612 Aug 11 06:09:50 PM PDT 24 Aug 11 06:09:51 PM PDT 24 13838581 ps
T565 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3816138304 Aug 11 06:09:45 PM PDT 24 Aug 11 06:09:45 PM PDT 24 12196654 ps
T566 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4283559247 Aug 11 06:09:49 PM PDT 24 Aug 11 06:09:50 PM PDT 24 28154542 ps
T567 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2781421490 Aug 11 06:09:59 PM PDT 24 Aug 11 06:10:00 PM PDT 24 91046792 ps
T568 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.100299545 Aug 11 06:09:53 PM PDT 24 Aug 11 06:09:54 PM PDT 24 36707909 ps
T569 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3476981661 Aug 11 06:09:29 PM PDT 24 Aug 11 06:09:30 PM PDT 24 89877472 ps
T570 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2294501817 Aug 11 06:09:51 PM PDT 24 Aug 11 06:09:53 PM PDT 24 436974746 ps
T571 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.609820986 Aug 11 06:09:52 PM PDT 24 Aug 11 06:09:54 PM PDT 24 132209377 ps
T572 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.677934721 Aug 11 06:10:00 PM PDT 24 Aug 11 06:10:00 PM PDT 24 42248346 ps
T573 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.642017329 Aug 11 06:09:48 PM PDT 24 Aug 11 06:09:49 PM PDT 24 35706726 ps
T574 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1125823722 Aug 11 06:09:49 PM PDT 24 Aug 11 06:09:51 PM PDT 24 229329766 ps
T575 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2915675885 Aug 11 06:09:48 PM PDT 24 Aug 11 06:09:50 PM PDT 24 433396438 ps
T576 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1380011853 Aug 11 06:09:33 PM PDT 24 Aug 11 06:09:35 PM PDT 24 67018017 ps
T577 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2620489445 Aug 11 06:09:52 PM PDT 24 Aug 11 06:09:53 PM PDT 24 97987884 ps
T578 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2929683929 Aug 11 06:09:40 PM PDT 24 Aug 11 06:09:43 PM PDT 24 50167943 ps

Test location /workspace/coverage/default/136.rv_timer_random.3948865244
Short name T10
Test name
Test status
Simulation time 112253455418 ps
CPU time 547.74 seconds
Started Aug 11 06:28:39 PM PDT 24
Finished Aug 11 06:37:47 PM PDT 24
Peak memory 191588 kb
Host smart-5418a60c-81d3-4931-87cd-0124a2800eec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948865244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3948865244
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.2705548579
Short name T32
Test name
Test status
Simulation time 71591780486 ps
CPU time 137.81 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:29:53 PM PDT 24
Peak memory 206368 kb
Host smart-b949f6f5-6990-4c13-a087-92cc862d4e96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705548579 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.2705548579
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2463984267
Short name T68
Test name
Test status
Simulation time 1011640864737 ps
CPU time 2248.75 seconds
Started Aug 11 06:27:32 PM PDT 24
Finished Aug 11 07:05:01 PM PDT 24
Peak memory 194784 kb
Host smart-679b2f42-ab0e-424f-ad9f-f2cae491dd27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463984267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2463984267
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.803775998
Short name T171
Test name
Test status
Simulation time 549687378481 ps
CPU time 1346.69 seconds
Started Aug 11 06:28:09 PM PDT 24
Finished Aug 11 06:50:36 PM PDT 24
Peak memory 191596 kb
Host smart-b567047e-10c5-4807-9bbc-0e206ed56925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803775998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
803775998
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.4036936893
Short name T24
Test name
Test status
Simulation time 108786705 ps
CPU time 1.39 seconds
Started Aug 11 06:09:41 PM PDT 24
Finished Aug 11 06:09:43 PM PDT 24
Peak memory 195188 kb
Host smart-26fb12d9-f9c3-4e49-ac1d-594630a13140
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036936893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.4036936893
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.4208897793
Short name T125
Test name
Test status
Simulation time 783215546909 ps
CPU time 2201.28 seconds
Started Aug 11 06:28:12 PM PDT 24
Finished Aug 11 07:04:54 PM PDT 24
Peak memory 191664 kb
Host smart-1d3744ac-ae4d-40c8-82d4-4dc2b65d9898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208897793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.4208897793
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3483873974
Short name T66
Test name
Test status
Simulation time 785508216273 ps
CPU time 1538.48 seconds
Started Aug 11 06:28:10 PM PDT 24
Finished Aug 11 06:53:49 PM PDT 24
Peak memory 191624 kb
Host smart-66288f69-5f44-488c-b83a-c137faf526b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483873974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3483873974
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/152.rv_timer_random.2633252619
Short name T2
Test name
Test status
Simulation time 170898744506 ps
CPU time 178.92 seconds
Started Aug 11 06:28:59 PM PDT 24
Finished Aug 11 06:31:58 PM PDT 24
Peak memory 191640 kb
Host smart-9aeabc8c-ce16-4b2c-ae16-4069b9582ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633252619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2633252619
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3465974032
Short name T248
Test name
Test status
Simulation time 561874166161 ps
CPU time 1328.8 seconds
Started Aug 11 06:28:03 PM PDT 24
Finished Aug 11 06:50:12 PM PDT 24
Peak memory 191600 kb
Host smart-ce3e07b4-49a9-4e53-bfb4-ffee08d04177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465974032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3465974032
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1976206249
Short name T184
Test name
Test status
Simulation time 2673850235837 ps
CPU time 1160.94 seconds
Started Aug 11 06:27:45 PM PDT 24
Finished Aug 11 06:47:06 PM PDT 24
Peak memory 191636 kb
Host smart-f5db720f-3206-4ace-b7a7-3dabda02b406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976206249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1976206249
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2389436342
Short name T83
Test name
Test status
Simulation time 20856285 ps
CPU time 0.59 seconds
Started Aug 11 06:09:44 PM PDT 24
Finished Aug 11 06:09:45 PM PDT 24
Peak memory 182864 kb
Host smart-58426b61-5d72-43f6-ace1-f22af4be7421
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389436342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2389436342
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1872818233
Short name T114
Test name
Test status
Simulation time 1499699285088 ps
CPU time 2264.2 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 07:05:24 PM PDT 24
Peak memory 196184 kb
Host smart-9c93d8d1-04d2-4b91-9e2c-ba18df4cb5dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872818233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1872818233
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2007272939
Short name T30
Test name
Test status
Simulation time 1608521643177 ps
CPU time 588.64 seconds
Started Aug 11 06:27:43 PM PDT 24
Finished Aug 11 06:37:32 PM PDT 24
Peak memory 196104 kb
Host smart-d877d957-a499-4a27-bd7f-7a5f02371024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007272939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2007272939
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.419518619
Short name T182
Test name
Test status
Simulation time 392272155345 ps
CPU time 670.69 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:38:50 PM PDT 24
Peak memory 191612 kb
Host smart-11eeb2cb-24cf-4edf-a0f0-68adeaff8ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419518619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
419518619
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1722567708
Short name T16
Test name
Test status
Simulation time 54934692 ps
CPU time 0.81 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:27:36 PM PDT 24
Peak memory 214024 kb
Host smart-bf9bb462-d54f-44c5-a961-6e7d33416a2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722567708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1722567708
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.629662093
Short name T196
Test name
Test status
Simulation time 1186317681737 ps
CPU time 2063.33 seconds
Started Aug 11 06:28:08 PM PDT 24
Finished Aug 11 07:02:32 PM PDT 24
Peak memory 191656 kb
Host smart-e941f730-b039-4789-8e10-cc8e7974d072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629662093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
629662093
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/118.rv_timer_random.29124572
Short name T154
Test name
Test status
Simulation time 210997998342 ps
CPU time 375.11 seconds
Started Aug 11 06:28:21 PM PDT 24
Finished Aug 11 06:34:36 PM PDT 24
Peak memory 191688 kb
Host smart-933ecdac-2e1d-41e5-8941-f6806294048d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29124572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.29124572
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2427636939
Short name T163
Test name
Test status
Simulation time 7614894003323 ps
CPU time 2347.17 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 07:06:45 PM PDT 24
Peak memory 191572 kb
Host smart-0afb86f7-7eb9-4747-b7dc-fcf8bc4bcc98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427636939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2427636939
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.222705667
Short name T339
Test name
Test status
Simulation time 902024507907 ps
CPU time 1333.29 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:49:51 PM PDT 24
Peak memory 191620 kb
Host smart-27fde591-aa52-47a7-84a0-9cefe637ea57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222705667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.222705667
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/108.rv_timer_random.1636133489
Short name T131
Test name
Test status
Simulation time 176525995142 ps
CPU time 407.99 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:35:04 PM PDT 24
Peak memory 191640 kb
Host smart-cf60097a-2443-4ecb-9dd5-3046c71c0ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636133489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1636133489
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.4021960841
Short name T183
Test name
Test status
Simulation time 1048362029307 ps
CPU time 579.93 seconds
Started Aug 11 06:28:11 PM PDT 24
Finished Aug 11 06:37:51 PM PDT 24
Peak memory 196336 kb
Host smart-1f045e46-b4bf-410d-a528-768fffd01cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021960841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.4021960841
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1538474857
Short name T289
Test name
Test status
Simulation time 613793926380 ps
CPU time 1759.62 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:57:00 PM PDT 24
Peak memory 195860 kb
Host smart-3a12b211-966c-4977-8b3d-8dd27d0581ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538474857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1538474857
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/198.rv_timer_random.115488156
Short name T166
Test name
Test status
Simulation time 1167861713592 ps
CPU time 471.81 seconds
Started Aug 11 06:29:33 PM PDT 24
Finished Aug 11 06:37:25 PM PDT 24
Peak memory 191644 kb
Host smart-7e24def9-b07d-40ee-90c5-a547c7b5736a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115488156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.115488156
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3045236397
Short name T142
Test name
Test status
Simulation time 689338883664 ps
CPU time 1318.35 seconds
Started Aug 11 06:28:27 PM PDT 24
Finished Aug 11 06:50:26 PM PDT 24
Peak memory 191712 kb
Host smart-a85b59be-3485-48a3-9a6e-884c886ebee6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045236397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3045236397
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2522623323
Short name T203
Test name
Test status
Simulation time 525039735883 ps
CPU time 293.52 seconds
Started Aug 11 06:29:10 PM PDT 24
Finished Aug 11 06:34:03 PM PDT 24
Peak memory 191668 kb
Host smart-52af4491-7292-485b-a4db-bd4c01142e5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522623323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2522623323
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.920804877
Short name T129
Test name
Test status
Simulation time 469107066865 ps
CPU time 670.95 seconds
Started Aug 11 06:29:22 PM PDT 24
Finished Aug 11 06:40:33 PM PDT 24
Peak memory 191680 kb
Host smart-08cc9bd5-56a4-4ab5-9756-3c2eafb167b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920804877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.920804877
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.952292518
Short name T253
Test name
Test status
Simulation time 1901992266461 ps
CPU time 942.31 seconds
Started Aug 11 06:27:45 PM PDT 24
Finished Aug 11 06:43:27 PM PDT 24
Peak memory 183436 kb
Host smart-6bff40bb-e5e6-4c9c-8dbe-0d70090df88b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952292518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.952292518
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.333847907
Short name T282
Test name
Test status
Simulation time 1217930854602 ps
CPU time 644.47 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:38:23 PM PDT 24
Peak memory 191660 kb
Host smart-3941fac4-a351-4827-a690-e13279d0d4e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333847907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.333847907
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_random.3741546406
Short name T330
Test name
Test status
Simulation time 251093810859 ps
CPU time 428.72 seconds
Started Aug 11 06:27:47 PM PDT 24
Finished Aug 11 06:34:56 PM PDT 24
Peak memory 191656 kb
Host smart-742d2f55-c0da-4f7b-b988-180e3c53ba80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741546406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3741546406
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3337413175
Short name T345
Test name
Test status
Simulation time 603267830502 ps
CPU time 770.74 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:40:31 PM PDT 24
Peak memory 191668 kb
Host smart-25a54c95-dc29-4cf0-af6d-c91318fb2022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337413175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3337413175
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/142.rv_timer_random.1313022473
Short name T225
Test name
Test status
Simulation time 129430973828 ps
CPU time 1329.58 seconds
Started Aug 11 06:28:44 PM PDT 24
Finished Aug 11 06:50:54 PM PDT 24
Peak memory 191624 kb
Host smart-2e078d19-236d-43dc-8a0b-419ba18211bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313022473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1313022473
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.3828780493
Short name T178
Test name
Test status
Simulation time 423229359603 ps
CPU time 1005.37 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:44:26 PM PDT 24
Peak memory 191556 kb
Host smart-73b49336-f30b-4922-9282-be6b3b8665aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828780493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3828780493
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.4206002879
Short name T287
Test name
Test status
Simulation time 324557028931 ps
CPU time 1010.21 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:44:30 PM PDT 24
Peak memory 195780 kb
Host smart-7e261bf8-47bf-43e1-a450-5a94fdcaf083
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206002879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.4206002879
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1741370182
Short name T301
Test name
Test status
Simulation time 808222830268 ps
CPU time 1088.19 seconds
Started Aug 11 06:27:45 PM PDT 24
Finished Aug 11 06:45:53 PM PDT 24
Peak memory 196544 kb
Host smart-5cbf791a-4b04-4dc8-878b-e6ae1a457785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741370182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1741370182
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/179.rv_timer_random.1698984696
Short name T191
Test name
Test status
Simulation time 142592566992 ps
CPU time 207.97 seconds
Started Aug 11 06:29:24 PM PDT 24
Finished Aug 11 06:32:52 PM PDT 24
Peak memory 193660 kb
Host smart-6bd791b3-f7d3-4ecf-903a-b8a9a666e6cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698984696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1698984696
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random.3483419187
Short name T240
Test name
Test status
Simulation time 282383229972 ps
CPU time 600.15 seconds
Started Aug 11 06:27:44 PM PDT 24
Finished Aug 11 06:37:44 PM PDT 24
Peak memory 191680 kb
Host smart-1c607310-0721-445b-8bdc-a078651fc1e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483419187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3483419187
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random.1024363286
Short name T220
Test name
Test status
Simulation time 431888746949 ps
CPU time 647.25 seconds
Started Aug 11 06:28:09 PM PDT 24
Finished Aug 11 06:38:56 PM PDT 24
Peak memory 191660 kb
Host smart-e2999d74-e7b0-4bce-9593-3484f6bb947b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024363286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1024363286
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3093423353
Short name T242
Test name
Test status
Simulation time 937350154839 ps
CPU time 652.32 seconds
Started Aug 11 06:28:15 PM PDT 24
Finished Aug 11 06:39:08 PM PDT 24
Peak memory 191608 kb
Host smart-034b50ba-ec67-45d5-86b8-f14fe2007924
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093423353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3093423353
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.4040485150
Short name T297
Test name
Test status
Simulation time 102144861269 ps
CPU time 180.59 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:30:36 PM PDT 24
Peak memory 191592 kb
Host smart-dfec9b73-cbd7-496c-b2ce-9ad894d9c7dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040485150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
4040485150
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/115.rv_timer_random.3610115201
Short name T257
Test name
Test status
Simulation time 69363358904 ps
CPU time 237.99 seconds
Started Aug 11 06:28:23 PM PDT 24
Finished Aug 11 06:32:21 PM PDT 24
Peak memory 191680 kb
Host smart-e0fc5e82-5728-4976-aa89-319acabff63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610115201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3610115201
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1865788515
Short name T335
Test name
Test status
Simulation time 185961892876 ps
CPU time 2234.58 seconds
Started Aug 11 06:28:34 PM PDT 24
Finished Aug 11 07:05:49 PM PDT 24
Peak memory 191524 kb
Host smart-ed45ed20-8092-4913-b385-35bab29bf53a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865788515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1865788515
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2791483306
Short name T177
Test name
Test status
Simulation time 1896681784527 ps
CPU time 524.48 seconds
Started Aug 11 06:29:04 PM PDT 24
Finished Aug 11 06:37:49 PM PDT 24
Peak memory 191628 kb
Host smart-694d92c6-5ad6-4494-87b3-bfe32a952451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791483306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2791483306
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1504678007
Short name T135
Test name
Test status
Simulation time 423636231802 ps
CPU time 872.64 seconds
Started Aug 11 06:29:05 PM PDT 24
Finished Aug 11 06:43:38 PM PDT 24
Peak memory 191656 kb
Host smart-1b1ae0bc-4cc2-4730-89be-cbb19773bba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504678007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1504678007
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.269917517
Short name T71
Test name
Test status
Simulation time 952027657213 ps
CPU time 322.11 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 06:32:59 PM PDT 24
Peak memory 183412 kb
Host smart-a1024936-f2ac-48e0-b664-d40c180f7bc1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269917517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.269917517
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.414480359
Short name T269
Test name
Test status
Simulation time 358833522712 ps
CPU time 304.55 seconds
Started Aug 11 06:27:42 PM PDT 24
Finished Aug 11 06:32:47 PM PDT 24
Peak memory 191624 kb
Host smart-131401a4-67de-4e37-9939-9ed1cbd4e266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414480359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
414480359
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1380394608
Short name T175
Test name
Test status
Simulation time 1685555752155 ps
CPU time 795.92 seconds
Started Aug 11 06:27:32 PM PDT 24
Finished Aug 11 06:40:48 PM PDT 24
Peak memory 183408 kb
Host smart-d2488725-9939-470e-b700-8af59b9a4cd5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380394608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1380394608
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.3365132228
Short name T70
Test name
Test status
Simulation time 172993106453 ps
CPU time 1277.02 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:48:57 PM PDT 24
Peak memory 206280 kb
Host smart-34e9ad26-fb7e-43e9-8fe5-4d3c1890ec6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365132228 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.3365132228
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.3104503005
Short name T211
Test name
Test status
Simulation time 369331443747 ps
CPU time 480.72 seconds
Started Aug 11 06:28:18 PM PDT 24
Finished Aug 11 06:36:19 PM PDT 24
Peak memory 191700 kb
Host smart-dc45877a-f203-4f00-b610-a046abc1347f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104503005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3104503005
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3642865466
Short name T172
Test name
Test status
Simulation time 186521897113 ps
CPU time 796.06 seconds
Started Aug 11 06:28:22 PM PDT 24
Finished Aug 11 06:41:38 PM PDT 24
Peak memory 191656 kb
Host smart-6d567515-8905-44f0-8f2f-f5dcaa953902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642865466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3642865466
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2011649863
Short name T214
Test name
Test status
Simulation time 80260512449 ps
CPU time 113.47 seconds
Started Aug 11 06:28:26 PM PDT 24
Finished Aug 11 06:30:20 PM PDT 24
Peak memory 195276 kb
Host smart-3cb31355-0269-441d-a073-fbbdbfb9d4b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011649863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2011649863
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.2253536214
Short name T200
Test name
Test status
Simulation time 362888253484 ps
CPU time 703.07 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:39:18 PM PDT 24
Peak memory 193876 kb
Host smart-24f61491-51df-48bf-bee6-ab0139f3dc5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253536214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2253536214
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.1830009445
Short name T280
Test name
Test status
Simulation time 658526414659 ps
CPU time 658.56 seconds
Started Aug 11 06:28:34 PM PDT 24
Finished Aug 11 06:39:32 PM PDT 24
Peak memory 191632 kb
Host smart-7a4e0c7f-7a11-4a2e-b6c9-93510a9a65ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830009445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1830009445
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.1542619000
Short name T268
Test name
Test status
Simulation time 109040849201 ps
CPU time 399.49 seconds
Started Aug 11 06:28:50 PM PDT 24
Finished Aug 11 06:35:30 PM PDT 24
Peak memory 191628 kb
Host smart-f5a909ac-6889-40b6-bd8f-f522e83213b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542619000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1542619000
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.261489653
Short name T212
Test name
Test status
Simulation time 652826321589 ps
CPU time 337.76 seconds
Started Aug 11 06:28:12 PM PDT 24
Finished Aug 11 06:33:50 PM PDT 24
Peak memory 183420 kb
Host smart-a53ba50d-41fe-4f1b-8b20-532881d99561
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261489653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.261489653
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2685577357
Short name T247
Test name
Test status
Simulation time 1441962866924 ps
CPU time 747.72 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:40:42 PM PDT 24
Peak memory 183428 kb
Host smart-43c09aa2-416b-4fc2-8c67-37343b3efb71
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685577357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2685577357
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.21732745
Short name T61
Test name
Test status
Simulation time 108958849095 ps
CPU time 286.57 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:33:01 PM PDT 24
Peak memory 191704 kb
Host smart-d654a181-c855-4c16-be27-05fb339c4a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21732745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.21732745
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2251741171
Short name T69
Test name
Test status
Simulation time 442077560447 ps
CPU time 804.19 seconds
Started Aug 11 06:28:13 PM PDT 24
Finished Aug 11 06:41:37 PM PDT 24
Peak memory 191684 kb
Host smart-e0437483-f235-499e-b15d-ac5ff94f184e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251741171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2251741171
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/94.rv_timer_random.1086499402
Short name T74
Test name
Test status
Simulation time 566032931608 ps
CPU time 367.66 seconds
Started Aug 11 06:28:22 PM PDT 24
Finished Aug 11 06:34:30 PM PDT 24
Peak memory 191832 kb
Host smart-435453fb-ddb7-405f-802e-f4e305919c66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086499402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1086499402
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.656790443
Short name T543
Test name
Test status
Simulation time 107139742 ps
CPU time 1.1 seconds
Started Aug 11 06:09:42 PM PDT 24
Finished Aug 11 06:09:43 PM PDT 24
Peak memory 183668 kb
Host smart-7963ab2e-42f7-421c-aaf0-09e5442fc6cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656790443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.656790443
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/116.rv_timer_random.426077825
Short name T190
Test name
Test status
Simulation time 160316149695 ps
CPU time 693.82 seconds
Started Aug 11 06:28:23 PM PDT 24
Finished Aug 11 06:39:57 PM PDT 24
Peak memory 191692 kb
Host smart-f8805dcb-a4e9-4606-9a7c-13341ea3854d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426077825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.426077825
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3744113627
Short name T352
Test name
Test status
Simulation time 111175527609 ps
CPU time 110.44 seconds
Started Aug 11 06:28:26 PM PDT 24
Finished Aug 11 06:30:17 PM PDT 24
Peak memory 191636 kb
Host smart-6ec8e0e0-7af6-49e2-908f-09337beacfb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744113627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3744113627
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2928835991
Short name T237
Test name
Test status
Simulation time 766749602288 ps
CPU time 455.16 seconds
Started Aug 11 06:28:58 PM PDT 24
Finished Aug 11 06:36:33 PM PDT 24
Peak memory 191636 kb
Host smart-b8a031e7-323a-4d99-b992-1da3930e5401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928835991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2928835991
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.3525554387
Short name T155
Test name
Test status
Simulation time 153723079622 ps
CPU time 396.43 seconds
Started Aug 11 06:27:41 PM PDT 24
Finished Aug 11 06:34:18 PM PDT 24
Peak memory 191648 kb
Host smart-42bc49cd-d277-41b2-93de-618c4ec4eebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525554387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3525554387
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.425059890
Short name T179
Test name
Test status
Simulation time 143042141236 ps
CPU time 215.13 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:31:12 PM PDT 24
Peak memory 183380 kb
Host smart-f2710ffc-92bb-46bb-8960-d18607446792
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425059890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.425059890
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2227754989
Short name T222
Test name
Test status
Simulation time 304742214684 ps
CPU time 254.34 seconds
Started Aug 11 06:27:32 PM PDT 24
Finished Aug 11 06:31:47 PM PDT 24
Peak memory 183612 kb
Host smart-e4587c73-9c1d-4133-be70-b3b3beef9a76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227754989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2227754989
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2827625916
Short name T260
Test name
Test status
Simulation time 269536096742 ps
CPU time 144.12 seconds
Started Aug 11 06:27:48 PM PDT 24
Finished Aug 11 06:30:13 PM PDT 24
Peak memory 183432 kb
Host smart-35c09086-a9cc-4dfb-b5da-20295ee5a573
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827625916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2827625916
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3157239934
Short name T180
Test name
Test status
Simulation time 259035554940 ps
CPU time 390.22 seconds
Started Aug 11 06:27:49 PM PDT 24
Finished Aug 11 06:34:19 PM PDT 24
Peak memory 183436 kb
Host smart-baf48b52-b4c2-498c-ba5e-ca8de288794d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157239934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3157239934
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_random.4262254246
Short name T181
Test name
Test status
Simulation time 132322115853 ps
CPU time 538.25 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:37:12 PM PDT 24
Peak memory 191688 kb
Host smart-b011c819-7dbf-43f8-9bd1-42373aaf3432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262254246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.4262254246
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1387226202
Short name T169
Test name
Test status
Simulation time 118963559672 ps
CPU time 723.98 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:40:21 PM PDT 24
Peak memory 195016 kb
Host smart-a058e718-fd60-401a-a403-c3cd5bbd24b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387226202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1387226202
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3790969098
Short name T165
Test name
Test status
Simulation time 567550654696 ps
CPU time 1032.21 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:45:28 PM PDT 24
Peak memory 191632 kb
Host smart-cba3d5c3-f6b7-4da6-bc01-0ffb5edf00ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790969098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3790969098
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3657296106
Short name T298
Test name
Test status
Simulation time 209915105642 ps
CPU time 304.87 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:33:19 PM PDT 24
Peak memory 191652 kb
Host smart-ee854d77-68ce-457b-bf57-6b28e1a4befd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657296106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3657296106
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.4053090721
Short name T241
Test name
Test status
Simulation time 595700803555 ps
CPU time 223.85 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:31:58 PM PDT 24
Peak memory 191660 kb
Host smart-d400289f-756a-4c0a-a52b-1b1bf6953f22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053090721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.4053090721
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.4167911743
Short name T26
Test name
Test status
Simulation time 437151615 ps
CPU time 1.37 seconds
Started Aug 11 06:09:55 PM PDT 24
Finished Aug 11 06:09:56 PM PDT 24
Peak memory 195576 kb
Host smart-b4b6d1d8-7f25-470c-b71e-0cb277c58965
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167911743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.4167911743
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/101.rv_timer_random.2485617488
Short name T151
Test name
Test status
Simulation time 53279815855 ps
CPU time 78.46 seconds
Started Aug 11 06:28:22 PM PDT 24
Finished Aug 11 06:29:41 PM PDT 24
Peak memory 191656 kb
Host smart-de374b13-c935-4abb-aefe-2f7897507312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485617488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2485617488
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2652997916
Short name T262
Test name
Test status
Simulation time 226147263991 ps
CPU time 107.42 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:30:04 PM PDT 24
Peak memory 191624 kb
Host smart-5342f57b-8b03-440f-a7e1-a824ffe3c68f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652997916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2652997916
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.195849602
Short name T21
Test name
Test status
Simulation time 118994009216 ps
CPU time 312.36 seconds
Started Aug 11 06:27:41 PM PDT 24
Finished Aug 11 06:32:54 PM PDT 24
Peak memory 183424 kb
Host smart-881c21af-afd9-4968-accd-1b742e780fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195849602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.195849602
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.1498377638
Short name T124
Test name
Test status
Simulation time 164207435036 ps
CPU time 76.39 seconds
Started Aug 11 06:28:21 PM PDT 24
Finished Aug 11 06:29:38 PM PDT 24
Peak memory 191624 kb
Host smart-02d7c859-a32b-48b5-8d8a-1bcbd1babfac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498377638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1498377638
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.235129510
Short name T146
Test name
Test status
Simulation time 46586753184 ps
CPU time 41.78 seconds
Started Aug 11 06:28:22 PM PDT 24
Finished Aug 11 06:29:04 PM PDT 24
Peak memory 191660 kb
Host smart-3969a0af-a86e-4b27-b45a-8a8255ed8a61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235129510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.235129510
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1066939282
Short name T119
Test name
Test status
Simulation time 212408461850 ps
CPU time 629.64 seconds
Started Aug 11 06:28:23 PM PDT 24
Finished Aug 11 06:38:53 PM PDT 24
Peak memory 195064 kb
Host smart-1d3d41e8-6c02-4aad-b57a-557c16578f4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066939282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1066939282
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1795475895
Short name T104
Test name
Test status
Simulation time 126672699074 ps
CPU time 207.49 seconds
Started Aug 11 06:28:34 PM PDT 24
Finished Aug 11 06:32:01 PM PDT 24
Peak memory 191876 kb
Host smart-3ac820f6-5843-4404-97b0-47ae95b7b19e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795475895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1795475895
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.589091832
Short name T149
Test name
Test status
Simulation time 183041787986 ps
CPU time 446.15 seconds
Started Aug 11 06:28:41 PM PDT 24
Finished Aug 11 06:36:07 PM PDT 24
Peak memory 191696 kb
Host smart-76fe9777-80b7-4171-99f5-23c51ee7d1d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589091832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.589091832
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.4288251179
Short name T115
Test name
Test status
Simulation time 244198562824 ps
CPU time 495.97 seconds
Started Aug 11 06:28:44 PM PDT 24
Finished Aug 11 06:37:00 PM PDT 24
Peak memory 191620 kb
Host smart-8f5951d1-2f77-4c9a-98ec-61e355cf51b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288251179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.4288251179
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3867204205
Short name T308
Test name
Test status
Simulation time 128724735851 ps
CPU time 45.43 seconds
Started Aug 11 06:28:53 PM PDT 24
Finished Aug 11 06:29:38 PM PDT 24
Peak memory 183284 kb
Host smart-574bda60-83fb-4536-866e-cf1f38975b31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867204205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3867204205
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.49896529
Short name T148
Test name
Test status
Simulation time 516085202022 ps
CPU time 432.51 seconds
Started Aug 11 06:27:41 PM PDT 24
Finished Aug 11 06:34:54 PM PDT 24
Peak memory 183468 kb
Host smart-24862262-5a9b-4cee-bb28-484a39e624ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49896529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.rv_timer_cfg_update_on_fly.49896529
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/176.rv_timer_random.1011124611
Short name T78
Test name
Test status
Simulation time 368875453148 ps
CPU time 621.84 seconds
Started Aug 11 06:29:22 PM PDT 24
Finished Aug 11 06:39:45 PM PDT 24
Peak memory 191680 kb
Host smart-89db2806-e31f-4f22-85e6-2bad4a56cbc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011124611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1011124611
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2732082013
Short name T130
Test name
Test status
Simulation time 78481367364 ps
CPU time 79.03 seconds
Started Aug 11 06:29:21 PM PDT 24
Finished Aug 11 06:30:40 PM PDT 24
Peak memory 191648 kb
Host smart-65397b89-19f2-420e-b0f9-e2e291ab3741
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732082013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2732082013
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3108799384
Short name T158
Test name
Test status
Simulation time 68071014568 ps
CPU time 105.38 seconds
Started Aug 11 06:29:28 PM PDT 24
Finished Aug 11 06:31:14 PM PDT 24
Peak memory 191664 kb
Host smart-f3b6e133-3e76-4de4-a888-5e17577c972b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108799384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3108799384
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.1927511155
Short name T321
Test name
Test status
Simulation time 167895854052 ps
CPU time 233.27 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:31:31 PM PDT 24
Peak memory 191652 kb
Host smart-c5d3722d-4d4a-493a-abcf-8e0686a3bd72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927511155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1927511155
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2511069597
Short name T31
Test name
Test status
Simulation time 405237523961 ps
CPU time 338.49 seconds
Started Aug 11 06:27:45 PM PDT 24
Finished Aug 11 06:33:23 PM PDT 24
Peak memory 191664 kb
Host smart-1110a062-a9ed-476f-b6d3-fa092c0c5ee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511069597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2511069597
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_random.3323156559
Short name T59
Test name
Test status
Simulation time 518473211545 ps
CPU time 271.48 seconds
Started Aug 11 06:27:41 PM PDT 24
Finished Aug 11 06:32:13 PM PDT 24
Peak memory 191704 kb
Host smart-b557d354-b4ef-45e7-a853-e9482ba3ce65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323156559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3323156559
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.898538437
Short name T310
Test name
Test status
Simulation time 462695477403 ps
CPU time 214.11 seconds
Started Aug 11 06:27:48 PM PDT 24
Finished Aug 11 06:31:22 PM PDT 24
Peak memory 191688 kb
Host smart-aa9e883a-1d61-4a1b-89c7-37db0bcd14c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898538437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.898538437
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1731392685
Short name T189
Test name
Test status
Simulation time 156310777690 ps
CPU time 140.86 seconds
Started Aug 11 06:27:54 PM PDT 24
Finished Aug 11 06:30:15 PM PDT 24
Peak memory 183468 kb
Host smart-4563b456-fc99-4cfc-bccb-77bb9196bc0f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731392685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1731392685
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.746969764
Short name T281
Test name
Test status
Simulation time 3464680380527 ps
CPU time 1735.19 seconds
Started Aug 11 06:28:05 PM PDT 24
Finished Aug 11 06:57:01 PM PDT 24
Peak memory 196064 kb
Host smart-8b384d2f-dfa9-4bff-a44a-62a8e5b8cb51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746969764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
746969764
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_random.730500769
Short name T332
Test name
Test status
Simulation time 25960138152 ps
CPU time 35.06 seconds
Started Aug 11 06:28:13 PM PDT 24
Finished Aug 11 06:28:48 PM PDT 24
Peak memory 183260 kb
Host smart-284dbf1e-fe52-46e4-958d-119cb3392a3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730500769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.730500769
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2887440757
Short name T160
Test name
Test status
Simulation time 1108524754942 ps
CPU time 513.24 seconds
Started Aug 11 06:28:17 PM PDT 24
Finished Aug 11 06:36:51 PM PDT 24
Peak memory 191644 kb
Host smart-a733641e-4dd4-4612-945c-17c31f1896a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887440757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2887440757
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1161762261
Short name T147
Test name
Test status
Simulation time 120427274346 ps
CPU time 1675.28 seconds
Started Aug 11 06:28:18 PM PDT 24
Finished Aug 11 06:56:13 PM PDT 24
Peak memory 191516 kb
Host smart-00813e00-4ee4-49e2-8ac1-2294cee12130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161762261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1161762261
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.871156719
Short name T539
Test name
Test status
Simulation time 16273318 ps
CPU time 0.67 seconds
Started Aug 11 06:09:28 PM PDT 24
Finished Aug 11 06:09:28 PM PDT 24
Peak memory 182948 kb
Host smart-675eb8c9-6897-4192-b508-74fb6d2a8de7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871156719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.871156719
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.4120158187
Short name T27
Test name
Test status
Simulation time 3136147234 ps
CPU time 3.68 seconds
Started Aug 11 06:09:39 PM PDT 24
Finished Aug 11 06:09:43 PM PDT 24
Peak memory 191296 kb
Host smart-1e831b7e-4342-4e75-bb4b-1e156de76464
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120158187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.4120158187
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3042440633
Short name T485
Test name
Test status
Simulation time 14010207 ps
CPU time 0.55 seconds
Started Aug 11 06:09:47 PM PDT 24
Finished Aug 11 06:09:48 PM PDT 24
Peak memory 182460 kb
Host smart-bfc36e6d-3dd2-453c-983a-76b4677c60f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042440633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3042440633
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2438269440
Short name T471
Test name
Test status
Simulation time 39417061 ps
CPU time 0.61 seconds
Started Aug 11 06:09:42 PM PDT 24
Finished Aug 11 06:09:43 PM PDT 24
Peak memory 193340 kb
Host smart-7c9953fa-7918-4eda-8ce1-8357e9eac560
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438269440 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2438269440
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3018825689
Short name T81
Test name
Test status
Simulation time 16836376 ps
CPU time 0.57 seconds
Started Aug 11 06:09:30 PM PDT 24
Finished Aug 11 06:09:31 PM PDT 24
Peak memory 182852 kb
Host smart-15adda75-541b-499d-9dd5-23c30fd52004
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018825689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3018825689
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1444809553
Short name T521
Test name
Test status
Simulation time 32170117 ps
CPU time 0.52 seconds
Started Aug 11 06:09:30 PM PDT 24
Finished Aug 11 06:09:30 PM PDT 24
Peak memory 182692 kb
Host smart-b2822b7b-7dbb-4aae-b40a-49d6f99c0618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444809553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1444809553
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4124775081
Short name T28
Test name
Test status
Simulation time 18682978 ps
CPU time 0.78 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 191892 kb
Host smart-7f7064e7-a7b1-421d-91df-accebf3609bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124775081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.4124775081
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3009112026
Short name T467
Test name
Test status
Simulation time 44868143 ps
CPU time 2.36 seconds
Started Aug 11 06:09:27 PM PDT 24
Finished Aug 11 06:09:30 PM PDT 24
Peak memory 197632 kb
Host smart-ece8d250-3f87-410f-b188-9663b74e0475
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009112026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3009112026
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1602164760
Short name T93
Test name
Test status
Simulation time 75473708 ps
CPU time 0.83 seconds
Started Aug 11 06:09:45 PM PDT 24
Finished Aug 11 06:09:46 PM PDT 24
Peak memory 182964 kb
Host smart-7a64a53e-34de-46c7-a369-72b8f104321b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602164760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1602164760
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2018290374
Short name T519
Test name
Test status
Simulation time 1114992358 ps
CPU time 3.51 seconds
Started Aug 11 06:09:44 PM PDT 24
Finished Aug 11 06:09:48 PM PDT 24
Peak memory 194124 kb
Host smart-cc6c02ed-cdec-4c03-a8c8-92c10620407c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018290374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2018290374
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.285024683
Short name T49
Test name
Test status
Simulation time 22849317 ps
CPU time 0.54 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 182296 kb
Host smart-ea37f0c6-d1c6-478e-b5f5-d1af3629a6b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285024683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.285024683
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2858720532
Short name T472
Test name
Test status
Simulation time 33339955 ps
CPU time 0.68 seconds
Started Aug 11 06:09:29 PM PDT 24
Finished Aug 11 06:09:30 PM PDT 24
Peak memory 195068 kb
Host smart-839fecbf-f1c7-4ac9-881c-abf35b4555c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858720532 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2858720532
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.233609269
Short name T94
Test name
Test status
Simulation time 11608488 ps
CPU time 0.56 seconds
Started Aug 11 06:09:27 PM PDT 24
Finished Aug 11 06:09:27 PM PDT 24
Peak memory 182800 kb
Host smart-ddbc32ee-2123-456c-bba1-97e126cec5c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233609269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.233609269
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2634405135
Short name T522
Test name
Test status
Simulation time 28635648 ps
CPU time 0.54 seconds
Started Aug 11 06:09:44 PM PDT 24
Finished Aug 11 06:09:45 PM PDT 24
Peak memory 182656 kb
Host smart-8bbc10bd-fa76-45c1-b357-df80e48da6ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634405135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2634405135
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.209643780
Short name T502
Test name
Test status
Simulation time 87007367 ps
CPU time 0.61 seconds
Started Aug 11 06:09:29 PM PDT 24
Finished Aug 11 06:09:30 PM PDT 24
Peak memory 191740 kb
Host smart-5bf2bfe8-bb7f-4dee-9af1-e18f62130405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209643780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.209643780
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.4142948632
Short name T50
Test name
Test status
Simulation time 278616279 ps
CPU time 2.46 seconds
Started Aug 11 06:09:28 PM PDT 24
Finished Aug 11 06:09:31 PM PDT 24
Peak memory 197596 kb
Host smart-438fafc1-f5fc-4163-aa68-50dcc00ca95a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142948632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.4142948632
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3592479255
Short name T494
Test name
Test status
Simulation time 46551940 ps
CPU time 0.84 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 193916 kb
Host smart-36cfbf61-bdbd-4a92-bb0f-1490948ce9e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592479255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3592479255
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3053471328
Short name T561
Test name
Test status
Simulation time 143527101 ps
CPU time 0.89 seconds
Started Aug 11 06:09:44 PM PDT 24
Finished Aug 11 06:09:45 PM PDT 24
Peak memory 196480 kb
Host smart-c0cc3134-3407-4920-951b-3c96adc6efa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053471328 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3053471328
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.613131326
Short name T91
Test name
Test status
Simulation time 13689732 ps
CPU time 0.59 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:49 PM PDT 24
Peak memory 182920 kb
Host smart-c2876a20-67e7-4e22-b50c-5b74925b3912
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613131326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.613131326
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1694949275
Short name T449
Test name
Test status
Simulation time 48702104 ps
CPU time 0.53 seconds
Started Aug 11 06:09:52 PM PDT 24
Finished Aug 11 06:09:53 PM PDT 24
Peak memory 182372 kb
Host smart-7d26aeff-55ff-490e-8b6b-e94daeb911a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694949275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1694949275
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.829068139
Short name T524
Test name
Test status
Simulation time 15027392 ps
CPU time 0.68 seconds
Started Aug 11 06:09:39 PM PDT 24
Finished Aug 11 06:09:40 PM PDT 24
Peak memory 191656 kb
Host smart-7ad45287-447c-48fe-b38e-6f20a7e9402f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829068139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.829068139
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2057180432
Short name T516
Test name
Test status
Simulation time 103469986 ps
CPU time 2.18 seconds
Started Aug 11 06:09:47 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 197668 kb
Host smart-104d6bf9-c96f-45ab-88d8-ca0931ed56a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057180432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2057180432
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.27350122
Short name T497
Test name
Test status
Simulation time 97333858 ps
CPU time 1.06 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:49 PM PDT 24
Peak memory 195428 kb
Host smart-04235b4b-9cda-4ee8-b12f-14de3bdf7c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27350122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_int
g_err.27350122
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1034487753
Short name T542
Test name
Test status
Simulation time 25927299 ps
CPU time 1.18 seconds
Started Aug 11 06:09:38 PM PDT 24
Finished Aug 11 06:09:39 PM PDT 24
Peak memory 197648 kb
Host smart-584a2312-9375-46fb-abe2-6bd8bfa29532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034487753 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1034487753
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1550300766
Short name T92
Test name
Test status
Simulation time 22268308 ps
CPU time 0.58 seconds
Started Aug 11 06:09:54 PM PDT 24
Finished Aug 11 06:09:54 PM PDT 24
Peak memory 182968 kb
Host smart-802c929a-2103-4315-8d39-a844311ac04e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550300766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1550300766
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1995341834
Short name T451
Test name
Test status
Simulation time 56236537 ps
CPU time 0.54 seconds
Started Aug 11 06:09:39 PM PDT 24
Finished Aug 11 06:09:39 PM PDT 24
Peak memory 182728 kb
Host smart-5ba69c4a-7a20-4057-b170-11f8f1518f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995341834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1995341834
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.4137848764
Short name T87
Test name
Test status
Simulation time 61353148 ps
CPU time 0.7 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:49 PM PDT 24
Peak memory 191904 kb
Host smart-015c6a01-de67-402b-8229-865b74c03f1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137848764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.4137848764
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3499458419
Short name T483
Test name
Test status
Simulation time 151604527 ps
CPU time 2.94 seconds
Started Aug 11 06:09:37 PM PDT 24
Finished Aug 11 06:09:40 PM PDT 24
Peak memory 197684 kb
Host smart-04ae6dd2-206b-4cb2-89d2-cbf5df18f628
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499458419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3499458419
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1279953811
Short name T498
Test name
Test status
Simulation time 72525384 ps
CPU time 1.05 seconds
Started Aug 11 06:09:45 PM PDT 24
Finished Aug 11 06:09:46 PM PDT 24
Peak memory 183320 kb
Host smart-70fa00b2-7744-43ba-8151-c5e1c19d60d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279953811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1279953811
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2302842089
Short name T455
Test name
Test status
Simulation time 52528047 ps
CPU time 1.21 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 197644 kb
Host smart-4f430b5b-cbe5-454e-8175-ef9544308b7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302842089 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2302842089
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1502492587
Short name T523
Test name
Test status
Simulation time 20236970 ps
CPU time 0.56 seconds
Started Aug 11 06:09:38 PM PDT 24
Finished Aug 11 06:09:38 PM PDT 24
Peak memory 182836 kb
Host smart-83a1df54-dbc0-441c-9137-04f6324f68a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502492587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1502492587
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2178095726
Short name T461
Test name
Test status
Simulation time 40764373 ps
CPU time 0.52 seconds
Started Aug 11 06:09:39 PM PDT 24
Finished Aug 11 06:09:39 PM PDT 24
Peak memory 182400 kb
Host smart-199afb47-ac8d-41d4-8dae-b16ce5bd7f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178095726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2178095726
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1188492646
Short name T532
Test name
Test status
Simulation time 71499393 ps
CPU time 0.81 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:49 PM PDT 24
Peak memory 194792 kb
Host smart-660eec1f-4148-4738-9947-29c31c760faf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188492646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1188492646
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.609820986
Short name T571
Test name
Test status
Simulation time 132209377 ps
CPU time 1.7 seconds
Started Aug 11 06:09:52 PM PDT 24
Finished Aug 11 06:09:54 PM PDT 24
Peak memory 197688 kb
Host smart-3ce02165-48ec-4cf3-bbe1-9ed36ffd2fc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609820986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.609820986
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3130196629
Short name T546
Test name
Test status
Simulation time 147252685 ps
CPU time 0.79 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 183312 kb
Host smart-ae69caaa-056a-4679-af94-2487c49468b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130196629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3130196629
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2669693558
Short name T558
Test name
Test status
Simulation time 25228733 ps
CPU time 1.11 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 197824 kb
Host smart-52a475f8-a7c0-415f-8024-dba2e5a7a675
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669693558 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2669693558
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3816138304
Short name T565
Test name
Test status
Simulation time 12196654 ps
CPU time 0.53 seconds
Started Aug 11 06:09:45 PM PDT 24
Finished Aug 11 06:09:45 PM PDT 24
Peak memory 182644 kb
Host smart-9013c338-2fd7-4d6e-9c1e-0cc32d85281b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816138304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3816138304
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3138492612
Short name T564
Test name
Test status
Simulation time 13838581 ps
CPU time 0.56 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 182724 kb
Host smart-f6507720-4fe2-429e-b9f7-9c650acc4b11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138492612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3138492612
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2781421490
Short name T567
Test name
Test status
Simulation time 91046792 ps
CPU time 0.61 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:00 PM PDT 24
Peak memory 191844 kb
Host smart-7e67bdff-9652-4309-9050-041de582cc0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781421490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2781421490
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3139108238
Short name T476
Test name
Test status
Simulation time 2804040522 ps
CPU time 3.18 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:53 PM PDT 24
Peak memory 197652 kb
Host smart-b50aeeb3-2484-42cf-b970-0cebe8b5f773
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139108238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3139108238
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.929902520
Short name T109
Test name
Test status
Simulation time 618496815 ps
CPU time 1.18 seconds
Started Aug 11 06:09:47 PM PDT 24
Finished Aug 11 06:09:48 PM PDT 24
Peak memory 183372 kb
Host smart-9d740caa-3666-49b8-b23c-5982ed419ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929902520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.929902520
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4283559247
Short name T566
Test name
Test status
Simulation time 28154542 ps
CPU time 0.78 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 195480 kb
Host smart-1f913e7b-d9e2-44d4-8d13-2a5614626024
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283559247 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4283559247
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.4162396925
Short name T453
Test name
Test status
Simulation time 103289682 ps
CPU time 0.54 seconds
Started Aug 11 06:09:45 PM PDT 24
Finished Aug 11 06:09:46 PM PDT 24
Peak memory 182580 kb
Host smart-42b9300f-453b-4af0-a2c6-157b4a4a8f41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162396925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.4162396925
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.697306408
Short name T555
Test name
Test status
Simulation time 66400198 ps
CPU time 0.61 seconds
Started Aug 11 06:09:41 PM PDT 24
Finished Aug 11 06:09:41 PM PDT 24
Peak memory 192360 kb
Host smart-6f03c6e6-42a8-4ca1-8489-12312a5d66e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697306408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.697306408
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1627499877
Short name T474
Test name
Test status
Simulation time 255638716 ps
CPU time 0.86 seconds
Started Aug 11 06:09:47 PM PDT 24
Finished Aug 11 06:09:48 PM PDT 24
Peak memory 196128 kb
Host smart-ec0aeccd-c67d-4634-9bdd-d75c18c31131
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627499877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1627499877
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1506647590
Short name T538
Test name
Test status
Simulation time 157748122 ps
CPU time 0.87 seconds
Started Aug 11 06:09:41 PM PDT 24
Finished Aug 11 06:09:42 PM PDT 24
Peak memory 193808 kb
Host smart-925b50b1-5137-461a-9a62-94d3c0a8bdb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506647590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1506647590
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3105117586
Short name T460
Test name
Test status
Simulation time 80908346 ps
CPU time 1.03 seconds
Started Aug 11 06:09:46 PM PDT 24
Finished Aug 11 06:09:47 PM PDT 24
Peak memory 196836 kb
Host smart-6032ddcb-72cc-4726-9975-e1355dfe27bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105117586 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3105117586
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1859606308
Short name T88
Test name
Test status
Simulation time 23854362 ps
CPU time 0.56 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:49 PM PDT 24
Peak memory 182824 kb
Host smart-49f4bc5d-76f7-4ff1-8ac4-e41da4fc8b3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859606308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1859606308
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2408147073
Short name T552
Test name
Test status
Simulation time 14651006 ps
CPU time 0.55 seconds
Started Aug 11 06:09:41 PM PDT 24
Finished Aug 11 06:09:41 PM PDT 24
Peak memory 182784 kb
Host smart-d140b94f-ac11-4044-84c8-54768ff095cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408147073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2408147073
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.700398664
Short name T82
Test name
Test status
Simulation time 18611812 ps
CPU time 0.66 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 192148 kb
Host smart-be7e3282-3d67-43a3-b9ba-0e051df80e0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700398664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.700398664
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3247542858
Short name T457
Test name
Test status
Simulation time 59026208 ps
CPU time 1.37 seconds
Started Aug 11 06:09:46 PM PDT 24
Finished Aug 11 06:09:48 PM PDT 24
Peak memory 196448 kb
Host smart-111aa14d-5431-4f64-af3b-59259eae4d37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247542858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3247542858
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.547055802
Short name T549
Test name
Test status
Simulation time 96189271 ps
CPU time 0.83 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 193484 kb
Host smart-592a6fa3-fa35-4ff4-872e-8698cb59e223
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547055802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.547055802
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2620489445
Short name T577
Test name
Test status
Simulation time 97987884 ps
CPU time 0.78 seconds
Started Aug 11 06:09:52 PM PDT 24
Finished Aug 11 06:09:53 PM PDT 24
Peak memory 196376 kb
Host smart-1f4c3238-b932-4388-9c12-c1b0723e8870
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620489445 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2620489445
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4247574726
Short name T505
Test name
Test status
Simulation time 12695142 ps
CPU time 0.56 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 182616 kb
Host smart-d9e2c81d-6482-45ea-854f-1f70765a7c74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247574726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4247574726
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.494762708
Short name T527
Test name
Test status
Simulation time 38373046 ps
CPU time 0.55 seconds
Started Aug 11 06:09:41 PM PDT 24
Finished Aug 11 06:09:42 PM PDT 24
Peak memory 182276 kb
Host smart-42effc51-ffdc-4d94-88c3-b68d7511b863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494762708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.494762708
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1428856804
Short name T84
Test name
Test status
Simulation time 43005578 ps
CPU time 0.82 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 193568 kb
Host smart-f33ace76-9c55-4005-9acc-c2e01d4bb686
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428856804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1428856804
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.601501427
Short name T459
Test name
Test status
Simulation time 1144167876 ps
CPU time 1.74 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 197864 kb
Host smart-4e655d40-0b67-4604-91a3-3f846527507c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601501427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.601501427
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3798387793
Short name T545
Test name
Test status
Simulation time 64938637 ps
CPU time 0.79 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:01 PM PDT 24
Peak memory 196012 kb
Host smart-b305cf49-7773-4662-905e-6bd2670feb2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798387793 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3798387793
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.146577
Short name T486
Test name
Test status
Simulation time 68973550 ps
CPU time 0.52 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:49 PM PDT 24
Peak memory 182632 kb
Host smart-7eff91d7-3009-45dc-b7b3-1d6ed77f8ed9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.146577
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1973720621
Short name T501
Test name
Test status
Simulation time 19657840 ps
CPU time 0.61 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 182724 kb
Host smart-8c85f172-9da1-40de-9656-ce0f9f80570f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973720621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1973720621
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3055588581
Short name T86
Test name
Test status
Simulation time 136063139 ps
CPU time 0.8 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 193620 kb
Host smart-2294c37c-082d-4b7e-b4d4-8a4d7975a96e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055588581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3055588581
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2102172399
Short name T62
Test name
Test status
Simulation time 119195650 ps
CPU time 1.51 seconds
Started Aug 11 06:09:55 PM PDT 24
Finished Aug 11 06:09:57 PM PDT 24
Peak memory 197636 kb
Host smart-b0bc665b-e7c3-4826-8763-93ab342eae7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102172399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2102172399
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1709397481
Short name T487
Test name
Test status
Simulation time 189578165 ps
CPU time 0.85 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 183412 kb
Host smart-37384c80-f85d-4e9d-9062-f1f646c95a55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709397481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1709397481
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3929259053
Short name T52
Test name
Test status
Simulation time 24579452 ps
CPU time 0.69 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 195308 kb
Host smart-db142e7d-855a-4dc2-88d9-93cd2be23bfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929259053 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3929259053
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2164026311
Short name T563
Test name
Test status
Simulation time 52481200 ps
CPU time 0.58 seconds
Started Aug 11 06:09:57 PM PDT 24
Finished Aug 11 06:09:57 PM PDT 24
Peak memory 182952 kb
Host smart-295658b0-6d1a-41fc-ba7d-ff111f410020
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164026311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2164026311
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2606666780
Short name T478
Test name
Test status
Simulation time 45251187 ps
CPU time 0.53 seconds
Started Aug 11 06:09:54 PM PDT 24
Finished Aug 11 06:09:55 PM PDT 24
Peak memory 182272 kb
Host smart-562ccbd2-0f92-4cc5-b482-cd23d66d57ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606666780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2606666780
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1078991278
Short name T556
Test name
Test status
Simulation time 19849429 ps
CPU time 0.75 seconds
Started Aug 11 06:09:54 PM PDT 24
Finished Aug 11 06:09:55 PM PDT 24
Peak memory 193580 kb
Host smart-578a7636-c17e-49b1-baaf-f6e846c6683c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078991278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1078991278
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2915675885
Short name T575
Test name
Test status
Simulation time 433396438 ps
CPU time 2.44 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 197672 kb
Host smart-f214eda8-b1ba-43e8-b0b3-da9d08783186
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915675885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2915675885
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.23833085
Short name T503
Test name
Test status
Simulation time 259865123 ps
CPU time 1.05 seconds
Started Aug 11 06:09:45 PM PDT 24
Finished Aug 11 06:09:46 PM PDT 24
Peak memory 195036 kb
Host smart-0f470ea9-9fe5-4cef-a254-2ba6aa941b2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23833085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_int
g_err.23833085
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2774063090
Short name T484
Test name
Test status
Simulation time 38522312 ps
CPU time 1.71 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 197756 kb
Host smart-e128f98a-9bd3-4737-b968-aeb53e99cde7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774063090 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2774063090
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2916039607
Short name T562
Test name
Test status
Simulation time 95647453 ps
CPU time 0.57 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 182976 kb
Host smart-6bd22647-7c90-44f0-96c4-e6411557fe97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916039607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2916039607
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1728197159
Short name T496
Test name
Test status
Simulation time 38700644 ps
CPU time 0.55 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 182660 kb
Host smart-e8e01667-cc75-4eca-8f98-a14ed597b2d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728197159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1728197159
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1821878638
Short name T85
Test name
Test status
Simulation time 21554310 ps
CPU time 0.69 seconds
Started Aug 11 06:09:58 PM PDT 24
Finished Aug 11 06:09:59 PM PDT 24
Peak memory 191492 kb
Host smart-7c7b8a1e-3733-4566-b165-e4bcfbbb8bdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821878638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1821878638
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3916442928
Short name T525
Test name
Test status
Simulation time 157642840 ps
CPU time 1.8 seconds
Started Aug 11 06:09:47 PM PDT 24
Finished Aug 11 06:09:49 PM PDT 24
Peak memory 197636 kb
Host smart-17f8caeb-4a6a-4fc6-9936-4c6c8d764815
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916442928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3916442928
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2553606946
Short name T534
Test name
Test status
Simulation time 48763259 ps
CPU time 0.63 seconds
Started Aug 11 06:09:34 PM PDT 24
Finished Aug 11 06:09:34 PM PDT 24
Peak memory 182908 kb
Host smart-604fa7e8-03d6-4f9b-b18e-f5258bc040a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553606946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2553606946
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1060650210
Short name T481
Test name
Test status
Simulation time 191902757 ps
CPU time 1.5 seconds
Started Aug 11 06:09:28 PM PDT 24
Finished Aug 11 06:09:30 PM PDT 24
Peak memory 193068 kb
Host smart-90c77aed-b72f-4543-8b78-357635015d62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060650210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1060650210
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.331604854
Short name T492
Test name
Test status
Simulation time 15041499 ps
CPU time 0.58 seconds
Started Aug 11 06:09:35 PM PDT 24
Finished Aug 11 06:09:36 PM PDT 24
Peak memory 182440 kb
Host smart-0efe72b9-fd96-4bbb-8aa5-d0f0efe69267
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331604854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.331604854
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3476981661
Short name T569
Test name
Test status
Simulation time 89877472 ps
CPU time 0.82 seconds
Started Aug 11 06:09:29 PM PDT 24
Finished Aug 11 06:09:30 PM PDT 24
Peak memory 195856 kb
Host smart-bccc8c4f-afd1-4300-8482-2e28fc04f969
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476981661 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3476981661
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2528259519
Short name T80
Test name
Test status
Simulation time 12647995 ps
CPU time 0.54 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:48 PM PDT 24
Peak memory 182940 kb
Host smart-0c623a0d-6482-4e00-8df1-220951cee6b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528259519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2528259519
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2516426635
Short name T535
Test name
Test status
Simulation time 12537879 ps
CPU time 0.56 seconds
Started Aug 11 06:09:27 PM PDT 24
Finished Aug 11 06:09:28 PM PDT 24
Peak memory 182816 kb
Host smart-1415342a-acd1-4137-9a2a-bddfe16eb149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516426635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2516426635
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4231062007
Short name T29
Test name
Test status
Simulation time 25944627 ps
CPU time 0.73 seconds
Started Aug 11 06:09:47 PM PDT 24
Finished Aug 11 06:09:48 PM PDT 24
Peak memory 192464 kb
Host smart-8de87981-9107-4fe7-a97f-999cb0ddfc2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231062007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.4231062007
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.459005235
Short name T48
Test name
Test status
Simulation time 118148709 ps
CPU time 2.2 seconds
Started Aug 11 06:09:31 PM PDT 24
Finished Aug 11 06:09:33 PM PDT 24
Peak memory 197676 kb
Host smart-da3d4d72-0b51-44f3-bc24-afd9db245609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459005235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.459005235
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.407445399
Short name T510
Test name
Test status
Simulation time 79888116 ps
CPU time 0.82 seconds
Started Aug 11 06:09:31 PM PDT 24
Finished Aug 11 06:09:32 PM PDT 24
Peak memory 193464 kb
Host smart-84ec216d-4dd5-4ca9-9c49-e3e229db49ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407445399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.407445399
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.138075024
Short name T479
Test name
Test status
Simulation time 63296205 ps
CPU time 0.57 seconds
Started Aug 11 06:09:46 PM PDT 24
Finished Aug 11 06:09:47 PM PDT 24
Peak memory 182736 kb
Host smart-24872f85-703f-4798-a5a4-829588198fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138075024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.138075024
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.713194105
Short name T548
Test name
Test status
Simulation time 13406867 ps
CPU time 0.55 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 182660 kb
Host smart-4842f38a-59f6-42d2-94f4-ddabebab5ca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713194105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.713194105
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.439666211
Short name T533
Test name
Test status
Simulation time 15131233 ps
CPU time 0.56 seconds
Started Aug 11 06:09:44 PM PDT 24
Finished Aug 11 06:09:45 PM PDT 24
Peak memory 182220 kb
Host smart-47df1b0f-a190-4bd6-b953-c9fdfc306731
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439666211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.439666211
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3552811900
Short name T520
Test name
Test status
Simulation time 62510900 ps
CPU time 0.63 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:00 PM PDT 24
Peak memory 182716 kb
Host smart-35a1ca91-64ba-4b63-91f5-69cd2f54b083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552811900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3552811900
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1678383564
Short name T464
Test name
Test status
Simulation time 46590223 ps
CPU time 0.55 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:49 PM PDT 24
Peak memory 182656 kb
Host smart-d3d431c1-bf0b-4e4e-8228-11c0ba5dcf05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678383564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1678383564
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1390801304
Short name T540
Test name
Test status
Simulation time 48262876 ps
CPU time 0.54 seconds
Started Aug 11 06:09:53 PM PDT 24
Finished Aug 11 06:09:53 PM PDT 24
Peak memory 182208 kb
Host smart-3afca003-1d1d-4243-9244-3e62b22f4a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390801304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1390801304
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.308285774
Short name T491
Test name
Test status
Simulation time 97821049 ps
CPU time 0.52 seconds
Started Aug 11 06:09:47 PM PDT 24
Finished Aug 11 06:09:48 PM PDT 24
Peak memory 182116 kb
Host smart-65ccc8a3-db9e-4719-8200-d62e7da81430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308285774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.308285774
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3320912535
Short name T499
Test name
Test status
Simulation time 22386043 ps
CPU time 0.54 seconds
Started Aug 11 06:10:02 PM PDT 24
Finished Aug 11 06:10:03 PM PDT 24
Peak memory 182256 kb
Host smart-145dcdda-8d5c-486d-919b-6ab0160cce06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320912535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3320912535
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.691114822
Short name T511
Test name
Test status
Simulation time 41413344 ps
CPU time 0.52 seconds
Started Aug 11 06:09:47 PM PDT 24
Finished Aug 11 06:09:47 PM PDT 24
Peak memory 182384 kb
Host smart-6b4f142b-6e1a-49c9-814f-e94ddf9cc256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691114822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.691114822
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2016746928
Short name T450
Test name
Test status
Simulation time 53623485 ps
CPU time 0.57 seconds
Started Aug 11 06:09:57 PM PDT 24
Finished Aug 11 06:09:58 PM PDT 24
Peak memory 182780 kb
Host smart-989f0333-cead-4247-aa1d-15d29f968ee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016746928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2016746928
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.856529002
Short name T488
Test name
Test status
Simulation time 29308959 ps
CPU time 0.83 seconds
Started Aug 11 06:09:29 PM PDT 24
Finished Aug 11 06:09:30 PM PDT 24
Peak memory 192884 kb
Host smart-658f54d6-bced-488a-b09c-a83ab8d652c9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856529002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.856529002
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1380011853
Short name T576
Test name
Test status
Simulation time 67018017 ps
CPU time 2.38 seconds
Started Aug 11 06:09:33 PM PDT 24
Finished Aug 11 06:09:35 PM PDT 24
Peak memory 191304 kb
Host smart-0a29ba69-cde9-44ca-ba31-9c860dd4d264
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380011853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1380011853
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4206069776
Short name T90
Test name
Test status
Simulation time 13555223 ps
CPU time 0.56 seconds
Started Aug 11 06:09:28 PM PDT 24
Finished Aug 11 06:09:29 PM PDT 24
Peak memory 182916 kb
Host smart-5d57d376-67b6-4973-b2f4-ddf6bcf250fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206069776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4206069776
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2550511503
Short name T470
Test name
Test status
Simulation time 61776751 ps
CPU time 0.88 seconds
Started Aug 11 06:09:54 PM PDT 24
Finished Aug 11 06:09:54 PM PDT 24
Peak memory 197560 kb
Host smart-b8915f9c-16a1-4ac1-bbef-bd79d2e8742a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550511503 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2550511503
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2196440549
Short name T550
Test name
Test status
Simulation time 120314420 ps
CPU time 0.54 seconds
Started Aug 11 06:09:29 PM PDT 24
Finished Aug 11 06:09:30 PM PDT 24
Peak memory 182980 kb
Host smart-a2fc9a78-1dd8-4790-b628-2cd0dfa57c95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196440549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2196440549
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1027681087
Short name T482
Test name
Test status
Simulation time 39921790 ps
CPU time 0.52 seconds
Started Aug 11 06:09:37 PM PDT 24
Finished Aug 11 06:09:38 PM PDT 24
Peak memory 182380 kb
Host smart-3538b97b-f35e-412f-b23a-8492b2bab4e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027681087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1027681087
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.138185417
Short name T96
Test name
Test status
Simulation time 27865469 ps
CPU time 0.69 seconds
Started Aug 11 06:09:46 PM PDT 24
Finished Aug 11 06:09:47 PM PDT 24
Peak memory 192396 kb
Host smart-e0cb049f-4fc9-4fef-beb4-46c6455bd201
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138185417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.138185417
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2575204513
Short name T506
Test name
Test status
Simulation time 52498973 ps
CPU time 2.47 seconds
Started Aug 11 06:09:37 PM PDT 24
Finished Aug 11 06:09:40 PM PDT 24
Peak memory 197764 kb
Host smart-b4c56a4e-4a9a-4d41-ac2d-0119ded5188c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575204513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2575204513
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.384608402
Short name T557
Test name
Test status
Simulation time 3869002403 ps
CPU time 1.48 seconds
Started Aug 11 06:09:40 PM PDT 24
Finished Aug 11 06:09:41 PM PDT 24
Peak memory 183704 kb
Host smart-6d7039bf-4eec-4831-a748-145daa4f57cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384608402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.384608402
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1786912802
Short name T518
Test name
Test status
Simulation time 16482803 ps
CPU time 0.58 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 182740 kb
Host smart-c45c67d0-b064-49c3-a808-4ac736f00d7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786912802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1786912802
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1961417339
Short name T456
Test name
Test status
Simulation time 36890002 ps
CPU time 0.54 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 182300 kb
Host smart-8af3c80e-0900-40ac-8bef-43861f8ea570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961417339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1961417339
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.415157116
Short name T504
Test name
Test status
Simulation time 33151867 ps
CPU time 0.56 seconds
Started Aug 11 06:09:54 PM PDT 24
Finished Aug 11 06:09:55 PM PDT 24
Peak memory 182456 kb
Host smart-e626346b-17e2-49c0-8d28-36c46b041705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415157116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.415157116
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2793414526
Short name T469
Test name
Test status
Simulation time 53424821 ps
CPU time 0.55 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 182764 kb
Host smart-9c1537a9-d1db-4d98-9ea6-db5d791f1bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793414526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2793414526
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.755188892
Short name T544
Test name
Test status
Simulation time 50254675 ps
CPU time 0.58 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 182436 kb
Host smart-2b952eba-eb62-4585-a428-0b0d62785a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755188892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.755188892
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1665596747
Short name T537
Test name
Test status
Simulation time 27416207 ps
CPU time 0.56 seconds
Started Aug 11 06:09:55 PM PDT 24
Finished Aug 11 06:09:55 PM PDT 24
Peak memory 182688 kb
Host smart-0e5d27b2-f050-4a56-aec7-ddc243d81e2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665596747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1665596747
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.100299545
Short name T568
Test name
Test status
Simulation time 36707909 ps
CPU time 0.54 seconds
Started Aug 11 06:09:53 PM PDT 24
Finished Aug 11 06:09:54 PM PDT 24
Peak memory 182396 kb
Host smart-296851a8-e397-4d23-8683-19eba620a490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100299545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.100299545
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1966052037
Short name T526
Test name
Test status
Simulation time 17576771 ps
CPU time 0.58 seconds
Started Aug 11 06:10:03 PM PDT 24
Finished Aug 11 06:10:03 PM PDT 24
Peak memory 182688 kb
Host smart-df934737-9494-4728-a3dc-87cb1b78772f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966052037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1966052037
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1843324887
Short name T500
Test name
Test status
Simulation time 136469165 ps
CPU time 0.58 seconds
Started Aug 11 06:09:54 PM PDT 24
Finished Aug 11 06:09:55 PM PDT 24
Peak memory 182784 kb
Host smart-c49f08c8-7107-439a-8fe1-ca931e533e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843324887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1843324887
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.8381967
Short name T480
Test name
Test status
Simulation time 14108964 ps
CPU time 0.53 seconds
Started Aug 11 06:09:59 PM PDT 24
Finished Aug 11 06:10:00 PM PDT 24
Peak memory 182192 kb
Host smart-6da3f601-a2a0-4d1c-a774-bb367c295368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8381967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.8381967
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3298536857
Short name T89
Test name
Test status
Simulation time 70402216 ps
CPU time 0.72 seconds
Started Aug 11 06:09:36 PM PDT 24
Finished Aug 11 06:09:37 PM PDT 24
Peak memory 192156 kb
Host smart-cffa4d05-1c00-436a-ad33-372d00e9ca9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298536857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3298536857
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.30763817
Short name T95
Test name
Test status
Simulation time 1626709437 ps
CPU time 3.79 seconds
Started Aug 11 06:09:39 PM PDT 24
Finished Aug 11 06:09:43 PM PDT 24
Peak memory 193864 kb
Host smart-1efa7956-40ea-4eef-b4f1-07ce38882363
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30763817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ba
sh.30763817
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.464259887
Short name T531
Test name
Test status
Simulation time 23921527 ps
CPU time 0.61 seconds
Started Aug 11 06:09:44 PM PDT 24
Finished Aug 11 06:09:45 PM PDT 24
Peak memory 192044 kb
Host smart-b20b106a-e63d-41e0-a7a2-86a655d7680c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464259887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.464259887
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2688591111
Short name T468
Test name
Test status
Simulation time 66027351 ps
CPU time 0.92 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 196860 kb
Host smart-5d1caacc-4b79-4b96-b69a-3b9cde1f1998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688591111 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2688591111
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1409842897
Short name T515
Test name
Test status
Simulation time 21462464 ps
CPU time 0.53 seconds
Started Aug 11 06:09:54 PM PDT 24
Finished Aug 11 06:09:55 PM PDT 24
Peak memory 182932 kb
Host smart-b4a0cab8-ecec-46d1-81ce-c6dcfb0b8cc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409842897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1409842897
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1301422685
Short name T452
Test name
Test status
Simulation time 42819905 ps
CPU time 0.55 seconds
Started Aug 11 06:09:42 PM PDT 24
Finished Aug 11 06:09:43 PM PDT 24
Peak memory 182264 kb
Host smart-302876f2-6451-42ab-ab34-c36e19c708c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301422685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1301422685
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2349271661
Short name T509
Test name
Test status
Simulation time 168401690 ps
CPU time 0.81 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:49 PM PDT 24
Peak memory 193564 kb
Host smart-5e29292a-2e59-4566-b1f2-fe75c477cb55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349271661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2349271661
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2929683929
Short name T578
Test name
Test status
Simulation time 50167943 ps
CPU time 2.34 seconds
Started Aug 11 06:09:40 PM PDT 24
Finished Aug 11 06:09:43 PM PDT 24
Peak memory 197704 kb
Host smart-17daf954-dcf9-40fc-8f46-05cbcd00b642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929683929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2929683929
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4220405846
Short name T25
Test name
Test status
Simulation time 88221109 ps
CPU time 0.81 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 193736 kb
Host smart-cbd01898-61bd-4364-9bcb-9a9d1290b93a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220405846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.4220405846
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.504565902
Short name T517
Test name
Test status
Simulation time 120810908 ps
CPU time 0.53 seconds
Started Aug 11 06:09:56 PM PDT 24
Finished Aug 11 06:09:57 PM PDT 24
Peak memory 182656 kb
Host smart-2bc075ee-da79-46af-9df3-1e30a26946d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504565902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.504565902
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1319702043
Short name T477
Test name
Test status
Simulation time 84837960 ps
CPU time 0.54 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 182632 kb
Host smart-ed74f45b-dc1a-4245-b6f6-9a38fcc0deb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319702043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1319702043
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2034288766
Short name T495
Test name
Test status
Simulation time 21145277 ps
CPU time 0.53 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 182408 kb
Host smart-3b4a8c7a-f3e7-498d-9747-db5cfc2b1d88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034288766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2034288766
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4214153841
Short name T465
Test name
Test status
Simulation time 41871614 ps
CPU time 0.56 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 182216 kb
Host smart-90a5082f-5b04-4a67-a637-226e0e57989a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214153841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4214153841
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.526066941
Short name T529
Test name
Test status
Simulation time 14615881 ps
CPU time 0.54 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 182772 kb
Host smart-15f3d090-da1e-44c0-8ac6-8409f2910081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526066941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.526066941
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3890628079
Short name T466
Test name
Test status
Simulation time 24332455 ps
CPU time 0.55 seconds
Started Aug 11 06:09:52 PM PDT 24
Finished Aug 11 06:09:53 PM PDT 24
Peak memory 182712 kb
Host smart-0cf76801-ebb1-49f2-91aa-e64019ece8cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890628079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3890628079
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2249182679
Short name T462
Test name
Test status
Simulation time 38173213 ps
CPU time 0.56 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 182640 kb
Host smart-157be18c-91f1-43a7-a477-bd974cee9c8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249182679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2249182679
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1194185372
Short name T512
Test name
Test status
Simulation time 30209021 ps
CPU time 0.55 seconds
Started Aug 11 06:09:46 PM PDT 24
Finished Aug 11 06:09:47 PM PDT 24
Peak memory 182800 kb
Host smart-0943f5a6-ab5e-4392-8353-d9033e5d0616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194185372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1194185372
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.563518252
Short name T475
Test name
Test status
Simulation time 13122383 ps
CPU time 0.55 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:01 PM PDT 24
Peak memory 182204 kb
Host smart-1fd730e5-6317-4d0f-8752-4fbaa86614e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563518252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.563518252
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2146348172
Short name T493
Test name
Test status
Simulation time 55039446 ps
CPU time 0.56 seconds
Started Aug 11 06:09:56 PM PDT 24
Finished Aug 11 06:09:56 PM PDT 24
Peak memory 182760 kb
Host smart-c42dea67-8a17-4ba8-93f0-6ae2f7d9a641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146348172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2146348172
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1399893882
Short name T547
Test name
Test status
Simulation time 22194466 ps
CPU time 0.69 seconds
Started Aug 11 06:09:52 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 194052 kb
Host smart-ec65b3c8-314a-4872-91c2-25b601647f64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399893882 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1399893882
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3427315187
Short name T463
Test name
Test status
Simulation time 88839468 ps
CPU time 0.58 seconds
Started Aug 11 06:09:44 PM PDT 24
Finished Aug 11 06:09:45 PM PDT 24
Peak memory 182856 kb
Host smart-44b768a4-4d75-42b1-81ae-b58f95b9940e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427315187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3427315187
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2915715176
Short name T454
Test name
Test status
Simulation time 15085911 ps
CPU time 0.6 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 182608 kb
Host smart-0dec795e-e954-4be3-b8d9-0e81bda45648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915715176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2915715176
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1827244178
Short name T554
Test name
Test status
Simulation time 94938280 ps
CPU time 0.66 seconds
Started Aug 11 06:09:46 PM PDT 24
Finished Aug 11 06:09:47 PM PDT 24
Peak memory 191760 kb
Host smart-9967569e-20e4-458e-a9eb-e5c6d1a3b761
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827244178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1827244178
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1991031676
Short name T51
Test name
Test status
Simulation time 128293144 ps
CPU time 2.17 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 197732 kb
Host smart-64ef6e18-7be3-434a-a720-a2fbc82f46f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991031676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1991031676
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3464895846
Short name T108
Test name
Test status
Simulation time 481052032 ps
CPU time 1.31 seconds
Started Aug 11 06:09:36 PM PDT 24
Finished Aug 11 06:09:37 PM PDT 24
Peak memory 195304 kb
Host smart-ab30bdd2-7fab-4216-bf36-2778a8721bbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464895846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3464895846
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1892181320
Short name T489
Test name
Test status
Simulation time 66626102 ps
CPU time 0.93 seconds
Started Aug 11 06:09:50 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 197320 kb
Host smart-4e42c4a2-c6b5-45fd-b4b1-46886afc274d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892181320 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1892181320
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.535665364
Short name T514
Test name
Test status
Simulation time 37513782 ps
CPU time 0.53 seconds
Started Aug 11 06:09:37 PM PDT 24
Finished Aug 11 06:09:38 PM PDT 24
Peak memory 182596 kb
Host smart-8c720f3a-ede5-415f-b658-8664ebac37d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535665364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.535665364
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2581684568
Short name T530
Test name
Test status
Simulation time 28148532 ps
CPU time 0.67 seconds
Started Aug 11 06:09:37 PM PDT 24
Finished Aug 11 06:09:38 PM PDT 24
Peak memory 182672 kb
Host smart-f6ed7ef4-ade3-42cc-8fb4-1a96008d1cb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581684568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2581684568
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.82350870
Short name T97
Test name
Test status
Simulation time 97597490 ps
CPU time 0.72 seconds
Started Aug 11 06:09:37 PM PDT 24
Finished Aug 11 06:09:37 PM PDT 24
Peak memory 191760 kb
Host smart-38ed4027-4556-42c7-b5af-7a65febb3031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82350870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_time
r_same_csr_outstanding.82350870
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.490529917
Short name T508
Test name
Test status
Simulation time 226927773 ps
CPU time 1.16 seconds
Started Aug 11 06:09:35 PM PDT 24
Finished Aug 11 06:09:36 PM PDT 24
Peak memory 197648 kb
Host smart-d1b9fabd-17f0-4c6d-9fc8-3b98936c8544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490529917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.490529917
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1125823722
Short name T574
Test name
Test status
Simulation time 229329766 ps
CPU time 1.14 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 195468 kb
Host smart-3252e072-dba9-4b63-b64d-7130cd955d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125823722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1125823722
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2329620411
Short name T473
Test name
Test status
Simulation time 108953825 ps
CPU time 1.08 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 197728 kb
Host smart-fb40a541-ef58-45f7-a9f8-6868b71d4281
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329620411 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2329620411
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.497408880
Short name T551
Test name
Test status
Simulation time 105887596 ps
CPU time 0.59 seconds
Started Aug 11 06:09:56 PM PDT 24
Finished Aug 11 06:09:57 PM PDT 24
Peak memory 182800 kb
Host smart-c2684813-4da6-4360-8173-155c5ed31a1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497408880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.497408880
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2665190903
Short name T448
Test name
Test status
Simulation time 32863909 ps
CPU time 0.57 seconds
Started Aug 11 06:09:39 PM PDT 24
Finished Aug 11 06:09:39 PM PDT 24
Peak memory 182756 kb
Host smart-1a211fe4-5414-4eda-88b1-e009bb7b6177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665190903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2665190903
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1208364592
Short name T507
Test name
Test status
Simulation time 15231764 ps
CPU time 0.63 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:52 PM PDT 24
Peak memory 192132 kb
Host smart-28c3c4da-c920-4bc5-ba7d-6c8be4c63ba9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208364592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1208364592
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.273483503
Short name T559
Test name
Test status
Simulation time 93798427 ps
CPU time 1.12 seconds
Started Aug 11 06:09:35 PM PDT 24
Finished Aug 11 06:09:36 PM PDT 24
Peak memory 197424 kb
Host smart-8bf92ecd-cd7a-4db2-9833-022e206e4f25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273483503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.273483503
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2674232868
Short name T553
Test name
Test status
Simulation time 203795888 ps
CPU time 0.8 seconds
Started Aug 11 06:09:58 PM PDT 24
Finished Aug 11 06:09:59 PM PDT 24
Peak memory 193640 kb
Host smart-12c5c065-3d21-44a1-bed2-5a84ea079bde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674232868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2674232868
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.642017329
Short name T573
Test name
Test status
Simulation time 35706726 ps
CPU time 0.9 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:49 PM PDT 24
Peak memory 197312 kb
Host smart-e3e35b1b-118c-42f3-b174-44941d4fb9b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642017329 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.642017329
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.135097637
Short name T560
Test name
Test status
Simulation time 30807244 ps
CPU time 0.58 seconds
Started Aug 11 06:09:44 PM PDT 24
Finished Aug 11 06:09:45 PM PDT 24
Peak memory 183096 kb
Host smart-0ad17ca6-705d-4df3-84e9-cc6dd84ec8d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135097637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.135097637
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3554695297
Short name T458
Test name
Test status
Simulation time 18665028 ps
CPU time 0.55 seconds
Started Aug 11 06:09:37 PM PDT 24
Finished Aug 11 06:09:38 PM PDT 24
Peak memory 182572 kb
Host smart-92d35a11-5a04-41bb-a545-7e4790d87c50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554695297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3554695297
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2439677501
Short name T541
Test name
Test status
Simulation time 62220416 ps
CPU time 0.6 seconds
Started Aug 11 06:09:37 PM PDT 24
Finished Aug 11 06:09:37 PM PDT 24
Peak memory 191144 kb
Host smart-4304bb8e-6ea2-463c-84c5-a31c6f2675e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439677501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2439677501
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1158113815
Short name T536
Test name
Test status
Simulation time 42105752 ps
CPU time 2.06 seconds
Started Aug 11 06:09:38 PM PDT 24
Finished Aug 11 06:09:40 PM PDT 24
Peak memory 197704 kb
Host smart-df19411b-e48f-4b71-b308-785e9f247bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158113815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1158113815
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.788645995
Short name T107
Test name
Test status
Simulation time 976593140 ps
CPU time 1.3 seconds
Started Aug 11 06:09:49 PM PDT 24
Finished Aug 11 06:09:51 PM PDT 24
Peak memory 195540 kb
Host smart-d476902f-8b0c-4b97-bfbe-3060519e45a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788645995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.788645995
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2380526892
Short name T490
Test name
Test status
Simulation time 84272711 ps
CPU time 1.11 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:50 PM PDT 24
Peak memory 197748 kb
Host smart-8d8ebc64-a284-4f8f-afc2-32a6ad19a8b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380526892 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2380526892
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2926460712
Short name T513
Test name
Test status
Simulation time 47834533 ps
CPU time 0.58 seconds
Started Aug 11 06:09:41 PM PDT 24
Finished Aug 11 06:09:42 PM PDT 24
Peak memory 182848 kb
Host smart-93304d2a-8493-4bfc-93e2-bdcbea51f6c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926460712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2926460712
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.677934721
Short name T572
Test name
Test status
Simulation time 42248346 ps
CPU time 0.55 seconds
Started Aug 11 06:10:00 PM PDT 24
Finished Aug 11 06:10:00 PM PDT 24
Peak memory 182696 kb
Host smart-5ab09730-f4f6-45d4-a566-389bc67b014d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677934721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.677934721
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1607995526
Short name T528
Test name
Test status
Simulation time 22990189 ps
CPU time 0.69 seconds
Started Aug 11 06:09:48 PM PDT 24
Finished Aug 11 06:09:49 PM PDT 24
Peak memory 192520 kb
Host smart-7322f0e7-5fef-4a4d-8a1d-4f3d34a8169f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607995526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1607995526
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2294501817
Short name T570
Test name
Test status
Simulation time 436974746 ps
CPU time 1.96 seconds
Started Aug 11 06:09:51 PM PDT 24
Finished Aug 11 06:09:53 PM PDT 24
Peak memory 197588 kb
Host smart-d54c8d7b-dfd2-4ba1-8fdb-f3c6630ee726
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294501817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2294501817
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2535683799
Short name T106
Test name
Test status
Simulation time 163097011 ps
CPU time 0.84 seconds
Started Aug 11 06:09:39 PM PDT 24
Finished Aug 11 06:09:40 PM PDT 24
Peak memory 193592 kb
Host smart-3078396f-00b7-44dc-9082-a3d9ff7f1592
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535683799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2535683799
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3589312697
Short name T208
Test name
Test status
Simulation time 9848220151 ps
CPU time 14.87 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:27:54 PM PDT 24
Peak memory 183436 kb
Host smart-bff0edcc-f889-44e5-97fd-33adc3162220
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589312697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3589312697
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3972627728
Short name T378
Test name
Test status
Simulation time 584423127466 ps
CPU time 175.1 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:30:35 PM PDT 24
Peak memory 183388 kb
Host smart-bb6c7744-92c6-4bca-a804-f9b9587f1e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972627728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3972627728
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.4064605716
Short name T296
Test name
Test status
Simulation time 96863341625 ps
CPU time 137.72 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:29:58 PM PDT 24
Peak memory 191680 kb
Host smart-c2feceea-4dcf-4e72-b56c-1f750072c8bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064605716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.4064605716
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2158705733
Short name T263
Test name
Test status
Simulation time 39852579990 ps
CPU time 72.05 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:28:51 PM PDT 24
Peak memory 183472 kb
Host smart-7f592be9-04a3-4f47-b86b-17badd81f837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158705733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2158705733
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2667964825
Short name T217
Test name
Test status
Simulation time 1714593575127 ps
CPU time 1255.05 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:48:35 PM PDT 24
Peak memory 191680 kb
Host smart-b0c40960-ab2a-4221-8c04-5eead5b9ea99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667964825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2667964825
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2736685889
Short name T422
Test name
Test status
Simulation time 503038541585 ps
CPU time 239.38 seconds
Started Aug 11 06:27:33 PM PDT 24
Finished Aug 11 06:31:33 PM PDT 24
Peak memory 183432 kb
Host smart-4420e0e6-c387-4c9f-837b-2cc140c714dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736685889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2736685889
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2519167062
Short name T386
Test name
Test status
Simulation time 88250367219 ps
CPU time 114.61 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:29:29 PM PDT 24
Peak memory 183424 kb
Host smart-49d5e27c-da3a-49a9-89c1-2f770cdf1010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519167062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2519167062
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.4137698681
Short name T353
Test name
Test status
Simulation time 227371194980 ps
CPU time 126.08 seconds
Started Aug 11 06:27:30 PM PDT 24
Finished Aug 11 06:29:36 PM PDT 24
Peak memory 191528 kb
Host smart-35029d4c-2d79-4dc7-995b-61bbcd88aed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137698681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.4137698681
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2525255453
Short name T435
Test name
Test status
Simulation time 30520028501 ps
CPU time 46.91 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:28:25 PM PDT 24
Peak memory 183440 kb
Host smart-08f84478-03f5-4a6d-8514-2fcf5bcf2f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525255453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2525255453
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2487810338
Short name T18
Test name
Test status
Simulation time 60016528 ps
CPU time 0.86 seconds
Started Aug 11 06:27:28 PM PDT 24
Finished Aug 11 06:27:29 PM PDT 24
Peak memory 214040 kb
Host smart-08cf22e2-ab84-473f-b409-eb4903631aa8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487810338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2487810338
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3367651582
Short name T199
Test name
Test status
Simulation time 2150163145108 ps
CPU time 858.08 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:41:56 PM PDT 24
Peak memory 183460 kb
Host smart-183596ad-8f04-4197-8b76-5ddb55ac99d0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367651582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3367651582
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3894345091
Short name T382
Test name
Test status
Simulation time 98091378491 ps
CPU time 129.24 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:29:43 PM PDT 24
Peak memory 183420 kb
Host smart-155e78d4-5842-4630-85d2-d674b7186008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894345091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3894345091
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.2293485034
Short name T20
Test name
Test status
Simulation time 127470100956 ps
CPU time 2076.95 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 07:02:14 PM PDT 24
Peak memory 191712 kb
Host smart-3b492336-657e-4d49-b779-91b5fd96a20c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293485034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2293485034
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1322188214
Short name T186
Test name
Test status
Simulation time 102565977390 ps
CPU time 820.77 seconds
Started Aug 11 06:27:41 PM PDT 24
Finished Aug 11 06:41:22 PM PDT 24
Peak memory 191592 kb
Host smart-2d751337-ab5f-45af-9a19-22ae770a8ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322188214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1322188214
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3737365646
Short name T243
Test name
Test status
Simulation time 188225005027 ps
CPU time 682.38 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:39:00 PM PDT 24
Peak memory 193844 kb
Host smart-172a668b-b36b-4a49-a442-1c8cbac6a76b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737365646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3737365646
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/102.rv_timer_random.3490680251
Short name T354
Test name
Test status
Simulation time 90270819766 ps
CPU time 186.54 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:31:23 PM PDT 24
Peak memory 191648 kb
Host smart-882ba719-e993-455e-89c8-c0bdddd350d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490680251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3490680251
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.674184531
Short name T437
Test name
Test status
Simulation time 39029897189 ps
CPU time 62.71 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:29:19 PM PDT 24
Peak memory 183460 kb
Host smart-287e719f-51f3-428b-a514-d86de8196257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674184531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.674184531
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.583714831
Short name T349
Test name
Test status
Simulation time 212603227275 ps
CPU time 191.88 seconds
Started Aug 11 06:28:19 PM PDT 24
Finished Aug 11 06:31:31 PM PDT 24
Peak memory 191656 kb
Host smart-626aca94-75f2-438b-a5a9-0c7c396a4b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583714831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.583714831
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2063859467
Short name T46
Test name
Test status
Simulation time 127979031445 ps
CPU time 116.25 seconds
Started Aug 11 06:28:19 PM PDT 24
Finished Aug 11 06:30:16 PM PDT 24
Peak memory 191656 kb
Host smart-41b1ab44-c651-40b1-bc18-638e7e79809d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063859467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2063859467
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2771134312
Short name T425
Test name
Test status
Simulation time 21737858975 ps
CPU time 793.33 seconds
Started Aug 11 06:28:17 PM PDT 24
Finished Aug 11 06:41:30 PM PDT 24
Peak memory 183436 kb
Host smart-42bdefba-0cb2-499e-8ae9-28f9f86a8b2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771134312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2771134312
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1989263214
Short name T161
Test name
Test status
Simulation time 1256837686973 ps
CPU time 1023.75 seconds
Started Aug 11 06:27:41 PM PDT 24
Finished Aug 11 06:44:45 PM PDT 24
Peak memory 183384 kb
Host smart-8f110528-3c8a-490c-80c2-71fe804b3894
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989263214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1989263214
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_random.2145869561
Short name T317
Test name
Test status
Simulation time 61732839111 ps
CPU time 334.24 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:33:08 PM PDT 24
Peak memory 191604 kb
Host smart-2ba2ea88-4401-447e-b98c-fb8d056f5ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145869561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2145869561
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1500856839
Short name T419
Test name
Test status
Simulation time 77992294050 ps
CPU time 62.77 seconds
Started Aug 11 06:27:28 PM PDT 24
Finished Aug 11 06:28:31 PM PDT 24
Peak memory 183456 kb
Host smart-68d6e498-275e-42b0-9fb9-a198a3b7d22b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500856839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1500856839
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/112.rv_timer_random.2201742263
Short name T300
Test name
Test status
Simulation time 139091764093 ps
CPU time 380.89 seconds
Started Aug 11 06:28:24 PM PDT 24
Finished Aug 11 06:34:45 PM PDT 24
Peak memory 191668 kb
Host smart-30c381cb-ad16-42ce-b7f8-ba8912ebc594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201742263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2201742263
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2799955578
Short name T204
Test name
Test status
Simulation time 42565611666 ps
CPU time 78.26 seconds
Started Aug 11 06:28:21 PM PDT 24
Finished Aug 11 06:29:39 PM PDT 24
Peak memory 183480 kb
Host smart-9cca644f-98fa-4bf3-bab5-ac8f4c3cc2d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799955578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2799955578
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1581356500
Short name T397
Test name
Test status
Simulation time 49928553510 ps
CPU time 93.45 seconds
Started Aug 11 06:28:22 PM PDT 24
Finished Aug 11 06:29:56 PM PDT 24
Peak memory 183492 kb
Host smart-709d6b39-2576-49cd-b56a-60023d255e33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581356500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1581356500
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2109651472
Short name T347
Test name
Test status
Simulation time 135538482179 ps
CPU time 211.67 seconds
Started Aug 11 06:28:22 PM PDT 24
Finished Aug 11 06:31:53 PM PDT 24
Peak memory 195232 kb
Host smart-b5b3259e-b141-48c1-ac46-9bb260a37d72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109651472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2109651472
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2138961004
Short name T381
Test name
Test status
Simulation time 15218460425 ps
CPU time 23.14 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:28:04 PM PDT 24
Peak memory 183476 kb
Host smart-500c89d5-d314-433b-bb82-902ec3971770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138961004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2138961004
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1537014025
Short name T45
Test name
Test status
Simulation time 11763150054 ps
CPU time 428.38 seconds
Started Aug 11 06:27:26 PM PDT 24
Finished Aug 11 06:34:35 PM PDT 24
Peak memory 183416 kb
Host smart-f0de2c21-91cf-4513-9b95-254b0497f1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537014025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1537014025
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2358275202
Short name T64
Test name
Test status
Simulation time 926799079504 ps
CPU time 727.49 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:39:45 PM PDT 24
Peak memory 191660 kb
Host smart-c025f1a9-9f96-469d-855d-fde1fa24fca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358275202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2358275202
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.2109342893
Short name T408
Test name
Test status
Simulation time 326837725443 ps
CPU time 149.39 seconds
Started Aug 11 06:28:22 PM PDT 24
Finished Aug 11 06:30:52 PM PDT 24
Peak memory 183440 kb
Host smart-2f048748-8095-4178-87db-b2ebc9ed5a31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109342893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2109342893
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.960156556
Short name T265
Test name
Test status
Simulation time 874878101177 ps
CPU time 314.2 seconds
Started Aug 11 06:28:26 PM PDT 24
Finished Aug 11 06:33:40 PM PDT 24
Peak memory 191656 kb
Host smart-ac384f4f-cc2b-40c2-8488-16bbc9b56c21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960156556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.960156556
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.858210023
Short name T98
Test name
Test status
Simulation time 909029417688 ps
CPU time 212.81 seconds
Started Aug 11 06:28:26 PM PDT 24
Finished Aug 11 06:31:59 PM PDT 24
Peak memory 191692 kb
Host smart-287f4623-854c-47a3-bcd2-6bb5ce67d09d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858210023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.858210023
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.475752159
Short name T293
Test name
Test status
Simulation time 133149888990 ps
CPU time 786.42 seconds
Started Aug 11 06:28:26 PM PDT 24
Finished Aug 11 06:41:33 PM PDT 24
Peak memory 191680 kb
Host smart-43d77596-b155-4d32-b47e-06fdbd040e56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475752159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.475752159
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3883524799
Short name T111
Test name
Test status
Simulation time 204194757182 ps
CPU time 114.88 seconds
Started Aug 11 06:28:26 PM PDT 24
Finished Aug 11 06:30:21 PM PDT 24
Peak memory 191648 kb
Host smart-8594b8d7-c18c-4897-8a33-51ed4f6bee64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883524799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3883524799
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2688402626
Short name T276
Test name
Test status
Simulation time 496481705025 ps
CPU time 267.57 seconds
Started Aug 11 06:28:26 PM PDT 24
Finished Aug 11 06:32:54 PM PDT 24
Peak memory 191656 kb
Host smart-2078a1e5-4002-49cb-b32e-eb97e197cdfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688402626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2688402626
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2982752257
Short name T223
Test name
Test status
Simulation time 18819825902 ps
CPU time 15.64 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:27:55 PM PDT 24
Peak memory 183436 kb
Host smart-de72ec3f-f22e-489d-b10b-1543c9c14d6f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982752257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2982752257
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2397954156
Short name T357
Test name
Test status
Simulation time 65883226206 ps
CPU time 107.65 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:29:27 PM PDT 24
Peak memory 183404 kb
Host smart-5618388b-91ec-48df-9951-93eec95403ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397954156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2397954156
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1368704121
Short name T326
Test name
Test status
Simulation time 52016364384 ps
CPU time 153.17 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:30:12 PM PDT 24
Peak memory 183416 kb
Host smart-798e3ac8-8a8d-4605-b8af-d0cb233b66b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368704121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1368704121
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.1824047715
Short name T33
Test name
Test status
Simulation time 91252990582 ps
CPU time 115.53 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 06:29:32 PM PDT 24
Peak memory 206328 kb
Host smart-333bd9c9-cd5d-43b0-a9e4-9b49360df918
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824047715 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.1824047715
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.629919242
Short name T159
Test name
Test status
Simulation time 67836995129 ps
CPU time 103.59 seconds
Started Aug 11 06:28:34 PM PDT 24
Finished Aug 11 06:30:17 PM PDT 24
Peak memory 191640 kb
Host smart-699b2dd2-2b06-461d-b833-fe708d3b0a42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629919242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.629919242
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3448163383
Short name T207
Test name
Test status
Simulation time 109631263865 ps
CPU time 436.25 seconds
Started Aug 11 06:28:34 PM PDT 24
Finished Aug 11 06:35:50 PM PDT 24
Peak memory 191688 kb
Host smart-ccda43a2-9cd5-491a-9ec5-fc210ad8f9ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448163383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3448163383
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1467854009
Short name T319
Test name
Test status
Simulation time 27142477359 ps
CPU time 44.3 seconds
Started Aug 11 06:28:34 PM PDT 24
Finished Aug 11 06:29:18 PM PDT 24
Peak memory 183380 kb
Host smart-7ddd9ac5-2ac2-4b44-abe0-2f30cd09c541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467854009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1467854009
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.112679190
Short name T197
Test name
Test status
Simulation time 206480473062 ps
CPU time 168.96 seconds
Started Aug 11 06:28:40 PM PDT 24
Finished Aug 11 06:31:29 PM PDT 24
Peak memory 191664 kb
Host smart-f0076efe-6f83-4443-9f7c-2cc57c859c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112679190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.112679190
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.4245229380
Short name T134
Test name
Test status
Simulation time 332483765218 ps
CPU time 298.16 seconds
Started Aug 11 06:28:41 PM PDT 24
Finished Aug 11 06:33:39 PM PDT 24
Peak memory 191648 kb
Host smart-bae94be7-02d0-4b40-b447-543dda1fbfd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245229380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.4245229380
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.564465476
Short name T164
Test name
Test status
Simulation time 270798004933 ps
CPU time 257.34 seconds
Started Aug 11 06:28:39 PM PDT 24
Finished Aug 11 06:32:57 PM PDT 24
Peak memory 191624 kb
Host smart-910a67ad-e2e1-4553-9ee2-d67ecaef35c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564465476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.564465476
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3936076394
Short name T174
Test name
Test status
Simulation time 167799492712 ps
CPU time 380.01 seconds
Started Aug 11 06:28:40 PM PDT 24
Finished Aug 11 06:35:00 PM PDT 24
Peak memory 191672 kb
Host smart-7f13be9d-70ae-4ede-9879-ffdd0a1d6374
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936076394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3936076394
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2309639394
Short name T127
Test name
Test status
Simulation time 814343791352 ps
CPU time 308.14 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:32:47 PM PDT 24
Peak memory 183632 kb
Host smart-702cca0b-8fb4-48d3-9c99-994d5fc1294b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309639394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2309639394
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1657345373
Short name T429
Test name
Test status
Simulation time 47030501593 ps
CPU time 63.61 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:28:42 PM PDT 24
Peak memory 183452 kb
Host smart-e68f5558-fc96-4fb1-b901-1d430ad17d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657345373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1657345373
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1789471763
Short name T215
Test name
Test status
Simulation time 753883162995 ps
CPU time 295.99 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:32:34 PM PDT 24
Peak memory 191504 kb
Host smart-4f0c65da-5d2f-4eb8-bb27-ee44f8ae6af9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789471763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1789471763
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3518537344
Short name T402
Test name
Test status
Simulation time 157648215 ps
CPU time 0.73 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:27:41 PM PDT 24
Peak memory 183048 kb
Host smart-2f7700a9-ac48-4449-97d0-e79208612e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518537344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3518537344
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2468757541
Short name T360
Test name
Test status
Simulation time 70867872 ps
CPU time 0.56 seconds
Started Aug 11 06:27:43 PM PDT 24
Finished Aug 11 06:27:43 PM PDT 24
Peak memory 183156 kb
Host smart-35e7bccf-1e9e-4779-9c4c-f522e2ee7b2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468757541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2468757541
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.3950975548
Short name T116
Test name
Test status
Simulation time 97170706199 ps
CPU time 293.24 seconds
Started Aug 11 06:28:39 PM PDT 24
Finished Aug 11 06:33:32 PM PDT 24
Peak memory 191704 kb
Host smart-91d1d3c5-e709-4ec4-be74-caef75459bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950975548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3950975548
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2727947246
Short name T6
Test name
Test status
Simulation time 35276545126 ps
CPU time 231.47 seconds
Started Aug 11 06:28:43 PM PDT 24
Finished Aug 11 06:32:34 PM PDT 24
Peak memory 183496 kb
Host smart-946965af-2187-4aaf-913d-e31c84a849bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727947246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2727947246
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2845476492
Short name T231
Test name
Test status
Simulation time 336075555599 ps
CPU time 149.1 seconds
Started Aug 11 06:28:44 PM PDT 24
Finished Aug 11 06:31:13 PM PDT 24
Peak memory 191648 kb
Host smart-680d7af9-464f-4f40-8817-e387ef83b361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845476492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2845476492
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1627295910
Short name T318
Test name
Test status
Simulation time 324661022587 ps
CPU time 134.16 seconds
Started Aug 11 06:28:51 PM PDT 24
Finished Aug 11 06:31:06 PM PDT 24
Peak memory 191652 kb
Host smart-7d1399ad-7281-4ba0-8b78-7eaeb5f96407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627295910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1627295910
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1723934203
Short name T245
Test name
Test status
Simulation time 155011682917 ps
CPU time 1113.01 seconds
Started Aug 11 06:28:52 PM PDT 24
Finished Aug 11 06:47:25 PM PDT 24
Peak memory 191644 kb
Host smart-58a55ece-be5e-4fee-8aa7-7f5bf9128e17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723934203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1723934203
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3082683786
Short name T418
Test name
Test status
Simulation time 303379497850 ps
CPU time 413.34 seconds
Started Aug 11 06:28:50 PM PDT 24
Finished Aug 11 06:35:43 PM PDT 24
Peak memory 191492 kb
Host smart-768957a2-851a-441b-8dac-24316c24fbcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082683786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3082683786
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1626076476
Short name T398
Test name
Test status
Simulation time 245918439664 ps
CPU time 142.48 seconds
Started Aug 11 06:28:50 PM PDT 24
Finished Aug 11 06:31:13 PM PDT 24
Peak memory 191648 kb
Host smart-40937364-4db5-4949-9705-72874fcc29d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626076476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1626076476
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2860705378
Short name T101
Test name
Test status
Simulation time 10358111235 ps
CPU time 15.08 seconds
Started Aug 11 06:27:45 PM PDT 24
Finished Aug 11 06:28:00 PM PDT 24
Peak memory 183472 kb
Host smart-56b4a352-98bd-4352-a7c6-964b5e61d585
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860705378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2860705378
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.360602429
Short name T413
Test name
Test status
Simulation time 110390816519 ps
CPU time 158.72 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:30:14 PM PDT 24
Peak memory 183396 kb
Host smart-e7dac047-d832-4fc8-861e-7648174a518f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360602429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.360602429
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2947874826
Short name T341
Test name
Test status
Simulation time 248709035573 ps
CPU time 511.7 seconds
Started Aug 11 06:27:31 PM PDT 24
Finished Aug 11 06:36:03 PM PDT 24
Peak memory 191628 kb
Host smart-1e3c5cb4-16ae-4872-b756-d06e87f3d11a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947874826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2947874826
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1250073752
Short name T379
Test name
Test status
Simulation time 185197812 ps
CPU time 0.74 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:27:40 PM PDT 24
Peak memory 183156 kb
Host smart-1ee82fc8-9a54-4a16-a52c-33b68c6a6301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250073752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1250073752
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/153.rv_timer_random.3115423962
Short name T235
Test name
Test status
Simulation time 130405947540 ps
CPU time 278.27 seconds
Started Aug 11 06:28:58 PM PDT 24
Finished Aug 11 06:33:36 PM PDT 24
Peak memory 191600 kb
Host smart-b484de82-cc37-4cd6-b108-2613dbca1f7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115423962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3115423962
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2270282921
Short name T288
Test name
Test status
Simulation time 8490372887 ps
CPU time 50.71 seconds
Started Aug 11 06:28:57 PM PDT 24
Finished Aug 11 06:29:48 PM PDT 24
Peak memory 191684 kb
Host smart-34b3cd3e-cc55-41e6-9bc2-f49e44181ed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270282921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2270282921
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2203439088
Short name T272
Test name
Test status
Simulation time 387394750150 ps
CPU time 790.64 seconds
Started Aug 11 06:28:58 PM PDT 24
Finished Aug 11 06:42:09 PM PDT 24
Peak memory 191696 kb
Host smart-f8596bbc-cdaa-4f12-844b-b5718e008cca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203439088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2203439088
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3288731295
Short name T221
Test name
Test status
Simulation time 80900531251 ps
CPU time 483.84 seconds
Started Aug 11 06:28:58 PM PDT 24
Finished Aug 11 06:37:02 PM PDT 24
Peak memory 183504 kb
Host smart-3019dfe8-d75f-466b-9b27-12f14daf802f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288731295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3288731295
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.4274061501
Short name T343
Test name
Test status
Simulation time 148108590056 ps
CPU time 147.17 seconds
Started Aug 11 06:29:04 PM PDT 24
Finished Aug 11 06:31:31 PM PDT 24
Peak memory 191672 kb
Host smart-a132ba7e-cb97-471d-9fbb-d2c6d007c5e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274061501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.4274061501
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1076849736
Short name T385
Test name
Test status
Simulation time 4766553835 ps
CPU time 3.52 seconds
Started Aug 11 06:27:41 PM PDT 24
Finished Aug 11 06:27:44 PM PDT 24
Peak memory 183260 kb
Host smart-9a823e55-50fd-429c-bd3a-d6c2c3ddbe04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076849736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1076849736
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3565169677
Short name T239
Test name
Test status
Simulation time 712725061425 ps
CPU time 839.95 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 06:41:36 PM PDT 24
Peak memory 183512 kb
Host smart-2ec2785d-23d9-4696-94fc-0ff972c8547a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565169677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3565169677
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.847900864
Short name T5
Test name
Test status
Simulation time 78631875315 ps
CPU time 389.49 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:34:10 PM PDT 24
Peak memory 191600 kb
Host smart-000e62bc-e8be-4052-a3fe-b2d9d210d9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847900864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.847900864
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1736786945
Short name T406
Test name
Test status
Simulation time 41722974 ps
CPU time 0.56 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:27:39 PM PDT 24
Peak memory 183184 kb
Host smart-2c61f8ad-60e1-47ce-9bf9-705d3fe7449f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736786945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1736786945
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.792139947
Short name T224
Test name
Test status
Simulation time 80020607393 ps
CPU time 80.86 seconds
Started Aug 11 06:29:04 PM PDT 24
Finished Aug 11 06:30:25 PM PDT 24
Peak memory 191584 kb
Host smart-517eb5be-a0ff-43aa-8def-beee7506cdd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792139947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.792139947
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.891287531
Short name T194
Test name
Test status
Simulation time 163582574541 ps
CPU time 790.44 seconds
Started Aug 11 06:29:05 PM PDT 24
Finished Aug 11 06:42:15 PM PDT 24
Peak memory 191660 kb
Host smart-458708fd-9b41-471f-a13b-04d8d2ca481f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891287531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.891287531
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2201165568
Short name T428
Test name
Test status
Simulation time 111796022162 ps
CPU time 179.96 seconds
Started Aug 11 06:29:04 PM PDT 24
Finished Aug 11 06:32:04 PM PDT 24
Peak memory 191700 kb
Host smart-0c60267a-2305-43d1-9818-ab6778af7931
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201165568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2201165568
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1507383982
Short name T238
Test name
Test status
Simulation time 162046610088 ps
CPU time 576.47 seconds
Started Aug 11 06:29:09 PM PDT 24
Finished Aug 11 06:38:46 PM PDT 24
Peak memory 191696 kb
Host smart-ea1df395-bf84-4df6-aea5-ea2f87b0cc1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507383982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1507383982
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2170723785
Short name T137
Test name
Test status
Simulation time 1151085420964 ps
CPU time 1446.08 seconds
Started Aug 11 06:29:10 PM PDT 24
Finished Aug 11 06:53:16 PM PDT 24
Peak memory 192932 kb
Host smart-8056761c-ebea-4e01-b2bc-a04c30f50831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170723785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2170723785
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1397985154
Short name T314
Test name
Test status
Simulation time 189378756021 ps
CPU time 79.81 seconds
Started Aug 11 06:29:09 PM PDT 24
Finished Aug 11 06:30:29 PM PDT 24
Peak memory 183448 kb
Host smart-cccf4013-3d22-45f0-8102-93088efd986d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397985154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1397985154
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1077690699
Short name T307
Test name
Test status
Simulation time 288477364672 ps
CPU time 494.4 seconds
Started Aug 11 06:29:09 PM PDT 24
Finished Aug 11 06:37:24 PM PDT 24
Peak memory 191656 kb
Host smart-c58e14a2-b21d-47ff-af57-57205ae58089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077690699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1077690699
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1568528219
Short name T75
Test name
Test status
Simulation time 50227700008 ps
CPU time 73.84 seconds
Started Aug 11 06:29:09 PM PDT 24
Finished Aug 11 06:30:23 PM PDT 24
Peak memory 195756 kb
Host smart-a594cfc8-5e9c-4563-95ec-a1b6a2aec836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568528219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1568528219
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.2102660048
Short name T311
Test name
Test status
Simulation time 176119589744 ps
CPU time 279.34 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:32:15 PM PDT 24
Peak memory 183460 kb
Host smart-bae0e59f-dfec-490a-a508-0887a3607fad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102660048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.2102660048
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3040690625
Short name T390
Test name
Test status
Simulation time 128473076812 ps
CPU time 159.97 seconds
Started Aug 11 06:27:44 PM PDT 24
Finished Aug 11 06:30:24 PM PDT 24
Peak memory 183468 kb
Host smart-0b8c5939-059c-4873-b2dd-8116a8931009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040690625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3040690625
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3204304673
Short name T328
Test name
Test status
Simulation time 108674231291 ps
CPU time 25.67 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:28:04 PM PDT 24
Peak memory 191596 kb
Host smart-dc09ec26-f0d1-4a1e-85d5-af78fed829d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204304673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3204304673
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2809235718
Short name T412
Test name
Test status
Simulation time 170582332386 ps
CPU time 227.65 seconds
Started Aug 11 06:27:43 PM PDT 24
Finished Aug 11 06:31:31 PM PDT 24
Peak memory 195264 kb
Host smart-05c5a0bd-5f91-4c19-b0e8-27438e0efcbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809235718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2809235718
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.1929173716
Short name T329
Test name
Test status
Simulation time 45342018117 ps
CPU time 74 seconds
Started Aug 11 06:29:16 PM PDT 24
Finished Aug 11 06:30:30 PM PDT 24
Peak memory 183416 kb
Host smart-36d84134-0d42-4c55-86a5-e550561003d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929173716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1929173716
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.868864626
Short name T346
Test name
Test status
Simulation time 52790754308 ps
CPU time 70.76 seconds
Started Aug 11 06:29:18 PM PDT 24
Finished Aug 11 06:30:28 PM PDT 24
Peak memory 183464 kb
Host smart-5e39250d-992e-4289-8024-2f82ce418184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868864626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.868864626
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2539590117
Short name T229
Test name
Test status
Simulation time 670300246670 ps
CPU time 541.36 seconds
Started Aug 11 06:29:17 PM PDT 24
Finished Aug 11 06:38:19 PM PDT 24
Peak memory 191664 kb
Host smart-cd8eee6a-2c4d-4e92-9447-fb1ed9e65059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539590117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2539590117
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2493120110
Short name T291
Test name
Test status
Simulation time 202437525708 ps
CPU time 231.27 seconds
Started Aug 11 06:29:16 PM PDT 24
Finished Aug 11 06:33:08 PM PDT 24
Peak memory 191704 kb
Host smart-1223fa9f-67ed-4935-9f01-f5902355a35f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493120110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2493120110
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2888454121
Short name T236
Test name
Test status
Simulation time 433557275419 ps
CPU time 617.73 seconds
Started Aug 11 06:29:17 PM PDT 24
Finished Aug 11 06:39:35 PM PDT 24
Peak memory 191656 kb
Host smart-30221bf6-e2e9-43c1-aa6d-9fa9c8e2de2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888454121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2888454121
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.30487992
Short name T47
Test name
Test status
Simulation time 117567147254 ps
CPU time 57.73 seconds
Started Aug 11 06:29:23 PM PDT 24
Finished Aug 11 06:30:20 PM PDT 24
Peak memory 183472 kb
Host smart-2822d78f-d2a7-43c0-9c9c-afa5b4c075d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30487992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.30487992
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2502194941
Short name T264
Test name
Test status
Simulation time 534687249709 ps
CPU time 1320.77 seconds
Started Aug 11 06:29:23 PM PDT 24
Finished Aug 11 06:51:24 PM PDT 24
Peak memory 191676 kb
Host smart-b1397974-ee21-4b6e-ae95-e4a4c21313c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502194941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2502194941
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3049705998
Short name T267
Test name
Test status
Simulation time 76239641124 ps
CPU time 1675.67 seconds
Started Aug 11 06:29:22 PM PDT 24
Finished Aug 11 06:57:18 PM PDT 24
Peak memory 191648 kb
Host smart-9cff118c-d1ad-4a87-85e5-98b8ce1e07ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049705998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3049705998
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1029056032
Short name T270
Test name
Test status
Simulation time 45140180190 ps
CPU time 41.71 seconds
Started Aug 11 06:27:42 PM PDT 24
Finished Aug 11 06:28:24 PM PDT 24
Peak memory 183432 kb
Host smart-447b041b-8cbc-476d-806d-146696ade132
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029056032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1029056032
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1418617400
Short name T416
Test name
Test status
Simulation time 269265172403 ps
CPU time 109.68 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:29:30 PM PDT 24
Peak memory 183428 kb
Host smart-80c20206-92a2-4a88-8374-e92108ade575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418617400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1418617400
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1397587203
Short name T218
Test name
Test status
Simulation time 100618176582 ps
CPU time 515.7 seconds
Started Aug 11 06:27:41 PM PDT 24
Finished Aug 11 06:36:17 PM PDT 24
Peak memory 191648 kb
Host smart-5e6fa0e2-aaa3-451d-b250-190ea15de3e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397587203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1397587203
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2362137283
Short name T138
Test name
Test status
Simulation time 267798414195 ps
CPU time 467.58 seconds
Started Aug 11 06:27:43 PM PDT 24
Finished Aug 11 06:35:31 PM PDT 24
Peak memory 191664 kb
Host smart-59c85666-22c3-467f-b570-bfa2b908979c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362137283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2362137283
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2901923750
Short name T256
Test name
Test status
Simulation time 4129214293550 ps
CPU time 678.94 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:38:58 PM PDT 24
Peak memory 195496 kb
Host smart-c574111a-72ec-4e89-9d4b-c30397d46810
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901923750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2901923750
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.3643323576
Short name T105
Test name
Test status
Simulation time 123910848883 ps
CPU time 203.36 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:31:03 PM PDT 24
Peak memory 197992 kb
Host smart-7eae18e7-8e77-4f6a-aff3-eda12c1b5b36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643323576 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.3643323576
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.3595331579
Short name T213
Test name
Test status
Simulation time 176197065012 ps
CPU time 256.28 seconds
Started Aug 11 06:29:22 PM PDT 24
Finished Aug 11 06:33:39 PM PDT 24
Peak memory 191644 kb
Host smart-a131d22b-0c8f-44ee-80dc-e4e33ff5430a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595331579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3595331579
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2160917953
Short name T230
Test name
Test status
Simulation time 586484329049 ps
CPU time 1541.81 seconds
Started Aug 11 06:29:21 PM PDT 24
Finished Aug 11 06:55:03 PM PDT 24
Peak memory 191656 kb
Host smart-dedd6ab4-9179-4150-8b0f-d4f13f4c1f8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160917953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2160917953
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3612679260
Short name T316
Test name
Test status
Simulation time 59721586210 ps
CPU time 238.05 seconds
Started Aug 11 06:29:23 PM PDT 24
Finished Aug 11 06:33:21 PM PDT 24
Peak memory 183476 kb
Host smart-df0be2c9-0a74-460e-80b3-57cd9eba01c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612679260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3612679260
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2174194948
Short name T384
Test name
Test status
Simulation time 199214981359 ps
CPU time 91.31 seconds
Started Aug 11 06:29:22 PM PDT 24
Finished Aug 11 06:30:54 PM PDT 24
Peak memory 183488 kb
Host smart-12eb8967-9c8a-472d-bc5d-78ea3f7f0d5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174194948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2174194948
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.4268376800
Short name T325
Test name
Test status
Simulation time 117362510890 ps
CPU time 96.97 seconds
Started Aug 11 06:29:23 PM PDT 24
Finished Aug 11 06:31:00 PM PDT 24
Peak memory 191624 kb
Host smart-05152709-98b4-4f08-8fd1-c2e795f469d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268376800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.4268376800
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1167679474
Short name T338
Test name
Test status
Simulation time 287973915958 ps
CPU time 163.27 seconds
Started Aug 11 06:29:29 PM PDT 24
Finished Aug 11 06:32:13 PM PDT 24
Peak memory 191624 kb
Host smart-3d46c684-a4bb-4192-9196-06548128a9c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167679474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1167679474
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.788207345
Short name T350
Test name
Test status
Simulation time 493789436811 ps
CPU time 539.43 seconds
Started Aug 11 06:29:29 PM PDT 24
Finished Aug 11 06:38:29 PM PDT 24
Peak memory 191688 kb
Host smart-ac174756-67c1-4f18-8114-960ee8980f7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788207345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.788207345
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.598191934
Short name T173
Test name
Test status
Simulation time 20800763010 ps
CPU time 32.37 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 06:28:10 PM PDT 24
Peak memory 183412 kb
Host smart-30b3958c-05af-4b47-b27a-111647891c33
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598191934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.598191934
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1901850246
Short name T9
Test name
Test status
Simulation time 145636299104 ps
CPU time 226.13 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 06:31:22 PM PDT 24
Peak memory 183400 kb
Host smart-fa722528-2491-427e-97da-a64ecbc5ec20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901850246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1901850246
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3520166163
Short name T99
Test name
Test status
Simulation time 82449168782 ps
CPU time 84.36 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:29:04 PM PDT 24
Peak memory 191572 kb
Host smart-16157e7b-a515-43c3-bc8a-d6cd8b2a9915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520166163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3520166163
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1893200845
Short name T152
Test name
Test status
Simulation time 951380114024 ps
CPU time 965.17 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:43:43 PM PDT 24
Peak memory 191632 kb
Host smart-b379784a-ac44-48a3-970b-9ecc0480f77d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893200845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1893200845
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.2401555535
Short name T35
Test name
Test status
Simulation time 292367599152 ps
CPU time 821.71 seconds
Started Aug 11 06:27:42 PM PDT 24
Finished Aug 11 06:41:24 PM PDT 24
Peak memory 209508 kb
Host smart-29b5b35c-91b3-4635-827a-b330f37a90af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401555535 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.2401555535
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.1116834358
Short name T176
Test name
Test status
Simulation time 54586722026 ps
CPU time 260.55 seconds
Started Aug 11 06:29:28 PM PDT 24
Finished Aug 11 06:33:49 PM PDT 24
Peak memory 191640 kb
Host smart-b1d8d398-c11a-4f98-9887-14f316d8d693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116834358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1116834358
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1276429870
Short name T23
Test name
Test status
Simulation time 312313384421 ps
CPU time 164.55 seconds
Started Aug 11 06:29:29 PM PDT 24
Finished Aug 11 06:32:14 PM PDT 24
Peak memory 191712 kb
Host smart-b9597d0b-4c42-4af3-bef4-193717425250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276429870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1276429870
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2022495946
Short name T415
Test name
Test status
Simulation time 84068331720 ps
CPU time 59.24 seconds
Started Aug 11 06:29:28 PM PDT 24
Finished Aug 11 06:30:27 PM PDT 24
Peak memory 183504 kb
Host smart-bfb7559f-faa3-4eb4-8840-4492e42eb9ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022495946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2022495946
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1774982736
Short name T294
Test name
Test status
Simulation time 534658343991 ps
CPU time 132.61 seconds
Started Aug 11 06:29:28 PM PDT 24
Finished Aug 11 06:31:41 PM PDT 24
Peak memory 191620 kb
Host smart-9c15907f-8a85-4c40-8d10-3a1fb1afd8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774982736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1774982736
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1968056166
Short name T244
Test name
Test status
Simulation time 74781040171 ps
CPU time 102.61 seconds
Started Aug 11 06:29:29 PM PDT 24
Finished Aug 11 06:31:11 PM PDT 24
Peak memory 191648 kb
Host smart-048aa973-77f6-44fe-9e83-f8635890004b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968056166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1968056166
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.365101266
Short name T303
Test name
Test status
Simulation time 39186799299 ps
CPU time 65.33 seconds
Started Aug 11 06:29:28 PM PDT 24
Finished Aug 11 06:30:34 PM PDT 24
Peak memory 183480 kb
Host smart-aa121179-2aca-453f-a0e9-e6dfe1247d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365101266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.365101266
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.4136707598
Short name T19
Test name
Test status
Simulation time 89434675783 ps
CPU time 128.09 seconds
Started Aug 11 06:29:33 PM PDT 24
Finished Aug 11 06:31:41 PM PDT 24
Peak memory 191588 kb
Host smart-fa357769-12e4-4ddd-8191-f52d7828e99b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136707598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.4136707598
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1189476174
Short name T299
Test name
Test status
Simulation time 87200674510 ps
CPU time 77.81 seconds
Started Aug 11 06:29:33 PM PDT 24
Finished Aug 11 06:30:51 PM PDT 24
Peak memory 191688 kb
Host smart-a30a1110-2b50-4ed2-a569-863dd974bc78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189476174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1189476174
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.389158209
Short name T292
Test name
Test status
Simulation time 128267031425 ps
CPU time 75.79 seconds
Started Aug 11 06:29:32 PM PDT 24
Finished Aug 11 06:30:48 PM PDT 24
Peak memory 183328 kb
Host smart-63dc5ef4-d32f-4a73-8e5a-eb9cc034c95e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389158209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.389158209
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.74469025
Short name T331
Test name
Test status
Simulation time 1045377567245 ps
CPU time 356.38 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:33:36 PM PDT 24
Peak memory 183448 kb
Host smart-8d8be745-8737-47b7-bb2b-a2fdc7acf7cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74469025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
rv_timer_cfg_update_on_fly.74469025
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3374912397
Short name T400
Test name
Test status
Simulation time 937030582 ps
CPU time 1.97 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:27:37 PM PDT 24
Peak memory 191972 kb
Host smart-2256058c-1a3a-425b-ad99-8741ea3bf846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374912397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3374912397
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1096041798
Short name T7
Test name
Test status
Simulation time 59332504 ps
CPU time 0.81 seconds
Started Aug 11 06:27:33 PM PDT 24
Finished Aug 11 06:27:34 PM PDT 24
Peak memory 213944 kb
Host smart-ec4f1496-3fea-4c4a-8560-fd45338ae4af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096041798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1096041798
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3277529458
Short name T290
Test name
Test status
Simulation time 116910925157 ps
CPU time 374.06 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:33:50 PM PDT 24
Peak memory 191656 kb
Host smart-9bd61d66-d5e5-4e3d-beb9-ae26dda34a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277529458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3277529458
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.2125528781
Short name T34
Test name
Test status
Simulation time 79878172686 ps
CPU time 877.8 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:42:18 PM PDT 24
Peak memory 214472 kb
Host smart-82b21333-775d-47ec-a1e6-6fa04e725969
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125528781 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.2125528781
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1198478767
Short name T392
Test name
Test status
Simulation time 139895352026 ps
CPU time 207.21 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:31:06 PM PDT 24
Peak memory 183236 kb
Host smart-0eb2786a-8174-4408-aa70-e536d57cb7e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198478767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1198478767
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3037493974
Short name T1
Test name
Test status
Simulation time 382362392435 ps
CPU time 153.85 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:30:12 PM PDT 24
Peak memory 183292 kb
Host smart-79c7458f-a088-43e9-8648-4d15dd4e91b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037493974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3037493974
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3037118903
Short name T143
Test name
Test status
Simulation time 186812727723 ps
CPU time 71.43 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:28:50 PM PDT 24
Peak memory 183448 kb
Host smart-98c73987-de8c-44f2-9504-15e390aa2157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037118903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3037118903
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2657060867
Short name T336
Test name
Test status
Simulation time 75870079999 ps
CPU time 289.78 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:32:30 PM PDT 24
Peak memory 183360 kb
Host smart-5de67d76-d42f-45a0-8093-7974b46891c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657060867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2657060867
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2254710420
Short name T348
Test name
Test status
Simulation time 399066304714 ps
CPU time 334.97 seconds
Started Aug 11 06:27:33 PM PDT 24
Finished Aug 11 06:33:09 PM PDT 24
Peak memory 183616 kb
Host smart-6616eaa7-ad3a-43d1-8332-ff99d6dbe5b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254710420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2254710420
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1135361086
Short name T436
Test name
Test status
Simulation time 101277904555 ps
CPU time 152.52 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:30:12 PM PDT 24
Peak memory 183284 kb
Host smart-973444a9-56f4-47e0-bf69-74a9c604187d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135361086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1135361086
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.355752948
Short name T8
Test name
Test status
Simulation time 57985357276 ps
CPU time 98.17 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:29:17 PM PDT 24
Peak memory 191636 kb
Host smart-c5e58dba-e481-4eec-9b7e-01df41cb9130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355752948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.355752948
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3608047100
Short name T271
Test name
Test status
Simulation time 100192155227 ps
CPU time 378.06 seconds
Started Aug 11 06:27:33 PM PDT 24
Finished Aug 11 06:33:51 PM PDT 24
Peak memory 191640 kb
Host smart-4777453c-3373-4609-8947-73b1aea6a1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608047100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3608047100
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1570620120
Short name T403
Test name
Test status
Simulation time 60504781826 ps
CPU time 93.67 seconds
Started Aug 11 06:27:45 PM PDT 24
Finished Aug 11 06:29:19 PM PDT 24
Peak memory 183420 kb
Host smart-4522dc4b-385c-4397-abf3-096ecc749a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570620120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1570620120
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3693753810
Short name T258
Test name
Test status
Simulation time 235061374147 ps
CPU time 144.41 seconds
Started Aug 11 06:27:44 PM PDT 24
Finished Aug 11 06:30:09 PM PDT 24
Peak memory 191696 kb
Host smart-b6f0fc0f-4339-42d6-b0b7-ad2971f9fb69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693753810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3693753810
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.259315825
Short name T153
Test name
Test status
Simulation time 156100395691 ps
CPU time 172.17 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:30:32 PM PDT 24
Peak memory 183420 kb
Host smart-60f6d962-2fbc-4550-9984-43cd65a30fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259315825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.259315825
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3570760284
Short name T370
Test name
Test status
Simulation time 507315980371 ps
CPU time 177.04 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:30:36 PM PDT 24
Peak memory 194924 kb
Host smart-8b7b017b-120d-45d5-8817-55f4f19a8f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570760284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3570760284
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2423539904
Short name T361
Test name
Test status
Simulation time 105337853157 ps
CPU time 46.19 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:28:25 PM PDT 24
Peak memory 183400 kb
Host smart-0884a4bd-1ea1-4246-99a8-b94a00cd078a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423539904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2423539904
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2594981480
Short name T121
Test name
Test status
Simulation time 726427461479 ps
CPU time 410.9 seconds
Started Aug 11 06:27:50 PM PDT 24
Finished Aug 11 06:34:41 PM PDT 24
Peak memory 191504 kb
Host smart-4712735e-89bf-4ceb-8bc9-e0b03692cfc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594981480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2594981480
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.905404030
Short name T144
Test name
Test status
Simulation time 197294585319 ps
CPU time 107.08 seconds
Started Aug 11 06:27:42 PM PDT 24
Finished Aug 11 06:29:29 PM PDT 24
Peak memory 191592 kb
Host smart-2a8fd2ce-fc52-40bf-940a-4cac52a337e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905404030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.905404030
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1076570804
Short name T77
Test name
Test status
Simulation time 68492573610 ps
CPU time 39.82 seconds
Started Aug 11 06:27:44 PM PDT 24
Finished Aug 11 06:28:24 PM PDT 24
Peak memory 183436 kb
Host smart-f32f94b1-4005-4afd-b389-933001033750
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076570804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1076570804
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1556552241
Short name T438
Test name
Test status
Simulation time 164767125209 ps
CPU time 261.76 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:32:02 PM PDT 24
Peak memory 183436 kb
Host smart-4bac3aa8-7111-45dd-878c-f23a8096b851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556552241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1556552241
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2798323489
Short name T426
Test name
Test status
Simulation time 3127002872 ps
CPU time 6.02 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:27:46 PM PDT 24
Peak memory 183488 kb
Host smart-9c8813c3-d249-492a-9521-a13fc660e00f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798323489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2798323489
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.564716294
Short name T279
Test name
Test status
Simulation time 30329673474 ps
CPU time 50.03 seconds
Started Aug 11 06:27:45 PM PDT 24
Finished Aug 11 06:28:35 PM PDT 24
Peak memory 191656 kb
Host smart-f81d98bb-06f8-4de7-bf0b-1f36e408ee8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564716294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.564716294
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1644050256
Short name T58
Test name
Test status
Simulation time 285534220337 ps
CPU time 407.3 seconds
Started Aug 11 06:27:48 PM PDT 24
Finished Aug 11 06:34:35 PM PDT 24
Peak memory 183416 kb
Host smart-a44b6506-d6dd-43ef-a00d-842c97e1f5d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644050256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1644050256
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2758443859
Short name T377
Test name
Test status
Simulation time 47078728565 ps
CPU time 31.2 seconds
Started Aug 11 06:27:42 PM PDT 24
Finished Aug 11 06:28:13 PM PDT 24
Peak memory 183408 kb
Host smart-cf758132-46cc-4e9d-a9f2-a7a63ae2763d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758443859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2758443859
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.25034080
Short name T53
Test name
Test status
Simulation time 627150450 ps
CPU time 0.98 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:27:41 PM PDT 24
Peak memory 191820 kb
Host smart-f2194636-1d23-489d-9b37-1cff6174f8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25034080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.25034080
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.551685815
Short name T322
Test name
Test status
Simulation time 3120040369631 ps
CPU time 1112.9 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:46:14 PM PDT 24
Peak memory 183420 kb
Host smart-19ccf2e8-178f-44a4-af96-47470ccc9fb1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551685815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.551685815
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1690407345
Short name T365
Test name
Test status
Simulation time 272840036478 ps
CPU time 124.45 seconds
Started Aug 11 06:27:47 PM PDT 24
Finished Aug 11 06:29:52 PM PDT 24
Peak memory 183420 kb
Host smart-1bd5f0c6-bc4e-4674-9a2b-45865f33dd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690407345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1690407345
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1477348045
Short name T420
Test name
Test status
Simulation time 114433473869 ps
CPU time 156.73 seconds
Started Aug 11 06:27:42 PM PDT 24
Finished Aug 11 06:30:19 PM PDT 24
Peak memory 191628 kb
Host smart-d854c34d-112d-42a3-b98b-f62c3bcce4ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477348045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1477348045
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2689033023
Short name T327
Test name
Test status
Simulation time 23871166882 ps
CPU time 37.88 seconds
Started Aug 11 06:27:43 PM PDT 24
Finished Aug 11 06:28:21 PM PDT 24
Peak memory 183412 kb
Host smart-31ea1d04-2c3f-4a6d-a23d-30dee0acf740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689033023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2689033023
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.714237965
Short name T407
Test name
Test status
Simulation time 65649306659 ps
CPU time 49.82 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:28:27 PM PDT 24
Peak memory 183472 kb
Host smart-61836bdf-8fe7-4483-bd51-edfb9385a3b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714237965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
714237965
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1882628179
Short name T232
Test name
Test status
Simulation time 847416752392 ps
CPU time 452.12 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:35:12 PM PDT 24
Peak memory 183440 kb
Host smart-e0ac1273-27c3-4085-a6eb-4505a98898d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882628179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1882628179
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.201157500
Short name T417
Test name
Test status
Simulation time 33103720818 ps
CPU time 51.71 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:28:32 PM PDT 24
Peak memory 183456 kb
Host smart-a7e34b21-effd-4ba5-98e8-dd931ef7a1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201157500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.201157500
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1116051400
Short name T113
Test name
Test status
Simulation time 81461250961 ps
CPU time 64.02 seconds
Started Aug 11 06:27:43 PM PDT 24
Finished Aug 11 06:28:47 PM PDT 24
Peak memory 191712 kb
Host smart-ee0ab815-3a69-4f37-86af-28cca06a3c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116051400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1116051400
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2092770459
Short name T139
Test name
Test status
Simulation time 19090733497 ps
CPU time 66.43 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:28:45 PM PDT 24
Peak memory 192192 kb
Host smart-7ba4586d-db16-43f7-8438-64efdbf109f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092770459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2092770459
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.745349286
Short name T36
Test name
Test status
Simulation time 43624000084 ps
CPU time 95.37 seconds
Started Aug 11 06:27:42 PM PDT 24
Finished Aug 11 06:29:17 PM PDT 24
Peak memory 198188 kb
Host smart-cabcd167-d959-4a5c-9ba6-cdc7ea28910c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745349286 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.745349286
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.167035021
Short name T145
Test name
Test status
Simulation time 1169802628580 ps
CPU time 490.76 seconds
Started Aug 11 06:27:49 PM PDT 24
Finished Aug 11 06:36:00 PM PDT 24
Peak memory 183492 kb
Host smart-8610f713-6c93-42a6-a361-48dda82d42c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167035021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.167035021
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.184099778
Short name T405
Test name
Test status
Simulation time 50867673508 ps
CPU time 62.15 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:28:43 PM PDT 24
Peak memory 183420 kb
Host smart-dff0db27-4610-4ad8-9d43-63987aa0613a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184099778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.184099778
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3024102456
Short name T439
Test name
Test status
Simulation time 998175925660 ps
CPU time 378.53 seconds
Started Aug 11 06:27:45 PM PDT 24
Finished Aug 11 06:34:04 PM PDT 24
Peak memory 191632 kb
Host smart-bfcfabf5-3e92-4715-a792-1247dd967fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024102456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3024102456
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3509039810
Short name T79
Test name
Test status
Simulation time 71009480683 ps
CPU time 100.55 seconds
Started Aug 11 06:27:42 PM PDT 24
Finished Aug 11 06:29:22 PM PDT 24
Peak memory 183420 kb
Host smart-6193c595-dbaf-496e-b972-7929059da613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509039810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3509039810
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.318702180
Short name T340
Test name
Test status
Simulation time 124504076807 ps
CPU time 518.38 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:36:18 PM PDT 24
Peak memory 191648 kb
Host smart-e1b9bf2d-f30a-44b3-bbe0-ede8ae0d45b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318702180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.318702180
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1291108016
Short name T431
Test name
Test status
Simulation time 46255714766 ps
CPU time 77.75 seconds
Started Aug 11 06:27:41 PM PDT 24
Finished Aug 11 06:28:59 PM PDT 24
Peak memory 183480 kb
Host smart-78edaead-e030-4c21-bce2-d9c0a347f6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291108016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1291108016
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2024881126
Short name T445
Test name
Test status
Simulation time 1181804360442 ps
CPU time 592.39 seconds
Started Aug 11 06:27:44 PM PDT 24
Finished Aug 11 06:37:37 PM PDT 24
Peak memory 191636 kb
Host smart-a4d51d06-a690-4fd8-8360-6dce636e7b89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024881126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2024881126
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.619187672
Short name T359
Test name
Test status
Simulation time 508068679594 ps
CPU time 195.05 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:30:55 PM PDT 24
Peak memory 183456 kb
Host smart-c3344919-8557-4c15-8166-d492da6ce97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619187672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.619187672
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.920980184
Short name T136
Test name
Test status
Simulation time 430309043802 ps
CPU time 260.29 seconds
Started Aug 11 06:27:33 PM PDT 24
Finished Aug 11 06:31:53 PM PDT 24
Peak memory 191604 kb
Host smart-70c7aac3-813d-4cb3-951d-43007d757000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920980184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.920980184
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.562524838
Short name T427
Test name
Test status
Simulation time 127641278217 ps
CPU time 112.43 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:29:32 PM PDT 24
Peak memory 191648 kb
Host smart-01f077d3-44b8-476d-b4d4-70baf4a1c0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562524838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.562524838
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3086053288
Short name T15
Test name
Test status
Simulation time 1422655657 ps
CPU time 0.9 seconds
Started Aug 11 06:27:36 PM PDT 24
Finished Aug 11 06:27:37 PM PDT 24
Peak memory 214176 kb
Host smart-5bdd311e-b17b-4e02-a605-47d8eb326aba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086053288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3086053288
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1253091594
Short name T383
Test name
Test status
Simulation time 62319936 ps
CPU time 0.58 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:27:40 PM PDT 24
Peak memory 183208 kb
Host smart-14efce87-cd97-410d-a71b-8e6b647e9a3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253091594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1253091594
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.1241530646
Short name T13
Test name
Test status
Simulation time 57269774421 ps
CPU time 325.1 seconds
Started Aug 11 06:27:28 PM PDT 24
Finished Aug 11 06:32:53 PM PDT 24
Peak memory 207936 kb
Host smart-a54b1ff6-802b-4c57-9d0d-28616497ffa6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241530646 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.1241530646
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.967621131
Short name T168
Test name
Test status
Simulation time 284273731700 ps
CPU time 146.82 seconds
Started Aug 11 06:27:46 PM PDT 24
Finished Aug 11 06:30:13 PM PDT 24
Peak memory 183404 kb
Host smart-663037c0-8f94-4bd7-b205-24fb460b4117
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967621131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.967621131
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2630309268
Short name T411
Test name
Test status
Simulation time 260212052691 ps
CPU time 200.75 seconds
Started Aug 11 06:27:59 PM PDT 24
Finished Aug 11 06:31:20 PM PDT 24
Peak memory 183292 kb
Host smart-24577a6f-7b3f-4e35-9ba4-7770bf6273e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630309268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2630309268
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.676360917
Short name T274
Test name
Test status
Simulation time 125523312254 ps
CPU time 46.15 seconds
Started Aug 11 06:27:42 PM PDT 24
Finished Aug 11 06:28:28 PM PDT 24
Peak memory 183220 kb
Host smart-2ee790c0-f0d7-4b37-ba94-7236819ce047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676360917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.676360917
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1044082197
Short name T333
Test name
Test status
Simulation time 111290195139 ps
CPU time 321.9 seconds
Started Aug 11 06:27:43 PM PDT 24
Finished Aug 11 06:33:05 PM PDT 24
Peak memory 191856 kb
Host smart-7ae63ef1-42d3-4c0d-80f9-4d9275ebd229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044082197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1044082197
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.1647841789
Short name T38
Test name
Test status
Simulation time 85434227100 ps
CPU time 558.02 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:36:59 PM PDT 24
Peak memory 206336 kb
Host smart-7fb19fe7-8a1e-4af6-ae63-767569c063e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647841789 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.1647841789
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3119729721
Short name T55
Test name
Test status
Simulation time 204105605462 ps
CPU time 329.07 seconds
Started Aug 11 06:27:48 PM PDT 24
Finished Aug 11 06:33:17 PM PDT 24
Peak memory 183256 kb
Host smart-cc07f470-ac4e-4f38-9978-9e3b7bd7229a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119729721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3119729721
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3228177594
Short name T388
Test name
Test status
Simulation time 488966012683 ps
CPU time 261.02 seconds
Started Aug 11 06:27:44 PM PDT 24
Finished Aug 11 06:32:05 PM PDT 24
Peak memory 183452 kb
Host smart-aa6e46ce-1c0a-4fd0-9970-36131c59bea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228177594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3228177594
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2244217257
Short name T141
Test name
Test status
Simulation time 221174933505 ps
CPU time 158.29 seconds
Started Aug 11 06:27:45 PM PDT 24
Finished Aug 11 06:30:23 PM PDT 24
Peak memory 191640 kb
Host smart-93d0217f-55d2-4cac-a135-9195dce33a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244217257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2244217257
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2952786549
Short name T63
Test name
Test status
Simulation time 757765276684 ps
CPU time 650.66 seconds
Started Aug 11 06:27:52 PM PDT 24
Finished Aug 11 06:38:43 PM PDT 24
Peak memory 191620 kb
Host smart-2a4b371a-2395-4503-b308-ee401133a66e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952786549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2952786549
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3588041008
Short name T56
Test name
Test status
Simulation time 120995164241 ps
CPU time 185.44 seconds
Started Aug 11 06:27:42 PM PDT 24
Finished Aug 11 06:30:58 PM PDT 24
Peak memory 183416 kb
Host smart-fb0792ea-6f0c-4c66-9269-a93375a8eddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588041008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3588041008
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.4194766775
Short name T424
Test name
Test status
Simulation time 204536778312 ps
CPU time 74.06 seconds
Started Aug 11 06:27:47 PM PDT 24
Finished Aug 11 06:29:01 PM PDT 24
Peak memory 183500 kb
Host smart-35b7308e-22b4-4fde-8dc9-d3db9517f089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194766775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4194766775
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2079586701
Short name T157
Test name
Test status
Simulation time 46087628696 ps
CPU time 62.98 seconds
Started Aug 11 06:27:43 PM PDT 24
Finished Aug 11 06:28:46 PM PDT 24
Peak memory 194124 kb
Host smart-536f243c-b45d-4791-aece-0867f594cf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079586701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2079586701
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.4029546806
Short name T261
Test name
Test status
Simulation time 1073213244185 ps
CPU time 550.2 seconds
Started Aug 11 06:27:51 PM PDT 24
Finished Aug 11 06:37:01 PM PDT 24
Peak memory 191660 kb
Host smart-19877f4e-c3c3-41d7-a9d4-92f35dd9f6b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029546806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.4029546806
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2098830344
Short name T126
Test name
Test status
Simulation time 3905150068983 ps
CPU time 1400.96 seconds
Started Aug 11 06:27:56 PM PDT 24
Finished Aug 11 06:51:17 PM PDT 24
Peak memory 183448 kb
Host smart-7c1e977f-f95d-48c5-bf69-18d73a5ec5c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098830344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2098830344
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random.768404702
Short name T150
Test name
Test status
Simulation time 483512119221 ps
CPU time 454.2 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:35:15 PM PDT 24
Peak memory 194932 kb
Host smart-0bedefc7-71a6-44a9-b4de-2a7c05220d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768404702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.768404702
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1469563127
Short name T433
Test name
Test status
Simulation time 1363435456 ps
CPU time 1.1 seconds
Started Aug 11 06:27:48 PM PDT 24
Finished Aug 11 06:27:49 PM PDT 24
Peak memory 183216 kb
Host smart-6e101336-0f82-4a9f-a403-b826df2ccd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469563127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1469563127
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2525605894
Short name T67
Test name
Test status
Simulation time 769981229687 ps
CPU time 1380.18 seconds
Started Aug 11 06:27:48 PM PDT 24
Finished Aug 11 06:50:48 PM PDT 24
Peak memory 191656 kb
Host smart-94e33cfa-f386-4c76-aaeb-4c08355fb676
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525605894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2525605894
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3662597264
Short name T250
Test name
Test status
Simulation time 818793016890 ps
CPU time 407.26 seconds
Started Aug 11 06:27:48 PM PDT 24
Finished Aug 11 06:34:36 PM PDT 24
Peak memory 183376 kb
Host smart-010d9e16-2139-4ef2-83d9-b3407704034e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662597264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3662597264
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3334787862
Short name T369
Test name
Test status
Simulation time 238804357083 ps
CPU time 95 seconds
Started Aug 11 06:27:58 PM PDT 24
Finished Aug 11 06:29:34 PM PDT 24
Peak memory 183428 kb
Host smart-eaee5f5a-f182-41b6-9188-85a7fc6df24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334787862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3334787862
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.4170275728
Short name T286
Test name
Test status
Simulation time 164223683785 ps
CPU time 528.5 seconds
Started Aug 11 06:27:57 PM PDT 24
Finished Aug 11 06:36:46 PM PDT 24
Peak memory 191608 kb
Host smart-7c7ce34d-ac60-4665-94f5-3a41f62c220f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170275728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.4170275728
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.631062754
Short name T399
Test name
Test status
Simulation time 255686013 ps
CPU time 0.72 seconds
Started Aug 11 06:27:48 PM PDT 24
Finished Aug 11 06:27:49 PM PDT 24
Peak memory 183204 kb
Host smart-c14252e8-5158-4c1b-8aab-79ed97175ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631062754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.631062754
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.85447679
Short name T374
Test name
Test status
Simulation time 218667659845 ps
CPU time 267.8 seconds
Started Aug 11 06:27:50 PM PDT 24
Finished Aug 11 06:32:18 PM PDT 24
Peak memory 183444 kb
Host smart-e9b9b290-a914-43f3-8f57-b62e8900ca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85447679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.85447679
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.38430427
Short name T371
Test name
Test status
Simulation time 127406014998 ps
CPU time 57.42 seconds
Started Aug 11 06:27:49 PM PDT 24
Finished Aug 11 06:28:46 PM PDT 24
Peak memory 183444 kb
Host smart-b3a24bdb-7edd-44f8-9b11-dfe3ad9f64af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38430427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.38430427
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1212332787
Short name T410
Test name
Test status
Simulation time 33247155 ps
CPU time 0.54 seconds
Started Aug 11 06:27:49 PM PDT 24
Finished Aug 11 06:27:49 PM PDT 24
Peak memory 183176 kb
Host smart-c89e3819-c3cd-401f-a8d0-129434f250d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212332787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1212332787
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1371980080
Short name T210
Test name
Test status
Simulation time 2367531382189 ps
CPU time 1333.4 seconds
Started Aug 11 06:28:05 PM PDT 24
Finished Aug 11 06:50:18 PM PDT 24
Peak memory 191648 kb
Host smart-8acf7bba-9199-445d-8396-4d9017fc8bf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371980080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1371980080
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2972151254
Short name T404
Test name
Test status
Simulation time 233871002053 ps
CPU time 371.58 seconds
Started Aug 11 06:27:59 PM PDT 24
Finished Aug 11 06:34:11 PM PDT 24
Peak memory 183392 kb
Host smart-35bae23e-cd72-489d-a183-37887af9923d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972151254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2972151254
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1238600520
Short name T396
Test name
Test status
Simulation time 807603186 ps
CPU time 1.1 seconds
Started Aug 11 06:27:58 PM PDT 24
Finished Aug 11 06:27:59 PM PDT 24
Peak memory 183220 kb
Host smart-42170ec3-001e-40df-8ec5-00dbd1071b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238600520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1238600520
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1553452012
Short name T140
Test name
Test status
Simulation time 69694270751 ps
CPU time 202.62 seconds
Started Aug 11 06:28:03 PM PDT 24
Finished Aug 11 06:31:25 PM PDT 24
Peak memory 191660 kb
Host smart-8c13e37c-d995-4129-a57f-b026ca1a13f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553452012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1553452012
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.869356704
Short name T11
Test name
Test status
Simulation time 130877908 ps
CPU time 1.06 seconds
Started Aug 11 06:27:58 PM PDT 24
Finished Aug 11 06:27:59 PM PDT 24
Peak memory 191596 kb
Host smart-a20ba8da-d335-45a7-b54b-74250e79c6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869356704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.869356704
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1376260294
Short name T72
Test name
Test status
Simulation time 76573850439 ps
CPU time 64.23 seconds
Started Aug 11 06:28:09 PM PDT 24
Finished Aug 11 06:29:14 PM PDT 24
Peak memory 183456 kb
Host smart-d73c2786-2c85-478a-960b-38d42f4bd8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376260294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1376260294
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.550834112
Short name T441
Test name
Test status
Simulation time 300123966414 ps
CPU time 107.66 seconds
Started Aug 11 06:28:05 PM PDT 24
Finished Aug 11 06:29:53 PM PDT 24
Peak memory 183404 kb
Host smart-444e7d7e-641c-45bf-b6ad-e43523603c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550834112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.550834112
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.918376989
Short name T254
Test name
Test status
Simulation time 129372229601 ps
CPU time 90.36 seconds
Started Aug 11 06:28:13 PM PDT 24
Finished Aug 11 06:29:44 PM PDT 24
Peak memory 192884 kb
Host smart-d689da63-51bd-44a9-b978-21268e3c1a42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918376989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.918376989
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1850418594
Short name T162
Test name
Test status
Simulation time 633060379584 ps
CPU time 329.35 seconds
Started Aug 11 06:28:06 PM PDT 24
Finished Aug 11 06:33:35 PM PDT 24
Peak memory 191608 kb
Host smart-aa5482e2-e3fd-4ca4-87f1-e9a9a70bbbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850418594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1850418594
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3309122533
Short name T228
Test name
Test status
Simulation time 1338808065561 ps
CPU time 1442.98 seconds
Started Aug 11 06:28:02 PM PDT 24
Finished Aug 11 06:52:05 PM PDT 24
Peak memory 191624 kb
Host smart-ec923baa-64bd-4d5e-8e0f-3bdb12bc42fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309122533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3309122533
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.939670489
Short name T409
Test name
Test status
Simulation time 33235240812 ps
CPU time 265.73 seconds
Started Aug 11 06:28:05 PM PDT 24
Finished Aug 11 06:32:30 PM PDT 24
Peak memory 198132 kb
Host smart-282ab5b7-f8ee-4211-8aaf-dcda4eba3543
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939670489 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.939670489
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1157994439
Short name T447
Test name
Test status
Simulation time 152557570469 ps
CPU time 142.17 seconds
Started Aug 11 06:27:55 PM PDT 24
Finished Aug 11 06:30:17 PM PDT 24
Peak memory 183436 kb
Host smart-ba73db84-c2a7-4edb-a2a0-91056fe5b42e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157994439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1157994439
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_random.1722486888
Short name T73
Test name
Test status
Simulation time 221218023492 ps
CPU time 56.4 seconds
Started Aug 11 06:28:07 PM PDT 24
Finished Aug 11 06:29:03 PM PDT 24
Peak memory 183480 kb
Host smart-0ee37a0e-05db-463e-9629-8c54789b97bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722486888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1722486888
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3796070794
Short name T304
Test name
Test status
Simulation time 36964108343 ps
CPU time 418.4 seconds
Started Aug 11 06:28:04 PM PDT 24
Finished Aug 11 06:35:03 PM PDT 24
Peak memory 194860 kb
Host smart-5e82af2c-36c3-444b-ab30-e7f4c7347ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796070794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3796070794
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3235393846
Short name T351
Test name
Test status
Simulation time 77530939069 ps
CPU time 131.32 seconds
Started Aug 11 06:27:53 PM PDT 24
Finished Aug 11 06:30:05 PM PDT 24
Peak memory 183452 kb
Host smart-48f90fd5-0efb-48a5-becb-45e049324bf1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235393846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3235393846
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2828112462
Short name T372
Test name
Test status
Simulation time 510823273 ps
CPU time 1.36 seconds
Started Aug 11 06:28:08 PM PDT 24
Finished Aug 11 06:28:10 PM PDT 24
Peak memory 183208 kb
Host smart-d6143df6-c23b-42d5-b6d5-7ca17166b4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828112462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2828112462
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2107884023
Short name T259
Test name
Test status
Simulation time 108903032100 ps
CPU time 387.8 seconds
Started Aug 11 06:28:01 PM PDT 24
Finished Aug 11 06:34:29 PM PDT 24
Peak memory 191616 kb
Host smart-a7865ea0-f99d-44ec-a95f-36c8ce9acafa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107884023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2107884023
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.76462943
Short name T363
Test name
Test status
Simulation time 95588743 ps
CPU time 0.66 seconds
Started Aug 11 06:27:53 PM PDT 24
Finished Aug 11 06:27:54 PM PDT 24
Peak memory 183200 kb
Host smart-2b11edfd-a665-4219-9a7f-366b7da0c017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76462943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.76462943
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2843376984
Short name T266
Test name
Test status
Simulation time 717910039816 ps
CPU time 1133.64 seconds
Started Aug 11 06:27:42 PM PDT 24
Finished Aug 11 06:46:36 PM PDT 24
Peak memory 183148 kb
Host smart-135ddbe2-074b-41bd-9e61-421a9f938541
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843376984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2843376984
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.15909437
Short name T443
Test name
Test status
Simulation time 75418269155 ps
CPU time 75.9 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:28:56 PM PDT 24
Peak memory 183448 kb
Host smart-4cfe6776-f20f-4de6-8401-daeb2f56746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15909437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.15909437
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3710442946
Short name T284
Test name
Test status
Simulation time 266437299190 ps
CPU time 1042.09 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:45:03 PM PDT 24
Peak memory 194868 kb
Host smart-f6b01de3-8413-4da6-8dbb-9c206c1c59fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710442946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3710442946
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3365602191
Short name T76
Test name
Test status
Simulation time 63527694223 ps
CPU time 29.8 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:28:05 PM PDT 24
Peak memory 195260 kb
Host smart-e3d6d025-f41e-4c0d-a2f9-6debfb9ae719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365602191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3365602191
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2268534476
Short name T17
Test name
Test status
Simulation time 302861940 ps
CPU time 0.88 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:27:36 PM PDT 24
Peak memory 214080 kb
Host smart-4f3146f1-3f81-4712-a438-7193a2c999e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268534476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2268534476
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1586896452
Short name T123
Test name
Test status
Simulation time 94516322595 ps
CPU time 110.75 seconds
Started Aug 11 06:28:04 PM PDT 24
Finished Aug 11 06:29:55 PM PDT 24
Peak memory 183416 kb
Host smart-e49439fb-ba81-4567-82ae-e24deae4d49d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586896452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1586896452
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2703973362
Short name T391
Test name
Test status
Simulation time 32286834224 ps
CPU time 43.23 seconds
Started Aug 11 06:27:59 PM PDT 24
Finished Aug 11 06:28:43 PM PDT 24
Peak memory 183424 kb
Host smart-52f1c390-27b0-484d-80f0-f7b172d0cd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703973362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2703973362
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3800603344
Short name T185
Test name
Test status
Simulation time 315869917610 ps
CPU time 1593.25 seconds
Started Aug 11 06:27:53 PM PDT 24
Finished Aug 11 06:54:26 PM PDT 24
Peak memory 191688 kb
Host smart-2bd1a64f-cb5d-425c-a4a5-edfcd01cde77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800603344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3800603344
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2555336917
Short name T320
Test name
Test status
Simulation time 301113014724 ps
CPU time 516.19 seconds
Started Aug 11 06:27:57 PM PDT 24
Finished Aug 11 06:36:33 PM PDT 24
Peak memory 183436 kb
Host smart-487986ad-41b7-46fc-bce5-303117989724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555336917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2555336917
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1428061644
Short name T275
Test name
Test status
Simulation time 119949559209 ps
CPU time 147.75 seconds
Started Aug 11 06:28:08 PM PDT 24
Finished Aug 11 06:30:35 PM PDT 24
Peak memory 191672 kb
Host smart-b275bc75-e5ea-4f48-aeb2-1c7e0f56eec7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428061644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1428061644
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3257932734
Short name T12
Test name
Test status
Simulation time 9758838611 ps
CPU time 103.4 seconds
Started Aug 11 06:28:05 PM PDT 24
Finished Aug 11 06:29:48 PM PDT 24
Peak memory 198104 kb
Host smart-93308459-4181-4df3-98cd-a77575225d40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257932734 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.3257932734
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3178058003
Short name T122
Test name
Test status
Simulation time 1078430574914 ps
CPU time 255.51 seconds
Started Aug 11 06:28:05 PM PDT 24
Finished Aug 11 06:32:21 PM PDT 24
Peak memory 183436 kb
Host smart-84b94104-b298-4a1f-ba65-6a9adc1a9cbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178058003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3178058003
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2456216082
Short name T358
Test name
Test status
Simulation time 383832648310 ps
CPU time 148.75 seconds
Started Aug 11 06:28:11 PM PDT 24
Finished Aug 11 06:30:40 PM PDT 24
Peak memory 183408 kb
Host smart-5a4ab03c-4f4b-4cb2-99b3-7477b5cce855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456216082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2456216082
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2334171435
Short name T100
Test name
Test status
Simulation time 84444418716 ps
CPU time 206.17 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:31:41 PM PDT 24
Peak memory 183408 kb
Host smart-d740f241-b1d2-4d4d-b4b8-98d79478c31b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334171435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2334171435
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2400115831
Short name T195
Test name
Test status
Simulation time 25101210097 ps
CPU time 42.18 seconds
Started Aug 11 06:28:07 PM PDT 24
Finished Aug 11 06:28:49 PM PDT 24
Peak memory 195196 kb
Host smart-5d936588-5bd3-4335-a7de-c29d5b2566bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400115831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2400115831
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.803598482
Short name T102
Test name
Test status
Simulation time 420892563171 ps
CPU time 473.87 seconds
Started Aug 11 06:28:10 PM PDT 24
Finished Aug 11 06:36:04 PM PDT 24
Peak memory 183484 kb
Host smart-860f45c6-a6ab-4bda-aa43-05121f6f6a01
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803598482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.803598482
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1214975080
Short name T421
Test name
Test status
Simulation time 83284790583 ps
CPU time 116.06 seconds
Started Aug 11 06:28:09 PM PDT 24
Finished Aug 11 06:30:05 PM PDT 24
Peak memory 183400 kb
Host smart-db0c3bb7-3fae-48ef-b549-78ccdcbca4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214975080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1214975080
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.455156261
Short name T4
Test name
Test status
Simulation time 65478423655 ps
CPU time 156.09 seconds
Started Aug 11 06:28:06 PM PDT 24
Finished Aug 11 06:30:42 PM PDT 24
Peak memory 183404 kb
Host smart-160190d2-6505-4524-9213-dc64dc5c0941
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455156261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.455156261
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1715747211
Short name T368
Test name
Test status
Simulation time 545813218 ps
CPU time 8.08 seconds
Started Aug 11 06:28:05 PM PDT 24
Finished Aug 11 06:28:13 PM PDT 24
Peak memory 183320 kb
Host smart-64f26ee2-25a9-49a1-9cd1-fa9e34777a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715747211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1715747211
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.867778634
Short name T395
Test name
Test status
Simulation time 511761789638 ps
CPU time 198.99 seconds
Started Aug 11 06:28:08 PM PDT 24
Finished Aug 11 06:31:27 PM PDT 24
Peak memory 191612 kb
Host smart-42683773-9064-472a-aaf8-ef76858361ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867778634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
867778634
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3415978852
Short name T133
Test name
Test status
Simulation time 96527610642 ps
CPU time 48.72 seconds
Started Aug 11 06:28:03 PM PDT 24
Finished Aug 11 06:28:52 PM PDT 24
Peak memory 183400 kb
Host smart-6ad4911e-37de-4679-9f16-355dcb18dee0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415978852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3415978852
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2838503327
Short name T375
Test name
Test status
Simulation time 47026918801 ps
CPU time 62.6 seconds
Started Aug 11 06:28:10 PM PDT 24
Finished Aug 11 06:29:12 PM PDT 24
Peak memory 183424 kb
Host smart-1960e5dc-4667-4a07-a8fd-330a9abd1b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838503327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2838503327
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2189109474
Short name T234
Test name
Test status
Simulation time 519996403710 ps
CPU time 260.3 seconds
Started Aug 11 06:28:07 PM PDT 24
Finished Aug 11 06:32:28 PM PDT 24
Peak memory 191680 kb
Host smart-2f7c0fc2-b87a-4712-9e74-ed432d0d4ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189109474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2189109474
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.86383899
Short name T209
Test name
Test status
Simulation time 71321103780 ps
CPU time 874.01 seconds
Started Aug 11 06:28:08 PM PDT 24
Finished Aug 11 06:42:43 PM PDT 24
Peak memory 183452 kb
Host smart-34cc1de7-c451-49bc-94dc-325bb9b89b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86383899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.86383899
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1982056091
Short name T312
Test name
Test status
Simulation time 28683408248 ps
CPU time 16.48 seconds
Started Aug 11 06:28:04 PM PDT 24
Finished Aug 11 06:28:21 PM PDT 24
Peak memory 183432 kb
Host smart-37fe05b1-8799-41e2-916b-4232b699e901
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982056091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1982056091
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.732425575
Short name T401
Test name
Test status
Simulation time 246091695588 ps
CPU time 93.7 seconds
Started Aug 11 06:28:09 PM PDT 24
Finished Aug 11 06:29:42 PM PDT 24
Peak memory 183476 kb
Host smart-339fd57d-6b5d-4062-b10d-3ccd8064a39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732425575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.732425575
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3278731936
Short name T432
Test name
Test status
Simulation time 89895169898 ps
CPU time 68.68 seconds
Started Aug 11 06:28:20 PM PDT 24
Finished Aug 11 06:29:28 PM PDT 24
Peak memory 183480 kb
Host smart-1beb9264-0843-4819-b7f4-93a23f8a460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278731936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3278731936
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.3236931779
Short name T37
Test name
Test status
Simulation time 76436331113 ps
CPU time 496.29 seconds
Started Aug 11 06:28:13 PM PDT 24
Finished Aug 11 06:36:30 PM PDT 24
Peak memory 206388 kb
Host smart-fc6cb253-8c67-4fdb-a6be-8139bf571761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236931779 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.3236931779
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.917715972
Short name T103
Test name
Test status
Simulation time 1729568057531 ps
CPU time 882.83 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:42:57 PM PDT 24
Peak memory 183468 kb
Host smart-ac6e5a89-d4e9-4e73-872e-00bd013556ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917715972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.917715972
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.659787166
Short name T440
Test name
Test status
Simulation time 538493049077 ps
CPU time 216.94 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:31:53 PM PDT 24
Peak memory 183476 kb
Host smart-d33b2f8e-bc25-4ca7-9fbb-df61f11d922d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659787166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.659787166
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2996980863
Short name T201
Test name
Test status
Simulation time 343183477783 ps
CPU time 168.16 seconds
Started Aug 11 06:28:15 PM PDT 24
Finished Aug 11 06:31:03 PM PDT 24
Peak memory 191572 kb
Host smart-1f884a18-ee54-4919-a863-50e40f8ca4a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996980863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2996980863
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3156684131
Short name T342
Test name
Test status
Simulation time 148946154956 ps
CPU time 77.1 seconds
Started Aug 11 06:28:13 PM PDT 24
Finished Aug 11 06:29:30 PM PDT 24
Peak memory 191648 kb
Host smart-e299be68-1e17-46c8-8884-d29bab3fc8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156684131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3156684131
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1313410068
Short name T65
Test name
Test status
Simulation time 457812247684 ps
CPU time 579.32 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:37:53 PM PDT 24
Peak memory 196348 kb
Host smart-c3105e5c-0027-4034-8fc7-66d1737dfb3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313410068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1313410068
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1000875653
Short name T362
Test name
Test status
Simulation time 705879677751 ps
CPU time 255.12 seconds
Started Aug 11 06:28:13 PM PDT 24
Finished Aug 11 06:32:28 PM PDT 24
Peak memory 183416 kb
Host smart-2609d21d-7e4c-4ea2-bb95-e6c52794398c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000875653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1000875653
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3734955588
Short name T233
Test name
Test status
Simulation time 222969114837 ps
CPU time 1641.72 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:55:39 PM PDT 24
Peak memory 191600 kb
Host smart-591d2ff0-3911-4a75-a515-77fe206f52a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734955588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3734955588
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2314439763
Short name T283
Test name
Test status
Simulation time 43109546041 ps
CPU time 71.77 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:29:28 PM PDT 24
Peak memory 183464 kb
Host smart-78607028-7bc9-4cbc-a871-4a0cdbab67bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314439763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2314439763
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.516580482
Short name T389
Test name
Test status
Simulation time 444322931760 ps
CPU time 188.61 seconds
Started Aug 11 06:28:12 PM PDT 24
Finished Aug 11 06:31:21 PM PDT 24
Peak memory 183420 kb
Host smart-53b7aa7d-d143-4d70-9761-d0348aeec063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516580482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.516580482
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1284517749
Short name T226
Test name
Test status
Simulation time 49959258395 ps
CPU time 292.1 seconds
Started Aug 11 06:28:07 PM PDT 24
Finished Aug 11 06:32:59 PM PDT 24
Peak memory 191524 kb
Host smart-55c45ce7-9cbc-4566-8e55-ac797750cf69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284517749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1284517749
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.904122424
Short name T43
Test name
Test status
Simulation time 28998158256 ps
CPU time 44.13 seconds
Started Aug 11 06:28:10 PM PDT 24
Finished Aug 11 06:28:55 PM PDT 24
Peak memory 183480 kb
Host smart-24c79d98-ae8f-4795-bac4-e04befee690f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904122424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
904122424
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3830935794
Short name T128
Test name
Test status
Simulation time 359406251018 ps
CPU time 327.73 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:33:42 PM PDT 24
Peak memory 183412 kb
Host smart-11350713-7ed8-4d72-9509-a24899abf340
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830935794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3830935794
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.4254393031
Short name T364
Test name
Test status
Simulation time 125201179860 ps
CPU time 154.02 seconds
Started Aug 11 06:28:07 PM PDT 24
Finished Aug 11 06:30:42 PM PDT 24
Peak memory 183436 kb
Host smart-43c9ec25-d0cd-47f6-891b-8c5080854bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254393031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4254393031
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3978002270
Short name T227
Test name
Test status
Simulation time 103773683496 ps
CPU time 499.54 seconds
Started Aug 11 06:28:08 PM PDT 24
Finished Aug 11 06:36:28 PM PDT 24
Peak memory 191620 kb
Host smart-b922396a-4e91-4280-bcd6-ea6661554dca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978002270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3978002270
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.4243785642
Short name T373
Test name
Test status
Simulation time 761615180 ps
CPU time 1.64 seconds
Started Aug 11 06:28:12 PM PDT 24
Finished Aug 11 06:28:14 PM PDT 24
Peak memory 183208 kb
Host smart-1343afe8-3f43-4eae-83f6-b49680c93115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243785642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.4243785642
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.2967738718
Short name T14
Test name
Test status
Simulation time 8073358459 ps
CPU time 66.84 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:29:21 PM PDT 24
Peak memory 198116 kb
Host smart-40bda55c-d3ae-46e3-8210-ec7750fd2a52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967738718 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.2967738718
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.153065944
Short name T309
Test name
Test status
Simulation time 650261298727 ps
CPU time 567.39 seconds
Started Aug 11 06:28:08 PM PDT 24
Finished Aug 11 06:37:36 PM PDT 24
Peak memory 183468 kb
Host smart-c0617e5d-5882-4d92-8063-246938a66334
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153065944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.153065944
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2537604006
Short name T380
Test name
Test status
Simulation time 204238761 ps
CPU time 0.87 seconds
Started Aug 11 06:28:13 PM PDT 24
Finished Aug 11 06:28:14 PM PDT 24
Peak memory 183356 kb
Host smart-a70e690d-0fb6-4596-9593-a5291a6cc591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537604006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2537604006
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.433366397
Short name T446
Test name
Test status
Simulation time 182928133624 ps
CPU time 187.5 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:30:43 PM PDT 24
Peak memory 183432 kb
Host smart-9cdf0aff-815d-4dc9-a788-256d1419b839
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433366397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.433366397
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2486537230
Short name T423
Test name
Test status
Simulation time 116277653394 ps
CPU time 158.75 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:30:17 PM PDT 24
Peak memory 183400 kb
Host smart-583bd54f-1704-4a88-b655-dbe237c11a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486537230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2486537230
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3500439741
Short name T334
Test name
Test status
Simulation time 1417712380808 ps
CPU time 227.77 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:31:28 PM PDT 24
Peak memory 191628 kb
Host smart-1ef9ec56-a9ca-4d32-919b-0658b8275600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500439741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3500439741
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3521488903
Short name T3
Test name
Test status
Simulation time 30902442931 ps
CPU time 274.13 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:32:12 PM PDT 24
Peak memory 191636 kb
Host smart-2f7d2638-c18a-42a9-ab45-e65217c96f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521488903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3521488903
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.4229822029
Short name T255
Test name
Test status
Simulation time 162932309508 ps
CPU time 198.98 seconds
Started Aug 11 06:28:11 PM PDT 24
Finished Aug 11 06:31:30 PM PDT 24
Peak memory 191660 kb
Host smart-378babd4-82fa-41f4-b6c9-318618902a3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229822029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.4229822029
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.778683819
Short name T44
Test name
Test status
Simulation time 44259711508 ps
CPU time 65.84 seconds
Started Aug 11 06:28:08 PM PDT 24
Finished Aug 11 06:29:14 PM PDT 24
Peak memory 183416 kb
Host smart-8a1beb84-37f9-4068-8ba3-6872fb36253f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778683819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.778683819
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.990767613
Short name T273
Test name
Test status
Simulation time 498286914948 ps
CPU time 242.7 seconds
Started Aug 11 06:28:15 PM PDT 24
Finished Aug 11 06:32:18 PM PDT 24
Peak memory 191636 kb
Host smart-77551e34-043e-4213-af88-4fde32e682fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990767613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.990767613
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.4058365326
Short name T202
Test name
Test status
Simulation time 149618669271 ps
CPU time 1241.48 seconds
Started Aug 11 06:28:17 PM PDT 24
Finished Aug 11 06:48:59 PM PDT 24
Peak memory 191636 kb
Host smart-44bb798f-23bf-4761-99d5-22b8f9298154
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058365326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.4058365326
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2681274622
Short name T22
Test name
Test status
Simulation time 187997854410 ps
CPU time 75.12 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:29:32 PM PDT 24
Peak memory 191824 kb
Host smart-7c6ce68a-4038-42bb-a58f-0bbfd39b1247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681274622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2681274622
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3450256328
Short name T57
Test name
Test status
Simulation time 569059758204 ps
CPU time 287.03 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:33:01 PM PDT 24
Peak memory 191656 kb
Host smart-a3ce8479-4638-445e-8b6a-641d4c1dd79b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450256328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3450256328
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2643982964
Short name T205
Test name
Test status
Simulation time 66763304359 ps
CPU time 109.81 seconds
Started Aug 11 06:28:13 PM PDT 24
Finished Aug 11 06:30:02 PM PDT 24
Peak memory 191832 kb
Host smart-c651ff06-cd45-4da3-961d-de0fac978151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643982964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2643982964
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3626674129
Short name T120
Test name
Test status
Simulation time 104629340813 ps
CPU time 3403.47 seconds
Started Aug 11 06:28:09 PM PDT 24
Finished Aug 11 07:24:53 PM PDT 24
Peak memory 191588 kb
Host smart-e7791285-7641-44b7-9634-2a8f318395ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626674129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3626674129
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3845446328
Short name T366
Test name
Test status
Simulation time 86824493141 ps
CPU time 37.99 seconds
Started Aug 11 06:27:40 PM PDT 24
Finished Aug 11 06:28:18 PM PDT 24
Peak memory 183436 kb
Host smart-718bb469-1504-4e4c-be2c-6769e6973c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845446328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3845446328
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1014453814
Short name T306
Test name
Test status
Simulation time 936743037423 ps
CPU time 1412.32 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:51:07 PM PDT 24
Peak memory 191628 kb
Host smart-cb25b343-3fd7-4e72-8b99-477f6ec68f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014453814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1014453814
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3446436412
Short name T170
Test name
Test status
Simulation time 72724941207 ps
CPU time 292.57 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:32:26 PM PDT 24
Peak memory 183440 kb
Host smart-66793719-17b0-4b41-bb32-1e781a4435e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446436412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3446436412
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.866813079
Short name T367
Test name
Test status
Simulation time 111555188 ps
CPU time 0.59 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:27:39 PM PDT 24
Peak memory 183172 kb
Host smart-d51f1ceb-3659-443f-878b-1553ff96b8db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866813079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.866813079
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.543358026
Short name T337
Test name
Test status
Simulation time 68265802277 ps
CPU time 106.09 seconds
Started Aug 11 06:28:19 PM PDT 24
Finished Aug 11 06:30:05 PM PDT 24
Peak memory 191668 kb
Host smart-f8309446-0c68-451e-a422-b7d2bb463303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543358026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.543358026
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1175834243
Short name T40
Test name
Test status
Simulation time 182228358094 ps
CPU time 491.54 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:36:26 PM PDT 24
Peak memory 191628 kb
Host smart-4e4297f0-c4f1-46c4-8549-bda830f9e0be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175834243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1175834243
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3191991780
Short name T344
Test name
Test status
Simulation time 182498640710 ps
CPU time 296.01 seconds
Started Aug 11 06:28:18 PM PDT 24
Finished Aug 11 06:33:14 PM PDT 24
Peak memory 183404 kb
Host smart-a61a2ad5-df04-4322-91d7-3af537cb6828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191991780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3191991780
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.4131035699
Short name T355
Test name
Test status
Simulation time 68799632953 ps
CPU time 59.01 seconds
Started Aug 11 06:28:19 PM PDT 24
Finished Aug 11 06:29:18 PM PDT 24
Peak memory 183460 kb
Host smart-910c136a-e1a8-4a2c-8dab-d98fdbe97923
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131035699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.4131035699
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1005744054
Short name T387
Test name
Test status
Simulation time 98967975807 ps
CPU time 79.78 seconds
Started Aug 11 06:28:15 PM PDT 24
Finished Aug 11 06:29:35 PM PDT 24
Peak memory 183512 kb
Host smart-640ce536-5204-4979-a8ad-ac2f59695e6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005744054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1005744054
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3903720780
Short name T110
Test name
Test status
Simulation time 194433939250 ps
CPU time 84.39 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:29:38 PM PDT 24
Peak memory 191668 kb
Host smart-2c0d54c8-0e0c-40db-9109-216022ffb80c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903720780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3903720780
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1870880311
Short name T187
Test name
Test status
Simulation time 100414236841 ps
CPU time 44.9 seconds
Started Aug 11 06:28:17 PM PDT 24
Finished Aug 11 06:29:02 PM PDT 24
Peak memory 183504 kb
Host smart-cdb7324a-fd97-4388-9d98-ccfc0b6fae75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870880311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1870880311
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.524153197
Short name T278
Test name
Test status
Simulation time 591363854677 ps
CPU time 1642.24 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:55:39 PM PDT 24
Peak memory 191660 kb
Host smart-ea266b3f-129e-426d-82e7-ae4df915efad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524153197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.524153197
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2820757213
Short name T302
Test name
Test status
Simulation time 298887301184 ps
CPU time 144.11 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:30:03 PM PDT 24
Peak memory 183104 kb
Host smart-d41ff0db-c95b-49b6-97ec-c711f0f23569
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820757213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2820757213
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3036064522
Short name T430
Test name
Test status
Simulation time 266589232350 ps
CPU time 208.51 seconds
Started Aug 11 06:27:31 PM PDT 24
Finished Aug 11 06:31:00 PM PDT 24
Peak memory 183404 kb
Host smart-062cd651-b09b-425d-ae0f-8e0fb45f5629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036064522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3036064522
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.411743968
Short name T206
Test name
Test status
Simulation time 206011353291 ps
CPU time 100.19 seconds
Started Aug 11 06:27:31 PM PDT 24
Finished Aug 11 06:29:11 PM PDT 24
Peak memory 191616 kb
Host smart-add8607f-fb0b-48f9-b7c1-71522eb91d7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411743968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.411743968
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2375607036
Short name T167
Test name
Test status
Simulation time 7300511796 ps
CPU time 17.18 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:27:56 PM PDT 24
Peak memory 193304 kb
Host smart-90b042d5-2a0c-4fa0-8580-1da5bc4a031a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375607036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2375607036
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.2889718162
Short name T442
Test name
Test status
Simulation time 180632945535 ps
CPU time 1290.32 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:49:09 PM PDT 24
Peak memory 210580 kb
Host smart-e1ab6763-57ec-4695-a3b2-e23169ed1da3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889718162 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.2889718162
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.1358316192
Short name T251
Test name
Test status
Simulation time 69129732717 ps
CPU time 111.78 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:30:08 PM PDT 24
Peak memory 195248 kb
Host smart-27fb1fa4-3a21-42db-b59b-27ff5cc1d2cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358316192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1358316192
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2901442759
Short name T277
Test name
Test status
Simulation time 194029798288 ps
CPU time 922.84 seconds
Started Aug 11 06:28:19 PM PDT 24
Finished Aug 11 06:43:42 PM PDT 24
Peak memory 191660 kb
Host smart-88eba9c6-156d-47f4-b1d3-6a7066e0c44a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901442759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2901442759
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3413016715
Short name T41
Test name
Test status
Simulation time 226650645337 ps
CPU time 600.29 seconds
Started Aug 11 06:28:17 PM PDT 24
Finished Aug 11 06:38:17 PM PDT 24
Peak memory 191636 kb
Host smart-135fc2cf-f749-4370-955e-2094e0fb6716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413016715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3413016715
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3436187930
Short name T42
Test name
Test status
Simulation time 59418470978 ps
CPU time 539.73 seconds
Started Aug 11 06:28:13 PM PDT 24
Finished Aug 11 06:37:13 PM PDT 24
Peak memory 191632 kb
Host smart-e1ec9a6c-8cb8-46e8-acbc-eab85266d122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436187930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3436187930
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1977183879
Short name T132
Test name
Test status
Simulation time 57391789555 ps
CPU time 90.59 seconds
Started Aug 11 06:28:18 PM PDT 24
Finished Aug 11 06:29:48 PM PDT 24
Peak memory 191640 kb
Host smart-3340600a-0d78-4988-a9e1-5cc758301c2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977183879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1977183879
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1102752782
Short name T198
Test name
Test status
Simulation time 541046812594 ps
CPU time 301.47 seconds
Started Aug 11 06:28:17 PM PDT 24
Finished Aug 11 06:33:19 PM PDT 24
Peak memory 191640 kb
Host smart-8227d14e-1c8a-4ac4-9471-9efc4899e77e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102752782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1102752782
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.532219944
Short name T444
Test name
Test status
Simulation time 150694976517 ps
CPU time 1315.16 seconds
Started Aug 11 06:28:19 PM PDT 24
Finished Aug 11 06:50:14 PM PDT 24
Peak memory 191660 kb
Host smart-b991cc9c-7b47-4b85-a512-f0dd04ea59ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532219944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.532219944
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1866755167
Short name T118
Test name
Test status
Simulation time 100499621252 ps
CPU time 409.48 seconds
Started Aug 11 06:28:15 PM PDT 24
Finished Aug 11 06:35:04 PM PDT 24
Peak memory 191680 kb
Host smart-abfa3863-8d0d-40d3-b1a0-b938c314a7c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866755167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1866755167
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.244187580
Short name T376
Test name
Test status
Simulation time 39970902320 ps
CPU time 71.35 seconds
Started Aug 11 06:28:20 PM PDT 24
Finished Aug 11 06:29:31 PM PDT 24
Peak memory 183472 kb
Host smart-ed0d95e5-ce12-43dc-ba57-9ca5d9eb8f46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244187580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.244187580
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2004030076
Short name T249
Test name
Test status
Simulation time 113363849361 ps
CPU time 179.29 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:30:38 PM PDT 24
Peak memory 183420 kb
Host smart-8ebfe451-793c-47c6-a512-6bcce895fed8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004030076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2004030076
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.689636343
Short name T414
Test name
Test status
Simulation time 437705751215 ps
CPU time 114.48 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:29:32 PM PDT 24
Peak memory 183420 kb
Host smart-02fae9f8-5fb8-4f9a-962c-f4dfe2db8c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689636343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.689636343
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.17203004
Short name T315
Test name
Test status
Simulation time 258255696940 ps
CPU time 259.16 seconds
Started Aug 11 06:27:35 PM PDT 24
Finished Aug 11 06:31:55 PM PDT 24
Peak memory 191696 kb
Host smart-2386087e-ef3a-40a8-a4d6-747fb6ff041a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17203004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.17203004
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3104366829
Short name T252
Test name
Test status
Simulation time 130375025368 ps
CPU time 1122.83 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:46:17 PM PDT 24
Peak memory 183492 kb
Host smart-bef36851-6cff-4069-a14b-b850da2356af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104366829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3104366829
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.1276047846
Short name T394
Test name
Test status
Simulation time 89818788795 ps
CPU time 195.37 seconds
Started Aug 11 06:27:37 PM PDT 24
Finished Aug 11 06:30:53 PM PDT 24
Peak memory 206392 kb
Host smart-8bef365b-264e-4285-a34f-f701644c250e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276047846 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.1276047846
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.233408050
Short name T54
Test name
Test status
Simulation time 2663671446794 ps
CPU time 2644.55 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 07:12:19 PM PDT 24
Peak memory 191712 kb
Host smart-83a2c4dc-a6e1-4fe3-b3ac-15e9575ecb35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233408050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.233408050
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3810113938
Short name T324
Test name
Test status
Simulation time 95715226770 ps
CPU time 152.64 seconds
Started Aug 11 06:28:25 PM PDT 24
Finished Aug 11 06:30:58 PM PDT 24
Peak memory 191672 kb
Host smart-cbde07eb-968a-4858-a4f9-134d3021d266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810113938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3810113938
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1581570114
Short name T356
Test name
Test status
Simulation time 64291931898 ps
CPU time 255.23 seconds
Started Aug 11 06:28:21 PM PDT 24
Finished Aug 11 06:32:36 PM PDT 24
Peak memory 192896 kb
Host smart-e2ffa00b-ecdd-4cd5-963c-36dbf1f2b804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581570114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1581570114
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.4174787486
Short name T188
Test name
Test status
Simulation time 201830605751 ps
CPU time 466.52 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:36:03 PM PDT 24
Peak memory 191624 kb
Host smart-3ca972af-e270-4560-a3f7-be6c2362f2da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174787486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.4174787486
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3762119625
Short name T192
Test name
Test status
Simulation time 39149503169 ps
CPU time 22.72 seconds
Started Aug 11 06:28:19 PM PDT 24
Finished Aug 11 06:28:42 PM PDT 24
Peak memory 191652 kb
Host smart-97d12e96-938b-4e68-8219-f79653d2db14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762119625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3762119625
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.177889864
Short name T434
Test name
Test status
Simulation time 951911702892 ps
CPU time 386.08 seconds
Started Aug 11 06:28:19 PM PDT 24
Finished Aug 11 06:34:46 PM PDT 24
Peak memory 191660 kb
Host smart-e28f302a-789e-46da-88e6-aad7d4170f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177889864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.177889864
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1116819355
Short name T117
Test name
Test status
Simulation time 701187105881 ps
CPU time 2017.29 seconds
Started Aug 11 06:28:13 PM PDT 24
Finished Aug 11 07:01:51 PM PDT 24
Peak memory 191672 kb
Host smart-d877095b-c98a-4e9b-954a-6cfb7aafe7eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116819355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1116819355
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3173491779
Short name T323
Test name
Test status
Simulation time 157184083962 ps
CPU time 60.32 seconds
Started Aug 11 06:28:20 PM PDT 24
Finished Aug 11 06:29:21 PM PDT 24
Peak memory 195096 kb
Host smart-35838dbb-4f1c-44f9-a7e8-75bcc7743050
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173491779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3173491779
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.567519613
Short name T305
Test name
Test status
Simulation time 14337743113 ps
CPU time 23.35 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:28:03 PM PDT 24
Peak memory 183460 kb
Host smart-489b1771-785b-494b-bf3b-f2728b7873bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567519613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.567519613
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2795269669
Short name T393
Test name
Test status
Simulation time 43524227308 ps
CPU time 57.63 seconds
Started Aug 11 06:27:39 PM PDT 24
Finished Aug 11 06:28:37 PM PDT 24
Peak memory 183456 kb
Host smart-68772969-0b80-4cb4-9286-6d9fed4aa22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795269669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2795269669
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.4248288571
Short name T156
Test name
Test status
Simulation time 54828900194 ps
CPU time 38.63 seconds
Started Aug 11 06:27:34 PM PDT 24
Finished Aug 11 06:28:13 PM PDT 24
Peak memory 194284 kb
Host smart-d5bfd0fa-96eb-4eab-9a50-a5e8ac66e0f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248288571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.4248288571
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.4112549667
Short name T246
Test name
Test status
Simulation time 321813606122 ps
CPU time 976.27 seconds
Started Aug 11 06:27:38 PM PDT 24
Finished Aug 11 06:43:55 PM PDT 24
Peak memory 191604 kb
Host smart-bf2b0d3f-bc4d-44bb-992d-6fd1e7269f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112549667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.4112549667
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.994079386
Short name T112
Test name
Test status
Simulation time 1485313174166 ps
CPU time 499.28 seconds
Started Aug 11 06:28:14 PM PDT 24
Finished Aug 11 06:36:34 PM PDT 24
Peak memory 191628 kb
Host smart-e3cf981b-302f-4654-8436-5c4731c03e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994079386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.994079386
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2498506421
Short name T60
Test name
Test status
Simulation time 190018221710 ps
CPU time 77.68 seconds
Started Aug 11 06:28:22 PM PDT 24
Finished Aug 11 06:29:40 PM PDT 24
Peak memory 183624 kb
Host smart-3505fdbe-7662-4123-831b-39f410d4a056
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498506421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2498506421
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3077018373
Short name T219
Test name
Test status
Simulation time 131324790384 ps
CPU time 230.41 seconds
Started Aug 11 06:28:18 PM PDT 24
Finished Aug 11 06:32:08 PM PDT 24
Peak memory 191612 kb
Host smart-4ec824fc-436c-49e2-9f23-7e1a3164e106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077018373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3077018373
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.953714743
Short name T39
Test name
Test status
Simulation time 628447487999 ps
CPU time 733.25 seconds
Started Aug 11 06:28:13 PM PDT 24
Finished Aug 11 06:40:27 PM PDT 24
Peak memory 191704 kb
Host smart-9592101f-dbd5-43ad-8195-e2dbb6586c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953714743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.953714743
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3518236401
Short name T193
Test name
Test status
Simulation time 352176536136 ps
CPU time 361.77 seconds
Started Aug 11 06:28:20 PM PDT 24
Finished Aug 11 06:34:22 PM PDT 24
Peak memory 191680 kb
Host smart-88893771-5c67-410f-9f76-1aacf813108b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518236401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3518236401
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.18862701
Short name T313
Test name
Test status
Simulation time 49059226903 ps
CPU time 309.5 seconds
Started Aug 11 06:28:18 PM PDT 24
Finished Aug 11 06:33:28 PM PDT 24
Peak memory 191608 kb
Host smart-1ef3f898-c981-45d9-8d70-3effde3ebc55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18862701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.18862701
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.4018196418
Short name T216
Test name
Test status
Simulation time 284785139706 ps
CPU time 312.33 seconds
Started Aug 11 06:28:16 PM PDT 24
Finished Aug 11 06:33:29 PM PDT 24
Peak memory 191660 kb
Host smart-9c0c5a95-7e57-4ab6-8b01-0fb104c59055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018196418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.4018196418
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.874145949
Short name T285
Test name
Test status
Simulation time 137446091068 ps
CPU time 275.27 seconds
Started Aug 11 06:28:18 PM PDT 24
Finished Aug 11 06:32:54 PM PDT 24
Peak memory 191668 kb
Host smart-62c41333-45c0-4f47-95d5-9cf4826061a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874145949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.874145949
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2311224768
Short name T295
Test name
Test status
Simulation time 239165988259 ps
CPU time 119.18 seconds
Started Aug 11 06:28:18 PM PDT 24
Finished Aug 11 06:30:17 PM PDT 24
Peak memory 191616 kb
Host smart-4b49a550-44f2-4e0d-a12f-c856e4830fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311224768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2311224768
Directory /workspace/99.rv_timer_random/latest
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