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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.36 98.73 100.00 100.00 100.00 99.43


Total test records in report: 582
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T508 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1351358894 Aug 12 05:16:00 PM PDT 24 Aug 12 05:16:01 PM PDT 24 12564921 ps
T509 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.725141380 Aug 12 05:16:10 PM PDT 24 Aug 12 05:16:10 PM PDT 24 41093341 ps
T510 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1662371247 Aug 12 05:15:49 PM PDT 24 Aug 12 05:15:50 PM PDT 24 13540997 ps
T511 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1329712978 Aug 12 05:16:04 PM PDT 24 Aug 12 05:16:05 PM PDT 24 27230564 ps
T72 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2619287093 Aug 12 05:15:37 PM PDT 24 Aug 12 05:15:38 PM PDT 24 65335975 ps
T512 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1309998283 Aug 12 05:16:10 PM PDT 24 Aug 12 05:16:11 PM PDT 24 27028701 ps
T513 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4121193700 Aug 12 05:15:55 PM PDT 24 Aug 12 05:15:55 PM PDT 24 14329050 ps
T82 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2423076479 Aug 12 05:15:41 PM PDT 24 Aug 12 05:15:42 PM PDT 24 39740849 ps
T514 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1126244240 Aug 12 05:15:41 PM PDT 24 Aug 12 05:15:43 PM PDT 24 424706854 ps
T515 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1403119751 Aug 12 05:15:47 PM PDT 24 Aug 12 05:15:48 PM PDT 24 153003830 ps
T516 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3016815188 Aug 12 05:16:00 PM PDT 24 Aug 12 05:16:02 PM PDT 24 439082568 ps
T517 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4131493003 Aug 12 05:15:40 PM PDT 24 Aug 12 05:15:43 PM PDT 24 2861529940 ps
T518 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2483777725 Aug 12 05:15:44 PM PDT 24 Aug 12 05:15:48 PM PDT 24 171268635 ps
T519 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3197944931 Aug 12 05:15:49 PM PDT 24 Aug 12 05:15:51 PM PDT 24 106976889 ps
T520 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.753270554 Aug 12 05:15:42 PM PDT 24 Aug 12 05:15:44 PM PDT 24 384305936 ps
T521 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.725826675 Aug 12 05:15:38 PM PDT 24 Aug 12 05:15:45 PM PDT 24 28018919 ps
T522 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.906056379 Aug 12 05:15:52 PM PDT 24 Aug 12 05:15:52 PM PDT 24 92512205 ps
T523 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2377944861 Aug 12 05:15:50 PM PDT 24 Aug 12 05:15:51 PM PDT 24 42809603 ps
T524 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1134640070 Aug 12 05:16:04 PM PDT 24 Aug 12 05:16:05 PM PDT 24 14364200 ps
T525 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.136155590 Aug 12 05:16:15 PM PDT 24 Aug 12 05:16:16 PM PDT 24 388375435 ps
T526 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1701968970 Aug 12 05:15:58 PM PDT 24 Aug 12 05:16:00 PM PDT 24 140679461 ps
T73 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2780855566 Aug 12 05:15:42 PM PDT 24 Aug 12 05:15:45 PM PDT 24 168620366 ps
T527 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4237545116 Aug 12 05:16:03 PM PDT 24 Aug 12 05:16:04 PM PDT 24 32511243 ps
T528 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3324354382 Aug 12 05:15:58 PM PDT 24 Aug 12 05:15:58 PM PDT 24 32283237 ps
T529 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2664671669 Aug 12 05:15:56 PM PDT 24 Aug 12 05:15:57 PM PDT 24 47062790 ps
T530 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1941417485 Aug 12 05:15:40 PM PDT 24 Aug 12 05:15:41 PM PDT 24 40456851 ps
T531 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2948579539 Aug 12 05:16:07 PM PDT 24 Aug 12 05:16:07 PM PDT 24 14652937 ps
T532 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2937105693 Aug 12 05:16:08 PM PDT 24 Aug 12 05:16:08 PM PDT 24 15118263 ps
T533 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1293951725 Aug 12 05:16:03 PM PDT 24 Aug 12 05:16:03 PM PDT 24 63006218 ps
T534 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3632819506 Aug 12 05:15:46 PM PDT 24 Aug 12 05:15:47 PM PDT 24 171574963 ps
T535 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1580894208 Aug 12 05:16:02 PM PDT 24 Aug 12 05:16:03 PM PDT 24 38646867 ps
T536 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1506754193 Aug 12 05:16:08 PM PDT 24 Aug 12 05:16:08 PM PDT 24 44231770 ps
T537 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3144566161 Aug 12 05:15:55 PM PDT 24 Aug 12 05:15:55 PM PDT 24 13252916 ps
T538 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2911166849 Aug 12 05:15:53 PM PDT 24 Aug 12 05:15:54 PM PDT 24 48951684 ps
T539 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2416720972 Aug 12 05:15:42 PM PDT 24 Aug 12 05:15:42 PM PDT 24 41883490 ps
T540 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3683156389 Aug 12 05:15:39 PM PDT 24 Aug 12 05:15:40 PM PDT 24 48201461 ps
T74 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1300643366 Aug 12 05:15:41 PM PDT 24 Aug 12 05:15:42 PM PDT 24 14438696 ps
T541 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2815059328 Aug 12 05:15:43 PM PDT 24 Aug 12 05:15:44 PM PDT 24 281931011 ps
T542 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2529568507 Aug 12 05:15:55 PM PDT 24 Aug 12 05:15:56 PM PDT 24 55976878 ps
T89 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2895781676 Aug 12 05:15:42 PM PDT 24 Aug 12 05:15:43 PM PDT 24 170620686 ps
T543 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1226762718 Aug 12 05:16:06 PM PDT 24 Aug 12 05:16:07 PM PDT 24 19024907 ps
T544 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3400223621 Aug 12 05:15:41 PM PDT 24 Aug 12 05:15:42 PM PDT 24 32404112 ps
T545 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3613957009 Aug 12 05:15:57 PM PDT 24 Aug 12 05:15:57 PM PDT 24 16389410 ps
T546 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1086558641 Aug 12 05:15:44 PM PDT 24 Aug 12 05:15:46 PM PDT 24 23303400 ps
T547 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1116364214 Aug 12 05:16:08 PM PDT 24 Aug 12 05:16:08 PM PDT 24 55200272 ps
T548 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1925741745 Aug 12 05:15:48 PM PDT 24 Aug 12 05:15:49 PM PDT 24 45928196 ps
T549 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3502123592 Aug 12 05:15:44 PM PDT 24 Aug 12 05:15:45 PM PDT 24 135102331 ps
T550 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.4107344863 Aug 12 05:15:41 PM PDT 24 Aug 12 05:15:46 PM PDT 24 11401123 ps
T551 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3119240362 Aug 12 05:15:45 PM PDT 24 Aug 12 05:15:46 PM PDT 24 186960442 ps
T552 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3339797337 Aug 12 05:15:43 PM PDT 24 Aug 12 05:15:45 PM PDT 24 40967020 ps
T553 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2674387364 Aug 12 05:15:59 PM PDT 24 Aug 12 05:16:02 PM PDT 24 157465887 ps
T75 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3359071165 Aug 12 05:15:42 PM PDT 24 Aug 12 05:15:43 PM PDT 24 23468841 ps
T554 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1832331669 Aug 12 05:15:51 PM PDT 24 Aug 12 05:15:52 PM PDT 24 106825724 ps
T555 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2184326095 Aug 12 05:16:00 PM PDT 24 Aug 12 05:16:01 PM PDT 24 84771036 ps
T556 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.940589681 Aug 12 05:15:37 PM PDT 24 Aug 12 05:15:38 PM PDT 24 42169568 ps
T557 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1708172721 Aug 12 05:15:52 PM PDT 24 Aug 12 05:15:54 PM PDT 24 150595854 ps
T558 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.8938274 Aug 12 05:16:06 PM PDT 24 Aug 12 05:16:07 PM PDT 24 58693759 ps
T559 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1187637892 Aug 12 05:15:51 PM PDT 24 Aug 12 05:15:52 PM PDT 24 14657784 ps
T560 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1075845360 Aug 12 05:15:43 PM PDT 24 Aug 12 05:15:44 PM PDT 24 51658719 ps
T561 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2005511575 Aug 12 05:15:50 PM PDT 24 Aug 12 05:15:51 PM PDT 24 41907117 ps
T562 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2640721547 Aug 12 05:16:09 PM PDT 24 Aug 12 05:16:10 PM PDT 24 13488545 ps
T563 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4287098145 Aug 12 05:15:36 PM PDT 24 Aug 12 05:15:37 PM PDT 24 98070074 ps
T564 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1579820764 Aug 12 05:15:46 PM PDT 24 Aug 12 05:15:47 PM PDT 24 22685144 ps
T565 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.866715119 Aug 12 05:15:40 PM PDT 24 Aug 12 05:15:42 PM PDT 24 75057072 ps
T566 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1929549634 Aug 12 05:15:52 PM PDT 24 Aug 12 05:15:53 PM PDT 24 25290538 ps
T567 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2180135460 Aug 12 05:15:49 PM PDT 24 Aug 12 05:15:50 PM PDT 24 29276561 ps
T568 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3291225314 Aug 12 05:15:30 PM PDT 24 Aug 12 05:15:31 PM PDT 24 39108992 ps
T569 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.239086134 Aug 12 05:15:46 PM PDT 24 Aug 12 05:15:48 PM PDT 24 34397298 ps
T570 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3421984525 Aug 12 05:16:07 PM PDT 24 Aug 12 05:16:08 PM PDT 24 232500989 ps
T571 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3304716444 Aug 12 05:16:02 PM PDT 24 Aug 12 05:16:05 PM PDT 24 666362452 ps
T572 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2947397138 Aug 12 05:15:43 PM PDT 24 Aug 12 05:15:44 PM PDT 24 40479871 ps
T573 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.59860496 Aug 12 05:15:41 PM PDT 24 Aug 12 05:15:42 PM PDT 24 183594744 ps
T574 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.584620095 Aug 12 05:15:42 PM PDT 24 Aug 12 05:15:43 PM PDT 24 39697372 ps
T575 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.4073174190 Aug 12 05:15:46 PM PDT 24 Aug 12 05:15:47 PM PDT 24 31312362 ps
T576 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2369737282 Aug 12 05:15:40 PM PDT 24 Aug 12 05:15:41 PM PDT 24 28999437 ps
T76 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3882995627 Aug 12 05:16:01 PM PDT 24 Aug 12 05:16:01 PM PDT 24 186895542 ps
T577 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4089786212 Aug 12 05:15:54 PM PDT 24 Aug 12 05:15:55 PM PDT 24 170617607 ps
T578 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3102630021 Aug 12 05:15:51 PM PDT 24 Aug 12 05:15:52 PM PDT 24 16111653 ps
T579 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1614560044 Aug 12 05:16:00 PM PDT 24 Aug 12 05:16:00 PM PDT 24 43494440 ps
T580 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2539227793 Aug 12 05:15:55 PM PDT 24 Aug 12 05:15:56 PM PDT 24 17034174 ps
T581 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2172279049 Aug 12 05:16:08 PM PDT 24 Aug 12 05:16:09 PM PDT 24 19485113 ps
T582 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1893352441 Aug 12 05:15:48 PM PDT 24 Aug 12 05:15:51 PM PDT 24 53607678 ps

Test location /workspace/coverage/default/50.rv_timer_random.3170618862
Short name T2
Test name
Test status
Simulation time 139337507405 ps
CPU time 268.75 seconds
Started Aug 12 05:16:46 PM PDT 24
Finished Aug 12 05:21:15 PM PDT 24
Peak memory 191348 kb
Host smart-d3a66be0-3bd6-4cb0-b0eb-20f82561acc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170618862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3170618862
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.1024956330
Short name T14
Test name
Test status
Simulation time 3438368881 ps
CPU time 27.64 seconds
Started Aug 12 05:16:33 PM PDT 24
Finished Aug 12 05:17:01 PM PDT 24
Peak memory 197012 kb
Host smart-fa6760bd-c781-4f23-b5bf-ef57acd414b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024956330 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.1024956330
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1712647868
Short name T30
Test name
Test status
Simulation time 459327779 ps
CPU time 1.31 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 196004 kb
Host smart-b90e14d0-6333-4d68-9b1a-e9278a8f67f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712647868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1712647868
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1727696645
Short name T59
Test name
Test status
Simulation time 368172881846 ps
CPU time 996.83 seconds
Started Aug 12 05:16:43 PM PDT 24
Finished Aug 12 05:33:20 PM PDT 24
Peak memory 195836 kb
Host smart-59227c8a-1649-40ec-9414-fb8643ab6bfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727696645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1727696645
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.4240035273
Short name T170
Test name
Test status
Simulation time 1314123424460 ps
CPU time 1548.28 seconds
Started Aug 12 05:16:08 PM PDT 24
Finished Aug 12 05:41:57 PM PDT 24
Peak memory 191304 kb
Host smart-cafe251d-2a2a-4fc7-9c1e-7e415daea221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240035273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
4240035273
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1788431742
Short name T141
Test name
Test status
Simulation time 801517216748 ps
CPU time 2634.27 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 06:00:08 PM PDT 24
Peak memory 191288 kb
Host smart-c7a8ad10-9dbd-457b-b1ca-544e789d70a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788431742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1788431742
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1905111055
Short name T129
Test name
Test status
Simulation time 473117737006 ps
CPU time 894.92 seconds
Started Aug 12 05:16:35 PM PDT 24
Finished Aug 12 05:31:30 PM PDT 24
Peak memory 191276 kb
Host smart-1f1f0c99-6d02-4122-a287-28ca9dd955ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905111055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1905111055
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3814656782
Short name T12
Test name
Test status
Simulation time 353276647814 ps
CPU time 1676.16 seconds
Started Aug 12 05:16:32 PM PDT 24
Finished Aug 12 05:44:29 PM PDT 24
Peak memory 195928 kb
Host smart-bbc7fb77-31be-4381-8c55-14fb6a446d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814656782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3814656782
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.766927128
Short name T58
Test name
Test status
Simulation time 1766775005543 ps
CPU time 915.17 seconds
Started Aug 12 05:16:08 PM PDT 24
Finished Aug 12 05:31:23 PM PDT 24
Peak memory 191332 kb
Host smart-a02219b5-9ddb-41a3-a4ac-7c0f3fbc0f4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766927128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.766927128
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3799067689
Short name T144
Test name
Test status
Simulation time 2917477773747 ps
CPU time 1891.09 seconds
Started Aug 12 05:16:15 PM PDT 24
Finished Aug 12 05:47:47 PM PDT 24
Peak memory 191188 kb
Host smart-36508cdc-7cf0-403a-8e3a-3eb19183a2b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799067689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3799067689
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3095857447
Short name T182
Test name
Test status
Simulation time 1226225641002 ps
CPU time 2256.03 seconds
Started Aug 12 05:16:39 PM PDT 24
Finished Aug 12 05:54:15 PM PDT 24
Peak memory 191208 kb
Host smart-94501b98-e256-4de8-ae64-3722a27588f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095857447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3095857447
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2934648004
Short name T64
Test name
Test status
Simulation time 73764368 ps
CPU time 0.58 seconds
Started Aug 12 05:15:53 PM PDT 24
Finished Aug 12 05:15:54 PM PDT 24
Peak memory 183208 kb
Host smart-0dc6c7b9-7f57-4256-8450-fd913297e708
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934648004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2934648004
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/167.rv_timer_random.820218219
Short name T117
Test name
Test status
Simulation time 246385271112 ps
CPU time 367.36 seconds
Started Aug 12 05:17:05 PM PDT 24
Finished Aug 12 05:23:12 PM PDT 24
Peak memory 195276 kb
Host smart-b7aaff32-e94a-43b0-a139-b86b082bedba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820218219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.820218219
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1740912698
Short name T339
Test name
Test status
Simulation time 1872862963067 ps
CPU time 2177.57 seconds
Started Aug 12 05:16:01 PM PDT 24
Finished Aug 12 05:52:19 PM PDT 24
Peak memory 196540 kb
Host smart-a22c8f4f-0c01-427c-80a8-51a8af49fd88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740912698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1740912698
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3452817561
Short name T20
Test name
Test status
Simulation time 35553068 ps
CPU time 0.79 seconds
Started Aug 12 05:16:02 PM PDT 24
Finished Aug 12 05:16:03 PM PDT 24
Peak memory 213528 kb
Host smart-44137c79-24f1-4ae8-9964-ac60a045496b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452817561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3452817561
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3547719559
Short name T338
Test name
Test status
Simulation time 357728512042 ps
CPU time 1699.14 seconds
Started Aug 12 05:16:31 PM PDT 24
Finished Aug 12 05:44:51 PM PDT 24
Peak memory 191176 kb
Host smart-fd29f16a-c1f4-44ad-9ca0-0e9fc57040f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547719559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3547719559
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2681944527
Short name T93
Test name
Test status
Simulation time 609890111735 ps
CPU time 539.91 seconds
Started Aug 12 05:16:05 PM PDT 24
Finished Aug 12 05:25:05 PM PDT 24
Peak memory 183112 kb
Host smart-027b2f92-b948-473c-8105-d35e9e722372
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681944527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2681944527
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/153.rv_timer_random.714877986
Short name T175
Test name
Test status
Simulation time 210565549866 ps
CPU time 644.35 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:27:45 PM PDT 24
Peak memory 191344 kb
Host smart-dbdd2452-b1ae-494b-b5b4-385d88de25dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714877986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.714877986
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.235690108
Short name T101
Test name
Test status
Simulation time 146028993280 ps
CPU time 254.49 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 05:20:28 PM PDT 24
Peak memory 183248 kb
Host smart-a357c140-9655-4ae7-beda-dd312350f6bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235690108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.235690108
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1121743609
Short name T197
Test name
Test status
Simulation time 728711679610 ps
CPU time 634.45 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:26:47 PM PDT 24
Peak memory 197028 kb
Host smart-20ce2b68-8057-4136-bf0e-15a483f4e0de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121743609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1121743609
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/124.rv_timer_random.3596381935
Short name T136
Test name
Test status
Simulation time 173731336623 ps
CPU time 3174.91 seconds
Started Aug 12 05:16:51 PM PDT 24
Finished Aug 12 06:09:47 PM PDT 24
Peak memory 191348 kb
Host smart-26521a96-6fcc-4e0c-b132-888380dd4fb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596381935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3596381935
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3135843261
Short name T160
Test name
Test status
Simulation time 203074948368 ps
CPU time 500.54 seconds
Started Aug 12 05:16:05 PM PDT 24
Finished Aug 12 05:24:26 PM PDT 24
Peak memory 191328 kb
Host smart-c7e380de-0b74-4a14-b796-a99a67b05b25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135843261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3135843261
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/172.rv_timer_random.3366601615
Short name T149
Test name
Test status
Simulation time 285776263825 ps
CPU time 569.59 seconds
Started Aug 12 05:16:59 PM PDT 24
Finished Aug 12 05:26:28 PM PDT 24
Peak memory 191280 kb
Host smart-48547f88-9a6d-4eb2-a046-6f3816b5f235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366601615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3366601615
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2802094688
Short name T273
Test name
Test status
Simulation time 418589947303 ps
CPU time 581.29 seconds
Started Aug 12 05:16:41 PM PDT 24
Finished Aug 12 05:26:22 PM PDT 24
Peak memory 191160 kb
Host smart-ee413e26-4bac-4c61-b174-249e8f98ce65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802094688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2802094688
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/144.rv_timer_random.3703049643
Short name T126
Test name
Test status
Simulation time 362642880527 ps
CPU time 950.18 seconds
Started Aug 12 05:16:55 PM PDT 24
Finished Aug 12 05:32:45 PM PDT 24
Peak memory 191328 kb
Host smart-fec48f70-39e3-4cf8-a861-4c0c08283141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703049643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3703049643
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.4035867961
Short name T186
Test name
Test status
Simulation time 2121779794575 ps
CPU time 977.09 seconds
Started Aug 12 05:16:31 PM PDT 24
Finished Aug 12 05:32:48 PM PDT 24
Peak memory 191364 kb
Host smart-86388be0-19b0-45f6-8854-7d454a57733a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035867961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.4035867961
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1293286009
Short name T157
Test name
Test status
Simulation time 529023365674 ps
CPU time 938.82 seconds
Started Aug 12 05:16:50 PM PDT 24
Finished Aug 12 05:32:29 PM PDT 24
Peak memory 195292 kb
Host smart-180c6b71-6382-4215-b1b7-89349a4089cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293286009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1293286009
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.2823028450
Short name T272
Test name
Test status
Simulation time 170179458400 ps
CPU time 540.47 seconds
Started Aug 12 05:16:55 PM PDT 24
Finished Aug 12 05:25:56 PM PDT 24
Peak memory 191356 kb
Host smart-2a017c2a-02cd-4ac6-9be7-dbe11aae2ec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823028450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2823028450
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.1871402650
Short name T210
Test name
Test status
Simulation time 150666621874 ps
CPU time 827.01 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:30:47 PM PDT 24
Peak memory 191240 kb
Host smart-dabbfe67-2ad2-40ac-a7e7-b1e213650fc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871402650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1871402650
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.711532168
Short name T268
Test name
Test status
Simulation time 4379641291950 ps
CPU time 2253.74 seconds
Started Aug 12 05:16:45 PM PDT 24
Finished Aug 12 05:54:19 PM PDT 24
Peak memory 191352 kb
Host smart-5d7b9ddf-bff1-40d5-bf98-cee354e9f1e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711532168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
711532168
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.694732793
Short name T214
Test name
Test status
Simulation time 423905261697 ps
CPU time 781.32 seconds
Started Aug 12 05:16:35 PM PDT 24
Finished Aug 12 05:29:37 PM PDT 24
Peak memory 183072 kb
Host smart-bf3565a7-2bc1-4c06-8a54-1c3c336261f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694732793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.694732793
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/118.rv_timer_random.1336560567
Short name T161
Test name
Test status
Simulation time 593402412408 ps
CPU time 535.23 seconds
Started Aug 12 05:16:45 PM PDT 24
Finished Aug 12 05:25:40 PM PDT 24
Peak memory 191240 kb
Host smart-7443d06f-0b3e-48d3-ba37-101ef009f31b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336560567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1336560567
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1454789315
Short name T213
Test name
Test status
Simulation time 290301882786 ps
CPU time 156.59 seconds
Started Aug 12 05:16:10 PM PDT 24
Finished Aug 12 05:18:47 PM PDT 24
Peak memory 183152 kb
Host smart-05a43015-4b57-4bd0-a040-f6a99d3a9cbe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454789315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1454789315
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/198.rv_timer_random.1990098458
Short name T192
Test name
Test status
Simulation time 374773764499 ps
CPU time 363.94 seconds
Started Aug 12 05:17:12 PM PDT 24
Finished Aug 12 05:23:16 PM PDT 24
Peak memory 191352 kb
Host smart-a7d5044b-3bbc-4182-a4d2-fe3c1dc67066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990098458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1990098458
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random.965388666
Short name T181
Test name
Test status
Simulation time 582878202524 ps
CPU time 1027.64 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:33:20 PM PDT 24
Peak memory 191264 kb
Host smart-c740d984-c346-4764-8c47-b1a2b332d009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965388666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.965388666
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3701764001
Short name T189
Test name
Test status
Simulation time 2015633628161 ps
CPU time 2796.04 seconds
Started Aug 12 05:16:09 PM PDT 24
Finished Aug 12 06:02:45 PM PDT 24
Peak memory 194472 kb
Host smart-e1e8e380-8a3d-482f-a1e3-00c8a7ca9d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701764001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3701764001
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1781639848
Short name T206
Test name
Test status
Simulation time 1560211759131 ps
CPU time 2676.84 seconds
Started Aug 12 05:16:17 PM PDT 24
Finished Aug 12 06:00:55 PM PDT 24
Peak memory 195660 kb
Host smart-d8819580-a314-43cb-84cb-dbd194f3562d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781639848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1781639848
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.3606524417
Short name T228
Test name
Test status
Simulation time 1536015700780 ps
CPU time 505.47 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:25:26 PM PDT 24
Peak memory 191296 kb
Host smart-19810886-9717-4219-9304-4a54edd32098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606524417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3606524417
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.975307229
Short name T219
Test name
Test status
Simulation time 354105660423 ps
CPU time 535.6 seconds
Started Aug 12 05:16:40 PM PDT 24
Finished Aug 12 05:25:36 PM PDT 24
Peak memory 183120 kb
Host smart-9897a83c-5491-493f-8c49-346436a4772c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975307229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.975307229
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_random.1023390998
Short name T24
Test name
Test status
Simulation time 845265468507 ps
CPU time 319.07 seconds
Started Aug 12 05:16:36 PM PDT 24
Finished Aug 12 05:21:55 PM PDT 24
Peak memory 191344 kb
Host smart-89076071-ea76-425f-bdef-1202f73e5132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023390998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1023390998
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.568662432
Short name T125
Test name
Test status
Simulation time 659461714203 ps
CPU time 525.43 seconds
Started Aug 12 05:16:49 PM PDT 24
Finished Aug 12 05:25:35 PM PDT 24
Peak memory 191352 kb
Host smart-f523a7be-a5b2-483e-89b7-c4ee7db9e742
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568662432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.568662432
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1041286621
Short name T326
Test name
Test status
Simulation time 270293692855 ps
CPU time 676.35 seconds
Started Aug 12 05:16:57 PM PDT 24
Finished Aug 12 05:28:13 PM PDT 24
Peak memory 191236 kb
Host smart-1e799b66-67de-48a0-b1bc-1be9aeabe9a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041286621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1041286621
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.371813344
Short name T203
Test name
Test status
Simulation time 342347443478 ps
CPU time 549.43 seconds
Started Aug 12 05:16:56 PM PDT 24
Finished Aug 12 05:26:06 PM PDT 24
Peak memory 191348 kb
Host smart-9afcd2e1-caf1-42d5-975a-6c10e43a0542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371813344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.371813344
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.3084635068
Short name T208
Test name
Test status
Simulation time 70836619950 ps
CPU time 1255.09 seconds
Started Aug 12 05:17:05 PM PDT 24
Finished Aug 12 05:38:01 PM PDT 24
Peak memory 183180 kb
Host smart-94080b8d-f244-44aa-904b-e655569edd9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084635068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3084635068
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random.1116050571
Short name T152
Test name
Test status
Simulation time 122632928239 ps
CPU time 201.29 seconds
Started Aug 12 05:16:37 PM PDT 24
Finished Aug 12 05:19:58 PM PDT 24
Peak memory 191264 kb
Host smart-2860f52a-16ee-4b15-a286-d4ccc64f7ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116050571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1116050571
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random.2448094136
Short name T142
Test name
Test status
Simulation time 676317278217 ps
CPU time 370.02 seconds
Started Aug 12 05:16:48 PM PDT 24
Finished Aug 12 05:22:58 PM PDT 24
Peak memory 191292 kb
Host smart-698c364d-94df-41cf-83ee-56ca21058207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448094136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2448094136
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random.4054362259
Short name T177
Test name
Test status
Simulation time 243124224918 ps
CPU time 965.19 seconds
Started Aug 12 05:16:41 PM PDT 24
Finished Aug 12 05:32:47 PM PDT 24
Peak memory 191372 kb
Host smart-f0840e2b-f006-4dd1-8731-179815aee3f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054362259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4054362259
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1576804874
Short name T227
Test name
Test status
Simulation time 440054700716 ps
CPU time 353.89 seconds
Started Aug 12 05:16:37 PM PDT 24
Finished Aug 12 05:22:31 PM PDT 24
Peak memory 191284 kb
Host smart-726a4074-edfc-4f39-985b-3a37e261b4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576804874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1576804874
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/75.rv_timer_random.2800635367
Short name T62
Test name
Test status
Simulation time 194048189112 ps
CPU time 411.64 seconds
Started Aug 12 05:16:38 PM PDT 24
Finished Aug 12 05:23:29 PM PDT 24
Peak memory 192628 kb
Host smart-f6d78c36-bd51-4fdc-a4c4-ca2a3d1d0611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800635367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2800635367
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.3405524652
Short name T241
Test name
Test status
Simulation time 144294164265 ps
CPU time 226.73 seconds
Started Aug 12 05:16:16 PM PDT 24
Finished Aug 12 05:20:03 PM PDT 24
Peak memory 191296 kb
Host smart-39af7091-121b-45d9-baf6-3d5216684d78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405524652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3405524652
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.324172922
Short name T195
Test name
Test status
Simulation time 259859602936 ps
CPU time 296.66 seconds
Started Aug 12 05:16:56 PM PDT 24
Finished Aug 12 05:21:53 PM PDT 24
Peak memory 191344 kb
Host smart-c27584a4-31d3-4f22-9597-2a75fb5e7f9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324172922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.324172922
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2959599962
Short name T243
Test name
Test status
Simulation time 115464885867 ps
CPU time 96.61 seconds
Started Aug 12 05:17:02 PM PDT 24
Finished Aug 12 05:18:39 PM PDT 24
Peak memory 191204 kb
Host smart-2fd3f262-9235-4e7e-870b-2ed32de8a394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959599962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2959599962
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1665239240
Short name T303
Test name
Test status
Simulation time 126177609210 ps
CPU time 72.93 seconds
Started Aug 12 05:17:01 PM PDT 24
Finished Aug 12 05:18:14 PM PDT 24
Peak memory 193348 kb
Host smart-af3131ba-02d6-4cc6-93bf-df6dd9dd6fa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665239240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1665239240
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.93386025
Short name T7
Test name
Test status
Simulation time 115829246806 ps
CPU time 3017.87 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 06:07:21 PM PDT 24
Peak memory 191260 kb
Host smart-c57d3d88-b48d-4d0e-90af-346839d78abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93386025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.93386025
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.4055001366
Short name T221
Test name
Test status
Simulation time 178298545797 ps
CPU time 503.24 seconds
Started Aug 12 05:16:55 PM PDT 24
Finished Aug 12 05:25:18 PM PDT 24
Peak memory 191388 kb
Host smart-a35d555c-8fec-427b-ade1-811179e5428b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055001366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.4055001366
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2469260098
Short name T6
Test name
Test status
Simulation time 86030628978 ps
CPU time 128.43 seconds
Started Aug 12 05:17:04 PM PDT 24
Finished Aug 12 05:19:12 PM PDT 24
Peak memory 191320 kb
Host smart-31a5024f-bcd1-40a2-94f9-fce69c386051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469260098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2469260098
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2792439099
Short name T46
Test name
Test status
Simulation time 319567963320 ps
CPU time 498.17 seconds
Started Aug 12 05:16:44 PM PDT 24
Finished Aug 12 05:25:02 PM PDT 24
Peak memory 191184 kb
Host smart-620c0b00-18bd-4bf8-a728-2a7a8f5e9ba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792439099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2792439099
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1240212238
Short name T81
Test name
Test status
Simulation time 25710110 ps
CPU time 0.72 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 193796 kb
Host smart-bf98b0f2-9b03-45bc-ab75-3ae81bde713a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240212238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1240212238
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1300643366
Short name T74
Test name
Test status
Simulation time 14438696 ps
CPU time 0.63 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 183220 kb
Host smart-babba715-935c-449c-bf90-8e87a2e9636b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300643366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1300643366
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4145007636
Short name T86
Test name
Test status
Simulation time 694300576 ps
CPU time 1.44 seconds
Started Aug 12 05:15:46 PM PDT 24
Finished Aug 12 05:15:48 PM PDT 24
Peak memory 195912 kb
Host smart-7219972a-cdfc-41ef-b47e-46da81ce9792
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145007636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.4145007636
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random.758144332
Short name T234
Test name
Test status
Simulation time 121939868011 ps
CPU time 2018.42 seconds
Started Aug 12 05:16:15 PM PDT 24
Finished Aug 12 05:49:54 PM PDT 24
Peak memory 191292 kb
Host smart-d8052ae2-83c7-477b-a0c8-ada0ce187611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758144332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.758144332
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2299298176
Short name T103
Test name
Test status
Simulation time 96317506732 ps
CPU time 1411.66 seconds
Started Aug 12 05:16:47 PM PDT 24
Finished Aug 12 05:40:19 PM PDT 24
Peak memory 195176 kb
Host smart-6a61a2b3-be17-4b22-ae56-ba264d106c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299298176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2299298176
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1582459772
Short name T102
Test name
Test status
Simulation time 202977586257 ps
CPU time 704.46 seconds
Started Aug 12 05:16:41 PM PDT 24
Finished Aug 12 05:28:26 PM PDT 24
Peak memory 191324 kb
Host smart-e2e99b81-96d4-4743-9464-6e74b2c49d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582459772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1582459772
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.3219769601
Short name T344
Test name
Test status
Simulation time 4362055726 ps
CPU time 32.11 seconds
Started Aug 12 05:16:10 PM PDT 24
Finished Aug 12 05:16:42 PM PDT 24
Peak memory 183136 kb
Host smart-ca1743e0-76f6-4197-9b96-227aa2adae35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219769601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3219769601
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1110089986
Short name T96
Test name
Test status
Simulation time 47616008127 ps
CPU time 81.7 seconds
Started Aug 12 05:16:59 PM PDT 24
Finished Aug 12 05:18:21 PM PDT 24
Peak memory 183144 kb
Host smart-f58d5ead-72c9-4c9e-be34-b437a76cd0fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110089986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1110089986
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.722645492
Short name T22
Test name
Test status
Simulation time 183138916684 ps
CPU time 352.48 seconds
Started Aug 12 05:16:52 PM PDT 24
Finished Aug 12 05:22:44 PM PDT 24
Peak memory 191356 kb
Host smart-6c1b255b-e7a9-46b5-8221-df52652e8068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722645492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.722645492
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.539682007
Short name T92
Test name
Test status
Simulation time 2963031936330 ps
CPU time 1117.29 seconds
Started Aug 12 05:17:05 PM PDT 24
Finished Aug 12 05:35:42 PM PDT 24
Peak memory 191244 kb
Host smart-e5ee86ee-d85d-4e90-ae00-e1f3f61d8286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539682007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.539682007
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2075311773
Short name T310
Test name
Test status
Simulation time 360550482611 ps
CPU time 173.9 seconds
Started Aug 12 05:16:55 PM PDT 24
Finished Aug 12 05:19:49 PM PDT 24
Peak memory 195016 kb
Host smart-1ba5b191-6bae-4226-8c1f-74db6259b1ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075311773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2075311773
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2161338540
Short name T223
Test name
Test status
Simulation time 494945164608 ps
CPU time 317.15 seconds
Started Aug 12 05:16:59 PM PDT 24
Finished Aug 12 05:22:17 PM PDT 24
Peak memory 191304 kb
Host smart-25742b76-3be7-4c06-a3bc-ea264afcc727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161338540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2161338540
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3373611450
Short name T164
Test name
Test status
Simulation time 401278740025 ps
CPU time 561.09 seconds
Started Aug 12 05:17:04 PM PDT 24
Finished Aug 12 05:26:25 PM PDT 24
Peak memory 191320 kb
Host smart-e6eb8d89-1439-486d-90c5-a48f281a4571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373611450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3373611450
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.805343047
Short name T216
Test name
Test status
Simulation time 565382012856 ps
CPU time 334.44 seconds
Started Aug 12 05:16:15 PM PDT 24
Finished Aug 12 05:21:50 PM PDT 24
Peak memory 191344 kb
Host smart-a4c1c5b7-613b-4b91-9519-66d1b7f8163b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805343047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.805343047
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3600390606
Short name T121
Test name
Test status
Simulation time 228002678515 ps
CPU time 916.1 seconds
Started Aug 12 05:16:59 PM PDT 24
Finished Aug 12 05:32:15 PM PDT 24
Peak memory 191284 kb
Host smart-355c6e82-9afe-4c94-9a5d-3f1a7a75ad64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600390606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3600390606
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.165186037
Short name T318
Test name
Test status
Simulation time 9690924253 ps
CPU time 27.4 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 05:16:46 PM PDT 24
Peak memory 183072 kb
Host smart-de2e6131-9133-4fa9-b739-5e8acc2b648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165186037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.165186037
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/194.rv_timer_random.1549526461
Short name T146
Test name
Test status
Simulation time 245126523660 ps
CPU time 597.84 seconds
Started Aug 12 05:17:05 PM PDT 24
Finished Aug 12 05:27:03 PM PDT 24
Peak memory 191316 kb
Host smart-280c9fa3-b19a-4932-9a0e-32858ba6aa1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549526461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1549526461
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2508205797
Short name T200
Test name
Test status
Simulation time 102317055643 ps
CPU time 156.23 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 05:19:39 PM PDT 24
Peak memory 191044 kb
Host smart-a3198110-0de3-4fec-a5fa-f1cfb5721d64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508205797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2508205797
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1310704843
Short name T158
Test name
Test status
Simulation time 323747421365 ps
CPU time 140.23 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:18:32 PM PDT 24
Peak memory 183180 kb
Host smart-9120a470-3386-45e8-8a16-3c6c77220dd3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310704843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1310704843
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3347121893
Short name T285
Test name
Test status
Simulation time 497654020674 ps
CPU time 1611.39 seconds
Started Aug 12 05:16:20 PM PDT 24
Finished Aug 12 05:43:12 PM PDT 24
Peak memory 191248 kb
Host smart-edba1d6f-df55-4a6f-bd4c-6cf2b3b74465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347121893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3347121893
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/53.rv_timer_random.1221097397
Short name T196
Test name
Test status
Simulation time 143544130986 ps
CPU time 1579.58 seconds
Started Aug 12 05:16:45 PM PDT 24
Finished Aug 12 05:43:05 PM PDT 24
Peak memory 191352 kb
Host smart-de9537d1-f501-4d4d-b43f-2dcd72a1324a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221097397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1221097397
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1014470465
Short name T110
Test name
Test status
Simulation time 1578144542832 ps
CPU time 776.7 seconds
Started Aug 12 05:16:11 PM PDT 24
Finished Aug 12 05:29:08 PM PDT 24
Peak memory 183152 kb
Host smart-b57173f9-99bd-4b37-b04a-85294c5ef10c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014470465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1014470465
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2111164656
Short name T155
Test name
Test status
Simulation time 964568938724 ps
CPU time 307.52 seconds
Started Aug 12 05:16:08 PM PDT 24
Finished Aug 12 05:21:16 PM PDT 24
Peak memory 183132 kb
Host smart-0ee139dd-7366-4433-b686-66199738b570
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111164656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2111164656
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/102.rv_timer_random.1758441657
Short name T204
Test name
Test status
Simulation time 109510116649 ps
CPU time 349.91 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:22:50 PM PDT 24
Peak memory 191360 kb
Host smart-4d0dfa1e-e9de-408c-8047-d3352c2c6898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758441657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1758441657
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.4060547175
Short name T232
Test name
Test status
Simulation time 80311092287 ps
CPU time 305.8 seconds
Started Aug 12 05:16:45 PM PDT 24
Finished Aug 12 05:21:51 PM PDT 24
Peak memory 191340 kb
Host smart-c587a28a-a798-4a10-b0a1-8c8236433aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060547175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.4060547175
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2069540810
Short name T242
Test name
Test status
Simulation time 119995350585 ps
CPU time 165.68 seconds
Started Aug 12 05:16:57 PM PDT 24
Finished Aug 12 05:19:43 PM PDT 24
Peak memory 191356 kb
Host smart-0b78e366-ff80-413d-aa37-0ced2afd0d9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069540810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2069540810
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2574928886
Short name T123
Test name
Test status
Simulation time 762405458616 ps
CPU time 558.13 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:26:19 PM PDT 24
Peak memory 191380 kb
Host smart-0244fbe9-5722-422a-afaa-6c7556079bb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574928886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2574928886
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.1443860505
Short name T246
Test name
Test status
Simulation time 95245452567 ps
CPU time 483.18 seconds
Started Aug 12 05:16:50 PM PDT 24
Finished Aug 12 05:24:54 PM PDT 24
Peak memory 191312 kb
Host smart-d8927b0d-5b57-45ce-b57e-12bf109ebd4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443860505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1443860505
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.181874258
Short name T145
Test name
Test status
Simulation time 512782428167 ps
CPU time 1098.32 seconds
Started Aug 12 05:16:48 PM PDT 24
Finished Aug 12 05:35:07 PM PDT 24
Peak memory 193896 kb
Host smart-b8a0984e-9635-4364-9d0c-7384e4888aa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181874258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.181874258
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1519085569
Short name T291
Test name
Test status
Simulation time 422457256665 ps
CPU time 438.11 seconds
Started Aug 12 05:16:51 PM PDT 24
Finished Aug 12 05:24:09 PM PDT 24
Peak memory 191384 kb
Host smart-3f72d025-8889-4557-8693-f52c88e74541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519085569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1519085569
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.661372605
Short name T134
Test name
Test status
Simulation time 525787100393 ps
CPU time 230.75 seconds
Started Aug 12 05:16:14 PM PDT 24
Finished Aug 12 05:20:05 PM PDT 24
Peak memory 183152 kb
Host smart-2bb3eb34-e10d-4828-ba97-9157df109f6f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661372605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.661372605
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3894534673
Short name T193
Test name
Test status
Simulation time 292936057152 ps
CPU time 163.43 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:18:56 PM PDT 24
Peak memory 183124 kb
Host smart-b5549582-1918-4bc5-8715-02973c465290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894534673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3894534673
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/179.rv_timer_random.3025073524
Short name T61
Test name
Test status
Simulation time 84264647451 ps
CPU time 160.24 seconds
Started Aug 12 05:17:06 PM PDT 24
Finished Aug 12 05:19:46 PM PDT 24
Peak memory 191280 kb
Host smart-1d424b1b-48d9-4732-9e10-310d416fb8d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025073524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3025073524
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2669343308
Short name T274
Test name
Test status
Simulation time 176562350443 ps
CPU time 142.62 seconds
Started Aug 12 05:17:01 PM PDT 24
Finished Aug 12 05:19:23 PM PDT 24
Peak memory 191480 kb
Host smart-47138e7a-a1a3-4121-8e5c-63b5567d6363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669343308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2669343308
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random.2327015764
Short name T115
Test name
Test status
Simulation time 265480964651 ps
CPU time 494.49 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:24:27 PM PDT 24
Peak memory 191404 kb
Host smart-f91032ab-a045-4072-a139-7703053acebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327015764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2327015764
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.4230122843
Short name T128
Test name
Test status
Simulation time 496982752201 ps
CPU time 1779.83 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:45:52 PM PDT 24
Peak memory 191324 kb
Host smart-7e705035-8e8b-429f-b1e0-e1c38a7e1bab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230122843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.4230122843
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.518303830
Short name T278
Test name
Test status
Simulation time 320995015831 ps
CPU time 188.62 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:19:21 PM PDT 24
Peak memory 183112 kb
Host smart-b73768bd-037c-4303-8e51-501b9ee65d08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518303830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.518303830
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_random.3859160678
Short name T277
Test name
Test status
Simulation time 46652196003 ps
CPU time 98.57 seconds
Started Aug 12 05:16:22 PM PDT 24
Finished Aug 12 05:18:00 PM PDT 24
Peak memory 191332 kb
Host smart-b8d117cc-5411-4ed4-af37-099146bbacd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859160678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3859160678
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.289441809
Short name T205
Test name
Test status
Simulation time 288329264341 ps
CPU time 229.02 seconds
Started Aug 12 05:16:36 PM PDT 24
Finished Aug 12 05:20:25 PM PDT 24
Peak memory 191184 kb
Host smart-db00d9bb-e7c9-4ae4-83f5-271f8c74cc0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289441809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.289441809
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.1984959169
Short name T174
Test name
Test status
Simulation time 589879083542 ps
CPU time 480.72 seconds
Started Aug 12 05:16:33 PM PDT 24
Finished Aug 12 05:24:34 PM PDT 24
Peak memory 190504 kb
Host smart-16a676df-8753-4a2c-9a3b-49ff14ee8441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984959169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1984959169
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random.3914366382
Short name T349
Test name
Test status
Simulation time 58345901140 ps
CPU time 1366.46 seconds
Started Aug 12 05:16:27 PM PDT 24
Finished Aug 12 05:39:14 PM PDT 24
Peak memory 191184 kb
Host smart-f7be5dd9-67da-4ba4-ada1-0430f6e7b201
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914366382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3914366382
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3570231324
Short name T254
Test name
Test status
Simulation time 49520904677 ps
CPU time 40.14 seconds
Started Aug 12 05:16:24 PM PDT 24
Finished Aug 12 05:17:04 PM PDT 24
Peak memory 182788 kb
Host smart-ca3d2440-a214-441f-9f2f-bcfd62e634e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570231324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3570231324
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.230163914
Short name T314
Test name
Test status
Simulation time 118483009846 ps
CPU time 171.83 seconds
Started Aug 12 05:16:29 PM PDT 24
Finished Aug 12 05:19:22 PM PDT 24
Peak memory 182992 kb
Host smart-6d450ad2-9cf8-4e8c-8a4a-087e2bf9405a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230163914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.230163914
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.808878083
Short name T309
Test name
Test status
Simulation time 1096393536004 ps
CPU time 609.15 seconds
Started Aug 12 05:16:20 PM PDT 24
Finished Aug 12 05:26:29 PM PDT 24
Peak memory 183096 kb
Host smart-236c76be-0575-431c-8c25-73be552bd6a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808878083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.808878083
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2183865826
Short name T165
Test name
Test status
Simulation time 635843822179 ps
CPU time 389.14 seconds
Started Aug 12 05:16:36 PM PDT 24
Finished Aug 12 05:23:05 PM PDT 24
Peak memory 191316 kb
Host smart-33d61d4f-2fe1-4b75-baaf-c1ffdb75d7e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183865826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2183865826
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_random.111344997
Short name T334
Test name
Test status
Simulation time 940475714891 ps
CPU time 214.03 seconds
Started Aug 12 05:16:11 PM PDT 24
Finished Aug 12 05:19:45 PM PDT 24
Peak memory 183068 kb
Host smart-c50defe8-8a46-4861-b50c-85f482381646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111344997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.111344997
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.3062736723
Short name T302
Test name
Test status
Simulation time 365578879477 ps
CPU time 431.43 seconds
Started Aug 12 05:16:50 PM PDT 24
Finished Aug 12 05:24:02 PM PDT 24
Peak memory 191272 kb
Host smart-db91795a-3597-426f-9c4c-65110f12637d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062736723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3062736723
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.963981352
Short name T63
Test name
Test status
Simulation time 44539338 ps
CPU time 0.71 seconds
Started Aug 12 05:15:38 PM PDT 24
Finished Aug 12 05:15:39 PM PDT 24
Peak memory 192780 kb
Host smart-2f48d2e9-d082-49b4-830f-55bbd67b7e52
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963981352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.963981352
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2483777725
Short name T518
Test name
Test status
Simulation time 171268635 ps
CPU time 3.38 seconds
Started Aug 12 05:15:44 PM PDT 24
Finished Aug 12 05:15:48 PM PDT 24
Peak memory 191576 kb
Host smart-d54f93af-d2fa-4824-ac5c-86759a0ca67b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483777725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2483777725
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3506867782
Short name T84
Test name
Test status
Simulation time 13371531 ps
CPU time 0.53 seconds
Started Aug 12 05:15:57 PM PDT 24
Finished Aug 12 05:15:57 PM PDT 24
Peak memory 182812 kb
Host smart-31210125-448c-4c1f-83bb-dab0146ae46a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506867782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3506867782
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3400223621
Short name T544
Test name
Test status
Simulation time 32404112 ps
CPU time 0.86 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 196792 kb
Host smart-c328b06b-da1f-4ce7-96c9-b02662c3f15e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400223621 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3400223621
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2241146237
Short name T56
Test name
Test status
Simulation time 26088500 ps
CPU time 0.55 seconds
Started Aug 12 05:15:28 PM PDT 24
Finished Aug 12 05:15:28 PM PDT 24
Peak memory 183140 kb
Host smart-85c4e7c7-2e78-4b8d-bdff-074e8986a56a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241146237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2241146237
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.445681114
Short name T459
Test name
Test status
Simulation time 34468996 ps
CPU time 0.53 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:15:45 PM PDT 24
Peak memory 182760 kb
Host smart-37116033-20af-44cd-9ef2-4f2e2ee0c7db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445681114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.445681114
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2124340044
Short name T473
Test name
Test status
Simulation time 59183052 ps
CPU time 2.19 seconds
Started Aug 12 05:15:44 PM PDT 24
Finished Aug 12 05:15:47 PM PDT 24
Peak memory 197944 kb
Host smart-72666a15-25bf-45af-a27d-d77593b51312
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124340044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2124340044
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3701931225
Short name T68
Test name
Test status
Simulation time 88662273 ps
CPU time 0.7 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:15:45 PM PDT 24
Peak memory 183276 kb
Host smart-45945adc-7c8c-454c-8ba6-8c5e78d84029
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701931225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3701931225
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.4050963869
Short name T462
Test name
Test status
Simulation time 151791253 ps
CPU time 1.56 seconds
Started Aug 12 05:15:49 PM PDT 24
Finished Aug 12 05:15:50 PM PDT 24
Peak memory 183492 kb
Host smart-b2c538cb-10f4-45be-a916-d99878269597
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050963869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.4050963869
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2531811603
Short name T469
Test name
Test status
Simulation time 30810614 ps
CPU time 0.74 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 195832 kb
Host smart-04a49dec-9c28-41af-bbc5-fe53aa59d7ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531811603 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2531811603
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3882995627
Short name T76
Test name
Test status
Simulation time 186895542 ps
CPU time 0.55 seconds
Started Aug 12 05:16:01 PM PDT 24
Finished Aug 12 05:16:01 PM PDT 24
Peak memory 182960 kb
Host smart-ff8c9706-481f-4d0b-874a-e97efc8e41e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882995627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3882995627
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1351358894
Short name T508
Test name
Test status
Simulation time 12564921 ps
CPU time 0.57 seconds
Started Aug 12 05:16:00 PM PDT 24
Finished Aug 12 05:16:01 PM PDT 24
Peak memory 183200 kb
Host smart-1b8406a1-47ef-4210-8e78-d833edbd0a34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351358894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1351358894
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.584620095
Short name T574
Test name
Test status
Simulation time 39697372 ps
CPU time 0.63 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 192800 kb
Host smart-3af1dca0-e908-4d54-9b51-7f20a8998f14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584620095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.584620095
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3291225314
Short name T568
Test name
Test status
Simulation time 39108992 ps
CPU time 1.15 seconds
Started Aug 12 05:15:30 PM PDT 24
Finished Aug 12 05:15:31 PM PDT 24
Peak memory 197980 kb
Host smart-27592ceb-6051-408f-8489-1ef7dbcc3f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291225314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3291225314
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4186157414
Short name T31
Test name
Test status
Simulation time 111784375 ps
CPU time 1.13 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 183776 kb
Host smart-6a9727d1-3124-4791-9c89-2bc34634e38f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186157414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.4186157414
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.98854339
Short name T33
Test name
Test status
Simulation time 192152172 ps
CPU time 0.97 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 197480 kb
Host smart-856e51d7-56aa-42c9-b00b-59d50f7f5fbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98854339 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.98854339
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.4107344863
Short name T550
Test name
Test status
Simulation time 11401123 ps
CPU time 0.54 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:46 PM PDT 24
Peak memory 183248 kb
Host smart-9aa0f5c1-0966-4eed-8e95-7e6929d645f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107344863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.4107344863
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.727986263
Short name T455
Test name
Test status
Simulation time 15823403 ps
CPU time 0.56 seconds
Started Aug 12 05:15:55 PM PDT 24
Finished Aug 12 05:15:56 PM PDT 24
Peak memory 183048 kb
Host smart-40967755-8b79-40f7-a576-9ba3e4ab6f95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727986263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.727986263
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2529568507
Short name T542
Test name
Test status
Simulation time 55976878 ps
CPU time 0.78 seconds
Started Aug 12 05:15:55 PM PDT 24
Finished Aug 12 05:15:56 PM PDT 24
Peak memory 193764 kb
Host smart-46ea80c4-0902-4a46-93b3-fd5a92f62980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529568507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2529568507
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3304716444
Short name T571
Test name
Test status
Simulation time 666362452 ps
CPU time 3.09 seconds
Started Aug 12 05:16:02 PM PDT 24
Finished Aug 12 05:16:05 PM PDT 24
Peak memory 197924 kb
Host smart-8d74e842-36d4-41dd-898e-60c35d8647ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304716444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3304716444
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.866715119
Short name T565
Test name
Test status
Simulation time 75057072 ps
CPU time 1.11 seconds
Started Aug 12 05:15:40 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 195268 kb
Host smart-9d6d10e7-0a95-4774-a37a-b7ca389e382c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866715119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.866715119
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3362263903
Short name T500
Test name
Test status
Simulation time 89505059 ps
CPU time 0.81 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:47 PM PDT 24
Peak memory 195012 kb
Host smart-4086dff5-0f64-4f68-af1e-e1867214fbc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362263903 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3362263903
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4098781064
Short name T495
Test name
Test status
Simulation time 30393564 ps
CPU time 0.53 seconds
Started Aug 12 05:15:45 PM PDT 24
Finished Aug 12 05:15:46 PM PDT 24
Peak memory 182988 kb
Host smart-e32a755c-c8d5-413e-9d20-20ea33dd49e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098781064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.4098781064
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2535621426
Short name T482
Test name
Test status
Simulation time 13828702 ps
CPU time 0.54 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 182616 kb
Host smart-310ff21e-d55c-4053-a1eb-1b34eddff4b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535621426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2535621426
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3714560395
Short name T70
Test name
Test status
Simulation time 62932697 ps
CPU time 0.63 seconds
Started Aug 12 05:16:01 PM PDT 24
Finished Aug 12 05:16:02 PM PDT 24
Peak memory 192232 kb
Host smart-84f7cd41-c2c1-4ebc-b64e-e37f45dad5a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714560395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3714560395
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1013943082
Short name T457
Test name
Test status
Simulation time 62410242 ps
CPU time 1.61 seconds
Started Aug 12 05:15:44 PM PDT 24
Finished Aug 12 05:15:46 PM PDT 24
Peak memory 197988 kb
Host smart-8e4b15da-cd3a-49f7-ab0e-2dc0d3b8b813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013943082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1013943082
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1953984210
Short name T502
Test name
Test status
Simulation time 18406893 ps
CPU time 0.64 seconds
Started Aug 12 05:15:53 PM PDT 24
Finished Aug 12 05:15:54 PM PDT 24
Peak memory 193932 kb
Host smart-30fb1c36-eaa0-498d-ba21-8ee774ee822e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953984210 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1953984210
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2539227793
Short name T580
Test name
Test status
Simulation time 17034174 ps
CPU time 0.57 seconds
Started Aug 12 05:15:55 PM PDT 24
Finished Aug 12 05:15:56 PM PDT 24
Peak memory 183304 kb
Host smart-7014ad00-5ef0-4f18-b015-699d11b11a64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539227793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2539227793
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3144566161
Short name T537
Test name
Test status
Simulation time 13252916 ps
CPU time 0.54 seconds
Started Aug 12 05:15:55 PM PDT 24
Finished Aug 12 05:15:55 PM PDT 24
Peak memory 183064 kb
Host smart-68e3d4a6-5c02-4b00-8a61-0c7f0dfc63a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144566161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3144566161
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.169145651
Short name T57
Test name
Test status
Simulation time 31298343 ps
CPU time 0.75 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 192500 kb
Host smart-0669f0b0-4c81-4345-bd48-306e6549c673
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169145651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.169145651
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.239086134
Short name T569
Test name
Test status
Simulation time 34397298 ps
CPU time 1.11 seconds
Started Aug 12 05:15:46 PM PDT 24
Finished Aug 12 05:15:48 PM PDT 24
Peak memory 197988 kb
Host smart-791611a8-67f1-479f-a0be-60e20f87c88e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239086134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.239086134
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2260089279
Short name T87
Test name
Test status
Simulation time 353396955 ps
CPU time 1.08 seconds
Started Aug 12 05:15:40 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 195548 kb
Host smart-ef6ed1dc-764e-40d8-a6fd-c25ae4ccb069
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260089279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2260089279
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4214953033
Short name T485
Test name
Test status
Simulation time 49555640 ps
CPU time 1.18 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 198068 kb
Host smart-b95a2a23-9e51-4307-95b0-e476e9b948f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214953033 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.4214953033
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3102630021
Short name T578
Test name
Test status
Simulation time 16111653 ps
CPU time 0.63 seconds
Started Aug 12 05:15:51 PM PDT 24
Finished Aug 12 05:15:52 PM PDT 24
Peak memory 183064 kb
Host smart-345cede4-c515-4bfd-8e43-043eb0e1a72c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102630021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3102630021
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3672442066
Short name T79
Test name
Test status
Simulation time 55411884 ps
CPU time 0.72 seconds
Started Aug 12 05:15:47 PM PDT 24
Finished Aug 12 05:15:48 PM PDT 24
Peak memory 193712 kb
Host smart-02dcf018-fa2c-40e6-863c-890d56eac2e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672442066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3672442066
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1884588843
Short name T484
Test name
Test status
Simulation time 67395928 ps
CPU time 1.48 seconds
Started Aug 12 05:15:40 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 197944 kb
Host smart-a26c59a1-b505-4ad5-aa0a-8638216d071c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884588843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1884588843
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.753270554
Short name T520
Test name
Test status
Simulation time 384305936 ps
CPU time 1.05 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 195376 kb
Host smart-35105167-7020-4731-a694-5d796c07db6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753270554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.753270554
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1832331669
Short name T554
Test name
Test status
Simulation time 106825724 ps
CPU time 0.85 seconds
Started Aug 12 05:15:51 PM PDT 24
Finished Aug 12 05:15:52 PM PDT 24
Peak memory 197468 kb
Host smart-78e648a8-06d5-450e-adb2-127ce52599ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832331669 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1832331669
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2416720972
Short name T539
Test name
Test status
Simulation time 41883490 ps
CPU time 0.57 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 183200 kb
Host smart-37524596-f019-41bc-81ed-5278f6c1398d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416720972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2416720972
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2007877758
Short name T488
Test name
Test status
Simulation time 20783779 ps
CPU time 0.53 seconds
Started Aug 12 05:15:50 PM PDT 24
Finished Aug 12 05:15:51 PM PDT 24
Peak memory 183016 kb
Host smart-e1c23605-9622-4d24-b795-ed9a78c5e226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007877758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2007877758
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2423076479
Short name T82
Test name
Test status
Simulation time 39740849 ps
CPU time 0.62 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 192640 kb
Host smart-fdcdc04f-8302-4b04-baad-cbc6ca5f399b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423076479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2423076479
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1893352441
Short name T582
Test name
Test status
Simulation time 53607678 ps
CPU time 2.69 seconds
Started Aug 12 05:15:48 PM PDT 24
Finished Aug 12 05:15:51 PM PDT 24
Peak memory 198032 kb
Host smart-51ba3229-225c-4c50-a94a-6dddf03a6ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893352441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1893352441
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4131493003
Short name T517
Test name
Test status
Simulation time 2861529940 ps
CPU time 2 seconds
Started Aug 12 05:15:40 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 196132 kb
Host smart-46ed4782-a7b7-4410-9585-3ab16d370eec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131493003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.4131493003
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.359159765
Short name T489
Test name
Test status
Simulation time 116151673 ps
CPU time 0.83 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 197096 kb
Host smart-fa9b270f-58aa-438e-9089-423ba0732641
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359159765 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.359159765
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3356704003
Short name T67
Test name
Test status
Simulation time 56087603 ps
CPU time 0.57 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 183160 kb
Host smart-70c69415-d942-419f-befe-1b77d998699a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356704003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3356704003
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2369737282
Short name T576
Test name
Test status
Simulation time 28999437 ps
CPU time 0.51 seconds
Started Aug 12 05:15:40 PM PDT 24
Finished Aug 12 05:15:41 PM PDT 24
Peak memory 182624 kb
Host smart-1c0c612c-0231-432c-a250-f5158a08d2c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369737282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2369737282
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.421483650
Short name T78
Test name
Test status
Simulation time 88744677 ps
CPU time 0.65 seconds
Started Aug 12 05:15:55 PM PDT 24
Finished Aug 12 05:15:56 PM PDT 24
Peak memory 192752 kb
Host smart-287dd160-53dc-4bf5-9866-2af4a5f7a1f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421483650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.421483650
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1708172721
Short name T557
Test name
Test status
Simulation time 150595854 ps
CPU time 1.76 seconds
Started Aug 12 05:15:52 PM PDT 24
Finished Aug 12 05:15:54 PM PDT 24
Peak memory 197996 kb
Host smart-483b3aa3-71e9-4144-ab9b-70a02e556a60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708172721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1708172721
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1126244240
Short name T514
Test name
Test status
Simulation time 424706854 ps
CPU time 1.42 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 196064 kb
Host smart-dfaaa054-477e-419e-9f9d-65487541459d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126244240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1126244240
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3421984525
Short name T570
Test name
Test status
Simulation time 232500989 ps
CPU time 1 seconds
Started Aug 12 05:16:07 PM PDT 24
Finished Aug 12 05:16:08 PM PDT 24
Peak memory 197744 kb
Host smart-98d8f03c-b056-45c6-b550-85119bc5047e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421984525 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3421984525
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1506754193
Short name T536
Test name
Test status
Simulation time 44231770 ps
CPU time 0.55 seconds
Started Aug 12 05:16:08 PM PDT 24
Finished Aug 12 05:16:08 PM PDT 24
Peak memory 183208 kb
Host smart-330a1cd4-3f04-49f0-8246-a9c5f5a13648
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506754193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1506754193
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3709925713
Short name T498
Test name
Test status
Simulation time 12324881 ps
CPU time 0.58 seconds
Started Aug 12 05:15:55 PM PDT 24
Finished Aug 12 05:15:56 PM PDT 24
Peak memory 182760 kb
Host smart-76f375de-cb52-4f90-a7b4-383019cd15b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709925713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3709925713
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2180135460
Short name T567
Test name
Test status
Simulation time 29276561 ps
CPU time 0.7 seconds
Started Aug 12 05:15:49 PM PDT 24
Finished Aug 12 05:15:50 PM PDT 24
Peak memory 192660 kb
Host smart-0c93e784-3c6c-4f07-8841-5590c88da6b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180135460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2180135460
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2674387364
Short name T553
Test name
Test status
Simulation time 157465887 ps
CPU time 2.75 seconds
Started Aug 12 05:15:59 PM PDT 24
Finished Aug 12 05:16:02 PM PDT 24
Peak memory 198016 kb
Host smart-272d8e48-cb89-4e47-818b-2cb5942ce6b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674387364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2674387364
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.660471819
Short name T88
Test name
Test status
Simulation time 312366097 ps
CPU time 1.13 seconds
Started Aug 12 05:16:05 PM PDT 24
Finished Aug 12 05:16:06 PM PDT 24
Peak memory 195588 kb
Host smart-b0157b91-9c38-405a-9d9d-b262e44226c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660471819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.660471819
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1309998283
Short name T512
Test name
Test status
Simulation time 27028701 ps
CPU time 0.87 seconds
Started Aug 12 05:16:10 PM PDT 24
Finished Aug 12 05:16:11 PM PDT 24
Peak memory 197488 kb
Host smart-ca4eb97b-78ac-4ea4-8384-79bdebf0a569
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309998283 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1309998283
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3862590995
Short name T480
Test name
Test status
Simulation time 22853695 ps
CPU time 0.56 seconds
Started Aug 12 05:16:03 PM PDT 24
Finished Aug 12 05:16:04 PM PDT 24
Peak memory 183300 kb
Host smart-86c313fe-9c89-43cb-a5b7-00ba86e8075b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862590995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3862590995
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1614560044
Short name T579
Test name
Test status
Simulation time 43494440 ps
CPU time 0.55 seconds
Started Aug 12 05:16:00 PM PDT 24
Finished Aug 12 05:16:00 PM PDT 24
Peak memory 182628 kb
Host smart-f7fd92c6-00ba-44f6-835d-c4fd68b23e1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614560044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1614560044
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1293951725
Short name T533
Test name
Test status
Simulation time 63006218 ps
CPU time 0.59 seconds
Started Aug 12 05:16:03 PM PDT 24
Finished Aug 12 05:16:03 PM PDT 24
Peak memory 192524 kb
Host smart-3d799704-39f5-4ec3-b607-03e17d2b6f2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293951725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1293951725
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1477021144
Short name T465
Test name
Test status
Simulation time 187165478 ps
CPU time 3.06 seconds
Started Aug 12 05:16:01 PM PDT 24
Finished Aug 12 05:16:04 PM PDT 24
Peak memory 197976 kb
Host smart-4bbc530f-8bd6-4d39-931b-b8c0e4135ecb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477021144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1477021144
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.136155590
Short name T525
Test name
Test status
Simulation time 388375435 ps
CPU time 1.33 seconds
Started Aug 12 05:16:15 PM PDT 24
Finished Aug 12 05:16:16 PM PDT 24
Peak memory 196128 kb
Host smart-b52ec1e7-3119-490e-af37-a8f2e01e3f6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136155590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.136155590
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2350892461
Short name T472
Test name
Test status
Simulation time 109727742 ps
CPU time 1.25 seconds
Started Aug 12 05:16:00 PM PDT 24
Finished Aug 12 05:16:02 PM PDT 24
Peak memory 198076 kb
Host smart-a2a8cbf0-b38d-439e-8660-b78135347b88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350892461 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2350892461
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1580894208
Short name T535
Test name
Test status
Simulation time 38646867 ps
CPU time 0.55 seconds
Started Aug 12 05:16:02 PM PDT 24
Finished Aug 12 05:16:03 PM PDT 24
Peak memory 183192 kb
Host smart-79715af3-c7ad-44eb-bd5c-7e9bce6807c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580894208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1580894208
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3231020207
Short name T456
Test name
Test status
Simulation time 18288645 ps
CPU time 0.52 seconds
Started Aug 12 05:16:05 PM PDT 24
Finished Aug 12 05:16:06 PM PDT 24
Peak memory 182756 kb
Host smart-26b629e9-6deb-4689-a4c2-1f0dc918ea90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231020207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3231020207
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1116364214
Short name T547
Test name
Test status
Simulation time 55200272 ps
CPU time 0.74 seconds
Started Aug 12 05:16:08 PM PDT 24
Finished Aug 12 05:16:08 PM PDT 24
Peak memory 191424 kb
Host smart-180a427c-14e9-426d-8089-e2ad869937a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116364214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1116364214
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1701968970
Short name T526
Test name
Test status
Simulation time 140679461 ps
CPU time 1.93 seconds
Started Aug 12 05:15:58 PM PDT 24
Finished Aug 12 05:16:00 PM PDT 24
Peak memory 197368 kb
Host smart-9b2e852a-604b-415a-b60b-0cc52ba4d719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701968970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1701968970
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.59860496
Short name T573
Test name
Test status
Simulation time 183594744 ps
CPU time 0.77 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 193940 kb
Host smart-4a8277b0-d5e0-47a6-94c1-15a1dae9d56e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59860496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_int
g_err.59860496
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2531370743
Short name T496
Test name
Test status
Simulation time 75306529 ps
CPU time 0.9 seconds
Started Aug 12 05:16:05 PM PDT 24
Finished Aug 12 05:16:06 PM PDT 24
Peak memory 197796 kb
Host smart-13b57eb9-aae6-49c6-bee9-256c685cf075
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531370743 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2531370743
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.916090303
Short name T71
Test name
Test status
Simulation time 14836869 ps
CPU time 0.58 seconds
Started Aug 12 05:16:00 PM PDT 24
Finished Aug 12 05:16:00 PM PDT 24
Peak memory 183200 kb
Host smart-2d2cb0b2-5b47-4bf9-9aaf-9949514ad131
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916090303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.916090303
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4063229775
Short name T461
Test name
Test status
Simulation time 12737479 ps
CPU time 0.63 seconds
Started Aug 12 05:16:01 PM PDT 24
Finished Aug 12 05:16:02 PM PDT 24
Peak memory 182660 kb
Host smart-5960e12a-3404-497c-aaeb-5c9e98c68afb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063229775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4063229775
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3500934247
Short name T69
Test name
Test status
Simulation time 121134596 ps
CPU time 0.72 seconds
Started Aug 12 05:16:05 PM PDT 24
Finished Aug 12 05:16:06 PM PDT 24
Peak memory 193668 kb
Host smart-7e559f38-4019-4ce0-a2a5-7af186eb1792
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500934247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3500934247
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3016815188
Short name T516
Test name
Test status
Simulation time 439082568 ps
CPU time 1.93 seconds
Started Aug 12 05:16:00 PM PDT 24
Finished Aug 12 05:16:02 PM PDT 24
Peak memory 198012 kb
Host smart-91b7de8f-1570-4db8-b1d6-52b3796e1e80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016815188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3016815188
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2184326095
Short name T555
Test name
Test status
Simulation time 84771036 ps
CPU time 1.09 seconds
Started Aug 12 05:16:00 PM PDT 24
Finished Aug 12 05:16:01 PM PDT 24
Peak memory 183736 kb
Host smart-2c13db45-16af-43e0-b374-81e0ed96bd2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184326095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2184326095
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2282968445
Short name T65
Test name
Test status
Simulation time 20115186 ps
CPU time 0.62 seconds
Started Aug 12 05:15:44 PM PDT 24
Finished Aug 12 05:15:45 PM PDT 24
Peak memory 192476 kb
Host smart-12902dd3-5455-4d99-b56a-70af8e455f76
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282968445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2282968445
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2780855566
Short name T73
Test name
Test status
Simulation time 168620366 ps
CPU time 3.26 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:45 PM PDT 24
Peak memory 194216 kb
Host smart-ee65931b-5804-4e24-b639-5d47357832ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780855566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2780855566
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3683156389
Short name T540
Test name
Test status
Simulation time 48201461 ps
CPU time 0.52 seconds
Started Aug 12 05:15:39 PM PDT 24
Finished Aug 12 05:15:40 PM PDT 24
Peak memory 182712 kb
Host smart-69ab635e-5f4b-4681-b9db-ff33df4f13ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683156389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3683156389
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.4073174190
Short name T575
Test name
Test status
Simulation time 31312362 ps
CPU time 1.25 seconds
Started Aug 12 05:15:46 PM PDT 24
Finished Aug 12 05:15:47 PM PDT 24
Peak memory 197932 kb
Host smart-52d06f67-cf2b-4a2e-88d4-12037a6b22fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073174190 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.4073174190
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1662371247
Short name T510
Test name
Test status
Simulation time 13540997 ps
CPU time 0.55 seconds
Started Aug 12 05:15:49 PM PDT 24
Finished Aug 12 05:15:50 PM PDT 24
Peak memory 183256 kb
Host smart-534957e9-bed7-4cb1-a189-d408c44e7e15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662371247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1662371247
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2381372461
Short name T463
Test name
Test status
Simulation time 70755407 ps
CPU time 0.55 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 183172 kb
Host smart-1a6e986f-e16d-4fbb-bc72-8aa97b7a81b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381372461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2381372461
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4287098145
Short name T563
Test name
Test status
Simulation time 98070074 ps
CPU time 0.68 seconds
Started Aug 12 05:15:36 PM PDT 24
Finished Aug 12 05:15:37 PM PDT 24
Peak memory 192252 kb
Host smart-0b0dbea8-73b9-4093-8f9e-d6e1d3ba5962
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287098145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.4287098145
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2815059328
Short name T541
Test name
Test status
Simulation time 281931011 ps
CPU time 1.24 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 197948 kb
Host smart-2d11259f-a08f-4c79-87ab-3488197d7ca6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815059328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2815059328
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2895781676
Short name T89
Test name
Test status
Simulation time 170620686 ps
CPU time 0.83 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 193112 kb
Host smart-7a0fa4a9-b17e-4fea-85c9-735796b78d28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895781676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2895781676
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1110501600
Short name T507
Test name
Test status
Simulation time 14254140 ps
CPU time 0.56 seconds
Started Aug 12 05:15:52 PM PDT 24
Finished Aug 12 05:15:53 PM PDT 24
Peak memory 183068 kb
Host smart-f1d04e74-916d-4796-aec1-9d94c5b43024
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110501600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1110501600
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3324354382
Short name T528
Test name
Test status
Simulation time 32283237 ps
CPU time 0.51 seconds
Started Aug 12 05:15:58 PM PDT 24
Finished Aug 12 05:15:58 PM PDT 24
Peak memory 182836 kb
Host smart-b0313a36-43c2-45ca-8ea1-32d8e3b9c2e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324354382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3324354382
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3974360307
Short name T460
Test name
Test status
Simulation time 178429680 ps
CPU time 0.53 seconds
Started Aug 12 05:16:08 PM PDT 24
Finished Aug 12 05:16:08 PM PDT 24
Peak memory 182504 kb
Host smart-a938be72-5ddb-4743-9f71-e5dcdf12a259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974360307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3974360307
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1991742677
Short name T490
Test name
Test status
Simulation time 13341322 ps
CPU time 0.54 seconds
Started Aug 12 05:15:57 PM PDT 24
Finished Aug 12 05:15:58 PM PDT 24
Peak memory 182532 kb
Host smart-9b0edbcc-960c-437c-b77f-f370ed9cecfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991742677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1991742677
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2573793152
Short name T453
Test name
Test status
Simulation time 21588084 ps
CPU time 0.58 seconds
Started Aug 12 05:16:02 PM PDT 24
Finished Aug 12 05:16:03 PM PDT 24
Peak memory 182632 kb
Host smart-91f31455-7b22-4ebc-b039-046472bbd1be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573793152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2573793152
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4001965540
Short name T471
Test name
Test status
Simulation time 16081365 ps
CPU time 0.57 seconds
Started Aug 12 05:15:53 PM PDT 24
Finished Aug 12 05:15:54 PM PDT 24
Peak memory 183128 kb
Host smart-cad4f161-3de6-43d6-8bd9-2d9c734af93c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001965540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4001965540
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3332437728
Short name T501
Test name
Test status
Simulation time 68977485 ps
CPU time 0.52 seconds
Started Aug 12 05:15:53 PM PDT 24
Finished Aug 12 05:15:54 PM PDT 24
Peak memory 183100 kb
Host smart-7109609c-08de-4205-91c0-b4be0fa6f420
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332437728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3332437728
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2172279049
Short name T581
Test name
Test status
Simulation time 19485113 ps
CPU time 0.56 seconds
Started Aug 12 05:16:08 PM PDT 24
Finished Aug 12 05:16:09 PM PDT 24
Peak memory 183120 kb
Host smart-4e631968-989c-4f5f-85d0-f5351d2d1aa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172279049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2172279049
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2937105693
Short name T532
Test name
Test status
Simulation time 15118263 ps
CPU time 0.55 seconds
Started Aug 12 05:16:08 PM PDT 24
Finished Aug 12 05:16:08 PM PDT 24
Peak memory 182796 kb
Host smart-0dffe829-52a0-4aaa-bb34-6f56ec4f48f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937105693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2937105693
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1226762718
Short name T543
Test name
Test status
Simulation time 19024907 ps
CPU time 0.53 seconds
Started Aug 12 05:16:06 PM PDT 24
Finished Aug 12 05:16:07 PM PDT 24
Peak memory 182780 kb
Host smart-218d5d6d-3b13-469f-9fc8-d55561252682
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226762718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1226762718
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3359071165
Short name T75
Test name
Test status
Simulation time 23468841 ps
CPU time 0.72 seconds
Started Aug 12 05:15:42 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 193020 kb
Host smart-1d96e255-ad70-41da-96d9-fe1a523ec86e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359071165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3359071165
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3632819506
Short name T534
Test name
Test status
Simulation time 171574963 ps
CPU time 1.45 seconds
Started Aug 12 05:15:46 PM PDT 24
Finished Aug 12 05:15:47 PM PDT 24
Peak memory 191568 kb
Host smart-5351cefe-18a3-4e67-b657-64c9a8a871fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632819506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3632819506
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4121193700
Short name T513
Test name
Test status
Simulation time 14329050 ps
CPU time 0.57 seconds
Started Aug 12 05:15:55 PM PDT 24
Finished Aug 12 05:15:55 PM PDT 24
Peak memory 182796 kb
Host smart-f1d49bcc-03f8-4885-8852-bf44127c1e43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121193700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4121193700
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1941417485
Short name T530
Test name
Test status
Simulation time 40456851 ps
CPU time 0.82 seconds
Started Aug 12 05:15:40 PM PDT 24
Finished Aug 12 05:15:41 PM PDT 24
Peak memory 197140 kb
Host smart-5a45df92-95e4-411b-9be3-934f19a2edc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941417485 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1941417485
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2377944861
Short name T523
Test name
Test status
Simulation time 42809603 ps
CPU time 0.57 seconds
Started Aug 12 05:15:50 PM PDT 24
Finished Aug 12 05:15:51 PM PDT 24
Peak memory 183264 kb
Host smart-eb8223da-c1b9-47c2-a76a-c846de9dcb9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377944861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2377944861
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1925741745
Short name T548
Test name
Test status
Simulation time 45928196 ps
CPU time 0.56 seconds
Started Aug 12 05:15:48 PM PDT 24
Finished Aug 12 05:15:49 PM PDT 24
Peak memory 183088 kb
Host smart-7a00c33f-5e92-4d87-8da4-1b9c85c4fd22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925741745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1925741745
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.940589681
Short name T556
Test name
Test status
Simulation time 42169568 ps
CPU time 0.85 seconds
Started Aug 12 05:15:37 PM PDT 24
Finished Aug 12 05:15:38 PM PDT 24
Peak memory 194136 kb
Host smart-e250918a-d9bc-4808-b00a-d081eb250bf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940589681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.940589681
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3763895661
Short name T466
Test name
Test status
Simulation time 131609983 ps
CPU time 1.69 seconds
Started Aug 12 05:15:35 PM PDT 24
Finished Aug 12 05:15:37 PM PDT 24
Peak memory 197968 kb
Host smart-d8bf5738-c500-4882-996f-3897e45fe29a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763895661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3763895661
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3197944931
Short name T519
Test name
Test status
Simulation time 106976889 ps
CPU time 1.32 seconds
Started Aug 12 05:15:49 PM PDT 24
Finished Aug 12 05:15:51 PM PDT 24
Peak memory 184088 kb
Host smart-477c1f92-cf47-4fcd-8243-d3bc13de8c25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197944931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3197944931
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2948579539
Short name T531
Test name
Test status
Simulation time 14652937 ps
CPU time 0.6 seconds
Started Aug 12 05:16:07 PM PDT 24
Finished Aug 12 05:16:07 PM PDT 24
Peak memory 183108 kb
Host smart-6eb180c7-ff72-46be-8d28-231b4cb9e46d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948579539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2948579539
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2664671669
Short name T529
Test name
Test status
Simulation time 47062790 ps
CPU time 0.56 seconds
Started Aug 12 05:15:56 PM PDT 24
Finished Aug 12 05:15:57 PM PDT 24
Peak memory 183156 kb
Host smart-5402efba-d071-4276-8c77-20394c00e355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664671669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2664671669
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1329712978
Short name T511
Test name
Test status
Simulation time 27230564 ps
CPU time 0.51 seconds
Started Aug 12 05:16:04 PM PDT 24
Finished Aug 12 05:16:05 PM PDT 24
Peak memory 182768 kb
Host smart-4bf8f2c2-ae90-45ca-a472-c8e4319307da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329712978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1329712978
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.110050633
Short name T504
Test name
Test status
Simulation time 39644250 ps
CPU time 0.58 seconds
Started Aug 12 05:15:57 PM PDT 24
Finished Aug 12 05:15:58 PM PDT 24
Peak memory 182816 kb
Host smart-8c20f6ea-0194-461c-86de-9a727e71955f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110050633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.110050633
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2003623066
Short name T476
Test name
Test status
Simulation time 48038538 ps
CPU time 0.56 seconds
Started Aug 12 05:15:55 PM PDT 24
Finished Aug 12 05:15:55 PM PDT 24
Peak memory 183144 kb
Host smart-a9ec5916-1d03-45aa-a508-28edda763b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003623066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2003623066
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3613957009
Short name T545
Test name
Test status
Simulation time 16389410 ps
CPU time 0.57 seconds
Started Aug 12 05:15:57 PM PDT 24
Finished Aug 12 05:15:57 PM PDT 24
Peak memory 182612 kb
Host smart-9758cf78-cac4-425d-b01b-b2b99084f922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613957009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3613957009
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1629882911
Short name T497
Test name
Test status
Simulation time 116253629 ps
CPU time 0.57 seconds
Started Aug 12 05:15:44 PM PDT 24
Finished Aug 12 05:15:45 PM PDT 24
Peak memory 183116 kb
Host smart-3cc77b5d-1e12-412a-843f-f8de64613eec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629882911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1629882911
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2911166849
Short name T538
Test name
Test status
Simulation time 48951684 ps
CPU time 0.52 seconds
Started Aug 12 05:15:53 PM PDT 24
Finished Aug 12 05:15:54 PM PDT 24
Peak memory 183164 kb
Host smart-79355966-860a-4635-91bf-eec7204d52e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911166849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2911166849
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2537903215
Short name T481
Test name
Test status
Simulation time 16439459 ps
CPU time 0.56 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 05:16:13 PM PDT 24
Peak memory 183100 kb
Host smart-85167652-6c43-4494-900e-64f9f9464194
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537903215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2537903215
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1257412602
Short name T458
Test name
Test status
Simulation time 42982881 ps
CPU time 0.53 seconds
Started Aug 12 05:16:02 PM PDT 24
Finished Aug 12 05:16:03 PM PDT 24
Peak memory 183064 kb
Host smart-72b200db-e66d-4505-8f6c-f80f3df3528c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257412602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1257412602
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1413475137
Short name T34
Test name
Test status
Simulation time 50954927 ps
CPU time 0.57 seconds
Started Aug 12 05:15:45 PM PDT 24
Finished Aug 12 05:15:46 PM PDT 24
Peak memory 183184 kb
Host smart-79d1ba80-1675-4c4b-b6be-3f833035d032
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413475137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1413475137
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1617364994
Short name T83
Test name
Test status
Simulation time 3915645504 ps
CPU time 3.69 seconds
Started Aug 12 05:15:39 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 193780 kb
Host smart-79becc9e-4c3f-4de6-9112-31fe2d10c5e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617364994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1617364994
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1821158511
Short name T499
Test name
Test status
Simulation time 18462503 ps
CPU time 0.59 seconds
Started Aug 12 05:15:57 PM PDT 24
Finished Aug 12 05:15:57 PM PDT 24
Peak memory 183180 kb
Host smart-45af1004-87ab-459b-a6a1-d7fb417a7181
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821158511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1821158511
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4237545116
Short name T527
Test name
Test status
Simulation time 32511243 ps
CPU time 0.83 seconds
Started Aug 12 05:16:03 PM PDT 24
Finished Aug 12 05:16:04 PM PDT 24
Peak memory 196860 kb
Host smart-e1d5cc13-19cd-4ba9-ae42-eac6b4666a1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237545116 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.4237545116
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2681538996
Short name T35
Test name
Test status
Simulation time 49088409 ps
CPU time 0.56 seconds
Started Aug 12 05:15:54 PM PDT 24
Finished Aug 12 05:15:55 PM PDT 24
Peak memory 183180 kb
Host smart-a62277e3-bde3-4286-81cc-c735392e4f01
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681538996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2681538996
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2005511575
Short name T561
Test name
Test status
Simulation time 41907117 ps
CPU time 0.56 seconds
Started Aug 12 05:15:50 PM PDT 24
Finished Aug 12 05:15:51 PM PDT 24
Peak memory 183132 kb
Host smart-50882e1e-a604-4b7a-9ad2-2b91478fe3df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005511575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2005511575
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1579820764
Short name T564
Test name
Test status
Simulation time 22685144 ps
CPU time 0.68 seconds
Started Aug 12 05:15:46 PM PDT 24
Finished Aug 12 05:15:47 PM PDT 24
Peak memory 192608 kb
Host smart-814ff435-ffab-4696-a179-9bfee091dd24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579820764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1579820764
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2270144111
Short name T493
Test name
Test status
Simulation time 49145026 ps
CPU time 1.22 seconds
Started Aug 12 05:15:44 PM PDT 24
Finished Aug 12 05:15:46 PM PDT 24
Peak memory 197112 kb
Host smart-27ecea55-68ee-4ef8-a0c7-7a5af17007bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270144111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2270144111
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3300444228
Short name T483
Test name
Test status
Simulation time 86848195 ps
CPU time 0.84 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:42 PM PDT 24
Peak memory 194024 kb
Host smart-77a96bd8-3304-49c5-a380-6722916d43d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300444228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3300444228
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.8938274
Short name T558
Test name
Test status
Simulation time 58693759 ps
CPU time 0.51 seconds
Started Aug 12 05:16:06 PM PDT 24
Finished Aug 12 05:16:07 PM PDT 24
Peak memory 182808 kb
Host smart-17512e2e-ee76-4560-97d5-289aa4b031e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8938274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.8938274
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.474727873
Short name T475
Test name
Test status
Simulation time 14437043 ps
CPU time 0.52 seconds
Started Aug 12 05:16:16 PM PDT 24
Finished Aug 12 05:16:17 PM PDT 24
Peak memory 182592 kb
Host smart-a2185c88-b7b9-4f8b-957c-45ba258abce0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474727873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.474727873
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.725141380
Short name T509
Test name
Test status
Simulation time 41093341 ps
CPU time 0.51 seconds
Started Aug 12 05:16:10 PM PDT 24
Finished Aug 12 05:16:10 PM PDT 24
Peak memory 182528 kb
Host smart-13307229-4f80-4bc5-afca-4b873850fad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725141380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.725141380
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2640721547
Short name T562
Test name
Test status
Simulation time 13488545 ps
CPU time 0.54 seconds
Started Aug 12 05:16:09 PM PDT 24
Finished Aug 12 05:16:10 PM PDT 24
Peak memory 182560 kb
Host smart-2e2f2119-3681-4243-8abb-3e568ac136f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640721547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2640721547
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1005126231
Short name T492
Test name
Test status
Simulation time 109926470 ps
CPU time 0.54 seconds
Started Aug 12 05:16:11 PM PDT 24
Finished Aug 12 05:16:12 PM PDT 24
Peak memory 183208 kb
Host smart-d3e8113b-653c-4dd4-a750-693fb53fd7b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005126231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1005126231
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1134640070
Short name T524
Test name
Test status
Simulation time 14364200 ps
CPU time 0.57 seconds
Started Aug 12 05:16:04 PM PDT 24
Finished Aug 12 05:16:05 PM PDT 24
Peak memory 183132 kb
Host smart-8269bd10-8971-452b-9416-7d0147fdfc0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134640070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1134640070
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3514667610
Short name T467
Test name
Test status
Simulation time 165475936 ps
CPU time 0.52 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 05:16:14 PM PDT 24
Peak memory 183096 kb
Host smart-0752f212-ee1c-45ae-babc-54b3f4370a71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514667610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3514667610
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.4126523299
Short name T479
Test name
Test status
Simulation time 14023430 ps
CPU time 0.58 seconds
Started Aug 12 05:16:04 PM PDT 24
Finished Aug 12 05:16:10 PM PDT 24
Peak memory 183120 kb
Host smart-ea9d6bd7-2236-4643-a486-0fe69acd2c25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126523299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.4126523299
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.4252880599
Short name T505
Test name
Test status
Simulation time 26465670 ps
CPU time 0.6 seconds
Started Aug 12 05:16:00 PM PDT 24
Finished Aug 12 05:16:00 PM PDT 24
Peak memory 183008 kb
Host smart-c3d74918-ca00-44e9-b6cc-35acc044a8d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252880599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.4252880599
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3220329536
Short name T474
Test name
Test status
Simulation time 12358545 ps
CPU time 0.56 seconds
Started Aug 12 05:16:03 PM PDT 24
Finished Aug 12 05:16:04 PM PDT 24
Peak memory 183120 kb
Host smart-d05986d0-5665-411f-b129-83abac23698d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220329536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3220329536
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.725826675
Short name T521
Test name
Test status
Simulation time 28018919 ps
CPU time 0.74 seconds
Started Aug 12 05:15:38 PM PDT 24
Finished Aug 12 05:15:45 PM PDT 24
Peak memory 195672 kb
Host smart-4d797537-fb24-4284-9e19-1f3461ba79f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725826675 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.725826675
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2947397138
Short name T572
Test name
Test status
Simulation time 40479871 ps
CPU time 0.53 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 182868 kb
Host smart-c548fe90-2e80-4a38-9e24-f8bbf475a5e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947397138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2947397138
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.403995001
Short name T503
Test name
Test status
Simulation time 44255277 ps
CPU time 0.55 seconds
Started Aug 12 05:15:39 PM PDT 24
Finished Aug 12 05:15:40 PM PDT 24
Peak memory 183088 kb
Host smart-ea43e4e5-0ea0-4ed7-afeb-377b29ba5519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403995001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.403995001
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3339797337
Short name T552
Test name
Test status
Simulation time 40967020 ps
CPU time 0.79 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:15:45 PM PDT 24
Peak memory 193780 kb
Host smart-b1df474b-b90c-441a-9987-9830861ea21a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339797337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3339797337
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3743517262
Short name T464
Test name
Test status
Simulation time 133330829 ps
CPU time 2.36 seconds
Started Aug 12 05:15:56 PM PDT 24
Finished Aug 12 05:15:58 PM PDT 24
Peak memory 197964 kb
Host smart-d1bb44a7-3c1f-4e53-903e-ebae231d2499
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743517262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3743517262
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3119240362
Short name T551
Test name
Test status
Simulation time 186960442 ps
CPU time 0.82 seconds
Started Aug 12 05:15:45 PM PDT 24
Finished Aug 12 05:15:46 PM PDT 24
Peak memory 193916 kb
Host smart-fbdaf6cc-6ba0-457a-ac40-b44284e494c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119240362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3119240362
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2944398107
Short name T470
Test name
Test status
Simulation time 29773357 ps
CPU time 0.61 seconds
Started Aug 12 05:15:49 PM PDT 24
Finished Aug 12 05:15:49 PM PDT 24
Peak memory 194384 kb
Host smart-5e376f51-5ddc-42ef-a6fe-1563c66f8432
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944398107 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2944398107
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1590968750
Short name T487
Test name
Test status
Simulation time 22462965 ps
CPU time 0.65 seconds
Started Aug 12 05:15:40 PM PDT 24
Finished Aug 12 05:15:41 PM PDT 24
Peak memory 183264 kb
Host smart-79ff55c4-ae1d-4dcf-a3d4-40daab75c152
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590968750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1590968750
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1187637892
Short name T559
Test name
Test status
Simulation time 14657784 ps
CPU time 0.58 seconds
Started Aug 12 05:15:51 PM PDT 24
Finished Aug 12 05:15:52 PM PDT 24
Peak memory 183136 kb
Host smart-f2fe9ae5-38f9-4a7b-b0aa-eeaf902864a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187637892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1187637892
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3556325420
Short name T77
Test name
Test status
Simulation time 26308773 ps
CPU time 0.72 seconds
Started Aug 12 05:15:55 PM PDT 24
Finished Aug 12 05:15:56 PM PDT 24
Peak memory 193888 kb
Host smart-175c2567-cf20-4905-8cea-924450426fda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556325420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3556325420
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3732401030
Short name T468
Test name
Test status
Simulation time 27950141 ps
CPU time 1.45 seconds
Started Aug 12 05:15:51 PM PDT 24
Finished Aug 12 05:15:52 PM PDT 24
Peak memory 197856 kb
Host smart-b5f458ee-35fe-4d0e-975e-30cf60d77765
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732401030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3732401030
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1403119751
Short name T515
Test name
Test status
Simulation time 153003830 ps
CPU time 1.1 seconds
Started Aug 12 05:15:47 PM PDT 24
Finished Aug 12 05:15:48 PM PDT 24
Peak memory 195836 kb
Host smart-740e6445-e893-4951-b7be-635ed26ab753
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403119751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1403119751
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2373812404
Short name T478
Test name
Test status
Simulation time 31303850 ps
CPU time 1.35 seconds
Started Aug 12 05:15:41 PM PDT 24
Finished Aug 12 05:15:43 PM PDT 24
Peak memory 198088 kb
Host smart-a3e88350-3c25-4933-b0b6-99fac521ca43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373812404 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2373812404
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2467687561
Short name T477
Test name
Test status
Simulation time 25829644 ps
CPU time 0.56 seconds
Started Aug 12 05:15:34 PM PDT 24
Finished Aug 12 05:15:35 PM PDT 24
Peak memory 183136 kb
Host smart-4710d52f-6682-434e-91e2-4c1dd0a7a669
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467687561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2467687561
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1929549634
Short name T566
Test name
Test status
Simulation time 25290538 ps
CPU time 0.54 seconds
Started Aug 12 05:15:52 PM PDT 24
Finished Aug 12 05:15:53 PM PDT 24
Peak memory 183072 kb
Host smart-2438096f-a65c-4de2-86be-fa30385d17d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929549634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1929549634
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1983116020
Short name T80
Test name
Test status
Simulation time 24824900 ps
CPU time 0.69 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 193568 kb
Host smart-0a15703a-3dd7-4204-85b2-14417f49b157
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983116020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1983116020
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2338274513
Short name T494
Test name
Test status
Simulation time 899508644 ps
CPU time 3.24 seconds
Started Aug 12 05:15:55 PM PDT 24
Finished Aug 12 05:15:58 PM PDT 24
Peak memory 197984 kb
Host smart-736ec372-92b7-4157-a495-1a55032759ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338274513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2338274513
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3502123592
Short name T549
Test name
Test status
Simulation time 135102331 ps
CPU time 1.05 seconds
Started Aug 12 05:15:44 PM PDT 24
Finished Aug 12 05:15:45 PM PDT 24
Peak memory 195740 kb
Host smart-87e4372b-ebfd-40aa-8a60-e01ef4067444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502123592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3502123592
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4089786212
Short name T577
Test name
Test status
Simulation time 170617607 ps
CPU time 0.91 seconds
Started Aug 12 05:15:54 PM PDT 24
Finished Aug 12 05:15:55 PM PDT 24
Peak memory 197516 kb
Host smart-91042ba9-e684-4f23-abc9-56877c09f478
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089786212 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.4089786212
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.906056379
Short name T522
Test name
Test status
Simulation time 92512205 ps
CPU time 0.59 seconds
Started Aug 12 05:15:52 PM PDT 24
Finished Aug 12 05:15:52 PM PDT 24
Peak memory 183248 kb
Host smart-014dd758-d632-450b-9032-64a7b07d25ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906056379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.906056379
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1530298348
Short name T454
Test name
Test status
Simulation time 47251292 ps
CPU time 0.56 seconds
Started Aug 12 05:15:51 PM PDT 24
Finished Aug 12 05:15:52 PM PDT 24
Peak memory 183084 kb
Host smart-fc5d98c4-cfda-4ac3-addc-9c0be978d399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530298348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1530298348
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1075845360
Short name T560
Test name
Test status
Simulation time 51658719 ps
CPU time 0.77 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 194052 kb
Host smart-a45b9dbc-af6f-42a2-9c7a-4c588f0d01b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075845360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1075845360
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2131052720
Short name T491
Test name
Test status
Simulation time 126899548 ps
CPU time 0.91 seconds
Started Aug 12 05:15:46 PM PDT 24
Finished Aug 12 05:15:47 PM PDT 24
Peak memory 195756 kb
Host smart-707b7418-b35c-459f-8a29-49aadbc74f00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131052720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2131052720
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.389816254
Short name T85
Test name
Test status
Simulation time 167356520 ps
CPU time 0.81 seconds
Started Aug 12 05:15:52 PM PDT 24
Finished Aug 12 05:15:53 PM PDT 24
Peak memory 183588 kb
Host smart-68f57767-86c3-45ea-95c3-62674cafa844
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389816254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.389816254
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1086558641
Short name T546
Test name
Test status
Simulation time 23303400 ps
CPU time 1.07 seconds
Started Aug 12 05:15:44 PM PDT 24
Finished Aug 12 05:15:46 PM PDT 24
Peak memory 197900 kb
Host smart-a2f96255-da79-44dd-bf5a-2aaf023c44c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086558641 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1086558641
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2619287093
Short name T72
Test name
Test status
Simulation time 65335975 ps
CPU time 0.52 seconds
Started Aug 12 05:15:37 PM PDT 24
Finished Aug 12 05:15:38 PM PDT 24
Peak memory 183308 kb
Host smart-c636eeed-bdca-4a79-872e-149265e2e4af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619287093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2619287093
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2052910633
Short name T506
Test name
Test status
Simulation time 30219953 ps
CPU time 0.54 seconds
Started Aug 12 05:15:39 PM PDT 24
Finished Aug 12 05:15:40 PM PDT 24
Peak memory 183112 kb
Host smart-1fda18b1-d57d-4539-8e7c-e864957a3cc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052910633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2052910633
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3193300041
Short name T66
Test name
Test status
Simulation time 176652771 ps
CPU time 0.61 seconds
Started Aug 12 05:15:51 PM PDT 24
Finished Aug 12 05:15:51 PM PDT 24
Peak memory 192072 kb
Host smart-d5c4420f-e408-4b6b-b711-0238181faf39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193300041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3193300041
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3505495742
Short name T486
Test name
Test status
Simulation time 384566140 ps
CPU time 1.37 seconds
Started Aug 12 05:15:43 PM PDT 24
Finished Aug 12 05:15:44 PM PDT 24
Peak memory 197920 kb
Host smart-4153031a-318b-4d48-be57-7db2d74c6f4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505495742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3505495742
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3142752698
Short name T32
Test name
Test status
Simulation time 528899292 ps
CPU time 0.91 seconds
Started Aug 12 05:15:50 PM PDT 24
Finished Aug 12 05:15:52 PM PDT 24
Peak memory 194148 kb
Host smart-e8875093-2315-4e84-b070-80bfdf2b6f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142752698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3142752698
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1452727250
Short name T436
Test name
Test status
Simulation time 705099085126 ps
CPU time 645.68 seconds
Started Aug 12 05:16:11 PM PDT 24
Finished Aug 12 05:26:57 PM PDT 24
Peak memory 183100 kb
Host smart-39540a84-328c-4354-9113-1ceb7a3a6165
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452727250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1452727250
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.4260027747
Short name T369
Test name
Test status
Simulation time 89734657999 ps
CPU time 153.12 seconds
Started Aug 12 05:16:05 PM PDT 24
Finished Aug 12 05:18:38 PM PDT 24
Peak memory 183160 kb
Host smart-2ed30287-6181-4d07-90b8-67c497f070ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260027747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.4260027747
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2437387177
Short name T99
Test name
Test status
Simulation time 111948355449 ps
CPU time 88.37 seconds
Started Aug 12 05:15:59 PM PDT 24
Finished Aug 12 05:17:28 PM PDT 24
Peak memory 183284 kb
Host smart-6d01f41f-7b7c-4590-b6e2-7e3c49853656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437387177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2437387177
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.792595384
Short name T374
Test name
Test status
Simulation time 593645046081 ps
CPU time 251.28 seconds
Started Aug 12 05:16:03 PM PDT 24
Finished Aug 12 05:20:14 PM PDT 24
Peak memory 183148 kb
Host smart-e645d9eb-d3d8-497f-875c-9ee49c287797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792595384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.792595384
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2528969164
Short name T187
Test name
Test status
Simulation time 1445323391943 ps
CPU time 344.99 seconds
Started Aug 12 05:16:06 PM PDT 24
Finished Aug 12 05:21:51 PM PDT 24
Peak memory 191368 kb
Host smart-88fb46fa-efd9-4098-abc0-7370c87a7e51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528969164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2528969164
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3995729022
Short name T356
Test name
Test status
Simulation time 44694723682 ps
CPU time 62.86 seconds
Started Aug 12 05:16:05 PM PDT 24
Finished Aug 12 05:17:08 PM PDT 24
Peak memory 191276 kb
Host smart-7f5dc016-6e53-4623-b252-2c7b90fa4129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995729022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3995729022
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2089525635
Short name T19
Test name
Test status
Simulation time 94780502 ps
CPU time 0.93 seconds
Started Aug 12 05:16:07 PM PDT 24
Finished Aug 12 05:16:08 PM PDT 24
Peak memory 214664 kb
Host smart-a5d920cb-f939-4731-a7d2-6d758ef62107
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089525635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2089525635
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.817145580
Short name T321
Test name
Test status
Simulation time 587821848271 ps
CPU time 306.4 seconds
Started Aug 12 05:16:06 PM PDT 24
Finished Aug 12 05:21:12 PM PDT 24
Peak memory 183144 kb
Host smart-43db7a27-36d1-4bde-8daf-aa3e4df992ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817145580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.817145580
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.154158219
Short name T442
Test name
Test status
Simulation time 731071998088 ps
CPU time 294.2 seconds
Started Aug 12 05:16:14 PM PDT 24
Finished Aug 12 05:21:08 PM PDT 24
Peak memory 183140 kb
Host smart-7883af0b-9d63-4ed6-b887-9f586d76df65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154158219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.154158219
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.439838601
Short name T433
Test name
Test status
Simulation time 161915725328 ps
CPU time 50.3 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 05:17:03 PM PDT 24
Peak memory 182924 kb
Host smart-eba257e6-93ff-48f0-a3ec-d832614ecdb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439838601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.439838601
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.4042503944
Short name T131
Test name
Test status
Simulation time 67680325869 ps
CPU time 123.31 seconds
Started Aug 12 05:16:07 PM PDT 24
Finished Aug 12 05:18:11 PM PDT 24
Peak memory 183068 kb
Host smart-c18dca02-d7f6-4964-aaaa-4671d909c2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042503944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.4042503944
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2665479942
Short name T402
Test name
Test status
Simulation time 69420237244 ps
CPU time 94.84 seconds
Started Aug 12 05:16:07 PM PDT 24
Finished Aug 12 05:17:42 PM PDT 24
Peak memory 183124 kb
Host smart-7bc64c07-ad3a-4be1-879c-cea7b0f6abf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665479942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2665479942
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2351232654
Short name T429
Test name
Test status
Simulation time 2585250961 ps
CPU time 11.41 seconds
Started Aug 12 05:16:06 PM PDT 24
Finished Aug 12 05:16:18 PM PDT 24
Peak memory 197828 kb
Host smart-56029c6c-4dde-4a91-84cf-87fa445ff51e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351232654 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2351232654
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.1191877834
Short name T108
Test name
Test status
Simulation time 33614497286 ps
CPU time 250.81 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:21:11 PM PDT 24
Peak memory 191320 kb
Host smart-a8f05797-cb4c-440c-b6c4-f57812ceabef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191877834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1191877834
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.65855812
Short name T236
Test name
Test status
Simulation time 1594145036 ps
CPU time 14.8 seconds
Started Aug 12 05:16:47 PM PDT 24
Finished Aug 12 05:17:02 PM PDT 24
Peak memory 183032 kb
Host smart-4dfd292f-9500-4b0e-93fb-6489bf320d51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65855812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.65855812
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.208974884
Short name T304
Test name
Test status
Simulation time 19138926834 ps
CPU time 57.1 seconds
Started Aug 12 05:16:57 PM PDT 24
Finished Aug 12 05:17:54 PM PDT 24
Peak memory 191328 kb
Host smart-30b0a10e-120d-41f3-b0be-2e9044013fbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208974884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.208974884
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2673479454
Short name T159
Test name
Test status
Simulation time 438427396528 ps
CPU time 444.37 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:24:25 PM PDT 24
Peak memory 191244 kb
Host smart-16ae71a3-c030-4592-80db-387925482b70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673479454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2673479454
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2489252416
Short name T308
Test name
Test status
Simulation time 1144067683796 ps
CPU time 1087.62 seconds
Started Aug 12 05:16:11 PM PDT 24
Finished Aug 12 05:34:19 PM PDT 24
Peak memory 182972 kb
Host smart-76ed95de-31e5-4ea5-b8ab-0118ec2ad37f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489252416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2489252416
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1785631457
Short name T391
Test name
Test status
Simulation time 714680598248 ps
CPU time 219.23 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:19:52 PM PDT 24
Peak memory 183140 kb
Host smart-5d9a096c-4bf4-4c6d-a652-d29f10d9f6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785631457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1785631457
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2593391304
Short name T94
Test name
Test status
Simulation time 13043389646 ps
CPU time 18.53 seconds
Started Aug 12 05:16:11 PM PDT 24
Finished Aug 12 05:16:30 PM PDT 24
Peak memory 183084 kb
Host smart-80f8fb53-25ca-475e-8bab-fa78258c290f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593391304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2593391304
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2547630407
Short name T280
Test name
Test status
Simulation time 116188143647 ps
CPU time 439.07 seconds
Started Aug 12 05:16:55 PM PDT 24
Finished Aug 12 05:24:15 PM PDT 24
Peak memory 191364 kb
Host smart-fe8c6764-f6cd-438a-8c1a-424ef04ea4bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547630407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2547630407
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2802033876
Short name T29
Test name
Test status
Simulation time 14296868714 ps
CPU time 91.94 seconds
Started Aug 12 05:16:50 PM PDT 24
Finished Aug 12 05:18:22 PM PDT 24
Peak memory 182940 kb
Host smart-0007909d-3bac-42de-8cfb-cf4c113079fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802033876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2802033876
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3568956793
Short name T293
Test name
Test status
Simulation time 114117953273 ps
CPU time 175.55 seconds
Started Aug 12 05:16:55 PM PDT 24
Finished Aug 12 05:19:50 PM PDT 24
Peak memory 191360 kb
Host smart-9ff23bfc-d193-40b3-b49c-ec7945a01479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568956793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3568956793
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.562212360
Short name T105
Test name
Test status
Simulation time 18629453147 ps
CPU time 10.45 seconds
Started Aug 12 05:16:56 PM PDT 24
Finished Aug 12 05:17:06 PM PDT 24
Peak memory 183172 kb
Host smart-d5bbfede-b8cf-4f7d-b755-9981674e48cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562212360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.562212360
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1425378749
Short name T305
Test name
Test status
Simulation time 71093446610 ps
CPU time 178.51 seconds
Started Aug 12 05:17:04 PM PDT 24
Finished Aug 12 05:20:03 PM PDT 24
Peak memory 183168 kb
Host smart-ccab6918-cbc6-46dc-9d24-8585f58fb299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425378749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1425378749
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3771430264
Short name T166
Test name
Test status
Simulation time 118395051551 ps
CPU time 212.19 seconds
Started Aug 12 05:16:51 PM PDT 24
Finished Aug 12 05:20:23 PM PDT 24
Peak memory 191388 kb
Host smart-276592c3-d1f2-4894-95ce-94620bb4c688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771430264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3771430264
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3225193753
Short name T190
Test name
Test status
Simulation time 409899574952 ps
CPU time 1642.49 seconds
Started Aug 12 05:16:49 PM PDT 24
Finished Aug 12 05:44:12 PM PDT 24
Peak memory 191244 kb
Host smart-d592c243-7447-45ca-8235-8583cd639532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225193753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3225193753
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.4087983927
Short name T324
Test name
Test status
Simulation time 24928792871 ps
CPU time 944.4 seconds
Started Aug 12 05:17:01 PM PDT 24
Finished Aug 12 05:32:46 PM PDT 24
Peak memory 183140 kb
Host smart-efdcc483-7981-4b7c-9f9d-1d82452e6ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087983927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4087983927
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.959079411
Short name T400
Test name
Test status
Simulation time 372760776920 ps
CPU time 130.5 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:18:23 PM PDT 24
Peak memory 183144 kb
Host smart-5f29c79d-fd0a-41c7-9fec-52563d921457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959079411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.959079411
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1751938981
Short name T21
Test name
Test status
Simulation time 34538610407 ps
CPU time 58.82 seconds
Started Aug 12 05:16:10 PM PDT 24
Finished Aug 12 05:17:09 PM PDT 24
Peak memory 191368 kb
Host smart-67728f38-a856-4915-a96b-0baa4dc8c6ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751938981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1751938981
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2756468134
Short name T390
Test name
Test status
Simulation time 2065903942 ps
CPU time 5.95 seconds
Started Aug 12 05:16:19 PM PDT 24
Finished Aug 12 05:16:25 PM PDT 24
Peak memory 183032 kb
Host smart-3cc7fdfa-10ed-4c87-9223-f55d8b7250ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756468134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2756468134
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3514538909
Short name T4
Test name
Test status
Simulation time 300761557549 ps
CPU time 253.26 seconds
Started Aug 12 05:16:21 PM PDT 24
Finished Aug 12 05:20:35 PM PDT 24
Peak memory 191348 kb
Host smart-93c115e6-7ba3-40a2-8688-b9a314e266e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514538909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3514538909
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.3898105252
Short name T267
Test name
Test status
Simulation time 508870084710 ps
CPU time 259.44 seconds
Started Aug 12 05:16:52 PM PDT 24
Finished Aug 12 05:21:12 PM PDT 24
Peak memory 191380 kb
Host smart-06e69750-2882-4172-a0bd-9c4655bace15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898105252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3898105252
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.916134718
Short name T425
Test name
Test status
Simulation time 24494159375 ps
CPU time 41.47 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:17:42 PM PDT 24
Peak memory 191380 kb
Host smart-6a7bbb58-4d8b-4627-b9e0-ebcde088412f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916134718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.916134718
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1505384434
Short name T130
Test name
Test status
Simulation time 181083880139 ps
CPU time 201.93 seconds
Started Aug 12 05:16:56 PM PDT 24
Finished Aug 12 05:20:18 PM PDT 24
Peak memory 191360 kb
Host smart-f091d4b6-fd61-4306-b0ae-4cb778b1d7db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505384434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1505384434
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3941744548
Short name T107
Test name
Test status
Simulation time 274946141451 ps
CPU time 1858.28 seconds
Started Aug 12 05:16:48 PM PDT 24
Finished Aug 12 05:47:47 PM PDT 24
Peak memory 191308 kb
Host smart-4fca2753-d593-4359-9daf-303d9d381dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941744548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3941744548
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1876188345
Short name T171
Test name
Test status
Simulation time 208560183214 ps
CPU time 425.07 seconds
Started Aug 12 05:16:49 PM PDT 24
Finished Aug 12 05:23:54 PM PDT 24
Peak memory 191352 kb
Host smart-993b9f77-3b40-4547-8755-c71451d0b5d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876188345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1876188345
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1620608737
Short name T269
Test name
Test status
Simulation time 125763248756 ps
CPU time 202.17 seconds
Started Aug 12 05:16:51 PM PDT 24
Finished Aug 12 05:20:13 PM PDT 24
Peak memory 183188 kb
Host smart-582cb239-950d-435e-a82f-ce0915183c3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620608737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1620608737
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.659292414
Short name T135
Test name
Test status
Simulation time 613688892 ps
CPU time 1.86 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:17:02 PM PDT 24
Peak memory 183020 kb
Host smart-85fd7bbf-f025-43b0-84f5-95d508abe526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659292414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.659292414
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2202354716
Short name T271
Test name
Test status
Simulation time 4376554156439 ps
CPU time 1018.25 seconds
Started Aug 12 05:16:19 PM PDT 24
Finished Aug 12 05:33:18 PM PDT 24
Peak memory 183156 kb
Host smart-8a0ba4f6-58da-44fd-a6bf-7bd417d04d59
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202354716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2202354716
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1172641613
Short name T372
Test name
Test status
Simulation time 505034271556 ps
CPU time 159.19 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 05:18:53 PM PDT 24
Peak memory 183136 kb
Host smart-1978c0e8-9b0d-4606-8487-396e04a1d994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172641613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1172641613
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2340939321
Short name T306
Test name
Test status
Simulation time 81123204650 ps
CPU time 329.45 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:21:42 PM PDT 24
Peak memory 191364 kb
Host smart-475d26cf-4a55-4925-83b7-0c0db27984b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340939321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2340939321
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3370424071
Short name T360
Test name
Test status
Simulation time 73509525 ps
CPU time 0.97 seconds
Started Aug 12 05:16:07 PM PDT 24
Finished Aug 12 05:16:09 PM PDT 24
Peak memory 183032 kb
Host smart-1da8624b-71e7-4df0-a49f-fff8695d3b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370424071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3370424071
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.1898331185
Short name T120
Test name
Test status
Simulation time 34043790076 ps
CPU time 69.23 seconds
Started Aug 12 05:16:56 PM PDT 24
Finished Aug 12 05:18:05 PM PDT 24
Peak memory 191348 kb
Host smart-f112698b-8b9b-4b75-b449-965c1ff8f9c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898331185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1898331185
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.775532312
Short name T179
Test name
Test status
Simulation time 270862574643 ps
CPU time 836.88 seconds
Started Aug 12 05:17:01 PM PDT 24
Finished Aug 12 05:30:58 PM PDT 24
Peak memory 191288 kb
Host smart-6f90266e-01f1-49b3-acb4-1b895c125d79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775532312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.775532312
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2878015375
Short name T354
Test name
Test status
Simulation time 378287743392 ps
CPU time 727.94 seconds
Started Aug 12 05:16:52 PM PDT 24
Finished Aug 12 05:29:00 PM PDT 24
Peak memory 191352 kb
Host smart-cdd743b9-ceab-4005-9fad-bfe1f82c743e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878015375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2878015375
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.318952392
Short name T95
Test name
Test status
Simulation time 1429932180257 ps
CPU time 872.94 seconds
Started Aug 12 05:16:52 PM PDT 24
Finished Aug 12 05:31:25 PM PDT 24
Peak memory 191348 kb
Host smart-855aa65c-bdd8-4aa8-bbf4-50d1242dcf9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318952392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.318952392
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.499202105
Short name T340
Test name
Test status
Simulation time 190807184778 ps
CPU time 102.28 seconds
Started Aug 12 05:16:59 PM PDT 24
Finished Aug 12 05:18:42 PM PDT 24
Peak memory 183180 kb
Host smart-7dacd2fb-1fe1-473f-a4df-82a8804d66cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499202105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.499202105
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3689863792
Short name T162
Test name
Test status
Simulation time 12119784396 ps
CPU time 7.71 seconds
Started Aug 12 05:16:19 PM PDT 24
Finished Aug 12 05:16:27 PM PDT 24
Peak memory 183060 kb
Host smart-40fa78bb-38a5-4804-ba63-191097208368
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689863792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3689863792
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.451717317
Short name T417
Test name
Test status
Simulation time 11494127167 ps
CPU time 17.07 seconds
Started Aug 12 05:16:22 PM PDT 24
Finished Aug 12 05:16:40 PM PDT 24
Peak memory 183144 kb
Host smart-b28e0626-836a-402b-9bef-14fda5f415ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451717317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.451717317
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3785653364
Short name T438
Test name
Test status
Simulation time 221190031386 ps
CPU time 699.62 seconds
Started Aug 12 05:16:11 PM PDT 24
Finished Aug 12 05:27:51 PM PDT 24
Peak memory 191368 kb
Host smart-99896578-96ce-4bf8-a314-8be6299ceadc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785653364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3785653364
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2406966997
Short name T292
Test name
Test status
Simulation time 81090380387 ps
CPU time 318.06 seconds
Started Aug 12 05:16:23 PM PDT 24
Finished Aug 12 05:21:41 PM PDT 24
Peak memory 191484 kb
Host smart-88dcd125-22f4-4493-a35e-129d6009566f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406966997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2406966997
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.4210999506
Short name T437
Test name
Test status
Simulation time 47350722616 ps
CPU time 69.09 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 05:17:22 PM PDT 24
Peak memory 183112 kb
Host smart-b253a6ad-60e2-4375-8bd5-5cb99a2ba06f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210999506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.4210999506
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.2369840132
Short name T348
Test name
Test status
Simulation time 164862362924 ps
CPU time 79.95 seconds
Started Aug 12 05:16:55 PM PDT 24
Finished Aug 12 05:18:15 PM PDT 24
Peak memory 183164 kb
Host smart-0357929a-40f9-487e-b9fd-aedec3bd9dfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369840132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2369840132
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.658260173
Short name T279
Test name
Test status
Simulation time 52653775164 ps
CPU time 34.74 seconds
Started Aug 12 05:17:04 PM PDT 24
Finished Aug 12 05:17:39 PM PDT 24
Peak memory 182884 kb
Host smart-5f1a101e-7bd9-4fd3-8fe1-bd1f61a66e72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658260173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.658260173
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1871838303
Short name T424
Test name
Test status
Simulation time 337557694049 ps
CPU time 196.06 seconds
Started Aug 12 05:16:49 PM PDT 24
Finished Aug 12 05:20:05 PM PDT 24
Peak memory 191280 kb
Host smart-068fbaee-ab38-4d29-bcb3-91a133aae159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871838303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1871838303
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.909747074
Short name T290
Test name
Test status
Simulation time 109432062940 ps
CPU time 236.99 seconds
Started Aug 12 05:16:55 PM PDT 24
Finished Aug 12 05:20:52 PM PDT 24
Peak memory 191344 kb
Host smart-c98c0d00-3382-46b7-8252-f28ca39085a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909747074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.909747074
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1226533019
Short name T109
Test name
Test status
Simulation time 208000242172 ps
CPU time 241.9 seconds
Started Aug 12 05:16:50 PM PDT 24
Finished Aug 12 05:20:53 PM PDT 24
Peak memory 191336 kb
Host smart-7fbfe297-5ab3-4391-99fe-424ddf404239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226533019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1226533019
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2327870180
Short name T172
Test name
Test status
Simulation time 203625646564 ps
CPU time 289.19 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:21:49 PM PDT 24
Peak memory 191240 kb
Host smart-bfa0aa31-37db-4e35-b0d4-d304e0e11e37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327870180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2327870180
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2719332769
Short name T287
Test name
Test status
Simulation time 2341931388 ps
CPU time 2.47 seconds
Started Aug 12 05:16:58 PM PDT 24
Finished Aug 12 05:17:00 PM PDT 24
Peak memory 182940 kb
Host smart-ad86b6ae-cfd0-494b-aa05-c76cc264ae90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719332769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2719332769
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1784990550
Short name T276
Test name
Test status
Simulation time 33578086250 ps
CPU time 163.79 seconds
Started Aug 12 05:16:59 PM PDT 24
Finished Aug 12 05:19:43 PM PDT 24
Peak memory 191364 kb
Host smart-94a63494-63bc-4c0d-ac89-a3a105332b95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784990550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1784990550
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2381564523
Short name T112
Test name
Test status
Simulation time 638373785804 ps
CPU time 612.47 seconds
Started Aug 12 05:16:15 PM PDT 24
Finished Aug 12 05:26:28 PM PDT 24
Peak memory 183096 kb
Host smart-e862f209-97af-41b0-8037-ab7dd6e5f3f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381564523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2381564523
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.325120603
Short name T407
Test name
Test status
Simulation time 119727420602 ps
CPU time 205.91 seconds
Started Aug 12 05:16:36 PM PDT 24
Finished Aug 12 05:20:02 PM PDT 24
Peak memory 183164 kb
Host smart-aacfd86f-f1bc-4d55-a7bd-6700f76789da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325120603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.325120603
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.1052612057
Short name T156
Test name
Test status
Simulation time 231379561074 ps
CPU time 274.43 seconds
Started Aug 12 05:16:32 PM PDT 24
Finished Aug 12 05:21:07 PM PDT 24
Peak memory 191356 kb
Host smart-4756eff6-44a2-4bc7-9ae1-f01be7d0f47a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052612057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1052612057
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3809936123
Short name T422
Test name
Test status
Simulation time 199570523 ps
CPU time 0.73 seconds
Started Aug 12 05:16:25 PM PDT 24
Finished Aug 12 05:16:26 PM PDT 24
Peak memory 182792 kb
Host smart-f873fee0-e1f6-417b-91a8-e0a630388441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809936123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3809936123
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2535059830
Short name T452
Test name
Test status
Simulation time 2667642503113 ps
CPU time 1087.09 seconds
Started Aug 12 05:16:10 PM PDT 24
Finished Aug 12 05:34:17 PM PDT 24
Peak memory 196272 kb
Host smart-df74bace-1d6a-4103-a882-01d75cfad224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535059830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2535059830
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.4034394857
Short name T42
Test name
Test status
Simulation time 171733031 ps
CPU time 1.81 seconds
Started Aug 12 05:16:09 PM PDT 24
Finished Aug 12 05:16:11 PM PDT 24
Peak memory 197732 kb
Host smart-3a381a9c-4efb-439e-9ee9-9926e2aaffe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034394857 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.4034394857
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/152.rv_timer_random.2827964381
Short name T350
Test name
Test status
Simulation time 102845884392 ps
CPU time 68.29 seconds
Started Aug 12 05:16:59 PM PDT 24
Finished Aug 12 05:18:08 PM PDT 24
Peak memory 183036 kb
Host smart-d3c18188-a267-490a-8b06-51174c236539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827964381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2827964381
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3019096656
Short name T281
Test name
Test status
Simulation time 8958158357 ps
CPU time 11.05 seconds
Started Aug 12 05:16:58 PM PDT 24
Finished Aug 12 05:17:09 PM PDT 24
Peak memory 183104 kb
Host smart-90dd773c-4062-4a08-9732-204728d3197a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019096656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3019096656
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2084494672
Short name T289
Test name
Test status
Simulation time 97302315860 ps
CPU time 79.21 seconds
Started Aug 12 05:17:01 PM PDT 24
Finished Aug 12 05:18:21 PM PDT 24
Peak memory 191360 kb
Host smart-d71fc184-e9f1-4606-8d92-9c5261798cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084494672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2084494672
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3867361669
Short name T282
Test name
Test status
Simulation time 163658152195 ps
CPU time 301.51 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:22:01 PM PDT 24
Peak memory 191308 kb
Host smart-608e50fe-b3e3-4737-839e-f32d468e9064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867361669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3867361669
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2206598510
Short name T381
Test name
Test status
Simulation time 5311543317 ps
CPU time 3.38 seconds
Started Aug 12 05:16:24 PM PDT 24
Finished Aug 12 05:16:28 PM PDT 24
Peak memory 182960 kb
Host smart-01a168c6-54bd-47ba-8339-7cc6cf8d69c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206598510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2206598510
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3806122068
Short name T207
Test name
Test status
Simulation time 14759790139 ps
CPU time 27.54 seconds
Started Aug 12 05:16:27 PM PDT 24
Finished Aug 12 05:16:54 PM PDT 24
Peak memory 191332 kb
Host smart-4c35fbbf-245d-40e8-922a-fee615df8cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806122068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3806122068
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.4256292369
Short name T384
Test name
Test status
Simulation time 19565930 ps
CPU time 0.55 seconds
Started Aug 12 05:16:19 PM PDT 24
Finished Aug 12 05:16:20 PM PDT 24
Peak memory 182832 kb
Host smart-916d71a4-fa88-41b2-bac2-ec7a7c340c70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256292369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.4256292369
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.1401449346
Short name T320
Test name
Test status
Simulation time 288849154220 ps
CPU time 243.35 seconds
Started Aug 12 05:17:02 PM PDT 24
Finished Aug 12 05:21:05 PM PDT 24
Peak memory 191208 kb
Host smart-ad7b664f-8277-4c4c-b1e0-55b699914a36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401449346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1401449346
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3387900698
Short name T263
Test name
Test status
Simulation time 21187003109 ps
CPU time 42.17 seconds
Started Aug 12 05:16:57 PM PDT 24
Finished Aug 12 05:17:40 PM PDT 24
Peak memory 183184 kb
Host smart-a9620b2b-83b7-4393-86ef-717484562810
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387900698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3387900698
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.461180156
Short name T351
Test name
Test status
Simulation time 387891593377 ps
CPU time 286.21 seconds
Started Aug 12 05:16:57 PM PDT 24
Finished Aug 12 05:21:44 PM PDT 24
Peak memory 191364 kb
Host smart-47aa20f1-b8ad-42a0-af73-83a77e1d7664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461180156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.461180156
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2258466213
Short name T446
Test name
Test status
Simulation time 71171776023 ps
CPU time 386.6 seconds
Started Aug 12 05:17:02 PM PDT 24
Finished Aug 12 05:23:29 PM PDT 24
Peak memory 194476 kb
Host smart-d296c831-abcd-4389-bf16-e03e91454c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258466213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2258466213
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3478197099
Short name T98
Test name
Test status
Simulation time 186266486885 ps
CPU time 990.48 seconds
Started Aug 12 05:16:59 PM PDT 24
Finished Aug 12 05:33:30 PM PDT 24
Peak memory 191316 kb
Host smart-e49e17ac-1fb7-44cc-9b41-788f2ca5efa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478197099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3478197099
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2085581671
Short name T150
Test name
Test status
Simulation time 191813446293 ps
CPU time 509.23 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 05:25:33 PM PDT 24
Peak memory 191380 kb
Host smart-2690e018-be88-438a-8d5f-ba8344543866
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085581671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2085581671
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3983351103
Short name T154
Test name
Test status
Simulation time 122311115312 ps
CPU time 182.85 seconds
Started Aug 12 05:16:35 PM PDT 24
Finished Aug 12 05:19:38 PM PDT 24
Peak memory 183140 kb
Host smart-f82b8042-612a-4c69-891b-c1dd81bdcabb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983351103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3983351103
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2222810289
Short name T385
Test name
Test status
Simulation time 15426974734 ps
CPU time 20.95 seconds
Started Aug 12 05:16:07 PM PDT 24
Finished Aug 12 05:16:28 PM PDT 24
Peak memory 183108 kb
Host smart-1c32f4a9-e925-4aa7-b20e-89ecac914e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222810289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2222810289
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.79800282
Short name T169
Test name
Test status
Simulation time 15224697316 ps
CPU time 28.86 seconds
Started Aug 12 05:16:15 PM PDT 24
Finished Aug 12 05:16:44 PM PDT 24
Peak memory 183096 kb
Host smart-d5d3b02d-9d94-4afc-a5db-5c4717f27ba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79800282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.79800282
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.4192304028
Short name T393
Test name
Test status
Simulation time 950318781159 ps
CPU time 266.52 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:20:38 PM PDT 24
Peak memory 183088 kb
Host smart-36eeeb22-c1b0-479b-9b16-7eb888de0954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192304028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.4192304028
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.2716250013
Short name T215
Test name
Test status
Simulation time 566537246837 ps
CPU time 445.94 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 05:24:29 PM PDT 24
Peak memory 191300 kb
Host smart-d9c574d6-1d4d-471c-a8f1-97ac6a39ae4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716250013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2716250013
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1738930044
Short name T139
Test name
Test status
Simulation time 138775053241 ps
CPU time 555.42 seconds
Started Aug 12 05:17:06 PM PDT 24
Finished Aug 12 05:26:21 PM PDT 24
Peak memory 191304 kb
Host smart-c056acf7-a081-43cf-ac6b-f67bf9881b32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738930044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1738930044
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3470466465
Short name T113
Test name
Test status
Simulation time 168477352112 ps
CPU time 269.63 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 05:21:33 PM PDT 24
Peak memory 191320 kb
Host smart-09a6ac96-7684-4746-a0dc-494539fc42f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470466465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3470466465
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3584629889
Short name T106
Test name
Test status
Simulation time 121693397190 ps
CPU time 1298.55 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 05:38:41 PM PDT 24
Peak memory 191016 kb
Host smart-1667b02c-48e3-478e-9e6f-b6c224e26825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584629889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3584629889
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.4114463764
Short name T345
Test name
Test status
Simulation time 64498296464 ps
CPU time 40.79 seconds
Started Aug 12 05:17:01 PM PDT 24
Finished Aug 12 05:17:42 PM PDT 24
Peak memory 191240 kb
Host smart-f23d4073-d501-4736-8e2c-e5eacf08b698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114463764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.4114463764
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3871720811
Short name T201
Test name
Test status
Simulation time 309427680855 ps
CPU time 140.05 seconds
Started Aug 12 05:16:59 PM PDT 24
Finished Aug 12 05:19:19 PM PDT 24
Peak memory 191316 kb
Host smart-e355a771-838d-4b57-b612-bfd2ebf36abf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871720811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3871720811
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.4007930330
Short name T353
Test name
Test status
Simulation time 388881099517 ps
CPU time 701.6 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 05:27:54 PM PDT 24
Peak memory 183212 kb
Host smart-f31b7d00-678d-4ab5-911b-89024c3a3f5d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007930330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.4007930330
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.4173363831
Short name T411
Test name
Test status
Simulation time 52764315387 ps
CPU time 65.91 seconds
Started Aug 12 05:16:16 PM PDT 24
Finished Aug 12 05:17:22 PM PDT 24
Peak memory 183140 kb
Host smart-ce891c2b-ee1c-4ca3-ab73-3f59e8fa133e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173363831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.4173363831
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1626056247
Short name T240
Test name
Test status
Simulation time 156107285188 ps
CPU time 86.42 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 05:17:39 PM PDT 24
Peak memory 183096 kb
Host smart-f0dd2980-6794-465c-9620-fe91854f90e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626056247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1626056247
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/182.rv_timer_random.493320634
Short name T25
Test name
Test status
Simulation time 199558512622 ps
CPU time 1911.54 seconds
Started Aug 12 05:17:01 PM PDT 24
Finished Aug 12 05:48:53 PM PDT 24
Peak memory 191252 kb
Host smart-30ef064b-a455-4ba4-b63b-8848d0ba92a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493320634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.493320634
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1846136605
Short name T194
Test name
Test status
Simulation time 134419973436 ps
CPU time 458.72 seconds
Started Aug 12 05:17:02 PM PDT 24
Finished Aug 12 05:24:41 PM PDT 24
Peak memory 191340 kb
Host smart-46fff8d8-c66b-46ef-bc33-429f0f02ea15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846136605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1846136605
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3354861048
Short name T355
Test name
Test status
Simulation time 327077811088 ps
CPU time 555.68 seconds
Started Aug 12 05:17:06 PM PDT 24
Finished Aug 12 05:26:22 PM PDT 24
Peak memory 191248 kb
Host smart-8d8adca4-947b-4c54-9a83-efe477b58359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354861048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3354861048
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1440534249
Short name T111
Test name
Test status
Simulation time 1165427307 ps
CPU time 1.07 seconds
Started Aug 12 05:16:52 PM PDT 24
Finished Aug 12 05:16:53 PM PDT 24
Peak memory 182868 kb
Host smart-6d58d6c3-db05-45e5-8014-cf4b4af17db2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440534249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1440534249
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3270290128
Short name T140
Test name
Test status
Simulation time 213022921957 ps
CPU time 111.54 seconds
Started Aug 12 05:17:02 PM PDT 24
Finished Aug 12 05:18:54 PM PDT 24
Peak memory 191320 kb
Host smart-563f74e0-91dd-49e6-98f0-b827d7c8d83c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270290128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3270290128
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3694833426
Short name T247
Test name
Test status
Simulation time 28467640725 ps
CPU time 61.5 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 05:18:04 PM PDT 24
Peak memory 183172 kb
Host smart-fd48b2e9-00c3-450b-bcf4-51c20d2db63d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694833426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3694833426
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.4139570586
Short name T91
Test name
Test status
Simulation time 53321641682 ps
CPU time 84.14 seconds
Started Aug 12 05:17:02 PM PDT 24
Finished Aug 12 05:18:27 PM PDT 24
Peak memory 191272 kb
Host smart-d2b99056-ffde-4836-8dff-40c7d510ff20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139570586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.4139570586
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.4028387368
Short name T296
Test name
Test status
Simulation time 3512763055486 ps
CPU time 1245.51 seconds
Started Aug 12 05:16:10 PM PDT 24
Finished Aug 12 05:36:55 PM PDT 24
Peak memory 183132 kb
Host smart-806aa62f-8ae7-4839-ad90-01f55f1c841b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028387368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.4028387368
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3726140277
Short name T47
Test name
Test status
Simulation time 73929788966 ps
CPU time 120.68 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 05:18:14 PM PDT 24
Peak memory 183080 kb
Host smart-95287cdb-d07b-4bc7-9899-54c3a60275b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726140277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3726140277
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.3668387619
Short name T180
Test name
Test status
Simulation time 112369100550 ps
CPU time 267.89 seconds
Started Aug 12 05:16:33 PM PDT 24
Finished Aug 12 05:21:01 PM PDT 24
Peak memory 193524 kb
Host smart-3d823800-1d10-4ec9-9460-2a1ef6ff6c16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668387619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3668387619
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.2350506358
Short name T100
Test name
Test status
Simulation time 516501994431 ps
CPU time 256.45 seconds
Started Aug 12 05:17:01 PM PDT 24
Finished Aug 12 05:21:18 PM PDT 24
Peak memory 191240 kb
Host smart-faae2674-31dc-473b-ad5a-1925d83b77ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350506358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2350506358
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3707962076
Short name T342
Test name
Test status
Simulation time 83301157503 ps
CPU time 73.04 seconds
Started Aug 12 05:17:04 PM PDT 24
Finished Aug 12 05:18:18 PM PDT 24
Peak memory 191320 kb
Host smart-d0b3c4fc-94e6-42eb-97dc-f1b49477a184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707962076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3707962076
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.440835333
Short name T395
Test name
Test status
Simulation time 20476678524 ps
CPU time 29.82 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 05:17:33 PM PDT 24
Peak memory 182932 kb
Host smart-454ee1aa-320e-436c-9b9c-1566800f7d72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440835333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.440835333
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1709955949
Short name T260
Test name
Test status
Simulation time 343079808139 ps
CPU time 213.75 seconds
Started Aug 12 05:16:51 PM PDT 24
Finished Aug 12 05:20:25 PM PDT 24
Peak memory 191332 kb
Host smart-962afe0a-f3b6-406b-934d-c0dab57001bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709955949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1709955949
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1350579293
Short name T447
Test name
Test status
Simulation time 700980173404 ps
CPU time 156.9 seconds
Started Aug 12 05:17:06 PM PDT 24
Finished Aug 12 05:19:43 PM PDT 24
Peak memory 183108 kb
Host smart-902d625f-78f6-46bf-bd34-6ba1fe66185a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350579293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1350579293
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.489249206
Short name T264
Test name
Test status
Simulation time 50551349149 ps
CPU time 88.86 seconds
Started Aug 12 05:17:09 PM PDT 24
Finished Aug 12 05:18:38 PM PDT 24
Peak memory 191392 kb
Host smart-b703106a-649f-422c-9dfb-92f88252663c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489249206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.489249206
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2385466140
Short name T389
Test name
Test status
Simulation time 808310982513 ps
CPU time 322.6 seconds
Started Aug 12 05:16:19 PM PDT 24
Finished Aug 12 05:21:42 PM PDT 24
Peak memory 183140 kb
Host smart-88e0775d-f388-4400-b5cf-434ddc075196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385466140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2385466140
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.2715826725
Short name T211
Test name
Test status
Simulation time 227834350753 ps
CPU time 215.72 seconds
Started Aug 12 05:16:10 PM PDT 24
Finished Aug 12 05:19:46 PM PDT 24
Peak memory 191332 kb
Host smart-837b4102-9f17-40df-b70f-0d1d414cd2b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715826725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2715826725
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2165388473
Short name T341
Test name
Test status
Simulation time 124147025106 ps
CPU time 21.34 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:16:34 PM PDT 24
Peak memory 183080 kb
Host smart-e0dbf6cd-e024-4b43-8252-99edecb4c047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165388473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2165388473
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.187347828
Short name T16
Test name
Test status
Simulation time 150329063 ps
CPU time 0.87 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 05:16:14 PM PDT 24
Peak memory 214576 kb
Host smart-ac430b30-cd6b-4077-a965-1504ef61c0f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187347828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.187347828
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2856296483
Short name T138
Test name
Test status
Simulation time 448066318980 ps
CPU time 222.27 seconds
Started Aug 12 05:16:11 PM PDT 24
Finished Aug 12 05:19:53 PM PDT 24
Peak memory 183136 kb
Host smart-6d9a90ed-64f0-467e-be3b-a3e468111fd4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856296483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2856296483
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1509955719
Short name T1
Test name
Test status
Simulation time 185287843503 ps
CPU time 159.4 seconds
Started Aug 12 05:16:20 PM PDT 24
Finished Aug 12 05:19:00 PM PDT 24
Peak memory 183168 kb
Host smart-ec7ade93-3f1e-478e-ad69-cdcda42c52e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509955719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1509955719
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2826739472
Short name T151
Test name
Test status
Simulation time 316505319521 ps
CPU time 2904.44 seconds
Started Aug 12 05:16:09 PM PDT 24
Finished Aug 12 06:04:34 PM PDT 24
Peak memory 191300 kb
Host smart-bbe261a4-c23d-49cf-b233-ca872dfebfc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826739472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2826739472
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3284268508
Short name T323
Test name
Test status
Simulation time 7505904775 ps
CPU time 14.74 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:16:27 PM PDT 24
Peak memory 183144 kb
Host smart-125e3670-d1d3-42bd-ba43-431370676dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284268508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3284268508
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3820649407
Short name T439
Test name
Test status
Simulation time 1272230855244 ps
CPU time 573.92 seconds
Started Aug 12 05:16:15 PM PDT 24
Finished Aug 12 05:25:49 PM PDT 24
Peak memory 191308 kb
Host smart-44119cbf-9f51-45ea-81fc-abea12d751cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820649407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3820649407
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.2639112292
Short name T412
Test name
Test status
Simulation time 4342637565 ps
CPU time 12.35 seconds
Started Aug 12 05:16:26 PM PDT 24
Finished Aug 12 05:16:38 PM PDT 24
Peak memory 197856 kb
Host smart-a21d3c7c-e09d-4ce4-a416-6c0a68a0bca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639112292 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.2639112292
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2535172439
Short name T431
Test name
Test status
Simulation time 84440722212 ps
CPU time 125.15 seconds
Started Aug 12 05:16:16 PM PDT 24
Finished Aug 12 05:18:22 PM PDT 24
Peak memory 183120 kb
Host smart-23711de9-b868-458c-bd83-bcb3b8a6ee40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535172439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2535172439
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.1569853485
Short name T143
Test name
Test status
Simulation time 61808650119 ps
CPU time 206.41 seconds
Started Aug 12 05:16:28 PM PDT 24
Finished Aug 12 05:19:55 PM PDT 24
Peak memory 191332 kb
Host smart-59d54068-ebc6-4183-81d2-3eca34a1cb86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569853485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1569853485
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2403479918
Short name T397
Test name
Test status
Simulation time 77645852 ps
CPU time 0.57 seconds
Started Aug 12 05:16:15 PM PDT 24
Finished Aug 12 05:16:16 PM PDT 24
Peak memory 182792 kb
Host smart-1cc9d13f-05cb-48e0-9729-81c944bfeb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403479918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2403479918
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1628895797
Short name T188
Test name
Test status
Simulation time 415823223556 ps
CPU time 3125.36 seconds
Started Aug 12 05:16:20 PM PDT 24
Finished Aug 12 06:08:26 PM PDT 24
Peak memory 196220 kb
Host smart-a25fa2cb-956d-4dba-a501-a2376d50f69b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628895797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1628895797
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2792960591
Short name T253
Test name
Test status
Simulation time 293950471896 ps
CPU time 261.65 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 05:20:40 PM PDT 24
Peak memory 183148 kb
Host smart-dd48a97a-9a23-4b94-ac19-559ca6edc1be
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792960591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2792960591
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3650870652
Short name T449
Test name
Test status
Simulation time 84284276072 ps
CPU time 143.97 seconds
Started Aug 12 05:16:23 PM PDT 24
Finished Aug 12 05:18:47 PM PDT 24
Peak memory 183144 kb
Host smart-f0327233-a5fc-4a23-8d12-c85328c84263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650870652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3650870652
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1491791797
Short name T294
Test name
Test status
Simulation time 73005486814 ps
CPU time 35.63 seconds
Started Aug 12 05:16:29 PM PDT 24
Finished Aug 12 05:17:04 PM PDT 24
Peak memory 183168 kb
Host smart-22babf4d-2ef2-44ee-b9f6-57de84b18468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491791797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1491791797
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1659113755
Short name T388
Test name
Test status
Simulation time 20921864 ps
CPU time 0.56 seconds
Started Aug 12 05:16:26 PM PDT 24
Finished Aug 12 05:16:27 PM PDT 24
Peak memory 182796 kb
Host smart-c0f84ead-346f-491c-a7f2-1f8cf63e7d48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659113755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1659113755
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1638651813
Short name T168
Test name
Test status
Simulation time 126247619597 ps
CPU time 213.46 seconds
Started Aug 12 05:16:17 PM PDT 24
Finished Aug 12 05:19:51 PM PDT 24
Peak memory 183008 kb
Host smart-e4149565-66bc-45b4-9501-031193d6bbfa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638651813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1638651813
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_random.3631338246
Short name T307
Test name
Test status
Simulation time 2182921315462 ps
CPU time 608.81 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:26:21 PM PDT 24
Peak memory 191356 kb
Host smart-34302103-e348-492c-b144-7692d1d8999d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631338246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3631338246
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3468560665
Short name T137
Test name
Test status
Simulation time 37475232148 ps
CPU time 65.55 seconds
Started Aug 12 05:16:14 PM PDT 24
Finished Aug 12 05:17:20 PM PDT 24
Peak memory 183140 kb
Host smart-9347e4dd-5366-4a57-be26-220b1e49d621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468560665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3468560665
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2586965485
Short name T225
Test name
Test status
Simulation time 195733368425 ps
CPU time 331.87 seconds
Started Aug 12 05:16:24 PM PDT 24
Finished Aug 12 05:21:56 PM PDT 24
Peak memory 183044 kb
Host smart-cab54fa6-d88a-401f-98f6-7b12fa75fae7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586965485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2586965485
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.801692459
Short name T399
Test name
Test status
Simulation time 136259162271 ps
CPU time 107.9 seconds
Started Aug 12 05:16:39 PM PDT 24
Finished Aug 12 05:18:27 PM PDT 24
Peak memory 183100 kb
Host smart-fc75afbf-d1df-4cbc-b2cd-81048d87e0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801692459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.801692459
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2342240910
Short name T212
Test name
Test status
Simulation time 33878269067 ps
CPU time 61.86 seconds
Started Aug 12 05:16:27 PM PDT 24
Finished Aug 12 05:17:29 PM PDT 24
Peak memory 183144 kb
Host smart-2d4f86e6-290d-4fc0-bcad-8c1ccb4024be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342240910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2342240910
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2070891997
Short name T11
Test name
Test status
Simulation time 176112695259 ps
CPU time 45.42 seconds
Started Aug 12 05:16:21 PM PDT 24
Finished Aug 12 05:17:12 PM PDT 24
Peak memory 194476 kb
Host smart-e8cba3a7-d495-434e-9fef-e6d797e08c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070891997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2070891997
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.672021059
Short name T377
Test name
Test status
Simulation time 601557426828 ps
CPU time 244.66 seconds
Started Aug 12 05:16:29 PM PDT 24
Finished Aug 12 05:20:34 PM PDT 24
Peak memory 183108 kb
Host smart-85c8e480-dc8b-4505-9f63-9d72eaf0df34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672021059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.672021059
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2075585355
Short name T298
Test name
Test status
Simulation time 37485080497 ps
CPU time 8.25 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:16:21 PM PDT 24
Peak memory 191360 kb
Host smart-6a665608-c9c5-4478-8cb6-e93c8f21eceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075585355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2075585355
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.65002808
Short name T114
Test name
Test status
Simulation time 27659232076 ps
CPU time 16.39 seconds
Started Aug 12 05:16:40 PM PDT 24
Finished Aug 12 05:16:56 PM PDT 24
Peak memory 183132 kb
Host smart-2c9551ea-6e40-42f3-ab16-4cfd20c09dbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65002808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.rv_timer_cfg_update_on_fly.65002808
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2912831048
Short name T405
Test name
Test status
Simulation time 570138990631 ps
CPU time 206.62 seconds
Started Aug 12 05:16:37 PM PDT 24
Finished Aug 12 05:20:04 PM PDT 24
Peak memory 183068 kb
Host smart-36622753-a945-4315-898d-867b686433ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912831048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2912831048
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1192527981
Short name T333
Test name
Test status
Simulation time 72154900393 ps
CPU time 47.74 seconds
Started Aug 12 05:16:35 PM PDT 24
Finished Aug 12 05:17:23 PM PDT 24
Peak memory 183080 kb
Host smart-a25ae042-f11c-4a05-978c-0cf2fc6ca8d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192527981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1192527981
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3039522991
Short name T352
Test name
Test status
Simulation time 33730680016 ps
CPU time 63.27 seconds
Started Aug 12 05:16:20 PM PDT 24
Finished Aug 12 05:17:23 PM PDT 24
Peak memory 191256 kb
Host smart-f8a06966-72ae-45d2-a1c0-7714140c110c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039522991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3039522991
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3512637896
Short name T265
Test name
Test status
Simulation time 495825961362 ps
CPU time 295.03 seconds
Started Aug 12 05:16:15 PM PDT 24
Finished Aug 12 05:21:10 PM PDT 24
Peak memory 183148 kb
Host smart-1b0f0c91-5628-4cba-87cc-3f451623ef02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512637896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3512637896
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2499864131
Short name T358
Test name
Test status
Simulation time 1070085820 ps
CPU time 2.42 seconds
Started Aug 12 05:16:35 PM PDT 24
Finished Aug 12 05:16:38 PM PDT 24
Peak memory 182172 kb
Host smart-28feda7c-17eb-459b-b341-4453e367901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499864131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2499864131
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3414845111
Short name T337
Test name
Test status
Simulation time 29193392822 ps
CPU time 17.8 seconds
Started Aug 12 05:16:29 PM PDT 24
Finished Aug 12 05:16:47 PM PDT 24
Peak memory 183136 kb
Host smart-bd233499-4eb4-4ee3-a97c-dfe0c22f4a4f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414845111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3414845111
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3948214740
Short name T383
Test name
Test status
Simulation time 169658314092 ps
CPU time 141.77 seconds
Started Aug 12 05:16:16 PM PDT 24
Finished Aug 12 05:18:38 PM PDT 24
Peak memory 183124 kb
Host smart-2e7d1ade-1386-4376-803a-f45576ed86a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948214740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3948214740
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.127279691
Short name T416
Test name
Test status
Simulation time 152420661 ps
CPU time 0.99 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:16:13 PM PDT 24
Peak memory 182768 kb
Host smart-536a123a-0619-479a-8cf0-add5fefdfe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127279691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.127279691
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3617496782
Short name T36
Test name
Test status
Simulation time 1088090420990 ps
CPU time 346.5 seconds
Started Aug 12 05:16:29 PM PDT 24
Finished Aug 12 05:22:16 PM PDT 24
Peak memory 190496 kb
Host smart-52dd01bb-96cd-4635-a3c8-bbe82e2e80ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617496782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3617496782
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2480448622
Short name T444
Test name
Test status
Simulation time 12887779235 ps
CPU time 13.04 seconds
Started Aug 12 05:16:13 PM PDT 24
Finished Aug 12 05:16:26 PM PDT 24
Peak memory 183116 kb
Host smart-5d016953-cda7-418e-883d-b6f18bbcf93c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480448622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2480448622
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1663670022
Short name T363
Test name
Test status
Simulation time 210772084937 ps
CPU time 317.11 seconds
Started Aug 12 05:16:17 PM PDT 24
Finished Aug 12 05:21:34 PM PDT 24
Peak memory 183064 kb
Host smart-3e3c31e7-2cb0-4bfe-ab67-c4c59fbb393d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663670022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1663670022
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3805287826
Short name T183
Test name
Test status
Simulation time 90728201249 ps
CPU time 95.05 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:17:48 PM PDT 24
Peak memory 191312 kb
Host smart-f1cb3f14-23df-4e1a-a34c-8d7abf586efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805287826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3805287826
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.146701389
Short name T316
Test name
Test status
Simulation time 20767426226 ps
CPU time 8.26 seconds
Started Aug 12 05:16:03 PM PDT 24
Finished Aug 12 05:16:12 PM PDT 24
Peak memory 183108 kb
Host smart-75674682-1361-4a2f-a70a-d4cd457da035
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146701389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.146701389
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.471889187
Short name T28
Test name
Test status
Simulation time 150124856510 ps
CPU time 117.88 seconds
Started Aug 12 05:16:20 PM PDT 24
Finished Aug 12 05:18:18 PM PDT 24
Peak memory 183140 kb
Host smart-0283f6cd-3a59-4b33-b722-8804933e0154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471889187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.471889187
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.4007889435
Short name T343
Test name
Test status
Simulation time 27863480273 ps
CPU time 51.11 seconds
Started Aug 12 05:16:04 PM PDT 24
Finished Aug 12 05:16:55 PM PDT 24
Peak memory 193604 kb
Host smart-b082f266-4f59-45eb-b7c8-bbcbb562b32f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007889435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.4007889435
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2351152271
Short name T410
Test name
Test status
Simulation time 743994623 ps
CPU time 1.73 seconds
Started Aug 12 05:16:08 PM PDT 24
Finished Aug 12 05:16:10 PM PDT 24
Peak memory 182828 kb
Host smart-a2eddaca-d246-4cd0-b788-6622ecea09da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351152271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2351152271
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.719023617
Short name T18
Test name
Test status
Simulation time 343471889 ps
CPU time 0.9 seconds
Started Aug 12 05:16:04 PM PDT 24
Finished Aug 12 05:16:05 PM PDT 24
Peak memory 214640 kb
Host smart-3f81ed80-5f91-464d-8290-bc329dcd09f1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719023617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.719023617
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2234287571
Short name T224
Test name
Test status
Simulation time 1303328334176 ps
CPU time 3494.52 seconds
Started Aug 12 05:16:14 PM PDT 24
Finished Aug 12 06:14:29 PM PDT 24
Peak memory 191328 kb
Host smart-af74addf-a73c-4fdc-92f8-3a68bb6c61bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234287571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2234287571
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.472236786
Short name T347
Test name
Test status
Simulation time 619271753083 ps
CPU time 308.05 seconds
Started Aug 12 05:16:32 PM PDT 24
Finished Aug 12 05:21:40 PM PDT 24
Peak memory 183128 kb
Host smart-fcbac126-3c0e-4a13-9e71-80658835ca2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472236786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.472236786
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1501658810
Short name T359
Test name
Test status
Simulation time 463512484329 ps
CPU time 192.99 seconds
Started Aug 12 05:16:31 PM PDT 24
Finished Aug 12 05:19:44 PM PDT 24
Peak memory 182968 kb
Host smart-a16f2b21-4124-41f7-9dfb-21bd83550e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501658810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1501658810
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3526930436
Short name T153
Test name
Test status
Simulation time 86755726777 ps
CPU time 124.56 seconds
Started Aug 12 05:16:46 PM PDT 24
Finished Aug 12 05:18:51 PM PDT 24
Peak memory 183136 kb
Host smart-a46bc4df-f1a0-4cd6-90f7-399f793c469b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526930436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3526930436
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.4046469439
Short name T262
Test name
Test status
Simulation time 481067321613 ps
CPU time 492.8 seconds
Started Aug 12 05:16:32 PM PDT 24
Finished Aug 12 05:24:45 PM PDT 24
Peak memory 183120 kb
Host smart-1e490df5-d94a-4486-b0e8-c08d775a781d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046469439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.4046469439
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.840438964
Short name T202
Test name
Test status
Simulation time 24705464632 ps
CPU time 24.77 seconds
Started Aug 12 05:16:44 PM PDT 24
Finished Aug 12 05:17:08 PM PDT 24
Peak memory 183076 kb
Host smart-67eafdbc-5360-4cc6-b74a-4b5dab13d956
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840438964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.840438964
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.921839886
Short name T367
Test name
Test status
Simulation time 775378982557 ps
CPU time 270.75 seconds
Started Aug 12 05:16:28 PM PDT 24
Finished Aug 12 05:20:59 PM PDT 24
Peak memory 183144 kb
Host smart-6520d1b3-64e7-4813-bd02-207578e2f324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921839886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.921839886
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2907208792
Short name T257
Test name
Test status
Simulation time 544216676452 ps
CPU time 1104.04 seconds
Started Aug 12 05:16:37 PM PDT 24
Finished Aug 12 05:35:01 PM PDT 24
Peak memory 191328 kb
Host smart-da9217be-3218-4776-bf50-bd9047e0c979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907208792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2907208792
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1516351606
Short name T371
Test name
Test status
Simulation time 827515041 ps
CPU time 0.99 seconds
Started Aug 12 05:16:31 PM PDT 24
Finished Aug 12 05:16:37 PM PDT 24
Peak memory 182808 kb
Host smart-bbfc50e7-3a65-41d7-a3c7-1ce9dd23f331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516351606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1516351606
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3248864268
Short name T52
Test name
Test status
Simulation time 309739893703 ps
CPU time 188.06 seconds
Started Aug 12 05:16:35 PM PDT 24
Finished Aug 12 05:19:43 PM PDT 24
Peak memory 191324 kb
Host smart-25ac0532-9bb7-4063-b189-c36a62b25a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248864268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3248864268
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2178463419
Short name T43
Test name
Test status
Simulation time 1360114246 ps
CPU time 10.37 seconds
Started Aug 12 05:16:40 PM PDT 24
Finished Aug 12 05:16:51 PM PDT 24
Peak memory 193488 kb
Host smart-30dd2ce3-2685-4e15-982f-0d4977db4484
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178463419 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2178463419
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1589614441
Short name T373
Test name
Test status
Simulation time 107410980141 ps
CPU time 136.55 seconds
Started Aug 12 05:16:30 PM PDT 24
Finished Aug 12 05:18:47 PM PDT 24
Peak memory 183120 kb
Host smart-47b07222-7908-418a-9944-52d972ab1947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589614441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1589614441
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2740133716
Short name T331
Test name
Test status
Simulation time 26189919866 ps
CPU time 200.54 seconds
Started Aug 12 05:16:35 PM PDT 24
Finished Aug 12 05:19:56 PM PDT 24
Peak memory 183124 kb
Host smart-b598415f-4e78-4124-9e73-aa1f9f8d8fae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740133716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2740133716
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1005989655
Short name T27
Test name
Test status
Simulation time 147932219778 ps
CPU time 1013.94 seconds
Started Aug 12 05:16:35 PM PDT 24
Finished Aug 12 05:33:29 PM PDT 24
Peak memory 191320 kb
Host smart-ce32d1f9-ba6c-4207-8b84-7d3e36253a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005989655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1005989655
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3759073194
Short name T60
Test name
Test status
Simulation time 142986898124 ps
CPU time 199.65 seconds
Started Aug 12 05:16:26 PM PDT 24
Finished Aug 12 05:19:46 PM PDT 24
Peak memory 195144 kb
Host smart-4908579d-44e3-444c-b581-278e9004e145
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759073194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3759073194
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.1981756568
Short name T53
Test name
Test status
Simulation time 5969512605 ps
CPU time 43.32 seconds
Started Aug 12 05:16:35 PM PDT 24
Finished Aug 12 05:17:19 PM PDT 24
Peak memory 197796 kb
Host smart-39939a41-d1f7-45d1-9670-9a5e107d6729
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981756568 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.1981756568
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3711796607
Short name T5
Test name
Test status
Simulation time 38109571152 ps
CPU time 58.81 seconds
Started Aug 12 05:16:37 PM PDT 24
Finished Aug 12 05:17:36 PM PDT 24
Peak memory 183008 kb
Host smart-50a06268-c96e-4ad4-a678-5eafe4676dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711796607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3711796607
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.756263584
Short name T217
Test name
Test status
Simulation time 88127074991 ps
CPU time 79.76 seconds
Started Aug 12 05:16:34 PM PDT 24
Finished Aug 12 05:17:54 PM PDT 24
Peak memory 191324 kb
Host smart-2d7599f6-6bbf-44a2-a96f-481e72ee4a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756263584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.756263584
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.4268802363
Short name T413
Test name
Test status
Simulation time 959980426497 ps
CPU time 1409.71 seconds
Started Aug 12 05:16:36 PM PDT 24
Finished Aug 12 05:40:06 PM PDT 24
Peak memory 192848 kb
Host smart-b2030900-6451-4d2c-85c1-95c62036977f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268802363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.4268802363
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3791572391
Short name T414
Test name
Test status
Simulation time 586381003455 ps
CPU time 218.11 seconds
Started Aug 12 05:16:33 PM PDT 24
Finished Aug 12 05:20:12 PM PDT 24
Peak memory 182968 kb
Host smart-500b499f-69da-4b0d-83ca-697203b8a00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791572391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3791572391
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3646856030
Short name T191
Test name
Test status
Simulation time 2380669441096 ps
CPU time 551.61 seconds
Started Aug 12 05:16:39 PM PDT 24
Finished Aug 12 05:25:51 PM PDT 24
Peak memory 191364 kb
Host smart-d33ea2cb-3e7c-4063-9c07-0e77a38e55fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646856030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3646856030
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3732793829
Short name T315
Test name
Test status
Simulation time 260400098945 ps
CPU time 137.53 seconds
Started Aug 12 05:16:32 PM PDT 24
Finished Aug 12 05:18:50 PM PDT 24
Peak memory 191284 kb
Host smart-39c8d93e-4fd1-4be1-ad5f-5872980e481d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732793829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3732793829
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3841115500
Short name T226
Test name
Test status
Simulation time 2891846363893 ps
CPU time 1774.12 seconds
Started Aug 12 05:16:35 PM PDT 24
Finished Aug 12 05:46:10 PM PDT 24
Peak memory 191348 kb
Host smart-2f7d67ed-1a0b-40c4-9f85-be43c933ebe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841115500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3841115500
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.3999015361
Short name T415
Test name
Test status
Simulation time 7739811790 ps
CPU time 42.6 seconds
Started Aug 12 05:16:30 PM PDT 24
Finished Aug 12 05:17:13 PM PDT 24
Peak memory 197688 kb
Host smart-a141b967-3a61-4eba-89d5-704bf09a334c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999015361 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.3999015361
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2144438332
Short name T266
Test name
Test status
Simulation time 335197778576 ps
CPU time 507.92 seconds
Started Aug 12 05:16:30 PM PDT 24
Finished Aug 12 05:24:58 PM PDT 24
Peak memory 183124 kb
Host smart-6409bc95-f7a2-4120-8dcf-e0380ae37108
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144438332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2144438332
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1862282868
Short name T365
Test name
Test status
Simulation time 77866445440 ps
CPU time 113.3 seconds
Started Aug 12 05:16:43 PM PDT 24
Finished Aug 12 05:18:37 PM PDT 24
Peak memory 183112 kb
Host smart-c5dd263c-6a92-46ee-9e77-5ac3acbd3816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862282868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1862282868
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.684124464
Short name T238
Test name
Test status
Simulation time 283486524136 ps
CPU time 1073.54 seconds
Started Aug 12 05:16:39 PM PDT 24
Finished Aug 12 05:34:33 PM PDT 24
Peak memory 191396 kb
Host smart-7552594b-c3b2-45e8-8f2f-36ddf76071fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684124464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.684124464
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1835856411
Short name T423
Test name
Test status
Simulation time 88044842018 ps
CPU time 171.16 seconds
Started Aug 12 05:16:18 PM PDT 24
Finished Aug 12 05:19:09 PM PDT 24
Peak memory 193576 kb
Host smart-e4f64ca1-fbd9-4095-a9c7-0cc9e3479d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835856411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1835856411
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.162485083
Short name T133
Test name
Test status
Simulation time 422585203322 ps
CPU time 236.63 seconds
Started Aug 12 05:16:32 PM PDT 24
Finished Aug 12 05:20:29 PM PDT 24
Peak memory 183100 kb
Host smart-9ffd6964-8980-4644-b410-4e549fe96aea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162485083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.162485083
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2872712397
Short name T421
Test name
Test status
Simulation time 79924857063 ps
CPU time 122.13 seconds
Started Aug 12 05:16:50 PM PDT 24
Finished Aug 12 05:18:52 PM PDT 24
Peak memory 183160 kb
Host smart-e5650a97-627c-4d74-9418-85896bc94004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872712397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2872712397
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2336353529
Short name T49
Test name
Test status
Simulation time 102020126547 ps
CPU time 441.93 seconds
Started Aug 12 05:16:33 PM PDT 24
Finished Aug 12 05:23:55 PM PDT 24
Peak memory 193524 kb
Host smart-cdc2b580-16c6-4aa4-9567-9b0e39fcbe7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336353529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2336353529
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.624164047
Short name T368
Test name
Test status
Simulation time 159808719 ps
CPU time 0.59 seconds
Started Aug 12 05:16:25 PM PDT 24
Finished Aug 12 05:16:26 PM PDT 24
Peak memory 182852 kb
Host smart-111c826b-22ba-4aa8-829d-c9915f6224db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624164047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.624164047
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1137748907
Short name T104
Test name
Test status
Simulation time 147708750863 ps
CPU time 142.64 seconds
Started Aug 12 05:16:31 PM PDT 24
Finished Aug 12 05:18:54 PM PDT 24
Peak memory 183112 kb
Host smart-4c395415-f8d0-456b-bbdc-6396d4c68a07
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137748907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1137748907
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.4072712473
Short name T427
Test name
Test status
Simulation time 46925274190 ps
CPU time 78.3 seconds
Started Aug 12 05:16:34 PM PDT 24
Finished Aug 12 05:17:53 PM PDT 24
Peak memory 183136 kb
Host smart-c5e7954d-66b8-4fcd-b0f4-4a002122dc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072712473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.4072712473
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2800336939
Short name T441
Test name
Test status
Simulation time 210528251973 ps
CPU time 190.88 seconds
Started Aug 12 05:16:37 PM PDT 24
Finished Aug 12 05:19:48 PM PDT 24
Peak memory 191392 kb
Host smart-bdfc03b0-a42e-484e-bacd-17c875de9fdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800336939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2800336939
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2749187336
Short name T23
Test name
Test status
Simulation time 1176993203 ps
CPU time 1.16 seconds
Started Aug 12 05:16:28 PM PDT 24
Finished Aug 12 05:16:34 PM PDT 24
Peak memory 191984 kb
Host smart-4385301e-1b74-4eaf-813e-d6baf7149a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749187336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2749187336
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2092035554
Short name T364
Test name
Test status
Simulation time 188799444400 ps
CPU time 136.89 seconds
Started Aug 12 05:16:32 PM PDT 24
Finished Aug 12 05:18:49 PM PDT 24
Peak memory 183128 kb
Host smart-0b5f6792-c90e-4ff8-a60d-1b441c57408d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092035554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2092035554
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.209897756
Short name T37
Test name
Test status
Simulation time 2208807716 ps
CPU time 17.02 seconds
Started Aug 12 05:16:36 PM PDT 24
Finished Aug 12 05:16:53 PM PDT 24
Peak memory 197692 kb
Host smart-20fd712e-1232-4c27-9e17-763b0a6b920e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209897756 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.209897756
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3100745876
Short name T229
Test name
Test status
Simulation time 289892558349 ps
CPU time 158.88 seconds
Started Aug 12 05:16:36 PM PDT 24
Finished Aug 12 05:19:15 PM PDT 24
Peak memory 183128 kb
Host smart-cc2b8710-f5f1-4af0-9c96-ab32700c194a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100745876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3100745876
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1502110897
Short name T380
Test name
Test status
Simulation time 320011660066 ps
CPU time 229.69 seconds
Started Aug 12 05:16:33 PM PDT 24
Finished Aug 12 05:20:23 PM PDT 24
Peak memory 183140 kb
Host smart-1184d8ce-26b1-47f4-80d1-dbfa7395ec31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502110897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1502110897
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1317245549
Short name T401
Test name
Test status
Simulation time 25598946586 ps
CPU time 110.48 seconds
Started Aug 12 05:16:35 PM PDT 24
Finished Aug 12 05:18:26 PM PDT 24
Peak memory 183168 kb
Host smart-e82ac6c9-c47d-4162-90d1-668745fe996e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317245549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1317245549
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3502590581
Short name T409
Test name
Test status
Simulation time 253867935794 ps
CPU time 106.94 seconds
Started Aug 12 05:16:45 PM PDT 24
Finished Aug 12 05:18:32 PM PDT 24
Peak memory 183196 kb
Host smart-c7d6fdb3-ffd9-446b-a30e-4ff2bbf8f169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502590581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3502590581
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2166440344
Short name T450
Test name
Test status
Simulation time 125162210881 ps
CPU time 49.84 seconds
Started Aug 12 05:16:52 PM PDT 24
Finished Aug 12 05:17:42 PM PDT 24
Peak memory 183164 kb
Host smart-1e1cc271-dd55-4dce-8d4f-4df66e114d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166440344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2166440344
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3054064259
Short name T9
Test name
Test status
Simulation time 2113352946536 ps
CPU time 781.15 seconds
Started Aug 12 05:16:36 PM PDT 24
Finished Aug 12 05:29:37 PM PDT 24
Peak memory 183128 kb
Host smart-25783e97-11ae-4dcb-8031-2f1912e994df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054064259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3054064259
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1966556635
Short name T394
Test name
Test status
Simulation time 89552941215 ps
CPU time 141.95 seconds
Started Aug 12 05:16:49 PM PDT 24
Finished Aug 12 05:19:11 PM PDT 24
Peak memory 183144 kb
Host smart-a9ed3ba9-9d7f-48cd-b5e6-3586f7c4b0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966556635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1966556635
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.762397456
Short name T283
Test name
Test status
Simulation time 9179398021 ps
CPU time 6.23 seconds
Started Aug 12 05:16:35 PM PDT 24
Finished Aug 12 05:16:41 PM PDT 24
Peak memory 183116 kb
Host smart-047e182f-ac3f-4cc0-886a-a08bb1ed886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762397456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.762397456
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.1452082521
Short name T13
Test name
Test status
Simulation time 6766095528 ps
CPU time 12.98 seconds
Started Aug 12 05:16:34 PM PDT 24
Finished Aug 12 05:16:48 PM PDT 24
Peak memory 197828 kb
Host smart-a9bd45d8-ceb3-4d93-81d4-1351b098eae9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452082521 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.1452082521
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3157732695
Short name T147
Test name
Test status
Simulation time 1216561550183 ps
CPU time 1211.45 seconds
Started Aug 12 05:16:04 PM PDT 24
Finished Aug 12 05:36:15 PM PDT 24
Peak memory 183112 kb
Host smart-85598d0e-24a1-4ec3-b925-b88b6900d10d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157732695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3157732695
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3973069627
Short name T430
Test name
Test status
Simulation time 14781056015 ps
CPU time 24.57 seconds
Started Aug 12 05:16:17 PM PDT 24
Finished Aug 12 05:16:42 PM PDT 24
Peak memory 183144 kb
Host smart-2e6e738a-0fd8-4d70-877e-bffff992e6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973069627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3973069627
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3033066824
Short name T245
Test name
Test status
Simulation time 189886514658 ps
CPU time 480.41 seconds
Started Aug 12 05:16:06 PM PDT 24
Finished Aug 12 05:24:07 PM PDT 24
Peak memory 191312 kb
Host smart-4046362a-b932-4ff3-b0c4-d112016af967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033066824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3033066824
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2293146566
Short name T48
Test name
Test status
Simulation time 12543950817 ps
CPU time 20.51 seconds
Started Aug 12 05:16:11 PM PDT 24
Finished Aug 12 05:16:32 PM PDT 24
Peak memory 183100 kb
Host smart-293d96ef-0f01-4681-abd3-0d4dbc1eee0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293146566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2293146566
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2108567573
Short name T17
Test name
Test status
Simulation time 315114637 ps
CPU time 0.71 seconds
Started Aug 12 05:16:06 PM PDT 24
Finished Aug 12 05:16:07 PM PDT 24
Peak memory 213508 kb
Host smart-673c3c02-5707-4752-a5b4-bf446830c1a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108567573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2108567573
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.1944597571
Short name T15
Test name
Test status
Simulation time 5303629235 ps
CPU time 23.36 seconds
Started Aug 12 05:16:09 PM PDT 24
Finished Aug 12 05:16:32 PM PDT 24
Peak memory 197840 kb
Host smart-d1122c00-3f01-4547-8306-658fce40174b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944597571 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.1944597571
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1237452684
Short name T122
Test name
Test status
Simulation time 386315120384 ps
CPU time 217.73 seconds
Started Aug 12 05:16:39 PM PDT 24
Finished Aug 12 05:20:17 PM PDT 24
Peak memory 183116 kb
Host smart-b98e842e-8b32-4c8b-86af-60d958b5e8f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237452684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1237452684
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2288566535
Short name T361
Test name
Test status
Simulation time 61304990696 ps
CPU time 26.48 seconds
Started Aug 12 05:16:48 PM PDT 24
Finished Aug 12 05:17:14 PM PDT 24
Peak memory 183076 kb
Host smart-b083bb16-4661-4a3b-8a66-b4c534917f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288566535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2288566535
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1703834135
Short name T259
Test name
Test status
Simulation time 193091329695 ps
CPU time 146.47 seconds
Started Aug 12 05:16:41 PM PDT 24
Finished Aug 12 05:19:08 PM PDT 24
Peak memory 191312 kb
Host smart-47d2afd2-9da0-4674-9d57-3010f5c7bbc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703834135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1703834135
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2430117876
Short name T288
Test name
Test status
Simulation time 308105835766 ps
CPU time 77.78 seconds
Started Aug 12 05:16:47 PM PDT 24
Finished Aug 12 05:18:05 PM PDT 24
Peak memory 183280 kb
Host smart-2d1a8aa1-9cbc-4da7-894f-3f830a7b4ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430117876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2430117876
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.4240335344
Short name T41
Test name
Test status
Simulation time 3329148216 ps
CPU time 27.41 seconds
Started Aug 12 05:16:42 PM PDT 24
Finished Aug 12 05:17:10 PM PDT 24
Peak memory 197832 kb
Host smart-3067b1ef-d880-4f99-a11f-8b419395c3b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240335344 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.4240335344
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1045280528
Short name T231
Test name
Test status
Simulation time 419659289356 ps
CPU time 728.02 seconds
Started Aug 12 05:16:41 PM PDT 24
Finished Aug 12 05:28:54 PM PDT 24
Peak memory 183132 kb
Host smart-9da2a5cd-97b6-4b47-bf02-ff72003bafd3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045280528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1045280528
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3460046823
Short name T408
Test name
Test status
Simulation time 579914989086 ps
CPU time 241.04 seconds
Started Aug 12 05:16:47 PM PDT 24
Finished Aug 12 05:20:48 PM PDT 24
Peak memory 183148 kb
Host smart-84a8b146-cd61-4028-b7c2-7b54179d5cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460046823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3460046823
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2181910087
Short name T432
Test name
Test status
Simulation time 37442781687 ps
CPU time 61.01 seconds
Started Aug 12 05:16:45 PM PDT 24
Finished Aug 12 05:17:46 PM PDT 24
Peak memory 183160 kb
Host smart-27e18f1b-e483-400e-a85a-8bccaa4abd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181910087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2181910087
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1596823780
Short name T376
Test name
Test status
Simulation time 1011903596517 ps
CPU time 239.82 seconds
Started Aug 12 05:16:44 PM PDT 24
Finished Aug 12 05:20:44 PM PDT 24
Peak memory 183148 kb
Host smart-388375c7-8108-428b-8861-ae2736758d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596823780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1596823780
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3045113578
Short name T116
Test name
Test status
Simulation time 2225970255879 ps
CPU time 874.06 seconds
Started Aug 12 05:16:44 PM PDT 24
Finished Aug 12 05:31:19 PM PDT 24
Peak memory 183116 kb
Host smart-7f8554f8-2bb0-459e-a843-e7a23077b6d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045113578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3045113578
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_random.2287637343
Short name T346
Test name
Test status
Simulation time 120836198788 ps
CPU time 50.07 seconds
Started Aug 12 05:16:46 PM PDT 24
Finished Aug 12 05:17:36 PM PDT 24
Peak memory 183088 kb
Host smart-7b53118a-910a-49e1-9519-8452b59b58f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287637343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2287637343
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.152954349
Short name T426
Test name
Test status
Simulation time 49111775238 ps
CPU time 210.94 seconds
Started Aug 12 05:16:39 PM PDT 24
Finished Aug 12 05:20:10 PM PDT 24
Peak memory 183172 kb
Host smart-0eabf6f2-0045-41c9-8808-bd6eff80b8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152954349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.152954349
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.2102455128
Short name T38
Test name
Test status
Simulation time 1554746825 ps
CPU time 12.35 seconds
Started Aug 12 05:16:45 PM PDT 24
Finished Aug 12 05:16:58 PM PDT 24
Peak memory 197712 kb
Host smart-e317da47-4689-4187-ba40-b708abc24eda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102455128 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.2102455128
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1796390541
Short name T250
Test name
Test status
Simulation time 156367419435 ps
CPU time 140.57 seconds
Started Aug 12 05:16:37 PM PDT 24
Finished Aug 12 05:18:58 PM PDT 24
Peak memory 183140 kb
Host smart-72fb0d72-c1de-4298-a21f-5180112da7ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796390541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1796390541
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1368323610
Short name T418
Test name
Test status
Simulation time 86702643214 ps
CPU time 150.35 seconds
Started Aug 12 05:16:38 PM PDT 24
Finished Aug 12 05:19:09 PM PDT 24
Peak memory 183128 kb
Host smart-c1d3d1eb-d2d4-4db1-a0bf-0bd995c364cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368323610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1368323610
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2752799942
Short name T406
Test name
Test status
Simulation time 31521294869 ps
CPU time 51.14 seconds
Started Aug 12 05:16:38 PM PDT 24
Finished Aug 12 05:17:29 PM PDT 24
Peak memory 193488 kb
Host smart-4d50c01d-dd06-4aca-b9f2-6fa757d2f284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752799942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2752799942
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.405022331
Short name T50
Test name
Test status
Simulation time 1003905463 ps
CPU time 0.9 seconds
Started Aug 12 05:16:40 PM PDT 24
Finished Aug 12 05:16:41 PM PDT 24
Peak memory 191852 kb
Host smart-4162b56a-b0dc-4abf-b2ae-a9ab187afcbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405022331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.405022331
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2935664665
Short name T222
Test name
Test status
Simulation time 192280529384 ps
CPU time 256.7 seconds
Started Aug 12 05:16:45 PM PDT 24
Finished Aug 12 05:21:02 PM PDT 24
Peak memory 191308 kb
Host smart-f2849fa6-d379-4333-9f61-7272081dfe4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935664665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2935664665
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.573471905
Short name T39
Test name
Test status
Simulation time 1379063985 ps
CPU time 11.85 seconds
Started Aug 12 05:16:35 PM PDT 24
Finished Aug 12 05:16:47 PM PDT 24
Peak memory 197740 kb
Host smart-5ccb91b1-ccfa-4af5-9814-cc7e6583df7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573471905 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.573471905
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.347069992
Short name T419
Test name
Test status
Simulation time 35454157675 ps
CPU time 57.47 seconds
Started Aug 12 05:16:34 PM PDT 24
Finished Aug 12 05:17:32 PM PDT 24
Peak memory 183072 kb
Host smart-41c10d69-ff9c-459d-ba38-a2ed644fb9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347069992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.347069992
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3009861368
Short name T329
Test name
Test status
Simulation time 80092659489 ps
CPU time 137.54 seconds
Started Aug 12 05:16:41 PM PDT 24
Finished Aug 12 05:18:59 PM PDT 24
Peak memory 191340 kb
Host smart-0d5de04f-fd46-4e1e-8f4d-9c6185da3ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009861368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3009861368
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2144581213
Short name T330
Test name
Test status
Simulation time 40484204314 ps
CPU time 72.84 seconds
Started Aug 12 05:16:46 PM PDT 24
Finished Aug 12 05:17:58 PM PDT 24
Peak memory 191304 kb
Host smart-a62dc0c2-72d3-4776-8e5e-4a9635784a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144581213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2144581213
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1976385257
Short name T185
Test name
Test status
Simulation time 72408731070 ps
CPU time 115.52 seconds
Started Aug 12 05:16:42 PM PDT 24
Finished Aug 12 05:18:38 PM PDT 24
Peak memory 195012 kb
Host smart-d585b4a7-f912-4b8b-9a24-c959b3970206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976385257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1976385257
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.671518630
Short name T40
Test name
Test status
Simulation time 6258238523 ps
CPU time 72.14 seconds
Started Aug 12 05:16:32 PM PDT 24
Finished Aug 12 05:17:45 PM PDT 24
Peak memory 197768 kb
Host smart-825b2db1-9027-457d-9a2b-8443d0b69732
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671518630 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.671518630
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2110067711
Short name T244
Test name
Test status
Simulation time 520691291736 ps
CPU time 465.02 seconds
Started Aug 12 05:16:48 PM PDT 24
Finished Aug 12 05:24:34 PM PDT 24
Peak memory 183132 kb
Host smart-b2da8a2d-e603-4370-8ef4-2f3509f96c2a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110067711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2110067711
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1697217841
Short name T387
Test name
Test status
Simulation time 234017607785 ps
CPU time 168.96 seconds
Started Aug 12 05:16:49 PM PDT 24
Finished Aug 12 05:19:38 PM PDT 24
Peak memory 183140 kb
Host smart-44bad98d-75c6-40d0-acc6-7843ff0ce0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697217841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1697217841
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.496281275
Short name T132
Test name
Test status
Simulation time 71983963577 ps
CPU time 110.98 seconds
Started Aug 12 05:16:40 PM PDT 24
Finished Aug 12 05:18:31 PM PDT 24
Peak memory 194060 kb
Host smart-3a2609a7-2212-4477-b09f-ff74e5294a07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496281275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.496281275
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2034358908
Short name T311
Test name
Test status
Simulation time 75175923839 ps
CPU time 141.37 seconds
Started Aug 12 05:16:48 PM PDT 24
Finished Aug 12 05:19:09 PM PDT 24
Peak memory 191348 kb
Host smart-0caca2ac-fd73-4bf5-a797-b5d563c25c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034358908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2034358908
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2210205555
Short name T209
Test name
Test status
Simulation time 1380559110144 ps
CPU time 4247.35 seconds
Started Aug 12 05:16:47 PM PDT 24
Finished Aug 12 06:27:35 PM PDT 24
Peak memory 195808 kb
Host smart-ed910575-bb0f-410b-aad0-90700396dd1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210205555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2210205555
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.3223484468
Short name T443
Test name
Test status
Simulation time 2874225693 ps
CPU time 14.95 seconds
Started Aug 12 05:16:38 PM PDT 24
Finished Aug 12 05:16:53 PM PDT 24
Peak memory 197848 kb
Host smart-d3887873-1124-44e0-bd2c-dac8ea8ec579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223484468 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.3223484468
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2345408823
Short name T233
Test name
Test status
Simulation time 17275792294 ps
CPU time 26.62 seconds
Started Aug 12 05:16:44 PM PDT 24
Finished Aug 12 05:17:11 PM PDT 24
Peak memory 183124 kb
Host smart-570d33f7-7a5f-414e-8b76-fc996db5a939
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345408823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2345408823
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3158532707
Short name T386
Test name
Test status
Simulation time 32564104636 ps
CPU time 42.39 seconds
Started Aug 12 05:16:46 PM PDT 24
Finished Aug 12 05:17:29 PM PDT 24
Peak memory 183124 kb
Host smart-f9becf93-c163-4210-a341-de37267d7518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158532707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3158532707
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1241917735
Short name T295
Test name
Test status
Simulation time 127485045909 ps
CPU time 228.02 seconds
Started Aug 12 05:16:40 PM PDT 24
Finished Aug 12 05:20:28 PM PDT 24
Peak memory 191332 kb
Host smart-89703de3-5217-4f9a-8852-e4f9a12481d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241917735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1241917735
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.525219072
Short name T199
Test name
Test status
Simulation time 107153636067 ps
CPU time 501.9 seconds
Started Aug 12 05:16:45 PM PDT 24
Finished Aug 12 05:25:07 PM PDT 24
Peak memory 183152 kb
Host smart-e2b1b235-053c-478b-828f-48c7052fb46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525219072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.525219072
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2454878020
Short name T379
Test name
Test status
Simulation time 407632465915 ps
CPU time 293.54 seconds
Started Aug 12 05:17:01 PM PDT 24
Finished Aug 12 05:21:55 PM PDT 24
Peak memory 191292 kb
Host smart-f7c8a383-2bfd-412a-bfdb-df9b1dde767a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454878020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2454878020
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.869510458
Short name T275
Test name
Test status
Simulation time 430741260864 ps
CPU time 658.79 seconds
Started Aug 12 05:16:44 PM PDT 24
Finished Aug 12 05:27:43 PM PDT 24
Peak memory 183032 kb
Host smart-40f216c5-e21e-48f7-9320-ad780a06e68e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869510458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.869510458
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_random.2905740397
Short name T428
Test name
Test status
Simulation time 76173347966 ps
CPU time 143.56 seconds
Started Aug 12 05:16:46 PM PDT 24
Finished Aug 12 05:19:09 PM PDT 24
Peak memory 191380 kb
Host smart-239ce778-7bce-4aed-9c68-a32ce96d70fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905740397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2905740397
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1910596220
Short name T398
Test name
Test status
Simulation time 16066156682 ps
CPU time 22.55 seconds
Started Aug 12 05:16:48 PM PDT 24
Finished Aug 12 05:17:11 PM PDT 24
Peak memory 191280 kb
Host smart-5415cd42-3381-42c6-8707-c30925f8537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910596220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1910596220
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.687293382
Short name T435
Test name
Test status
Simulation time 63132481210 ps
CPU time 88.32 seconds
Started Aug 12 05:16:42 PM PDT 24
Finished Aug 12 05:18:10 PM PDT 24
Peak memory 182420 kb
Host smart-9425d994-9b28-4336-9305-f09958e2ebd1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687293382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.687293382
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1419356431
Short name T366
Test name
Test status
Simulation time 56226997633 ps
CPU time 75.79 seconds
Started Aug 12 05:16:44 PM PDT 24
Finished Aug 12 05:18:00 PM PDT 24
Peak memory 183136 kb
Host smart-22a71b40-dbb0-47a5-b3d7-7841e878908d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419356431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1419356431
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1350346974
Short name T198
Test name
Test status
Simulation time 634201035644 ps
CPU time 612.1 seconds
Started Aug 12 05:16:36 PM PDT 24
Finished Aug 12 05:26:48 PM PDT 24
Peak memory 191340 kb
Host smart-410e60f9-df90-4c3b-8501-444161cc990c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350346974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1350346974
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.374105376
Short name T392
Test name
Test status
Simulation time 5555815305 ps
CPU time 58.89 seconds
Started Aug 12 05:16:36 PM PDT 24
Finished Aug 12 05:17:35 PM PDT 24
Peak memory 183172 kb
Host smart-2facca00-0679-4891-91f7-c54e710dd2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374105376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.374105376
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.484974635
Short name T404
Test name
Test status
Simulation time 673196937041 ps
CPU time 446.73 seconds
Started Aug 12 05:16:55 PM PDT 24
Finished Aug 12 05:24:21 PM PDT 24
Peak memory 191336 kb
Host smart-5d716b84-f634-4e14-b5d7-92086b65a3cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484974635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
484974635
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.4206253126
Short name T173
Test name
Test status
Simulation time 123973915033 ps
CPU time 68.33 seconds
Started Aug 12 05:16:37 PM PDT 24
Finished Aug 12 05:17:46 PM PDT 24
Peak memory 183048 kb
Host smart-d055fbfd-6f54-44df-80c2-270551f138e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206253126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.4206253126
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.4028284759
Short name T362
Test name
Test status
Simulation time 428959243473 ps
CPU time 62.48 seconds
Started Aug 12 05:16:46 PM PDT 24
Finished Aug 12 05:17:49 PM PDT 24
Peak memory 183140 kb
Host smart-55129890-6d4b-4fa4-aaca-aefd37165026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028284759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.4028284759
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.398901828
Short name T357
Test name
Test status
Simulation time 26450946567 ps
CPU time 38.96 seconds
Started Aug 12 05:16:36 PM PDT 24
Finished Aug 12 05:17:16 PM PDT 24
Peak memory 183096 kb
Host smart-a90352aa-6012-46d4-b5df-ec4a5fa3a5b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398901828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
398901828
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.3606878950
Short name T55
Test name
Test status
Simulation time 1178892207 ps
CPU time 10.97 seconds
Started Aug 12 05:16:41 PM PDT 24
Finished Aug 12 05:16:53 PM PDT 24
Peak memory 193152 kb
Host smart-fb000daf-8a10-4b16-99da-620816eb56a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606878950 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.3606878950
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.120355385
Short name T448
Test name
Test status
Simulation time 36270117431 ps
CPU time 18.64 seconds
Started Aug 12 05:16:11 PM PDT 24
Finished Aug 12 05:16:30 PM PDT 24
Peak memory 183164 kb
Host smart-7bc0c41d-b01b-4125-9ada-3bf6009627b0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120355385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.120355385
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.4065552349
Short name T378
Test name
Test status
Simulation time 80534420738 ps
CPU time 115.52 seconds
Started Aug 12 05:16:06 PM PDT 24
Finished Aug 12 05:18:02 PM PDT 24
Peak memory 183136 kb
Host smart-c622f27a-c8fa-4533-b269-30394ce7d72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065552349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.4065552349
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.4109890286
Short name T286
Test name
Test status
Simulation time 246280540697 ps
CPU time 380.72 seconds
Started Aug 12 05:16:07 PM PDT 24
Finished Aug 12 05:22:28 PM PDT 24
Peak memory 196032 kb
Host smart-eb11fb28-44c2-405d-8059-0f415f54a77a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109890286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
4109890286
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/51.rv_timer_random.3825819855
Short name T148
Test name
Test status
Simulation time 837450765839 ps
CPU time 696.53 seconds
Started Aug 12 05:16:44 PM PDT 24
Finished Aug 12 05:28:21 PM PDT 24
Peak memory 191364 kb
Host smart-849c31b4-7aa4-4360-b4ff-3d81ec4bc102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825819855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3825819855
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3835656507
Short name T251
Test name
Test status
Simulation time 148226952502 ps
CPU time 462.34 seconds
Started Aug 12 05:16:51 PM PDT 24
Finished Aug 12 05:24:33 PM PDT 24
Peak memory 191372 kb
Host smart-f4ad0618-c6b4-460a-bf7c-b11c907e26ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835656507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3835656507
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2483079203
Short name T328
Test name
Test status
Simulation time 672230360671 ps
CPU time 1195.8 seconds
Started Aug 12 05:16:52 PM PDT 24
Finished Aug 12 05:36:48 PM PDT 24
Peak memory 191336 kb
Host smart-9b667058-b621-46f5-85ec-e504614e73ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483079203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2483079203
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.3860094806
Short name T124
Test name
Test status
Simulation time 586042214263 ps
CPU time 1145.15 seconds
Started Aug 12 05:16:50 PM PDT 24
Finished Aug 12 05:35:56 PM PDT 24
Peak memory 191388 kb
Host smart-abb6bb4b-5679-48c0-a801-e5a62348401c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860094806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3860094806
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1000486174
Short name T45
Test name
Test status
Simulation time 1817945668949 ps
CPU time 316.31 seconds
Started Aug 12 05:16:47 PM PDT 24
Finished Aug 12 05:22:03 PM PDT 24
Peak memory 191356 kb
Host smart-377527e8-cf72-42d2-9ce1-607a45fcb64c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000486174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1000486174
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2459205978
Short name T300
Test name
Test status
Simulation time 240853388963 ps
CPU time 789.09 seconds
Started Aug 12 05:16:53 PM PDT 24
Finished Aug 12 05:30:02 PM PDT 24
Peak memory 191344 kb
Host smart-416611db-6ce8-44a5-9d15-d8a5315ab28d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459205978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2459205978
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3755575264
Short name T249
Test name
Test status
Simulation time 223080144731 ps
CPU time 175.01 seconds
Started Aug 12 05:16:50 PM PDT 24
Finished Aug 12 05:19:45 PM PDT 24
Peak memory 191144 kb
Host smart-97780681-f49e-498d-9d91-8322b2b32e61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755575264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3755575264
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.625468375
Short name T10
Test name
Test status
Simulation time 7346075157 ps
CPU time 11.11 seconds
Started Aug 12 05:16:11 PM PDT 24
Finished Aug 12 05:16:22 PM PDT 24
Peak memory 183128 kb
Host smart-242befed-88c1-4f85-a4ea-30e60b93e3f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625468375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.625468375
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.4276771040
Short name T403
Test name
Test status
Simulation time 460177653182 ps
CPU time 211.21 seconds
Started Aug 12 05:16:08 PM PDT 24
Finished Aug 12 05:19:39 PM PDT 24
Peak memory 183128 kb
Host smart-e0e05e26-1dc5-4ddc-83ec-c94f9d9d0e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276771040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.4276771040
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1016899900
Short name T332
Test name
Test status
Simulation time 43945933710 ps
CPU time 72.81 seconds
Started Aug 12 05:16:11 PM PDT 24
Finished Aug 12 05:17:24 PM PDT 24
Peak memory 191356 kb
Host smart-f5771a7a-e34d-4414-baba-3272ebf60f69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016899900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1016899900
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1140695390
Short name T382
Test name
Test status
Simulation time 265556277 ps
CPU time 1.2 seconds
Started Aug 12 05:16:23 PM PDT 24
Finished Aug 12 05:16:24 PM PDT 24
Peak memory 191232 kb
Host smart-15e5a70b-e289-48a4-8d7e-3e592770174e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140695390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1140695390
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.2589813863
Short name T54
Test name
Test status
Simulation time 7707647738 ps
CPU time 15.34 seconds
Started Aug 12 05:16:07 PM PDT 24
Finished Aug 12 05:16:23 PM PDT 24
Peak memory 197856 kb
Host smart-9e647e5b-0840-4018-8e0f-57b762002984
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589813863 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.2589813863
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.2992573213
Short name T256
Test name
Test status
Simulation time 2302456209721 ps
CPU time 519.32 seconds
Started Aug 12 05:16:43 PM PDT 24
Finished Aug 12 05:25:22 PM PDT 24
Peak memory 191344 kb
Host smart-adf8f8e0-2bf2-4f83-a41f-289e6ed0985c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992573213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2992573213
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.387508676
Short name T445
Test name
Test status
Simulation time 18491222041 ps
CPU time 33.36 seconds
Started Aug 12 05:16:36 PM PDT 24
Finished Aug 12 05:17:10 PM PDT 24
Peak memory 183152 kb
Host smart-2411a0c6-3f79-49e8-b125-676b9d241aa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387508676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.387508676
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1030758010
Short name T252
Test name
Test status
Simulation time 121511657673 ps
CPU time 136.15 seconds
Started Aug 12 05:16:46 PM PDT 24
Finished Aug 12 05:19:02 PM PDT 24
Peak memory 191292 kb
Host smart-3959e75b-f2b2-433f-8e03-790627c4defa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030758010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1030758010
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2902857716
Short name T312
Test name
Test status
Simulation time 22113328626 ps
CPU time 47.64 seconds
Started Aug 12 05:16:56 PM PDT 24
Finished Aug 12 05:17:44 PM PDT 24
Peak memory 195076 kb
Host smart-952afa18-e1a6-407f-a1e6-9bfa5fd85dd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902857716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2902857716
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.648612825
Short name T239
Test name
Test status
Simulation time 257153432673 ps
CPU time 663.11 seconds
Started Aug 12 05:16:50 PM PDT 24
Finished Aug 12 05:27:54 PM PDT 24
Peak memory 191388 kb
Host smart-638d6693-f658-43f9-a179-42f1c2d4f765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648612825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.648612825
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.874851173
Short name T248
Test name
Test status
Simulation time 748426058911 ps
CPU time 1290.89 seconds
Started Aug 12 05:16:50 PM PDT 24
Finished Aug 12 05:38:22 PM PDT 24
Peak memory 191272 kb
Host smart-0470d94a-d3b9-49f5-9784-cedfee5ea404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874851173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.874851173
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.4289311943
Short name T184
Test name
Test status
Simulation time 341755636716 ps
CPU time 303.7 seconds
Started Aug 12 05:16:44 PM PDT 24
Finished Aug 12 05:21:48 PM PDT 24
Peak memory 191300 kb
Host smart-e8f58b6b-d593-4d0b-97cf-82cea8262e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289311943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.4289311943
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2622886916
Short name T176
Test name
Test status
Simulation time 489511515852 ps
CPU time 782.33 seconds
Started Aug 12 05:17:03 PM PDT 24
Finished Aug 12 05:30:05 PM PDT 24
Peak memory 191344 kb
Host smart-e1a1f2cf-211f-4f14-a432-1b06113e6b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622886916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2622886916
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3896662326
Short name T261
Test name
Test status
Simulation time 140701087076 ps
CPU time 1189.53 seconds
Started Aug 12 05:17:01 PM PDT 24
Finished Aug 12 05:36:51 PM PDT 24
Peak memory 191336 kb
Host smart-31a0b471-eb53-4835-86b1-d20d5bc90f66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896662326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3896662326
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3645011615
Short name T270
Test name
Test status
Simulation time 728741642750 ps
CPU time 296.74 seconds
Started Aug 12 05:16:56 PM PDT 24
Finished Aug 12 05:21:53 PM PDT 24
Peak memory 191284 kb
Host smart-c54a788c-8973-430a-ad6e-86c2b57727de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645011615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3645011615
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3723261590
Short name T119
Test name
Test status
Simulation time 36566886023 ps
CPU time 21.01 seconds
Started Aug 12 05:16:04 PM PDT 24
Finished Aug 12 05:16:25 PM PDT 24
Peak memory 183132 kb
Host smart-4df04a62-cfcc-4f99-ab64-b15c637b98c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723261590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3723261590
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3142628501
Short name T375
Test name
Test status
Simulation time 118102956814 ps
CPU time 110.72 seconds
Started Aug 12 05:16:06 PM PDT 24
Finished Aug 12 05:17:57 PM PDT 24
Peak memory 183148 kb
Host smart-73a70a62-ed0b-4543-825b-6e961dda8591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142628501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3142628501
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2477715195
Short name T420
Test name
Test status
Simulation time 96443542 ps
CPU time 1 seconds
Started Aug 12 05:16:07 PM PDT 24
Finished Aug 12 05:16:08 PM PDT 24
Peak memory 182948 kb
Host smart-39d80150-f2ff-41ba-8bcf-390f4de77698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477715195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2477715195
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1846954530
Short name T44
Test name
Test status
Simulation time 1902281295343 ps
CPU time 772.88 seconds
Started Aug 12 05:16:17 PM PDT 24
Finished Aug 12 05:29:10 PM PDT 24
Peak memory 191284 kb
Host smart-0d5b4203-db80-4d32-b2fd-1549960a16f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846954530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1846954530
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.3063640942
Short name T319
Test name
Test status
Simulation time 20508575846 ps
CPU time 35.74 seconds
Started Aug 12 05:16:49 PM PDT 24
Finished Aug 12 05:17:25 PM PDT 24
Peak memory 191272 kb
Host smart-8b98fdef-b51c-4553-86fa-5385604f9244
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063640942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3063640942
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1334929955
Short name T230
Test name
Test status
Simulation time 82181862947 ps
CPU time 750.35 seconds
Started Aug 12 05:17:02 PM PDT 24
Finished Aug 12 05:29:33 PM PDT 24
Peak memory 191248 kb
Host smart-14697b39-a23d-4177-b781-1d32e5c5d281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334929955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1334929955
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.72618006
Short name T297
Test name
Test status
Simulation time 366655832345 ps
CPU time 308.04 seconds
Started Aug 12 05:17:04 PM PDT 24
Finished Aug 12 05:22:13 PM PDT 24
Peak memory 191288 kb
Host smart-ac1c9a46-be67-4839-8536-3a2c78d834ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72618006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.72618006
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2862850330
Short name T127
Test name
Test status
Simulation time 305372140181 ps
CPU time 320.87 seconds
Started Aug 12 05:16:48 PM PDT 24
Finished Aug 12 05:22:09 PM PDT 24
Peak memory 191368 kb
Host smart-d0f84216-076f-408e-b0ea-10bb02d3fb27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862850330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2862850330
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1938442344
Short name T163
Test name
Test status
Simulation time 106186865949 ps
CPU time 79.5 seconds
Started Aug 12 05:16:48 PM PDT 24
Finished Aug 12 05:18:08 PM PDT 24
Peak memory 191352 kb
Host smart-a74730ea-2408-45b7-bf35-6a021791e438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938442344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1938442344
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.4188138431
Short name T434
Test name
Test status
Simulation time 174341051446 ps
CPU time 107.41 seconds
Started Aug 12 05:16:55 PM PDT 24
Finished Aug 12 05:18:42 PM PDT 24
Peak memory 191332 kb
Host smart-7a0617e7-c46f-4337-b625-a37bc9c415a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188138431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4188138431
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1251698895
Short name T178
Test name
Test status
Simulation time 15495593260 ps
CPU time 28.04 seconds
Started Aug 12 05:16:55 PM PDT 24
Finished Aug 12 05:17:23 PM PDT 24
Peak memory 191344 kb
Host smart-09e86165-12ff-4625-a78b-61f15cb0cd29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251698895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1251698895
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3019706211
Short name T313
Test name
Test status
Simulation time 570845814454 ps
CPU time 212.17 seconds
Started Aug 12 05:16:51 PM PDT 24
Finished Aug 12 05:20:23 PM PDT 24
Peak memory 191388 kb
Host smart-7fe92e92-c596-41ec-a7d9-211f58a3b197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019706211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3019706211
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1821315885
Short name T220
Test name
Test status
Simulation time 167481239561 ps
CPU time 548.13 seconds
Started Aug 12 05:16:53 PM PDT 24
Finished Aug 12 05:26:02 PM PDT 24
Peak memory 191308 kb
Host smart-8577dea7-35f1-4972-978c-074e53ab9279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821315885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1821315885
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.806507218
Short name T317
Test name
Test status
Simulation time 277262284339 ps
CPU time 472.07 seconds
Started Aug 12 05:16:12 PM PDT 24
Finished Aug 12 05:24:05 PM PDT 24
Peak memory 183040 kb
Host smart-3ef1761f-833b-4a42-b5e2-9bae517937a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806507218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.806507218
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3460591119
Short name T396
Test name
Test status
Simulation time 249136671727 ps
CPU time 207.62 seconds
Started Aug 12 05:16:06 PM PDT 24
Finished Aug 12 05:19:34 PM PDT 24
Peak memory 183140 kb
Host smart-ce005085-8fd9-43e7-9f5e-b038f25d30c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460591119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3460591119
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1917354068
Short name T451
Test name
Test status
Simulation time 749558408 ps
CPU time 1.06 seconds
Started Aug 12 05:16:04 PM PDT 24
Finished Aug 12 05:16:06 PM PDT 24
Peak memory 193592 kb
Host smart-952fc356-1840-4116-bcf9-ddcfbe50f1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917354068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1917354068
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.2942990317
Short name T258
Test name
Test status
Simulation time 202222942430 ps
CPU time 405.46 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:23:45 PM PDT 24
Peak memory 191388 kb
Host smart-667ee20f-f4dc-4f04-ad16-6212fc209234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942990317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2942990317
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.869286019
Short name T218
Test name
Test status
Simulation time 79058199910 ps
CPU time 1732.04 seconds
Started Aug 12 05:17:06 PM PDT 24
Finished Aug 12 05:45:58 PM PDT 24
Peak memory 191312 kb
Host smart-c4b903b3-cb55-4b0d-8523-d67c4d869541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869286019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.869286019
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2892378993
Short name T8
Test name
Test status
Simulation time 87463694479 ps
CPU time 1411.66 seconds
Started Aug 12 05:16:45 PM PDT 24
Finished Aug 12 05:40:17 PM PDT 24
Peak memory 191388 kb
Host smart-362c214e-24e6-4724-b961-a7c56bc52836
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892378993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2892378993
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3232767211
Short name T118
Test name
Test status
Simulation time 162469579697 ps
CPU time 92.59 seconds
Started Aug 12 05:16:44 PM PDT 24
Finished Aug 12 05:18:16 PM PDT 24
Peak memory 183148 kb
Host smart-8a6bbb73-aa15-49be-950a-569d669c4a07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232767211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3232767211
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3836163725
Short name T301
Test name
Test status
Simulation time 336270990877 ps
CPU time 537.56 seconds
Started Aug 12 05:16:48 PM PDT 24
Finished Aug 12 05:25:46 PM PDT 24
Peak memory 191484 kb
Host smart-fb2deb24-e531-4c13-8f67-f30a50b9e510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836163725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3836163725
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3126191677
Short name T284
Test name
Test status
Simulation time 679062318904 ps
CPU time 1087.94 seconds
Started Aug 12 05:16:54 PM PDT 24
Finished Aug 12 05:35:02 PM PDT 24
Peak memory 191356 kb
Host smart-1a0960cf-c55e-4aa2-9f8d-e9a57484059e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126191677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3126191677
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4282694550
Short name T299
Test name
Test status
Simulation time 305851609603 ps
CPU time 1774.04 seconds
Started Aug 12 05:16:43 PM PDT 24
Finished Aug 12 05:46:17 PM PDT 24
Peak memory 191340 kb
Host smart-798502fa-bbc4-4789-a9ca-a346021e5fc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282694550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4282694550
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.427556078
Short name T327
Test name
Test status
Simulation time 17937234886 ps
CPU time 105.78 seconds
Started Aug 12 05:16:57 PM PDT 24
Finished Aug 12 05:18:43 PM PDT 24
Peak memory 191352 kb
Host smart-a8016154-9b91-400d-94b3-df299859a68d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427556078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.427556078
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1494091978
Short name T322
Test name
Test status
Simulation time 256696527734 ps
CPU time 559.95 seconds
Started Aug 12 05:16:54 PM PDT 24
Finished Aug 12 05:26:14 PM PDT 24
Peak memory 191324 kb
Host smart-05e60f92-aab1-4819-9f0c-a5e82a9fcd9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494091978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1494091978
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2632334813
Short name T255
Test name
Test status
Simulation time 44545764709 ps
CPU time 68.07 seconds
Started Aug 12 05:16:49 PM PDT 24
Finished Aug 12 05:17:58 PM PDT 24
Peak memory 191364 kb
Host smart-9657d91b-6502-4c29-bfa5-94e5312f7903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632334813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2632334813
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2511167522
Short name T440
Test name
Test status
Simulation time 67797071928 ps
CPU time 86.35 seconds
Started Aug 12 05:16:08 PM PDT 24
Finished Aug 12 05:17:34 PM PDT 24
Peak memory 183164 kb
Host smart-e391d55f-63e1-47d3-a8e5-70b9d0e435b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511167522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2511167522
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.799272146
Short name T3
Test name
Test status
Simulation time 358690462129 ps
CPU time 520.11 seconds
Started Aug 12 05:15:59 PM PDT 24
Finished Aug 12 05:24:39 PM PDT 24
Peak memory 191324 kb
Host smart-a263eefd-57c1-4841-afb7-228dfe2f57f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799272146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.799272146
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.528389278
Short name T335
Test name
Test status
Simulation time 766437133114 ps
CPU time 410.61 seconds
Started Aug 12 05:16:14 PM PDT 24
Finished Aug 12 05:23:05 PM PDT 24
Peak memory 194920 kb
Host smart-bd78027a-1ed0-4388-980e-72c6404cce79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528389278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.528389278
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3147976571
Short name T370
Test name
Test status
Simulation time 484859051913 ps
CPU time 356.71 seconds
Started Aug 12 05:16:08 PM PDT 24
Finished Aug 12 05:22:05 PM PDT 24
Peak memory 191348 kb
Host smart-510ce60a-59f3-4198-aafa-e7faacd2e88b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147976571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3147976571
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.1818496436
Short name T51
Test name
Test status
Simulation time 161878632316 ps
CPU time 157.22 seconds
Started Aug 12 05:17:01 PM PDT 24
Finished Aug 12 05:19:38 PM PDT 24
Peak memory 191324 kb
Host smart-cd330818-bbbc-45f4-b3a1-ae2e0aa055d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818496436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1818496436
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3479161545
Short name T167
Test name
Test status
Simulation time 165762552332 ps
CPU time 1092.06 seconds
Started Aug 12 05:17:04 PM PDT 24
Finished Aug 12 05:35:16 PM PDT 24
Peak memory 191332 kb
Host smart-dfd6b1ce-0a55-4017-b285-7a6e65039cb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479161545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3479161545
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3152035919
Short name T90
Test name
Test status
Simulation time 381967198705 ps
CPU time 590.35 seconds
Started Aug 12 05:16:37 PM PDT 24
Finished Aug 12 05:26:28 PM PDT 24
Peak memory 191244 kb
Host smart-c5a32b77-f7c5-46ac-800f-6f30e3c78b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152035919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3152035919
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2680589073
Short name T235
Test name
Test status
Simulation time 72706573757 ps
CPU time 132.98 seconds
Started Aug 12 05:17:00 PM PDT 24
Finished Aug 12 05:19:14 PM PDT 24
Peak memory 191368 kb
Host smart-0a9cde09-92d0-4cfc-b5b5-8aca793aac1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680589073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2680589073
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.4094626803
Short name T26
Test name
Test status
Simulation time 8373127191 ps
CPU time 4.33 seconds
Started Aug 12 05:16:50 PM PDT 24
Finished Aug 12 05:16:54 PM PDT 24
Peak memory 183204 kb
Host smart-d1c6e580-9a95-4507-a4a3-c4f3e34aff7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094626803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.4094626803
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3524747455
Short name T97
Test name
Test status
Simulation time 89351568631 ps
CPU time 157.81 seconds
Started Aug 12 05:16:52 PM PDT 24
Finished Aug 12 05:19:30 PM PDT 24
Peak memory 191308 kb
Host smart-e8f2c212-0330-4a37-a658-2746205c45c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524747455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3524747455
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2909085746
Short name T237
Test name
Test status
Simulation time 92883200555 ps
CPU time 1633.76 seconds
Started Aug 12 05:16:46 PM PDT 24
Finished Aug 12 05:44:00 PM PDT 24
Peak memory 191368 kb
Host smart-c8476807-ccdb-4faa-9096-b53e87774731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909085746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2909085746
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.438181207
Short name T325
Test name
Test status
Simulation time 22448069706 ps
CPU time 20.18 seconds
Started Aug 12 05:16:51 PM PDT 24
Finished Aug 12 05:17:12 PM PDT 24
Peak memory 183168 kb
Host smart-770e9af6-2b95-4908-b6ed-f45113b8acbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438181207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.438181207
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3996391435
Short name T336
Test name
Test status
Simulation time 74053036350 ps
CPU time 33.65 seconds
Started Aug 12 05:16:42 PM PDT 24
Finished Aug 12 05:17:16 PM PDT 24
Peak memory 183156 kb
Host smart-39f12907-96ef-4313-a83c-8bc7a2ca924c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996391435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3996391435
Directory /workspace/99.rv_timer_random/latest
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