Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 583
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T512 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.838970141 Aug 13 05:21:52 PM PDT 24 Aug 13 05:21:54 PM PDT 24 117277791 ps
T513 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2843350794 Aug 13 05:21:34 PM PDT 24 Aug 13 05:21:36 PM PDT 24 115679176 ps
T514 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.756342106 Aug 13 05:21:52 PM PDT 24 Aug 13 05:21:53 PM PDT 24 22683906 ps
T515 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.700558448 Aug 13 05:21:51 PM PDT 24 Aug 13 05:21:52 PM PDT 24 20256632 ps
T516 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2247923682 Aug 13 05:21:41 PM PDT 24 Aug 13 05:21:42 PM PDT 24 17760191 ps
T517 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1261673753 Aug 13 05:21:49 PM PDT 24 Aug 13 05:21:50 PM PDT 24 134159133 ps
T518 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.764619141 Aug 13 05:21:54 PM PDT 24 Aug 13 05:21:55 PM PDT 24 14481731 ps
T519 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2617938498 Aug 13 05:21:50 PM PDT 24 Aug 13 05:21:52 PM PDT 24 57919618 ps
T520 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.368585177 Aug 13 05:22:02 PM PDT 24 Aug 13 05:22:03 PM PDT 24 79061187 ps
T521 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1708418178 Aug 13 05:21:46 PM PDT 24 Aug 13 05:21:47 PM PDT 24 292806834 ps
T522 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3610768759 Aug 13 05:21:50 PM PDT 24 Aug 13 05:21:50 PM PDT 24 18572803 ps
T523 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.67544156 Aug 13 05:22:20 PM PDT 24 Aug 13 05:22:20 PM PDT 24 29664796 ps
T524 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.747083522 Aug 13 05:21:42 PM PDT 24 Aug 13 05:21:43 PM PDT 24 103877828 ps
T525 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.349559280 Aug 13 05:21:21 PM PDT 24 Aug 13 05:21:21 PM PDT 24 23407894 ps
T526 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.901640886 Aug 13 05:21:44 PM PDT 24 Aug 13 05:21:45 PM PDT 24 15492812 ps
T527 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1565548894 Aug 13 05:21:51 PM PDT 24 Aug 13 05:21:52 PM PDT 24 86454830 ps
T79 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.585117144 Aug 13 05:21:45 PM PDT 24 Aug 13 05:21:46 PM PDT 24 319627166 ps
T67 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.142732715 Aug 13 05:21:50 PM PDT 24 Aug 13 05:21:50 PM PDT 24 15767743 ps
T528 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3314661078 Aug 13 05:21:42 PM PDT 24 Aug 13 05:21:43 PM PDT 24 110705146 ps
T81 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1005529451 Aug 13 05:21:43 PM PDT 24 Aug 13 05:21:45 PM PDT 24 105900365 ps
T70 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4101396168 Aug 13 05:21:31 PM PDT 24 Aug 13 05:21:34 PM PDT 24 63128274 ps
T529 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.4117637607 Aug 13 05:21:44 PM PDT 24 Aug 13 05:21:45 PM PDT 24 328766487 ps
T68 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1291466077 Aug 13 05:21:31 PM PDT 24 Aug 13 05:21:32 PM PDT 24 110775844 ps
T530 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1143764963 Aug 13 05:21:36 PM PDT 24 Aug 13 05:21:37 PM PDT 24 16814015 ps
T531 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3630693132 Aug 13 05:21:50 PM PDT 24 Aug 13 05:21:50 PM PDT 24 23426411 ps
T532 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3186082233 Aug 13 05:21:30 PM PDT 24 Aug 13 05:21:31 PM PDT 24 147870696 ps
T533 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.597955605 Aug 13 05:21:27 PM PDT 24 Aug 13 05:21:28 PM PDT 24 37921883 ps
T534 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2850897653 Aug 13 05:21:36 PM PDT 24 Aug 13 05:21:40 PM PDT 24 833416309 ps
T535 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3016232271 Aug 13 05:21:43 PM PDT 24 Aug 13 05:21:44 PM PDT 24 15448938 ps
T536 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3166222681 Aug 13 05:21:43 PM PDT 24 Aug 13 05:21:44 PM PDT 24 14205506 ps
T537 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3460274485 Aug 13 05:21:56 PM PDT 24 Aug 13 05:21:56 PM PDT 24 18955677 ps
T538 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2929663009 Aug 13 05:22:05 PM PDT 24 Aug 13 05:22:06 PM PDT 24 11250870 ps
T539 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2231079240 Aug 13 05:22:01 PM PDT 24 Aug 13 05:22:02 PM PDT 24 16110458 ps
T540 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.4244279341 Aug 13 05:21:54 PM PDT 24 Aug 13 05:21:55 PM PDT 24 17512252 ps
T541 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2472619046 Aug 13 05:22:05 PM PDT 24 Aug 13 05:22:06 PM PDT 24 18055668 ps
T542 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1112481661 Aug 13 05:21:58 PM PDT 24 Aug 13 05:22:01 PM PDT 24 257502200 ps
T69 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1296788053 Aug 13 05:21:54 PM PDT 24 Aug 13 05:21:55 PM PDT 24 62493057 ps
T543 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.4185846187 Aug 13 05:21:48 PM PDT 24 Aug 13 05:21:48 PM PDT 24 13204949 ps
T544 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.333195860 Aug 13 05:21:39 PM PDT 24 Aug 13 05:21:40 PM PDT 24 18880444 ps
T545 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.114233346 Aug 13 05:21:50 PM PDT 24 Aug 13 05:21:51 PM PDT 24 322251485 ps
T82 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.439061889 Aug 13 05:21:27 PM PDT 24 Aug 13 05:21:29 PM PDT 24 390392799 ps
T546 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1717136509 Aug 13 05:21:36 PM PDT 24 Aug 13 05:21:37 PM PDT 24 14021664 ps
T547 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.233041116 Aug 13 05:21:47 PM PDT 24 Aug 13 05:21:50 PM PDT 24 170478063 ps
T548 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2422000147 Aug 13 05:21:54 PM PDT 24 Aug 13 05:21:55 PM PDT 24 53250987 ps
T549 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.123844336 Aug 13 05:21:36 PM PDT 24 Aug 13 05:21:38 PM PDT 24 20386870 ps
T550 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2976576121 Aug 13 05:22:00 PM PDT 24 Aug 13 05:22:06 PM PDT 24 55499428 ps
T551 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1764179174 Aug 13 05:21:52 PM PDT 24 Aug 13 05:21:55 PM PDT 24 938609807 ps
T71 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2013666869 Aug 13 05:21:32 PM PDT 24 Aug 13 05:21:33 PM PDT 24 41291752 ps
T552 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2521459546 Aug 13 05:21:42 PM PDT 24 Aug 13 05:21:43 PM PDT 24 17566056 ps
T553 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2199304965 Aug 13 05:22:08 PM PDT 24 Aug 13 05:22:09 PM PDT 24 14425868 ps
T554 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2626038908 Aug 13 05:21:59 PM PDT 24 Aug 13 05:22:00 PM PDT 24 15809059 ps
T555 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.873254207 Aug 13 05:22:07 PM PDT 24 Aug 13 05:22:08 PM PDT 24 85524654 ps
T556 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3496418222 Aug 13 05:21:54 PM PDT 24 Aug 13 05:21:55 PM PDT 24 32933551 ps
T557 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.707636692 Aug 13 05:21:17 PM PDT 24 Aug 13 05:21:19 PM PDT 24 40464792 ps
T558 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.722060044 Aug 13 05:21:40 PM PDT 24 Aug 13 05:21:41 PM PDT 24 14926629 ps
T559 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2070151914 Aug 13 05:21:59 PM PDT 24 Aug 13 05:22:00 PM PDT 24 41438187 ps
T560 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.716043869 Aug 13 05:21:43 PM PDT 24 Aug 13 05:21:43 PM PDT 24 33883005 ps
T561 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1662966667 Aug 13 05:21:56 PM PDT 24 Aug 13 05:21:57 PM PDT 24 25674675 ps
T562 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2647720757 Aug 13 05:21:49 PM PDT 24 Aug 13 05:21:49 PM PDT 24 77079551 ps
T563 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2343034964 Aug 13 05:21:53 PM PDT 24 Aug 13 05:21:53 PM PDT 24 34841745 ps
T564 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4077682902 Aug 13 05:21:43 PM PDT 24 Aug 13 05:21:43 PM PDT 24 77786343 ps
T565 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2703532314 Aug 13 05:21:45 PM PDT 24 Aug 13 05:21:46 PM PDT 24 139116593 ps
T566 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3430936389 Aug 13 05:21:40 PM PDT 24 Aug 13 05:21:43 PM PDT 24 148861280 ps
T567 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1443861732 Aug 13 05:22:07 PM PDT 24 Aug 13 05:22:07 PM PDT 24 48577624 ps
T80 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2308314346 Aug 13 05:21:48 PM PDT 24 Aug 13 05:21:49 PM PDT 24 61467372 ps
T568 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2703278503 Aug 13 05:22:00 PM PDT 24 Aug 13 05:22:01 PM PDT 24 21125587 ps
T569 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.97390198 Aug 13 05:21:53 PM PDT 24 Aug 13 05:21:54 PM PDT 24 18758953 ps
T570 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.84823693 Aug 13 05:21:41 PM PDT 24 Aug 13 05:21:42 PM PDT 24 152744895 ps
T571 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.171235869 Aug 13 05:21:39 PM PDT 24 Aug 13 05:21:40 PM PDT 24 45542207 ps
T572 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1377609872 Aug 13 05:21:30 PM PDT 24 Aug 13 05:21:32 PM PDT 24 349096855 ps
T573 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2434157373 Aug 13 05:21:53 PM PDT 24 Aug 13 05:21:54 PM PDT 24 11685973 ps
T574 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1624355361 Aug 13 05:22:09 PM PDT 24 Aug 13 05:22:15 PM PDT 24 48454496 ps
T575 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1915988679 Aug 13 05:21:43 PM PDT 24 Aug 13 05:21:44 PM PDT 24 98661502 ps
T576 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1715344516 Aug 13 05:21:57 PM PDT 24 Aug 13 05:21:57 PM PDT 24 14180063 ps
T577 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1039397218 Aug 13 05:21:55 PM PDT 24 Aug 13 05:21:55 PM PDT 24 17054002 ps
T578 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1604157394 Aug 13 05:21:47 PM PDT 24 Aug 13 05:21:53 PM PDT 24 379532463 ps
T579 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.504559743 Aug 13 05:21:21 PM PDT 24 Aug 13 05:21:22 PM PDT 24 394963550 ps
T83 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3542009117 Aug 13 05:21:21 PM PDT 24 Aug 13 05:21:22 PM PDT 24 89620668 ps
T580 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1613780858 Aug 13 05:21:50 PM PDT 24 Aug 13 05:21:52 PM PDT 24 84439210 ps
T581 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3472096566 Aug 13 05:21:49 PM PDT 24 Aug 13 05:21:50 PM PDT 24 95246988 ps
T72 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3979069131 Aug 13 05:21:29 PM PDT 24 Aug 13 05:21:30 PM PDT 24 55852030 ps
T582 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3251510809 Aug 13 05:21:41 PM PDT 24 Aug 13 05:21:42 PM PDT 24 64002603 ps
T583 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1348093738 Aug 13 05:21:48 PM PDT 24 Aug 13 05:21:49 PM PDT 24 36660727 ps

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.3474839621
Short name T10
Test name
Test status
Simulation time 2589661857 ps
CPU time 20.48 seconds
Started Aug 13 06:12:04 PM PDT 24
Finished Aug 13 06:12:25 PM PDT 24
Peak memory 198312 kb
Host smart-3f3167da-0cc3-47cb-a55f-953f63ba439f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474839621 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.3474839621
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.2263945782
Short name T45
Test name
Test status
Simulation time 175691250337 ps
CPU time 1363.99 seconds
Started Aug 13 06:13:21 PM PDT 24
Finished Aug 13 06:36:05 PM PDT 24
Peak memory 191764 kb
Host smart-a8d17fd3-82b9-4af2-95f7-a99451e6252c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263945782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2263945782
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1652479002
Short name T2
Test name
Test status
Simulation time 449973918239 ps
CPU time 1210.37 seconds
Started Aug 13 06:09:33 PM PDT 24
Finished Aug 13 06:29:43 PM PDT 24
Peak memory 191792 kb
Host smart-6e86c3d9-af3b-406b-b260-d506f65a3a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652479002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1652479002
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2605426922
Short name T13
Test name
Test status
Simulation time 78588380 ps
CPU time 0.84 seconds
Started Aug 13 06:08:50 PM PDT 24
Finished Aug 13 06:08:51 PM PDT 24
Peak memory 214044 kb
Host smart-d3646a42-4689-44e3-bc86-cb7650730caa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605426922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2605426922
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3024704006
Short name T54
Test name
Test status
Simulation time 563256918191 ps
CPU time 1480.41 seconds
Started Aug 13 06:09:59 PM PDT 24
Finished Aug 13 06:34:39 PM PDT 24
Peak memory 191712 kb
Host smart-4ca63d61-640d-447f-a4ac-fe30865af74f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024704006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3024704006
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3156856045
Short name T169
Test name
Test status
Simulation time 7087893257837 ps
CPU time 1846.63 seconds
Started Aug 13 06:11:26 PM PDT 24
Finished Aug 13 06:42:13 PM PDT 24
Peak memory 191672 kb
Host smart-6aca79cc-d6cc-42c6-92d7-54fbb3730b22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156856045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3156856045
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3006171606
Short name T198
Test name
Test status
Simulation time 3427633875137 ps
CPU time 5651.37 seconds
Started Aug 13 06:11:45 PM PDT 24
Finished Aug 13 07:45:57 PM PDT 24
Peak memory 191812 kb
Host smart-d8c02309-3aba-4af9-9182-39fe350da402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006171606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3006171606
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4035245716
Short name T58
Test name
Test status
Simulation time 350598244 ps
CPU time 3.11 seconds
Started Aug 13 05:21:42 PM PDT 24
Finished Aug 13 05:21:46 PM PDT 24
Peak memory 193084 kb
Host smart-b0699554-244f-4111-98e7-2b73ace9ad14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035245716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.4035245716
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2434549966
Short name T55
Test name
Test status
Simulation time 315289106112 ps
CPU time 728.53 seconds
Started Aug 13 06:10:10 PM PDT 24
Finished Aug 13 06:22:19 PM PDT 24
Peak memory 191780 kb
Host smart-1cc8ae27-2f0d-4c8a-9fd3-14af4a9e8130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434549966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2434549966
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2155957060
Short name T170
Test name
Test status
Simulation time 2427873742263 ps
CPU time 1118.5 seconds
Started Aug 13 06:10:38 PM PDT 24
Finished Aug 13 06:29:17 PM PDT 24
Peak memory 191652 kb
Host smart-e19e3466-3f5a-410b-8df1-b9feb8c8f069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155957060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2155957060
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.4072431693
Short name T228
Test name
Test status
Simulation time 2699886517424 ps
CPU time 2692.01 seconds
Started Aug 13 06:09:04 PM PDT 24
Finished Aug 13 06:53:57 PM PDT 24
Peak memory 191756 kb
Host smart-8f46f301-4b97-4569-9e8a-5b1a04a42233
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072431693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
4072431693
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1708993526
Short name T300
Test name
Test status
Simulation time 2191765017419 ps
CPU time 2204.42 seconds
Started Aug 13 06:11:18 PM PDT 24
Finished Aug 13 06:48:03 PM PDT 24
Peak memory 191804 kb
Host smart-96e2f704-0e99-405f-aa5d-065059516f91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708993526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1708993526
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2736628662
Short name T56
Test name
Test status
Simulation time 970157028357 ps
CPU time 996.05 seconds
Started Aug 13 06:11:09 PM PDT 24
Finished Aug 13 06:27:46 PM PDT 24
Peak memory 196632 kb
Host smart-785ec90f-70ab-41b5-b176-9c4a132e8ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736628662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2736628662
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1178148335
Short name T78
Test name
Test status
Simulation time 417396583 ps
CPU time 1.36 seconds
Started Aug 13 05:21:37 PM PDT 24
Finished Aug 13 05:21:39 PM PDT 24
Peak memory 184068 kb
Host smart-bdcb4632-48fe-4b55-aa47-9a92b227ae1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178148335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1178148335
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.410140526
Short name T141
Test name
Test status
Simulation time 538644081793 ps
CPU time 1050.83 seconds
Started Aug 13 06:09:22 PM PDT 24
Finished Aug 13 06:26:53 PM PDT 24
Peak memory 191820 kb
Host smart-cf868ea5-207b-4dcc-9f6f-9fc86e590d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410140526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
410140526
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3484433544
Short name T186
Test name
Test status
Simulation time 820969829980 ps
CPU time 968.37 seconds
Started Aug 13 06:08:56 PM PDT 24
Finished Aug 13 06:25:05 PM PDT 24
Peak memory 191788 kb
Host smart-f29efe96-602e-479f-a469-4e2a9f1add39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484433544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3484433544
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3666642178
Short name T168
Test name
Test status
Simulation time 2089104173931 ps
CPU time 2148.67 seconds
Started Aug 13 06:08:48 PM PDT 24
Finished Aug 13 06:44:37 PM PDT 24
Peak memory 191724 kb
Host smart-06e752eb-9502-4fd6-b8be-090720732934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666642178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3666642178
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.69089217
Short name T134
Test name
Test status
Simulation time 619523507216 ps
CPU time 984.41 seconds
Started Aug 13 06:10:50 PM PDT 24
Finished Aug 13 06:27:15 PM PDT 24
Peak memory 191760 kb
Host smart-96a22450-ca29-406f-8d7c-73587e99f4ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69089217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.69089217
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1766956252
Short name T180
Test name
Test status
Simulation time 563146208070 ps
CPU time 1433.81 seconds
Started Aug 13 06:09:42 PM PDT 24
Finished Aug 13 06:33:36 PM PDT 24
Peak memory 191784 kb
Host smart-efeed17d-e13c-442b-a96d-a3c5476586f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766956252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1766956252
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/171.rv_timer_random.3659476689
Short name T95
Test name
Test status
Simulation time 193567206062 ps
CPU time 287.63 seconds
Started Aug 13 06:13:18 PM PDT 24
Finished Aug 13 06:18:05 PM PDT 24
Peak memory 191804 kb
Host smart-39e21030-8e00-4e58-8a38-e0c33b87f846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659476689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3659476689
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1147822742
Short name T6
Test name
Test status
Simulation time 1324969444635 ps
CPU time 738.35 seconds
Started Aug 13 06:10:23 PM PDT 24
Finished Aug 13 06:22:41 PM PDT 24
Peak memory 183592 kb
Host smart-425f1c76-a639-4900-b038-8e2054d5ebf2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147822742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1147822742
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/130.rv_timer_random.3693182648
Short name T103
Test name
Test status
Simulation time 262660461972 ps
CPU time 1573.78 seconds
Started Aug 13 06:12:35 PM PDT 24
Finished Aug 13 06:38:50 PM PDT 24
Peak memory 191836 kb
Host smart-3e283ba5-ba45-4800-939e-3ef975188c57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693182648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3693182648
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.4264427352
Short name T57
Test name
Test status
Simulation time 1796880032118 ps
CPU time 976.72 seconds
Started Aug 13 06:08:54 PM PDT 24
Finished Aug 13 06:25:11 PM PDT 24
Peak memory 191928 kb
Host smart-d31fb955-d4e0-41bc-abd5-382d1ed013e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264427352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
4264427352
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/53.rv_timer_random.3010362647
Short name T230
Test name
Test status
Simulation time 80896832165 ps
CPU time 139.45 seconds
Started Aug 13 06:12:01 PM PDT 24
Finished Aug 13 06:14:21 PM PDT 24
Peak memory 194292 kb
Host smart-534bb401-1328-471e-8ea1-03109b87fee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010362647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3010362647
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.4175209036
Short name T252
Test name
Test status
Simulation time 119348363833 ps
CPU time 213.43 seconds
Started Aug 13 06:12:26 PM PDT 24
Finished Aug 13 06:16:00 PM PDT 24
Peak memory 191752 kb
Host smart-c9688f0a-5ddf-48a1-8932-6610a43741f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175209036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.4175209036
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1162037937
Short name T92
Test name
Test status
Simulation time 797552819513 ps
CPU time 2963.38 seconds
Started Aug 13 06:12:37 PM PDT 24
Finished Aug 13 07:02:01 PM PDT 24
Peak memory 191732 kb
Host smart-2101847a-0014-43ab-80c1-5acbffc040a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162037937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1162037937
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.968303488
Short name T166
Test name
Test status
Simulation time 1235493950536 ps
CPU time 1239.28 seconds
Started Aug 13 06:11:45 PM PDT 24
Finished Aug 13 06:32:24 PM PDT 24
Peak memory 191812 kb
Host smart-a8c3dacd-056a-48fd-bd44-9a600347bdfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968303488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
968303488
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/102.rv_timer_random.864084389
Short name T148
Test name
Test status
Simulation time 253908350030 ps
CPU time 1814.16 seconds
Started Aug 13 06:12:26 PM PDT 24
Finished Aug 13 06:42:41 PM PDT 24
Peak memory 191752 kb
Host smart-1adad55d-9f32-4b10-9b9a-869236f35d34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864084389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.864084389
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2527235184
Short name T173
Test name
Test status
Simulation time 379616816372 ps
CPU time 205.31 seconds
Started Aug 13 06:12:27 PM PDT 24
Finished Aug 13 06:15:52 PM PDT 24
Peak memory 191664 kb
Host smart-73f77271-60b3-4329-a727-ccee755f1af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527235184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2527235184
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3506014116
Short name T41
Test name
Test status
Simulation time 245829050131 ps
CPU time 401.58 seconds
Started Aug 13 06:12:53 PM PDT 24
Finished Aug 13 06:19:34 PM PDT 24
Peak memory 191844 kb
Host smart-7b11257a-c578-4ca9-8cd1-cf8c4eae4ebc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506014116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3506014116
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.358102899
Short name T436
Test name
Test status
Simulation time 721641211790 ps
CPU time 1373.73 seconds
Started Aug 13 06:11:53 PM PDT 24
Finished Aug 13 06:34:47 PM PDT 24
Peak memory 191652 kb
Host smart-c5b6b85f-0d08-42c2-a84e-3f6e0b43b449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358102899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
358102899
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/78.rv_timer_random.167524830
Short name T109
Test name
Test status
Simulation time 370221942541 ps
CPU time 482.28 seconds
Started Aug 13 06:12:11 PM PDT 24
Finished Aug 13 06:20:14 PM PDT 24
Peak memory 191816 kb
Host smart-e98cf66d-68ac-4ff2-80fa-92221a5a9379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167524830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.167524830
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.693644895
Short name T131
Test name
Test status
Simulation time 959822445124 ps
CPU time 1058.01 seconds
Started Aug 13 06:09:43 PM PDT 24
Finished Aug 13 06:27:21 PM PDT 24
Peak memory 191760 kb
Host smart-eafc2c80-aee8-4b6a-a853-242cdb565f21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693644895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
693644895
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_random.2667998062
Short name T194
Test name
Test status
Simulation time 108302419768 ps
CPU time 157.11 seconds
Started Aug 13 06:09:58 PM PDT 24
Finished Aug 13 06:12:35 PM PDT 24
Peak memory 183588 kb
Host smart-a8bcece3-96c2-4507-9960-2cdd9586e2a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667998062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2667998062
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.2962224203
Short name T264
Test name
Test status
Simulation time 644994519887 ps
CPU time 378.97 seconds
Started Aug 13 06:10:13 PM PDT 24
Finished Aug 13 06:16:32 PM PDT 24
Peak memory 191832 kb
Host smart-f87132ad-74d4-41b9-810b-f131a1e54378
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962224203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2962224203
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random.1832329666
Short name T323
Test name
Test status
Simulation time 220756368605 ps
CPU time 321.92 seconds
Started Aug 13 06:11:18 PM PDT 24
Finished Aug 13 06:16:40 PM PDT 24
Peak memory 191792 kb
Host smart-2ca7db3a-575e-4ead-bd34-63ea8295afcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832329666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1832329666
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random.1187360912
Short name T138
Test name
Test status
Simulation time 1753384238393 ps
CPU time 1338.18 seconds
Started Aug 13 06:11:08 PM PDT 24
Finished Aug 13 06:33:27 PM PDT 24
Peak memory 191820 kb
Host smart-625a7b76-289e-4a4a-b5f5-f6fd8fb5ca18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187360912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1187360912
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.791919500
Short name T211
Test name
Test status
Simulation time 161982315984 ps
CPU time 485.46 seconds
Started Aug 13 06:12:17 PM PDT 24
Finished Aug 13 06:20:23 PM PDT 24
Peak memory 191808 kb
Host smart-5e24bfe5-fc77-4b06-91a7-639508158efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791919500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.791919500
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3439597461
Short name T160
Test name
Test status
Simulation time 118408181350 ps
CPU time 345.57 seconds
Started Aug 13 06:12:17 PM PDT 24
Finished Aug 13 06:18:02 PM PDT 24
Peak memory 191748 kb
Host smart-83d433ba-cf86-4947-8570-1f8c269b4c74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439597461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3439597461
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.1749951006
Short name T270
Test name
Test status
Simulation time 145301037449 ps
CPU time 161.54 seconds
Started Aug 13 06:08:53 PM PDT 24
Finished Aug 13 06:11:35 PM PDT 24
Peak memory 191820 kb
Host smart-0afffb62-8b95-4470-aeb2-cbcf5eb7647d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749951006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1749951006
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3410120740
Short name T182
Test name
Test status
Simulation time 509791260970 ps
CPU time 458.66 seconds
Started Aug 13 06:09:43 PM PDT 24
Finished Aug 13 06:17:22 PM PDT 24
Peak memory 196696 kb
Host smart-0fbcb9c8-46dc-4f6a-abfe-a3546bfd76cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410120740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3410120740
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/186.rv_timer_random.2677938217
Short name T221
Test name
Test status
Simulation time 348002994242 ps
CPU time 485.45 seconds
Started Aug 13 06:13:26 PM PDT 24
Finished Aug 13 06:21:32 PM PDT 24
Peak memory 191832 kb
Host smart-9187ab58-8b8c-4fe1-a824-bc55c8e05c62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677938217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2677938217
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3130747145
Short name T106
Test name
Test status
Simulation time 1966826659076 ps
CPU time 1039.69 seconds
Started Aug 13 06:10:07 PM PDT 24
Finished Aug 13 06:27:26 PM PDT 24
Peak memory 191800 kb
Host smart-7c2b50c5-0cba-4821-977c-ad3429774fd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130747145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3130747145
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2730012886
Short name T324
Test name
Test status
Simulation time 6553764016134 ps
CPU time 941.77 seconds
Started Aug 13 06:10:04 PM PDT 24
Finished Aug 13 06:25:46 PM PDT 24
Peak memory 191824 kb
Host smart-a55a0919-0a9b-473f-9614-9d0dc5efcad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730012886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2730012886
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.4134730022
Short name T177
Test name
Test status
Simulation time 680758944559 ps
CPU time 1120.36 seconds
Started Aug 13 06:11:00 PM PDT 24
Finished Aug 13 06:29:40 PM PDT 24
Peak memory 191688 kb
Host smart-d0554982-159a-4c25-aff9-67841e002004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134730022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.4134730022
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/72.rv_timer_random.1183315272
Short name T330
Test name
Test status
Simulation time 551257890952 ps
CPU time 435.12 seconds
Started Aug 13 06:12:11 PM PDT 24
Finished Aug 13 06:19:26 PM PDT 24
Peak memory 191796 kb
Host smart-5a437588-15cd-4602-a6c6-eb85369ae9a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183315272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1183315272
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1282124624
Short name T144
Test name
Test status
Simulation time 1619507203472 ps
CPU time 1062.73 seconds
Started Aug 13 06:09:26 PM PDT 24
Finished Aug 13 06:27:09 PM PDT 24
Peak memory 191604 kb
Host smart-0e6b23d3-03b7-4a2d-acd0-7635be4c1d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282124624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1282124624
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_random.2094960353
Short name T25
Test name
Test status
Simulation time 137269491293 ps
CPU time 176.41 seconds
Started Aug 13 06:09:31 PM PDT 24
Finished Aug 13 06:12:28 PM PDT 24
Peak memory 191804 kb
Host smart-4a802261-4557-4db4-aebb-2bdc0327e6eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094960353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2094960353
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1392468233
Short name T93
Test name
Test status
Simulation time 181647617017 ps
CPU time 160.61 seconds
Started Aug 13 06:12:50 PM PDT 24
Finished Aug 13 06:15:31 PM PDT 24
Peak memory 191768 kb
Host smart-2cad4836-faef-45dc-92e7-8eb67cd36ac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392468233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1392468233
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.396359609
Short name T249
Test name
Test status
Simulation time 542658854933 ps
CPU time 322.97 seconds
Started Aug 13 06:13:20 PM PDT 24
Finished Aug 13 06:18:43 PM PDT 24
Peak memory 191772 kb
Host smart-60e11efa-39ae-4228-b82f-42d9329293dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396359609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.396359609
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.240342831
Short name T181
Test name
Test status
Simulation time 318558259108 ps
CPU time 326.11 seconds
Started Aug 13 06:13:36 PM PDT 24
Finished Aug 13 06:19:02 PM PDT 24
Peak memory 191844 kb
Host smart-0106f6e2-2b40-4766-8093-2a1878a45394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240342831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.240342831
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1754783651
Short name T145
Test name
Test status
Simulation time 942742440517 ps
CPU time 1104.44 seconds
Started Aug 13 06:10:32 PM PDT 24
Finished Aug 13 06:28:56 PM PDT 24
Peak memory 191804 kb
Host smart-c18398d3-5808-4d78-b831-16cff6f14171
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754783651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1754783651
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2940454147
Short name T243
Test name
Test status
Simulation time 117848879714 ps
CPU time 176.96 seconds
Started Aug 13 06:10:50 PM PDT 24
Finished Aug 13 06:13:47 PM PDT 24
Peak memory 183600 kb
Host smart-97a4c5de-9107-4048-8b13-81a0b1d2505e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940454147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2940454147
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_random.3322377492
Short name T253
Test name
Test status
Simulation time 119711063769 ps
CPU time 840.9 seconds
Started Aug 13 06:11:44 PM PDT 24
Finished Aug 13 06:25:45 PM PDT 24
Peak memory 191792 kb
Host smart-4ffa41f0-2ac6-4ba1-819e-d327aceff81d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322377492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3322377492
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2282411510
Short name T287
Test name
Test status
Simulation time 108205575108 ps
CPU time 409.68 seconds
Started Aug 13 06:12:01 PM PDT 24
Finished Aug 13 06:18:51 PM PDT 24
Peak memory 191784 kb
Host smart-c260d501-efcb-455c-a599-994a7da86a72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282411510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2282411510
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2948808808
Short name T60
Test name
Test status
Simulation time 45173002 ps
CPU time 0.6 seconds
Started Aug 13 05:21:54 PM PDT 24
Finished Aug 13 05:21:55 PM PDT 24
Peak memory 192032 kb
Host smart-3e9bf50e-fe67-487a-86c1-12c1c751af17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948808808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2948808808
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/104.rv_timer_random.3905825767
Short name T216
Test name
Test status
Simulation time 217046924427 ps
CPU time 514.49 seconds
Started Aug 13 06:12:26 PM PDT 24
Finished Aug 13 06:21:01 PM PDT 24
Peak memory 191808 kb
Host smart-d458744e-f2d2-474c-b3a7-3ee05521d677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905825767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3905825767
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1716410172
Short name T241
Test name
Test status
Simulation time 114679803311 ps
CPU time 199.39 seconds
Started Aug 13 06:12:44 PM PDT 24
Finished Aug 13 06:16:03 PM PDT 24
Peak memory 195368 kb
Host smart-d2b6f24f-e511-4b6c-8e58-4cea6c7d226c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716410172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1716410172
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1972957561
Short name T40
Test name
Test status
Simulation time 246539721700 ps
CPU time 232.21 seconds
Started Aug 13 06:13:19 PM PDT 24
Finished Aug 13 06:17:11 PM PDT 24
Peak memory 191756 kb
Host smart-16aafb80-d093-4351-88fc-c21c06743cd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972957561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1972957561
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1136355854
Short name T298
Test name
Test status
Simulation time 459543982987 ps
CPU time 514.61 seconds
Started Aug 13 06:13:17 PM PDT 24
Finished Aug 13 06:21:51 PM PDT 24
Peak memory 193884 kb
Host smart-007848ad-dd94-4197-838b-190fc5f588ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136355854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1136355854
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1076006317
Short name T364
Test name
Test status
Simulation time 624045167426 ps
CPU time 242.06 seconds
Started Aug 13 06:10:06 PM PDT 24
Finished Aug 13 06:14:09 PM PDT 24
Peak memory 183584 kb
Host smart-7e94f988-6fb8-4f26-b168-79656cd5dce1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076006317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1076006317
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_random.324679551
Short name T162
Test name
Test status
Simulation time 447364585348 ps
CPU time 205.16 seconds
Started Aug 13 06:10:03 PM PDT 24
Finished Aug 13 06:13:29 PM PDT 24
Peak memory 191836 kb
Host smart-a6adb8f2-1e9c-477c-8b60-5d84ad5afe89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324679551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.324679551
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.337817278
Short name T224
Test name
Test status
Simulation time 35893708225 ps
CPU time 32.52 seconds
Started Aug 13 06:10:05 PM PDT 24
Finished Aug 13 06:10:38 PM PDT 24
Peak memory 183624 kb
Host smart-32bea2ed-d03c-4323-b4c0-f2bff109ab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337817278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.337817278
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_random.2467780945
Short name T114
Test name
Test status
Simulation time 80703851500 ps
CPU time 63.66 seconds
Started Aug 13 06:10:23 PM PDT 24
Finished Aug 13 06:11:27 PM PDT 24
Peak memory 191792 kb
Host smart-c4d76b82-02ee-4721-9adc-3964c870bf56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467780945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2467780945
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1519623575
Short name T308
Test name
Test status
Simulation time 80010763272 ps
CPU time 1142.57 seconds
Started Aug 13 06:10:51 PM PDT 24
Finished Aug 13 06:29:54 PM PDT 24
Peak memory 183592 kb
Host smart-e2970179-9740-4f5b-9bc3-a8cb40a2bd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519623575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1519623575
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.133440751
Short name T428
Test name
Test status
Simulation time 340241669886 ps
CPU time 164.04 seconds
Started Aug 13 06:11:53 PM PDT 24
Finished Aug 13 06:14:37 PM PDT 24
Peak memory 191772 kb
Host smart-59668eec-28d7-4ec7-9622-e0360d9d841f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133440751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.133440751
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/93.rv_timer_random.1475726101
Short name T233
Test name
Test status
Simulation time 27993145462 ps
CPU time 45.98 seconds
Started Aug 13 06:12:19 PM PDT 24
Finished Aug 13 06:13:05 PM PDT 24
Peak memory 183636 kb
Host smart-4c402e72-5222-46ed-9151-8cef31fcf24c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475726101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1475726101
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1005529451
Short name T81
Test name
Test status
Simulation time 105900365 ps
CPU time 1.19 seconds
Started Aug 13 05:21:43 PM PDT 24
Finished Aug 13 05:21:45 PM PDT 24
Peak memory 184096 kb
Host smart-52582f46-83ae-44dc-b419-c83577320c68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005529451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1005529451
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2402517488
Short name T149
Test name
Test status
Simulation time 501107851622 ps
CPU time 174.1 seconds
Started Aug 13 06:08:43 PM PDT 24
Finished Aug 13 06:11:37 PM PDT 24
Peak memory 183540 kb
Host smart-626a0dd9-91a5-4b94-ae83-dd9f667c23c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402517488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2402517488
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_random.1495127922
Short name T86
Test name
Test status
Simulation time 193346969825 ps
CPU time 129.38 seconds
Started Aug 13 06:08:41 PM PDT 24
Finished Aug 13 06:10:50 PM PDT 24
Peak memory 191752 kb
Host smart-68bab1b8-1c39-4cd8-b69b-0a9feabe11ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495127922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1495127922
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2065150575
Short name T172
Test name
Test status
Simulation time 58277558747 ps
CPU time 31.6 seconds
Started Aug 13 06:09:19 PM PDT 24
Finished Aug 13 06:09:50 PM PDT 24
Peak memory 183492 kb
Host smart-4f4c6eaf-d402-4ebc-baa3-391de4258b10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065150575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2065150575
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/105.rv_timer_random.1695970381
Short name T317
Test name
Test status
Simulation time 81918272899 ps
CPU time 141.26 seconds
Started Aug 13 06:12:26 PM PDT 24
Finished Aug 13 06:14:48 PM PDT 24
Peak memory 191796 kb
Host smart-9cb53f49-6177-4b49-9358-2c8894e5dcea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695970381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1695970381
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3936917709
Short name T280
Test name
Test status
Simulation time 353493960147 ps
CPU time 233.36 seconds
Started Aug 13 06:12:25 PM PDT 24
Finished Aug 13 06:16:19 PM PDT 24
Peak memory 191708 kb
Host smart-0aeddb6c-ccb1-4fee-b9ad-9d8769e04ad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936917709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3936917709
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3699409841
Short name T139
Test name
Test status
Simulation time 351000612925 ps
CPU time 1280.14 seconds
Started Aug 13 06:12:26 PM PDT 24
Finished Aug 13 06:33:47 PM PDT 24
Peak memory 191668 kb
Host smart-5ddee31c-d1e9-4b2a-bcdc-b139e90a50d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699409841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3699409841
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2856205077
Short name T123
Test name
Test status
Simulation time 93388572997 ps
CPU time 82.13 seconds
Started Aug 13 06:12:35 PM PDT 24
Finished Aug 13 06:13:57 PM PDT 24
Peak memory 191796 kb
Host smart-10b0d3be-4850-49a1-abab-1b13e7816f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856205077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2856205077
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2153060788
Short name T150
Test name
Test status
Simulation time 96490266476 ps
CPU time 149.3 seconds
Started Aug 13 06:09:31 PM PDT 24
Finished Aug 13 06:12:01 PM PDT 24
Peak memory 183536 kb
Host smart-36646a87-f22b-4b44-af58-91d1cd7224d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153060788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2153060788
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_random.2485112409
Short name T292
Test name
Test status
Simulation time 61147023900 ps
CPU time 510.06 seconds
Started Aug 13 06:09:28 PM PDT 24
Finished Aug 13 06:17:59 PM PDT 24
Peak memory 183728 kb
Host smart-4f700667-7207-48c2-95e4-acdc6a899e25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485112409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2485112409
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2664545855
Short name T9
Test name
Test status
Simulation time 213901426550 ps
CPU time 134.92 seconds
Started Aug 13 06:12:36 PM PDT 24
Finished Aug 13 06:14:51 PM PDT 24
Peak memory 191844 kb
Host smart-ca7de541-b483-4cc0-85fd-335b41a50a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664545855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2664545855
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1111833828
Short name T261
Test name
Test status
Simulation time 29862777289 ps
CPU time 49.63 seconds
Started Aug 13 06:12:35 PM PDT 24
Finished Aug 13 06:13:24 PM PDT 24
Peak memory 183600 kb
Host smart-e710bf3c-ed7c-42f4-849b-045913d09235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111833828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1111833828
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1041268187
Short name T155
Test name
Test status
Simulation time 346025822621 ps
CPU time 3294.06 seconds
Started Aug 13 06:12:40 PM PDT 24
Finished Aug 13 07:07:35 PM PDT 24
Peak memory 191772 kb
Host smart-e27bcb89-ac9a-42be-b357-4176d9ccef6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041268187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1041268187
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2400104550
Short name T157
Test name
Test status
Simulation time 777876707229 ps
CPU time 419.49 seconds
Started Aug 13 06:12:44 PM PDT 24
Finished Aug 13 06:19:44 PM PDT 24
Peak memory 191828 kb
Host smart-31b76a03-ad6d-41f7-bd0d-2bb218a5b022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400104550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2400104550
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2708650154
Short name T135
Test name
Test status
Simulation time 422548106493 ps
CPU time 243.9 seconds
Started Aug 13 06:12:45 PM PDT 24
Finished Aug 13 06:16:49 PM PDT 24
Peak memory 191800 kb
Host smart-4bf6f61f-4690-4320-9b06-c906da1a808b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708650154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2708650154
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.4046893266
Short name T277
Test name
Test status
Simulation time 20718881862 ps
CPU time 18 seconds
Started Aug 13 06:12:45 PM PDT 24
Finished Aug 13 06:13:03 PM PDT 24
Peak memory 183600 kb
Host smart-620cdd36-a80f-4fee-9683-47c07b691b8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046893266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4046893266
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2726162704
Short name T20
Test name
Test status
Simulation time 188302473583 ps
CPU time 673.12 seconds
Started Aug 13 06:12:53 PM PDT 24
Finished Aug 13 06:24:06 PM PDT 24
Peak memory 191772 kb
Host smart-089e4a4a-2ab7-451f-9a71-20381219f135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726162704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2726162704
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3767013707
Short name T125
Test name
Test status
Simulation time 160912181649 ps
CPU time 147.68 seconds
Started Aug 13 06:13:05 PM PDT 24
Finished Aug 13 06:15:33 PM PDT 24
Peak memory 191804 kb
Host smart-dc299749-182a-46d7-b948-dadd4548cb5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767013707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3767013707
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3772270022
Short name T214
Test name
Test status
Simulation time 746774339400 ps
CPU time 1964.26 seconds
Started Aug 13 06:13:14 PM PDT 24
Finished Aug 13 06:45:59 PM PDT 24
Peak memory 191780 kb
Host smart-29669c79-c69f-4390-b377-d0f198559d95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772270022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3772270022
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1770454126
Short name T291
Test name
Test status
Simulation time 215251721138 ps
CPU time 107.96 seconds
Started Aug 13 06:09:59 PM PDT 24
Finished Aug 13 06:11:47 PM PDT 24
Peak memory 183464 kb
Host smart-0511e611-50b1-410d-9fb2-c68ee1ddf1b0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770454126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1770454126
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/191.rv_timer_random.3811876028
Short name T238
Test name
Test status
Simulation time 229990208680 ps
CPU time 1528.33 seconds
Started Aug 13 06:13:27 PM PDT 24
Finished Aug 13 06:38:55 PM PDT 24
Peak memory 191796 kb
Host smart-6dda246c-0228-4045-bf60-cd8a91909888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811876028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3811876028
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.605249282
Short name T96
Test name
Test status
Simulation time 70306470396 ps
CPU time 353.83 seconds
Started Aug 13 06:08:50 PM PDT 24
Finished Aug 13 06:14:44 PM PDT 24
Peak memory 191808 kb
Host smart-a7351674-85dd-4374-8f65-b6da204acad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605249282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.605249282
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.978662451
Short name T312
Test name
Test status
Simulation time 84574987202 ps
CPU time 71.43 seconds
Started Aug 13 06:09:59 PM PDT 24
Finished Aug 13 06:11:11 PM PDT 24
Peak memory 191772 kb
Host smart-40586cfd-9d7f-400e-b570-ee6dbe0e9491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978662451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.978662451
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3506843645
Short name T345
Test name
Test status
Simulation time 982289239877 ps
CPU time 423 seconds
Started Aug 13 06:10:14 PM PDT 24
Finished Aug 13 06:17:17 PM PDT 24
Peak memory 191756 kb
Host smart-c671225e-c9e5-4681-8888-c853401681bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506843645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3506843645
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2235702918
Short name T285
Test name
Test status
Simulation time 796460072212 ps
CPU time 474.89 seconds
Started Aug 13 06:08:57 PM PDT 24
Finished Aug 13 06:16:52 PM PDT 24
Peak memory 183488 kb
Host smart-b0a56fea-f801-46f2-9b4a-7668a4e5882d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235702918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2235702918
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_random.1900969559
Short name T208
Test name
Test status
Simulation time 172319004857 ps
CPU time 642.84 seconds
Started Aug 13 06:10:58 PM PDT 24
Finished Aug 13 06:21:41 PM PDT 24
Peak memory 191812 kb
Host smart-a5d71b1c-4edb-49ed-8710-73cd17dbed79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900969559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1900969559
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random.2610306041
Short name T215
Test name
Test status
Simulation time 34184498299 ps
CPU time 56.2 seconds
Started Aug 13 06:11:35 PM PDT 24
Finished Aug 13 06:12:31 PM PDT 24
Peak memory 183528 kb
Host smart-cb035dda-3a0e-4a1c-b2dc-6ee63e9b2b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610306041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2610306041
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.4015673735
Short name T154
Test name
Test status
Simulation time 124524804482 ps
CPU time 227 seconds
Started Aug 13 06:12:13 PM PDT 24
Finished Aug 13 06:16:01 PM PDT 24
Peak memory 191796 kb
Host smart-ab8472f7-25e2-4686-98de-027057eb0ca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015673735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.4015673735
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.3699995133
Short name T213
Test name
Test status
Simulation time 66412271495 ps
CPU time 930.77 seconds
Started Aug 13 06:09:13 PM PDT 24
Finished Aug 13 06:24:44 PM PDT 24
Peak memory 191796 kb
Host smart-6b5ad8c4-591d-4a40-a14b-3ed66cffd008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699995133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3699995133
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3470184047
Short name T305
Test name
Test status
Simulation time 116413252449 ps
CPU time 391.11 seconds
Started Aug 13 06:12:27 PM PDT 24
Finished Aug 13 06:18:58 PM PDT 24
Peak memory 191780 kb
Host smart-6a302bb4-7b31-4f70-87c7-0a28643f64c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470184047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3470184047
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1520789615
Short name T334
Test name
Test status
Simulation time 881000551315 ps
CPU time 2303.23 seconds
Started Aug 13 06:12:23 PM PDT 24
Finished Aug 13 06:50:46 PM PDT 24
Peak memory 191792 kb
Host smart-c6139997-2d17-44de-a0f4-b2e471c3b32d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520789615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1520789615
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3103159604
Short name T246
Test name
Test status
Simulation time 560445494942 ps
CPU time 247.16 seconds
Started Aug 13 06:09:20 PM PDT 24
Finished Aug 13 06:13:28 PM PDT 24
Peak memory 183612 kb
Host smart-448f3fc2-d928-4452-a60a-40c000a91eb3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103159604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3103159604
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/95.rv_timer_random.3950333542
Short name T332
Test name
Test status
Simulation time 63044140233 ps
CPU time 542.8 seconds
Started Aug 13 06:12:18 PM PDT 24
Finished Aug 13 06:21:21 PM PDT 24
Peak memory 183600 kb
Host smart-4c2a96d1-7b90-4a1c-ae17-8f9a04d6fee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950333542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3950333542
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1296788053
Short name T69
Test name
Test status
Simulation time 62493057 ps
CPU time 0.79 seconds
Started Aug 13 05:21:54 PM PDT 24
Finished Aug 13 05:21:55 PM PDT 24
Peak memory 192996 kb
Host smart-2478ce21-f936-44b1-854f-090a00301fe0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296788053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1296788053
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.167026070
Short name T485
Test name
Test status
Simulation time 250615022 ps
CPU time 2.62 seconds
Started Aug 13 05:21:45 PM PDT 24
Finished Aug 13 05:21:47 PM PDT 24
Peak memory 191716 kb
Host smart-86da21d3-00ac-4a5a-aef4-e560e4e81a5a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167026070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.167026070
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2343034964
Short name T563
Test name
Test status
Simulation time 34841745 ps
CPU time 0.54 seconds
Started Aug 13 05:21:53 PM PDT 24
Finished Aug 13 05:21:53 PM PDT 24
Peak memory 182812 kb
Host smart-37a794ca-0052-4726-adbd-f42264695f44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343034964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2343034964
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.838970141
Short name T512
Test name
Test status
Simulation time 117277791 ps
CPU time 1.34 seconds
Started Aug 13 05:21:52 PM PDT 24
Finished Aug 13 05:21:54 PM PDT 24
Peak memory 198196 kb
Host smart-9c2aa9cf-f9a3-447e-be08-19f0b82f18bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838970141 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.838970141
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.83522713
Short name T500
Test name
Test status
Simulation time 14679373 ps
CPU time 0.54 seconds
Started Aug 13 05:21:38 PM PDT 24
Finished Aug 13 05:21:39 PM PDT 24
Peak memory 183048 kb
Host smart-df9f7094-92ed-43cc-804e-b026a6bc6b8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83522713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.83522713
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3959396249
Short name T489
Test name
Test status
Simulation time 14858525 ps
CPU time 0.56 seconds
Started Aug 13 05:21:36 PM PDT 24
Finished Aug 13 05:21:37 PM PDT 24
Peak memory 182648 kb
Host smart-9a6b0e6d-dc15-4d20-8b78-de4b91c50d1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959396249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3959396249
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3251510809
Short name T582
Test name
Test status
Simulation time 64002603 ps
CPU time 0.62 seconds
Started Aug 13 05:21:41 PM PDT 24
Finished Aug 13 05:21:42 PM PDT 24
Peak memory 192560 kb
Host smart-92bd6ba0-aa99-42fd-b2f4-a8d7039f090c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251510809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3251510809
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.707636692
Short name T557
Test name
Test status
Simulation time 40464792 ps
CPU time 1.82 seconds
Started Aug 13 05:21:17 PM PDT 24
Finished Aug 13 05:21:19 PM PDT 24
Peak memory 198128 kb
Host smart-0c8e60d7-d7c0-4601-8c42-8699a5c10fcc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707636692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.707636692
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1291466077
Short name T68
Test name
Test status
Simulation time 110775844 ps
CPU time 0.79 seconds
Started Aug 13 05:21:31 PM PDT 24
Finished Aug 13 05:21:32 PM PDT 24
Peak memory 193068 kb
Host smart-8f52a0c3-542f-4e36-8044-946dd2d87835
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291466077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1291466077
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1764179174
Short name T551
Test name
Test status
Simulation time 938609807 ps
CPU time 2.62 seconds
Started Aug 13 05:21:52 PM PDT 24
Finished Aug 13 05:21:55 PM PDT 24
Peak memory 191716 kb
Host smart-362c5466-b85c-46aa-857e-91b74a794e03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764179174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1764179174
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2013666869
Short name T71
Test name
Test status
Simulation time 41291752 ps
CPU time 0.58 seconds
Started Aug 13 05:21:32 PM PDT 24
Finished Aug 13 05:21:33 PM PDT 24
Peak memory 183304 kb
Host smart-c07c1d25-8204-4771-8604-e358074512c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013666869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2013666869
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1695210880
Short name T511
Test name
Test status
Simulation time 49847835 ps
CPU time 0.71 seconds
Started Aug 13 05:21:35 PM PDT 24
Finished Aug 13 05:21:35 PM PDT 24
Peak memory 195292 kb
Host smart-87867e3d-18ef-4f17-88d2-493f1f8132bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695210880 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1695210880
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1715344516
Short name T576
Test name
Test status
Simulation time 14180063 ps
CPU time 0.52 seconds
Started Aug 13 05:21:57 PM PDT 24
Finished Aug 13 05:21:57 PM PDT 24
Peak memory 183084 kb
Host smart-cdeba77c-4a8d-4230-94b1-078e8195aa69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715344516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1715344516
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.582593153
Short name T479
Test name
Test status
Simulation time 34272295 ps
CPU time 0.54 seconds
Started Aug 13 05:21:46 PM PDT 24
Finished Aug 13 05:21:47 PM PDT 24
Peak memory 183132 kb
Host smart-57cc927d-48f0-400b-b95b-7ebda2a80e8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582593153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.582593153
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.123844336
Short name T549
Test name
Test status
Simulation time 20386870 ps
CPU time 0.85 seconds
Started Aug 13 05:21:36 PM PDT 24
Finished Aug 13 05:21:38 PM PDT 24
Peak memory 194084 kb
Host smart-fe0e72a0-6fca-4040-992c-5aa4ddbb606a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123844336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.123844336
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1450026100
Short name T460
Test name
Test status
Simulation time 861337677 ps
CPU time 1.53 seconds
Started Aug 13 05:21:45 PM PDT 24
Finished Aug 13 05:21:46 PM PDT 24
Peak memory 198004 kb
Host smart-cc71b4a3-8229-4662-91ff-b9938d8457be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450026100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1450026100
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1098259046
Short name T497
Test name
Test status
Simulation time 53027885 ps
CPU time 1.22 seconds
Started Aug 13 05:21:49 PM PDT 24
Finished Aug 13 05:21:50 PM PDT 24
Peak memory 198236 kb
Host smart-854ee1cf-bb54-4514-8b9a-5b04245fa45d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098259046 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1098259046
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3016232271
Short name T535
Test name
Test status
Simulation time 15448938 ps
CPU time 0.57 seconds
Started Aug 13 05:21:43 PM PDT 24
Finished Aug 13 05:21:44 PM PDT 24
Peak memory 183344 kb
Host smart-c8eb1f11-aec6-4f65-9bc5-1c13fd2cd2a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016232271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3016232271
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2434157373
Short name T573
Test name
Test status
Simulation time 11685973 ps
CPU time 0.58 seconds
Started Aug 13 05:21:53 PM PDT 24
Finished Aug 13 05:21:54 PM PDT 24
Peak memory 183188 kb
Host smart-39ef3d3e-c8c5-455f-87b7-3aec20cfd29b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434157373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2434157373
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2247923682
Short name T516
Test name
Test status
Simulation time 17760191 ps
CPU time 0.71 seconds
Started Aug 13 05:21:41 PM PDT 24
Finished Aug 13 05:21:42 PM PDT 24
Peak memory 193908 kb
Host smart-5520403a-5d54-48d9-a0f0-48b7ff5d3f07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247923682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2247923682
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1613780858
Short name T580
Test name
Test status
Simulation time 84439210 ps
CPU time 1.82 seconds
Started Aug 13 05:21:50 PM PDT 24
Finished Aug 13 05:21:52 PM PDT 24
Peak memory 198108 kb
Host smart-ebc15501-ac79-4c52-9d02-f612a8b9782a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613780858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1613780858
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1253481817
Short name T27
Test name
Test status
Simulation time 85415168 ps
CPU time 0.8 seconds
Started Aug 13 05:21:42 PM PDT 24
Finished Aug 13 05:21:43 PM PDT 24
Peak memory 194436 kb
Host smart-fe3cf043-2470-46bb-b081-7c84e5d57dc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253481817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1253481817
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1143764963
Short name T530
Test name
Test status
Simulation time 16814015 ps
CPU time 0.76 seconds
Started Aug 13 05:21:36 PM PDT 24
Finished Aug 13 05:21:37 PM PDT 24
Peak memory 195624 kb
Host smart-c231a714-01fe-47ef-a34b-d61ecb73bb24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143764963 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1143764963
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2294257853
Short name T62
Test name
Test status
Simulation time 14895984 ps
CPU time 0.58 seconds
Started Aug 13 05:21:40 PM PDT 24
Finished Aug 13 05:21:41 PM PDT 24
Peak memory 183372 kb
Host smart-3ca67810-8206-403e-a53c-0875539ba850
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294257853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2294257853
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1249066640
Short name T488
Test name
Test status
Simulation time 54584694 ps
CPU time 0.55 seconds
Started Aug 13 05:21:45 PM PDT 24
Finished Aug 13 05:21:46 PM PDT 24
Peak memory 183248 kb
Host smart-227b049b-ae18-4c02-ba2f-6f55038e8a45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249066640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1249066640
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3430936389
Short name T566
Test name
Test status
Simulation time 148861280 ps
CPU time 2.32 seconds
Started Aug 13 05:21:40 PM PDT 24
Finished Aug 13 05:21:43 PM PDT 24
Peak memory 198140 kb
Host smart-610e6d0f-6ba1-40b2-a238-b7d7afa3ed1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430936389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3430936389
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2647720757
Short name T562
Test name
Test status
Simulation time 77079551 ps
CPU time 0.77 seconds
Started Aug 13 05:21:49 PM PDT 24
Finished Aug 13 05:21:49 PM PDT 24
Peak memory 193960 kb
Host smart-6cb95dd4-3f58-4ed3-8d83-bc0e9eb6e29f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647720757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2647720757
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1382134178
Short name T490
Test name
Test status
Simulation time 30116563 ps
CPU time 0.83 seconds
Started Aug 13 05:21:48 PM PDT 24
Finished Aug 13 05:21:49 PM PDT 24
Peak memory 195936 kb
Host smart-f6ddaf75-04d0-43b3-8780-ced85ab89a2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382134178 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1382134178
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.719982230
Short name T50
Test name
Test status
Simulation time 14937203 ps
CPU time 0.53 seconds
Started Aug 13 05:21:40 PM PDT 24
Finished Aug 13 05:21:41 PM PDT 24
Peak memory 183048 kb
Host smart-0c232374-8324-4381-b40f-54bb742b5ec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719982230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.719982230
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2929663009
Short name T538
Test name
Test status
Simulation time 11250870 ps
CPU time 0.55 seconds
Started Aug 13 05:22:05 PM PDT 24
Finished Aug 13 05:22:06 PM PDT 24
Peak memory 183272 kb
Host smart-0595ae1f-180d-4658-a5be-fc077d24071d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929663009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2929663009
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4200452162
Short name T52
Test name
Test status
Simulation time 167433353 ps
CPU time 0.81 seconds
Started Aug 13 05:21:43 PM PDT 24
Finished Aug 13 05:21:44 PM PDT 24
Peak memory 192268 kb
Host smart-4a3deedc-bb5d-4e7b-bafd-3f45b20f1996
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200452162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.4200452162
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2617938498
Short name T519
Test name
Test status
Simulation time 57919618 ps
CPU time 1.42 seconds
Started Aug 13 05:21:50 PM PDT 24
Finished Aug 13 05:21:52 PM PDT 24
Peak memory 198064 kb
Host smart-6da0bda0-ab52-4d1d-b63a-68220aa69be1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617938498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2617938498
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2843350794
Short name T513
Test name
Test status
Simulation time 115679176 ps
CPU time 1.38 seconds
Started Aug 13 05:21:34 PM PDT 24
Finished Aug 13 05:21:36 PM PDT 24
Peak memory 183856 kb
Host smart-2d4223ad-979c-4172-96e9-fd97e91a66b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843350794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2843350794
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2922822794
Short name T491
Test name
Test status
Simulation time 52880545 ps
CPU time 0.65 seconds
Started Aug 13 05:21:47 PM PDT 24
Finished Aug 13 05:21:48 PM PDT 24
Peak memory 194232 kb
Host smart-248d9f6b-19fe-412a-99c6-54505139d7a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922822794 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2922822794
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.722060044
Short name T558
Test name
Test status
Simulation time 14926629 ps
CPU time 0.58 seconds
Started Aug 13 05:21:40 PM PDT 24
Finished Aug 13 05:21:41 PM PDT 24
Peak memory 183264 kb
Host smart-a74bfb0d-97a2-4b7b-b0a2-508c57c93ca9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722060044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.722060044
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3630693132
Short name T531
Test name
Test status
Simulation time 23426411 ps
CPU time 0.54 seconds
Started Aug 13 05:21:50 PM PDT 24
Finished Aug 13 05:21:50 PM PDT 24
Peak memory 183328 kb
Host smart-6568db4a-a64f-4b6c-9dba-fb25e03c44a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630693132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3630693132
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1565548894
Short name T527
Test name
Test status
Simulation time 86454830 ps
CPU time 0.73 seconds
Started Aug 13 05:21:51 PM PDT 24
Finished Aug 13 05:21:52 PM PDT 24
Peak memory 193996 kb
Host smart-bf9703c8-bba0-481c-be88-7e284c12ad41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565548894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1565548894
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2703532314
Short name T565
Test name
Test status
Simulation time 139116593 ps
CPU time 1.45 seconds
Started Aug 13 05:21:45 PM PDT 24
Finished Aug 13 05:21:46 PM PDT 24
Peak memory 197780 kb
Host smart-fd835990-555e-45a6-9528-3abe7ae7220e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703532314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2703532314
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2308314346
Short name T80
Test name
Test status
Simulation time 61467372 ps
CPU time 0.85 seconds
Started Aug 13 05:21:48 PM PDT 24
Finished Aug 13 05:21:49 PM PDT 24
Peak memory 194424 kb
Host smart-db57da91-c601-44f6-8856-1626551a2df6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308314346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2308314346
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4077682902
Short name T564
Test name
Test status
Simulation time 77786343 ps
CPU time 0.7 seconds
Started Aug 13 05:21:43 PM PDT 24
Finished Aug 13 05:21:43 PM PDT 24
Peak memory 195068 kb
Host smart-d670d09a-cdf5-40a5-863f-87cb6714c63f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077682902 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4077682902
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1443861732
Short name T567
Test name
Test status
Simulation time 48577624 ps
CPU time 0.53 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 183308 kb
Host smart-2334529e-15f7-4430-83b3-cc1bb422a286
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443861732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1443861732
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2064292152
Short name T458
Test name
Test status
Simulation time 12989771 ps
CPU time 0.54 seconds
Started Aug 13 05:21:53 PM PDT 24
Finished Aug 13 05:21:54 PM PDT 24
Peak memory 183172 kb
Host smart-4f989b2c-8fba-4bed-a59c-c9dd7a150dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064292152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2064292152
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1717136509
Short name T546
Test name
Test status
Simulation time 14021664 ps
CPU time 0.6 seconds
Started Aug 13 05:21:36 PM PDT 24
Finished Aug 13 05:21:37 PM PDT 24
Peak memory 192132 kb
Host smart-841703e7-e79f-4841-a8d5-26ef5f2242f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717136509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1717136509
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.233041116
Short name T547
Test name
Test status
Simulation time 170478063 ps
CPU time 2.93 seconds
Started Aug 13 05:21:47 PM PDT 24
Finished Aug 13 05:21:50 PM PDT 24
Peak memory 198100 kb
Host smart-247f37a6-3ef8-487b-bf0d-be68aa1f815a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233041116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.233041116
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.114233346
Short name T545
Test name
Test status
Simulation time 322251485 ps
CPU time 0.79 seconds
Started Aug 13 05:21:50 PM PDT 24
Finished Aug 13 05:21:51 PM PDT 24
Peak memory 194012 kb
Host smart-d91a597f-6d4f-4f73-aa3f-c760b51ed202
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114233346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.114233346
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2332845139
Short name T492
Test name
Test status
Simulation time 59522054 ps
CPU time 0.93 seconds
Started Aug 13 05:21:43 PM PDT 24
Finished Aug 13 05:21:44 PM PDT 24
Peak memory 197948 kb
Host smart-f42b6d95-0bae-4156-95bf-99f2d3081877
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332845139 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2332845139
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.4185846187
Short name T543
Test name
Test status
Simulation time 13204949 ps
CPU time 0.58 seconds
Started Aug 13 05:21:48 PM PDT 24
Finished Aug 13 05:21:48 PM PDT 24
Peak memory 183356 kb
Host smart-dce9211e-c00e-491f-8f8c-f90ea5d90794
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185846187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.4185846187
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2003084714
Short name T499
Test name
Test status
Simulation time 12400951 ps
CPU time 0.54 seconds
Started Aug 13 05:21:43 PM PDT 24
Finished Aug 13 05:21:44 PM PDT 24
Peak memory 182852 kb
Host smart-0269851a-54ec-4418-af02-f6ce0028b9dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003084714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2003084714
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.716043869
Short name T560
Test name
Test status
Simulation time 33883005 ps
CPU time 0.62 seconds
Started Aug 13 05:21:43 PM PDT 24
Finished Aug 13 05:21:43 PM PDT 24
Peak memory 192096 kb
Host smart-a0ca8780-bce3-47c6-89b7-36c922886f45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716043869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.716043869
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2173860223
Short name T471
Test name
Test status
Simulation time 510295331 ps
CPU time 2.24 seconds
Started Aug 13 05:21:56 PM PDT 24
Finished Aug 13 05:21:59 PM PDT 24
Peak memory 198056 kb
Host smart-c7dfa37e-06bc-47bd-9115-9ce3bffb2bc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173860223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2173860223
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3160326397
Short name T28
Test name
Test status
Simulation time 1907986900 ps
CPU time 1.37 seconds
Started Aug 13 05:22:04 PM PDT 24
Finished Aug 13 05:22:05 PM PDT 24
Peak memory 195816 kb
Host smart-4d1d25ca-83c1-4ea0-8b85-a8b4d49e8186
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160326397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3160326397
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.624639808
Short name T457
Test name
Test status
Simulation time 121382264 ps
CPU time 1.56 seconds
Started Aug 13 05:21:45 PM PDT 24
Finished Aug 13 05:21:47 PM PDT 24
Peak memory 198180 kb
Host smart-a9ec13cb-2cfa-45a1-bd74-3682b70ebb40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624639808 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.624639808
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.238009735
Short name T506
Test name
Test status
Simulation time 15481572 ps
CPU time 0.56 seconds
Started Aug 13 05:21:49 PM PDT 24
Finished Aug 13 05:21:49 PM PDT 24
Peak memory 183140 kb
Host smart-94dfac52-3779-4afa-8156-297ebc54bf5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238009735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.238009735
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1857494073
Short name T507
Test name
Test status
Simulation time 41262379 ps
CPU time 0.56 seconds
Started Aug 13 05:21:56 PM PDT 24
Finished Aug 13 05:21:56 PM PDT 24
Peak memory 183136 kb
Host smart-3a5555a1-abf4-4e55-afc9-9247e3b6cec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857494073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1857494073
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3850867844
Short name T73
Test name
Test status
Simulation time 22826264 ps
CPU time 0.7 seconds
Started Aug 13 05:22:02 PM PDT 24
Finished Aug 13 05:22:02 PM PDT 24
Peak memory 192280 kb
Host smart-44051b95-1845-491d-b958-492b59a0afeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850867844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3850867844
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1112481661
Short name T542
Test name
Test status
Simulation time 257502200 ps
CPU time 2.48 seconds
Started Aug 13 05:21:58 PM PDT 24
Finished Aug 13 05:22:01 PM PDT 24
Peak memory 198156 kb
Host smart-f522b366-6e40-412e-8044-39fb86806e97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112481661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1112481661
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1624355361
Short name T574
Test name
Test status
Simulation time 48454496 ps
CPU time 0.79 seconds
Started Aug 13 05:22:09 PM PDT 24
Finished Aug 13 05:22:15 PM PDT 24
Peak memory 193880 kb
Host smart-071ff1fb-880e-4221-9ec0-65ed7d64afa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624355361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1624355361
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.196712408
Short name T478
Test name
Test status
Simulation time 40040339 ps
CPU time 0.97 seconds
Started Aug 13 05:21:55 PM PDT 24
Finished Aug 13 05:21:56 PM PDT 24
Peak memory 198020 kb
Host smart-1ddf319e-1672-4c58-b0b4-4517d3a89557
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196712408 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.196712408
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1880972178
Short name T65
Test name
Test status
Simulation time 50660030 ps
CPU time 0.54 seconds
Started Aug 13 05:21:50 PM PDT 24
Finished Aug 13 05:21:51 PM PDT 24
Peak memory 183344 kb
Host smart-65b65e97-d311-435f-acf4-1412642bcedf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880972178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1880972178
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1261673753
Short name T517
Test name
Test status
Simulation time 134159133 ps
CPU time 0.53 seconds
Started Aug 13 05:21:49 PM PDT 24
Finished Aug 13 05:21:50 PM PDT 24
Peak memory 182696 kb
Host smart-347adf14-0e4a-45ef-852c-b02e13dfc27a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261673753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1261673753
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.761056413
Short name T31
Test name
Test status
Simulation time 15630980 ps
CPU time 0.65 seconds
Started Aug 13 05:21:50 PM PDT 24
Finished Aug 13 05:21:51 PM PDT 24
Peak memory 192664 kb
Host smart-04ca53f7-1e29-4ccd-a54a-ca194c1142a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761056413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.761056413
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2422000147
Short name T548
Test name
Test status
Simulation time 53250987 ps
CPU time 1.33 seconds
Started Aug 13 05:21:54 PM PDT 24
Finished Aug 13 05:21:55 PM PDT 24
Peak memory 198100 kb
Host smart-b08321dd-f566-4782-8622-7f4b9f71144a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422000147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2422000147
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1708418178
Short name T521
Test name
Test status
Simulation time 292806834 ps
CPU time 1.11 seconds
Started Aug 13 05:21:46 PM PDT 24
Finished Aug 13 05:21:47 PM PDT 24
Peak memory 183876 kb
Host smart-c2ccbc12-70ab-4669-aae3-05178622a2c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708418178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1708418178
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3496418222
Short name T556
Test name
Test status
Simulation time 32933551 ps
CPU time 0.77 seconds
Started Aug 13 05:21:54 PM PDT 24
Finished Aug 13 05:21:55 PM PDT 24
Peak memory 196148 kb
Host smart-a5fc3139-9d2a-4cda-9e89-b9fafdf2e1f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496418222 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3496418222
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1274543655
Short name T76
Test name
Test status
Simulation time 45416407 ps
CPU time 0.57 seconds
Started Aug 13 05:21:37 PM PDT 24
Finished Aug 13 05:21:38 PM PDT 24
Peak memory 183272 kb
Host smart-c12a3f20-7c2f-46f9-ac80-1c44769c95d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274543655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1274543655
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2657669574
Short name T502
Test name
Test status
Simulation time 111407821 ps
CPU time 0.51 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:09 PM PDT 24
Peak memory 183108 kb
Host smart-2811059c-abf8-467b-b224-bb50384c557d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657669574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2657669574
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1026072775
Short name T74
Test name
Test status
Simulation time 17389078 ps
CPU time 0.76 seconds
Started Aug 13 05:21:59 PM PDT 24
Finished Aug 13 05:22:00 PM PDT 24
Peak memory 193956 kb
Host smart-f1cedd77-171c-46d8-a2a4-a6b5f9707b30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026072775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1026072775
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1604157394
Short name T578
Test name
Test status
Simulation time 379532463 ps
CPU time 1.58 seconds
Started Aug 13 05:21:47 PM PDT 24
Finished Aug 13 05:21:53 PM PDT 24
Peak memory 198164 kb
Host smart-6fcfed7e-2f0a-4a23-93a4-10e6f40b735d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604157394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1604157394
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4021585802
Short name T501
Test name
Test status
Simulation time 306466107 ps
CPU time 1.33 seconds
Started Aug 13 05:21:45 PM PDT 24
Finished Aug 13 05:21:46 PM PDT 24
Peak memory 183812 kb
Host smart-e9db0760-7977-4963-8e0f-fcba60c3ea75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021585802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.4021585802
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.873254207
Short name T555
Test name
Test status
Simulation time 85524654 ps
CPU time 0.79 seconds
Started Aug 13 05:22:07 PM PDT 24
Finished Aug 13 05:22:08 PM PDT 24
Peak memory 195364 kb
Host smart-c9694d85-8bb8-4d9a-9451-64f317ce10a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873254207 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.873254207
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1729353636
Short name T30
Test name
Test status
Simulation time 16171082 ps
CPU time 0.6 seconds
Started Aug 13 05:21:50 PM PDT 24
Finished Aug 13 05:21:51 PM PDT 24
Peak memory 183236 kb
Host smart-6f6bb989-87be-4742-bb52-4f9e3b41453f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729353636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1729353636
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2690031313
Short name T473
Test name
Test status
Simulation time 21271874 ps
CPU time 0.55 seconds
Started Aug 13 05:21:56 PM PDT 24
Finished Aug 13 05:21:57 PM PDT 24
Peak memory 182660 kb
Host smart-bf57a216-5591-43ad-89ff-e64571738500
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690031313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2690031313
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3850183040
Short name T509
Test name
Test status
Simulation time 20596393 ps
CPU time 0.66 seconds
Started Aug 13 05:21:56 PM PDT 24
Finished Aug 13 05:21:57 PM PDT 24
Peak memory 191912 kb
Host smart-f0740115-ab04-487f-a36b-ee439413fe04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850183040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3850183040
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3593616524
Short name T484
Test name
Test status
Simulation time 38759920 ps
CPU time 1.65 seconds
Started Aug 13 05:22:02 PM PDT 24
Finished Aug 13 05:22:04 PM PDT 24
Peak memory 198084 kb
Host smart-8551c3f5-a3d2-4841-8495-893d393c291b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593616524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3593616524
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2351419304
Short name T487
Test name
Test status
Simulation time 86421179 ps
CPU time 1.07 seconds
Started Aug 13 05:22:06 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 195556 kb
Host smart-fb3768a3-a8ec-4ed3-a341-01d19de78e1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351419304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2351419304
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1155313394
Short name T64
Test name
Test status
Simulation time 227523446 ps
CPU time 0.77 seconds
Started Aug 13 05:21:21 PM PDT 24
Finished Aug 13 05:21:22 PM PDT 24
Peak memory 183352 kb
Host smart-bdf99307-0f26-4b2a-95d1-8495e0048d18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155313394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1155313394
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.4101396168
Short name T70
Test name
Test status
Simulation time 63128274 ps
CPU time 2.33 seconds
Started Aug 13 05:21:31 PM PDT 24
Finished Aug 13 05:21:34 PM PDT 24
Peak memory 194548 kb
Host smart-c1bec7be-d4c1-4cf7-ba4c-2c9d22868bc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101396168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.4101396168
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3603912720
Short name T63
Test name
Test status
Simulation time 69737313 ps
CPU time 0.59 seconds
Started Aug 13 05:21:44 PM PDT 24
Finished Aug 13 05:21:44 PM PDT 24
Peak memory 192548 kb
Host smart-c7d3a451-5300-4e4e-b59d-6c45ccc1c28e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603912720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3603912720
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.171235869
Short name T571
Test name
Test status
Simulation time 45542207 ps
CPU time 0.76 seconds
Started Aug 13 05:21:39 PM PDT 24
Finished Aug 13 05:21:40 PM PDT 24
Peak memory 196340 kb
Host smart-28bf296b-b185-422c-965c-a64a91b5550b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171235869 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.171235869
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.700558448
Short name T515
Test name
Test status
Simulation time 20256632 ps
CPU time 0.58 seconds
Started Aug 13 05:21:51 PM PDT 24
Finished Aug 13 05:21:52 PM PDT 24
Peak memory 183392 kb
Host smart-d997a721-5381-42b0-b18a-7b3520180f34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700558448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.700558448
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.959348447
Short name T503
Test name
Test status
Simulation time 41081711 ps
CPU time 0.53 seconds
Started Aug 13 05:21:35 PM PDT 24
Finished Aug 13 05:21:36 PM PDT 24
Peak memory 182688 kb
Host smart-6150e636-0e74-4cb5-af90-05668073eb5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959348447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.959348447
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.349559280
Short name T525
Test name
Test status
Simulation time 23407894 ps
CPU time 0.6 seconds
Started Aug 13 05:21:21 PM PDT 24
Finished Aug 13 05:21:21 PM PDT 24
Peak memory 192660 kb
Host smart-4c58a844-5fa8-4301-93e1-daea0330e040
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349559280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.349559280
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2850897653
Short name T534
Test name
Test status
Simulation time 833416309 ps
CPU time 2.71 seconds
Started Aug 13 05:21:36 PM PDT 24
Finished Aug 13 05:21:40 PM PDT 24
Peak memory 198060 kb
Host smart-21ff5d3b-d20b-4402-9056-af4ce5fa8fe0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850897653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2850897653
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3542009117
Short name T83
Test name
Test status
Simulation time 89620668 ps
CPU time 1.11 seconds
Started Aug 13 05:21:21 PM PDT 24
Finished Aug 13 05:21:22 PM PDT 24
Peak memory 195608 kb
Host smart-a93511b3-e867-480e-bc8e-a659301ef288
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542009117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3542009117
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2231079240
Short name T539
Test name
Test status
Simulation time 16110458 ps
CPU time 0.56 seconds
Started Aug 13 05:22:01 PM PDT 24
Finished Aug 13 05:22:02 PM PDT 24
Peak memory 183180 kb
Host smart-61f268d2-c18b-4703-85b6-c09413379c85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231079240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2231079240
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.847235449
Short name T461
Test name
Test status
Simulation time 44291924 ps
CPU time 0.59 seconds
Started Aug 13 05:22:05 PM PDT 24
Finished Aug 13 05:22:05 PM PDT 24
Peak memory 183184 kb
Host smart-1534de7e-171b-4010-9b34-2b96b2de77bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847235449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.847235449
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3324055
Short name T498
Test name
Test status
Simulation time 19378460 ps
CPU time 0.56 seconds
Started Aug 13 05:21:51 PM PDT 24
Finished Aug 13 05:21:52 PM PDT 24
Peak memory 183156 kb
Host smart-5b750ee7-d7a4-49e0-a140-649716b2892e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3324055
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.764619141
Short name T518
Test name
Test status
Simulation time 14481731 ps
CPU time 0.55 seconds
Started Aug 13 05:21:54 PM PDT 24
Finished Aug 13 05:21:55 PM PDT 24
Peak memory 182708 kb
Host smart-248d961d-eeda-42fe-8073-0d4a89751a80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764619141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.764619141
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1662966667
Short name T561
Test name
Test status
Simulation time 25674675 ps
CPU time 0.58 seconds
Started Aug 13 05:21:56 PM PDT 24
Finished Aug 13 05:21:57 PM PDT 24
Peak memory 183236 kb
Host smart-804de7e2-23c6-4dab-98b0-9e93ccc7e5a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662966667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1662966667
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3460274485
Short name T537
Test name
Test status
Simulation time 18955677 ps
CPU time 0.56 seconds
Started Aug 13 05:21:56 PM PDT 24
Finished Aug 13 05:21:56 PM PDT 24
Peak memory 183280 kb
Host smart-e07e3128-134a-4c5f-8545-fb7862c400ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460274485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3460274485
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.188967751
Short name T456
Test name
Test status
Simulation time 37917597 ps
CPU time 0.52 seconds
Started Aug 13 05:22:04 PM PDT 24
Finished Aug 13 05:22:05 PM PDT 24
Peak memory 182648 kb
Host smart-d185a1bb-cb31-43dc-b0a2-28f804ba8ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188967751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.188967751
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2703278503
Short name T568
Test name
Test status
Simulation time 21125587 ps
CPU time 0.54 seconds
Started Aug 13 05:22:00 PM PDT 24
Finished Aug 13 05:22:01 PM PDT 24
Peak memory 182692 kb
Host smart-1ac7d39a-e094-49fc-8093-cf9e429827ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703278503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2703278503
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2472619046
Short name T541
Test name
Test status
Simulation time 18055668 ps
CPU time 0.56 seconds
Started Aug 13 05:22:05 PM PDT 24
Finished Aug 13 05:22:06 PM PDT 24
Peak memory 183200 kb
Host smart-913f16be-29b1-43dd-bcaf-4e515d19672d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472619046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2472619046
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2393161893
Short name T475
Test name
Test status
Simulation time 36254129 ps
CPU time 0.53 seconds
Started Aug 13 05:21:52 PM PDT 24
Finished Aug 13 05:21:52 PM PDT 24
Peak memory 182668 kb
Host smart-b9ea2fa3-8fc2-432e-9150-02b4704f2e1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393161893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2393161893
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3979069131
Short name T72
Test name
Test status
Simulation time 55852030 ps
CPU time 0.78 seconds
Started Aug 13 05:21:29 PM PDT 24
Finished Aug 13 05:21:30 PM PDT 24
Peak memory 193296 kb
Host smart-955297ec-6d87-4378-a401-13b0fccce826
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979069131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3979069131
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3493466218
Short name T61
Test name
Test status
Simulation time 464543648 ps
CPU time 3.08 seconds
Started Aug 13 05:21:33 PM PDT 24
Finished Aug 13 05:21:37 PM PDT 24
Peak memory 191736 kb
Host smart-4235582f-545a-4bbb-9d12-e35599cc08af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493466218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3493466218
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.133684026
Short name T66
Test name
Test status
Simulation time 39301734 ps
CPU time 0.53 seconds
Started Aug 13 05:21:53 PM PDT 24
Finished Aug 13 05:21:54 PM PDT 24
Peak memory 182864 kb
Host smart-902267bc-c7d0-40d8-a8ab-2dbd10854e97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133684026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.133684026
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3478919433
Short name T482
Test name
Test status
Simulation time 122743737 ps
CPU time 1.56 seconds
Started Aug 13 05:21:23 PM PDT 24
Finished Aug 13 05:21:25 PM PDT 24
Peak memory 198172 kb
Host smart-562eefee-fb3a-4a39-9b60-dfc0d9594c06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478919433 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3478919433
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.901640886
Short name T526
Test name
Test status
Simulation time 15492812 ps
CPU time 0.57 seconds
Started Aug 13 05:21:44 PM PDT 24
Finished Aug 13 05:21:45 PM PDT 24
Peak memory 183364 kb
Host smart-3b138859-e9f0-447d-a5d0-57153d948e1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901640886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.901640886
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2521459546
Short name T552
Test name
Test status
Simulation time 17566056 ps
CPU time 0.57 seconds
Started Aug 13 05:21:42 PM PDT 24
Finished Aug 13 05:21:43 PM PDT 24
Peak memory 183220 kb
Host smart-4a383ebd-146e-447d-84e9-adc87fe5eb11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521459546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2521459546
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2076502318
Short name T496
Test name
Test status
Simulation time 55892614 ps
CPU time 0.61 seconds
Started Aug 13 05:21:38 PM PDT 24
Finished Aug 13 05:21:39 PM PDT 24
Peak memory 192604 kb
Host smart-87ad0072-31ba-418a-bf19-abab183028fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076502318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2076502318
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3186082233
Short name T532
Test name
Test status
Simulation time 147870696 ps
CPU time 0.99 seconds
Started Aug 13 05:21:30 PM PDT 24
Finished Aug 13 05:21:31 PM PDT 24
Peak memory 196028 kb
Host smart-bababc84-38d1-403c-be63-17f0cf0e1234
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186082233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3186082233
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.439061889
Short name T82
Test name
Test status
Simulation time 390392799 ps
CPU time 1.05 seconds
Started Aug 13 05:21:27 PM PDT 24
Finished Aug 13 05:21:29 PM PDT 24
Peak memory 195744 kb
Host smart-69b04507-3251-44df-b68e-326bfc233164
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439061889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.439061889
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2625751511
Short name T505
Test name
Test status
Simulation time 14699825 ps
CPU time 0.51 seconds
Started Aug 13 05:22:13 PM PDT 24
Finished Aug 13 05:22:14 PM PDT 24
Peak memory 182684 kb
Host smart-9b405dd6-74d1-4dc3-9fb3-76dcb7feb4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625751511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2625751511
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.115130444
Short name T459
Test name
Test status
Simulation time 27260759 ps
CPU time 0.53 seconds
Started Aug 13 05:22:01 PM PDT 24
Finished Aug 13 05:22:02 PM PDT 24
Peak memory 182688 kb
Host smart-b08f5f85-54f0-4591-94e8-1b37c7b19a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115130444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.115130444
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.267721987
Short name T464
Test name
Test status
Simulation time 14107646 ps
CPU time 0.54 seconds
Started Aug 13 05:21:53 PM PDT 24
Finished Aug 13 05:21:54 PM PDT 24
Peak memory 182692 kb
Host smart-94525aa5-1c5b-4fef-b8a9-7dcb60668015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267721987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.267721987
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1168737636
Short name T469
Test name
Test status
Simulation time 12605962 ps
CPU time 0.53 seconds
Started Aug 13 05:22:00 PM PDT 24
Finished Aug 13 05:22:01 PM PDT 24
Peak memory 182892 kb
Host smart-2bc0889e-1f19-4bba-952d-19b1cb09973b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168737636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1168737636
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3748173283
Short name T463
Test name
Test status
Simulation time 27721287 ps
CPU time 0.55 seconds
Started Aug 13 05:22:19 PM PDT 24
Finished Aug 13 05:22:19 PM PDT 24
Peak memory 183200 kb
Host smart-91605ba1-8e81-43f0-bfb1-67984f17ebb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748173283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3748173283
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2199304965
Short name T553
Test name
Test status
Simulation time 14425868 ps
CPU time 0.55 seconds
Started Aug 13 05:22:08 PM PDT 24
Finished Aug 13 05:22:09 PM PDT 24
Peak memory 183248 kb
Host smart-d0978842-3909-48ea-95d8-57fad84e1dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199304965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2199304965
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.585676143
Short name T483
Test name
Test status
Simulation time 65038602 ps
CPU time 0.58 seconds
Started Aug 13 05:22:04 PM PDT 24
Finished Aug 13 05:22:05 PM PDT 24
Peak memory 183200 kb
Host smart-afc68545-e62e-47ed-add6-f6b95ab0fed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585676143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.585676143
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.4244279341
Short name T540
Test name
Test status
Simulation time 17512252 ps
CPU time 0.57 seconds
Started Aug 13 05:21:54 PM PDT 24
Finished Aug 13 05:21:55 PM PDT 24
Peak memory 183100 kb
Host smart-ecd4319d-6aa9-46e9-95ff-3facee7df788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244279341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.4244279341
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2626038908
Short name T554
Test name
Test status
Simulation time 15809059 ps
CPU time 0.56 seconds
Started Aug 13 05:21:59 PM PDT 24
Finished Aug 13 05:22:00 PM PDT 24
Peak memory 183124 kb
Host smart-45385cd5-1422-490a-a396-7ff829d7f5da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626038908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2626038908
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1269855486
Short name T474
Test name
Test status
Simulation time 12245783 ps
CPU time 0.51 seconds
Started Aug 13 05:22:10 PM PDT 24
Finished Aug 13 05:22:10 PM PDT 24
Peak memory 183160 kb
Host smart-b0e9b533-23de-4d0c-b536-a5145f2df403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269855486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1269855486
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.747083522
Short name T524
Test name
Test status
Simulation time 103877828 ps
CPU time 0.82 seconds
Started Aug 13 05:21:42 PM PDT 24
Finished Aug 13 05:21:43 PM PDT 24
Peak memory 193340 kb
Host smart-10441c02-f3f7-498b-8833-f5d5b8532fc1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747083522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.747083522
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.367009878
Short name T53
Test name
Test status
Simulation time 26515201 ps
CPU time 0.55 seconds
Started Aug 13 05:21:27 PM PDT 24
Finished Aug 13 05:21:28 PM PDT 24
Peak memory 183360 kb
Host smart-e5b45fab-ad1c-42ef-852f-7fed5c40aa04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367009878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.367009878
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3143746298
Short name T51
Test name
Test status
Simulation time 32398638 ps
CPU time 0.84 seconds
Started Aug 13 05:21:41 PM PDT 24
Finished Aug 13 05:21:42 PM PDT 24
Peak memory 195524 kb
Host smart-dc181ba6-3b19-44fa-950e-1f215e49b278
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143746298 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3143746298
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3166222681
Short name T536
Test name
Test status
Simulation time 14205506 ps
CPU time 0.55 seconds
Started Aug 13 05:21:43 PM PDT 24
Finished Aug 13 05:21:44 PM PDT 24
Peak memory 183364 kb
Host smart-2571096f-8914-4297-afef-94de40f49c32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166222681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3166222681
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.4289852133
Short name T477
Test name
Test status
Simulation time 13194287 ps
CPU time 0.55 seconds
Started Aug 13 05:21:45 PM PDT 24
Finished Aug 13 05:21:46 PM PDT 24
Peak memory 183176 kb
Host smart-ec577a19-015e-4709-87ba-bff1b0e9c1d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289852133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.4289852133
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.4171527782
Short name T75
Test name
Test status
Simulation time 289474586 ps
CPU time 0.62 seconds
Started Aug 13 05:21:53 PM PDT 24
Finished Aug 13 05:21:54 PM PDT 24
Peak memory 192608 kb
Host smart-7fbd0707-65c6-4b8a-b829-6bd3a3505216
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171527782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.4171527782
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1092542843
Short name T493
Test name
Test status
Simulation time 1178212316 ps
CPU time 2.12 seconds
Started Aug 13 05:21:27 PM PDT 24
Finished Aug 13 05:21:29 PM PDT 24
Peak memory 198132 kb
Host smart-57e1c691-f1cb-40be-b6c0-11062a6a2c67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092542843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1092542843
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1377609872
Short name T572
Test name
Test status
Simulation time 349096855 ps
CPU time 1.06 seconds
Started Aug 13 05:21:30 PM PDT 24
Finished Aug 13 05:21:32 PM PDT 24
Peak memory 195952 kb
Host smart-46343a29-5bbd-4e7c-ad62-37008f3630da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377609872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1377609872
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1559711465
Short name T468
Test name
Test status
Simulation time 26328843 ps
CPU time 0.52 seconds
Started Aug 13 05:21:50 PM PDT 24
Finished Aug 13 05:21:50 PM PDT 24
Peak memory 182692 kb
Host smart-60e43bfd-dbe3-4a4c-abb9-23785af66597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559711465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1559711465
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3610768759
Short name T522
Test name
Test status
Simulation time 18572803 ps
CPU time 0.56 seconds
Started Aug 13 05:21:50 PM PDT 24
Finished Aug 13 05:21:50 PM PDT 24
Peak memory 183220 kb
Host smart-225b6fe6-0be3-45ae-9355-a6b812524544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610768759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3610768759
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1071363738
Short name T481
Test name
Test status
Simulation time 20412865 ps
CPU time 0.54 seconds
Started Aug 13 05:21:58 PM PDT 24
Finished Aug 13 05:21:59 PM PDT 24
Peak memory 183276 kb
Host smart-78f7b23f-b1b6-429c-94c6-e6b52cd8c7df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071363738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1071363738
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.67544156
Short name T523
Test name
Test status
Simulation time 29664796 ps
CPU time 0.56 seconds
Started Aug 13 05:22:20 PM PDT 24
Finished Aug 13 05:22:20 PM PDT 24
Peak memory 183268 kb
Host smart-dd16831d-d7a5-45be-8e61-85d207120139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67544156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.67544156
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2682336227
Short name T466
Test name
Test status
Simulation time 21740853 ps
CPU time 0.56 seconds
Started Aug 13 05:22:20 PM PDT 24
Finished Aug 13 05:22:20 PM PDT 24
Peak memory 183028 kb
Host smart-6e7f5b5b-6436-4e14-9b7a-524dfe1a463a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682336227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2682336227
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1169496136
Short name T462
Test name
Test status
Simulation time 25835207 ps
CPU time 0.54 seconds
Started Aug 13 05:21:55 PM PDT 24
Finished Aug 13 05:21:56 PM PDT 24
Peak memory 183408 kb
Host smart-415017aa-94d8-4824-8e07-02240b2e6588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169496136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1169496136
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1039397218
Short name T577
Test name
Test status
Simulation time 17054002 ps
CPU time 0.59 seconds
Started Aug 13 05:21:55 PM PDT 24
Finished Aug 13 05:21:55 PM PDT 24
Peak memory 183168 kb
Host smart-35b8f092-f452-4506-aed9-28ccc690874d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039397218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1039397218
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.756342106
Short name T514
Test name
Test status
Simulation time 22683906 ps
CPU time 0.59 seconds
Started Aug 13 05:21:52 PM PDT 24
Finished Aug 13 05:21:53 PM PDT 24
Peak memory 182680 kb
Host smart-677f213c-72ef-442d-a01c-898f2b1b8a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756342106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.756342106
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.97390198
Short name T569
Test name
Test status
Simulation time 18758953 ps
CPU time 0.56 seconds
Started Aug 13 05:21:53 PM PDT 24
Finished Aug 13 05:21:54 PM PDT 24
Peak memory 183136 kb
Host smart-40512da9-4109-44b3-b75c-ecbda33320dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97390198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.97390198
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2899072858
Short name T495
Test name
Test status
Simulation time 29742140 ps
CPU time 0.54 seconds
Started Aug 13 05:22:06 PM PDT 24
Finished Aug 13 05:22:07 PM PDT 24
Peak memory 183248 kb
Host smart-bbc2c4fe-3d9b-412a-bdaf-b4a46777c2d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899072858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2899072858
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.4117637607
Short name T529
Test name
Test status
Simulation time 328766487 ps
CPU time 1.22 seconds
Started Aug 13 05:21:44 PM PDT 24
Finished Aug 13 05:21:45 PM PDT 24
Peak memory 198176 kb
Host smart-dcf79341-47c9-4d49-99f9-6b5cecd325b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117637607 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.4117637607
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2233657295
Short name T59
Test name
Test status
Simulation time 23441103 ps
CPU time 0.54 seconds
Started Aug 13 05:21:49 PM PDT 24
Finished Aug 13 05:21:50 PM PDT 24
Peak memory 183392 kb
Host smart-70e1e9e2-fac9-4aee-b8ed-e0b414da855c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233657295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2233657295
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1214705802
Short name T470
Test name
Test status
Simulation time 14275315 ps
CPU time 0.59 seconds
Started Aug 13 05:21:47 PM PDT 24
Finished Aug 13 05:21:48 PM PDT 24
Peak memory 182688 kb
Host smart-5001f059-3ae1-45dd-8a77-3f19062a6c9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214705802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1214705802
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3472096566
Short name T581
Test name
Test status
Simulation time 95246988 ps
CPU time 0.64 seconds
Started Aug 13 05:21:49 PM PDT 24
Finished Aug 13 05:21:50 PM PDT 24
Peak memory 192740 kb
Host smart-c04c227e-6481-4534-bbb8-a2f3d9fa41f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472096566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3472096566
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.374430643
Short name T472
Test name
Test status
Simulation time 127464726 ps
CPU time 1.82 seconds
Started Aug 13 05:21:48 PM PDT 24
Finished Aug 13 05:21:50 PM PDT 24
Peak memory 198072 kb
Host smart-4efc7518-6de4-48d1-9e05-a5823961701e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374430643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.374430643
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.585117144
Short name T79
Test name
Test status
Simulation time 319627166 ps
CPU time 1.1 seconds
Started Aug 13 05:21:45 PM PDT 24
Finished Aug 13 05:21:46 PM PDT 24
Peak memory 195720 kb
Host smart-754d74ec-5dd1-45fd-9852-c2b264deb229
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585117144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.585117144
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2579561653
Short name T486
Test name
Test status
Simulation time 20818539 ps
CPU time 0.67 seconds
Started Aug 13 05:21:48 PM PDT 24
Finished Aug 13 05:21:49 PM PDT 24
Peak memory 194180 kb
Host smart-f429ab5e-f7ca-4ad9-bb22-a04e677238e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579561653 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2579561653
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1633379492
Short name T480
Test name
Test status
Simulation time 55512089 ps
CPU time 0.55 seconds
Started Aug 13 05:21:35 PM PDT 24
Finished Aug 13 05:21:35 PM PDT 24
Peak memory 183380 kb
Host smart-d6fb24fd-add3-4905-b761-7779e19781e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633379492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1633379492
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3630157269
Short name T476
Test name
Test status
Simulation time 55036643 ps
CPU time 0.53 seconds
Started Aug 13 05:21:20 PM PDT 24
Finished Aug 13 05:21:21 PM PDT 24
Peak memory 182620 kb
Host smart-82bbfe45-e154-472b-8452-c6d0680ac10e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630157269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3630157269
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1497108097
Short name T49
Test name
Test status
Simulation time 20992695 ps
CPU time 0.59 seconds
Started Aug 13 05:21:56 PM PDT 24
Finished Aug 13 05:21:57 PM PDT 24
Peak memory 192524 kb
Host smart-427a6658-5616-412b-a69b-4c96537b3ce8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497108097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1497108097
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.823588579
Short name T508
Test name
Test status
Simulation time 195659504 ps
CPU time 1.26 seconds
Started Aug 13 05:21:51 PM PDT 24
Finished Aug 13 05:21:52 PM PDT 24
Peak memory 198148 kb
Host smart-c03d6e9f-1984-4e09-93fc-780867c04c3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823588579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.823588579
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.504559743
Short name T579
Test name
Test status
Simulation time 394963550 ps
CPU time 1.3 seconds
Started Aug 13 05:21:21 PM PDT 24
Finished Aug 13 05:21:22 PM PDT 24
Peak memory 194944 kb
Host smart-add52d94-c8c2-4e20-9dd0-cf642cfa375f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504559743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.504559743
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.597955605
Short name T533
Test name
Test status
Simulation time 37921883 ps
CPU time 0.64 seconds
Started Aug 13 05:21:27 PM PDT 24
Finished Aug 13 05:21:28 PM PDT 24
Peak memory 194452 kb
Host smart-463fc5cb-402b-41f0-9641-0d7f9a1bbe6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597955605 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.597955605
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1348093738
Short name T583
Test name
Test status
Simulation time 36660727 ps
CPU time 0.55 seconds
Started Aug 13 05:21:48 PM PDT 24
Finished Aug 13 05:21:49 PM PDT 24
Peak memory 183244 kb
Host smart-42488eaf-1c27-46bd-9404-01ffe5cbbfb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348093738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1348093738
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1915988679
Short name T575
Test name
Test status
Simulation time 98661502 ps
CPU time 0.55 seconds
Started Aug 13 05:21:43 PM PDT 24
Finished Aug 13 05:21:44 PM PDT 24
Peak memory 182800 kb
Host smart-ba62f5a6-7037-4b50-8531-e22d8ce8bf9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915988679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1915988679
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.368585177
Short name T520
Test name
Test status
Simulation time 79061187 ps
CPU time 0.75 seconds
Started Aug 13 05:22:02 PM PDT 24
Finished Aug 13 05:22:03 PM PDT 24
Peak memory 192864 kb
Host smart-97c6d954-c9b7-456d-bd69-00f01a87c981
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368585177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.368585177
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1027488623
Short name T465
Test name
Test status
Simulation time 125676336 ps
CPU time 2.08 seconds
Started Aug 13 05:22:02 PM PDT 24
Finished Aug 13 05:22:04 PM PDT 24
Peak memory 198092 kb
Host smart-63187652-57f1-4336-a133-fd88baf2941d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027488623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1027488623
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.84823693
Short name T570
Test name
Test status
Simulation time 152744895 ps
CPU time 0.79 seconds
Started Aug 13 05:21:41 PM PDT 24
Finished Aug 13 05:21:42 PM PDT 24
Peak memory 193012 kb
Host smart-201c84d9-eda9-4ec7-997c-dbc04c2a16ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84823693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg
_err.84823693
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2070151914
Short name T559
Test name
Test status
Simulation time 41438187 ps
CPU time 0.87 seconds
Started Aug 13 05:21:59 PM PDT 24
Finished Aug 13 05:22:00 PM PDT 24
Peak memory 196668 kb
Host smart-d67886d3-71b6-4ee4-af3c-31afca1b28d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070151914 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2070151914
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.142732715
Short name T67
Test name
Test status
Simulation time 15767743 ps
CPU time 0.55 seconds
Started Aug 13 05:21:50 PM PDT 24
Finished Aug 13 05:21:50 PM PDT 24
Peak memory 183516 kb
Host smart-de8524ae-41f7-40d1-a7f5-6c63c6f9eee6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142732715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.142732715
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3015799237
Short name T510
Test name
Test status
Simulation time 12638635 ps
CPU time 0.55 seconds
Started Aug 13 05:21:55 PM PDT 24
Finished Aug 13 05:21:55 PM PDT 24
Peak memory 182804 kb
Host smart-39f35ad9-a346-40cd-946a-1ffb0a9a93ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015799237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3015799237
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.333195860
Short name T544
Test name
Test status
Simulation time 18880444 ps
CPU time 0.62 seconds
Started Aug 13 05:21:39 PM PDT 24
Finished Aug 13 05:21:40 PM PDT 24
Peak memory 192544 kb
Host smart-ddac8db1-5d06-45e0-88ae-3a831eb3bae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333195860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.333195860
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3406016622
Short name T504
Test name
Test status
Simulation time 99599970 ps
CPU time 1.21 seconds
Started Aug 13 05:21:39 PM PDT 24
Finished Aug 13 05:21:40 PM PDT 24
Peak memory 196548 kb
Host smart-babd71c4-cf81-48de-8fc0-1862ce1ab956
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406016622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3406016622
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.541689781
Short name T494
Test name
Test status
Simulation time 114570809 ps
CPU time 1.07 seconds
Started Aug 13 05:21:43 PM PDT 24
Finished Aug 13 05:21:44 PM PDT 24
Peak memory 183864 kb
Host smart-45c36e1e-7d99-4a06-868f-2172be379efd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541689781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.541689781
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3314661078
Short name T528
Test name
Test status
Simulation time 110705146 ps
CPU time 0.89 seconds
Started Aug 13 05:21:42 PM PDT 24
Finished Aug 13 05:21:43 PM PDT 24
Peak memory 197236 kb
Host smart-45dbe448-df5c-49d4-b0ce-fe1561c38624
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314661078 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3314661078
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3640974690
Short name T29
Test name
Test status
Simulation time 51133217 ps
CPU time 0.53 seconds
Started Aug 13 05:22:12 PM PDT 24
Finished Aug 13 05:22:13 PM PDT 24
Peak memory 183380 kb
Host smart-fea855eb-698f-417f-872f-78cd61713b2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640974690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3640974690
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2976576121
Short name T550
Test name
Test status
Simulation time 55499428 ps
CPU time 0.54 seconds
Started Aug 13 05:22:00 PM PDT 24
Finished Aug 13 05:22:06 PM PDT 24
Peak memory 183220 kb
Host smart-b9f27d9e-2e30-4f43-9a07-a4060ac667e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976576121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2976576121
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2668375698
Short name T77
Test name
Test status
Simulation time 204635519 ps
CPU time 0.76 seconds
Started Aug 13 05:22:02 PM PDT 24
Finished Aug 13 05:22:03 PM PDT 24
Peak memory 194016 kb
Host smart-b79e7cde-a298-4313-9cda-08091b4bb482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668375698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2668375698
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3082520507
Short name T467
Test name
Test status
Simulation time 234205547 ps
CPU time 1.28 seconds
Started Aug 13 05:21:48 PM PDT 24
Finished Aug 13 05:21:50 PM PDT 24
Peak memory 197964 kb
Host smart-d4d4c7df-8f32-4a74-9f2a-403e7687f8c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082520507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3082520507
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3103172357
Short name T26
Test name
Test status
Simulation time 76830604 ps
CPU time 0.84 seconds
Started Aug 13 05:21:47 PM PDT 24
Finished Aug 13 05:21:48 PM PDT 24
Peak memory 194152 kb
Host smart-1d52d45b-1f60-4c5e-8cfa-9caefc8fbd2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103172357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3103172357
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3841402350
Short name T370
Test name
Test status
Simulation time 12724189569 ps
CPU time 19.02 seconds
Started Aug 13 06:08:42 PM PDT 24
Finished Aug 13 06:09:01 PM PDT 24
Peak memory 183560 kb
Host smart-76125e7c-ecb0-4952-86ef-4b912a024ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841402350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3841402350
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.589622581
Short name T391
Test name
Test status
Simulation time 197657695 ps
CPU time 1.01 seconds
Started Aug 13 06:08:50 PM PDT 24
Finished Aug 13 06:08:51 PM PDT 24
Peak memory 192156 kb
Host smart-af8d4733-a800-4421-9931-be2b334a4748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589622581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.589622581
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.672031025
Short name T433
Test name
Test status
Simulation time 59633330526 ps
CPU time 46.44 seconds
Started Aug 13 06:08:49 PM PDT 24
Finished Aug 13 06:09:36 PM PDT 24
Peak memory 183596 kb
Host smart-3ff1627d-efbe-49e9-ab31-34a92fa05d1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672031025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.672031025
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2522254362
Short name T450
Test name
Test status
Simulation time 59910751100 ps
CPU time 82.75 seconds
Started Aug 13 06:08:50 PM PDT 24
Finished Aug 13 06:10:13 PM PDT 24
Peak memory 183560 kb
Host smart-41fa14cf-859f-4737-a878-954d03e2af4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522254362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2522254362
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3845424631
Short name T23
Test name
Test status
Simulation time 800990946 ps
CPU time 1.11 seconds
Started Aug 13 06:08:48 PM PDT 24
Finished Aug 13 06:08:49 PM PDT 24
Peak memory 183280 kb
Host smart-4e7a73b9-f5f9-4e5a-8807-238f37cb05a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845424631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3845424631
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1403828695
Short name T15
Test name
Test status
Simulation time 313642304 ps
CPU time 0.88 seconds
Started Aug 13 06:08:49 PM PDT 24
Finished Aug 13 06:08:50 PM PDT 24
Peak memory 215112 kb
Host smart-2039ea36-7d21-4437-a42c-2a08857d53d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403828695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1403828695
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3318230857
Short name T209
Test name
Test status
Simulation time 623828649381 ps
CPU time 302.03 seconds
Started Aug 13 06:08:49 PM PDT 24
Finished Aug 13 06:13:51 PM PDT 24
Peak memory 191780 kb
Host smart-39dabce8-4190-4940-abd4-9febb5c7dd42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318230857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3318230857
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2367566551
Short name T38
Test name
Test status
Simulation time 1127039479 ps
CPU time 15.22 seconds
Started Aug 13 06:08:50 PM PDT 24
Finished Aug 13 06:09:06 PM PDT 24
Peak memory 193588 kb
Host smart-464b4adb-d90b-4e16-a4ad-49528260f08c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367566551 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2367566551
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2680048525
Short name T407
Test name
Test status
Simulation time 150811251636 ps
CPU time 230.31 seconds
Started Aug 13 06:09:21 PM PDT 24
Finished Aug 13 06:13:12 PM PDT 24
Peak memory 183596 kb
Host smart-467ec0bf-b9d4-42d0-9923-807cd0151aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680048525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2680048525
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1059764092
Short name T24
Test name
Test status
Simulation time 98115986288 ps
CPU time 166.96 seconds
Started Aug 13 06:09:21 PM PDT 24
Finished Aug 13 06:12:08 PM PDT 24
Peak memory 191772 kb
Host smart-ca6b6665-bc53-40b4-be81-e397d01f5f75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059764092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1059764092
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3428361068
Short name T163
Test name
Test status
Simulation time 112306548107 ps
CPU time 211.47 seconds
Started Aug 13 06:09:23 PM PDT 24
Finished Aug 13 06:12:54 PM PDT 24
Peak memory 191680 kb
Host smart-ce415add-4af4-44cd-89bb-1db03c2f8bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428361068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3428361068
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.1834641357
Short name T413
Test name
Test status
Simulation time 1649057354 ps
CPU time 14.63 seconds
Started Aug 13 06:09:20 PM PDT 24
Finished Aug 13 06:09:35 PM PDT 24
Peak memory 198204 kb
Host smart-9810a1f3-49dc-47e0-abf2-c36bdbd04555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834641357 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.1834641357
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.3734102681
Short name T90
Test name
Test status
Simulation time 405304300721 ps
CPU time 436.03 seconds
Started Aug 13 06:12:26 PM PDT 24
Finished Aug 13 06:19:43 PM PDT 24
Peak memory 191784 kb
Host smart-eab27ad6-cafd-4360-b0be-00f96f3e0b8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734102681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3734102681
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.2409219725
Short name T325
Test name
Test status
Simulation time 28174720784 ps
CPU time 46.37 seconds
Started Aug 13 06:12:26 PM PDT 24
Finished Aug 13 06:13:13 PM PDT 24
Peak memory 183592 kb
Host smart-a20bb0b6-3a3e-4999-9505-ffb230b938cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409219725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2409219725
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2512051976
Short name T111
Test name
Test status
Simulation time 116959455524 ps
CPU time 173.7 seconds
Started Aug 13 06:12:27 PM PDT 24
Finished Aug 13 06:15:20 PM PDT 24
Peak memory 191772 kb
Host smart-b93ba5ec-56bc-48d2-833b-867f43f461c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512051976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2512051976
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2905454618
Short name T164
Test name
Test status
Simulation time 284771438731 ps
CPU time 282.36 seconds
Started Aug 13 06:12:28 PM PDT 24
Finished Aug 13 06:17:11 PM PDT 24
Peak memory 191772 kb
Host smart-c13f4ece-4b7b-49f9-9403-07d49a99a3b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905454618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2905454618
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3591833458
Short name T286
Test name
Test status
Simulation time 101297235592 ps
CPU time 325.56 seconds
Started Aug 13 06:12:27 PM PDT 24
Finished Aug 13 06:17:53 PM PDT 24
Peak memory 191784 kb
Host smart-451ea1a4-5d5f-40e0-9ba0-d21465724cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591833458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3591833458
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3709755889
Short name T396
Test name
Test status
Simulation time 81083077168 ps
CPU time 31.34 seconds
Started Aug 13 06:09:30 PM PDT 24
Finished Aug 13 06:10:02 PM PDT 24
Peak memory 183448 kb
Host smart-8a1791b6-c9b8-48cd-813c-8b86d2526edb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709755889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3709755889
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3225635538
Short name T383
Test name
Test status
Simulation time 124004672558 ps
CPU time 96.17 seconds
Started Aug 13 06:09:34 PM PDT 24
Finished Aug 13 06:11:10 PM PDT 24
Peak memory 183572 kb
Host smart-cdff8750-a5e9-4c59-91fb-8b8f5c1bc516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225635538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3225635538
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.3780319808
Short name T255
Test name
Test status
Simulation time 625986033808 ps
CPU time 273.51 seconds
Started Aug 13 06:09:29 PM PDT 24
Finished Aug 13 06:14:03 PM PDT 24
Peak memory 191760 kb
Host smart-f170bc69-37f3-471f-880d-1b96808a8d14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780319808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3780319808
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.68170686
Short name T427
Test name
Test status
Simulation time 105327894585 ps
CPU time 332.73 seconds
Started Aug 13 06:09:33 PM PDT 24
Finished Aug 13 06:15:06 PM PDT 24
Peak memory 195460 kb
Host smart-9e416fed-4168-4804-8707-d1a45aff5055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68170686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.68170686
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.4267691837
Short name T35
Test name
Test status
Simulation time 1380737397 ps
CPU time 11.43 seconds
Started Aug 13 06:09:31 PM PDT 24
Finished Aug 13 06:09:43 PM PDT 24
Peak memory 198192 kb
Host smart-f47089e2-d4f7-4e13-8bf8-aef405c4b5e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267691837 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.4267691837
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.3046532157
Short name T434
Test name
Test status
Simulation time 192591576071 ps
CPU time 526.91 seconds
Started Aug 13 06:12:28 PM PDT 24
Finished Aug 13 06:21:15 PM PDT 24
Peak memory 191780 kb
Host smart-035801af-69b3-47ff-9d64-26d386816ec0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046532157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3046532157
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1063153418
Short name T105
Test name
Test status
Simulation time 131632066131 ps
CPU time 210.16 seconds
Started Aug 13 06:12:26 PM PDT 24
Finished Aug 13 06:15:57 PM PDT 24
Peak memory 191672 kb
Host smart-720cfc99-4b76-4d70-a0b0-54c50f5950c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063153418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1063153418
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3533112989
Short name T240
Test name
Test status
Simulation time 351193285925 ps
CPU time 797.84 seconds
Started Aug 13 06:12:26 PM PDT 24
Finished Aug 13 06:25:44 PM PDT 24
Peak memory 191812 kb
Host smart-1feda339-acf3-4bec-9b4f-686e1a329ace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533112989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3533112989
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1896420108
Short name T340
Test name
Test status
Simulation time 194468239815 ps
CPU time 307.64 seconds
Started Aug 13 06:12:29 PM PDT 24
Finished Aug 13 06:17:37 PM PDT 24
Peak memory 191836 kb
Host smart-bedd8fef-867a-44b8-b40a-5fec43178b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896420108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1896420108
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.207840709
Short name T313
Test name
Test status
Simulation time 94454975700 ps
CPU time 69.98 seconds
Started Aug 13 06:12:28 PM PDT 24
Finished Aug 13 06:13:38 PM PDT 24
Peak memory 183580 kb
Host smart-529cab95-d405-4714-b8fa-315a1961ed46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207840709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.207840709
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.637310705
Short name T281
Test name
Test status
Simulation time 74104080609 ps
CPU time 226.15 seconds
Started Aug 13 06:12:37 PM PDT 24
Finished Aug 13 06:16:23 PM PDT 24
Peak memory 193976 kb
Host smart-2f119858-0805-4b0b-958b-d285734f82e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637310705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.637310705
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3616450614
Short name T191
Test name
Test status
Simulation time 280300051353 ps
CPU time 270.53 seconds
Started Aug 13 06:12:38 PM PDT 24
Finished Aug 13 06:17:09 PM PDT 24
Peak memory 191736 kb
Host smart-2402d52a-361b-44e5-81c6-2a89ca287651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616450614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3616450614
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1844020681
Short name T437
Test name
Test status
Simulation time 41485056229 ps
CPU time 52.55 seconds
Started Aug 13 06:09:31 PM PDT 24
Finished Aug 13 06:10:24 PM PDT 24
Peak memory 183600 kb
Host smart-004e28bd-fad0-46db-b9fd-78dea613d081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844020681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1844020681
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.4155004771
Short name T418
Test name
Test status
Simulation time 7544689333 ps
CPU time 10.47 seconds
Started Aug 13 06:09:32 PM PDT 24
Finished Aug 13 06:09:42 PM PDT 24
Peak memory 183352 kb
Host smart-5927496f-885e-41b0-b363-9924bd9272ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155004771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.4155004771
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.387924028
Short name T385
Test name
Test status
Simulation time 1603485284014 ps
CPU time 332.69 seconds
Started Aug 13 06:09:34 PM PDT 24
Finished Aug 13 06:15:07 PM PDT 24
Peak memory 191760 kb
Host smart-0585d847-4232-4623-95cb-e34790ca078d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387924028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
387924028
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.1791578715
Short name T206
Test name
Test status
Simulation time 460962176443 ps
CPU time 266.81 seconds
Started Aug 13 06:12:34 PM PDT 24
Finished Aug 13 06:17:01 PM PDT 24
Peak memory 191928 kb
Host smart-c620fefe-5c9f-480d-a2d2-8ccd8015fb39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791578715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1791578715
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2089167309
Short name T128
Test name
Test status
Simulation time 142871249103 ps
CPU time 267.94 seconds
Started Aug 13 06:12:35 PM PDT 24
Finished Aug 13 06:17:03 PM PDT 24
Peak memory 191736 kb
Host smart-5b399106-979a-46ad-abd8-3033b0a466c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089167309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2089167309
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3690927413
Short name T344
Test name
Test status
Simulation time 92284060634 ps
CPU time 1195.59 seconds
Started Aug 13 06:12:36 PM PDT 24
Finished Aug 13 06:32:32 PM PDT 24
Peak memory 183568 kb
Host smart-65d6cb6b-3094-4475-be71-273c35722b6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690927413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3690927413
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2322972368
Short name T336
Test name
Test status
Simulation time 335932475872 ps
CPU time 953.81 seconds
Started Aug 13 06:12:35 PM PDT 24
Finished Aug 13 06:28:29 PM PDT 24
Peak memory 191824 kb
Host smart-69e87b0b-aa21-49d1-8259-d2e268108f84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322972368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2322972368
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3009308949
Short name T299
Test name
Test status
Simulation time 320434266115 ps
CPU time 183.89 seconds
Started Aug 13 06:12:35 PM PDT 24
Finished Aug 13 06:15:39 PM PDT 24
Peak memory 191792 kb
Host smart-62e47891-b99e-4d84-b8e3-7ab731f8ba97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009308949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3009308949
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.213148028
Short name T398
Test name
Test status
Simulation time 202296769515 ps
CPU time 150.04 seconds
Started Aug 13 06:12:35 PM PDT 24
Finished Aug 13 06:15:05 PM PDT 24
Peak memory 183636 kb
Host smart-c0e8e494-d6fc-4cb0-9343-7765f10b5498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213148028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.213148028
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2660472372
Short name T107
Test name
Test status
Simulation time 508386969185 ps
CPU time 591.41 seconds
Started Aug 13 06:12:35 PM PDT 24
Finished Aug 13 06:22:27 PM PDT 24
Peak memory 190744 kb
Host smart-6ccb1d8d-776a-4739-9ec1-b335a3a95d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660472372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2660472372
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3821221459
Short name T279
Test name
Test status
Simulation time 358985366690 ps
CPU time 574.63 seconds
Started Aug 13 06:09:32 PM PDT 24
Finished Aug 13 06:19:07 PM PDT 24
Peak memory 183568 kb
Host smart-ad483d61-b75e-44fb-9492-f6e60cc0f50b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821221459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3821221459
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1596373
Short name T414
Test name
Test status
Simulation time 76938415027 ps
CPU time 103.47 seconds
Started Aug 13 06:09:33 PM PDT 24
Finished Aug 13 06:11:16 PM PDT 24
Peak memory 183588 kb
Host smart-24b6d928-b371-4531-b52a-e8c95515a878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1596373
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3826514736
Short name T4
Test name
Test status
Simulation time 23988766475 ps
CPU time 113.15 seconds
Started Aug 13 06:09:45 PM PDT 24
Finished Aug 13 06:11:39 PM PDT 24
Peak memory 191772 kb
Host smart-ab9e01b8-9741-423e-9bda-5b718e749de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826514736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3826514736
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.2710546
Short name T175
Test name
Test status
Simulation time 338339840024 ps
CPU time 257.79 seconds
Started Aug 13 06:12:35 PM PDT 24
Finished Aug 13 06:16:54 PM PDT 24
Peak memory 191796 kb
Host smart-1bce4fcc-b7cf-49d0-8f6a-b0f838508914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2710546
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.312935640
Short name T140
Test name
Test status
Simulation time 264188247448 ps
CPU time 284.07 seconds
Started Aug 13 06:12:37 PM PDT 24
Finished Aug 13 06:17:22 PM PDT 24
Peak memory 191812 kb
Host smart-956bdf10-237d-4a03-be73-0c6329636487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312935640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.312935640
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.911524502
Short name T229
Test name
Test status
Simulation time 11242347870 ps
CPU time 33.42 seconds
Started Aug 13 06:12:37 PM PDT 24
Finished Aug 13 06:13:10 PM PDT 24
Peak memory 191672 kb
Host smart-c1221ab2-7d78-4e13-9484-39d5f9294f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911524502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.911524502
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1975321240
Short name T156
Test name
Test status
Simulation time 62513925616 ps
CPU time 41.84 seconds
Started Aug 13 06:12:44 PM PDT 24
Finished Aug 13 06:13:26 PM PDT 24
Peak memory 183592 kb
Host smart-03d6c1a0-8836-4472-b310-f418c3c89d37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975321240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1975321240
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.4155378341
Short name T318
Test name
Test status
Simulation time 254370127203 ps
CPU time 1072.18 seconds
Started Aug 13 06:12:42 PM PDT 24
Finished Aug 13 06:30:34 PM PDT 24
Peak memory 191728 kb
Host smart-9d265f44-fb12-4941-b8e8-67afbb681f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155378341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.4155378341
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2946372780
Short name T133
Test name
Test status
Simulation time 774496403195 ps
CPU time 641.54 seconds
Started Aug 13 06:12:41 PM PDT 24
Finished Aug 13 06:23:22 PM PDT 24
Peak memory 191776 kb
Host smart-265ce632-43a2-47f5-b80b-803bf8d23ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946372780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2946372780
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.4211257703
Short name T250
Test name
Test status
Simulation time 168321840946 ps
CPU time 145.49 seconds
Started Aug 13 06:09:43 PM PDT 24
Finished Aug 13 06:12:08 PM PDT 24
Peak memory 183532 kb
Host smart-51412bc8-c297-4432-8c58-d8bddb72d82b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211257703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.4211257703
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1713702396
Short name T386
Test name
Test status
Simulation time 326929114351 ps
CPU time 100.4 seconds
Started Aug 13 06:09:45 PM PDT 24
Finished Aug 13 06:11:26 PM PDT 24
Peak memory 183584 kb
Host smart-d7eab282-4967-419f-8c3b-ded80a6e0e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713702396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1713702396
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.491109787
Short name T165
Test name
Test status
Simulation time 106524712685 ps
CPU time 656 seconds
Started Aug 13 06:09:42 PM PDT 24
Finished Aug 13 06:20:39 PM PDT 24
Peak memory 191848 kb
Host smart-7299f807-bed2-4615-bd7f-1bbc16cc787e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491109787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.491109787
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.4142151797
Short name T443
Test name
Test status
Simulation time 406663464 ps
CPU time 4.61 seconds
Started Aug 13 06:09:44 PM PDT 24
Finished Aug 13 06:09:49 PM PDT 24
Peak memory 183476 kb
Host smart-c06346aa-31dc-4654-ad4f-1afc09728352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142151797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4142151797
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.2553024866
Short name T448
Test name
Test status
Simulation time 10849468404 ps
CPU time 34.78 seconds
Started Aug 13 06:09:45 PM PDT 24
Finished Aug 13 06:10:20 PM PDT 24
Peak memory 198288 kb
Host smart-c34b3deb-689e-44b5-9a9e-28db462a25f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553024866 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.2553024866
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.3038618412
Short name T116
Test name
Test status
Simulation time 33671402848 ps
CPU time 50.88 seconds
Started Aug 13 06:12:45 PM PDT 24
Finished Aug 13 06:13:36 PM PDT 24
Peak memory 191732 kb
Host smart-dbd39c9a-9276-4a80-af09-649cc63451e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038618412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3038618412
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.4224217477
Short name T108
Test name
Test status
Simulation time 374564877567 ps
CPU time 791.85 seconds
Started Aug 13 06:12:43 PM PDT 24
Finished Aug 13 06:25:55 PM PDT 24
Peak memory 191688 kb
Host smart-0e121a63-f36c-4c06-b149-1f750811686d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224217477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4224217477
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2858133212
Short name T161
Test name
Test status
Simulation time 58155171722 ps
CPU time 89.5 seconds
Started Aug 13 06:12:40 PM PDT 24
Finished Aug 13 06:14:09 PM PDT 24
Peak memory 191800 kb
Host smart-90a78517-2a17-4036-a17c-5a58246ab855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858133212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2858133212
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.541507382
Short name T258
Test name
Test status
Simulation time 149996022049 ps
CPU time 479.03 seconds
Started Aug 13 06:12:44 PM PDT 24
Finished Aug 13 06:20:43 PM PDT 24
Peak memory 195444 kb
Host smart-efa00adc-8743-49e9-b374-a51c880d8950
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541507382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.541507382
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2938632703
Short name T342
Test name
Test status
Simulation time 755748368083 ps
CPU time 573.55 seconds
Started Aug 13 06:12:42 PM PDT 24
Finished Aug 13 06:22:16 PM PDT 24
Peak memory 191784 kb
Host smart-bc896818-16c8-44a4-bd87-faf1f2c1fb2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938632703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2938632703
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.795217249
Short name T302
Test name
Test status
Simulation time 155119682702 ps
CPU time 197.38 seconds
Started Aug 13 06:12:45 PM PDT 24
Finished Aug 13 06:16:03 PM PDT 24
Peak memory 195048 kb
Host smart-56403adc-05b5-4e1c-bd99-ec81ef936157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795217249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.795217249
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1808761792
Short name T236
Test name
Test status
Simulation time 907650603806 ps
CPU time 1340.89 seconds
Started Aug 13 06:12:44 PM PDT 24
Finished Aug 13 06:35:05 PM PDT 24
Peak memory 191784 kb
Host smart-3eb10b01-2679-40e2-a68b-babd31c918fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808761792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1808761792
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3052024454
Short name T357
Test name
Test status
Simulation time 140869374847 ps
CPU time 100.6 seconds
Started Aug 13 06:12:53 PM PDT 24
Finished Aug 13 06:14:33 PM PDT 24
Peak memory 191796 kb
Host smart-307a969a-b4cf-402f-a94c-bd61d28856f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052024454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3052024454
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2536680817
Short name T122
Test name
Test status
Simulation time 2979708277321 ps
CPU time 609.8 seconds
Started Aug 13 06:09:45 PM PDT 24
Finished Aug 13 06:19:55 PM PDT 24
Peak memory 183560 kb
Host smart-9f594736-1468-48f7-8056-c1d9d6f2c541
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536680817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2536680817
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_random.1364186104
Short name T193
Test name
Test status
Simulation time 75839673017 ps
CPU time 251.06 seconds
Started Aug 13 06:09:43 PM PDT 24
Finished Aug 13 06:13:54 PM PDT 24
Peak memory 191796 kb
Host smart-e2ad1017-53ed-4f2f-8fbb-f2c24a24535b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364186104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1364186104
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2000757732
Short name T43
Test name
Test status
Simulation time 298726974728 ps
CPU time 73.5 seconds
Started Aug 13 06:09:43 PM PDT 24
Finished Aug 13 06:10:56 PM PDT 24
Peak memory 191760 kb
Host smart-5d02d540-8555-4026-96e9-3afea43cc719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000757732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2000757732
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.2292773831
Short name T219
Test name
Test status
Simulation time 127487184242 ps
CPU time 217.3 seconds
Started Aug 13 06:12:53 PM PDT 24
Finished Aug 13 06:16:31 PM PDT 24
Peak memory 191780 kb
Host smart-f7460727-871f-4942-9f9c-e1c28616a2ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292773831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2292773831
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.1050406198
Short name T89
Test name
Test status
Simulation time 308213055085 ps
CPU time 378.29 seconds
Started Aug 13 06:12:52 PM PDT 24
Finished Aug 13 06:19:11 PM PDT 24
Peak memory 191760 kb
Host smart-f4093f3b-b517-42df-b95f-5a45de18c33a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050406198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1050406198
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1605166126
Short name T158
Test name
Test status
Simulation time 1011319920983 ps
CPU time 440.99 seconds
Started Aug 13 06:12:50 PM PDT 24
Finished Aug 13 06:20:12 PM PDT 24
Peak memory 191756 kb
Host smart-4ecdfdd3-5721-441a-b74d-c2ddbae3f340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605166126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1605166126
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3105593814
Short name T423
Test name
Test status
Simulation time 25865320078 ps
CPU time 275.06 seconds
Started Aug 13 06:12:53 PM PDT 24
Finished Aug 13 06:17:28 PM PDT 24
Peak memory 183600 kb
Host smart-5dc67912-d4e7-469a-996c-db68c8f0ebb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105593814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3105593814
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1225998222
Short name T143
Test name
Test status
Simulation time 64452811858 ps
CPU time 149.82 seconds
Started Aug 13 06:12:50 PM PDT 24
Finished Aug 13 06:15:20 PM PDT 24
Peak memory 191928 kb
Host smart-a60b89ae-863a-4264-adcc-561eaac4dd4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225998222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1225998222
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3340470274
Short name T222
Test name
Test status
Simulation time 14500826897 ps
CPU time 36.52 seconds
Started Aug 13 06:12:52 PM PDT 24
Finished Aug 13 06:13:29 PM PDT 24
Peak memory 183564 kb
Host smart-23de1908-d49e-4db8-9a6b-7107913d9c4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340470274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3340470274
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3254474610
Short name T335
Test name
Test status
Simulation time 2789704566131 ps
CPU time 1233.68 seconds
Started Aug 13 06:12:52 PM PDT 24
Finished Aug 13 06:33:26 PM PDT 24
Peak memory 191792 kb
Host smart-b0764689-2902-4ff0-88bc-f3ba7d463fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254474610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3254474610
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3112951918
Short name T262
Test name
Test status
Simulation time 1000070789683 ps
CPU time 579.82 seconds
Started Aug 13 06:09:51 PM PDT 24
Finished Aug 13 06:19:31 PM PDT 24
Peak memory 183592 kb
Host smart-edc9242e-5804-40a3-8332-a54c74632d4f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112951918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3112951918
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1223195026
Short name T19
Test name
Test status
Simulation time 5588385055 ps
CPU time 2.59 seconds
Started Aug 13 06:09:51 PM PDT 24
Finished Aug 13 06:09:53 PM PDT 24
Peak memory 183408 kb
Host smart-6afcd0db-d242-4d02-a18d-eb02539b9018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223195026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1223195026
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.531219458
Short name T189
Test name
Test status
Simulation time 85743177187 ps
CPU time 152.38 seconds
Started Aug 13 06:09:49 PM PDT 24
Finished Aug 13 06:12:22 PM PDT 24
Peak memory 191792 kb
Host smart-10535338-63a7-4fdc-ae0b-a7a79eeb5a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531219458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.531219458
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2985035641
Short name T341
Test name
Test status
Simulation time 25894262483 ps
CPU time 37.72 seconds
Started Aug 13 06:09:49 PM PDT 24
Finished Aug 13 06:10:27 PM PDT 24
Peak memory 183380 kb
Host smart-08cf6b82-1f98-4d4b-87ef-d13caa6d8b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985035641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2985035641
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3844584550
Short name T184
Test name
Test status
Simulation time 664979576010 ps
CPU time 502.96 seconds
Started Aug 13 06:09:50 PM PDT 24
Finished Aug 13 06:18:13 PM PDT 24
Peak memory 191796 kb
Host smart-c85ca0f6-83fb-45db-afe2-7eacb3a75bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844584550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3844584550
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.822936222
Short name T84
Test name
Test status
Simulation time 450862256412 ps
CPU time 2479.82 seconds
Started Aug 13 06:12:54 PM PDT 24
Finished Aug 13 06:54:14 PM PDT 24
Peak memory 191732 kb
Host smart-29230bdb-2bde-46b4-8dca-fa70dcb06934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822936222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.822936222
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3092050701
Short name T354
Test name
Test status
Simulation time 321924969092 ps
CPU time 1597.26 seconds
Started Aug 13 06:13:06 PM PDT 24
Finished Aug 13 06:39:44 PM PDT 24
Peak memory 191780 kb
Host smart-c91e87ee-3d18-4c16-9c1a-965556491197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092050701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3092050701
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2794030387
Short name T273
Test name
Test status
Simulation time 103059790620 ps
CPU time 217.21 seconds
Started Aug 13 06:13:06 PM PDT 24
Finished Aug 13 06:16:43 PM PDT 24
Peak memory 191796 kb
Host smart-108b675f-b414-4cb9-b773-e21d3e2450b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794030387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2794030387
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.586658385
Short name T195
Test name
Test status
Simulation time 176817915161 ps
CPU time 1104.89 seconds
Started Aug 13 06:13:16 PM PDT 24
Finished Aug 13 06:31:41 PM PDT 24
Peak memory 191768 kb
Host smart-4f21afe8-4895-41fb-bc60-9f69dd3da793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586658385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.586658385
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3561959699
Short name T303
Test name
Test status
Simulation time 40367363496 ps
CPU time 203.11 seconds
Started Aug 13 06:13:17 PM PDT 24
Finished Aug 13 06:16:40 PM PDT 24
Peak memory 191848 kb
Host smart-c1993bea-fcb3-4ebb-93a7-9925b029c354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561959699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3561959699
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3563665946
Short name T352
Test name
Test status
Simulation time 447870687732 ps
CPU time 199.88 seconds
Started Aug 13 06:13:18 PM PDT 24
Finished Aug 13 06:16:38 PM PDT 24
Peak memory 191792 kb
Host smart-fa3625f2-2497-49a4-b8bf-1f7e849c8d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563665946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3563665946
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1842522337
Short name T245
Test name
Test status
Simulation time 92048218429 ps
CPU time 42.43 seconds
Started Aug 13 06:09:50 PM PDT 24
Finished Aug 13 06:10:32 PM PDT 24
Peak memory 183468 kb
Host smart-9b581d31-a74c-4f99-9a15-c62e507d05d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842522337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1842522337
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1429569780
Short name T424
Test name
Test status
Simulation time 78603861123 ps
CPU time 112.2 seconds
Started Aug 13 06:09:49 PM PDT 24
Finished Aug 13 06:11:41 PM PDT 24
Peak memory 183592 kb
Host smart-d020f493-919a-4d40-b1b7-639064ed24ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429569780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1429569780
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.2514697346
Short name T101
Test name
Test status
Simulation time 770089714950 ps
CPU time 476.31 seconds
Started Aug 13 06:09:47 PM PDT 24
Finished Aug 13 06:17:44 PM PDT 24
Peak memory 191940 kb
Host smart-a91fbc65-5047-4cd9-818e-f981c639070a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514697346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2514697346
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2414503319
Short name T375
Test name
Test status
Simulation time 124434425 ps
CPU time 0.73 seconds
Started Aug 13 06:09:49 PM PDT 24
Finished Aug 13 06:09:50 PM PDT 24
Peak memory 183284 kb
Host smart-9623b569-f50f-4f34-b691-01787dda8432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414503319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2414503319
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2881918166
Short name T422
Test name
Test status
Simulation time 207294218593 ps
CPU time 738.45 seconds
Started Aug 13 06:09:49 PM PDT 24
Finished Aug 13 06:22:08 PM PDT 24
Peak memory 195084 kb
Host smart-aaf4b7eb-930b-422e-9e05-dd2610418485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881918166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2881918166
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.3162436723
Short name T33
Test name
Test status
Simulation time 2239272705 ps
CPU time 24.75 seconds
Started Aug 13 06:09:50 PM PDT 24
Finished Aug 13 06:10:14 PM PDT 24
Peak memory 198272 kb
Host smart-f811f31c-1583-4e38-96ae-410806eaf8d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162436723 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.3162436723
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.3365132764
Short name T204
Test name
Test status
Simulation time 212429716952 ps
CPU time 439.52 seconds
Started Aug 13 06:13:16 PM PDT 24
Finished Aug 13 06:20:35 PM PDT 24
Peak memory 191736 kb
Host smart-b9bac1ed-476a-484c-b3f0-b3eaf61e0cc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365132764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3365132764
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.42155379
Short name T311
Test name
Test status
Simulation time 635045883701 ps
CPU time 2141.39 seconds
Started Aug 13 06:13:17 PM PDT 24
Finished Aug 13 06:48:59 PM PDT 24
Peak memory 191740 kb
Host smart-e21ab304-0a1f-43b2-99d1-45772969d605
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42155379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.42155379
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.4131482188
Short name T183
Test name
Test status
Simulation time 498343156492 ps
CPU time 608.57 seconds
Started Aug 13 06:13:20 PM PDT 24
Finished Aug 13 06:23:28 PM PDT 24
Peak memory 191776 kb
Host smart-a170d608-3053-4585-96b8-4f36a6385feb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131482188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.4131482188
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.395008810
Short name T284
Test name
Test status
Simulation time 159589550854 ps
CPU time 240.37 seconds
Started Aug 13 06:13:21 PM PDT 24
Finished Aug 13 06:17:21 PM PDT 24
Peak memory 191812 kb
Host smart-5e42f874-217d-4b9c-bd13-fd89b31da814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395008810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.395008810
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3607210173
Short name T353
Test name
Test status
Simulation time 215867521163 ps
CPU time 188.16 seconds
Started Aug 13 06:13:20 PM PDT 24
Finished Aug 13 06:16:29 PM PDT 24
Peak memory 191832 kb
Host smart-0848ce44-22ac-4f51-9f45-3e853dee4927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607210173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3607210173
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2896319261
Short name T399
Test name
Test status
Simulation time 40872971739 ps
CPU time 19.38 seconds
Started Aug 13 06:13:19 PM PDT 24
Finished Aug 13 06:13:39 PM PDT 24
Peak memory 183500 kb
Host smart-41f56e25-87eb-4039-bd91-718f07abdc93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896319261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2896319261
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2152507703
Short name T130
Test name
Test status
Simulation time 37656313312 ps
CPU time 70.9 seconds
Started Aug 13 06:13:19 PM PDT 24
Finished Aug 13 06:14:30 PM PDT 24
Peak memory 191752 kb
Host smart-4dd165de-9725-451e-88d5-8f59c359d0a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152507703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2152507703
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2210123054
Short name T251
Test name
Test status
Simulation time 91518612316 ps
CPU time 164.75 seconds
Started Aug 13 06:13:17 PM PDT 24
Finished Aug 13 06:16:02 PM PDT 24
Peak memory 191692 kb
Host smart-f0ddd67a-f2af-447d-8394-914a3cff7362
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210123054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2210123054
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2294982211
Short name T256
Test name
Test status
Simulation time 6377476351 ps
CPU time 10.83 seconds
Started Aug 13 06:09:47 PM PDT 24
Finished Aug 13 06:09:58 PM PDT 24
Peak memory 183504 kb
Host smart-1e93e657-8e4b-47c1-a333-2d3603a05b84
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294982211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2294982211
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.4275013655
Short name T444
Test name
Test status
Simulation time 189066650897 ps
CPU time 248 seconds
Started Aug 13 06:09:50 PM PDT 24
Finished Aug 13 06:13:58 PM PDT 24
Peak memory 183604 kb
Host smart-0ebd7e27-5d65-43cc-87b5-10a15b484992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275013655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.4275013655
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3776029028
Short name T288
Test name
Test status
Simulation time 71522559998 ps
CPU time 56.8 seconds
Started Aug 13 06:09:50 PM PDT 24
Finished Aug 13 06:10:47 PM PDT 24
Peak memory 183468 kb
Host smart-7be1e113-0a94-4fbc-8555-7ba2f3facddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776029028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3776029028
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2675293964
Short name T314
Test name
Test status
Simulation time 33577261146 ps
CPU time 175.9 seconds
Started Aug 13 06:09:59 PM PDT 24
Finished Aug 13 06:12:55 PM PDT 24
Peak memory 191792 kb
Host smart-e6c72807-df05-439a-9911-25b77415562b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675293964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2675293964
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.67627606
Short name T113
Test name
Test status
Simulation time 59093084644 ps
CPU time 59.34 seconds
Started Aug 13 06:13:20 PM PDT 24
Finished Aug 13 06:14:20 PM PDT 24
Peak memory 183632 kb
Host smart-6eae628e-f723-48b2-9651-5f1ed1bfc78c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67627606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.67627606
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.2257300853
Short name T441
Test name
Test status
Simulation time 188266317558 ps
CPU time 107.09 seconds
Started Aug 13 06:13:20 PM PDT 24
Finished Aug 13 06:15:07 PM PDT 24
Peak memory 183632 kb
Host smart-d41a03ab-c9b4-4eb6-bfb5-938a275ef82b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257300853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2257300853
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2552335657
Short name T91
Test name
Test status
Simulation time 243562232528 ps
CPU time 864.29 seconds
Started Aug 13 06:13:18 PM PDT 24
Finished Aug 13 06:27:42 PM PDT 24
Peak memory 191792 kb
Host smart-a9f824b5-7b36-43d2-90c1-d68bc384075a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552335657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2552335657
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.753957321
Short name T242
Test name
Test status
Simulation time 719242945742 ps
CPU time 1087.65 seconds
Started Aug 13 06:13:14 PM PDT 24
Finished Aug 13 06:31:22 PM PDT 24
Peak memory 191800 kb
Host smart-a7a6b566-6897-45e6-be79-6ae34ab170f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753957321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.753957321
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2339326542
Short name T267
Test name
Test status
Simulation time 19150496687 ps
CPU time 31.01 seconds
Started Aug 13 06:13:20 PM PDT 24
Finished Aug 13 06:13:51 PM PDT 24
Peak memory 183612 kb
Host smart-84d68ff1-0107-4d98-92e2-0621f0a37a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339326542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2339326542
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2727440178
Short name T110
Test name
Test status
Simulation time 91127902730 ps
CPU time 345.9 seconds
Started Aug 13 06:13:23 PM PDT 24
Finished Aug 13 06:19:10 PM PDT 24
Peak memory 195068 kb
Host smart-895b016f-a27d-4789-aed4-969369e113fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727440178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2727440178
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.362311423
Short name T349
Test name
Test status
Simulation time 426484579093 ps
CPU time 527.43 seconds
Started Aug 13 06:13:29 PM PDT 24
Finished Aug 13 06:22:16 PM PDT 24
Peak memory 191812 kb
Host smart-522f12c6-250e-4970-83cb-ba9d42dc8ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362311423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.362311423
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.917868871
Short name T112
Test name
Test status
Simulation time 69898315094 ps
CPU time 103.08 seconds
Started Aug 13 06:13:26 PM PDT 24
Finished Aug 13 06:15:09 PM PDT 24
Peak memory 191680 kb
Host smart-46c7dbe0-ed91-40a8-90c8-a330a3d216be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917868871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.917868871
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2855641351
Short name T377
Test name
Test status
Simulation time 89532715391 ps
CPU time 134.25 seconds
Started Aug 13 06:09:58 PM PDT 24
Finished Aug 13 06:12:13 PM PDT 24
Peak memory 183592 kb
Host smart-c0eb9d84-3ea5-4628-9a8c-e0c7953e4dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855641351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2855641351
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.4233185034
Short name T432
Test name
Test status
Simulation time 60521515457 ps
CPU time 93.27 seconds
Started Aug 13 06:09:59 PM PDT 24
Finished Aug 13 06:11:32 PM PDT 24
Peak memory 191672 kb
Host smart-c1e8426c-44f2-4487-a898-8ed008dee814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233185034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.4233185034
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1314476051
Short name T401
Test name
Test status
Simulation time 57144824440 ps
CPU time 181.75 seconds
Started Aug 13 06:09:56 PM PDT 24
Finished Aug 13 06:12:57 PM PDT 24
Peak memory 191768 kb
Host smart-b938290c-4f9e-4ae2-9f98-b8b7e176f3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314476051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1314476051
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1660781314
Short name T367
Test name
Test status
Simulation time 341139316658 ps
CPU time 538.18 seconds
Started Aug 13 06:09:59 PM PDT 24
Finished Aug 13 06:18:57 PM PDT 24
Peak memory 191676 kb
Host smart-fe214f28-124c-44e0-aa72-04002db7823b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660781314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1660781314
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.1954347771
Short name T37
Test name
Test status
Simulation time 1554066014 ps
CPU time 13.08 seconds
Started Aug 13 06:09:57 PM PDT 24
Finished Aug 13 06:10:10 PM PDT 24
Peak memory 198112 kb
Host smart-83e4332d-c71b-42a5-a0ba-8c9184d41c72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954347771 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.1954347771
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.4022347616
Short name T359
Test name
Test status
Simulation time 194351709512 ps
CPU time 278.36 seconds
Started Aug 13 06:13:25 PM PDT 24
Finished Aug 13 06:18:04 PM PDT 24
Peak memory 191764 kb
Host smart-d8f3813b-5f5f-4d66-9fa7-318960a61327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022347616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.4022347616
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1088785099
Short name T295
Test name
Test status
Simulation time 51375770684 ps
CPU time 535.01 seconds
Started Aug 13 06:13:26 PM PDT 24
Finished Aug 13 06:22:21 PM PDT 24
Peak memory 191808 kb
Host smart-80ca4184-ba64-4284-9eb4-ce819a21ee9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088785099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1088785099
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.4076268272
Short name T159
Test name
Test status
Simulation time 499258926681 ps
CPU time 309.16 seconds
Started Aug 13 06:13:27 PM PDT 24
Finished Aug 13 06:18:36 PM PDT 24
Peak memory 191812 kb
Host smart-2f39b544-3db5-48cb-9cf6-1080dfbbbd93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076268272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.4076268272
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1526180830
Short name T85
Test name
Test status
Simulation time 81122468250 ps
CPU time 121.9 seconds
Started Aug 13 06:13:36 PM PDT 24
Finished Aug 13 06:15:38 PM PDT 24
Peak memory 191792 kb
Host smart-f92e4cee-197c-4faa-a863-4a1832d935ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526180830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1526180830
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3690945983
Short name T137
Test name
Test status
Simulation time 414664477432 ps
CPU time 252.03 seconds
Started Aug 13 06:13:37 PM PDT 24
Finished Aug 13 06:17:49 PM PDT 24
Peak memory 191760 kb
Host smart-8ee20963-d4c6-451a-bdc9-d951b88b0028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690945983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3690945983
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1140865027
Short name T178
Test name
Test status
Simulation time 92838073840 ps
CPU time 314.46 seconds
Started Aug 13 06:13:37 PM PDT 24
Finished Aug 13 06:18:52 PM PDT 24
Peak memory 191764 kb
Host smart-2364b136-8884-4d4a-b012-2c9e07fef473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140865027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1140865027
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3383778296
Short name T297
Test name
Test status
Simulation time 23497427602 ps
CPU time 37.79 seconds
Started Aug 13 06:13:38 PM PDT 24
Finished Aug 13 06:14:16 PM PDT 24
Peak memory 183500 kb
Host smart-24fe37c6-ba50-4ce5-8039-d429224e5b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383778296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3383778296
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.116187425
Short name T174
Test name
Test status
Simulation time 138310650863 ps
CPU time 100.06 seconds
Started Aug 13 06:13:33 PM PDT 24
Finished Aug 13 06:15:13 PM PDT 24
Peak memory 194068 kb
Host smart-a1e74f3e-da37-4a89-88d7-b324961087f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116187425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.116187425
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3140381280
Short name T363
Test name
Test status
Simulation time 1407729802 ps
CPU time 3.15 seconds
Started Aug 13 06:08:46 PM PDT 24
Finished Aug 13 06:08:49 PM PDT 24
Peak memory 183256 kb
Host smart-5d493b87-211b-49ff-b72b-f9ce4d633a1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140381280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3140381280
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1198695645
Short name T368
Test name
Test status
Simulation time 186341596128 ps
CPU time 285.09 seconds
Started Aug 13 06:08:49 PM PDT 24
Finished Aug 13 06:13:34 PM PDT 24
Peak memory 183560 kb
Host smart-ae7d19da-a550-4a18-b92a-7ffe3962f8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198695645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1198695645
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.2792485790
Short name T348
Test name
Test status
Simulation time 1310684360297 ps
CPU time 543.12 seconds
Started Aug 13 06:08:47 PM PDT 24
Finished Aug 13 06:17:50 PM PDT 24
Peak memory 191780 kb
Host smart-8af91712-d21c-487a-b8f3-9b7ea772843c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792485790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2792485790
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.299728846
Short name T14
Test name
Test status
Simulation time 568991335 ps
CPU time 0.86 seconds
Started Aug 13 06:08:56 PM PDT 24
Finished Aug 13 06:08:57 PM PDT 24
Peak memory 215084 kb
Host smart-0e55119a-d619-4358-b983-65d772d35982
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299728846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.299728846
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2496354643
Short name T21
Test name
Test status
Simulation time 47672461201 ps
CPU time 81.8 seconds
Started Aug 13 06:09:57 PM PDT 24
Finished Aug 13 06:11:19 PM PDT 24
Peak memory 183572 kb
Host smart-f13dcace-0bb5-4dbb-b518-aa1d7bacf4bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496354643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2496354643
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1373338580
Short name T371
Test name
Test status
Simulation time 588797829525 ps
CPU time 241.06 seconds
Started Aug 13 06:10:00 PM PDT 24
Finished Aug 13 06:14:01 PM PDT 24
Peak memory 183604 kb
Host smart-ae70a962-950e-4c20-bcf1-137d9be9995f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373338580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1373338580
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2154506540
Short name T389
Test name
Test status
Simulation time 53627872102 ps
CPU time 73.35 seconds
Started Aug 13 06:10:06 PM PDT 24
Finished Aug 13 06:11:20 PM PDT 24
Peak memory 183568 kb
Host smart-97ddf3e8-2b47-442d-b24f-5e29054b8ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154506540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2154506540
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.217501179
Short name T266
Test name
Test status
Simulation time 17176266713 ps
CPU time 29.14 seconds
Started Aug 13 06:10:04 PM PDT 24
Finished Aug 13 06:10:33 PM PDT 24
Peak memory 183564 kb
Host smart-956e7d99-1c6f-44b0-bd63-affcbfc0ed97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217501179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.217501179
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1510543377
Short name T374
Test name
Test status
Simulation time 328682019578 ps
CPU time 250.9 seconds
Started Aug 13 06:10:04 PM PDT 24
Finished Aug 13 06:14:15 PM PDT 24
Peak memory 183604 kb
Host smart-96c4e514-0c08-48b0-88c1-35f6deaf67f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510543377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1510543377
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1527953626
Short name T102
Test name
Test status
Simulation time 211205508139 ps
CPU time 285.02 seconds
Started Aug 13 06:10:06 PM PDT 24
Finished Aug 13 06:14:51 PM PDT 24
Peak memory 183572 kb
Host smart-d0c8a27c-1ba1-4e3a-abeb-3cc6a332e48e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527953626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1527953626
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1194999253
Short name T306
Test name
Test status
Simulation time 115693044413 ps
CPU time 90.07 seconds
Started Aug 13 06:10:15 PM PDT 24
Finished Aug 13 06:11:45 PM PDT 24
Peak memory 191804 kb
Host smart-289df1ef-7a6b-4b04-985e-5c6e057fe8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194999253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1194999253
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1660986117
Short name T39
Test name
Test status
Simulation time 159079314816 ps
CPU time 157.07 seconds
Started Aug 13 06:10:13 PM PDT 24
Finished Aug 13 06:12:50 PM PDT 24
Peak memory 183536 kb
Host smart-29b44d6f-69a4-46ae-be56-8b59af650661
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660986117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1660986117
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.3898209213
Short name T409
Test name
Test status
Simulation time 144120283170 ps
CPU time 62.66 seconds
Started Aug 13 06:10:14 PM PDT 24
Finished Aug 13 06:11:17 PM PDT 24
Peak memory 183596 kb
Host smart-f61d0c43-8e3f-46cb-a9d9-3162612cffb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898209213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.3898209213
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3804238211
Short name T390
Test name
Test status
Simulation time 11768572540 ps
CPU time 9.32 seconds
Started Aug 13 06:10:14 PM PDT 24
Finished Aug 13 06:10:23 PM PDT 24
Peak memory 183604 kb
Host smart-2009225c-30cf-4488-8279-f174062bd422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804238211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3804238211
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3993830025
Short name T381
Test name
Test status
Simulation time 250238499631 ps
CPU time 169.92 seconds
Started Aug 13 06:10:23 PM PDT 24
Finished Aug 13 06:13:13 PM PDT 24
Peak memory 183608 kb
Host smart-b27f6436-5073-4fa7-ac02-ef25f9636c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993830025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3993830025
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.707390550
Short name T188
Test name
Test status
Simulation time 633796977248 ps
CPU time 416.02 seconds
Started Aug 13 06:10:13 PM PDT 24
Finished Aug 13 06:17:09 PM PDT 24
Peak memory 191748 kb
Host smart-0fb8df6e-290b-4c85-a191-428d147c45f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707390550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.707390550
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2664177390
Short name T388
Test name
Test status
Simulation time 178089733923 ps
CPU time 856.71 seconds
Started Aug 13 06:10:22 PM PDT 24
Finished Aug 13 06:24:39 PM PDT 24
Peak memory 195036 kb
Host smart-0112a7cc-5aaf-4ad8-9e18-91a71cd2f8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664177390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2664177390
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1876448987
Short name T201
Test name
Test status
Simulation time 184175295750 ps
CPU time 3284.26 seconds
Started Aug 13 06:10:21 PM PDT 24
Finished Aug 13 07:05:06 PM PDT 24
Peak memory 196252 kb
Host smart-884976b9-45ac-45c1-b644-ea73d1518e38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876448987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1876448987
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2875911623
Short name T115
Test name
Test status
Simulation time 547323770444 ps
CPU time 972.47 seconds
Started Aug 13 06:10:20 PM PDT 24
Finished Aug 13 06:26:32 PM PDT 24
Peak memory 183564 kb
Host smart-8f1c0153-7bd1-46c5-ad90-f94e264cb905
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875911623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2875911623
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.945601891
Short name T394
Test name
Test status
Simulation time 770599136978 ps
CPU time 192.69 seconds
Started Aug 13 06:10:22 PM PDT 24
Finished Aug 13 06:13:35 PM PDT 24
Peak memory 183612 kb
Host smart-e23ec7ac-0073-4575-a8f5-a14de4bbb606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945601891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.945601891
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.413967691
Short name T356
Test name
Test status
Simulation time 83297420743 ps
CPU time 121.32 seconds
Started Aug 13 06:10:24 PM PDT 24
Finished Aug 13 06:12:26 PM PDT 24
Peak memory 191800 kb
Host smart-c8458aa6-40ac-4c5f-bae1-62bcef477e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413967691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.413967691
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3075129870
Short name T257
Test name
Test status
Simulation time 1355083129908 ps
CPU time 1354.53 seconds
Started Aug 13 06:10:31 PM PDT 24
Finished Aug 13 06:33:06 PM PDT 24
Peak memory 191800 kb
Host smart-0baa7134-c6e8-46c5-9bcb-026d280e66f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075129870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3075129870
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1728817775
Short name T254
Test name
Test status
Simulation time 356838906923 ps
CPU time 225.79 seconds
Started Aug 13 06:10:36 PM PDT 24
Finished Aug 13 06:14:21 PM PDT 24
Peak memory 183596 kb
Host smart-e3624f2a-e8de-4c4a-a73c-5808f9ea9547
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728817775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1728817775
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2799084468
Short name T369
Test name
Test status
Simulation time 226089995842 ps
CPU time 73.98 seconds
Started Aug 13 06:10:31 PM PDT 24
Finished Aug 13 06:11:45 PM PDT 24
Peak memory 183572 kb
Host smart-75078761-0a5f-4067-a905-45f0c2129488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799084468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2799084468
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2205877743
Short name T278
Test name
Test status
Simulation time 187350349975 ps
CPU time 351.23 seconds
Started Aug 13 06:10:31 PM PDT 24
Finished Aug 13 06:16:23 PM PDT 24
Peak memory 191792 kb
Host smart-bbb02248-9780-41ad-9570-2685e159b31d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205877743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2205877743
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.59781887
Short name T316
Test name
Test status
Simulation time 127572161597 ps
CPU time 59.65 seconds
Started Aug 13 06:10:31 PM PDT 24
Finished Aug 13 06:11:30 PM PDT 24
Peak memory 183596 kb
Host smart-1b3fe2c6-759a-4f3b-a129-ef8a4de70b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59781887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.59781887
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2491461997
Short name T196
Test name
Test status
Simulation time 198556860007 ps
CPU time 501.26 seconds
Started Aug 13 06:10:29 PM PDT 24
Finished Aug 13 06:18:51 PM PDT 24
Peak memory 191744 kb
Host smart-69d7b827-45a1-4bfa-a6a2-7dade1e4a41a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491461997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2491461997
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1983962330
Short name T153
Test name
Test status
Simulation time 70337713089 ps
CPU time 123.91 seconds
Started Aug 13 06:10:29 PM PDT 24
Finished Aug 13 06:12:33 PM PDT 24
Peak memory 183588 kb
Host smart-07fa0891-6665-493b-bf19-f1d644acd3e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983962330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1983962330
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3238952908
Short name T403
Test name
Test status
Simulation time 133988566678 ps
CPU time 147.21 seconds
Started Aug 13 06:10:32 PM PDT 24
Finished Aug 13 06:12:59 PM PDT 24
Peak memory 183500 kb
Host smart-69f386b3-b52b-42a2-bbc0-325a9df2c753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238952908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3238952908
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.238319473
Short name T46
Test name
Test status
Simulation time 100494277336 ps
CPU time 553.29 seconds
Started Aug 13 06:10:31 PM PDT 24
Finished Aug 13 06:19:44 PM PDT 24
Peak memory 191740 kb
Host smart-5c283998-add7-47c5-a0b8-838a4833aed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238319473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.238319473
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3343789792
Short name T333
Test name
Test status
Simulation time 67558685969 ps
CPU time 999.54 seconds
Started Aug 13 06:10:36 PM PDT 24
Finished Aug 13 06:27:16 PM PDT 24
Peak memory 183600 kb
Host smart-b8d416b4-dbba-4076-b347-36551a823c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343789792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3343789792
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.381204319
Short name T36
Test name
Test status
Simulation time 7887286909 ps
CPU time 16.58 seconds
Started Aug 13 06:10:35 PM PDT 24
Finished Aug 13 06:10:51 PM PDT 24
Peak memory 198312 kb
Host smart-5a393e8a-5c26-4ffe-9359-abdcddc9befa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381204319 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.381204319
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3620603698
Short name T410
Test name
Test status
Simulation time 1013367603920 ps
CPU time 522.63 seconds
Started Aug 13 06:10:30 PM PDT 24
Finished Aug 13 06:19:13 PM PDT 24
Peak memory 183536 kb
Host smart-f0bceb9a-af33-4bee-8643-c79f98d10b82
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620603698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3620603698
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1923098074
Short name T430
Test name
Test status
Simulation time 54791815771 ps
CPU time 79 seconds
Started Aug 13 06:10:36 PM PDT 24
Finished Aug 13 06:11:55 PM PDT 24
Peak memory 183612 kb
Host smart-1a8f6721-16b7-4765-a351-503bdcbe8bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923098074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1923098074
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2046484365
Short name T447
Test name
Test status
Simulation time 1726630211 ps
CPU time 6.47 seconds
Started Aug 13 06:10:33 PM PDT 24
Finished Aug 13 06:10:40 PM PDT 24
Peak memory 183360 kb
Host smart-f1fa27b0-96a8-479a-9aaa-5d97bb8e2e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046484365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2046484365
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2908835081
Short name T263
Test name
Test status
Simulation time 151558028790 ps
CPU time 169.73 seconds
Started Aug 13 06:10:30 PM PDT 24
Finished Aug 13 06:13:20 PM PDT 24
Peak memory 195392 kb
Host smart-661ed9f4-9496-42c5-9f94-a3e027462c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908835081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2908835081
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2328674552
Short name T376
Test name
Test status
Simulation time 627753135986 ps
CPU time 748.15 seconds
Started Aug 13 06:10:39 PM PDT 24
Finished Aug 13 06:23:08 PM PDT 24
Peak memory 191804 kb
Host smart-1e027d88-87e9-4e12-a36d-5c111c42b174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328674552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2328674552
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3862502553
Short name T187
Test name
Test status
Simulation time 133482126633 ps
CPU time 239.02 seconds
Started Aug 13 06:10:41 PM PDT 24
Finished Aug 13 06:14:40 PM PDT 24
Peak memory 183580 kb
Host smart-7b77478d-5d99-4dce-b623-86c456996bca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862502553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3862502553
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.448326363
Short name T395
Test name
Test status
Simulation time 38392624914 ps
CPU time 62.84 seconds
Started Aug 13 06:10:41 PM PDT 24
Finished Aug 13 06:11:44 PM PDT 24
Peak memory 183544 kb
Host smart-4a6f3239-c0ca-416e-a981-c22500d16780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448326363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.448326363
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2634033836
Short name T87
Test name
Test status
Simulation time 366885777200 ps
CPU time 176.37 seconds
Started Aug 13 06:10:38 PM PDT 24
Finished Aug 13 06:13:35 PM PDT 24
Peak memory 191796 kb
Host smart-764914d4-fe17-4426-b8a2-20d73750784f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634033836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2634033836
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2853482854
Short name T235
Test name
Test status
Simulation time 122028609388 ps
CPU time 219.49 seconds
Started Aug 13 06:10:40 PM PDT 24
Finished Aug 13 06:14:19 PM PDT 24
Peak memory 191800 kb
Host smart-ab430d75-12d3-4e90-a7eb-47f9182b7451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853482854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2853482854
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1559429096
Short name T419
Test name
Test status
Simulation time 137782868467 ps
CPU time 209.86 seconds
Started Aug 13 06:08:58 PM PDT 24
Finished Aug 13 06:12:28 PM PDT 24
Peak memory 183492 kb
Host smart-46292a71-a5b0-4439-bf16-8f66f6626be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559429096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1559429096
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.186091794
Short name T237
Test name
Test status
Simulation time 128662864896 ps
CPU time 176.75 seconds
Started Aug 13 06:08:58 PM PDT 24
Finished Aug 13 06:11:55 PM PDT 24
Peak memory 191820 kb
Host smart-315f98d5-fea5-475d-a0b9-6910f11e83ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186091794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.186091794
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.4169313875
Short name T326
Test name
Test status
Simulation time 100541424046 ps
CPU time 179.36 seconds
Started Aug 13 06:08:55 PM PDT 24
Finished Aug 13 06:11:54 PM PDT 24
Peak memory 191776 kb
Host smart-107f4abf-82a1-48c7-b9ca-18d547ae78a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169313875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.4169313875
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1022980403
Short name T17
Test name
Test status
Simulation time 86114632 ps
CPU time 0.89 seconds
Started Aug 13 06:08:58 PM PDT 24
Finished Aug 13 06:08:59 PM PDT 24
Peak memory 215080 kb
Host smart-92048bd7-4f6b-4c99-80a6-d29991ee881c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022980403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1022980403
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3072491122
Short name T126
Test name
Test status
Simulation time 51951336282 ps
CPU time 16.75 seconds
Started Aug 13 06:10:38 PM PDT 24
Finished Aug 13 06:10:55 PM PDT 24
Peak memory 183556 kb
Host smart-312c2e4f-5832-42f4-8761-1806959789c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072491122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3072491122
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2782160505
Short name T405
Test name
Test status
Simulation time 472698555133 ps
CPU time 197.02 seconds
Started Aug 13 06:10:39 PM PDT 24
Finished Aug 13 06:13:56 PM PDT 24
Peak memory 183600 kb
Host smart-3baad4b5-89de-4195-8f5d-7556eba1a240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782160505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2782160505
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.342901410
Short name T210
Test name
Test status
Simulation time 77903524019 ps
CPU time 130.31 seconds
Started Aug 13 06:10:40 PM PDT 24
Finished Aug 13 06:12:50 PM PDT 24
Peak memory 191844 kb
Host smart-63df9d4a-8d92-4919-8976-fa572c54cdf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342901410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.342901410
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2492846758
Short name T393
Test name
Test status
Simulation time 233018651 ps
CPU time 0.62 seconds
Started Aug 13 06:10:38 PM PDT 24
Finished Aug 13 06:10:39 PM PDT 24
Peak memory 183240 kb
Host smart-95c56db4-e049-4514-bcf8-a750bc05c8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492846758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2492846758
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.2750888574
Short name T455
Test name
Test status
Simulation time 39886181179 ps
CPU time 68.44 seconds
Started Aug 13 06:10:42 PM PDT 24
Finished Aug 13 06:11:50 PM PDT 24
Peak memory 183600 kb
Host smart-bd348e9e-6966-4a7d-bbed-1244f61e6309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750888574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.2750888574
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3703740492
Short name T429
Test name
Test status
Simulation time 467018671844 ps
CPU time 393.69 seconds
Started Aug 13 06:10:51 PM PDT 24
Finished Aug 13 06:17:25 PM PDT 24
Peak memory 183488 kb
Host smart-79c07d46-d0a9-45b1-8734-b4ecb21a62ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703740492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3703740492
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2649793131
Short name T7
Test name
Test status
Simulation time 315977891445 ps
CPU time 239.89 seconds
Started Aug 13 06:10:51 PM PDT 24
Finished Aug 13 06:14:51 PM PDT 24
Peak memory 183608 kb
Host smart-348fa3f0-b6c5-4b5e-9c9d-a544d15815e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649793131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2649793131
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.26525760
Short name T343
Test name
Test status
Simulation time 430495191115 ps
CPU time 74.67 seconds
Started Aug 13 06:10:42 PM PDT 24
Finished Aug 13 06:11:57 PM PDT 24
Peak memory 183508 kb
Host smart-c4d51544-43dd-4d42-9e9f-2a3db9d5010f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26525760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.26525760
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2199468076
Short name T440
Test name
Test status
Simulation time 258350570583 ps
CPU time 111.59 seconds
Started Aug 13 06:10:50 PM PDT 24
Finished Aug 13 06:12:42 PM PDT 24
Peak memory 183588 kb
Host smart-8011dfd2-0392-459f-ae1c-580472a2d9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199468076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2199468076
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2373919197
Short name T411
Test name
Test status
Simulation time 107935668545 ps
CPU time 160.2 seconds
Started Aug 13 06:10:51 PM PDT 24
Finished Aug 13 06:13:31 PM PDT 24
Peak memory 183568 kb
Host smart-a39ac7d9-9a7f-40da-ace5-ae550daf59fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373919197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2373919197
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2082022050
Short name T205
Test name
Test status
Simulation time 78598427094 ps
CPU time 285.31 seconds
Started Aug 13 06:10:49 PM PDT 24
Finished Aug 13 06:15:34 PM PDT 24
Peak memory 191816 kb
Host smart-cb1e5a89-f718-4ba7-9b67-62e701bd8bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082022050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2082022050
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1106178271
Short name T339
Test name
Test status
Simulation time 38338965054 ps
CPU time 271.8 seconds
Started Aug 13 06:10:50 PM PDT 24
Finished Aug 13 06:15:22 PM PDT 24
Peak memory 183604 kb
Host smart-22511733-4dbc-47f2-9bc0-11f9ed363970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106178271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1106178271
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1652151065
Short name T18
Test name
Test status
Simulation time 1430073464454 ps
CPU time 616.54 seconds
Started Aug 13 06:10:50 PM PDT 24
Finished Aug 13 06:21:06 PM PDT 24
Peak memory 191764 kb
Host smart-9ffbc1f7-ac31-4aee-9257-edc74c5c5702
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652151065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1652151065
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.2283440184
Short name T32
Test name
Test status
Simulation time 12003818082 ps
CPU time 44.83 seconds
Started Aug 13 06:10:49 PM PDT 24
Finished Aug 13 06:11:34 PM PDT 24
Peak memory 198308 kb
Host smart-2c078393-1b08-4473-abfe-90844b75882e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283440184 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.2283440184
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1560476551
Short name T98
Test name
Test status
Simulation time 426853898886 ps
CPU time 392.18 seconds
Started Aug 13 06:10:50 PM PDT 24
Finished Aug 13 06:17:22 PM PDT 24
Peak memory 183516 kb
Host smart-ca3e9b06-eb52-44b2-8605-7a513cbe29d3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560476551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1560476551
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.418952614
Short name T425
Test name
Test status
Simulation time 45217976331 ps
CPU time 60.15 seconds
Started Aug 13 06:10:49 PM PDT 24
Finished Aug 13 06:11:49 PM PDT 24
Peak memory 183528 kb
Host smart-46397e96-0369-4d63-9ddc-60c9af4a531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418952614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.418952614
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3236768821
Short name T171
Test name
Test status
Simulation time 323615434583 ps
CPU time 254.86 seconds
Started Aug 13 06:10:49 PM PDT 24
Finished Aug 13 06:15:04 PM PDT 24
Peak memory 191828 kb
Host smart-b8bf7bc1-a8c3-4f72-8433-5c2cb83cd887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236768821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3236768821
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1398653680
Short name T347
Test name
Test status
Simulation time 1944047407230 ps
CPU time 599.96 seconds
Started Aug 13 06:10:59 PM PDT 24
Finished Aug 13 06:21:00 PM PDT 24
Peak memory 183568 kb
Host smart-39e247a4-bd5f-42e7-b514-6a1c1722d6e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398653680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1398653680
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3184993053
Short name T406
Test name
Test status
Simulation time 778124997853 ps
CPU time 335.09 seconds
Started Aug 13 06:10:59 PM PDT 24
Finished Aug 13 06:16:35 PM PDT 24
Peak memory 183568 kb
Host smart-4a0bbc5b-62ea-4847-9d99-9b17530924b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184993053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3184993053
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3262442281
Short name T94
Test name
Test status
Simulation time 279509913756 ps
CPU time 219.33 seconds
Started Aug 13 06:11:00 PM PDT 24
Finished Aug 13 06:14:40 PM PDT 24
Peak memory 191760 kb
Host smart-4a6402d7-24fe-49a0-82a3-8d50f6bfc4cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262442281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3262442281
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.178884223
Short name T382
Test name
Test status
Simulation time 35864845 ps
CPU time 0.52 seconds
Started Aug 13 06:11:00 PM PDT 24
Finished Aug 13 06:11:00 PM PDT 24
Peak memory 183296 kb
Host smart-6d999de3-3827-4ffc-b976-877fbedeaa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178884223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.178884223
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1236661668
Short name T1
Test name
Test status
Simulation time 186246916453 ps
CPU time 320.42 seconds
Started Aug 13 06:10:58 PM PDT 24
Finished Aug 13 06:16:19 PM PDT 24
Peak memory 195732 kb
Host smart-bba4c5a0-5817-4449-99e7-51810efddba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236661668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1236661668
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2224646070
Short name T231
Test name
Test status
Simulation time 87490923835 ps
CPU time 141.05 seconds
Started Aug 13 06:11:00 PM PDT 24
Finished Aug 13 06:13:21 PM PDT 24
Peak memory 183528 kb
Host smart-dc052c37-a9d8-4d4b-acff-ddd1ca02550e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224646070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2224646070
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3152299239
Short name T420
Test name
Test status
Simulation time 70718178196 ps
CPU time 102.59 seconds
Started Aug 13 06:11:00 PM PDT 24
Finished Aug 13 06:12:43 PM PDT 24
Peak memory 183596 kb
Host smart-a637072b-f4b9-4cc5-a4be-7c0044695323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152299239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3152299239
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.4130436040
Short name T417
Test name
Test status
Simulation time 31341643124 ps
CPU time 50.53 seconds
Started Aug 13 06:11:01 PM PDT 24
Finished Aug 13 06:11:52 PM PDT 24
Peak memory 183580 kb
Host smart-b972538d-970a-4034-8859-4527f4bbe081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130436040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4130436040
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2329918946
Short name T207
Test name
Test status
Simulation time 377483347617 ps
CPU time 156.39 seconds
Started Aug 13 06:10:59 PM PDT 24
Finished Aug 13 06:13:35 PM PDT 24
Peak memory 191796 kb
Host smart-2640ae36-4725-455f-a74e-b72d2b57eed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329918946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2329918946
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2414397318
Short name T346
Test name
Test status
Simulation time 807195167382 ps
CPU time 746.78 seconds
Started Aug 13 06:11:08 PM PDT 24
Finished Aug 13 06:23:35 PM PDT 24
Peak memory 183440 kb
Host smart-5f54cc0a-6942-4f42-9924-1502c9377988
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414397318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2414397318
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.776914628
Short name T372
Test name
Test status
Simulation time 484627806598 ps
CPU time 195.87 seconds
Started Aug 13 06:11:08 PM PDT 24
Finished Aug 13 06:14:24 PM PDT 24
Peak memory 183592 kb
Host smart-70730a66-650b-45d2-88fc-c95350312df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776914628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.776914628
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2384374209
Short name T301
Test name
Test status
Simulation time 399556614265 ps
CPU time 242.97 seconds
Started Aug 13 06:10:59 PM PDT 24
Finished Aug 13 06:15:02 PM PDT 24
Peak memory 191756 kb
Host smart-b23fa50e-7094-4052-9b44-f56f75253aae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384374209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2384374209
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3583522032
Short name T351
Test name
Test status
Simulation time 220778825686 ps
CPU time 86.35 seconds
Started Aug 13 06:11:08 PM PDT 24
Finished Aug 13 06:12:35 PM PDT 24
Peak memory 191772 kb
Host smart-526dc803-38c5-4355-98f0-382613a89369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583522032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3583522032
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1351386737
Short name T260
Test name
Test status
Simulation time 2347785511188 ps
CPU time 879.88 seconds
Started Aug 13 06:11:08 PM PDT 24
Finished Aug 13 06:25:48 PM PDT 24
Peak memory 183556 kb
Host smart-6d1bd74b-5292-4718-bce1-8902e5cc1444
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351386737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1351386737
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1414157176
Short name T373
Test name
Test status
Simulation time 9289672385 ps
CPU time 14.99 seconds
Started Aug 13 06:11:09 PM PDT 24
Finished Aug 13 06:11:24 PM PDT 24
Peak memory 183600 kb
Host smart-3d4a5e1d-7e4c-451c-9965-2bee1101a48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414157176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1414157176
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3600593576
Short name T47
Test name
Test status
Simulation time 264531813904 ps
CPU time 1286.78 seconds
Started Aug 13 06:11:08 PM PDT 24
Finished Aug 13 06:32:35 PM PDT 24
Peak memory 191764 kb
Host smart-5cebe3a6-51f9-46b8-b9ec-e239f939c147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600593576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3600593576
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1038250046
Short name T387
Test name
Test status
Simulation time 35109568477 ps
CPU time 1275.19 seconds
Started Aug 13 06:11:09 PM PDT 24
Finished Aug 13 06:32:25 PM PDT 24
Peak memory 183504 kb
Host smart-b49244cb-3f0b-40c1-bcbe-7117a1d80abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038250046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1038250046
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2268278756
Short name T446
Test name
Test status
Simulation time 72564817 ps
CPU time 0.54 seconds
Started Aug 13 06:11:07 PM PDT 24
Finished Aug 13 06:11:08 PM PDT 24
Peak memory 183280 kb
Host smart-881a1169-d129-4c9d-90d1-2a1bc70c66d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268278756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2268278756
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2801242434
Short name T244
Test name
Test status
Simulation time 2423204043070 ps
CPU time 750.21 seconds
Started Aug 13 06:11:16 PM PDT 24
Finished Aug 13 06:23:46 PM PDT 24
Peak memory 183528 kb
Host smart-d305d458-8c01-4359-b4c0-b7212abe863a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801242434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2801242434
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1869165821
Short name T384
Test name
Test status
Simulation time 698656026578 ps
CPU time 295.76 seconds
Started Aug 13 06:11:09 PM PDT 24
Finished Aug 13 06:16:04 PM PDT 24
Peak memory 183596 kb
Host smart-10371120-e446-430f-aa7b-17b0aebfa2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869165821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1869165821
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1972581797
Short name T129
Test name
Test status
Simulation time 3090590992 ps
CPU time 15.99 seconds
Started Aug 13 06:11:19 PM PDT 24
Finished Aug 13 06:11:35 PM PDT 24
Peak memory 194532 kb
Host smart-99556740-835d-49c5-8f75-a8cb76352d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972581797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1972581797
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.800396132
Short name T293
Test name
Test status
Simulation time 159067295695 ps
CPU time 423.37 seconds
Started Aug 13 06:11:18 PM PDT 24
Finished Aug 13 06:18:22 PM PDT 24
Peak memory 191788 kb
Host smart-028cd495-1bcd-40c9-907c-6babbcd31891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800396132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
800396132
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.2004035640
Short name T48
Test name
Test status
Simulation time 4118189662 ps
CPU time 31.71 seconds
Started Aug 13 06:11:17 PM PDT 24
Finished Aug 13 06:11:49 PM PDT 24
Peak memory 198200 kb
Host smart-bfd710de-4b6e-46ed-897e-ea2687201114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004035640 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.2004035640
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.536982534
Short name T5
Test name
Test status
Simulation time 610007771026 ps
CPU time 522.07 seconds
Started Aug 13 06:11:17 PM PDT 24
Finished Aug 13 06:19:59 PM PDT 24
Peak memory 183568 kb
Host smart-f8ac37e1-e0f2-4634-bcd6-7ece50e88f03
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536982534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.536982534
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3486750042
Short name T366
Test name
Test status
Simulation time 54941948064 ps
CPU time 72.06 seconds
Started Aug 13 06:11:18 PM PDT 24
Finished Aug 13 06:12:30 PM PDT 24
Peak memory 183556 kb
Host smart-c95519e9-f7bc-4878-bc30-4242b1720d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486750042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3486750042
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.872856003
Short name T268
Test name
Test status
Simulation time 109389248319 ps
CPU time 353.89 seconds
Started Aug 13 06:11:19 PM PDT 24
Finished Aug 13 06:17:13 PM PDT 24
Peak memory 183592 kb
Host smart-e6fec7fd-4c36-4ee9-8497-def69cefe602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872856003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.872856003
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1793340323
Short name T190
Test name
Test status
Simulation time 1976505860301 ps
CPU time 782.22 seconds
Started Aug 13 06:08:57 PM PDT 24
Finished Aug 13 06:21:59 PM PDT 24
Peak memory 183600 kb
Host smart-8a3bcd08-fe82-4edd-abed-4da715c1dc11
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793340323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1793340323
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2335637487
Short name T400
Test name
Test status
Simulation time 545180520430 ps
CPU time 193.38 seconds
Started Aug 13 06:08:55 PM PDT 24
Finished Aug 13 06:12:09 PM PDT 24
Peak memory 183552 kb
Host smart-21ae81ca-779c-4181-9c4f-51b991b19600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335637487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2335637487
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1010758213
Short name T104
Test name
Test status
Simulation time 174288188910 ps
CPU time 87.45 seconds
Started Aug 13 06:08:56 PM PDT 24
Finished Aug 13 06:10:23 PM PDT 24
Peak memory 194644 kb
Host smart-853074bb-f834-47e6-ac9d-185e9a29af92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010758213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1010758213
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1580370137
Short name T355
Test name
Test status
Simulation time 163317870421 ps
CPU time 618.61 seconds
Started Aug 13 06:08:56 PM PDT 24
Finished Aug 13 06:19:15 PM PDT 24
Peak memory 191760 kb
Host smart-25ddfc8a-da7e-4a38-af57-f628438f1e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580370137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1580370137
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3131319663
Short name T16
Test name
Test status
Simulation time 385723034 ps
CPU time 0.84 seconds
Started Aug 13 06:09:06 PM PDT 24
Finished Aug 13 06:09:07 PM PDT 24
Peak memory 214032 kb
Host smart-9241e566-0ef3-4140-837a-4bd72abd01ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131319663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3131319663
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3921701531
Short name T328
Test name
Test status
Simulation time 378641304555 ps
CPU time 346.97 seconds
Started Aug 13 06:11:26 PM PDT 24
Finished Aug 13 06:17:13 PM PDT 24
Peak memory 183556 kb
Host smart-d67b3911-c63d-4923-b625-08144804c993
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921701531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3921701531
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.964617549
Short name T453
Test name
Test status
Simulation time 115429616901 ps
CPU time 176.64 seconds
Started Aug 13 06:11:18 PM PDT 24
Finished Aug 13 06:14:15 PM PDT 24
Peak memory 183576 kb
Host smart-8f436296-da9a-4795-ad6b-121fe862b17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964617549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.964617549
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.732852322
Short name T358
Test name
Test status
Simulation time 166726622115 ps
CPU time 291.68 seconds
Started Aug 13 06:11:18 PM PDT 24
Finished Aug 13 06:16:10 PM PDT 24
Peak memory 191736 kb
Host smart-dfc1c36e-adbd-4fa2-8395-4d9719cb4a83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732852322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.732852322
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1245586618
Short name T88
Test name
Test status
Simulation time 54241521652 ps
CPU time 1199.88 seconds
Started Aug 13 06:11:27 PM PDT 24
Finished Aug 13 06:31:27 PM PDT 24
Peak memory 191688 kb
Host smart-7e854353-b499-40d8-b7a3-122e65a18ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245586618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1245586618
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3103226747
Short name T319
Test name
Test status
Simulation time 396405480081 ps
CPU time 650.48 seconds
Started Aug 13 06:11:28 PM PDT 24
Finished Aug 13 06:22:18 PM PDT 24
Peak memory 183588 kb
Host smart-1f543240-26fb-4695-94cc-bb17e3f69e0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103226747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3103226747
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.401756102
Short name T408
Test name
Test status
Simulation time 587803543971 ps
CPU time 235.76 seconds
Started Aug 13 06:11:26 PM PDT 24
Finished Aug 13 06:15:22 PM PDT 24
Peak memory 183580 kb
Host smart-9a68d6a4-b7a7-4c8c-825f-f55e1107a191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401756102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.401756102
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.4286641504
Short name T449
Test name
Test status
Simulation time 1375658486859 ps
CPU time 2773.65 seconds
Started Aug 13 06:11:27 PM PDT 24
Finished Aug 13 06:57:40 PM PDT 24
Peak memory 191652 kb
Host smart-0adb3220-aab5-4b6b-8550-2af56ed45fac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286641504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4286641504
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3410865728
Short name T404
Test name
Test status
Simulation time 15820921619 ps
CPU time 7.82 seconds
Started Aug 13 06:11:26 PM PDT 24
Finished Aug 13 06:11:34 PM PDT 24
Peak memory 191752 kb
Host smart-533bf483-4b32-4977-8e70-0fe9d39f7c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410865728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3410865728
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2180349518
Short name T337
Test name
Test status
Simulation time 270807196246 ps
CPU time 839.87 seconds
Started Aug 13 06:11:37 PM PDT 24
Finished Aug 13 06:25:37 PM PDT 24
Peak memory 195388 kb
Host smart-1d8fca68-d209-4b92-8b13-eb855c455756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180349518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2180349518
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1214645501
Short name T202
Test name
Test status
Simulation time 1433120927620 ps
CPU time 346.87 seconds
Started Aug 13 06:11:38 PM PDT 24
Finished Aug 13 06:17:25 PM PDT 24
Peak memory 183568 kb
Host smart-5350d754-0e80-4f98-925e-0a768b32be53
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214645501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1214645501
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3745011959
Short name T431
Test name
Test status
Simulation time 427958511896 ps
CPU time 174.59 seconds
Started Aug 13 06:11:38 PM PDT 24
Finished Aug 13 06:14:32 PM PDT 24
Peak memory 183572 kb
Host smart-9fe9afb1-37b9-42c6-96d8-54d066f35607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745011959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3745011959
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3340635770
Short name T310
Test name
Test status
Simulation time 36496889951 ps
CPU time 55.43 seconds
Started Aug 13 06:11:38 PM PDT 24
Finished Aug 13 06:12:34 PM PDT 24
Peak memory 183552 kb
Host smart-892d5330-3c7c-4a02-99c5-d629832e0b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340635770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3340635770
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2853040661
Short name T322
Test name
Test status
Simulation time 550434534249 ps
CPU time 2750.62 seconds
Started Aug 13 06:11:37 PM PDT 24
Finished Aug 13 06:57:28 PM PDT 24
Peak memory 196384 kb
Host smart-42d7c739-fafc-4a7d-a103-5339fbf74d9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853040661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2853040661
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.1187891262
Short name T12
Test name
Test status
Simulation time 1834679530 ps
CPU time 15.76 seconds
Started Aug 13 06:11:38 PM PDT 24
Finished Aug 13 06:11:53 PM PDT 24
Peak memory 194028 kb
Host smart-41afd028-b7e0-4f7c-a693-e09b360baf14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187891262 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.1187891262
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2019928839
Short name T282
Test name
Test status
Simulation time 164174032498 ps
CPU time 88.82 seconds
Started Aug 13 06:11:38 PM PDT 24
Finished Aug 13 06:13:07 PM PDT 24
Peak memory 183568 kb
Host smart-f86d395d-5b1b-4782-b360-9c2c9220d9e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019928839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2019928839
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.534313673
Short name T397
Test name
Test status
Simulation time 48700086316 ps
CPU time 76.6 seconds
Started Aug 13 06:11:37 PM PDT 24
Finished Aug 13 06:12:54 PM PDT 24
Peak memory 183524 kb
Host smart-3f4d1487-94ea-451a-984b-8f63e5161438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534313673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.534313673
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1915322170
Short name T451
Test name
Test status
Simulation time 114579697424 ps
CPU time 63.72 seconds
Started Aug 13 06:11:38 PM PDT 24
Finished Aug 13 06:12:42 PM PDT 24
Peak memory 183644 kb
Host smart-458df198-beb3-4c51-ad8e-1b211a6b066b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915322170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1915322170
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2423396953
Short name T438
Test name
Test status
Simulation time 516393791 ps
CPU time 1.11 seconds
Started Aug 13 06:11:34 PM PDT 24
Finished Aug 13 06:11:35 PM PDT 24
Peak memory 183420 kb
Host smart-b9fecec5-9136-40d8-819c-96edd8736d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423396953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2423396953
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2065563861
Short name T212
Test name
Test status
Simulation time 2977286319323 ps
CPU time 4197.04 seconds
Started Aug 13 06:11:37 PM PDT 24
Finished Aug 13 07:21:35 PM PDT 24
Peak memory 191788 kb
Host smart-8544c54b-7138-454b-b950-a14422704e23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065563861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2065563861
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2280861217
Short name T11
Test name
Test status
Simulation time 6811431804 ps
CPU time 14.94 seconds
Started Aug 13 06:11:38 PM PDT 24
Finished Aug 13 06:11:53 PM PDT 24
Peak memory 194244 kb
Host smart-2feaa83a-032e-4bee-ba1a-2e07532d5ecb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280861217 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2280861217
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.4201884181
Short name T225
Test name
Test status
Simulation time 1255246472216 ps
CPU time 684.94 seconds
Started Aug 13 06:11:44 PM PDT 24
Finished Aug 13 06:23:09 PM PDT 24
Peak memory 183592 kb
Host smart-4716c956-c5a3-464d-8ae0-1682af76c9a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201884181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.4201884181
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.4194505889
Short name T421
Test name
Test status
Simulation time 176930177434 ps
CPU time 145.9 seconds
Started Aug 13 06:11:46 PM PDT 24
Finished Aug 13 06:14:12 PM PDT 24
Peak memory 183616 kb
Host smart-7d2ece24-7e07-4f1b-95d1-ef3571e3946e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194505889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.4194505889
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3880679248
Short name T294
Test name
Test status
Simulation time 52562373563 ps
CPU time 88.99 seconds
Started Aug 13 06:11:46 PM PDT 24
Finished Aug 13 06:13:15 PM PDT 24
Peak memory 191764 kb
Host smart-632d09be-f608-42c6-a7ff-9543961336a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880679248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3880679248
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1657199752
Short name T402
Test name
Test status
Simulation time 163134686 ps
CPU time 0.69 seconds
Started Aug 13 06:11:44 PM PDT 24
Finished Aug 13 06:11:45 PM PDT 24
Peak memory 183152 kb
Host smart-cfd9936e-6cf4-43ac-85fe-09fc3013176d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657199752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1657199752
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1022042417
Short name T265
Test name
Test status
Simulation time 238861913999 ps
CPU time 380.35 seconds
Started Aug 13 06:11:45 PM PDT 24
Finished Aug 13 06:18:05 PM PDT 24
Peak memory 183624 kb
Host smart-995fe6f8-a60f-4ffa-ad1c-6e12bc6590d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022042417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1022042417
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2162808220
Short name T426
Test name
Test status
Simulation time 196130485312 ps
CPU time 74.39 seconds
Started Aug 13 06:11:44 PM PDT 24
Finished Aug 13 06:12:59 PM PDT 24
Peak memory 183592 kb
Host smart-4dbc8160-cc22-4310-a2f0-6c2a3ddeb859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162808220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2162808220
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2813484861
Short name T315
Test name
Test status
Simulation time 383391235039 ps
CPU time 131.8 seconds
Started Aug 13 06:11:44 PM PDT 24
Finished Aug 13 06:13:55 PM PDT 24
Peak memory 183620 kb
Host smart-29a6ab3d-93c8-4a99-b2bc-2c4f64be60eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813484861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2813484861
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2781020309
Short name T234
Test name
Test status
Simulation time 34398838796 ps
CPU time 123.3 seconds
Started Aug 13 06:11:46 PM PDT 24
Finished Aug 13 06:13:50 PM PDT 24
Peak memory 195104 kb
Host smart-94aebf9e-2208-4e0c-9568-d4be534670c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781020309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2781020309
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1273930160
Short name T435
Test name
Test status
Simulation time 53426972970 ps
CPU time 24.38 seconds
Started Aug 13 06:11:43 PM PDT 24
Finished Aug 13 06:12:08 PM PDT 24
Peak memory 183564 kb
Host smart-ab692dd6-3e86-45c3-b44f-481ae08deba6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273930160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1273930160
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2782724655
Short name T42
Test name
Test status
Simulation time 30126557912 ps
CPU time 44.7 seconds
Started Aug 13 06:11:45 PM PDT 24
Finished Aug 13 06:12:30 PM PDT 24
Peak memory 183588 kb
Host smart-f25ad156-5381-48ea-803b-2c7db632b7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782724655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2782724655
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1552557167
Short name T220
Test name
Test status
Simulation time 450732218924 ps
CPU time 446.73 seconds
Started Aug 13 06:11:54 PM PDT 24
Finished Aug 13 06:19:21 PM PDT 24
Peak memory 183552 kb
Host smart-e8a187bb-4799-4bd4-be08-a095195761de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552557167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1552557167
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2758754865
Short name T392
Test name
Test status
Simulation time 54782829286 ps
CPU time 86.16 seconds
Started Aug 13 06:11:52 PM PDT 24
Finished Aug 13 06:13:19 PM PDT 24
Peak memory 183572 kb
Host smart-125be428-57bd-4410-bf99-f8eadab1b6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758754865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2758754865
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.839957322
Short name T360
Test name
Test status
Simulation time 26788202332 ps
CPU time 40.76 seconds
Started Aug 13 06:11:50 PM PDT 24
Finished Aug 13 06:12:31 PM PDT 24
Peak memory 183384 kb
Host smart-7aaf84b1-4036-44a5-a0d7-ada477ed9052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839957322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.839957322
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2454244452
Short name T290
Test name
Test status
Simulation time 121861919292 ps
CPU time 62.07 seconds
Started Aug 13 06:11:54 PM PDT 24
Finished Aug 13 06:12:56 PM PDT 24
Peak memory 191760 kb
Host smart-acd0506a-d25e-470d-8df8-2aec67e1b2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454244452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2454244452
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1439458650
Short name T365
Test name
Test status
Simulation time 96738747525 ps
CPU time 127.67 seconds
Started Aug 13 06:11:52 PM PDT 24
Finished Aug 13 06:14:00 PM PDT 24
Peak memory 191680 kb
Host smart-6eef6bf2-b41b-4196-b628-34a4fd996614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439458650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1439458650
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.583496562
Short name T445
Test name
Test status
Simulation time 16240156435 ps
CPU time 36.37 seconds
Started Aug 13 06:11:53 PM PDT 24
Finished Aug 13 06:12:29 PM PDT 24
Peak memory 198316 kb
Host smart-025a98b5-160f-4d7b-9096-2ce5597b5529
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583496562 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.583496562
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1501488634
Short name T142
Test name
Test status
Simulation time 6831707255 ps
CPU time 11.8 seconds
Started Aug 13 06:11:49 PM PDT 24
Finished Aug 13 06:12:01 PM PDT 24
Peak memory 183564 kb
Host smart-2de11384-08cb-48c0-8526-2ae71a30a7d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501488634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1501488634
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3693502959
Short name T412
Test name
Test status
Simulation time 479338035889 ps
CPU time 154.49 seconds
Started Aug 13 06:11:52 PM PDT 24
Finished Aug 13 06:14:26 PM PDT 24
Peak memory 183568 kb
Host smart-3087c63b-ca27-4e76-a84d-db118acb5819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693502959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3693502959
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2711038577
Short name T259
Test name
Test status
Simulation time 318625341087 ps
CPU time 294.44 seconds
Started Aug 13 06:11:53 PM PDT 24
Finished Aug 13 06:16:47 PM PDT 24
Peak memory 191792 kb
Host smart-475d5480-99f9-4a03-976a-14b61d83bf63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711038577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2711038577
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2297112440
Short name T329
Test name
Test status
Simulation time 190570473182 ps
CPU time 460.04 seconds
Started Aug 13 06:11:53 PM PDT 24
Finished Aug 13 06:19:33 PM PDT 24
Peak memory 191800 kb
Host smart-5b0b2525-ae2b-42a1-a717-f0f1c264e4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297112440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2297112440
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1295223407
Short name T203
Test name
Test status
Simulation time 1465683877573 ps
CPU time 1528.07 seconds
Started Aug 13 06:11:52 PM PDT 24
Finished Aug 13 06:37:20 PM PDT 24
Peak memory 195612 kb
Host smart-1f8eeab3-7b0f-4232-88d3-7dfb93b8c5cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295223407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1295223407
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3748727858
Short name T179
Test name
Test status
Simulation time 40419216688 ps
CPU time 9.28 seconds
Started Aug 13 06:12:03 PM PDT 24
Finished Aug 13 06:12:12 PM PDT 24
Peak memory 183596 kb
Host smart-b30a46dc-8eef-4096-b665-61a12a6e739c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748727858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3748727858
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.800942149
Short name T22
Test name
Test status
Simulation time 153151927542 ps
CPU time 116.96 seconds
Started Aug 13 06:11:53 PM PDT 24
Finished Aug 13 06:13:50 PM PDT 24
Peak memory 183592 kb
Host smart-d65b19be-86a1-4b07-bf0c-059ff76d4373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800942149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.800942149
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.69191420
Short name T338
Test name
Test status
Simulation time 120542970564 ps
CPU time 172.87 seconds
Started Aug 13 06:11:51 PM PDT 24
Finished Aug 13 06:14:44 PM PDT 24
Peak memory 195948 kb
Host smart-514e174b-fcb5-431b-ba2c-752d709fde24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69191420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.69191420
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1351040892
Short name T439
Test name
Test status
Simulation time 191195612 ps
CPU time 0.67 seconds
Started Aug 13 06:12:01 PM PDT 24
Finished Aug 13 06:12:01 PM PDT 24
Peak memory 183284 kb
Host smart-6306ddce-216a-4f02-8548-e38c75a397ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351040892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1351040892
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.814782063
Short name T454
Test name
Test status
Simulation time 456388548252 ps
CPU time 185.26 seconds
Started Aug 13 06:12:00 PM PDT 24
Finished Aug 13 06:15:06 PM PDT 24
Peak memory 195132 kb
Host smart-1bb36461-100b-4c01-b25b-cc5c673bfe80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814782063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
814782063
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2253536285
Short name T248
Test name
Test status
Simulation time 558604970085 ps
CPU time 324.41 seconds
Started Aug 13 06:09:04 PM PDT 24
Finished Aug 13 06:14:29 PM PDT 24
Peak memory 183580 kb
Host smart-98902253-9ecc-4969-bfc9-61ed8194852b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253536285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2253536285
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3182931322
Short name T8
Test name
Test status
Simulation time 185057856131 ps
CPU time 111.26 seconds
Started Aug 13 06:09:04 PM PDT 24
Finished Aug 13 06:10:55 PM PDT 24
Peak memory 183608 kb
Host smart-4012b4fe-6ee9-42a2-b190-016b6224caba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182931322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3182931322
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1806675735
Short name T276
Test name
Test status
Simulation time 369461405248 ps
CPU time 229.06 seconds
Started Aug 13 06:09:08 PM PDT 24
Finished Aug 13 06:12:57 PM PDT 24
Peak memory 191708 kb
Host smart-3d20b713-d53e-41b3-b56a-1e279dbf900a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806675735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1806675735
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2046355625
Short name T197
Test name
Test status
Simulation time 112564898797 ps
CPU time 1784.27 seconds
Started Aug 13 06:09:05 PM PDT 24
Finished Aug 13 06:38:50 PM PDT 24
Peak memory 183560 kb
Host smart-1f555d85-6e85-4c8a-a631-33e4a20617e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046355625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2046355625
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.977206764
Short name T176
Test name
Test status
Simulation time 3222291956077 ps
CPU time 3704.62 seconds
Started Aug 13 06:09:04 PM PDT 24
Finished Aug 13 07:10:49 PM PDT 24
Peak memory 191784 kb
Host smart-1e7091bc-ee18-44de-a7a6-ea1753180974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977206764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.977206764
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.2125803909
Short name T309
Test name
Test status
Simulation time 540249573079 ps
CPU time 416.02 seconds
Started Aug 13 06:12:00 PM PDT 24
Finished Aug 13 06:18:56 PM PDT 24
Peak memory 191792 kb
Host smart-69b706af-3dd2-4682-93f3-4953f388c6d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125803909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2125803909
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2276190030
Short name T247
Test name
Test status
Simulation time 146985888643 ps
CPU time 501.87 seconds
Started Aug 13 06:12:01 PM PDT 24
Finished Aug 13 06:20:23 PM PDT 24
Peak memory 195752 kb
Host smart-039c181b-4148-4c54-9937-d5b0d3884c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276190030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2276190030
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1761938457
Short name T146
Test name
Test status
Simulation time 472379758769 ps
CPU time 184.28 seconds
Started Aug 13 06:12:03 PM PDT 24
Finished Aug 13 06:15:07 PM PDT 24
Peak memory 191808 kb
Host smart-1d999eb0-8fa4-4b59-ae69-4e51082954de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761938457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1761938457
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1866354284
Short name T271
Test name
Test status
Simulation time 99361211565 ps
CPU time 1907.27 seconds
Started Aug 13 06:12:00 PM PDT 24
Finished Aug 13 06:43:47 PM PDT 24
Peak memory 191808 kb
Host smart-53d74fa0-3ef9-4dd1-b25c-bebd0f9cd627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866354284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1866354284
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1034670867
Short name T269
Test name
Test status
Simulation time 104766220095 ps
CPU time 167.05 seconds
Started Aug 13 06:12:03 PM PDT 24
Finished Aug 13 06:14:50 PM PDT 24
Peak memory 183588 kb
Host smart-311be0c6-fae1-4657-b4ce-a9b32062d0c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034670867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1034670867
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3755196638
Short name T99
Test name
Test status
Simulation time 1909614889911 ps
CPU time 523.93 seconds
Started Aug 13 06:12:00 PM PDT 24
Finished Aug 13 06:20:44 PM PDT 24
Peak memory 191736 kb
Host smart-86b2072d-4384-4f91-977d-55a15e34be38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755196638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3755196638
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1219094139
Short name T289
Test name
Test status
Simulation time 97006384034 ps
CPU time 149.76 seconds
Started Aug 13 06:12:02 PM PDT 24
Finished Aug 13 06:14:32 PM PDT 24
Peak memory 191788 kb
Host smart-cd30f3b5-edb4-4e6c-839e-1e46d14b1427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219094139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1219094139
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3147265842
Short name T226
Test name
Test status
Simulation time 38552929386 ps
CPU time 58.73 seconds
Started Aug 13 06:12:01 PM PDT 24
Finished Aug 13 06:13:00 PM PDT 24
Peak memory 192936 kb
Host smart-bc875144-f3a4-4a4a-9cab-56b8dffc5a51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147265842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3147265842
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.4033179291
Short name T217
Test name
Test status
Simulation time 123737064639 ps
CPU time 288.82 seconds
Started Aug 13 06:11:59 PM PDT 24
Finished Aug 13 06:16:48 PM PDT 24
Peak memory 191800 kb
Host smart-71c91e18-1f7f-4400-867e-dcaa13c2c948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033179291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.4033179291
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.583225229
Short name T185
Test name
Test status
Simulation time 993540948 ps
CPU time 1.42 seconds
Started Aug 13 06:09:12 PM PDT 24
Finished Aug 13 06:09:13 PM PDT 24
Peak memory 183220 kb
Host smart-37685d9e-3dbc-4f49-95f9-a903714eb6f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583225229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.583225229
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3629579955
Short name T380
Test name
Test status
Simulation time 848568337427 ps
CPU time 177.01 seconds
Started Aug 13 06:09:13 PM PDT 24
Finished Aug 13 06:12:10 PM PDT 24
Peak memory 183556 kb
Host smart-10b5e25b-0ca7-44ec-a02d-84895783a640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629579955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3629579955
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1214954191
Short name T320
Test name
Test status
Simulation time 103455895159 ps
CPU time 157.3 seconds
Started Aug 13 06:09:05 PM PDT 24
Finished Aug 13 06:11:42 PM PDT 24
Peak memory 191752 kb
Host smart-ffebbc5f-e129-4c7e-b3d4-6f3abbcebbc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214954191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1214954191
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1640159814
Short name T415
Test name
Test status
Simulation time 238489769 ps
CPU time 1.02 seconds
Started Aug 13 06:09:10 PM PDT 24
Finished Aug 13 06:09:11 PM PDT 24
Peak memory 183284 kb
Host smart-cd55f994-31b0-4c8e-9014-054a09cb0608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640159814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1640159814
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2664525617
Short name T192
Test name
Test status
Simulation time 1053407880338 ps
CPU time 836.46 seconds
Started Aug 13 06:09:12 PM PDT 24
Finished Aug 13 06:23:09 PM PDT 24
Peak memory 191804 kb
Host smart-67baacd1-c5e9-4ef1-a5c8-159b461aa9aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664525617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2664525617
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.3692182982
Short name T227
Test name
Test status
Simulation time 544832339443 ps
CPU time 1490.41 seconds
Started Aug 13 06:11:59 PM PDT 24
Finished Aug 13 06:36:50 PM PDT 24
Peak memory 191724 kb
Host smart-ee85847d-5f99-4781-b980-410c164a55c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692182982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3692182982
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3737923799
Short name T152
Test name
Test status
Simulation time 974744054761 ps
CPU time 843.64 seconds
Started Aug 13 06:12:01 PM PDT 24
Finished Aug 13 06:26:04 PM PDT 24
Peak memory 191832 kb
Host smart-ee86a3d9-d304-4d0c-ae86-89fb11f00764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737923799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3737923799
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.4102065039
Short name T275
Test name
Test status
Simulation time 72159740308 ps
CPU time 172.93 seconds
Started Aug 13 06:12:00 PM PDT 24
Finished Aug 13 06:14:53 PM PDT 24
Peak memory 191804 kb
Host smart-a3e76002-9d91-437c-a1ba-380b9a724281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102065039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.4102065039
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.564613810
Short name T119
Test name
Test status
Simulation time 340724681385 ps
CPU time 151.79 seconds
Started Aug 13 06:11:59 PM PDT 24
Finished Aug 13 06:14:31 PM PDT 24
Peak memory 191780 kb
Host smart-89e876da-92d4-4367-8791-bc8f93d37b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564613810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.564613810
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2527714718
Short name T296
Test name
Test status
Simulation time 130451424836 ps
CPU time 26.62 seconds
Started Aug 13 06:12:03 PM PDT 24
Finished Aug 13 06:12:30 PM PDT 24
Peak memory 183588 kb
Host smart-b33dab8f-405b-468c-883e-dd370af18f56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527714718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2527714718
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1216674866
Short name T283
Test name
Test status
Simulation time 213605644803 ps
CPU time 126.88 seconds
Started Aug 13 06:12:00 PM PDT 24
Finished Aug 13 06:14:07 PM PDT 24
Peak memory 191800 kb
Host smart-d4fa9132-5ac6-40ff-a8a3-468b3f66b13d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216674866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1216674866
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.4198262535
Short name T124
Test name
Test status
Simulation time 464307044557 ps
CPU time 82.11 seconds
Started Aug 13 06:12:12 PM PDT 24
Finished Aug 13 06:13:35 PM PDT 24
Peak memory 183464 kb
Host smart-f95c4420-3c9b-4f0d-8232-260d7b7f8fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198262535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4198262535
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3633602915
Short name T361
Test name
Test status
Simulation time 276043257028 ps
CPU time 128.36 seconds
Started Aug 13 06:12:12 PM PDT 24
Finished Aug 13 06:14:21 PM PDT 24
Peak memory 191660 kb
Host smart-3fbd5278-f119-496b-8fb1-43dcabf0d962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633602915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3633602915
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3145194628
Short name T151
Test name
Test status
Simulation time 392131148 ps
CPU time 1.03 seconds
Started Aug 13 06:09:13 PM PDT 24
Finished Aug 13 06:09:14 PM PDT 24
Peak memory 183268 kb
Host smart-461e7a01-9a07-43f8-ac6b-3ae497b36539
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145194628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3145194628
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.946731231
Short name T379
Test name
Test status
Simulation time 296590919697 ps
CPU time 108 seconds
Started Aug 13 06:09:13 PM PDT 24
Finished Aug 13 06:11:01 PM PDT 24
Peak memory 183576 kb
Host smart-f022bde2-33e3-421d-bc01-50ef285ca77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946731231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.946731231
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.69231780
Short name T100
Test name
Test status
Simulation time 81308894943 ps
CPU time 157.12 seconds
Started Aug 13 06:09:12 PM PDT 24
Finished Aug 13 06:11:50 PM PDT 24
Peak memory 191760 kb
Host smart-2f7dd7f2-91b2-4843-91e4-391447874c4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69231780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.69231780
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1806319225
Short name T416
Test name
Test status
Simulation time 892650848 ps
CPU time 2.23 seconds
Started Aug 13 06:09:13 PM PDT 24
Finished Aug 13 06:09:15 PM PDT 24
Peak memory 194836 kb
Host smart-e5dfad9c-b4cb-4800-bf73-75acef596954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806319225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1806319225
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3689018667
Short name T350
Test name
Test status
Simulation time 913159754073 ps
CPU time 544.32 seconds
Started Aug 13 06:09:12 PM PDT 24
Finished Aug 13 06:18:16 PM PDT 24
Peak memory 191744 kb
Host smart-1dd2e7be-5521-45e2-8396-c716223f43d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689018667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3689018667
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.902083391
Short name T34
Test name
Test status
Simulation time 17354309274 ps
CPU time 50.35 seconds
Started Aug 13 06:09:16 PM PDT 24
Finished Aug 13 06:10:06 PM PDT 24
Peak memory 196192 kb
Host smart-3ca9e6fd-50b6-4ec4-b295-f4a0d08eac00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902083391 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.902083391
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.287930609
Short name T272
Test name
Test status
Simulation time 78801728373 ps
CPU time 162.83 seconds
Started Aug 13 06:12:10 PM PDT 24
Finished Aug 13 06:14:53 PM PDT 24
Peak memory 195428 kb
Host smart-66b9512e-afb8-482e-bbb5-5f9d8d9d42ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287930609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.287930609
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.355297316
Short name T307
Test name
Test status
Simulation time 70492627095 ps
CPU time 1120.98 seconds
Started Aug 13 06:12:09 PM PDT 24
Finished Aug 13 06:30:50 PM PDT 24
Peak memory 191800 kb
Host smart-c9265328-e03d-43da-9179-5f87db11517f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355297316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.355297316
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.397005544
Short name T121
Test name
Test status
Simulation time 360625744541 ps
CPU time 1875.49 seconds
Started Aug 13 06:12:12 PM PDT 24
Finished Aug 13 06:43:27 PM PDT 24
Peak memory 193176 kb
Host smart-b1cc7f77-4125-4b22-a820-8ec50b704d07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397005544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.397005544
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2552395177
Short name T147
Test name
Test status
Simulation time 178721280680 ps
CPU time 133.15 seconds
Started Aug 13 06:12:10 PM PDT 24
Finished Aug 13 06:14:24 PM PDT 24
Peak memory 191736 kb
Host smart-9ea157b5-5dfd-4d2b-93ff-2ca9c7890464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552395177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2552395177
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3263749670
Short name T232
Test name
Test status
Simulation time 240835200271 ps
CPU time 223.79 seconds
Started Aug 13 06:12:12 PM PDT 24
Finished Aug 13 06:15:55 PM PDT 24
Peak memory 191804 kb
Host smart-b0592fe5-6b9c-4501-9e79-c733819cb2bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263749670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3263749670
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1205261684
Short name T331
Test name
Test status
Simulation time 232438701912 ps
CPU time 179.92 seconds
Started Aug 13 06:12:09 PM PDT 24
Finished Aug 13 06:15:09 PM PDT 24
Peak memory 192796 kb
Host smart-f36f9a32-1b25-4d50-8187-648ab4253a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205261684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1205261684
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2404182212
Short name T120
Test name
Test status
Simulation time 108670074885 ps
CPU time 399.38 seconds
Started Aug 13 06:12:10 PM PDT 24
Finished Aug 13 06:18:50 PM PDT 24
Peak memory 191744 kb
Host smart-97b51793-795d-4169-ad0d-9f03bf662117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404182212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2404182212
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1331177350
Short name T239
Test name
Test status
Simulation time 144129570212 ps
CPU time 222.04 seconds
Started Aug 13 06:12:10 PM PDT 24
Finished Aug 13 06:15:52 PM PDT 24
Peak memory 191796 kb
Host smart-7a35cc9b-61ab-4881-87b9-93c35d3166b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331177350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1331177350
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.701555951
Short name T362
Test name
Test status
Simulation time 49255977883 ps
CPU time 44.06 seconds
Started Aug 13 06:09:16 PM PDT 24
Finished Aug 13 06:10:00 PM PDT 24
Peak memory 183520 kb
Host smart-e3c7079b-0315-426a-9fea-fefb55812372
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701555951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.701555951
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2284101879
Short name T452
Test name
Test status
Simulation time 229850497019 ps
CPU time 159.28 seconds
Started Aug 13 06:09:14 PM PDT 24
Finished Aug 13 06:11:53 PM PDT 24
Peak memory 183468 kb
Host smart-d77e2d5b-aaf8-4271-962b-0db1564d74ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284101879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2284101879
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.412857847
Short name T442
Test name
Test status
Simulation time 655896907 ps
CPU time 0.83 seconds
Started Aug 13 06:09:13 PM PDT 24
Finished Aug 13 06:09:14 PM PDT 24
Peak memory 183152 kb
Host smart-81837c96-d202-4675-a074-7e70c0467f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412857847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.412857847
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2700022566
Short name T218
Test name
Test status
Simulation time 32182712801 ps
CPU time 45.44 seconds
Started Aug 13 06:09:12 PM PDT 24
Finished Aug 13 06:09:57 PM PDT 24
Peak memory 195396 kb
Host smart-3b0b13d3-d541-4bbc-a10b-6e6f63c3fe4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700022566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2700022566
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.1413077194
Short name T167
Test name
Test status
Simulation time 36860887598 ps
CPU time 49.87 seconds
Started Aug 13 06:12:11 PM PDT 24
Finished Aug 13 06:13:01 PM PDT 24
Peak memory 191836 kb
Host smart-cdc36139-6242-4aca-b4ab-aa4f7f881d13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413077194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1413077194
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.291070728
Short name T118
Test name
Test status
Simulation time 242687494418 ps
CPU time 179.13 seconds
Started Aug 13 06:12:17 PM PDT 24
Finished Aug 13 06:15:17 PM PDT 24
Peak memory 191796 kb
Host smart-0af3a7cc-b207-43eb-be86-d50179bab6eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291070728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.291070728
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1198348750
Short name T327
Test name
Test status
Simulation time 117781730462 ps
CPU time 180.32 seconds
Started Aug 13 06:12:18 PM PDT 24
Finished Aug 13 06:15:19 PM PDT 24
Peak memory 191836 kb
Host smart-a9df6204-1c03-4203-bd5b-cac1eb7bff6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198348750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1198348750
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.4110657718
Short name T97
Test name
Test status
Simulation time 309080396617 ps
CPU time 165.13 seconds
Started Aug 13 06:12:27 PM PDT 24
Finished Aug 13 06:15:12 PM PDT 24
Peak memory 191760 kb
Host smart-0c453552-9532-42cc-bbde-0132f9a518f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110657718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.4110657718
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3557024623
Short name T132
Test name
Test status
Simulation time 9221617337 ps
CPU time 2.25 seconds
Started Aug 13 06:12:16 PM PDT 24
Finished Aug 13 06:12:18 PM PDT 24
Peak memory 183580 kb
Host smart-6590b782-5271-4605-ad4e-cd8d309f6a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557024623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3557024623
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3087805057
Short name T127
Test name
Test status
Simulation time 249545932409 ps
CPU time 153.84 seconds
Started Aug 13 06:12:20 PM PDT 24
Finished Aug 13 06:14:54 PM PDT 24
Peak memory 191732 kb
Host smart-228a4f33-2453-4d2b-8c8e-dc6ad2adca7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087805057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3087805057
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.4211062083
Short name T117
Test name
Test status
Simulation time 143440039149 ps
CPU time 206.61 seconds
Started Aug 13 06:12:26 PM PDT 24
Finished Aug 13 06:15:53 PM PDT 24
Peak memory 191780 kb
Host smart-92b00f6c-384e-4fb7-9640-3b18185cb115
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211062083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.4211062083
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.4081513962
Short name T378
Test name
Test status
Simulation time 313376474494 ps
CPU time 141.1 seconds
Started Aug 13 06:09:26 PM PDT 24
Finished Aug 13 06:11:48 PM PDT 24
Peak memory 183368 kb
Host smart-8dfddd16-88ec-4369-9c72-096adb7936bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081513962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.4081513962
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.249994283
Short name T321
Test name
Test status
Simulation time 245017835616 ps
CPU time 227.43 seconds
Started Aug 13 06:09:26 PM PDT 24
Finished Aug 13 06:13:14 PM PDT 24
Peak memory 191664 kb
Host smart-4229157c-9114-458b-9904-a05b0a0f5074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249994283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.249994283
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3880986598
Short name T3
Test name
Test status
Simulation time 172879664 ps
CPU time 0.66 seconds
Started Aug 13 06:09:21 PM PDT 24
Finished Aug 13 06:09:22 PM PDT 24
Peak memory 183288 kb
Host smart-e5dbd719-2c1a-482a-b1df-8ecf3037e993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880986598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3880986598
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.960710790
Short name T199
Test name
Test status
Simulation time 722225490102 ps
CPU time 599.92 seconds
Started Aug 13 06:12:17 PM PDT 24
Finished Aug 13 06:22:17 PM PDT 24
Peak memory 191924 kb
Host smart-1ad9f534-7f75-47a3-abdd-9b1ebf368dc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960710790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.960710790
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3127536089
Short name T44
Test name
Test status
Simulation time 173552256336 ps
CPU time 429.97 seconds
Started Aug 13 06:12:17 PM PDT 24
Finished Aug 13 06:19:27 PM PDT 24
Peak memory 191780 kb
Host smart-6570de37-899c-4a37-a773-a0b586dd8801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127536089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3127536089
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1043384750
Short name T200
Test name
Test status
Simulation time 959045458458 ps
CPU time 662.23 seconds
Started Aug 13 06:12:22 PM PDT 24
Finished Aug 13 06:23:25 PM PDT 24
Peak memory 191792 kb
Host smart-b528371a-ef04-4c66-b5b9-5ea5b6850bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043384750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1043384750
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1195379200
Short name T136
Test name
Test status
Simulation time 373487759963 ps
CPU time 1026.97 seconds
Started Aug 13 06:12:26 PM PDT 24
Finished Aug 13 06:29:33 PM PDT 24
Peak memory 191784 kb
Host smart-d9147e26-eb8e-4239-b8c7-01f8dcb9cf32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195379200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1195379200
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3903051093
Short name T223
Test name
Test status
Simulation time 45118611629 ps
CPU time 77.23 seconds
Started Aug 13 06:12:23 PM PDT 24
Finished Aug 13 06:13:40 PM PDT 24
Peak memory 183592 kb
Host smart-5629fdbc-84c3-48ff-8cb8-81063dfa4e69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903051093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3903051093
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2139529317
Short name T274
Test name
Test status
Simulation time 115684905022 ps
CPU time 458.12 seconds
Started Aug 13 06:12:27 PM PDT 24
Finished Aug 13 06:20:05 PM PDT 24
Peak memory 191780 kb
Host smart-a9b8b6c2-5d7c-490b-9fe7-00111c165dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139529317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2139529317
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1339123775
Short name T304
Test name
Test status
Simulation time 281058802100 ps
CPU time 274.81 seconds
Started Aug 13 06:12:22 PM PDT 24
Finished Aug 13 06:16:57 PM PDT 24
Peak memory 191796 kb
Host smart-995a653e-fb8e-40f3-a11d-b7faebc344ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339123775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1339123775
Directory /workspace/99.rv_timer_random/latest
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