Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 584
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T510 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1582818502 Aug 14 04:45:05 PM PDT 24 Aug 14 04:45:06 PM PDT 24 16263827 ps
T511 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2396030508 Aug 14 04:45:35 PM PDT 24 Aug 14 04:45:36 PM PDT 24 11404027 ps
T72 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3134217694 Aug 14 04:45:11 PM PDT 24 Aug 14 04:45:12 PM PDT 24 127023111 ps
T512 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2493976420 Aug 14 04:45:06 PM PDT 24 Aug 14 04:45:07 PM PDT 24 26932396 ps
T513 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3011021507 Aug 14 04:45:23 PM PDT 24 Aug 14 04:45:31 PM PDT 24 634767236 ps
T514 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.831568305 Aug 14 04:45:05 PM PDT 24 Aug 14 04:45:06 PM PDT 24 19252095 ps
T515 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3453078016 Aug 14 04:45:07 PM PDT 24 Aug 14 04:45:08 PM PDT 24 12006714 ps
T516 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1269857616 Aug 14 04:45:51 PM PDT 24 Aug 14 04:45:57 PM PDT 24 165731609 ps
T87 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.657549360 Aug 14 04:45:49 PM PDT 24 Aug 14 04:45:51 PM PDT 24 166469759 ps
T517 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.660928677 Aug 14 04:45:09 PM PDT 24 Aug 14 04:45:10 PM PDT 24 35782763 ps
T518 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.243220539 Aug 14 04:45:39 PM PDT 24 Aug 14 04:45:40 PM PDT 24 39774739 ps
T519 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2106263721 Aug 14 04:45:03 PM PDT 24 Aug 14 04:45:04 PM PDT 24 76846467 ps
T520 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2000339855 Aug 14 04:45:26 PM PDT 24 Aug 14 04:45:27 PM PDT 24 11001491 ps
T521 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.277797327 Aug 14 04:45:35 PM PDT 24 Aug 14 04:45:36 PM PDT 24 234825327 ps
T76 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2276002459 Aug 14 04:45:06 PM PDT 24 Aug 14 04:45:07 PM PDT 24 51229996 ps
T522 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2831365397 Aug 14 04:45:35 PM PDT 24 Aug 14 04:45:36 PM PDT 24 113560590 ps
T77 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.952037508 Aug 14 04:45:06 PM PDT 24 Aug 14 04:45:07 PM PDT 24 25291011 ps
T73 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1882481934 Aug 14 04:45:06 PM PDT 24 Aug 14 04:45:07 PM PDT 24 51595910 ps
T523 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.4011077803 Aug 14 04:45:03 PM PDT 24 Aug 14 04:45:04 PM PDT 24 28366820 ps
T524 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2175061394 Aug 14 04:45:04 PM PDT 24 Aug 14 04:45:06 PM PDT 24 79397402 ps
T525 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.569613626 Aug 14 04:45:27 PM PDT 24 Aug 14 04:45:27 PM PDT 24 70700302 ps
T526 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1129254715 Aug 14 04:45:17 PM PDT 24 Aug 14 04:45:19 PM PDT 24 59646079 ps
T527 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1774247812 Aug 14 04:45:06 PM PDT 24 Aug 14 04:45:07 PM PDT 24 40339356 ps
T74 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3242599322 Aug 14 04:45:11 PM PDT 24 Aug 14 04:45:12 PM PDT 24 30503342 ps
T528 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2220406373 Aug 14 04:45:05 PM PDT 24 Aug 14 04:45:07 PM PDT 24 1243265555 ps
T529 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1654476944 Aug 14 04:45:23 PM PDT 24 Aug 14 04:45:29 PM PDT 24 21530819 ps
T530 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.886473350 Aug 14 04:45:39 PM PDT 24 Aug 14 04:45:39 PM PDT 24 159105833 ps
T531 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4133222226 Aug 14 04:45:04 PM PDT 24 Aug 14 04:45:05 PM PDT 24 173917700 ps
T532 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.742298921 Aug 14 04:45:05 PM PDT 24 Aug 14 04:45:06 PM PDT 24 40332115 ps
T533 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1560052019 Aug 14 04:45:09 PM PDT 24 Aug 14 04:45:10 PM PDT 24 57896295 ps
T534 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2389136993 Aug 14 04:45:07 PM PDT 24 Aug 14 04:45:08 PM PDT 24 28175988 ps
T535 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1856362513 Aug 14 04:45:17 PM PDT 24 Aug 14 04:45:17 PM PDT 24 33328694 ps
T536 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1059866924 Aug 14 04:45:23 PM PDT 24 Aug 14 04:45:23 PM PDT 24 17857331 ps
T75 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1538909483 Aug 14 04:45:05 PM PDT 24 Aug 14 04:45:06 PM PDT 24 15035646 ps
T537 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.917292013 Aug 14 04:45:06 PM PDT 24 Aug 14 04:45:07 PM PDT 24 14255459 ps
T538 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1127306240 Aug 14 04:45:05 PM PDT 24 Aug 14 04:45:06 PM PDT 24 24142636 ps
T539 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3157834522 Aug 14 04:45:03 PM PDT 24 Aug 14 04:45:04 PM PDT 24 110134571 ps
T540 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1504799157 Aug 14 04:45:06 PM PDT 24 Aug 14 04:45:07 PM PDT 24 144636119 ps
T541 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3303411580 Aug 14 04:45:52 PM PDT 24 Aug 14 04:45:53 PM PDT 24 39435773 ps
T542 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3881385490 Aug 14 04:45:49 PM PDT 24 Aug 14 04:45:50 PM PDT 24 217662006 ps
T543 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2939377790 Aug 14 04:45:16 PM PDT 24 Aug 14 04:45:17 PM PDT 24 103938926 ps
T544 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.840166017 Aug 14 04:45:13 PM PDT 24 Aug 14 04:45:14 PM PDT 24 42528645 ps
T545 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.4071696889 Aug 14 04:45:11 PM PDT 24 Aug 14 04:45:12 PM PDT 24 84498077 ps
T546 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2531860182 Aug 14 04:45:04 PM PDT 24 Aug 14 04:45:05 PM PDT 24 12556952 ps
T547 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1449570098 Aug 14 04:45:11 PM PDT 24 Aug 14 04:45:18 PM PDT 24 312234869 ps
T548 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1790348837 Aug 14 04:45:06 PM PDT 24 Aug 14 04:45:07 PM PDT 24 28668283 ps
T549 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3419436599 Aug 14 04:45:18 PM PDT 24 Aug 14 04:45:19 PM PDT 24 95503865 ps
T550 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2490449172 Aug 14 04:45:08 PM PDT 24 Aug 14 04:45:09 PM PDT 24 100586776 ps
T551 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2839147239 Aug 14 04:45:04 PM PDT 24 Aug 14 04:45:05 PM PDT 24 154265142 ps
T552 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.659227732 Aug 14 04:45:31 PM PDT 24 Aug 14 04:45:34 PM PDT 24 574218181 ps
T553 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1060117302 Aug 14 04:45:40 PM PDT 24 Aug 14 04:45:41 PM PDT 24 31327342 ps
T554 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3285675331 Aug 14 04:45:24 PM PDT 24 Aug 14 04:45:25 PM PDT 24 37047651 ps
T555 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4084202924 Aug 14 04:45:05 PM PDT 24 Aug 14 04:45:06 PM PDT 24 34271536 ps
T556 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.306896042 Aug 14 04:45:14 PM PDT 24 Aug 14 04:45:15 PM PDT 24 16798820 ps
T557 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3772201381 Aug 14 04:45:44 PM PDT 24 Aug 14 04:45:45 PM PDT 24 14566891 ps
T558 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.4154124740 Aug 14 04:45:09 PM PDT 24 Aug 14 04:45:09 PM PDT 24 69125850 ps
T559 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2814603761 Aug 14 04:45:35 PM PDT 24 Aug 14 04:45:36 PM PDT 24 43844129 ps
T560 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3334817698 Aug 14 04:45:13 PM PDT 24 Aug 14 04:45:15 PM PDT 24 123029154 ps
T561 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3980289908 Aug 14 04:45:30 PM PDT 24 Aug 14 04:45:30 PM PDT 24 25000492 ps
T562 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1165480317 Aug 14 04:45:06 PM PDT 24 Aug 14 04:45:07 PM PDT 24 12090423 ps
T563 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.249472550 Aug 14 04:45:06 PM PDT 24 Aug 14 04:45:07 PM PDT 24 51079938 ps
T564 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.4224375350 Aug 14 04:45:33 PM PDT 24 Aug 14 04:45:34 PM PDT 24 18531237 ps
T565 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3459730017 Aug 14 04:45:43 PM PDT 24 Aug 14 04:45:44 PM PDT 24 24374230 ps
T566 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2435346927 Aug 14 04:45:16 PM PDT 24 Aug 14 04:45:16 PM PDT 24 74809454 ps
T567 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2115824731 Aug 14 04:45:22 PM PDT 24 Aug 14 04:45:23 PM PDT 24 77968965 ps
T568 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.414708084 Aug 14 04:45:06 PM PDT 24 Aug 14 04:45:07 PM PDT 24 200493793 ps
T569 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2514516295 Aug 14 04:45:12 PM PDT 24 Aug 14 04:45:18 PM PDT 24 346071087 ps
T570 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1776376780 Aug 14 04:45:34 PM PDT 24 Aug 14 04:45:35 PM PDT 24 53755649 ps
T571 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1248866382 Aug 14 04:45:23 PM PDT 24 Aug 14 04:45:24 PM PDT 24 36283743 ps
T78 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2335335200 Aug 14 04:45:08 PM PDT 24 Aug 14 04:45:08 PM PDT 24 44285205 ps
T572 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.369654815 Aug 14 04:45:05 PM PDT 24 Aug 14 04:45:06 PM PDT 24 19864694 ps
T573 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.898639813 Aug 14 04:45:23 PM PDT 24 Aug 14 04:45:24 PM PDT 24 103102587 ps
T574 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.511659552 Aug 14 04:45:18 PM PDT 24 Aug 14 04:45:19 PM PDT 24 45054840 ps
T575 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1294411461 Aug 14 04:45:28 PM PDT 24 Aug 14 04:45:29 PM PDT 24 12048509 ps
T576 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1540904845 Aug 14 04:45:09 PM PDT 24 Aug 14 04:45:10 PM PDT 24 37148512 ps
T577 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1264886348 Aug 14 04:45:44 PM PDT 24 Aug 14 04:45:46 PM PDT 24 425662494 ps
T578 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1301105699 Aug 14 04:45:26 PM PDT 24 Aug 14 04:45:26 PM PDT 24 24734867 ps
T579 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3960013595 Aug 14 04:45:13 PM PDT 24 Aug 14 04:45:14 PM PDT 24 100741192 ps
T580 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2200608774 Aug 14 04:45:05 PM PDT 24 Aug 14 04:45:07 PM PDT 24 23740860 ps
T581 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3988219402 Aug 14 04:45:28 PM PDT 24 Aug 14 04:45:29 PM PDT 24 58929266 ps
T79 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3497177152 Aug 14 04:45:26 PM PDT 24 Aug 14 04:45:26 PM PDT 24 14367129 ps
T582 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1231797942 Aug 14 04:45:30 PM PDT 24 Aug 14 04:45:31 PM PDT 24 241188703 ps
T583 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2496787478 Aug 14 04:45:04 PM PDT 24 Aug 14 04:45:06 PM PDT 24 224323825 ps
T584 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2549177047 Aug 14 04:45:08 PM PDT 24 Aug 14 04:45:09 PM PDT 24 108593021 ps

Test location /workspace/coverage/default/30.rv_timer_stress_all.1790253013
Short name T7
Test name
Test status
Simulation time 360367996739 ps
CPU time 141.83 seconds
Started Aug 14 04:49:15 PM PDT 24
Finished Aug 14 04:51:37 PM PDT 24
Peak memory 191672 kb
Host smart-afd6fb63-3526-476f-bac9-a2ccf49b7bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790253013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1790253013
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1905913604
Short name T11
Test name
Test status
Simulation time 4782580829 ps
CPU time 11.03 seconds
Started Aug 14 04:48:30 PM PDT 24
Finished Aug 14 04:48:41 PM PDT 24
Peak memory 198312 kb
Host smart-c8caed99-9c80-40aa-ba20-1ae3d3a7bd04
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905913604 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1905913604
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.rv_timer_random.3809747333
Short name T13
Test name
Test status
Simulation time 954577277977 ps
CPU time 380.04 seconds
Started Aug 14 04:49:59 PM PDT 24
Finished Aug 14 04:56:19 PM PDT 24
Peak memory 191064 kb
Host smart-e82ae245-e463-4dd8-bd2f-4a79cdfd7f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809747333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3809747333
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.940809674
Short name T29
Test name
Test status
Simulation time 37814122 ps
CPU time 0.82 seconds
Started Aug 14 04:45:24 PM PDT 24
Finished Aug 14 04:45:25 PM PDT 24
Peak memory 193732 kb
Host smart-8e6b0d1a-1d43-4127-a6d6-cf982e4fb923
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940809674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.940809674
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1855244112
Short name T152
Test name
Test status
Simulation time 948009972927 ps
CPU time 2229.31 seconds
Started Aug 14 04:49:12 PM PDT 24
Finished Aug 14 05:26:22 PM PDT 24
Peak memory 191796 kb
Host smart-cd96e14d-92cf-4705-b1ce-da999c50fdd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855244112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1855244112
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.2396824359
Short name T91
Test name
Test status
Simulation time 304444863359 ps
CPU time 604.33 seconds
Started Aug 14 04:49:38 PM PDT 24
Finished Aug 14 04:59:43 PM PDT 24
Peak memory 191728 kb
Host smart-60c7216f-efdf-41ba-a6ea-73579715275a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396824359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.2396824359
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1109853227
Short name T199
Test name
Test status
Simulation time 615851476065 ps
CPU time 4243.98 seconds
Started Aug 14 04:49:23 PM PDT 24
Finished Aug 14 06:00:07 PM PDT 24
Peak memory 191680 kb
Host smart-5f7f92d1-f11b-48b0-994d-11331f7e30ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109853227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1109853227
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3074238388
Short name T156
Test name
Test status
Simulation time 2841009232248 ps
CPU time 2037.23 seconds
Started Aug 14 04:48:49 PM PDT 24
Finished Aug 14 05:22:47 PM PDT 24
Peak memory 191796 kb
Host smart-326118e0-3de1-4a83-80dc-13e3ec092ac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074238388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3074238388
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2088010157
Short name T139
Test name
Test status
Simulation time 733962474327 ps
CPU time 1641.58 seconds
Started Aug 14 04:48:54 PM PDT 24
Finished Aug 14 05:16:16 PM PDT 24
Peak memory 196652 kb
Host smart-d05205ea-f113-4762-aeab-99f65a87e6df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088010157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2088010157
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3533066335
Short name T265
Test name
Test status
Simulation time 2278493420472 ps
CPU time 1918.14 seconds
Started Aug 14 04:49:22 PM PDT 24
Finished Aug 14 05:21:20 PM PDT 24
Peak memory 190776 kb
Host smart-a2a744b5-1bbb-4ce7-8489-2c470b38c926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533066335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3533066335
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1184623544
Short name T103
Test name
Test status
Simulation time 664554613318 ps
CPU time 373.73 seconds
Started Aug 14 04:49:27 PM PDT 24
Finished Aug 14 04:55:41 PM PDT 24
Peak memory 191792 kb
Host smart-2ea2d504-8a4f-4c74-8fd4-5aa880554374
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184623544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1184623544
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3956831819
Short name T33
Test name
Test status
Simulation time 421055571 ps
CPU time 3.77 seconds
Started Aug 14 04:45:19 PM PDT 24
Finished Aug 14 04:45:22 PM PDT 24
Peak memory 183608 kb
Host smart-9803fc4c-c7d6-4892-942e-ea549a125485
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956831819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3956831819
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2717740097
Short name T162
Test name
Test status
Simulation time 409858847015 ps
CPU time 1327.72 seconds
Started Aug 14 04:48:23 PM PDT 24
Finished Aug 14 05:10:31 PM PDT 24
Peak memory 196464 kb
Host smart-43c1c52a-2a4b-4203-8c71-b1b1008fa812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717740097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2717740097
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1958314231
Short name T144
Test name
Test status
Simulation time 1704809945586 ps
CPU time 1418.5 seconds
Started Aug 14 04:49:30 PM PDT 24
Finished Aug 14 05:13:09 PM PDT 24
Peak memory 191728 kb
Host smart-43007554-8324-4a40-bfcc-8a6f2178608d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958314231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1958314231
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.3615733192
Short name T47
Test name
Test status
Simulation time 489298181660 ps
CPU time 297.15 seconds
Started Aug 14 04:50:06 PM PDT 24
Finished Aug 14 04:55:03 PM PDT 24
Peak memory 191792 kb
Host smart-00d45df8-de27-4c36-8d39-ba953607e560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615733192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3615733192
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.6523035
Short name T19
Test name
Test status
Simulation time 185962443 ps
CPU time 0.93 seconds
Started Aug 14 04:48:28 PM PDT 24
Finished Aug 14 04:48:29 PM PDT 24
Peak memory 216488 kb
Host smart-fabdd711-434a-4524-9808-27ad603c0773
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6523035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.6523035
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/59.rv_timer_random.822117919
Short name T88
Test name
Test status
Simulation time 74736277490 ps
CPU time 139.53 seconds
Started Aug 14 04:49:58 PM PDT 24
Finished Aug 14 04:52:17 PM PDT 24
Peak memory 191716 kb
Host smart-13771aa4-0057-4604-a474-32fcbea7bbf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822117919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.822117919
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.4222397121
Short name T194
Test name
Test status
Simulation time 386240990614 ps
CPU time 987.81 seconds
Started Aug 14 04:48:33 PM PDT 24
Finished Aug 14 05:05:01 PM PDT 24
Peak memory 191784 kb
Host smart-43231847-5617-43e4-8ee6-52a06c5c7e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222397121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
4222397121
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/153.rv_timer_random.3828708727
Short name T114
Test name
Test status
Simulation time 131651420581 ps
CPU time 423.45 seconds
Started Aug 14 04:50:35 PM PDT 24
Finished Aug 14 04:57:38 PM PDT 24
Peak memory 191708 kb
Host smart-fcc8e4ab-8136-48bb-a1db-46a4a1fe4660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828708727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3828708727
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.641597198
Short name T95
Test name
Test status
Simulation time 130619750005 ps
CPU time 200.18 seconds
Started Aug 14 04:50:38 PM PDT 24
Finished Aug 14 04:53:59 PM PDT 24
Peak memory 194268 kb
Host smart-48340d74-e554-4882-97f7-da6a9f1ccd33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641597198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.641597198
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3112495303
Short name T104
Test name
Test status
Simulation time 414356792159 ps
CPU time 1178.01 seconds
Started Aug 14 04:50:42 PM PDT 24
Finished Aug 14 05:10:20 PM PDT 24
Peak memory 191816 kb
Host smart-f1dce524-a897-42f2-886e-eb6f7b85c8f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112495303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3112495303
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3617070468
Short name T97
Test name
Test status
Simulation time 181811086357 ps
CPU time 1857.59 seconds
Started Aug 14 04:50:33 PM PDT 24
Finished Aug 14 05:21:31 PM PDT 24
Peak memory 191828 kb
Host smart-f363de7d-4a43-49c1-96f9-126d38aa745d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617070468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3617070468
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.799909512
Short name T200
Test name
Test status
Simulation time 1190547189639 ps
CPU time 550.8 seconds
Started Aug 14 04:49:13 PM PDT 24
Finished Aug 14 04:58:24 PM PDT 24
Peak memory 196504 kb
Host smart-684fb289-fdd5-445f-a5cc-4b6f6b05bddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799909512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
799909512
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/95.rv_timer_random.701858092
Short name T344
Test name
Test status
Simulation time 199670593862 ps
CPU time 548.21 seconds
Started Aug 14 04:50:15 PM PDT 24
Finished Aug 14 04:59:23 PM PDT 24
Peak memory 194252 kb
Host smart-4e48ba83-cbac-4e70-addf-302e5aeec0bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701858092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.701858092
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.1452334786
Short name T329
Test name
Test status
Simulation time 104977641688 ps
CPU time 149.22 seconds
Started Aug 14 04:49:23 PM PDT 24
Finished Aug 14 04:51:52 PM PDT 24
Peak memory 190796 kb
Host smart-35988b58-0ff7-43e1-a9e1-ff541eb90952
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452334786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1452334786
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1925208866
Short name T168
Test name
Test status
Simulation time 1295666855985 ps
CPU time 603.79 seconds
Started Aug 14 04:50:46 PM PDT 24
Finished Aug 14 05:00:50 PM PDT 24
Peak memory 191720 kb
Host smart-d753517b-6e6b-4a28-b872-b114cc0e8d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925208866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1925208866
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1368555956
Short name T222
Test name
Test status
Simulation time 162400361047 ps
CPU time 606.12 seconds
Started Aug 14 04:49:59 PM PDT 24
Finished Aug 14 05:00:05 PM PDT 24
Peak memory 191716 kb
Host smart-6575f06a-ea4b-453b-a9d0-5c744bce8954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368555956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1368555956
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2675647168
Short name T159
Test name
Test status
Simulation time 205757414059 ps
CPU time 183.47 seconds
Started Aug 14 04:50:18 PM PDT 24
Finished Aug 14 04:53:21 PM PDT 24
Peak memory 191792 kb
Host smart-661ce0ff-0b01-4f89-8bdb-5bfc89af9dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675647168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2675647168
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.1436007232
Short name T204
Test name
Test status
Simulation time 668579975358 ps
CPU time 377.78 seconds
Started Aug 14 04:48:59 PM PDT 24
Finished Aug 14 04:55:17 PM PDT 24
Peak memory 191744 kb
Host smart-3040a942-dab0-4e57-89f2-39a5b7fc7124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436007232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1436007232
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1761436217
Short name T56
Test name
Test status
Simulation time 2015949772663 ps
CPU time 1925.25 seconds
Started Aug 14 04:48:59 PM PDT 24
Finished Aug 14 05:21:05 PM PDT 24
Peak memory 191664 kb
Host smart-1033521d-b987-427b-bcdc-46e83e59c567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761436217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1761436217
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2557041771
Short name T178
Test name
Test status
Simulation time 1541104396254 ps
CPU time 2454.75 seconds
Started Aug 14 04:49:39 PM PDT 24
Finished Aug 14 05:30:34 PM PDT 24
Peak memory 195960 kb
Host smart-a5f6f5a5-f793-4db9-9bf9-2b38dcf47c55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557041771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2557041771
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.116810297
Short name T117
Test name
Test status
Simulation time 1400492606044 ps
CPU time 957.73 seconds
Started Aug 14 04:49:57 PM PDT 24
Finished Aug 14 05:05:55 PM PDT 24
Peak memory 191780 kb
Host smart-2998e7b5-3c99-4cf0-8775-8bfa28ef5dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116810297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.116810297
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3710883233
Short name T65
Test name
Test status
Simulation time 12295447 ps
CPU time 0.57 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 183328 kb
Host smart-be0bfb77-ff7f-4bf1-b9fc-83fd560c5bde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710883233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3710883233
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/117.rv_timer_random.2742834878
Short name T296
Test name
Test status
Simulation time 183832760529 ps
CPU time 348.42 seconds
Started Aug 14 04:50:31 PM PDT 24
Finished Aug 14 04:56:20 PM PDT 24
Peak memory 192948 kb
Host smart-4fb95450-831d-4dd2-8d72-c6c83757e695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742834878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2742834878
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2018189556
Short name T305
Test name
Test status
Simulation time 141470065344 ps
CPU time 231.98 seconds
Started Aug 14 04:50:28 PM PDT 24
Finished Aug 14 04:54:20 PM PDT 24
Peak memory 191892 kb
Host smart-0cd431be-3237-4eb9-b364-65e86a5e43b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018189556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2018189556
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.367536906
Short name T208
Test name
Test status
Simulation time 617109067662 ps
CPU time 619.38 seconds
Started Aug 14 04:50:33 PM PDT 24
Finished Aug 14 05:00:52 PM PDT 24
Peak memory 191836 kb
Host smart-417a67b9-0a08-455e-acd6-74cea23ea1ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367536906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.367536906
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.3027194163
Short name T122
Test name
Test status
Simulation time 634297297593 ps
CPU time 690.22 seconds
Started Aug 14 04:48:51 PM PDT 24
Finished Aug 14 05:00:22 PM PDT 24
Peak memory 191676 kb
Host smart-7880fbd7-894c-4a63-bc7a-26cc329936fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027194163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3027194163
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1038924843
Short name T233
Test name
Test status
Simulation time 2333863237204 ps
CPU time 1122.24 seconds
Started Aug 14 04:48:51 PM PDT 24
Finished Aug 14 05:07:34 PM PDT 24
Peak memory 194928 kb
Host smart-27e3f611-caef-4c23-838a-0c6f7c999505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038924843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1038924843
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.3457276734
Short name T220
Test name
Test status
Simulation time 82852894920 ps
CPU time 187 seconds
Started Aug 14 04:50:58 PM PDT 24
Finished Aug 14 04:54:05 PM PDT 24
Peak memory 191792 kb
Host smart-f5b524f4-0c49-4d26-ae16-fd28f8459b85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457276734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3457276734
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3277080631
Short name T271
Test name
Test status
Simulation time 198706654444 ps
CPU time 1185.65 seconds
Started Aug 14 04:50:59 PM PDT 24
Finished Aug 14 05:10:45 PM PDT 24
Peak memory 195396 kb
Host smart-b440581f-32f5-4f6f-a73d-16dbd3010e7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277080631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3277080631
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.946281918
Short name T148
Test name
Test status
Simulation time 164492903876 ps
CPU time 487.51 seconds
Started Aug 14 04:49:03 PM PDT 24
Finished Aug 14 04:57:11 PM PDT 24
Peak memory 191740 kb
Host smart-76b1ca49-1316-4fdf-b2de-dec3f1f924c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946281918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
946281918
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_random.2314436310
Short name T189
Test name
Test status
Simulation time 117207290335 ps
CPU time 209.16 seconds
Started Aug 14 04:49:14 PM PDT 24
Finished Aug 14 04:52:43 PM PDT 24
Peak memory 191788 kb
Host smart-e03bd2e2-934b-4f6f-8e9f-6b4152f70ad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314436310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2314436310
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random.3496300443
Short name T351
Test name
Test status
Simulation time 95232284925 ps
CPU time 199.72 seconds
Started Aug 14 04:49:25 PM PDT 24
Finished Aug 14 04:52:45 PM PDT 24
Peak memory 191800 kb
Host smart-ccddc90a-3fb3-45fc-a02b-f2c6e4238688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496300443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3496300443
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2426823599
Short name T31
Test name
Test status
Simulation time 275717013 ps
CPU time 1.04 seconds
Started Aug 14 04:45:26 PM PDT 24
Finished Aug 14 04:45:27 PM PDT 24
Peak memory 183768 kb
Host smart-dcd3db02-0f27-4d2d-a694-3149d7cb7c77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426823599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2426823599
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/129.rv_timer_random.4226365917
Short name T246
Test name
Test status
Simulation time 102674898771 ps
CPU time 169.43 seconds
Started Aug 14 04:50:26 PM PDT 24
Finished Aug 14 04:53:15 PM PDT 24
Peak memory 191824 kb
Host smart-33cce232-d4d0-4cf0-98dd-1e8bfb1f7751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226365917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4226365917
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3461394833
Short name T182
Test name
Test status
Simulation time 1713080856900 ps
CPU time 469.84 seconds
Started Aug 14 04:50:42 PM PDT 24
Finished Aug 14 04:58:32 PM PDT 24
Peak memory 191824 kb
Host smart-cd2a3ae8-7214-40bf-8714-8d04c4a774c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461394833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3461394833
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1789595968
Short name T240
Test name
Test status
Simulation time 1725009072821 ps
CPU time 394.39 seconds
Started Aug 14 04:51:08 PM PDT 24
Finished Aug 14 04:57:43 PM PDT 24
Peak memory 191792 kb
Host smart-16585fbd-712f-4ce5-8bec-a267c7cf62c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789595968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1789595968
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3492787177
Short name T93
Test name
Test status
Simulation time 142836342105 ps
CPU time 472.91 seconds
Started Aug 14 04:51:11 PM PDT 24
Finished Aug 14 04:59:04 PM PDT 24
Peak memory 191716 kb
Host smart-bafbb1b0-f500-46ba-8573-8180494ad0fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492787177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3492787177
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3604964285
Short name T217
Test name
Test status
Simulation time 299957847090 ps
CPU time 477.5 seconds
Started Aug 14 04:49:01 PM PDT 24
Finished Aug 14 04:56:59 PM PDT 24
Peak memory 183588 kb
Host smart-862d7e2b-b4db-4828-9cd5-48fbe7f08e1a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604964285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3604964285
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.542124383
Short name T211
Test name
Test status
Simulation time 665920680768 ps
CPU time 1009.63 seconds
Started Aug 14 04:49:15 PM PDT 24
Finished Aug 14 05:06:05 PM PDT 24
Peak memory 191580 kb
Host smart-b7d89db2-8c52-4e5e-bea8-eb0e73c098bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542124383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
542124383
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1922149037
Short name T292
Test name
Test status
Simulation time 2607009930288 ps
CPU time 1452.67 seconds
Started Aug 14 04:49:38 PM PDT 24
Finished Aug 14 05:13:51 PM PDT 24
Peak memory 191700 kb
Host smart-64951c5b-89ee-447f-9e9f-a851b1a6fd25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922149037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1922149037
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_random.4293370013
Short name T291
Test name
Test status
Simulation time 311444733780 ps
CPU time 224.64 seconds
Started Aug 14 04:48:41 PM PDT 24
Finished Aug 14 04:52:26 PM PDT 24
Peak memory 191756 kb
Host smart-71993bc2-aa3e-4af3-bbf3-219c2f63d9b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293370013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.4293370013
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.144300848
Short name T362
Test name
Test status
Simulation time 150048705064 ps
CPU time 291.56 seconds
Started Aug 14 04:49:58 PM PDT 24
Finished Aug 14 04:54:49 PM PDT 24
Peak memory 191820 kb
Host smart-16538317-e3ef-4fba-850a-dc6509da7022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144300848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.144300848
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2382058761
Short name T252
Test name
Test status
Simulation time 513807593092 ps
CPU time 533.59 seconds
Started Aug 14 04:50:24 PM PDT 24
Finished Aug 14 04:59:18 PM PDT 24
Peak memory 191780 kb
Host smart-c03ac3f0-201b-4ccf-989a-2e4f8623d2ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382058761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2382058761
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3735684797
Short name T254
Test name
Test status
Simulation time 115207437738 ps
CPU time 459.21 seconds
Started Aug 14 04:50:25 PM PDT 24
Finished Aug 14 04:58:04 PM PDT 24
Peak memory 191832 kb
Host smart-e59fab3b-428c-467d-a228-1d23ac75e102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735684797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3735684797
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.620083964
Short name T137
Test name
Test status
Simulation time 458469881144 ps
CPU time 1396.6 seconds
Started Aug 14 04:49:00 PM PDT 24
Finished Aug 14 05:12:17 PM PDT 24
Peak memory 195972 kb
Host smart-91cbe7ba-53fb-42c1-ae27-3eb9812c1f1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620083964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
620083964
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_random.1857198103
Short name T236
Test name
Test status
Simulation time 793376052673 ps
CPU time 697.49 seconds
Started Aug 14 04:49:12 PM PDT 24
Finished Aug 14 05:00:50 PM PDT 24
Peak memory 191808 kb
Host smart-6ca3b492-23e5-49a5-abc2-287cb28e9dd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857198103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1857198103
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3608706008
Short name T125
Test name
Test status
Simulation time 825749713217 ps
CPU time 810.43 seconds
Started Aug 14 04:49:22 PM PDT 24
Finished Aug 14 05:02:53 PM PDT 24
Peak memory 183536 kb
Host smart-27367192-5fe3-4deb-8861-d885d3817f00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608706008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3608706008
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_random.3541786044
Short name T274
Test name
Test status
Simulation time 188098361936 ps
CPU time 1230.02 seconds
Started Aug 14 04:48:30 PM PDT 24
Finished Aug 14 05:09:00 PM PDT 24
Peak memory 191804 kb
Host smart-dc7dc04b-44a7-4f4d-8657-26ee4c65f5f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541786044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3541786044
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2926251980
Short name T298
Test name
Test status
Simulation time 276847517532 ps
CPU time 482.52 seconds
Started Aug 14 04:49:58 PM PDT 24
Finished Aug 14 04:58:01 PM PDT 24
Peak memory 191624 kb
Host smart-16534cf7-bf71-42a0-9834-988187cc27bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926251980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2926251980
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3783081690
Short name T238
Test name
Test status
Simulation time 104410835021 ps
CPU time 657.75 seconds
Started Aug 14 04:49:57 PM PDT 24
Finished Aug 14 05:00:55 PM PDT 24
Peak memory 191776 kb
Host smart-d2ca98be-b4c6-4de9-9c40-9ea5159e8f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783081690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3783081690
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.4071471186
Short name T224
Test name
Test status
Simulation time 425671712040 ps
CPU time 268.72 seconds
Started Aug 14 04:50:17 PM PDT 24
Finished Aug 14 04:54:46 PM PDT 24
Peak memory 191820 kb
Host smart-a9073efc-2c3c-4501-95c4-3a7cb0e67565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071471186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.4071471186
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.4026658967
Short name T268
Test name
Test status
Simulation time 145258233572 ps
CPU time 665.5 seconds
Started Aug 14 04:50:16 PM PDT 24
Finished Aug 14 05:01:22 PM PDT 24
Peak memory 191612 kb
Host smart-5ebeea09-6ccc-4f1e-a94e-d936b34c7761
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026658967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.4026658967
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.802722816
Short name T205
Test name
Test status
Simulation time 664312050217 ps
CPU time 298.99 seconds
Started Aug 14 04:50:35 PM PDT 24
Finished Aug 14 04:55:34 PM PDT 24
Peak memory 193768 kb
Host smart-29851c22-b76f-4480-9366-721ec230e219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802722816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.802722816
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3555889150
Short name T452
Test name
Test status
Simulation time 143762013656 ps
CPU time 3519.53 seconds
Started Aug 14 04:50:43 PM PDT 24
Finished Aug 14 05:49:23 PM PDT 24
Peak memory 191820 kb
Host smart-1bee1d67-5a6d-40c3-ad30-7c47c0b4d417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555889150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3555889150
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3024313404
Short name T187
Test name
Test status
Simulation time 239347704921 ps
CPU time 289.28 seconds
Started Aug 14 04:50:58 PM PDT 24
Finished Aug 14 04:55:48 PM PDT 24
Peak memory 191928 kb
Host smart-2c15413a-8940-4d0e-a270-4ed5229e1120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024313404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3024313404
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3231526708
Short name T165
Test name
Test status
Simulation time 3001005618245 ps
CPU time 1016.96 seconds
Started Aug 14 04:51:12 PM PDT 24
Finished Aug 14 05:08:09 PM PDT 24
Peak memory 191836 kb
Host smart-b8ba13db-ceab-4c56-819b-2f2ecc0df7be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231526708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3231526708
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.528089882
Short name T102
Test name
Test status
Simulation time 998417997701 ps
CPU time 2066.7 seconds
Started Aug 14 04:49:11 PM PDT 24
Finished Aug 14 05:23:38 PM PDT 24
Peak memory 191720 kb
Host smart-51514779-34c0-4ec8-ad7b-97a6714b743d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528089882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
528089882
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2285134048
Short name T227
Test name
Test status
Simulation time 43235544372 ps
CPU time 411.9 seconds
Started Aug 14 04:49:13 PM PDT 24
Finished Aug 14 04:56:05 PM PDT 24
Peak memory 194668 kb
Host smart-99323f41-c23c-48c5-bbb2-582fba931450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285134048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2285134048
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.771272060
Short name T166
Test name
Test status
Simulation time 293544769536 ps
CPU time 486.45 seconds
Started Aug 14 04:48:30 PM PDT 24
Finished Aug 14 04:56:36 PM PDT 24
Peak memory 191928 kb
Host smart-288fc1bc-a3e9-41ec-a4da-64ac06a2280e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771272060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.771272060
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2666009913
Short name T185
Test name
Test status
Simulation time 420395562425 ps
CPU time 900.48 seconds
Started Aug 14 04:49:25 PM PDT 24
Finished Aug 14 05:04:25 PM PDT 24
Peak memory 183584 kb
Host smart-a2bddc31-b86d-45c5-8b40-5ae29120a012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666009913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2666009913
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_random.3473766816
Short name T105
Test name
Test status
Simulation time 225227000095 ps
CPU time 430.58 seconds
Started Aug 14 04:49:25 PM PDT 24
Finished Aug 14 04:56:35 PM PDT 24
Peak memory 191800 kb
Host smart-e6273857-6804-4114-9021-a32669522c92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473766816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3473766816
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/50.rv_timer_random.727797028
Short name T176
Test name
Test status
Simulation time 94225889620 ps
CPU time 1148.03 seconds
Started Aug 14 04:49:47 PM PDT 24
Finished Aug 14 05:08:56 PM PDT 24
Peak memory 191812 kb
Host smart-3cfab103-9e5a-4ca3-bcc0-83eed79569c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727797028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.727797028
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1129938493
Short name T266
Test name
Test status
Simulation time 35338318421 ps
CPU time 54.26 seconds
Started Aug 14 04:50:06 PM PDT 24
Finished Aug 14 04:51:01 PM PDT 24
Peak memory 191732 kb
Host smart-b3edf274-1b37-474f-8bd3-8f2e1a91259c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129938493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1129938493
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.956202314
Short name T153
Test name
Test status
Simulation time 180121438003 ps
CPU time 803.59 seconds
Started Aug 14 04:48:23 PM PDT 24
Finished Aug 14 05:01:47 PM PDT 24
Peak memory 191812 kb
Host smart-b2d64002-ce38-47c2-bbc8-494831d1c614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956202314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.956202314
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.1881499482
Short name T175
Test name
Test status
Simulation time 288096429937 ps
CPU time 366.12 seconds
Started Aug 14 04:48:31 PM PDT 24
Finished Aug 14 04:54:38 PM PDT 24
Peak memory 191756 kb
Host smart-e3691767-aaaa-433e-bd9c-da7ee534d60d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881499482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1881499482
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1738213297
Short name T235
Test name
Test status
Simulation time 40138956362 ps
CPU time 55.18 seconds
Started Aug 14 04:48:41 PM PDT 24
Finished Aug 14 04:49:36 PM PDT 24
Peak memory 193792 kb
Host smart-7e6afb98-78ed-4dc1-ba05-c9465a1f9408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738213297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1738213297
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/107.rv_timer_random.3643217226
Short name T197
Test name
Test status
Simulation time 100855172160 ps
CPU time 180.19 seconds
Started Aug 14 04:50:15 PM PDT 24
Finished Aug 14 04:53:16 PM PDT 24
Peak memory 191788 kb
Host smart-8f039194-e88a-43bd-a9f7-072eb515d251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643217226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3643217226
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.964916024
Short name T230
Test name
Test status
Simulation time 214767197131 ps
CPU time 196.44 seconds
Started Aug 14 04:50:16 PM PDT 24
Finished Aug 14 04:53:32 PM PDT 24
Peak memory 191800 kb
Host smart-bb99957e-b8ae-4d91-adf0-93e8c880c30d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964916024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.964916024
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1752532426
Short name T126
Test name
Test status
Simulation time 242300301662 ps
CPU time 383.43 seconds
Started Aug 14 04:48:42 PM PDT 24
Finished Aug 14 04:55:06 PM PDT 24
Peak memory 183564 kb
Host smart-29bfcc66-dfa0-44b0-ace9-eb6b3182dfc4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752532426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1752532426
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/110.rv_timer_random.1667778427
Short name T90
Test name
Test status
Simulation time 624203179690 ps
CPU time 400.24 seconds
Started Aug 14 04:50:17 PM PDT 24
Finished Aug 14 04:56:57 PM PDT 24
Peak memory 191792 kb
Host smart-a69f2036-498d-42fd-af32-ca33686008ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667778427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1667778427
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1862650981
Short name T237
Test name
Test status
Simulation time 48002771133 ps
CPU time 80.01 seconds
Started Aug 14 04:50:25 PM PDT 24
Finished Aug 14 04:51:45 PM PDT 24
Peak memory 191736 kb
Host smart-25528bb3-adea-4dea-a7c6-492bdc4d8c09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862650981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1862650981
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3131812871
Short name T260
Test name
Test status
Simulation time 537149345272 ps
CPU time 813.02 seconds
Started Aug 14 04:50:24 PM PDT 24
Finished Aug 14 05:03:57 PM PDT 24
Peak memory 191812 kb
Host smart-61901e28-46ee-4dec-8335-5155ed870ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131812871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3131812871
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3901141887
Short name T284
Test name
Test status
Simulation time 758297657816 ps
CPU time 402.43 seconds
Started Aug 14 04:48:56 PM PDT 24
Finished Aug 14 04:55:38 PM PDT 24
Peak memory 183500 kb
Host smart-c541ab80-7d9e-44ae-a9a7-a674c0d23eac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901141887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3901141887
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3283714926
Short name T241
Test name
Test status
Simulation time 706596187096 ps
CPU time 1010.24 seconds
Started Aug 14 04:48:57 PM PDT 24
Finished Aug 14 05:05:47 PM PDT 24
Peak memory 196564 kb
Host smart-3587c065-fb48-4310-b6c5-91d236340396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283714926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3283714926
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.3755404070
Short name T167
Test name
Test status
Simulation time 23782813727 ps
CPU time 42.99 seconds
Started Aug 14 04:50:27 PM PDT 24
Finished Aug 14 04:51:11 PM PDT 24
Peak memory 183692 kb
Host smart-67fd8eb7-92b9-494b-8b35-77dfefdb0543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755404070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3755404070
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3747410137
Short name T325
Test name
Test status
Simulation time 124014732516 ps
CPU time 101.15 seconds
Started Aug 14 04:50:35 PM PDT 24
Finished Aug 14 04:52:16 PM PDT 24
Peak memory 191788 kb
Host smart-e4c6e1ed-501c-45b5-adbe-7b6757e4b434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747410137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3747410137
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.292816290
Short name T100
Test name
Test status
Simulation time 112867000300 ps
CPU time 179.4 seconds
Started Aug 14 04:50:33 PM PDT 24
Finished Aug 14 04:53:32 PM PDT 24
Peak memory 191708 kb
Host smart-293e8f46-4c9f-476c-bedf-13a06e8efa5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292816290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.292816290
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1552081108
Short name T186
Test name
Test status
Simulation time 122901358734 ps
CPU time 201.83 seconds
Started Aug 14 04:48:57 PM PDT 24
Finished Aug 14 04:52:19 PM PDT 24
Peak memory 191748 kb
Host smart-3a929eb0-1853-4aaa-bfec-1151465bfb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552081108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1552081108
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/178.rv_timer_random.4110540326
Short name T343
Test name
Test status
Simulation time 45275760815 ps
CPU time 128.93 seconds
Started Aug 14 04:51:00 PM PDT 24
Finished Aug 14 04:53:09 PM PDT 24
Peak memory 191676 kb
Host smart-45063e31-36f6-49ab-b5b6-18d626406583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110540326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.4110540326
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2038207603
Short name T273
Test name
Test status
Simulation time 57129347579 ps
CPU time 49.09 seconds
Started Aug 14 04:48:50 PM PDT 24
Finished Aug 14 04:49:39 PM PDT 24
Peak memory 183584 kb
Host smart-81e07b9c-f94a-4107-9f80-74cf662dfb0d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038207603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2038207603
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1068224688
Short name T129
Test name
Test status
Simulation time 74285311723 ps
CPU time 76.66 seconds
Started Aug 14 04:48:51 PM PDT 24
Finished Aug 14 04:50:08 PM PDT 24
Peak memory 183584 kb
Host smart-84c146e3-c5ca-4b1b-8e65-7cab1550ea5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068224688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1068224688
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/192.rv_timer_random.2745074625
Short name T332
Test name
Test status
Simulation time 120737631622 ps
CPU time 81.18 seconds
Started Aug 14 04:51:13 PM PDT 24
Finished Aug 14 04:52:34 PM PDT 24
Peak memory 195724 kb
Host smart-2aa02c43-6b0a-4a86-aa15-ba3190f847da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745074625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2745074625
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1087120432
Short name T262
Test name
Test status
Simulation time 111513771078 ps
CPU time 213.97 seconds
Started Aug 14 04:51:11 PM PDT 24
Finished Aug 14 04:54:45 PM PDT 24
Peak memory 191704 kb
Host smart-04b62632-6907-41c2-b25e-622bfb5828da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087120432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1087120432
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2586447109
Short name T309
Test name
Test status
Simulation time 150159793394 ps
CPU time 60.59 seconds
Started Aug 14 04:48:32 PM PDT 24
Finished Aug 14 04:49:33 PM PDT 24
Peak memory 191512 kb
Host smart-dc8742e9-c8fa-4dd3-af8d-9db71b4d6252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586447109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2586447109
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2739809509
Short name T352
Test name
Test status
Simulation time 237056943324 ps
CPU time 130.98 seconds
Started Aug 14 04:49:11 PM PDT 24
Finished Aug 14 04:51:22 PM PDT 24
Peak memory 191720 kb
Host smart-b8c2d359-6a34-4f8e-bed9-54776a60c2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739809509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2739809509
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.4186079714
Short name T158
Test name
Test status
Simulation time 398318517643 ps
CPU time 580.82 seconds
Started Aug 14 04:49:26 PM PDT 24
Finished Aug 14 04:59:07 PM PDT 24
Peak memory 191704 kb
Host smart-c041fb0c-8602-441b-a66e-111f6da0a54a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186079714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.4186079714
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_random.1317567600
Short name T180
Test name
Test status
Simulation time 114024507683 ps
CPU time 193.11 seconds
Started Aug 14 04:49:27 PM PDT 24
Finished Aug 14 04:52:40 PM PDT 24
Peak memory 191832 kb
Host smart-2ebd4464-c55b-4325-9d08-36289b0975aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317567600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1317567600
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random.126369744
Short name T149
Test name
Test status
Simulation time 325439604774 ps
CPU time 1430.21 seconds
Started Aug 14 04:48:37 PM PDT 24
Finished Aug 14 05:12:28 PM PDT 24
Peak memory 191716 kb
Host smart-051e7be6-6059-4176-bc95-8d3907a1b970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126369744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.126369744
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.4030000687
Short name T229
Test name
Test status
Simulation time 1591048814240 ps
CPU time 828.67 seconds
Started Aug 14 04:49:34 PM PDT 24
Finished Aug 14 05:03:23 PM PDT 24
Peak memory 183624 kb
Host smart-f481f33b-735e-411c-b8be-c7920fd9a0c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030000687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.4030000687
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.554537437
Short name T110
Test name
Test status
Simulation time 5623072883918 ps
CPU time 1023.63 seconds
Started Aug 14 04:49:32 PM PDT 24
Finished Aug 14 05:06:36 PM PDT 24
Peak memory 191792 kb
Host smart-bf16d621-25e4-4402-9ea2-0bfbf82212e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554537437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
554537437
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.566266448
Short name T250
Test name
Test status
Simulation time 119576545621 ps
CPU time 215.33 seconds
Started Aug 14 04:49:38 PM PDT 24
Finished Aug 14 04:53:14 PM PDT 24
Peak memory 183464 kb
Host smart-be2dc4e7-3745-4aff-96ba-e5f694161a4d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566266448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.566266448
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/54.rv_timer_random.1837689411
Short name T164
Test name
Test status
Simulation time 162961891053 ps
CPU time 135.65 seconds
Started Aug 14 04:49:48 PM PDT 24
Finished Aug 14 04:52:04 PM PDT 24
Peak memory 191812 kb
Host smart-79750824-2543-4b15-acf8-a4e6784ca5d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837689411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1837689411
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3615264888
Short name T231
Test name
Test status
Simulation time 79029893825 ps
CPU time 589.33 seconds
Started Aug 14 04:49:56 PM PDT 24
Finished Aug 14 04:59:45 PM PDT 24
Peak memory 191820 kb
Host smart-e0a44fa1-cd81-4f41-87f1-5f8497ad774b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615264888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3615264888
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3318904798
Short name T64
Test name
Test status
Simulation time 84396364 ps
CPU time 0.62 seconds
Started Aug 14 04:45:44 PM PDT 24
Finished Aug 14 04:45:45 PM PDT 24
Peak memory 192620 kb
Host smart-61dd0f0f-424c-4550-afa8-b4d4a9668d24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318904798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3318904798
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1772864893
Short name T482
Test name
Test status
Simulation time 68426868 ps
CPU time 1.39 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 191784 kb
Host smart-65730931-3cb2-45ee-9147-5b03556a4e18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772864893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1772864893
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.840166017
Short name T544
Test name
Test status
Simulation time 42528645 ps
CPU time 0.55 seconds
Started Aug 14 04:45:13 PM PDT 24
Finished Aug 14 04:45:14 PM PDT 24
Peak memory 183332 kb
Host smart-6d718b30-874a-4a1a-94f7-ec928f5e7691
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840166017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.840166017
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1129254715
Short name T526
Test name
Test status
Simulation time 59646079 ps
CPU time 1.06 seconds
Started Aug 14 04:45:17 PM PDT 24
Finished Aug 14 04:45:19 PM PDT 24
Peak memory 198164 kb
Host smart-a999814a-f448-4eb6-aa44-95255f9b32d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129254715 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1129254715
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3242599322
Short name T74
Test name
Test status
Simulation time 30503342 ps
CPU time 0.58 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:12 PM PDT 24
Peak memory 183336 kb
Host smart-4a5993cf-598b-405c-8b09-4bdacc779b85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242599322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3242599322
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2273306011
Short name T507
Test name
Test status
Simulation time 14015738 ps
CPU time 0.61 seconds
Started Aug 14 04:45:25 PM PDT 24
Finished Aug 14 04:45:25 PM PDT 24
Peak memory 183176 kb
Host smart-6f88eab9-2cae-4afd-8acc-62f0bfc788c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273306011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2273306011
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1774247812
Short name T527
Test name
Test status
Simulation time 40339356 ps
CPU time 0.61 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 192520 kb
Host smart-5862cd36-32a5-40c2-9df3-6df6e988a8f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774247812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1774247812
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2875243597
Short name T460
Test name
Test status
Simulation time 36691304 ps
CPU time 1.02 seconds
Started Aug 14 04:45:13 PM PDT 24
Finished Aug 14 04:45:14 PM PDT 24
Peak memory 197824 kb
Host smart-f120de0c-7213-4e26-b4fe-6c690474c0e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875243597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2875243597
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4260835389
Short name T86
Test name
Test status
Simulation time 694380482 ps
CPU time 0.87 seconds
Started Aug 14 04:45:14 PM PDT 24
Finished Aug 14 04:45:15 PM PDT 24
Peak memory 194432 kb
Host smart-1aa80094-93ea-4653-a257-33de22db0d56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260835389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.4260835389
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.952037508
Short name T77
Test name
Test status
Simulation time 25291011 ps
CPU time 0.7 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 183392 kb
Host smart-76fc603c-bfcc-41e2-ac48-83b9b9898fc7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952037508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.952037508
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1672007494
Short name T62
Test name
Test status
Simulation time 18198561 ps
CPU time 0.58 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:12 PM PDT 24
Peak memory 183412 kb
Host smart-99d09615-aef7-4931-ab35-76d5ece7add8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672007494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1672007494
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3798214951
Short name T476
Test name
Test status
Simulation time 82362957 ps
CPU time 1.08 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 198020 kb
Host smart-c5731bbe-9cdd-4846-bcaa-4dd9d92b0b45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798214951 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3798214951
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1246972536
Short name T505
Test name
Test status
Simulation time 34385985 ps
CPU time 0.56 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 183408 kb
Host smart-73de2180-748e-47d8-bc34-de301c5f73e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246972536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1246972536
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3082237400
Short name T496
Test name
Test status
Simulation time 17494169 ps
CPU time 0.57 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 182936 kb
Host smart-20dbfa32-eb79-482b-9a92-c0af437c4f89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082237400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3082237400
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.146984975
Short name T32
Test name
Test status
Simulation time 18682900 ps
CPU time 0.65 seconds
Started Aug 14 04:45:31 PM PDT 24
Finished Aug 14 04:45:32 PM PDT 24
Peak memory 192516 kb
Host smart-54b43143-5564-4723-b7cb-7a1646cd1234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146984975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.146984975
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2836481135
Short name T474
Test name
Test status
Simulation time 144654114 ps
CPU time 2.11 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 198080 kb
Host smart-22fefcae-63e8-42e4-b1da-31d5260454c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836481135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2836481135
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3880949195
Short name T503
Test name
Test status
Simulation time 127040272 ps
CPU time 1.04 seconds
Started Aug 14 04:45:14 PM PDT 24
Finished Aug 14 04:45:15 PM PDT 24
Peak memory 195676 kb
Host smart-005a9f6a-3e39-4cdf-9d0a-fa9994154d11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880949195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3880949195
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.4224375350
Short name T564
Test name
Test status
Simulation time 18531237 ps
CPU time 0.65 seconds
Started Aug 14 04:45:33 PM PDT 24
Finished Aug 14 04:45:34 PM PDT 24
Peak memory 194236 kb
Host smart-95a7c53e-d6af-4715-a9a7-cdf1316ceba7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224375350 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.4224375350
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2435346927
Short name T566
Test name
Test status
Simulation time 74809454 ps
CPU time 0.52 seconds
Started Aug 14 04:45:16 PM PDT 24
Finished Aug 14 04:45:16 PM PDT 24
Peak memory 183220 kb
Host smart-bdad6cc5-d70e-4583-bbc0-05b30f379309
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435346927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2435346927
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3453078016
Short name T515
Test name
Test status
Simulation time 12006714 ps
CPU time 0.58 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 183372 kb
Host smart-280682d4-8f19-4070-b321-740de09a2b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453078016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3453078016
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4084202924
Short name T555
Test name
Test status
Simulation time 34271536 ps
CPU time 0.61 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 191968 kb
Host smart-2b305203-b050-41ca-9d27-4fc6f7447668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084202924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4084202924
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.357215414
Short name T469
Test name
Test status
Simulation time 141558245 ps
CPU time 2.02 seconds
Started Aug 14 04:45:33 PM PDT 24
Finished Aug 14 04:45:35 PM PDT 24
Peak memory 198112 kb
Host smart-4c3d0b6e-1839-404f-b801-bf9111a01407
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357215414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.357215414
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1588728712
Short name T50
Test name
Test status
Simulation time 48239353 ps
CPU time 0.79 seconds
Started Aug 14 04:45:09 PM PDT 24
Finished Aug 14 04:45:10 PM PDT 24
Peak memory 194100 kb
Host smart-4e51dc5f-a9a4-4d79-aad4-8f20558cd30b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588728712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1588728712
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1248866382
Short name T571
Test name
Test status
Simulation time 36283743 ps
CPU time 1.09 seconds
Started Aug 14 04:45:23 PM PDT 24
Finished Aug 14 04:45:24 PM PDT 24
Peak memory 197904 kb
Host smart-77602849-ed81-45a3-bb76-446a1211fe73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248866382 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1248866382
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1352040476
Short name T68
Test name
Test status
Simulation time 30253314 ps
CPU time 0.51 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 183408 kb
Host smart-c20d1b68-3b52-4e3c-a76c-db40d2e8baa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352040476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1352040476
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.715078414
Short name T461
Test name
Test status
Simulation time 88036114 ps
CPU time 0.54 seconds
Started Aug 14 04:45:22 PM PDT 24
Finished Aug 14 04:45:22 PM PDT 24
Peak memory 183244 kb
Host smart-cc53b485-7412-481a-a46a-2c88589d95b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715078414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.715078414
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3713407298
Short name T82
Test name
Test status
Simulation time 124306274 ps
CPU time 0.68 seconds
Started Aug 14 04:45:41 PM PDT 24
Finished Aug 14 04:45:41 PM PDT 24
Peak memory 192304 kb
Host smart-338942b5-b14c-465f-b343-51a03880036c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713407298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3713407298
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2563468834
Short name T52
Test name
Test status
Simulation time 254042929 ps
CPU time 1.73 seconds
Started Aug 14 04:45:32 PM PDT 24
Finished Aug 14 04:45:34 PM PDT 24
Peak memory 198064 kb
Host smart-ec4848f4-ddef-465c-8749-c01b01a5105f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563468834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2563468834
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2549177047
Short name T584
Test name
Test status
Simulation time 108593021 ps
CPU time 0.81 seconds
Started Aug 14 04:45:08 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 183820 kb
Host smart-4290286d-953e-45e8-99b3-9aa143eba35f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549177047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2549177047
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.937540201
Short name T502
Test name
Test status
Simulation time 66202834 ps
CPU time 0.76 seconds
Started Aug 14 04:45:43 PM PDT 24
Finished Aug 14 04:45:44 PM PDT 24
Peak memory 195656 kb
Host smart-7a29c9c8-01e6-497d-b099-f47e76d16015
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937540201 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.937540201
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2276002459
Short name T76
Test name
Test status
Simulation time 51229996 ps
CPU time 0.64 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 183296 kb
Host smart-e3da2db6-71eb-47aa-b83c-317768345874
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276002459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2276002459
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3654675601
Short name T491
Test name
Test status
Simulation time 13893009 ps
CPU time 0.61 seconds
Started Aug 14 04:45:17 PM PDT 24
Finished Aug 14 04:45:18 PM PDT 24
Peak memory 183260 kb
Host smart-c2292284-b8a3-431e-9806-42abb5ab433a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654675601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3654675601
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3960013595
Short name T579
Test name
Test status
Simulation time 100741192 ps
CPU time 0.72 seconds
Started Aug 14 04:45:13 PM PDT 24
Finished Aug 14 04:45:14 PM PDT 24
Peak memory 193860 kb
Host smart-b196eb3d-83b4-4b44-8d4f-831aa205342c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960013595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3960013595
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.414708084
Short name T568
Test name
Test status
Simulation time 200493793 ps
CPU time 1.1 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 197980 kb
Host smart-b5e1a8f1-4558-4d0d-b058-5f5972e4c809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414708084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.414708084
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2597611998
Short name T30
Test name
Test status
Simulation time 177376145 ps
CPU time 1.39 seconds
Started Aug 14 04:45:16 PM PDT 24
Finished Aug 14 04:45:28 PM PDT 24
Peak memory 195760 kb
Host smart-a678b1aa-adea-4269-afbc-e63545161e72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597611998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2597611998
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2175061394
Short name T524
Test name
Test status
Simulation time 79397402 ps
CPU time 0.98 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 197932 kb
Host smart-c83d36db-39c5-4a0a-b9f2-e55ae25b0469
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175061394 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2175061394
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3497177152
Short name T79
Test name
Test status
Simulation time 14367129 ps
CPU time 0.57 seconds
Started Aug 14 04:45:26 PM PDT 24
Finished Aug 14 04:45:26 PM PDT 24
Peak memory 183280 kb
Host smart-4c6730e5-88b6-4ccb-a859-3835622ebfbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497177152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3497177152
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.777278941
Short name T481
Test name
Test status
Simulation time 128132508 ps
CPU time 0.57 seconds
Started Aug 14 04:45:21 PM PDT 24
Finished Aug 14 04:45:22 PM PDT 24
Peak memory 183192 kb
Host smart-cfe05227-394c-443c-a074-d8d2911155aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777278941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.777278941
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2115824731
Short name T567
Test name
Test status
Simulation time 77968965 ps
CPU time 0.6 seconds
Started Aug 14 04:45:22 PM PDT 24
Finished Aug 14 04:45:23 PM PDT 24
Peak memory 192612 kb
Host smart-9f1fe381-e747-4af4-9d96-097956f93fb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115824731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2115824731
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.4291490374
Short name T477
Test name
Test status
Simulation time 197273935 ps
CPU time 1.74 seconds
Started Aug 14 04:45:46 PM PDT 24
Finished Aug 14 04:45:53 PM PDT 24
Peak memory 198052 kb
Host smart-5b18876a-e4f3-4db6-a270-969c2cf7daa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291490374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.4291490374
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1866225459
Short name T499
Test name
Test status
Simulation time 130522072 ps
CPU time 0.81 seconds
Started Aug 14 04:45:29 PM PDT 24
Finished Aug 14 04:45:30 PM PDT 24
Peak memory 194156 kb
Host smart-5b5e6723-28f6-4972-af8c-ec333dc0860a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866225459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1866225459
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4251794631
Short name T509
Test name
Test status
Simulation time 18496350 ps
CPU time 0.64 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 194400 kb
Host smart-b09cdb72-c1ec-4775-9624-d3f95395f4d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251794631 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4251794631
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3366080828
Short name T487
Test name
Test status
Simulation time 44584287 ps
CPU time 0.53 seconds
Started Aug 14 04:45:20 PM PDT 24
Finished Aug 14 04:45:20 PM PDT 24
Peak memory 183388 kb
Host smart-6a993927-6545-4e67-8a3a-e8c40d25c3d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366080828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3366080828
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.343042276
Short name T466
Test name
Test status
Simulation time 56143086 ps
CPU time 0.55 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 183312 kb
Host smart-30bee5d4-b34b-4995-9169-c40b4a84bcb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343042276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.343042276
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1060117302
Short name T553
Test name
Test status
Simulation time 31327342 ps
CPU time 0.61 seconds
Started Aug 14 04:45:40 PM PDT 24
Finished Aug 14 04:45:41 PM PDT 24
Peak memory 192600 kb
Host smart-7f37ca8b-f84c-4500-87a3-ece8d6b694fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060117302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1060117302
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1264886348
Short name T577
Test name
Test status
Simulation time 425662494 ps
CPU time 2.02 seconds
Started Aug 14 04:45:44 PM PDT 24
Finished Aug 14 04:45:46 PM PDT 24
Peak memory 198056 kb
Host smart-f9a07a34-b8ca-4413-950b-0e5d6a43b8be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264886348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1264886348
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.657549360
Short name T87
Test name
Test status
Simulation time 166469759 ps
CPU time 1.2 seconds
Started Aug 14 04:45:49 PM PDT 24
Finished Aug 14 04:45:51 PM PDT 24
Peak memory 195980 kb
Host smart-20aa7564-3e0d-44dc-8bcb-517766dbeef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657549360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.657549360
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.4168538140
Short name T489
Test name
Test status
Simulation time 36624940 ps
CPU time 0.79 seconds
Started Aug 14 04:45:10 PM PDT 24
Finished Aug 14 04:45:11 PM PDT 24
Peak memory 196560 kb
Host smart-b6825029-ca7d-4ec0-93c2-d0a64ca3d1ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168538140 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.4168538140
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.729234758
Short name T472
Test name
Test status
Simulation time 15138878 ps
CPU time 0.53 seconds
Started Aug 14 04:45:29 PM PDT 24
Finished Aug 14 04:45:30 PM PDT 24
Peak memory 182616 kb
Host smart-3f0a65e4-c1ce-4148-8890-0226412b9256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729234758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.729234758
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.898639813
Short name T573
Test name
Test status
Simulation time 103102587 ps
CPU time 0.69 seconds
Started Aug 14 04:45:23 PM PDT 24
Finished Aug 14 04:45:24 PM PDT 24
Peak memory 192696 kb
Host smart-4acb7daf-731b-4870-a57b-398b27e6b4b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898639813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.898639813
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2200608774
Short name T580
Test name
Test status
Simulation time 23740860 ps
CPU time 1.21 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 198156 kb
Host smart-7f42d2ab-dde7-489b-8437-131c9b8d45e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200608774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2200608774
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1231797942
Short name T582
Test name
Test status
Simulation time 241188703 ps
CPU time 1.06 seconds
Started Aug 14 04:45:30 PM PDT 24
Finished Aug 14 04:45:31 PM PDT 24
Peak memory 184148 kb
Host smart-ba4cda1b-10a4-4faa-a2a7-ad145eabb541
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231797942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1231797942
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3980289908
Short name T561
Test name
Test status
Simulation time 25000492 ps
CPU time 0.75 seconds
Started Aug 14 04:45:30 PM PDT 24
Finished Aug 14 04:45:30 PM PDT 24
Peak memory 195792 kb
Host smart-74a2316e-aaee-43f2-aa61-d306e5ef59fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980289908 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3980289908
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1538909483
Short name T75
Test name
Test status
Simulation time 15035646 ps
CPU time 0.58 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 183508 kb
Host smart-62b37bbe-2f62-4eb8-a7c2-aa79bd18583d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538909483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1538909483
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2000339855
Short name T520
Test name
Test status
Simulation time 11001491 ps
CPU time 0.55 seconds
Started Aug 14 04:45:26 PM PDT 24
Finished Aug 14 04:45:27 PM PDT 24
Peak memory 183104 kb
Host smart-158bf4bc-0dac-4a93-bd5f-d67e0307aec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000339855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2000339855
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3892916981
Short name T60
Test name
Test status
Simulation time 33969536 ps
CPU time 0.82 seconds
Started Aug 14 04:45:29 PM PDT 24
Finished Aug 14 04:45:30 PM PDT 24
Peak memory 194144 kb
Host smart-73ab804c-32d7-44d3-9419-0280d6cc6834
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892916981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3892916981
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.659227732
Short name T552
Test name
Test status
Simulation time 574218181 ps
CPU time 2.1 seconds
Started Aug 14 04:45:31 PM PDT 24
Finished Aug 14 04:45:34 PM PDT 24
Peak memory 197992 kb
Host smart-7717c835-b070-4725-b5c5-7575151216f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659227732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.659227732
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2839147239
Short name T551
Test name
Test status
Simulation time 154265142 ps
CPU time 0.72 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 196076 kb
Host smart-ea7f7d4a-860d-4e8e-b743-9cf8d2d701c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839147239 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2839147239
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3772201381
Short name T557
Test name
Test status
Simulation time 14566891 ps
CPU time 0.57 seconds
Started Aug 14 04:45:44 PM PDT 24
Finished Aug 14 04:45:45 PM PDT 24
Peak memory 183400 kb
Host smart-6812ae4b-4ae0-4567-b9d2-75e3318c8b75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772201381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3772201381
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1294411461
Short name T575
Test name
Test status
Simulation time 12048509 ps
CPU time 0.53 seconds
Started Aug 14 04:45:28 PM PDT 24
Finished Aug 14 04:45:29 PM PDT 24
Peak memory 183268 kb
Host smart-068bf3e6-e968-41a6-a428-3617a41762cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294411461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1294411461
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2939377790
Short name T543
Test name
Test status
Simulation time 103938926 ps
CPU time 0.68 seconds
Started Aug 14 04:45:16 PM PDT 24
Finished Aug 14 04:45:17 PM PDT 24
Peak memory 192860 kb
Host smart-87327b6d-9a8d-48cb-973a-177b6bff2714
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939377790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2939377790
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.919861689
Short name T492
Test name
Test status
Simulation time 50960745 ps
CPU time 2.57 seconds
Started Aug 14 04:45:32 PM PDT 24
Finished Aug 14 04:45:35 PM PDT 24
Peak memory 198112 kb
Host smart-63c0fa6d-2e7e-42e7-8e76-f21ffb0078dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919861689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.919861689
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2814603761
Short name T559
Test name
Test status
Simulation time 43844129 ps
CPU time 0.8 seconds
Started Aug 14 04:45:35 PM PDT 24
Finished Aug 14 04:45:36 PM PDT 24
Peak memory 194484 kb
Host smart-b1d107e0-2cdc-462a-95b3-6dbd814dbbe9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814603761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2814603761
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.886473350
Short name T530
Test name
Test status
Simulation time 159105833 ps
CPU time 0.71 seconds
Started Aug 14 04:45:39 PM PDT 24
Finished Aug 14 04:45:39 PM PDT 24
Peak memory 194056 kb
Host smart-d1bdf27f-cba5-49f5-b955-ff4810c250d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886473350 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.886473350
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3285675331
Short name T554
Test name
Test status
Simulation time 37047651 ps
CPU time 0.56 seconds
Started Aug 14 04:45:24 PM PDT 24
Finished Aug 14 04:45:25 PM PDT 24
Peak memory 183392 kb
Host smart-6967b1a2-cfea-426d-9e10-fd08d0897c65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285675331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3285675331
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1059866924
Short name T536
Test name
Test status
Simulation time 17857331 ps
CPU time 0.52 seconds
Started Aug 14 04:45:23 PM PDT 24
Finished Aug 14 04:45:23 PM PDT 24
Peak memory 182604 kb
Host smart-10c30e25-3cc3-4403-80b6-f9a6f56bedef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059866924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1059866924
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2127884724
Short name T59
Test name
Test status
Simulation time 40042368 ps
CPU time 0.58 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 191904 kb
Host smart-9a42c30a-a94c-4e56-b465-59f54cf8e949
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127884724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2127884724
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3881385490
Short name T542
Test name
Test status
Simulation time 217662006 ps
CPU time 1.54 seconds
Started Aug 14 04:45:49 PM PDT 24
Finished Aug 14 04:45:50 PM PDT 24
Peak memory 198068 kb
Host smart-153d0d09-5e67-4358-8d6e-a7afcc3471b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881385490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3881385490
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2496787478
Short name T583
Test name
Test status
Simulation time 224323825 ps
CPU time 1.01 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 195788 kb
Host smart-cf65919c-4883-4c32-a3f4-ed60aa462bb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496787478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2496787478
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2183509588
Short name T494
Test name
Test status
Simulation time 85060196 ps
CPU time 0.76 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 195768 kb
Host smart-3afbad4a-b89a-45de-bb70-5a9c4285f214
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183509588 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2183509588
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.987441836
Short name T49
Test name
Test status
Simulation time 75129730 ps
CPU time 0.54 seconds
Started Aug 14 04:45:31 PM PDT 24
Finished Aug 14 04:45:32 PM PDT 24
Peak memory 183352 kb
Host smart-fea16005-21b9-4bf6-8ef1-9f17c82f0c93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987441836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.987441836
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2396030508
Short name T511
Test name
Test status
Simulation time 11404027 ps
CPU time 0.53 seconds
Started Aug 14 04:45:35 PM PDT 24
Finished Aug 14 04:45:36 PM PDT 24
Peak memory 182924 kb
Host smart-47158d61-2b7c-4c8f-86ac-0c0a154256d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396030508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2396030508
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2107155454
Short name T58
Test name
Test status
Simulation time 46758227 ps
CPU time 0.69 seconds
Started Aug 14 04:45:29 PM PDT 24
Finished Aug 14 04:45:30 PM PDT 24
Peak memory 192896 kb
Host smart-7fa48ca1-62f4-4519-ad01-a6093f4dfd63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107155454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2107155454
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1917325037
Short name T485
Test name
Test status
Simulation time 120220296 ps
CPU time 1.47 seconds
Started Aug 14 04:45:31 PM PDT 24
Finished Aug 14 04:45:33 PM PDT 24
Peak memory 198136 kb
Host smart-8a03a846-aaeb-46ee-b73e-80669bc905b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917325037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1917325037
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.4185628553
Short name T70
Test name
Test status
Simulation time 38519828 ps
CPU time 0.79 seconds
Started Aug 14 04:45:09 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 183364 kb
Host smart-f93656bf-406e-4524-908c-9b57467eda8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185628553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.4185628553
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2220406373
Short name T528
Test name
Test status
Simulation time 1243265555 ps
CPU time 2.59 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 191768 kb
Host smart-ca7665d6-411f-4e53-b809-df19241565f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220406373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2220406373
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.306896042
Short name T556
Test name
Test status
Simulation time 16798820 ps
CPU time 0.57 seconds
Started Aug 14 04:45:14 PM PDT 24
Finished Aug 14 04:45:15 PM PDT 24
Peak memory 183408 kb
Host smart-ed7d7b0a-fa9e-4e77-8384-0cb8d17a2277
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306896042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.306896042
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2106263721
Short name T519
Test name
Test status
Simulation time 76846467 ps
CPU time 1 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 197644 kb
Host smart-dc4fdf7f-c56c-4ffe-bcac-c15fd78048cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106263721 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2106263721
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2377775579
Short name T66
Test name
Test status
Simulation time 12998693 ps
CPU time 0.56 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 192492 kb
Host smart-4e7d5deb-ef06-47fb-b771-1d540bab93d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377775579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2377775579
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.4125413155
Short name T484
Test name
Test status
Simulation time 30617123 ps
CPU time 0.54 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 183184 kb
Host smart-8159f32f-5d16-4a3a-87ec-d5d3e5e52f43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125413155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.4125413155
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2054895137
Short name T83
Test name
Test status
Simulation time 31938061 ps
CPU time 0.73 seconds
Started Aug 14 04:45:09 PM PDT 24
Finished Aug 14 04:45:10 PM PDT 24
Peak memory 193872 kb
Host smart-2aaaf0e3-b02b-4b86-a866-699c24214896
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054895137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2054895137
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1560052019
Short name T533
Test name
Test status
Simulation time 57896295 ps
CPU time 1.5 seconds
Started Aug 14 04:45:09 PM PDT 24
Finished Aug 14 04:45:10 PM PDT 24
Peak memory 198148 kb
Host smart-48c7cc12-9caa-43ab-8c08-02898ba50d71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560052019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1560052019
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.4071696889
Short name T545
Test name
Test status
Simulation time 84498077 ps
CPU time 1.14 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:12 PM PDT 24
Peak memory 195728 kb
Host smart-b982fc23-9382-427e-9a93-d9bc4bf30ed3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071696889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.4071696889
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.284130521
Short name T497
Test name
Test status
Simulation time 13666130 ps
CPU time 0.56 seconds
Started Aug 14 04:45:28 PM PDT 24
Finished Aug 14 04:45:29 PM PDT 24
Peak memory 183224 kb
Host smart-9b7a8d80-dbec-4fa3-85c0-ce630242246e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284130521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.284130521
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.831568305
Short name T514
Test name
Test status
Simulation time 19252095 ps
CPU time 0.52 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 183236 kb
Host smart-4a41f9c3-2523-4f26-91cf-5e97c22e1a6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831568305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.831568305
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.569613626
Short name T525
Test name
Test status
Simulation time 70700302 ps
CPU time 0.56 seconds
Started Aug 14 04:45:27 PM PDT 24
Finished Aug 14 04:45:27 PM PDT 24
Peak memory 183248 kb
Host smart-c2526b97-ff82-4302-8cb7-19c39da9c440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569613626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.569613626
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1790348837
Short name T548
Test name
Test status
Simulation time 28668283 ps
CPU time 0.53 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 183024 kb
Host smart-87d8590f-8d0b-4f31-ba60-9cf3a0c8b804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790348837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1790348837
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.369654815
Short name T572
Test name
Test status
Simulation time 19864694 ps
CPU time 0.56 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 183228 kb
Host smart-b4be485d-bab3-4dff-894f-2285db2851a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369654815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.369654815
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.164933607
Short name T463
Test name
Test status
Simulation time 45746657 ps
CPU time 0.53 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 182720 kb
Host smart-33d352f7-096e-4d4d-a0c3-549907c609a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164933607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.164933607
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3813395269
Short name T490
Test name
Test status
Simulation time 41578143 ps
CPU time 0.57 seconds
Started Aug 14 04:45:31 PM PDT 24
Finished Aug 14 04:45:32 PM PDT 24
Peak memory 183128 kb
Host smart-4e6c693f-9483-4301-a33f-60d9c6af30e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813395269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3813395269
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.728895535
Short name T473
Test name
Test status
Simulation time 14604718 ps
CPU time 0.53 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 182920 kb
Host smart-637f45dd-ec1c-46ba-b5c7-e4949cafefb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728895535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.728895535
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1528158608
Short name T500
Test name
Test status
Simulation time 62303800 ps
CPU time 0.56 seconds
Started Aug 14 04:45:08 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 183276 kb
Host smart-99801ba5-eb82-4361-a599-e44b2b8ce357
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528158608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1528158608
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1654476944
Short name T529
Test name
Test status
Simulation time 21530819 ps
CPU time 0.53 seconds
Started Aug 14 04:45:23 PM PDT 24
Finished Aug 14 04:45:29 PM PDT 24
Peak memory 183244 kb
Host smart-8460ca9e-63f9-48d2-9060-8ffa3e810dee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654476944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1654476944
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2321339128
Short name T506
Test name
Test status
Simulation time 15243403 ps
CPU time 0.67 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 192752 kb
Host smart-69280f46-7799-4044-866c-fc81a6a9eaca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321339128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2321339128
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2365667960
Short name T67
Test name
Test status
Simulation time 1687016569 ps
CPU time 2.48 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:14 PM PDT 24
Peak memory 192712 kb
Host smart-006e8ace-f6cc-4268-bc13-fe8314e522f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365667960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2365667960
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.730978008
Short name T498
Test name
Test status
Simulation time 19354616 ps
CPU time 0.56 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 183276 kb
Host smart-34f5dfe3-d5df-4e11-af71-8b469e56c408
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730978008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.730978008
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3419436599
Short name T549
Test name
Test status
Simulation time 95503865 ps
CPU time 0.82 seconds
Started Aug 14 04:45:18 PM PDT 24
Finished Aug 14 04:45:19 PM PDT 24
Peak memory 196468 kb
Host smart-7f6faf35-407c-4ca3-a318-64bf27590a27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419436599 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3419436599
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3353088502
Short name T61
Test name
Test status
Simulation time 28013115 ps
CPU time 0.56 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 183396 kb
Host smart-a11af0df-2ffa-4fae-beb4-1ab74c0233f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353088502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3353088502
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.742298921
Short name T532
Test name
Test status
Simulation time 40332115 ps
CPU time 0.54 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 183200 kb
Host smart-4c6b580d-abcc-4826-ac58-af77d5873ac3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742298921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.742298921
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.249472550
Short name T563
Test name
Test status
Simulation time 51079938 ps
CPU time 0.67 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 192368 kb
Host smart-9dddf90e-c3ea-4392-a145-853bd03d3fe8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249472550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.249472550
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2125812240
Short name T504
Test name
Test status
Simulation time 47392786 ps
CPU time 1.18 seconds
Started Aug 14 04:45:28 PM PDT 24
Finished Aug 14 04:45:29 PM PDT 24
Peak memory 197908 kb
Host smart-2dbf3fee-7a7d-4c91-8f64-d7f631a4043d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125812240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2125812240
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3334817698
Short name T560
Test name
Test status
Simulation time 123029154 ps
CPU time 1.3 seconds
Started Aug 14 04:45:13 PM PDT 24
Finished Aug 14 04:45:15 PM PDT 24
Peak memory 195968 kb
Host smart-d97598eb-1593-4fa6-b7a5-fcccf76bba68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334817698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3334817698
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1301105699
Short name T578
Test name
Test status
Simulation time 24734867 ps
CPU time 0.55 seconds
Started Aug 14 04:45:26 PM PDT 24
Finished Aug 14 04:45:26 PM PDT 24
Peak memory 183216 kb
Host smart-a9c236f6-2224-4cd1-ac3e-566d0bd4130c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301105699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1301105699
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3303411580
Short name T541
Test name
Test status
Simulation time 39435773 ps
CPU time 0.55 seconds
Started Aug 14 04:45:52 PM PDT 24
Finished Aug 14 04:45:53 PM PDT 24
Peak memory 183100 kb
Host smart-c1ef3c45-9851-46c1-a8cd-a6250106b929
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303411580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3303411580
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1096958464
Short name T479
Test name
Test status
Simulation time 33490834 ps
CPU time 0.54 seconds
Started Aug 14 04:45:57 PM PDT 24
Finished Aug 14 04:45:58 PM PDT 24
Peak memory 183128 kb
Host smart-da90b417-ad73-4965-b721-299c1f993542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096958464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1096958464
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1504799157
Short name T540
Test name
Test status
Simulation time 144636119 ps
CPU time 0.56 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 183240 kb
Host smart-d02b4c42-780e-474f-bfc4-13a0206a828a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504799157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1504799157
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.234175339
Short name T480
Test name
Test status
Simulation time 42403689 ps
CPU time 0.55 seconds
Started Aug 14 04:45:26 PM PDT 24
Finished Aug 14 04:45:27 PM PDT 24
Peak memory 183228 kb
Host smart-1cb46473-156e-4416-a399-53e0082fbfe3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234175339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.234175339
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1127306240
Short name T538
Test name
Test status
Simulation time 24142636 ps
CPU time 0.53 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 182908 kb
Host smart-46956e5a-5f62-4a37-81e2-e7ecd53eabe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127306240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1127306240
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.917292013
Short name T537
Test name
Test status
Simulation time 14255459 ps
CPU time 0.55 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 182896 kb
Host smart-8c864874-2b20-489b-9c6f-ddab391ca873
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917292013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.917292013
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.808156095
Short name T470
Test name
Test status
Simulation time 25611776 ps
CPU time 0.53 seconds
Started Aug 14 04:45:23 PM PDT 24
Finished Aug 14 04:45:24 PM PDT 24
Peak memory 182760 kb
Host smart-b25cc2f4-0cf8-43b2-8317-785f84f7b0fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808156095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.808156095
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.4210865279
Short name T486
Test name
Test status
Simulation time 20072918 ps
CPU time 0.53 seconds
Started Aug 14 04:45:08 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 183200 kb
Host smart-bab9edf5-04c0-40be-b680-d3c4352c9196
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210865279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.4210865279
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3459730017
Short name T565
Test name
Test status
Simulation time 24374230 ps
CPU time 0.52 seconds
Started Aug 14 04:45:43 PM PDT 24
Finished Aug 14 04:45:44 PM PDT 24
Peak memory 182688 kb
Host smart-9a745974-3c6f-4f97-b1ac-4b2e342e766a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459730017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3459730017
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3134217694
Short name T72
Test name
Test status
Simulation time 127023111 ps
CPU time 0.69 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:12 PM PDT 24
Peak memory 183312 kb
Host smart-931fddaa-c0ec-4539-b271-620b9ae88760
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134217694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3134217694
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2516179553
Short name T71
Test name
Test status
Simulation time 280501152 ps
CPU time 2.62 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 193912 kb
Host smart-3d65dc12-5aa3-478c-9a67-b48d9bf0bd49
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516179553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2516179553
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.691592183
Short name T84
Test name
Test status
Simulation time 54147918 ps
CPU time 0.55 seconds
Started Aug 14 04:45:17 PM PDT 24
Finished Aug 14 04:45:18 PM PDT 24
Peak memory 183296 kb
Host smart-bcf338d3-636d-424f-87de-e47d11bd8c8f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691592183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.691592183
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3988219402
Short name T581
Test name
Test status
Simulation time 58929266 ps
CPU time 0.86 seconds
Started Aug 14 04:45:28 PM PDT 24
Finished Aug 14 04:45:29 PM PDT 24
Peak memory 197524 kb
Host smart-3f153e3f-0768-4204-b2c2-e4209ec9339c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988219402 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3988219402
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2335335200
Short name T78
Test name
Test status
Simulation time 44285205 ps
CPU time 0.55 seconds
Started Aug 14 04:45:08 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 182968 kb
Host smart-f4423fc4-ed0b-4751-bc1b-8733d8dfd4aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335335200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2335335200
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1549833586
Short name T493
Test name
Test status
Simulation time 11449121 ps
CPU time 0.57 seconds
Started Aug 14 04:45:25 PM PDT 24
Finished Aug 14 04:45:25 PM PDT 24
Peak memory 183320 kb
Host smart-830caccb-1ffd-4714-8f8e-15ed7eea26ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549833586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1549833586
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1976262910
Short name T508
Test name
Test status
Simulation time 19262554 ps
CPU time 0.72 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 193876 kb
Host smart-b233818b-2f38-4830-b9bf-ff6e612fef5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976262910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1976262910
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2542758587
Short name T465
Test name
Test status
Simulation time 141838188 ps
CPU time 1.9 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 198072 kb
Host smart-40495c4f-f258-4168-82b9-cde9dad59608
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542758587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2542758587
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1037355833
Short name T85
Test name
Test status
Simulation time 80471817 ps
CPU time 0.83 seconds
Started Aug 14 04:45:12 PM PDT 24
Finished Aug 14 04:45:13 PM PDT 24
Peak memory 194456 kb
Host smart-c814740a-2d46-4dea-b704-a749f09f3694
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037355833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1037355833
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1582818502
Short name T510
Test name
Test status
Simulation time 16263827 ps
CPU time 0.54 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 183268 kb
Host smart-d9d57960-0bfa-42a3-82da-c48bffca5c43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582818502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1582818502
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1807000637
Short name T467
Test name
Test status
Simulation time 12940401 ps
CPU time 0.53 seconds
Started Aug 14 04:45:30 PM PDT 24
Finished Aug 14 04:45:31 PM PDT 24
Peak memory 182708 kb
Host smart-e377492f-1a50-478e-b527-ba1761df0e4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807000637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1807000637
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2103817696
Short name T471
Test name
Test status
Simulation time 38995643 ps
CPU time 0.51 seconds
Started Aug 14 04:45:41 PM PDT 24
Finished Aug 14 04:45:41 PM PDT 24
Peak memory 182724 kb
Host smart-90424d23-a689-4bbd-8397-9a971c3ee858
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103817696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2103817696
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4133222226
Short name T531
Test name
Test status
Simulation time 173917700 ps
CPU time 0.52 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 182744 kb
Host smart-63189f58-8bb9-4375-afbe-dac5cbab6b8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133222226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4133222226
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2389136993
Short name T534
Test name
Test status
Simulation time 28175988 ps
CPU time 0.53 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 183216 kb
Host smart-a4735e7a-daf9-4527-accf-7f7ed54ae0af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389136993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2389136993
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1776376780
Short name T570
Test name
Test status
Simulation time 53755649 ps
CPU time 0.6 seconds
Started Aug 14 04:45:34 PM PDT 24
Finished Aug 14 04:45:35 PM PDT 24
Peak memory 183416 kb
Host smart-c578c412-ae3d-4887-9fd1-fc5879d1dc89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776376780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1776376780
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.138452935
Short name T478
Test name
Test status
Simulation time 103204557 ps
CPU time 0.56 seconds
Started Aug 14 04:45:21 PM PDT 24
Finished Aug 14 04:45:21 PM PDT 24
Peak memory 183192 kb
Host smart-895aafcc-c11a-4657-9cd4-16127fa6e9a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138452935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.138452935
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1856362513
Short name T535
Test name
Test status
Simulation time 33328694 ps
CPU time 0.52 seconds
Started Aug 14 04:45:17 PM PDT 24
Finished Aug 14 04:45:17 PM PDT 24
Peak memory 182752 kb
Host smart-4fe02dc6-1f83-4506-a1c1-462c80fad8e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856362513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1856362513
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1958240929
Short name T462
Test name
Test status
Simulation time 13612515 ps
CPU time 0.57 seconds
Started Aug 14 04:45:33 PM PDT 24
Finished Aug 14 04:45:33 PM PDT 24
Peak memory 183108 kb
Host smart-1db0bd6b-1a7d-4808-a491-38a856f93474
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958240929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1958240929
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3404936518
Short name T495
Test name
Test status
Simulation time 51194554 ps
CPU time 0.58 seconds
Started Aug 14 04:45:35 PM PDT 24
Finished Aug 14 04:45:35 PM PDT 24
Peak memory 183228 kb
Host smart-6c40b1d8-b2c4-45d8-bfd2-e681a378c3e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404936518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3404936518
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.660928677
Short name T517
Test name
Test status
Simulation time 35782763 ps
CPU time 0.85 seconds
Started Aug 14 04:45:09 PM PDT 24
Finished Aug 14 04:45:10 PM PDT 24
Peak memory 197588 kb
Host smart-a77aab34-c81b-4c25-be48-4e7e8f0f53d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660928677 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.660928677
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.139177651
Short name T69
Test name
Test status
Simulation time 14638979 ps
CPU time 0.58 seconds
Started Aug 14 04:45:17 PM PDT 24
Finished Aug 14 04:45:18 PM PDT 24
Peak memory 183340 kb
Host smart-d562dbf9-d126-4558-bc3c-7823182184e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139177651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.139177651
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.16265706
Short name T468
Test name
Test status
Simulation time 15267069 ps
CPU time 0.56 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:17 PM PDT 24
Peak memory 183244 kb
Host smart-ad02c924-cbac-4bce-8e59-8df34e003718
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16265706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.16265706
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.396341950
Short name T80
Test name
Test status
Simulation time 18205547 ps
CPU time 0.7 seconds
Started Aug 14 04:45:21 PM PDT 24
Finished Aug 14 04:45:22 PM PDT 24
Peak memory 192256 kb
Host smart-58a48421-a45a-4c3f-9561-c7972630ba05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396341950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.396341950
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2118043508
Short name T483
Test name
Test status
Simulation time 140903099 ps
CPU time 0.89 seconds
Started Aug 14 04:45:23 PM PDT 24
Finished Aug 14 04:45:24 PM PDT 24
Peak memory 191516 kb
Host smart-5fc53978-5c91-44b4-b31f-3dd98f763e1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118043508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2118043508
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1449570098
Short name T547
Test name
Test status
Simulation time 312234869 ps
CPU time 1.04 seconds
Started Aug 14 04:45:11 PM PDT 24
Finished Aug 14 04:45:18 PM PDT 24
Peak memory 191864 kb
Host smart-3df0ab47-997a-4e4a-960a-465111e15e56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449570098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1449570098
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.642210632
Short name T501
Test name
Test status
Simulation time 93128399 ps
CPU time 0.78 seconds
Started Aug 14 04:45:08 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 196852 kb
Host smart-d29fef0f-b8f2-423d-b0fe-a5e1b0c934f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642210632 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.642210632
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.4154124740
Short name T558
Test name
Test status
Simulation time 69125850 ps
CPU time 0.55 seconds
Started Aug 14 04:45:09 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 183344 kb
Host smart-f60c2231-3d60-47bd-b72b-c9caad35d13c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154124740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.4154124740
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2531860182
Short name T546
Test name
Test status
Simulation time 12556952 ps
CPU time 0.5 seconds
Started Aug 14 04:45:04 PM PDT 24
Finished Aug 14 04:45:05 PM PDT 24
Peak memory 182764 kb
Host smart-f500d1e0-1060-4ab5-bfe2-6ffb03a8f7d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531860182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2531860182
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.691948166
Short name T81
Test name
Test status
Simulation time 47914126 ps
CPU time 0.6 seconds
Started Aug 14 04:45:22 PM PDT 24
Finished Aug 14 04:45:22 PM PDT 24
Peak memory 192196 kb
Host smart-8f53d43d-e768-4a32-867a-cfa8cd3570a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691948166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.691948166
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2234179254
Short name T475
Test name
Test status
Simulation time 234792668 ps
CPU time 2.25 seconds
Started Aug 14 04:45:21 PM PDT 24
Finished Aug 14 04:45:24 PM PDT 24
Peak memory 198088 kb
Host smart-21d60acf-3fb5-4675-a475-c5ce6366ffb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234179254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2234179254
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3157834522
Short name T539
Test name
Test status
Simulation time 110134571 ps
CPU time 1.07 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 195812 kb
Host smart-ef4ba7c1-1b7e-4eae-813f-c2541a50091d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157834522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3157834522
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2493976420
Short name T512
Test name
Test status
Simulation time 26932396 ps
CPU time 0.65 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 194224 kb
Host smart-b358a074-af5a-42d3-b98d-0359375b1eb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493976420 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2493976420
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1165480317
Short name T562
Test name
Test status
Simulation time 12090423 ps
CPU time 0.6 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 183344 kb
Host smart-0ce5ca7c-1462-4656-811c-4f3bd372dc22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165480317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1165480317
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2020754998
Short name T488
Test name
Test status
Simulation time 12419352 ps
CPU time 0.55 seconds
Started Aug 14 04:45:32 PM PDT 24
Finished Aug 14 04:45:32 PM PDT 24
Peak memory 182832 kb
Host smart-cdf70f7e-7db4-4539-b6dd-5b7ebda4b3a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020754998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2020754998
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2002802741
Short name T48
Test name
Test status
Simulation time 48108893 ps
CPU time 0.78 seconds
Started Aug 14 04:45:05 PM PDT 24
Finished Aug 14 04:45:06 PM PDT 24
Peak memory 192360 kb
Host smart-d74b6709-72b5-4084-b708-a2a439c1462c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002802741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2002802741
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1982118834
Short name T464
Test name
Test status
Simulation time 58542464 ps
CPU time 1.29 seconds
Started Aug 14 04:45:07 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 197016 kb
Host smart-0b3642c2-946e-415b-8619-ca279c0db56f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982118834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1982118834
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.511659552
Short name T574
Test name
Test status
Simulation time 45054840 ps
CPU time 0.84 seconds
Started Aug 14 04:45:18 PM PDT 24
Finished Aug 14 04:45:19 PM PDT 24
Peak memory 193996 kb
Host smart-cd6ae561-6f51-4862-9a90-924f56b28bd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511659552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.511659552
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3991614034
Short name T51
Test name
Test status
Simulation time 112595635 ps
CPU time 0.87 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:08 PM PDT 24
Peak memory 195920 kb
Host smart-9bacd5f2-5554-4cdf-a7ba-cc78b58859d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991614034 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3991614034
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1882481934
Short name T73
Test name
Test status
Simulation time 51595910 ps
CPU time 0.58 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 183420 kb
Host smart-518207f5-62f4-48af-bca5-e6cf1236babf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882481934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1882481934
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2831365397
Short name T522
Test name
Test status
Simulation time 113560590 ps
CPU time 0.56 seconds
Started Aug 14 04:45:35 PM PDT 24
Finished Aug 14 04:45:36 PM PDT 24
Peak memory 183100 kb
Host smart-c6cf15b5-32c9-4614-ad98-2a4322f67b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831365397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2831365397
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2490449172
Short name T550
Test name
Test status
Simulation time 100586776 ps
CPU time 0.73 seconds
Started Aug 14 04:45:08 PM PDT 24
Finished Aug 14 04:45:09 PM PDT 24
Peak memory 192388 kb
Host smart-28ee5550-993a-4395-8c5c-1e083b6cde41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490449172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2490449172
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.4011077803
Short name T523
Test name
Test status
Simulation time 28366820 ps
CPU time 1.25 seconds
Started Aug 14 04:45:03 PM PDT 24
Finished Aug 14 04:45:04 PM PDT 24
Peak memory 198040 kb
Host smart-8eb1f0c8-fcc6-4adf-b650-796e7e4e2ee8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011077803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.4011077803
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1269857616
Short name T516
Test name
Test status
Simulation time 165731609 ps
CPU time 0.78 seconds
Started Aug 14 04:45:51 PM PDT 24
Finished Aug 14 04:45:57 PM PDT 24
Peak memory 183624 kb
Host smart-488239ab-ec7d-43b5-97d3-0361a5f1b5b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269857616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1269857616
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.277797327
Short name T521
Test name
Test status
Simulation time 234825327 ps
CPU time 0.88 seconds
Started Aug 14 04:45:35 PM PDT 24
Finished Aug 14 04:45:36 PM PDT 24
Peak memory 197272 kb
Host smart-102c68fb-8786-435f-a2ec-09cb29051a5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277797327 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.277797327
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3776672180
Short name T63
Test name
Test status
Simulation time 48600001 ps
CPU time 0.6 seconds
Started Aug 14 04:45:06 PM PDT 24
Finished Aug 14 04:45:07 PM PDT 24
Peak memory 183336 kb
Host smart-a1972ce4-b4e4-4e3e-ad05-908b0cdbdecd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776672180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3776672180
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.243220539
Short name T518
Test name
Test status
Simulation time 39774739 ps
CPU time 0.57 seconds
Started Aug 14 04:45:39 PM PDT 24
Finished Aug 14 04:45:40 PM PDT 24
Peak memory 183320 kb
Host smart-3e7384d5-bad0-4185-b217-d5c7e99153bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243220539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.243220539
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1540904845
Short name T576
Test name
Test status
Simulation time 37148512 ps
CPU time 0.62 seconds
Started Aug 14 04:45:09 PM PDT 24
Finished Aug 14 04:45:10 PM PDT 24
Peak memory 192312 kb
Host smart-012773a8-9ef8-478f-949a-3bfa36980c01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540904845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1540904845
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3011021507
Short name T513
Test name
Test status
Simulation time 634767236 ps
CPU time 2.92 seconds
Started Aug 14 04:45:23 PM PDT 24
Finished Aug 14 04:45:31 PM PDT 24
Peak memory 198196 kb
Host smart-2e1d3148-66df-4425-801e-0590380cfe37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011021507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3011021507
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2514516295
Short name T569
Test name
Test status
Simulation time 346071087 ps
CPU time 1.27 seconds
Started Aug 14 04:45:12 PM PDT 24
Finished Aug 14 04:45:18 PM PDT 24
Peak memory 196148 kb
Host smart-7fb51eef-6f3c-4ef4-95ec-d70efadc1aca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514516295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2514516295
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.4004816667
Short name T300
Test name
Test status
Simulation time 75693422040 ps
CPU time 40.68 seconds
Started Aug 14 04:48:32 PM PDT 24
Finished Aug 14 04:49:13 PM PDT 24
Peak memory 183624 kb
Host smart-b4553eca-43d5-4a7a-8ce4-ddf81d2c36fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004816667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.4004816667
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1250096444
Short name T387
Test name
Test status
Simulation time 152368082438 ps
CPU time 117.19 seconds
Started Aug 14 04:48:22 PM PDT 24
Finished Aug 14 04:50:19 PM PDT 24
Peak memory 183612 kb
Host smart-08573dfd-3f95-4695-b55c-3d8ac44a4324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250096444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1250096444
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.333251020
Short name T9
Test name
Test status
Simulation time 38254739945 ps
CPU time 66.58 seconds
Started Aug 14 04:48:29 PM PDT 24
Finished Aug 14 04:49:35 PM PDT 24
Peak memory 183604 kb
Host smart-c03e629e-5859-4e38-b6aa-c176aaf2a59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333251020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.333251020
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.2516337805
Short name T38
Test name
Test status
Simulation time 6577209466 ps
CPU time 26.72 seconds
Started Aug 14 04:48:28 PM PDT 24
Finished Aug 14 04:48:55 PM PDT 24
Peak memory 193900 kb
Host smart-9b77c755-7b40-4d69-9d7c-426dcb4fa1c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516337805 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.2516337805
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3367295385
Short name T349
Test name
Test status
Simulation time 1272712124030 ps
CPU time 624.02 seconds
Started Aug 14 04:48:24 PM PDT 24
Finished Aug 14 04:58:48 PM PDT 24
Peak memory 183608 kb
Host smart-5465b81a-d151-4bc3-b517-c292c6b49ee1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367295385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3367295385
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2595988394
Short name T403
Test name
Test status
Simulation time 129114702949 ps
CPU time 50.16 seconds
Started Aug 14 04:48:24 PM PDT 24
Finished Aug 14 04:49:14 PM PDT 24
Peak memory 183484 kb
Host smart-7134dead-e06e-45be-94bf-ea71578fc374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595988394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2595988394
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2349570001
Short name T380
Test name
Test status
Simulation time 54190489 ps
CPU time 0.56 seconds
Started Aug 14 04:48:33 PM PDT 24
Finished Aug 14 04:48:33 PM PDT 24
Peak memory 183292 kb
Host smart-fd9ac3f0-22f8-41ed-9546-f1302d24cee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349570001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2349570001
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3676828662
Short name T20
Test name
Test status
Simulation time 44548777 ps
CPU time 0.77 seconds
Started Aug 14 04:48:33 PM PDT 24
Finished Aug 14 04:48:34 PM PDT 24
Peak memory 214664 kb
Host smart-2681cfa7-cffb-438a-9f28-67245d4a82d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676828662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3676828662
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3445017323
Short name T121
Test name
Test status
Simulation time 709286246373 ps
CPU time 370.31 seconds
Started Aug 14 04:48:40 PM PDT 24
Finished Aug 14 04:54:51 PM PDT 24
Peak memory 183552 kb
Host smart-32141af1-9547-4181-a44a-4db589e54f5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445017323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3445017323
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1353011423
Short name T398
Test name
Test status
Simulation time 48109097561 ps
CPU time 73.03 seconds
Started Aug 14 04:48:42 PM PDT 24
Finished Aug 14 04:49:55 PM PDT 24
Peak memory 183508 kb
Host smart-b90d495d-c7f1-4999-9616-3570d0e91b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353011423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1353011423
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.80313840
Short name T324
Test name
Test status
Simulation time 584082547324 ps
CPU time 115.48 seconds
Started Aug 14 04:48:45 PM PDT 24
Finished Aug 14 04:50:40 PM PDT 24
Peak memory 191796 kb
Host smart-94c7721c-2284-46c0-bd8b-13a51587e1fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80313840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.80313840
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2762635058
Short name T288
Test name
Test status
Simulation time 71489555826 ps
CPU time 43.29 seconds
Started Aug 14 04:48:43 PM PDT 24
Finished Aug 14 04:49:26 PM PDT 24
Peak memory 191716 kb
Host smart-e645099f-43c6-499d-bba5-3141c71b5a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762635058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2762635058
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.998287999
Short name T321
Test name
Test status
Simulation time 11048033477 ps
CPU time 20.99 seconds
Started Aug 14 04:50:17 PM PDT 24
Finished Aug 14 04:50:38 PM PDT 24
Peak memory 183604 kb
Host smart-7e9b10dd-030d-4b07-a42c-5486ec59a5fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998287999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.998287999
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1050958169
Short name T245
Test name
Test status
Simulation time 117933505344 ps
CPU time 66.49 seconds
Started Aug 14 04:50:15 PM PDT 24
Finished Aug 14 04:51:22 PM PDT 24
Peak memory 183532 kb
Host smart-a322464d-8d33-45a1-8ee0-8c78dfc655d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050958169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1050958169
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.4208895719
Short name T138
Test name
Test status
Simulation time 363446771208 ps
CPU time 223.13 seconds
Started Aug 14 04:50:16 PM PDT 24
Finished Aug 14 04:53:59 PM PDT 24
Peak memory 191840 kb
Host smart-b649340a-4df8-483d-9056-739654daaa75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208895719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.4208895719
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1060733368
Short name T261
Test name
Test status
Simulation time 293551464497 ps
CPU time 247.89 seconds
Started Aug 14 04:50:15 PM PDT 24
Finished Aug 14 04:54:23 PM PDT 24
Peak memory 191740 kb
Host smart-385e65e3-af36-4fbe-9d49-054cda3d260a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060733368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1060733368
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.4013627044
Short name T214
Test name
Test status
Simulation time 635271927212 ps
CPU time 227.75 seconds
Started Aug 14 04:50:16 PM PDT 24
Finished Aug 14 04:54:04 PM PDT 24
Peak memory 191680 kb
Host smart-f653cf35-3128-4c2a-8fc8-437308b7d561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013627044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.4013627044
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.927356994
Short name T46
Test name
Test status
Simulation time 209064997961 ps
CPU time 147.43 seconds
Started Aug 14 04:48:40 PM PDT 24
Finished Aug 14 04:51:07 PM PDT 24
Peak memory 183520 kb
Host smart-24d2f444-8070-4b1f-89c4-bd0b064d6414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927356994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.927356994
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.472482960
Short name T289
Test name
Test status
Simulation time 62952088962 ps
CPU time 44.64 seconds
Started Aug 14 04:48:40 PM PDT 24
Finished Aug 14 04:49:25 PM PDT 24
Peak memory 183476 kb
Host smart-fccc53a8-f69c-46c5-9596-2a23516829ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472482960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.472482960
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3597266016
Short name T370
Test name
Test status
Simulation time 1044792850 ps
CPU time 1.9 seconds
Started Aug 14 04:48:40 PM PDT 24
Finished Aug 14 04:48:42 PM PDT 24
Peak memory 191580 kb
Host smart-69384d12-1fd3-42ba-be91-790cdf5827a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597266016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3597266016
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.287860204
Short name T142
Test name
Test status
Simulation time 1914323332310 ps
CPU time 3064.2 seconds
Started Aug 14 04:48:41 PM PDT 24
Finished Aug 14 05:39:45 PM PDT 24
Peak memory 196156 kb
Host smart-df9032d7-431b-4391-a12a-1edb2ecab401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287860204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
287860204
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.1802386163
Short name T338
Test name
Test status
Simulation time 63095154532 ps
CPU time 132.72 seconds
Started Aug 14 04:50:17 PM PDT 24
Finished Aug 14 04:52:30 PM PDT 24
Peak memory 191716 kb
Host smart-d1dd8e61-b709-4027-8618-d61b4f756d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802386163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1802386163
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.87246673
Short name T213
Test name
Test status
Simulation time 82525449371 ps
CPU time 73.56 seconds
Started Aug 14 04:50:24 PM PDT 24
Finished Aug 14 04:51:38 PM PDT 24
Peak memory 183600 kb
Host smart-a9224d5b-eb64-4dfa-b29c-481e5d669843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87246673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.87246673
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1433127364
Short name T107
Test name
Test status
Simulation time 774284921914 ps
CPU time 2475.93 seconds
Started Aug 14 04:50:24 PM PDT 24
Finished Aug 14 05:31:40 PM PDT 24
Peak memory 191812 kb
Host smart-70ae9203-864f-4a85-8a80-b4d660898684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433127364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1433127364
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.4235310801
Short name T223
Test name
Test status
Simulation time 378667860714 ps
CPU time 383.16 seconds
Started Aug 14 04:50:25 PM PDT 24
Finished Aug 14 04:56:48 PM PDT 24
Peak memory 191820 kb
Host smart-c59b3ec4-d0f0-4ce9-ab20-b95058516ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235310801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.4235310801
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1687227417
Short name T6
Test name
Test status
Simulation time 72459481514 ps
CPU time 101.76 seconds
Started Aug 14 04:50:25 PM PDT 24
Finished Aug 14 04:52:07 PM PDT 24
Peak memory 195456 kb
Host smart-85f25132-3c6b-418d-a13f-e5abb5f8cedc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687227417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1687227417
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2392819759
Short name T279
Test name
Test status
Simulation time 401098613864 ps
CPU time 385.91 seconds
Started Aug 14 04:50:25 PM PDT 24
Finished Aug 14 04:56:51 PM PDT 24
Peak memory 191844 kb
Host smart-8f7b39ad-08b5-40ab-91ee-fa1c2e4b64d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392819759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2392819759
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3580113528
Short name T445
Test name
Test status
Simulation time 142045299167 ps
CPU time 231.37 seconds
Started Aug 14 04:48:41 PM PDT 24
Finished Aug 14 04:52:33 PM PDT 24
Peak memory 183556 kb
Host smart-7090bb5c-b62c-4fb3-aa00-2a348c81b55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580113528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3580113528
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.4124662315
Short name T146
Test name
Test status
Simulation time 166664467768 ps
CPU time 176.07 seconds
Started Aug 14 04:48:41 PM PDT 24
Finished Aug 14 04:51:37 PM PDT 24
Peak memory 183540 kb
Host smart-b166459e-c509-4787-be65-af389e9b4de8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124662315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4124662315
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.175418628
Short name T130
Test name
Test status
Simulation time 305034812010 ps
CPU time 144.87 seconds
Started Aug 14 04:48:49 PM PDT 24
Finished Aug 14 04:51:14 PM PDT 24
Peak memory 191724 kb
Host smart-9768c7cd-d025-46fe-a61c-ef4ee758fcf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175418628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.175418628
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.2838468411
Short name T359
Test name
Test status
Simulation time 197637686965 ps
CPU time 538.16 seconds
Started Aug 14 04:50:25 PM PDT 24
Finished Aug 14 04:59:23 PM PDT 24
Peak memory 183592 kb
Host smart-cf20ddc9-0204-4675-b458-599a5b43ef22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838468411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2838468411
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3173433913
Short name T306
Test name
Test status
Simulation time 171713106771 ps
CPU time 272.66 seconds
Started Aug 14 04:50:27 PM PDT 24
Finished Aug 14 04:54:59 PM PDT 24
Peak memory 191776 kb
Host smart-e033df21-fa63-491f-a6c6-18029774841b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173433913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3173433913
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3029303200
Short name T340
Test name
Test status
Simulation time 119730125586 ps
CPU time 561.28 seconds
Started Aug 14 04:50:24 PM PDT 24
Finished Aug 14 04:59:46 PM PDT 24
Peak memory 191680 kb
Host smart-a37851f7-f7ec-409e-85ab-da70ae79fdf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029303200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3029303200
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.642760778
Short name T330
Test name
Test status
Simulation time 262798677146 ps
CPU time 998.93 seconds
Started Aug 14 04:50:24 PM PDT 24
Finished Aug 14 05:07:03 PM PDT 24
Peak memory 191784 kb
Host smart-50603422-ea62-499b-a530-44404a7f1f1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642760778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.642760778
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.396919509
Short name T427
Test name
Test status
Simulation time 668187115762 ps
CPU time 250.34 seconds
Started Aug 14 04:50:23 PM PDT 24
Finished Aug 14 04:54:34 PM PDT 24
Peak memory 191780 kb
Host smart-150cb562-0567-44a6-b6b9-849b2f37e66d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396919509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.396919509
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.553198421
Short name T256
Test name
Test status
Simulation time 451859055945 ps
CPU time 192.32 seconds
Started Aug 14 04:50:26 PM PDT 24
Finished Aug 14 04:53:39 PM PDT 24
Peak memory 191784 kb
Host smart-fd94bb9b-2d36-44d2-9eab-dee1098d25eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553198421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.553198421
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2771366478
Short name T207
Test name
Test status
Simulation time 2878230184506 ps
CPU time 1379.13 seconds
Started Aug 14 04:48:51 PM PDT 24
Finished Aug 14 05:11:50 PM PDT 24
Peak memory 183540 kb
Host smart-037cdde4-81c4-48ba-811d-16ebecb2a4b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771366478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2771366478
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3633696564
Short name T401
Test name
Test status
Simulation time 70486556120 ps
CPU time 99.3 seconds
Started Aug 14 04:48:54 PM PDT 24
Finished Aug 14 04:50:34 PM PDT 24
Peak memory 183592 kb
Host smart-123ec5c4-bf91-43f1-8569-5c6bfac7c0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633696564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3633696564
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.404572700
Short name T154
Test name
Test status
Simulation time 41167641045 ps
CPU time 182.49 seconds
Started Aug 14 04:48:51 PM PDT 24
Finished Aug 14 04:51:54 PM PDT 24
Peak memory 183588 kb
Host smart-419ab476-6d5b-4050-8178-abb096d3f863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404572700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.404572700
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.540425865
Short name T367
Test name
Test status
Simulation time 776554447 ps
CPU time 2.34 seconds
Started Aug 14 04:48:51 PM PDT 24
Finished Aug 14 04:48:54 PM PDT 24
Peak memory 183500 kb
Host smart-9b2bc6c3-ad6f-4bdf-85a5-969ea5121c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540425865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.540425865
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.4145135469
Short name T54
Test name
Test status
Simulation time 639167266923 ps
CPU time 580 seconds
Started Aug 14 04:48:50 PM PDT 24
Finished Aug 14 04:58:31 PM PDT 24
Peak memory 183596 kb
Host smart-8102fab9-00ce-4b84-adc4-d680ef83974c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145135469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.4145135469
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.2117383518
Short name T181
Test name
Test status
Simulation time 69035290715 ps
CPU time 48.92 seconds
Started Aug 14 04:50:25 PM PDT 24
Finished Aug 14 04:51:14 PM PDT 24
Peak memory 183404 kb
Host smart-268b6c68-8e90-4cda-8e65-0e66b8f4b44d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117383518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2117383518
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.756201939
Short name T355
Test name
Test status
Simulation time 9141063887 ps
CPU time 5.06 seconds
Started Aug 14 04:50:34 PM PDT 24
Finished Aug 14 04:50:39 PM PDT 24
Peak memory 183516 kb
Host smart-83a5f5d9-ba5f-489a-a1f2-ca41743e49a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756201939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.756201939
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.4044201925
Short name T25
Test name
Test status
Simulation time 296653087753 ps
CPU time 365.94 seconds
Started Aug 14 04:50:33 PM PDT 24
Finished Aug 14 04:56:39 PM PDT 24
Peak memory 191776 kb
Host smart-5694dcf6-4534-4420-a618-050ffe3399b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044201925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.4044201925
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3550198833
Short name T334
Test name
Test status
Simulation time 706933256504 ps
CPU time 218.26 seconds
Started Aug 14 04:50:33 PM PDT 24
Finished Aug 14 04:54:12 PM PDT 24
Peak memory 191840 kb
Host smart-0e68b0d0-a12e-4744-a104-6a6d3fd0aab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550198833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3550198833
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1720048744
Short name T192
Test name
Test status
Simulation time 81673860787 ps
CPU time 138.07 seconds
Started Aug 14 04:50:36 PM PDT 24
Finished Aug 14 04:52:54 PM PDT 24
Peak memory 191776 kb
Host smart-692dd8f5-dfe4-497d-be78-d6ed67628e4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720048744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1720048744
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2572844786
Short name T310
Test name
Test status
Simulation time 46270837530 ps
CPU time 278.49 seconds
Started Aug 14 04:50:33 PM PDT 24
Finished Aug 14 04:55:12 PM PDT 24
Peak memory 191832 kb
Host smart-24067b01-d414-4009-a994-9d09dc77c20d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572844786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2572844786
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3215688722
Short name T458
Test name
Test status
Simulation time 113604732068 ps
CPU time 129.25 seconds
Started Aug 14 04:50:33 PM PDT 24
Finished Aug 14 04:52:43 PM PDT 24
Peak memory 183492 kb
Host smart-938697ef-2fe7-458f-ba99-81010fc2ce52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215688722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3215688722
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.797223345
Short name T278
Test name
Test status
Simulation time 619901474477 ps
CPU time 333.32 seconds
Started Aug 14 04:48:54 PM PDT 24
Finished Aug 14 04:54:28 PM PDT 24
Peak memory 183564 kb
Host smart-abd3b3ec-4f58-4357-ac14-f344c24fe250
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797223345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.797223345
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.4205741846
Short name T402
Test name
Test status
Simulation time 181956952385 ps
CPU time 68.3 seconds
Started Aug 14 04:48:51 PM PDT 24
Finished Aug 14 04:49:59 PM PDT 24
Peak memory 183592 kb
Host smart-7e20fb72-666f-4954-bdb4-68a1396c2e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205741846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.4205741846
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3270020808
Short name T118
Test name
Test status
Simulation time 151469177867 ps
CPU time 1180.53 seconds
Started Aug 14 04:48:56 PM PDT 24
Finished Aug 14 05:08:37 PM PDT 24
Peak memory 191744 kb
Host smart-aa025b7e-5312-4a11-83a2-45615c609ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270020808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3270020808
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.4289167630
Short name T253
Test name
Test status
Simulation time 31699793874 ps
CPU time 27.78 seconds
Started Aug 14 04:50:34 PM PDT 24
Finished Aug 14 04:51:02 PM PDT 24
Peak memory 183608 kb
Host smart-a0dd0e55-2ab4-4694-99dc-1755f97a3d8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289167630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4289167630
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3216404459
Short name T99
Test name
Test status
Simulation time 516153887136 ps
CPU time 1044.64 seconds
Started Aug 14 04:50:32 PM PDT 24
Finished Aug 14 05:07:57 PM PDT 24
Peak memory 191816 kb
Host smart-87938c16-22e0-4677-8380-37fc7fcb8d1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216404459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3216404459
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1032880185
Short name T335
Test name
Test status
Simulation time 17450492254 ps
CPU time 14.52 seconds
Started Aug 14 04:50:36 PM PDT 24
Finished Aug 14 04:50:51 PM PDT 24
Peak memory 183580 kb
Host smart-fa09498c-3a94-49f1-a717-5f000bcd837d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032880185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1032880185
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.461341404
Short name T345
Test name
Test status
Simulation time 176064311994 ps
CPU time 1553.45 seconds
Started Aug 14 04:50:32 PM PDT 24
Finished Aug 14 05:16:26 PM PDT 24
Peak memory 183520 kb
Host smart-76805b13-b2fe-46d2-8d95-f916269ff3c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461341404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.461341404
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2030232354
Short name T8
Test name
Test status
Simulation time 301484599628 ps
CPU time 209 seconds
Started Aug 14 04:50:33 PM PDT 24
Finished Aug 14 04:54:03 PM PDT 24
Peak memory 191732 kb
Host smart-bca75779-2aef-4bde-8914-3ebf2814d586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030232354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2030232354
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1328800281
Short name T232
Test name
Test status
Simulation time 320628911066 ps
CPU time 128.76 seconds
Started Aug 14 04:50:33 PM PDT 24
Finished Aug 14 04:52:42 PM PDT 24
Peak memory 191788 kb
Host smart-974a04d0-f81f-4dbc-a2c6-fcf4e67e0a5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328800281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1328800281
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2896852239
Short name T242
Test name
Test status
Simulation time 392262134321 ps
CPU time 384.83 seconds
Started Aug 14 04:50:34 PM PDT 24
Finished Aug 14 04:56:59 PM PDT 24
Peak memory 191884 kb
Host smart-0d62df81-40b8-4ac9-adc2-02a98c6b49b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896852239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2896852239
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1997747456
Short name T307
Test name
Test status
Simulation time 1080775847213 ps
CPU time 637.83 seconds
Started Aug 14 04:48:50 PM PDT 24
Finished Aug 14 04:59:29 PM PDT 24
Peak memory 183560 kb
Host smart-d3130d4e-35c1-49ad-a228-9db761e6efbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997747456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1997747456
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.422095146
Short name T379
Test name
Test status
Simulation time 182289079381 ps
CPU time 62.29 seconds
Started Aug 14 04:48:51 PM PDT 24
Finished Aug 14 04:49:53 PM PDT 24
Peak memory 183604 kb
Host smart-67f34182-b840-472a-8092-5289fb9813df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422095146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.422095146
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.1646368623
Short name T92
Test name
Test status
Simulation time 386405830226 ps
CPU time 840.89 seconds
Started Aug 14 04:48:52 PM PDT 24
Finished Aug 14 05:02:53 PM PDT 24
Peak memory 191712 kb
Host smart-62c81029-a7f4-4967-9a27-c2560521adf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646368623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1646368623
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2779141648
Short name T425
Test name
Test status
Simulation time 27519021976 ps
CPU time 306.02 seconds
Started Aug 14 04:48:51 PM PDT 24
Finished Aug 14 04:53:58 PM PDT 24
Peak memory 183532 kb
Host smart-26c9a5a9-d580-4a29-8111-ef4fc7802d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779141648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2779141648
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1642452674
Short name T55
Test name
Test status
Simulation time 100904335 ps
CPU time 0.59 seconds
Started Aug 14 04:48:53 PM PDT 24
Finished Aug 14 04:48:54 PM PDT 24
Peak memory 183208 kb
Host smart-47777ee4-b539-4153-9633-78d3db2c69ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642452674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1642452674
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.1369693053
Short name T218
Test name
Test status
Simulation time 58446343610 ps
CPU time 196.96 seconds
Started Aug 14 04:50:34 PM PDT 24
Finished Aug 14 04:53:51 PM PDT 24
Peak memory 194748 kb
Host smart-c004154a-d8aa-4bdb-8130-7bbcaac70805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369693053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1369693053
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3932068146
Short name T440
Test name
Test status
Simulation time 34281060640 ps
CPU time 165.9 seconds
Started Aug 14 04:50:33 PM PDT 24
Finished Aug 14 04:53:19 PM PDT 24
Peak memory 183504 kb
Host smart-9af2aed3-33da-4443-9dfa-fd3cf4521d90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932068146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3932068146
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3874453782
Short name T328
Test name
Test status
Simulation time 28098447552 ps
CPU time 32.16 seconds
Started Aug 14 04:50:34 PM PDT 24
Finished Aug 14 04:51:06 PM PDT 24
Peak memory 183620 kb
Host smart-75b560c6-77e3-4364-bb44-7558fc4a11e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874453782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3874453782
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3876230265
Short name T172
Test name
Test status
Simulation time 312274306249 ps
CPU time 224.83 seconds
Started Aug 14 04:50:43 PM PDT 24
Finished Aug 14 04:54:28 PM PDT 24
Peak memory 191820 kb
Host smart-f44a991d-2577-44c3-8d5c-7ca767a988c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876230265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3876230265
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3727778295
Short name T316
Test name
Test status
Simulation time 491235991400 ps
CPU time 863.54 seconds
Started Aug 14 04:50:46 PM PDT 24
Finished Aug 14 05:05:10 PM PDT 24
Peak memory 191632 kb
Host smart-f52d12df-f445-4e31-adb0-bf4e42674afa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727778295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3727778295
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1760023701
Short name T135
Test name
Test status
Simulation time 368513481471 ps
CPU time 242.37 seconds
Started Aug 14 04:50:46 PM PDT 24
Finished Aug 14 04:54:49 PM PDT 24
Peak memory 191708 kb
Host smart-6587d327-eabe-4fbd-9f50-05ccd4cfaabb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760023701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1760023701
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3353377895
Short name T196
Test name
Test status
Simulation time 1197292410653 ps
CPU time 658.15 seconds
Started Aug 14 04:48:53 PM PDT 24
Finished Aug 14 04:59:51 PM PDT 24
Peak memory 183492 kb
Host smart-a058b1f6-73ff-43d8-8c1c-0308d96d1f8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353377895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3353377895
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1266722290
Short name T23
Test name
Test status
Simulation time 71102165448 ps
CPU time 106.56 seconds
Started Aug 14 04:48:53 PM PDT 24
Finished Aug 14 04:50:40 PM PDT 24
Peak memory 183596 kb
Host smart-416c1d26-6212-4563-828a-639a6a9a5ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266722290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1266722290
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.729597198
Short name T257
Test name
Test status
Simulation time 35495473065 ps
CPU time 45.93 seconds
Started Aug 14 04:48:53 PM PDT 24
Finished Aug 14 04:49:39 PM PDT 24
Peak memory 183448 kb
Host smart-10adb450-152f-4d99-be45-6d53249274ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729597198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.729597198
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3609549425
Short name T333
Test name
Test status
Simulation time 161620791544 ps
CPU time 136.91 seconds
Started Aug 14 04:48:50 PM PDT 24
Finished Aug 14 04:51:07 PM PDT 24
Peak memory 183516 kb
Host smart-db7d6025-c873-4205-b513-d1d93e130732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609549425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3609549425
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.935635697
Short name T385
Test name
Test status
Simulation time 181913588025 ps
CPU time 285.44 seconds
Started Aug 14 04:48:52 PM PDT 24
Finished Aug 14 04:53:38 PM PDT 24
Peak memory 191792 kb
Host smart-a738d061-d7cb-4689-a0af-c82066cedf3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935635697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
935635697
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.669007950
Short name T37
Test name
Test status
Simulation time 2426768158 ps
CPU time 21.47 seconds
Started Aug 14 04:48:54 PM PDT 24
Finished Aug 14 04:49:15 PM PDT 24
Peak memory 198308 kb
Host smart-d7e80293-e53a-4bcf-8874-5e3a62438c20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669007950 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.669007950
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.4174097945
Short name T283
Test name
Test status
Simulation time 36957420368 ps
CPU time 70.42 seconds
Started Aug 14 04:50:43 PM PDT 24
Finished Aug 14 04:51:54 PM PDT 24
Peak memory 191840 kb
Host smart-f6346ee9-03f7-4a5b-849d-767dad50c6e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174097945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.4174097945
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3904494141
Short name T323
Test name
Test status
Simulation time 673217395617 ps
CPU time 473.5 seconds
Started Aug 14 04:50:41 PM PDT 24
Finished Aug 14 04:58:35 PM PDT 24
Peak memory 191724 kb
Host smart-08d96d1e-b526-4a7f-9b4c-fcb2918097cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904494141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3904494141
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1824750971
Short name T190
Test name
Test status
Simulation time 56392141232 ps
CPU time 1478.61 seconds
Started Aug 14 04:50:41 PM PDT 24
Finished Aug 14 05:15:20 PM PDT 24
Peak memory 191824 kb
Host smart-1916f2e1-fa32-4814-bd61-518802c8b1cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824750971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1824750971
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1396849023
Short name T244
Test name
Test status
Simulation time 114178713008 ps
CPU time 166.01 seconds
Started Aug 14 04:50:41 PM PDT 24
Finished Aug 14 04:53:28 PM PDT 24
Peak memory 191804 kb
Host smart-1eb46d50-ea8d-4cd3-b1e2-d984534b1a01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396849023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1396849023
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3611270579
Short name T294
Test name
Test status
Simulation time 112468056739 ps
CPU time 58.79 seconds
Started Aug 14 04:50:41 PM PDT 24
Finished Aug 14 04:51:40 PM PDT 24
Peak memory 183600 kb
Host smart-bc7943b2-e69a-45f0-b1fe-e58079383be3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611270579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3611270579
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.427774218
Short name T195
Test name
Test status
Simulation time 162281093721 ps
CPU time 972.26 seconds
Started Aug 14 04:50:42 PM PDT 24
Finished Aug 14 05:06:54 PM PDT 24
Peak memory 191716 kb
Host smart-884df4e7-1326-400a-a482-38cba916e345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427774218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.427774218
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3999440026
Short name T366
Test name
Test status
Simulation time 27601597811 ps
CPU time 49.16 seconds
Started Aug 14 04:50:44 PM PDT 24
Finished Aug 14 04:51:33 PM PDT 24
Peak memory 183608 kb
Host smart-fa4938f3-4eab-46ce-9b30-5537f3d8f0c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999440026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3999440026
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.4165081550
Short name T198
Test name
Test status
Simulation time 553571231153 ps
CPU time 2881.07 seconds
Started Aug 14 04:50:41 PM PDT 24
Finished Aug 14 05:38:42 PM PDT 24
Peak memory 191720 kb
Host smart-1d952f3c-1388-47c0-b323-cf7885ee9c57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165081550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4165081550
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1112935631
Short name T22
Test name
Test status
Simulation time 287505063828 ps
CPU time 518.29 seconds
Started Aug 14 04:48:56 PM PDT 24
Finished Aug 14 04:57:34 PM PDT 24
Peak memory 183504 kb
Host smart-c2dd5931-faae-4107-8e6e-c32e61e30ec1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112935631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1112935631
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1504494419
Short name T415
Test name
Test status
Simulation time 106595219362 ps
CPU time 166.88 seconds
Started Aug 14 04:48:50 PM PDT 24
Finished Aug 14 04:51:37 PM PDT 24
Peak memory 183580 kb
Host smart-a1c49262-69b7-4b3c-b567-1e92acc32fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504494419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1504494419
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1634193697
Short name T358
Test name
Test status
Simulation time 6790896519 ps
CPU time 50.68 seconds
Started Aug 14 04:48:52 PM PDT 24
Finished Aug 14 04:49:43 PM PDT 24
Peak memory 183680 kb
Host smart-a0c4bbda-8fcf-4e36-88f0-7bac44924cfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634193697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1634193697
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1279189770
Short name T4
Test name
Test status
Simulation time 72703235774 ps
CPU time 163.04 seconds
Started Aug 14 04:48:52 PM PDT 24
Finished Aug 14 04:51:36 PM PDT 24
Peak memory 183548 kb
Host smart-f8574977-c756-4af7-bf72-fa64b26783fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279189770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1279189770
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.781855584
Short name T57
Test name
Test status
Simulation time 163070420 ps
CPU time 0.53 seconds
Started Aug 14 04:48:56 PM PDT 24
Finished Aug 14 04:48:57 PM PDT 24
Peak memory 183192 kb
Host smart-681ee696-37fa-4e1a-bb42-fb2786d2edcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781855584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
781855584
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2759422886
Short name T35
Test name
Test status
Simulation time 1910652367 ps
CPU time 22.17 seconds
Started Aug 14 04:48:50 PM PDT 24
Finished Aug 14 04:49:12 PM PDT 24
Peak memory 198180 kb
Host smart-a833e5c6-4aa3-426a-a344-7d537010481d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759422886 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2759422886
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.3727521920
Short name T299
Test name
Test status
Simulation time 81438014248 ps
CPU time 187.05 seconds
Started Aug 14 04:50:59 PM PDT 24
Finished Aug 14 04:54:06 PM PDT 24
Peak memory 191752 kb
Host smart-90fd7048-7c05-4c54-95f6-6ef5cda6428f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727521920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3727521920
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.4137860722
Short name T248
Test name
Test status
Simulation time 62050018856 ps
CPU time 53.81 seconds
Started Aug 14 04:50:50 PM PDT 24
Finished Aug 14 04:51:44 PM PDT 24
Peak memory 183520 kb
Host smart-b89cc687-6fbb-4ec5-8699-0951b55248a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137860722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4137860722
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3032960770
Short name T243
Test name
Test status
Simulation time 8582789717 ps
CPU time 14.49 seconds
Started Aug 14 04:50:52 PM PDT 24
Finished Aug 14 04:51:06 PM PDT 24
Peak memory 191664 kb
Host smart-68b5be70-b268-420e-8c7f-a51a7e9810ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032960770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3032960770
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.507522693
Short name T264
Test name
Test status
Simulation time 86408447513 ps
CPU time 164.94 seconds
Started Aug 14 04:50:50 PM PDT 24
Finished Aug 14 04:53:35 PM PDT 24
Peak memory 191840 kb
Host smart-192ecbab-0e91-431c-9a4c-729b9626a5f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507522693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.507522693
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2303944785
Short name T449
Test name
Test status
Simulation time 28972362041 ps
CPU time 320.47 seconds
Started Aug 14 04:50:51 PM PDT 24
Finished Aug 14 04:56:12 PM PDT 24
Peak memory 183588 kb
Host smart-9687cd45-1dc1-4ffb-bc43-ff6d789c33a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303944785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2303944785
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.784638252
Short name T150
Test name
Test status
Simulation time 59429687129 ps
CPU time 771.43 seconds
Started Aug 14 04:50:50 PM PDT 24
Finished Aug 14 05:03:41 PM PDT 24
Peak memory 191804 kb
Host smart-3f92d30c-7348-4967-aee3-70e158556cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784638252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.784638252
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.4059683365
Short name T179
Test name
Test status
Simulation time 588300867013 ps
CPU time 427.52 seconds
Started Aug 14 04:50:51 PM PDT 24
Finished Aug 14 04:57:59 PM PDT 24
Peak memory 191832 kb
Host smart-c1106108-acd1-40a5-95d4-92b6fd2b4439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059683365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.4059683365
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2556355085
Short name T157
Test name
Test status
Simulation time 592710105994 ps
CPU time 392.19 seconds
Started Aug 14 04:50:50 PM PDT 24
Finished Aug 14 04:57:22 PM PDT 24
Peak memory 191792 kb
Host smart-54e2c411-9994-4e03-a0e5-d26bcfd512ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556355085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2556355085
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2673850506
Short name T322
Test name
Test status
Simulation time 302199037180 ps
CPU time 70.71 seconds
Started Aug 14 04:50:58 PM PDT 24
Finished Aug 14 04:52:09 PM PDT 24
Peak memory 183444 kb
Host smart-462ec67e-6360-404c-891a-1b5a5f39146d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673850506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2673850506
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.783878934
Short name T424
Test name
Test status
Simulation time 299017115641 ps
CPU time 223.14 seconds
Started Aug 14 04:48:53 PM PDT 24
Finished Aug 14 04:52:36 PM PDT 24
Peak memory 183532 kb
Host smart-20c6ffe1-7399-4dbc-8f50-3e6a59e42efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783878934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.783878934
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1731902262
Short name T408
Test name
Test status
Simulation time 332401420195 ps
CPU time 116.17 seconds
Started Aug 14 04:48:57 PM PDT 24
Finished Aug 14 04:50:53 PM PDT 24
Peak memory 183512 kb
Host smart-b824327b-668b-4da2-8d6b-ac55cecdff8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731902262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1731902262
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.3763973959
Short name T311
Test name
Test status
Simulation time 282432761730 ps
CPU time 1411.51 seconds
Started Aug 14 04:50:59 PM PDT 24
Finished Aug 14 05:14:31 PM PDT 24
Peak memory 191804 kb
Host smart-c5fefc07-ae32-48fc-8aa3-3058145087d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763973959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3763973959
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3963771689
Short name T331
Test name
Test status
Simulation time 75265174596 ps
CPU time 136.03 seconds
Started Aug 14 04:51:01 PM PDT 24
Finished Aug 14 04:53:17 PM PDT 24
Peak memory 191720 kb
Host smart-907da42c-1c21-467a-9952-895b1ccf2e18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963771689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3963771689
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3877744605
Short name T446
Test name
Test status
Simulation time 300130677191 ps
CPU time 491.74 seconds
Started Aug 14 04:51:00 PM PDT 24
Finished Aug 14 04:59:11 PM PDT 24
Peak memory 191832 kb
Host smart-3a8a6f43-7967-4818-b36b-ce5d0c0fd1d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877744605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3877744605
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2906335075
Short name T133
Test name
Test status
Simulation time 111025476872 ps
CPU time 99.09 seconds
Started Aug 14 04:51:00 PM PDT 24
Finished Aug 14 04:52:39 PM PDT 24
Peak memory 191764 kb
Host smart-966ce4fa-4052-4359-bd52-cabab14d78f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906335075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2906335075
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3492272728
Short name T10
Test name
Test status
Simulation time 68903772311 ps
CPU time 137.21 seconds
Started Aug 14 04:50:59 PM PDT 24
Finished Aug 14 04:53:16 PM PDT 24
Peak memory 191788 kb
Host smart-659253a4-a857-479b-8bd1-39d293f635c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492272728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3492272728
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3524244630
Short name T215
Test name
Test status
Simulation time 40784506991 ps
CPU time 749.57 seconds
Started Aug 14 04:51:02 PM PDT 24
Finished Aug 14 05:03:31 PM PDT 24
Peak memory 191704 kb
Host smart-a3063384-07e1-4b6e-94c8-ae03707f35be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524244630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3524244630
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2727974375
Short name T263
Test name
Test status
Simulation time 158347251455 ps
CPU time 265.25 seconds
Started Aug 14 04:51:01 PM PDT 24
Finished Aug 14 04:55:27 PM PDT 24
Peak memory 191704 kb
Host smart-c8f99132-2805-4ec9-800f-9acf46aec712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727974375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2727974375
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3957902368
Short name T454
Test name
Test status
Simulation time 106400105709 ps
CPU time 123.18 seconds
Started Aug 14 04:48:53 PM PDT 24
Finished Aug 14 04:50:56 PM PDT 24
Peak memory 183592 kb
Host smart-3552f15a-6c81-4e85-a41c-34180e3f83c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957902368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3957902368
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2775815146
Short name T365
Test name
Test status
Simulation time 74092824147 ps
CPU time 15.49 seconds
Started Aug 14 04:48:55 PM PDT 24
Finished Aug 14 04:49:10 PM PDT 24
Peak memory 183588 kb
Host smart-7adccccd-1f89-4442-9bb4-11f827427354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775815146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2775815146
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.700791435
Short name T239
Test name
Test status
Simulation time 30683094281 ps
CPU time 186.08 seconds
Started Aug 14 04:48:52 PM PDT 24
Finished Aug 14 04:51:59 PM PDT 24
Peak memory 183572 kb
Host smart-ea7bf1ab-8597-43c5-8525-ef338e6acf02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700791435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.700791435
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.1318278977
Short name T45
Test name
Test status
Simulation time 468513759306 ps
CPU time 499.05 seconds
Started Aug 14 04:51:00 PM PDT 24
Finished Aug 14 04:59:19 PM PDT 24
Peak memory 191724 kb
Host smart-ee110ee7-fdfe-4c41-9ee6-2ed906061a96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318278977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1318278977
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.4155822270
Short name T319
Test name
Test status
Simulation time 22750907177 ps
CPU time 187.85 seconds
Started Aug 14 04:51:08 PM PDT 24
Finished Aug 14 04:54:16 PM PDT 24
Peak memory 191712 kb
Host smart-bf1af966-7703-4714-944e-d62fe6cc68a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155822270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4155822270
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2189427412
Short name T3
Test name
Test status
Simulation time 147624302803 ps
CPU time 282.3 seconds
Started Aug 14 04:51:08 PM PDT 24
Finished Aug 14 04:55:51 PM PDT 24
Peak memory 183588 kb
Host smart-ccb65072-5e26-4bb5-9192-8de051c18b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189427412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2189427412
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2781697573
Short name T120
Test name
Test status
Simulation time 797061249431 ps
CPU time 354.83 seconds
Started Aug 14 04:51:09 PM PDT 24
Finished Aug 14 04:57:04 PM PDT 24
Peak memory 191820 kb
Host smart-d2b65913-8b51-40ec-9ded-7c4fafe78849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781697573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2781697573
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2414426795
Short name T353
Test name
Test status
Simulation time 55188876722 ps
CPU time 121.58 seconds
Started Aug 14 04:51:08 PM PDT 24
Finished Aug 14 04:53:10 PM PDT 24
Peak memory 191840 kb
Host smart-b541842f-2ccc-4040-aead-e53535eaea8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414426795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2414426795
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1887458053
Short name T206
Test name
Test status
Simulation time 231347298831 ps
CPU time 359.39 seconds
Started Aug 14 04:48:37 PM PDT 24
Finished Aug 14 04:54:36 PM PDT 24
Peak memory 183596 kb
Host smart-89e71d7f-8ab1-4433-ac64-d425cbd8df11
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887458053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1887458053
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3359657774
Short name T1
Test name
Test status
Simulation time 321352721156 ps
CPU time 131.17 seconds
Started Aug 14 04:48:28 PM PDT 24
Finished Aug 14 04:50:40 PM PDT 24
Peak memory 183256 kb
Host smart-1c5ee53b-55c8-42fc-bd02-86bbe7aef9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359657774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3359657774
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.818572680
Short name T347
Test name
Test status
Simulation time 297887833211 ps
CPU time 283 seconds
Started Aug 14 04:48:24 PM PDT 24
Finished Aug 14 04:53:07 PM PDT 24
Peak memory 191716 kb
Host smart-c02460a4-528b-41da-a507-f27c9c6c7f4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818572680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.818572680
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2136333800
Short name T388
Test name
Test status
Simulation time 207941273 ps
CPU time 0.59 seconds
Started Aug 14 04:48:32 PM PDT 24
Finished Aug 14 04:48:32 PM PDT 24
Peak memory 183200 kb
Host smart-4071499e-7d87-471a-999e-71dc3b1477d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136333800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2136333800
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1256024393
Short name T18
Test name
Test status
Simulation time 257845699 ps
CPU time 0.81 seconds
Started Aug 14 04:48:29 PM PDT 24
Finished Aug 14 04:48:31 PM PDT 24
Peak memory 214072 kb
Host smart-392ab7b4-6686-4d70-9cc1-07dcd534f762
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256024393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1256024393
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1571230144
Short name T404
Test name
Test status
Simulation time 36892097 ps
CPU time 0.55 seconds
Started Aug 14 04:48:32 PM PDT 24
Finished Aug 14 04:48:32 PM PDT 24
Peak memory 183252 kb
Host smart-13188081-400f-423c-8e88-b4c2c078c747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571230144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1571230144
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.3270671490
Short name T39
Test name
Test status
Simulation time 3838366552 ps
CPU time 33.19 seconds
Started Aug 14 04:48:29 PM PDT 24
Finished Aug 14 04:49:03 PM PDT 24
Peak memory 198252 kb
Host smart-103194bb-28d7-4d35-9efc-652e5c8940bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270671490 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.3270671490
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3604251446
Short name T420
Test name
Test status
Simulation time 103675087902 ps
CPU time 85.79 seconds
Started Aug 14 04:49:01 PM PDT 24
Finished Aug 14 04:50:27 PM PDT 24
Peak memory 183504 kb
Host smart-1056d8ce-7542-4a1b-ad7e-585cbac4a68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604251446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3604251446
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.784200886
Short name T422
Test name
Test status
Simulation time 148709512525 ps
CPU time 59.8 seconds
Started Aug 14 04:48:53 PM PDT 24
Finished Aug 14 04:49:53 PM PDT 24
Peak memory 183436 kb
Host smart-acb6d636-496c-4a8f-8d38-2599e3f2b68c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784200886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.784200886
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2026713789
Short name T313
Test name
Test status
Simulation time 52622821741 ps
CPU time 111.43 seconds
Started Aug 14 04:49:01 PM PDT 24
Finished Aug 14 04:50:52 PM PDT 24
Peak memory 191816 kb
Host smart-5b813c28-4555-41cb-af2d-ad159fd0d339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026713789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2026713789
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1369155011
Short name T350
Test name
Test status
Simulation time 161974137621 ps
CPU time 275.56 seconds
Started Aug 14 04:49:03 PM PDT 24
Finished Aug 14 04:53:38 PM PDT 24
Peak memory 183588 kb
Host smart-140dcd05-b1dd-4330-ad4d-130894dd9745
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369155011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1369155011
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.824413096
Short name T409
Test name
Test status
Simulation time 572811341473 ps
CPU time 83.57 seconds
Started Aug 14 04:49:01 PM PDT 24
Finished Aug 14 04:50:24 PM PDT 24
Peak memory 183600 kb
Host smart-ca302653-dcfa-4fb2-9ff2-4edf29f3ecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824413096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.824413096
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3679176940
Short name T147
Test name
Test status
Simulation time 42892140545 ps
CPU time 78.75 seconds
Started Aug 14 04:48:59 PM PDT 24
Finished Aug 14 04:50:18 PM PDT 24
Peak memory 183600 kb
Host smart-51699900-2124-438c-9a3a-dd9d45bfbbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679176940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3679176940
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.257926723
Short name T287
Test name
Test status
Simulation time 5859296096447 ps
CPU time 1879.84 seconds
Started Aug 14 04:49:00 PM PDT 24
Finished Aug 14 05:20:20 PM PDT 24
Peak memory 183504 kb
Host smart-2eb51448-c672-4ea4-8b2b-7c8c30ed41f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257926723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.257926723
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.540029854
Short name T372
Test name
Test status
Simulation time 95969064806 ps
CPU time 124.06 seconds
Started Aug 14 04:49:01 PM PDT 24
Finished Aug 14 04:51:05 PM PDT 24
Peak memory 183588 kb
Host smart-4cac67e8-82e4-455c-948b-7ad770a7e9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540029854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.540029854
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2803613753
Short name T341
Test name
Test status
Simulation time 366582738587 ps
CPU time 186.33 seconds
Started Aug 14 04:48:59 PM PDT 24
Finished Aug 14 04:52:06 PM PDT 24
Peak memory 195364 kb
Host smart-3c621387-73df-4bf0-a85a-aa3fbe7858ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803613753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2803613753
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1056340255
Short name T21
Test name
Test status
Simulation time 38489811053 ps
CPU time 101.21 seconds
Started Aug 14 04:49:02 PM PDT 24
Finished Aug 14 04:50:43 PM PDT 24
Peak memory 183708 kb
Host smart-476dc05c-5b94-44cc-8811-6e091edc845b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056340255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1056340255
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2203841238
Short name T275
Test name
Test status
Simulation time 71695418825 ps
CPU time 35.33 seconds
Started Aug 14 04:49:03 PM PDT 24
Finished Aug 14 04:49:38 PM PDT 24
Peak memory 183588 kb
Host smart-551db5f3-47c4-4d90-9366-d88214aeaefa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203841238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2203841238
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1870959983
Short name T459
Test name
Test status
Simulation time 219597688563 ps
CPU time 83.14 seconds
Started Aug 14 04:49:00 PM PDT 24
Finished Aug 14 04:50:23 PM PDT 24
Peak memory 183532 kb
Host smart-324425ac-3723-468e-826b-e6aa8f5d7ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870959983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1870959983
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1786204076
Short name T89
Test name
Test status
Simulation time 129891561979 ps
CPU time 590.71 seconds
Started Aug 14 04:49:01 PM PDT 24
Finished Aug 14 04:58:52 PM PDT 24
Peak memory 191792 kb
Host smart-875936d2-1920-46d9-b99e-a429053c82cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786204076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1786204076
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.4177510127
Short name T381
Test name
Test status
Simulation time 92462153 ps
CPU time 0.67 seconds
Started Aug 14 04:49:03 PM PDT 24
Finished Aug 14 04:49:04 PM PDT 24
Peak memory 183216 kb
Host smart-fe7fe081-a96d-44b1-b5bd-79e02fd9f919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177510127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.4177510127
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2986735907
Short name T188
Test name
Test status
Simulation time 145655297997 ps
CPU time 697.39 seconds
Started Aug 14 04:49:12 PM PDT 24
Finished Aug 14 05:00:50 PM PDT 24
Peak memory 195680 kb
Host smart-e70295c1-ed5e-40db-a01a-32e682e62e33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986735907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2986735907
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2626383348
Short name T34
Test name
Test status
Simulation time 20631324808 ps
CPU time 17.69 seconds
Started Aug 14 04:49:11 PM PDT 24
Finished Aug 14 04:49:29 PM PDT 24
Peak memory 198124 kb
Host smart-8efe1ee0-7a29-4876-9412-355875f0f4cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626383348 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2626383348
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2470021766
Short name T293
Test name
Test status
Simulation time 716987197449 ps
CPU time 633.85 seconds
Started Aug 14 04:49:13 PM PDT 24
Finished Aug 14 04:59:47 PM PDT 24
Peak memory 183576 kb
Host smart-353d3163-0070-4450-a279-8f3f22dd0fe7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470021766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2470021766
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3938969610
Short name T418
Test name
Test status
Simulation time 894790780113 ps
CPU time 132.67 seconds
Started Aug 14 04:49:12 PM PDT 24
Finished Aug 14 04:51:24 PM PDT 24
Peak memory 183600 kb
Host smart-184638ad-f86c-411e-bba7-e673e0cb2fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938969610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3938969610
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3028982938
Short name T277
Test name
Test status
Simulation time 112493965814 ps
CPU time 225.13 seconds
Started Aug 14 04:49:09 PM PDT 24
Finished Aug 14 04:52:54 PM PDT 24
Peak memory 191824 kb
Host smart-8d181fd9-7a2d-4651-a48d-e1343202abe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028982938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3028982938
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3372185468
Short name T251
Test name
Test status
Simulation time 18244805564 ps
CPU time 8.73 seconds
Started Aug 14 04:49:10 PM PDT 24
Finished Aug 14 04:49:19 PM PDT 24
Peak memory 191804 kb
Host smart-82ea5a66-481c-4d20-a099-0b7a158df94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372185468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3372185468
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.417121691
Short name T308
Test name
Test status
Simulation time 470258021174 ps
CPU time 279.71 seconds
Started Aug 14 04:49:15 PM PDT 24
Finished Aug 14 04:53:54 PM PDT 24
Peak memory 183592 kb
Host smart-ba1d818f-6d5d-4821-9e2b-d9e2fe610df2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417121691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.417121691
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1693189527
Short name T414
Test name
Test status
Simulation time 25451529452 ps
CPU time 34.25 seconds
Started Aug 14 04:49:14 PM PDT 24
Finished Aug 14 04:49:48 PM PDT 24
Peak memory 183580 kb
Host smart-d5c01532-1d31-4cf1-ab7b-df1b3f84ef9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693189527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1693189527
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.163527987
Short name T339
Test name
Test status
Simulation time 33333101330 ps
CPU time 62.74 seconds
Started Aug 14 04:49:10 PM PDT 24
Finished Aug 14 04:50:13 PM PDT 24
Peak memory 183628 kb
Host smart-b0d3ca2a-e697-41b4-995b-5ccd381ef0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163527987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.163527987
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.331268989
Short name T201
Test name
Test status
Simulation time 414913626638 ps
CPU time 254.88 seconds
Started Aug 14 04:49:14 PM PDT 24
Finished Aug 14 04:53:29 PM PDT 24
Peak memory 183596 kb
Host smart-486636a9-72a9-4606-9c29-44c954054f60
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331268989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.331268989
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2550849148
Short name T430
Test name
Test status
Simulation time 149544032692 ps
CPU time 208.6 seconds
Started Aug 14 04:49:16 PM PDT 24
Finished Aug 14 04:52:44 PM PDT 24
Peak memory 183600 kb
Host smart-11964ad9-f279-46ce-a5ae-fd732d31d7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550849148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2550849148
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1606485913
Short name T295
Test name
Test status
Simulation time 181508125445 ps
CPU time 106.3 seconds
Started Aug 14 04:49:10 PM PDT 24
Finished Aug 14 04:50:57 PM PDT 24
Peak memory 183496 kb
Host smart-875c1d56-5911-49da-b92f-9e8160d51e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606485913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1606485913
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2218845771
Short name T272
Test name
Test status
Simulation time 611631330514 ps
CPU time 493.54 seconds
Started Aug 14 04:49:11 PM PDT 24
Finished Aug 14 04:57:25 PM PDT 24
Peak memory 196724 kb
Host smart-1ee65d91-1f16-4f52-9b8f-36f678b3e6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218845771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2218845771
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.865431000
Short name T456
Test name
Test status
Simulation time 10583959543 ps
CPU time 33.71 seconds
Started Aug 14 04:49:11 PM PDT 24
Finished Aug 14 04:49:45 PM PDT 24
Peak memory 198304 kb
Host smart-ee559a1e-aa9d-41a4-af66-22e17f68be1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865431000 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.865431000
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.895045065
Short name T412
Test name
Test status
Simulation time 154480985421 ps
CPU time 156.86 seconds
Started Aug 14 04:49:15 PM PDT 24
Finished Aug 14 04:51:52 PM PDT 24
Peak memory 183592 kb
Host smart-ba40a9a3-396a-4407-8ae7-41b0a669a082
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895045065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.895045065
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2074033459
Short name T394
Test name
Test status
Simulation time 132281739780 ps
CPU time 101.27 seconds
Started Aug 14 04:49:10 PM PDT 24
Finished Aug 14 04:50:52 PM PDT 24
Peak memory 183600 kb
Host smart-4a69eb66-18e0-4406-9fed-738351374a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074033459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2074033459
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.34016428
Short name T98
Test name
Test status
Simulation time 30444420012 ps
CPU time 41.34 seconds
Started Aug 14 04:49:11 PM PDT 24
Finished Aug 14 04:49:53 PM PDT 24
Peak memory 183492 kb
Host smart-179b6609-4096-4e10-902a-331d99c2a3a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34016428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.34016428
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3942853359
Short name T356
Test name
Test status
Simulation time 41248326103 ps
CPU time 19.53 seconds
Started Aug 14 04:49:11 PM PDT 24
Finished Aug 14 04:49:30 PM PDT 24
Peak memory 183588 kb
Host smart-4e48310f-9cd3-48ff-b9c8-a9d78a7620e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942853359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3942853359
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2242548247
Short name T410
Test name
Test status
Simulation time 63219790114 ps
CPU time 87.77 seconds
Started Aug 14 04:49:11 PM PDT 24
Finished Aug 14 04:50:39 PM PDT 24
Peak memory 183476 kb
Host smart-368671fd-beda-4b00-bfda-0c5682dfe7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242548247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2242548247
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.4235445622
Short name T131
Test name
Test status
Simulation time 256929917950 ps
CPU time 102.4 seconds
Started Aug 14 04:49:14 PM PDT 24
Finished Aug 14 04:50:57 PM PDT 24
Peak memory 191732 kb
Host smart-aa8a52c2-13ad-4431-b70e-57113387667d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235445622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.4235445622
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1897520565
Short name T378
Test name
Test status
Simulation time 88951667 ps
CPU time 0.6 seconds
Started Aug 14 04:49:11 PM PDT 24
Finished Aug 14 04:49:11 PM PDT 24
Peak memory 183164 kb
Host smart-e568a779-ca11-46f8-ade9-6696b441f513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897520565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1897520565
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2740636824
Short name T160
Test name
Test status
Simulation time 207309786422 ps
CPU time 88.84 seconds
Started Aug 14 04:49:11 PM PDT 24
Finished Aug 14 04:50:40 PM PDT 24
Peak memory 183660 kb
Host smart-3bb5abda-af32-4f94-9a03-02bf67e39581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740636824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2740636824
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.4247560888
Short name T203
Test name
Test status
Simulation time 31463438746 ps
CPU time 46.45 seconds
Started Aug 14 04:49:12 PM PDT 24
Finished Aug 14 04:49:58 PM PDT 24
Peak memory 183472 kb
Host smart-84905e31-9d8b-4d10-bc5c-00ea588190e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247560888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.4247560888
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.63889037
Short name T368
Test name
Test status
Simulation time 18004640519 ps
CPU time 25.12 seconds
Started Aug 14 04:49:15 PM PDT 24
Finished Aug 14 04:49:40 PM PDT 24
Peak memory 183436 kb
Host smart-23daba97-7f1f-4649-b444-91d50a1b11ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63889037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.63889037
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2542916684
Short name T267
Test name
Test status
Simulation time 151843126661 ps
CPU time 634.08 seconds
Started Aug 14 04:49:15 PM PDT 24
Finished Aug 14 04:59:49 PM PDT 24
Peak memory 191628 kb
Host smart-59ccab9f-74a6-4132-9443-3030cee87f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542916684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2542916684
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2732970193
Short name T389
Test name
Test status
Simulation time 19335108 ps
CPU time 0.53 seconds
Started Aug 14 04:49:12 PM PDT 24
Finished Aug 14 04:49:13 PM PDT 24
Peak memory 183196 kb
Host smart-0710237a-3b0e-403f-aa93-8bf259a1671c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732970193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2732970193
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.442350668
Short name T457
Test name
Test status
Simulation time 295896177155 ps
CPU time 190.91 seconds
Started Aug 14 04:48:30 PM PDT 24
Finished Aug 14 04:51:41 PM PDT 24
Peak memory 183588 kb
Host smart-a3b3b32a-4fe7-4bb6-884b-a0446972eace
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442350668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.442350668
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1495231086
Short name T455
Test name
Test status
Simulation time 263753199270 ps
CPU time 206.78 seconds
Started Aug 14 04:48:29 PM PDT 24
Finished Aug 14 04:51:56 PM PDT 24
Peak memory 183504 kb
Host smart-f62f6b2d-3909-4013-b4cf-362f156a3f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495231086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1495231086
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.455157603
Short name T439
Test name
Test status
Simulation time 544066167350 ps
CPU time 561.86 seconds
Started Aug 14 04:48:31 PM PDT 24
Finished Aug 14 04:57:53 PM PDT 24
Peak memory 194464 kb
Host smart-055716a6-31b8-4bdc-8aa0-b53bbdc3f101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455157603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.455157603
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1711129262
Short name T16
Test name
Test status
Simulation time 272311912 ps
CPU time 0.97 seconds
Started Aug 14 04:48:29 PM PDT 24
Finished Aug 14 04:48:30 PM PDT 24
Peak memory 215024 kb
Host smart-7ca1122a-2ee8-4ac4-b591-3f9619b484ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711129262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1711129262
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.4259725368
Short name T337
Test name
Test status
Simulation time 8233279016 ps
CPU time 48.28 seconds
Started Aug 14 04:48:35 PM PDT 24
Finished Aug 14 04:49:24 PM PDT 24
Peak memory 198252 kb
Host smart-736a2743-ba05-4643-88ca-e72279f1ecfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259725368 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.4259725368
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1670768594
Short name T163
Test name
Test status
Simulation time 135183766982 ps
CPU time 227.98 seconds
Started Aug 14 04:49:12 PM PDT 24
Finished Aug 14 04:53:00 PM PDT 24
Peak memory 183548 kb
Host smart-f302d0b0-724a-4afd-b21a-f8cd211dd391
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670768594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1670768594
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2291642613
Short name T44
Test name
Test status
Simulation time 428491282446 ps
CPU time 164.67 seconds
Started Aug 14 04:49:14 PM PDT 24
Finished Aug 14 04:51:59 PM PDT 24
Peak memory 183528 kb
Host smart-88ef510f-a3bf-4d05-9aad-0fc5909d48f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291642613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2291642613
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2460020055
Short name T364
Test name
Test status
Simulation time 76494961756 ps
CPU time 352.52 seconds
Started Aug 14 04:49:11 PM PDT 24
Finished Aug 14 04:55:04 PM PDT 24
Peak memory 191840 kb
Host smart-3dbeee01-1e35-4f10-ab07-910144240c78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460020055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2460020055
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.1014453353
Short name T14
Test name
Test status
Simulation time 17745552723 ps
CPU time 36.48 seconds
Started Aug 14 04:49:15 PM PDT 24
Finished Aug 14 04:49:52 PM PDT 24
Peak memory 198292 kb
Host smart-f1caa90e-c8a2-469f-acfa-768d6b486876
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014453353 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.1014453353
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2936060732
Short name T249
Test name
Test status
Simulation time 248005604707 ps
CPU time 235.31 seconds
Started Aug 14 04:49:13 PM PDT 24
Finished Aug 14 04:53:08 PM PDT 24
Peak memory 183448 kb
Host smart-038ce4e6-ed79-44fe-b32e-12b1074a7a37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936060732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2936060732
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_random.4038257644
Short name T269
Test name
Test status
Simulation time 74991853197 ps
CPU time 327.03 seconds
Started Aug 14 04:49:12 PM PDT 24
Finished Aug 14 04:54:39 PM PDT 24
Peak memory 191816 kb
Host smart-9ef9b4c8-e6d1-47b4-b16b-7f4e9d483b0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038257644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.4038257644
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.446940557
Short name T43
Test name
Test status
Simulation time 26438386363 ps
CPU time 55.81 seconds
Started Aug 14 04:49:17 PM PDT 24
Finished Aug 14 04:50:13 PM PDT 24
Peak memory 195040 kb
Host smart-a7364a9c-da4f-437a-8815-b6f2b4e7187e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446940557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.446940557
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2109187515
Short name T96
Test name
Test status
Simulation time 1794650700135 ps
CPU time 1559.52 seconds
Started Aug 14 04:49:15 PM PDT 24
Finished Aug 14 05:15:14 PM PDT 24
Peak memory 191664 kb
Host smart-537170e2-7069-4d5f-9f67-ce29bd522fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109187515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2109187515
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2165075149
Short name T40
Test name
Test status
Simulation time 2899866312 ps
CPU time 22.01 seconds
Started Aug 14 04:49:16 PM PDT 24
Finished Aug 14 04:49:39 PM PDT 24
Peak memory 198288 kb
Host smart-a431f1e7-0650-4be1-b931-c7a91cd3a4d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165075149 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2165075149
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.740500259
Short name T281
Test name
Test status
Simulation time 141725110913 ps
CPU time 223.73 seconds
Started Aug 14 04:49:21 PM PDT 24
Finished Aug 14 04:53:05 PM PDT 24
Peak memory 183588 kb
Host smart-fa81266a-1bf8-457d-b50f-c11457812233
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740500259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.740500259
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3808270316
Short name T386
Test name
Test status
Simulation time 89039336446 ps
CPU time 115.99 seconds
Started Aug 14 04:49:20 PM PDT 24
Finished Aug 14 04:51:16 PM PDT 24
Peak memory 183520 kb
Host smart-6a3d49e1-66d2-48cb-8da7-eb025a3beb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808270316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3808270316
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2257759846
Short name T280
Test name
Test status
Simulation time 66104510781 ps
CPU time 67.34 seconds
Started Aug 14 04:49:20 PM PDT 24
Finished Aug 14 04:50:27 PM PDT 24
Peak memory 183572 kb
Host smart-4ce9a38a-16be-4555-8004-fe2dfaafcda9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257759846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2257759846
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2337125113
Short name T438
Test name
Test status
Simulation time 124418972 ps
CPU time 0.73 seconds
Started Aug 14 04:49:22 PM PDT 24
Finished Aug 14 04:49:23 PM PDT 24
Peak memory 183164 kb
Host smart-c11d3e1f-d2b1-443e-98f7-ac4544e7b40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337125113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2337125113
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.81870890
Short name T411
Test name
Test status
Simulation time 87690571661 ps
CPU time 156.9 seconds
Started Aug 14 04:49:24 PM PDT 24
Finished Aug 14 04:52:01 PM PDT 24
Peak memory 183568 kb
Host smart-fa2be993-86fc-49e4-b4db-1485ba0a4056
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81870890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.rv_timer_cfg_update_on_fly.81870890
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2923344415
Short name T377
Test name
Test status
Simulation time 516655709697 ps
CPU time 204 seconds
Started Aug 14 04:49:26 PM PDT 24
Finished Aug 14 04:52:50 PM PDT 24
Peak memory 183564 kb
Host smart-5cc88d08-f5bc-4878-84aa-f86aa7db7459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923344415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2923344415
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.669637283
Short name T314
Test name
Test status
Simulation time 72078636090 ps
CPU time 34.41 seconds
Started Aug 14 04:49:26 PM PDT 24
Finished Aug 14 04:50:00 PM PDT 24
Peak memory 183612 kb
Host smart-7c598717-9578-4817-828b-f09c43a54455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669637283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.669637283
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3074030394
Short name T216
Test name
Test status
Simulation time 132483229937 ps
CPU time 308.18 seconds
Started Aug 14 04:49:23 PM PDT 24
Finished Aug 14 04:54:32 PM PDT 24
Peak memory 195252 kb
Host smart-24096ade-d01c-4fa4-898b-d73a82a2c37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074030394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3074030394
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.396927062
Short name T393
Test name
Test status
Simulation time 113016210458 ps
CPU time 159.78 seconds
Started Aug 14 04:49:23 PM PDT 24
Finished Aug 14 04:52:02 PM PDT 24
Peak memory 183476 kb
Host smart-34f66e07-155f-41dd-92e2-90f20adce4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396927062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.396927062
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3441690411
Short name T106
Test name
Test status
Simulation time 628755354414 ps
CPU time 231.58 seconds
Started Aug 14 04:49:21 PM PDT 24
Finished Aug 14 04:53:13 PM PDT 24
Peak memory 191812 kb
Host smart-20ececd7-609e-45ef-b44e-c9a99def383b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441690411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3441690411
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3620763051
Short name T342
Test name
Test status
Simulation time 27879779949 ps
CPU time 37.22 seconds
Started Aug 14 04:49:23 PM PDT 24
Finished Aug 14 04:50:00 PM PDT 24
Peak memory 191812 kb
Host smart-02e5fc33-3e3e-49bc-b6df-29e5ede52df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620763051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3620763051
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2938330967
Short name T416
Test name
Test status
Simulation time 176505027466 ps
CPU time 293.2 seconds
Started Aug 14 04:49:26 PM PDT 24
Finished Aug 14 04:54:19 PM PDT 24
Peak memory 183564 kb
Host smart-60228eb5-5d49-42d4-9107-85faf30585b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938330967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2938330967
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2215703629
Short name T429
Test name
Test status
Simulation time 196680554568 ps
CPU time 281.65 seconds
Started Aug 14 04:49:26 PM PDT 24
Finished Aug 14 04:54:08 PM PDT 24
Peak memory 183624 kb
Host smart-1225fb81-49b0-4030-bc9c-52c5dd5ff00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215703629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2215703629
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.4197648769
Short name T285
Test name
Test status
Simulation time 96656029500 ps
CPU time 146.25 seconds
Started Aug 14 04:49:26 PM PDT 24
Finished Aug 14 04:51:52 PM PDT 24
Peak memory 183588 kb
Host smart-c78b143b-8f1f-427b-9b16-e04db24518fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197648769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4197648769
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2752959292
Short name T301
Test name
Test status
Simulation time 616742135972 ps
CPU time 584.49 seconds
Started Aug 14 04:49:20 PM PDT 24
Finished Aug 14 04:59:05 PM PDT 24
Peak memory 183616 kb
Host smart-c021d519-3cce-4d6c-a32d-88edb919e2f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752959292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2752959292
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3540075327
Short name T371
Test name
Test status
Simulation time 131054298821 ps
CPU time 109.77 seconds
Started Aug 14 04:49:23 PM PDT 24
Finished Aug 14 04:51:13 PM PDT 24
Peak memory 183512 kb
Host smart-51941ca8-b476-4d32-9f75-b51da851279e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540075327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3540075327
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3767547038
Short name T357
Test name
Test status
Simulation time 282393761290 ps
CPU time 150.33 seconds
Started Aug 14 04:49:22 PM PDT 24
Finished Aug 14 04:51:53 PM PDT 24
Peak memory 191796 kb
Host smart-6f4f0348-c9e0-4afa-a181-e699a1bd284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767547038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3767547038
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3489126728
Short name T177
Test name
Test status
Simulation time 234554166491 ps
CPU time 142.34 seconds
Started Aug 14 04:49:21 PM PDT 24
Finished Aug 14 04:51:43 PM PDT 24
Peak memory 183500 kb
Host smart-2a43c678-46fe-4b40-aa34-6a951944cc4b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489126728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3489126728
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3722871079
Short name T431
Test name
Test status
Simulation time 156444194425 ps
CPU time 123.07 seconds
Started Aug 14 04:49:27 PM PDT 24
Finished Aug 14 04:51:30 PM PDT 24
Peak memory 183632 kb
Host smart-3f9f58fe-9270-4e29-a80e-6e9dca92621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722871079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3722871079
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2394845469
Short name T443
Test name
Test status
Simulation time 161279353337 ps
CPU time 94.47 seconds
Started Aug 14 04:49:22 PM PDT 24
Finished Aug 14 04:50:57 PM PDT 24
Peak memory 183596 kb
Host smart-63258790-1886-4bc6-9c28-d9a234c2b657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394845469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2394845469
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.507673008
Short name T234
Test name
Test status
Simulation time 1520224523995 ps
CPU time 883.02 seconds
Started Aug 14 04:49:24 PM PDT 24
Finished Aug 14 05:04:07 PM PDT 24
Peak memory 191760 kb
Host smart-1167332b-495c-4d65-8054-ff0ff40a6eb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507673008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
507673008
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.3481855739
Short name T396
Test name
Test status
Simulation time 8325501710 ps
CPU time 38.12 seconds
Started Aug 14 04:49:21 PM PDT 24
Finished Aug 14 04:50:00 PM PDT 24
Peak memory 198296 kb
Host smart-5194b055-0320-4561-a93e-ceb5e1bc0270
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481855739 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.3481855739
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1423926196
Short name T132
Test name
Test status
Simulation time 2645679251 ps
CPU time 4.54 seconds
Started Aug 14 04:49:21 PM PDT 24
Finished Aug 14 04:49:26 PM PDT 24
Peak memory 183544 kb
Host smart-c5712440-8746-43f5-9005-f4b6dcb37120
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423926196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1423926196
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2573772035
Short name T41
Test name
Test status
Simulation time 106731321816 ps
CPU time 43.46 seconds
Started Aug 14 04:49:27 PM PDT 24
Finished Aug 14 04:50:10 PM PDT 24
Peak memory 183632 kb
Host smart-1634059a-5178-4744-993d-037f6ca03684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573772035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2573772035
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3159664047
Short name T116
Test name
Test status
Simulation time 153849746063 ps
CPU time 1731.27 seconds
Started Aug 14 04:49:23 PM PDT 24
Finished Aug 14 05:18:15 PM PDT 24
Peak memory 191688 kb
Host smart-d943c5c0-73a9-47ec-83df-0eb514318fb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159664047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3159664047
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2908006411
Short name T140
Test name
Test status
Simulation time 204347117236 ps
CPU time 74.58 seconds
Started Aug 14 04:49:21 PM PDT 24
Finished Aug 14 04:50:36 PM PDT 24
Peak memory 190776 kb
Host smart-ebb37aac-61f6-4eec-bac9-0090198dc0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908006411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2908006411
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.387283594
Short name T318
Test name
Test status
Simulation time 317008121210 ps
CPU time 486.84 seconds
Started Aug 14 04:49:21 PM PDT 24
Finished Aug 14 04:57:28 PM PDT 24
Peak memory 191916 kb
Host smart-9ba8e485-1170-46b7-abc8-9871a66fa295
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387283594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
387283594
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.3103884357
Short name T423
Test name
Test status
Simulation time 2448945555 ps
CPU time 12.77 seconds
Started Aug 14 04:49:21 PM PDT 24
Finished Aug 14 04:49:34 PM PDT 24
Peak memory 198308 kb
Host smart-8d16baf2-3ba2-4bc9-8b3c-b5a384b3315c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103884357 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.3103884357
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.999397574
Short name T109
Test name
Test status
Simulation time 524336454778 ps
CPU time 905.05 seconds
Started Aug 14 04:49:21 PM PDT 24
Finished Aug 14 05:04:26 PM PDT 24
Peak memory 183584 kb
Host smart-3aaef3a8-3873-43b8-834a-f9089d1f5f96
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999397574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.999397574
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.183070354
Short name T369
Test name
Test status
Simulation time 51295397 ps
CPU time 0.77 seconds
Started Aug 14 04:49:24 PM PDT 24
Finished Aug 14 04:49:25 PM PDT 24
Peak memory 183272 kb
Host smart-52015829-c773-4569-a9bc-8fb90c345c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183070354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.183070354
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3939189705
Short name T399
Test name
Test status
Simulation time 2697801670 ps
CPU time 23.7 seconds
Started Aug 14 04:49:30 PM PDT 24
Finished Aug 14 04:49:54 PM PDT 24
Peak memory 198180 kb
Host smart-34606af7-0629-4c58-9a8a-db06e2b733ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939189705 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3939189705
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2929135520
Short name T290
Test name
Test status
Simulation time 1071854522719 ps
CPU time 569.1 seconds
Started Aug 14 04:48:31 PM PDT 24
Finished Aug 14 04:58:00 PM PDT 24
Peak memory 183604 kb
Host smart-7aa78f6d-b2e6-47be-be03-1dd6551655c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929135520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2929135520
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.522210555
Short name T447
Test name
Test status
Simulation time 11919203909 ps
CPU time 16.29 seconds
Started Aug 14 04:48:30 PM PDT 24
Finished Aug 14 04:48:47 PM PDT 24
Peak memory 183432 kb
Host smart-9057d314-e629-4d81-aab5-82d1cba2bda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522210555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.522210555
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2831309799
Short name T128
Test name
Test status
Simulation time 274302950489 ps
CPU time 218.9 seconds
Started Aug 14 04:48:30 PM PDT 24
Finished Aug 14 04:52:09 PM PDT 24
Peak memory 183508 kb
Host smart-87df457d-f496-40c8-ba06-7c531d099fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831309799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2831309799
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2583848662
Short name T17
Test name
Test status
Simulation time 376562651 ps
CPU time 0.95 seconds
Started Aug 14 04:48:35 PM PDT 24
Finished Aug 14 04:48:36 PM PDT 24
Peak memory 215140 kb
Host smart-87462194-e134-44c3-a49f-2994497d4e74
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583848662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2583848662
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.841949886
Short name T219
Test name
Test status
Simulation time 69260104219 ps
CPU time 254.87 seconds
Started Aug 14 04:48:35 PM PDT 24
Finished Aug 14 04:52:50 PM PDT 24
Peak memory 195056 kb
Host smart-23196e32-dd9f-4e96-a74f-3b1869e6ef3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841949886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.841949886
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.428564841
Short name T123
Test name
Test status
Simulation time 36518993243 ps
CPU time 67.77 seconds
Started Aug 14 04:49:32 PM PDT 24
Finished Aug 14 04:50:40 PM PDT 24
Peak memory 183452 kb
Host smart-d84618f6-576b-492c-a077-0b4a7bd1da54
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428564841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.428564841
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.206732926
Short name T382
Test name
Test status
Simulation time 531522991900 ps
CPU time 72.17 seconds
Started Aug 14 04:49:32 PM PDT 24
Finished Aug 14 04:50:44 PM PDT 24
Peak memory 183424 kb
Host smart-2d28b9a8-defc-4983-b47b-7e4789a5438b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206732926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.206732926
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2868917813
Short name T276
Test name
Test status
Simulation time 9653617817 ps
CPU time 8.58 seconds
Started Aug 14 04:49:31 PM PDT 24
Finished Aug 14 04:49:39 PM PDT 24
Peak memory 183620 kb
Host smart-02c009a5-d780-4995-ba14-54bbf589e7ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868917813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2868917813
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1260884486
Short name T428
Test name
Test status
Simulation time 138704833029 ps
CPU time 225.38 seconds
Started Aug 14 04:49:29 PM PDT 24
Finished Aug 14 04:53:15 PM PDT 24
Peak memory 195060 kb
Host smart-6c726ec8-2671-44d3-960b-9f71098333c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260884486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1260884486
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2121507837
Short name T53
Test name
Test status
Simulation time 8969409650 ps
CPU time 15.72 seconds
Started Aug 14 04:49:31 PM PDT 24
Finished Aug 14 04:49:47 PM PDT 24
Peak memory 183536 kb
Host smart-35f93420-15a3-4734-a73b-9748163a9f15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121507837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2121507837
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.133572604
Short name T15
Test name
Test status
Simulation time 9695853459 ps
CPU time 20.48 seconds
Started Aug 14 04:49:34 PM PDT 24
Finished Aug 14 04:49:55 PM PDT 24
Peak memory 198296 kb
Host smart-47e48fa5-3a3d-4a46-8b9f-17cf1bc8e569
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133572604 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.133572604
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2424345985
Short name T442
Test name
Test status
Simulation time 6016652177 ps
CPU time 8.92 seconds
Started Aug 14 04:49:31 PM PDT 24
Finished Aug 14 04:49:40 PM PDT 24
Peak memory 183396 kb
Host smart-f5e02211-9f73-4571-b024-553b03e0d30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424345985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2424345985
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.4151233822
Short name T327
Test name
Test status
Simulation time 87824801388 ps
CPU time 150.75 seconds
Started Aug 14 04:49:32 PM PDT 24
Finished Aug 14 04:52:03 PM PDT 24
Peak memory 191728 kb
Host smart-87aa626c-3bda-44ac-9aec-7d603249889d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151233822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4151233822
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.225908370
Short name T384
Test name
Test status
Simulation time 68726230 ps
CPU time 0.63 seconds
Started Aug 14 04:49:30 PM PDT 24
Finished Aug 14 04:49:30 PM PDT 24
Peak memory 183308 kb
Host smart-28d4f28f-95e9-490c-b2c3-2652e73d65d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225908370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.225908370
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.674042108
Short name T161
Test name
Test status
Simulation time 224109605437 ps
CPU time 632.88 seconds
Started Aug 14 04:49:30 PM PDT 24
Finished Aug 14 05:00:03 PM PDT 24
Peak memory 191732 kb
Host smart-960949bd-e7a8-4574-bc7f-c9540fb035fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674042108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
674042108
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3889084796
Short name T434
Test name
Test status
Simulation time 52141844775 ps
CPU time 26 seconds
Started Aug 14 04:49:34 PM PDT 24
Finished Aug 14 04:50:00 PM PDT 24
Peak memory 183524 kb
Host smart-751191e5-8810-4b44-a562-24e9c2a6aaec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889084796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3889084796
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2767164681
Short name T27
Test name
Test status
Simulation time 141590442575 ps
CPU time 225.95 seconds
Started Aug 14 04:49:31 PM PDT 24
Finished Aug 14 04:53:17 PM PDT 24
Peak memory 183532 kb
Host smart-8cc7808e-c75a-4b50-b7f4-1c2c99872ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767164681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2767164681
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1220743455
Short name T444
Test name
Test status
Simulation time 306860874096 ps
CPU time 420.82 seconds
Started Aug 14 04:49:32 PM PDT 24
Finished Aug 14 04:56:33 PM PDT 24
Peak memory 191840 kb
Host smart-5bd8eedc-7365-4c92-bf63-3a6ea02afe7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220743455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1220743455
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2845014064
Short name T42
Test name
Test status
Simulation time 621455708 ps
CPU time 2.29 seconds
Started Aug 14 04:49:31 PM PDT 24
Finished Aug 14 04:49:33 PM PDT 24
Peak memory 183336 kb
Host smart-b96abc95-05f1-4b92-aed1-3bf32a93c2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845014064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2845014064
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3854503089
Short name T212
Test name
Test status
Simulation time 589234394063 ps
CPU time 340.76 seconds
Started Aug 14 04:49:30 PM PDT 24
Finished Aug 14 04:55:11 PM PDT 24
Peak memory 183588 kb
Host smart-aed5620a-2283-4d88-bbf7-8097b5ad6042
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854503089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3854503089
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random.2399344455
Short name T259
Test name
Test status
Simulation time 116274944884 ps
CPU time 163.19 seconds
Started Aug 14 04:49:31 PM PDT 24
Finished Aug 14 04:52:14 PM PDT 24
Peak memory 191824 kb
Host smart-21df631a-ef5b-4007-9ed1-7c2113da282f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399344455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2399344455
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.866512853
Short name T312
Test name
Test status
Simulation time 39953124310 ps
CPU time 57.1 seconds
Started Aug 14 04:49:39 PM PDT 24
Finished Aug 14 04:50:36 PM PDT 24
Peak memory 183588 kb
Host smart-0d24021a-6740-4207-8e20-a798b51ece76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866512853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.866512853
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.1251882279
Short name T435
Test name
Test status
Simulation time 1204022745 ps
CPU time 10.78 seconds
Started Aug 14 04:49:44 PM PDT 24
Finished Aug 14 04:49:55 PM PDT 24
Peak memory 198104 kb
Host smart-73c8ea1a-3f03-4623-b04f-ecbb20792314
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251882279 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.1251882279
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3898359744
Short name T346
Test name
Test status
Simulation time 236115883277 ps
CPU time 392.44 seconds
Started Aug 14 04:49:38 PM PDT 24
Finished Aug 14 04:56:11 PM PDT 24
Peak memory 183528 kb
Host smart-0133e615-3b7c-4ec7-a28f-c471f0379fb1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898359744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3898359744
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.4020523581
Short name T400
Test name
Test status
Simulation time 438639700037 ps
CPU time 155.35 seconds
Started Aug 14 04:49:39 PM PDT 24
Finished Aug 14 04:52:14 PM PDT 24
Peak memory 183592 kb
Host smart-b818e11b-9160-4b5b-b67b-9dc8374ee516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020523581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.4020523581
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3055713013
Short name T302
Test name
Test status
Simulation time 24032431968 ps
CPU time 22.02 seconds
Started Aug 14 04:49:39 PM PDT 24
Finished Aug 14 04:50:01 PM PDT 24
Peak memory 183644 kb
Host smart-11d1eef9-dab9-4a92-85cc-e370f1283534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055713013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3055713013
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1242431741
Short name T390
Test name
Test status
Simulation time 260461561618 ps
CPU time 475.56 seconds
Started Aug 14 04:49:38 PM PDT 24
Finished Aug 14 04:57:34 PM PDT 24
Peak memory 191744 kb
Host smart-f96f0783-1345-47bf-ab71-0abd0b727aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242431741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1242431741
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1070473923
Short name T183
Test name
Test status
Simulation time 261233589425 ps
CPU time 428.97 seconds
Started Aug 14 04:49:41 PM PDT 24
Finished Aug 14 04:56:50 PM PDT 24
Peak memory 183588 kb
Host smart-7620209c-38eb-47dd-905d-58f0748c0fb1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070473923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1070473923
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3417074961
Short name T448
Test name
Test status
Simulation time 133604057394 ps
CPU time 185.48 seconds
Started Aug 14 04:49:40 PM PDT 24
Finished Aug 14 04:52:45 PM PDT 24
Peak memory 183616 kb
Host smart-8fbf604f-5aff-4ca4-9c76-80b8f2fae4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417074961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3417074961
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.434780831
Short name T174
Test name
Test status
Simulation time 219810110225 ps
CPU time 180.14 seconds
Started Aug 14 04:49:37 PM PDT 24
Finished Aug 14 04:52:37 PM PDT 24
Peak memory 191732 kb
Host smart-47707598-2274-4b75-80ef-d93c815154f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434780831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.434780831
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3296858215
Short name T354
Test name
Test status
Simulation time 944269624 ps
CPU time 6.34 seconds
Started Aug 14 04:49:44 PM PDT 24
Finished Aug 14 04:49:50 PM PDT 24
Peak memory 183396 kb
Host smart-412f95ac-f24c-42a9-80fd-633236047eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296858215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3296858215
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1967397498
Short name T202
Test name
Test status
Simulation time 418965650399 ps
CPU time 1060.21 seconds
Started Aug 14 04:49:39 PM PDT 24
Finished Aug 14 05:07:20 PM PDT 24
Peak memory 183588 kb
Host smart-2caa9e66-126b-4a56-a3c5-1e6b9e990450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967397498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1967397498
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3600861256
Short name T376
Test name
Test status
Simulation time 43615866586 ps
CPU time 15.02 seconds
Started Aug 14 04:49:44 PM PDT 24
Finished Aug 14 04:50:00 PM PDT 24
Peak memory 183516 kb
Host smart-77ddc534-3f9f-418c-859d-74e93d65d293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600861256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3600861256
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1171178410
Short name T228
Test name
Test status
Simulation time 40090158148 ps
CPU time 60.23 seconds
Started Aug 14 04:49:38 PM PDT 24
Finished Aug 14 04:50:38 PM PDT 24
Peak memory 191796 kb
Host smart-d4c2616e-a820-4e0b-989c-e12b3bf3b377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171178410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1171178410
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2146206411
Short name T441
Test name
Test status
Simulation time 238018618 ps
CPU time 0.75 seconds
Started Aug 14 04:49:38 PM PDT 24
Finished Aug 14 04:49:39 PM PDT 24
Peak memory 183284 kb
Host smart-978280d7-069d-4bb9-a58b-3e8bfd1b9597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146206411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2146206411
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3739642576
Short name T326
Test name
Test status
Simulation time 837695451426 ps
CPU time 376.91 seconds
Started Aug 14 04:49:39 PM PDT 24
Finished Aug 14 04:55:56 PM PDT 24
Peak memory 183552 kb
Host smart-70f5baa0-7e5a-4864-a1e4-de4b751553d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739642576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3739642576
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3719988818
Short name T436
Test name
Test status
Simulation time 190852232206 ps
CPU time 147.62 seconds
Started Aug 14 04:49:38 PM PDT 24
Finished Aug 14 04:52:06 PM PDT 24
Peak memory 183596 kb
Host smart-09369967-bc62-45f4-9a0d-44db984678ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719988818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3719988818
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2211933584
Short name T210
Test name
Test status
Simulation time 104373569632 ps
CPU time 166.15 seconds
Started Aug 14 04:49:39 PM PDT 24
Finished Aug 14 04:52:25 PM PDT 24
Peak memory 191716 kb
Host smart-0a0372b2-dd3b-4564-8084-5b6a87bd525b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211933584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2211933584
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2627115305
Short name T421
Test name
Test status
Simulation time 77899256 ps
CPU time 0.54 seconds
Started Aug 14 04:49:40 PM PDT 24
Finished Aug 14 04:49:41 PM PDT 24
Peak memory 183192 kb
Host smart-adcee9d3-7bad-4a06-85b0-c2994b66cedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627115305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2627115305
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1515493381
Short name T395
Test name
Test status
Simulation time 1267607251707 ps
CPU time 437.72 seconds
Started Aug 14 04:49:38 PM PDT 24
Finished Aug 14 04:56:55 PM PDT 24
Peak memory 195276 kb
Host smart-6bb4c6b4-592d-4474-a13e-7b92d2911cf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515493381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1515493381
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.828195427
Short name T36
Test name
Test status
Simulation time 7647420542 ps
CPU time 36.42 seconds
Started Aug 14 04:49:38 PM PDT 24
Finished Aug 14 04:50:15 PM PDT 24
Peak memory 198320 kb
Host smart-c8638a9f-b2d3-45ed-8a6b-fc7d86d7418a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828195427 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.828195427
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1389088635
Short name T304
Test name
Test status
Simulation time 418797948955 ps
CPU time 623.98 seconds
Started Aug 14 04:49:50 PM PDT 24
Finished Aug 14 05:00:14 PM PDT 24
Peak memory 183504 kb
Host smart-44bac72f-4561-471e-8470-2af9b917cfc1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389088635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1389088635
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1708694089
Short name T5
Test name
Test status
Simulation time 239279148431 ps
CPU time 174.73 seconds
Started Aug 14 04:49:50 PM PDT 24
Finished Aug 14 04:52:45 PM PDT 24
Peak memory 183616 kb
Host smart-3ccd05c7-7769-4d88-b8f5-e5da3ee7841e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708694089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1708694089
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.769906153
Short name T348
Test name
Test status
Simulation time 194380924821 ps
CPU time 179.38 seconds
Started Aug 14 04:49:50 PM PDT 24
Finished Aug 14 04:52:50 PM PDT 24
Peak memory 191688 kb
Host smart-b396d3da-8dce-4653-bb18-e898650553ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769906153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.769906153
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.22417512
Short name T406
Test name
Test status
Simulation time 531129850 ps
CPU time 3.79 seconds
Started Aug 14 04:49:47 PM PDT 24
Finished Aug 14 04:49:51 PM PDT 24
Peak memory 183404 kb
Host smart-75fc0045-fe4d-4cee-9d60-d9bdde5b28d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22417512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.22417512
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.520118283
Short name T115
Test name
Test status
Simulation time 547698608063 ps
CPU time 1669.75 seconds
Started Aug 14 04:49:48 PM PDT 24
Finished Aug 14 05:17:38 PM PDT 24
Peak memory 191788 kb
Host smart-ed3955c3-2344-43ea-9351-5fe44b1c516f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520118283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
520118283
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.749805244
Short name T173
Test name
Test status
Simulation time 554835351655 ps
CPU time 351.79 seconds
Started Aug 14 04:49:47 PM PDT 24
Finished Aug 14 04:55:39 PM PDT 24
Peak memory 183604 kb
Host smart-642d6157-e759-4714-b59d-d5ac4cd1d144
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749805244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.749805244
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2240207365
Short name T413
Test name
Test status
Simulation time 35232234269 ps
CPU time 58.93 seconds
Started Aug 14 04:49:47 PM PDT 24
Finished Aug 14 04:50:47 PM PDT 24
Peak memory 183584 kb
Host smart-54e3f36a-d39b-41b5-ac18-becc4b1fd4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240207365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2240207365
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3163030750
Short name T124
Test name
Test status
Simulation time 71467705224 ps
CPU time 91.23 seconds
Started Aug 14 04:49:50 PM PDT 24
Finished Aug 14 04:51:21 PM PDT 24
Peak memory 191716 kb
Host smart-eaa4435f-539c-4d98-a2a2-79632fa0785a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163030750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3163030750
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1558295645
Short name T397
Test name
Test status
Simulation time 115203374 ps
CPU time 0.75 seconds
Started Aug 14 04:49:46 PM PDT 24
Finished Aug 14 04:49:47 PM PDT 24
Peak memory 183284 kb
Host smart-ba928c7d-e1d2-4d67-88a0-69e2e77e36af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558295645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1558295645
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3949921211
Short name T143
Test name
Test status
Simulation time 2410637957583 ps
CPU time 1924.55 seconds
Started Aug 14 04:49:52 PM PDT 24
Finished Aug 14 05:21:57 PM PDT 24
Peak memory 191728 kb
Host smart-7311af84-de31-4635-b46a-3d1d53f0f3d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949921211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3949921211
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.986113572
Short name T336
Test name
Test status
Simulation time 38311778595 ps
CPU time 16.67 seconds
Started Aug 14 04:48:31 PM PDT 24
Finished Aug 14 04:48:47 PM PDT 24
Peak memory 183492 kb
Host smart-80e9ba09-75f6-4e31-a937-a740d45289d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986113572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.986113572
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1639166671
Short name T391
Test name
Test status
Simulation time 31974606505 ps
CPU time 47.42 seconds
Started Aug 14 04:48:35 PM PDT 24
Finished Aug 14 04:49:22 PM PDT 24
Peak memory 183612 kb
Host smart-d040d7b5-3885-467a-a6b3-4dc2a441a5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639166671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1639166671
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.234538253
Short name T119
Test name
Test status
Simulation time 118550935821 ps
CPU time 94.2 seconds
Started Aug 14 04:48:32 PM PDT 24
Finished Aug 14 04:50:06 PM PDT 24
Peak memory 194308 kb
Host smart-2a219e1f-b2b7-4fd5-b4c6-3a9400a6e175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234538253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.234538253
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3402093057
Short name T141
Test name
Test status
Simulation time 314549899004 ps
CPU time 499.76 seconds
Started Aug 14 04:48:31 PM PDT 24
Finished Aug 14 04:56:51 PM PDT 24
Peak memory 191780 kb
Host smart-6dd0881d-f308-49b5-97f0-fca4b68bbb6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402093057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3402093057
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/51.rv_timer_random.2258499293
Short name T320
Test name
Test status
Simulation time 237933968306 ps
CPU time 181.76 seconds
Started Aug 14 04:49:49 PM PDT 24
Finished Aug 14 04:52:51 PM PDT 24
Peak memory 191740 kb
Host smart-7b31637a-1b8c-41c9-bb8d-30c2510d00f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258499293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2258499293
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.4178424596
Short name T209
Test name
Test status
Simulation time 111766518360 ps
CPU time 460.37 seconds
Started Aug 14 04:49:47 PM PDT 24
Finished Aug 14 04:57:28 PM PDT 24
Peak memory 191612 kb
Host smart-2693f96b-2a24-45a2-9cda-d5fee99970a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178424596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.4178424596
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1238292759
Short name T255
Test name
Test status
Simulation time 510034304256 ps
CPU time 799.36 seconds
Started Aug 14 04:49:48 PM PDT 24
Finished Aug 14 05:03:07 PM PDT 24
Peak memory 191832 kb
Host smart-88a33817-6d5a-40ab-b145-3b23fac16a26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238292759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1238292759
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1846432503
Short name T101
Test name
Test status
Simulation time 385382358023 ps
CPU time 168.18 seconds
Started Aug 14 04:49:49 PM PDT 24
Finished Aug 14 04:52:38 PM PDT 24
Peak memory 191844 kb
Host smart-a05c9bb9-5cfb-452d-a4fa-f14ebf70b86d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846432503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1846432503
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3104474493
Short name T108
Test name
Test status
Simulation time 114631156780 ps
CPU time 248.35 seconds
Started Aug 14 04:49:49 PM PDT 24
Finished Aug 14 04:53:57 PM PDT 24
Peak memory 191712 kb
Host smart-93f5672d-c28b-4210-8bff-80b6955e5f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104474493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3104474493
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.583823838
Short name T286
Test name
Test status
Simulation time 804873382 ps
CPU time 0.84 seconds
Started Aug 14 04:49:48 PM PDT 24
Finished Aug 14 04:49:49 PM PDT 24
Peak memory 183280 kb
Host smart-5625ff67-5133-4c80-9be3-9152d03b107d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583823838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.583823838
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1972447697
Short name T433
Test name
Test status
Simulation time 25887678950 ps
CPU time 9.48 seconds
Started Aug 14 04:49:48 PM PDT 24
Finished Aug 14 04:49:58 PM PDT 24
Peak memory 183328 kb
Host smart-f077450d-78db-422f-9360-00d7f82f735a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972447697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1972447697
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.496797104
Short name T155
Test name
Test status
Simulation time 6405705698 ps
CPU time 11.99 seconds
Started Aug 14 04:48:42 PM PDT 24
Finished Aug 14 04:48:54 PM PDT 24
Peak memory 183580 kb
Host smart-5ff1f2d9-85e8-4f39-9826-7f8d5c8fddfb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496797104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.496797104
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2296196882
Short name T383
Test name
Test status
Simulation time 112048122058 ps
CPU time 45.98 seconds
Started Aug 14 04:48:29 PM PDT 24
Finished Aug 14 04:49:15 PM PDT 24
Peak memory 183524 kb
Host smart-b3bfb2d0-6d07-40c2-b681-f0d8a28a1703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296196882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2296196882
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.952008366
Short name T169
Test name
Test status
Simulation time 114786414295 ps
CPU time 256.41 seconds
Started Aug 14 04:48:33 PM PDT 24
Finished Aug 14 04:52:49 PM PDT 24
Peak memory 191800 kb
Host smart-e25a1a0c-ee08-405e-88ee-2c9a8210378a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952008366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.952008366
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3231855850
Short name T373
Test name
Test status
Simulation time 224267163 ps
CPU time 0.71 seconds
Started Aug 14 04:48:43 PM PDT 24
Finished Aug 14 04:48:44 PM PDT 24
Peak memory 191960 kb
Host smart-100b99b1-0447-432e-896e-c7152e3d8271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231855850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3231855850
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2579271522
Short name T426
Test name
Test status
Simulation time 116546074390 ps
CPU time 43.74 seconds
Started Aug 14 04:48:41 PM PDT 24
Finished Aug 14 04:49:24 PM PDT 24
Peak memory 183576 kb
Host smart-347c8bd7-a9cd-42ce-a777-21b0a30c9f22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579271522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2579271522
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.868454363
Short name T405
Test name
Test status
Simulation time 5951964307 ps
CPU time 18.68 seconds
Started Aug 14 04:48:41 PM PDT 24
Finished Aug 14 04:49:00 PM PDT 24
Peak memory 198208 kb
Host smart-2650ab30-ad05-48fa-b628-3b4082723d5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868454363 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.868454363
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3256883256
Short name T317
Test name
Test status
Simulation time 43805599818 ps
CPU time 71.41 seconds
Started Aug 14 04:49:57 PM PDT 24
Finished Aug 14 04:51:09 PM PDT 24
Peak memory 183632 kb
Host smart-a7e49eac-7fd5-4a8b-9939-493f3abc01e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256883256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3256883256
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2832335919
Short name T111
Test name
Test status
Simulation time 218045903885 ps
CPU time 150.8 seconds
Started Aug 14 04:49:59 PM PDT 24
Finished Aug 14 04:52:30 PM PDT 24
Peak memory 190908 kb
Host smart-3f68c4b9-30a4-4dfc-9406-f111743d008a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832335919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2832335919
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2500570001
Short name T247
Test name
Test status
Simulation time 233300476340 ps
CPU time 190.34 seconds
Started Aug 14 04:49:57 PM PDT 24
Finished Aug 14 04:53:07 PM PDT 24
Peak memory 191716 kb
Host smart-914566d0-5824-43da-b1e6-616fba786913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500570001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2500570001
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1099544507
Short name T432
Test name
Test status
Simulation time 25030881018 ps
CPU time 38.32 seconds
Started Aug 14 04:49:57 PM PDT 24
Finished Aug 14 04:50:36 PM PDT 24
Peak memory 183520 kb
Host smart-38537dbd-2590-4ba0-b0fc-8ffe1b46f61e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099544507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1099544507
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1628975369
Short name T363
Test name
Test status
Simulation time 19806029297 ps
CPU time 21.55 seconds
Started Aug 14 04:49:57 PM PDT 24
Finished Aug 14 04:50:19 PM PDT 24
Peak memory 183556 kb
Host smart-7bb47da7-6cd9-4ed2-bfe6-42c5f90f95ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628975369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1628975369
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1958926013
Short name T315
Test name
Test status
Simulation time 3030606939 ps
CPU time 108.71 seconds
Started Aug 14 04:49:59 PM PDT 24
Finished Aug 14 04:51:48 PM PDT 24
Peak memory 183580 kb
Host smart-fa3c0549-3c7e-430d-976a-a7a8f081caa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958926013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1958926013
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2236315097
Short name T2
Test name
Test status
Simulation time 10922788948 ps
CPU time 24.54 seconds
Started Aug 14 04:50:00 PM PDT 24
Finished Aug 14 04:50:25 PM PDT 24
Peak memory 183592 kb
Host smart-9b2c0e72-ad3f-433b-9fd1-4c6bd88b9066
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236315097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2236315097
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1693462491
Short name T191
Test name
Test status
Simulation time 1367764894069 ps
CPU time 586.13 seconds
Started Aug 14 04:48:40 PM PDT 24
Finished Aug 14 04:58:26 PM PDT 24
Peak memory 183596 kb
Host smart-3e423704-6c06-4e09-ad36-f3dbcfb811a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693462491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1693462491
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1430432663
Short name T374
Test name
Test status
Simulation time 497175835861 ps
CPU time 163.98 seconds
Started Aug 14 04:48:41 PM PDT 24
Finished Aug 14 04:51:25 PM PDT 24
Peak memory 183588 kb
Host smart-c3f881bc-5a51-4c3f-a32e-286744930410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430432663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1430432663
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1911597203
Short name T407
Test name
Test status
Simulation time 48698001136 ps
CPU time 22.65 seconds
Started Aug 14 04:48:40 PM PDT 24
Finished Aug 14 04:49:03 PM PDT 24
Peak memory 191812 kb
Host smart-db38105e-5243-45a9-90ce-93143f12dd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911597203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1911597203
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1144019978
Short name T392
Test name
Test status
Simulation time 145015045854 ps
CPU time 204.53 seconds
Started Aug 14 04:48:40 PM PDT 24
Finished Aug 14 04:52:05 PM PDT 24
Peak memory 195176 kb
Host smart-42b2b421-cfc8-4a5d-a57f-ec518d357b06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144019978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1144019978
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/71.rv_timer_random.1917248152
Short name T113
Test name
Test status
Simulation time 101848451461 ps
CPU time 267.98 seconds
Started Aug 14 04:49:58 PM PDT 24
Finished Aug 14 04:54:26 PM PDT 24
Peak memory 193900 kb
Host smart-907b8f60-d6f8-47fb-b016-bdb87709090f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917248152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1917248152
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2337288827
Short name T94
Test name
Test status
Simulation time 619483094989 ps
CPU time 624.8 seconds
Started Aug 14 04:49:56 PM PDT 24
Finished Aug 14 05:00:21 PM PDT 24
Peak memory 191800 kb
Host smart-0f3a4702-6fb4-42a9-a47c-82611dc08fc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337288827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2337288827
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1571145068
Short name T151
Test name
Test status
Simulation time 33350578869 ps
CPU time 53.44 seconds
Started Aug 14 04:49:59 PM PDT 24
Finished Aug 14 04:50:53 PM PDT 24
Peak memory 191716 kb
Host smart-ea220a67-8684-4849-91b7-15aa37565304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571145068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1571145068
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2281221466
Short name T134
Test name
Test status
Simulation time 54379896436 ps
CPU time 93.01 seconds
Started Aug 14 04:49:57 PM PDT 24
Finished Aug 14 04:51:30 PM PDT 24
Peak memory 191812 kb
Host smart-b939c62e-737e-4195-a88c-68de28251930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281221466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2281221466
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3899249447
Short name T136
Test name
Test status
Simulation time 1279145848425 ps
CPU time 739.75 seconds
Started Aug 14 04:49:55 PM PDT 24
Finished Aug 14 05:02:15 PM PDT 24
Peak memory 191840 kb
Host smart-861e0ef9-cc67-4760-9c49-ae40fad78958
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899249447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3899249447
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3761746413
Short name T450
Test name
Test status
Simulation time 29141273029 ps
CPU time 55.72 seconds
Started Aug 14 04:50:07 PM PDT 24
Finished Aug 14 04:51:03 PM PDT 24
Peak memory 191708 kb
Host smart-fc2c2799-72c7-49cc-bb7c-1cd9b5648247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761746413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3761746413
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3966211551
Short name T361
Test name
Test status
Simulation time 21192707534 ps
CPU time 15.18 seconds
Started Aug 14 04:48:43 PM PDT 24
Finished Aug 14 04:48:59 PM PDT 24
Peak memory 183572 kb
Host smart-72f3d4d7-76ed-40b8-a418-bbf480d2ab45
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966211551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3966211551
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3799863867
Short name T375
Test name
Test status
Simulation time 143117872092 ps
CPU time 112.67 seconds
Started Aug 14 04:48:42 PM PDT 24
Finished Aug 14 04:50:35 PM PDT 24
Peak memory 183524 kb
Host smart-ce3e861f-115d-4994-9f4b-7a05c995ba15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799863867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3799863867
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3807116132
Short name T171
Test name
Test status
Simulation time 20876226854 ps
CPU time 115.9 seconds
Started Aug 14 04:48:40 PM PDT 24
Finished Aug 14 04:50:36 PM PDT 24
Peak memory 183508 kb
Host smart-5c822e54-db7b-4733-bf7b-4045c1df8daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807116132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3807116132
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.627533593
Short name T26
Test name
Test status
Simulation time 43305558066 ps
CPU time 147.79 seconds
Started Aug 14 04:48:39 PM PDT 24
Finished Aug 14 04:51:07 PM PDT 24
Peak memory 183516 kb
Host smart-9093781d-9ade-4f57-a23e-2c16335e94d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627533593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.627533593
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2398573401
Short name T360
Test name
Test status
Simulation time 123963609234 ps
CPU time 183.32 seconds
Started Aug 14 04:48:41 PM PDT 24
Finished Aug 14 04:51:44 PM PDT 24
Peak memory 194560 kb
Host smart-7130f086-7efc-4a35-8aba-59352794b679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398573401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2398573401
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/81.rv_timer_random.2790458009
Short name T193
Test name
Test status
Simulation time 29956829398 ps
CPU time 52.49 seconds
Started Aug 14 04:50:07 PM PDT 24
Finished Aug 14 04:51:00 PM PDT 24
Peak memory 195300 kb
Host smart-97074011-0dd2-47b6-a226-e2f28b85b970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790458009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2790458009
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.887056004
Short name T170
Test name
Test status
Simulation time 310012338397 ps
CPU time 153.15 seconds
Started Aug 14 04:50:07 PM PDT 24
Finished Aug 14 04:52:40 PM PDT 24
Peak memory 191712 kb
Host smart-705fd212-6800-4d8c-9838-d09dc3438291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887056004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.887056004
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1253563678
Short name T24
Test name
Test status
Simulation time 314099250991 ps
CPU time 278.92 seconds
Started Aug 14 04:50:08 PM PDT 24
Finished Aug 14 04:54:47 PM PDT 24
Peak memory 191676 kb
Host smart-29b24981-13f3-42ca-8e9e-88b52c0130a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253563678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1253563678
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2455135574
Short name T145
Test name
Test status
Simulation time 629731686050 ps
CPU time 583.55 seconds
Started Aug 14 04:50:06 PM PDT 24
Finished Aug 14 04:59:50 PM PDT 24
Peak memory 191700 kb
Host smart-87eae653-bb69-4ad0-adf4-46674db43d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455135574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2455135574
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3706010991
Short name T258
Test name
Test status
Simulation time 21364540776 ps
CPU time 167.07 seconds
Started Aug 14 04:50:06 PM PDT 24
Finished Aug 14 04:52:54 PM PDT 24
Peak memory 183516 kb
Host smart-a08b89c7-273f-42e7-ae98-ee86c424a6de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706010991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3706010991
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1739755863
Short name T127
Test name
Test status
Simulation time 198297061375 ps
CPU time 677.46 seconds
Started Aug 14 04:50:08 PM PDT 24
Finished Aug 14 05:01:25 PM PDT 24
Peak memory 195036 kb
Host smart-8020d3ce-5897-4209-b461-6648ec77ae49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739755863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1739755863
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.4186947397
Short name T282
Test name
Test status
Simulation time 153026125559 ps
CPU time 156.26 seconds
Started Aug 14 04:50:07 PM PDT 24
Finished Aug 14 04:52:43 PM PDT 24
Peak memory 191776 kb
Host smart-b6018133-30b1-492b-92f4-82789badc982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186947397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.4186947397
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2925390627
Short name T112
Test name
Test status
Simulation time 288378769023 ps
CPU time 368.66 seconds
Started Aug 14 04:50:08 PM PDT 24
Finished Aug 14 04:56:17 PM PDT 24
Peak memory 191772 kb
Host smart-cf53a6a1-bd25-4f1d-9bef-a1981a074793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925390627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2925390627
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.709403626
Short name T270
Test name
Test status
Simulation time 265923801075 ps
CPU time 113.74 seconds
Started Aug 14 04:50:07 PM PDT 24
Finished Aug 14 04:52:01 PM PDT 24
Peak memory 191824 kb
Host smart-c98689dc-c81b-4422-b5c2-b65afc3604d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709403626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.709403626
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.4268109474
Short name T453
Test name
Test status
Simulation time 162069647185 ps
CPU time 167.05 seconds
Started Aug 14 04:48:41 PM PDT 24
Finished Aug 14 04:51:28 PM PDT 24
Peak memory 183604 kb
Host smart-70466cf6-96c9-4c05-8166-bea9f5850e85
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268109474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.4268109474
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.4284190702
Short name T437
Test name
Test status
Simulation time 135814217340 ps
CPU time 204.95 seconds
Started Aug 14 04:48:43 PM PDT 24
Finished Aug 14 04:52:08 PM PDT 24
Peak memory 183592 kb
Host smart-7501e97c-ce07-4f6a-a391-9396d8d3b905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284190702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.4284190702
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.88651074
Short name T12
Test name
Test status
Simulation time 447749926308 ps
CPU time 424.66 seconds
Started Aug 14 04:48:42 PM PDT 24
Finished Aug 14 04:55:47 PM PDT 24
Peak memory 191804 kb
Host smart-7f945034-c0c6-46b8-a376-b0908ae7a156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88651074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.88651074
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.669173567
Short name T28
Test name
Test status
Simulation time 20400890022 ps
CPU time 16.58 seconds
Started Aug 14 04:48:42 PM PDT 24
Finished Aug 14 04:48:59 PM PDT 24
Peak memory 193940 kb
Host smart-2c4f8250-3859-4b8a-bf19-981706cb0133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669173567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.669173567
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.12032415
Short name T451
Test name
Test status
Simulation time 40985802367 ps
CPU time 65.05 seconds
Started Aug 14 04:48:41 PM PDT 24
Finished Aug 14 04:49:46 PM PDT 24
Peak memory 183504 kb
Host smart-900bf104-c929-4247-bc99-f03161e05898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12032415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.12032415
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.2637952462
Short name T221
Test name
Test status
Simulation time 561604577520 ps
CPU time 785.94 seconds
Started Aug 14 04:50:07 PM PDT 24
Finished Aug 14 05:03:13 PM PDT 24
Peak memory 191796 kb
Host smart-b1806ed8-e149-4ed4-a36c-f7b0321c0307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637952462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2637952462
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3056222439
Short name T303
Test name
Test status
Simulation time 533609834829 ps
CPU time 646.83 seconds
Started Aug 14 04:50:08 PM PDT 24
Finished Aug 14 05:00:55 PM PDT 24
Peak memory 191668 kb
Host smart-e4ebffa3-a48a-4c7b-851e-b3aaff2efad6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056222439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3056222439
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.958591062
Short name T297
Test name
Test status
Simulation time 756167030916 ps
CPU time 216.58 seconds
Started Aug 14 04:50:07 PM PDT 24
Finished Aug 14 04:53:44 PM PDT 24
Peak memory 191748 kb
Host smart-32f623ab-b2d8-4fa0-a796-fcee58176011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958591062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.958591062
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3739744128
Short name T184
Test name
Test status
Simulation time 662369670355 ps
CPU time 1665.1 seconds
Started Aug 14 04:50:15 PM PDT 24
Finished Aug 14 05:18:00 PM PDT 24
Peak memory 195204 kb
Host smart-bcccf981-375b-41ea-874c-32841b2c8b6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739744128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3739744128
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3112859450
Short name T226
Test name
Test status
Simulation time 61499311849 ps
CPU time 93.79 seconds
Started Aug 14 04:50:17 PM PDT 24
Finished Aug 14 04:51:51 PM PDT 24
Peak memory 195284 kb
Host smart-f9b50487-1258-448e-bdc3-1c1a32a9b21d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112859450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3112859450
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1976434138
Short name T419
Test name
Test status
Simulation time 49953998401 ps
CPU time 75.5 seconds
Started Aug 14 04:50:15 PM PDT 24
Finished Aug 14 04:51:31 PM PDT 24
Peak memory 183516 kb
Host smart-653e3f34-3d69-447d-bbb1-4cdbf1abe538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976434138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1976434138
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3330731287
Short name T225
Test name
Test status
Simulation time 265558850325 ps
CPU time 251.53 seconds
Started Aug 14 04:50:15 PM PDT 24
Finished Aug 14 04:54:27 PM PDT 24
Peak memory 191744 kb
Host smart-6a6d5c34-3f30-457b-aba5-c2c2a597e112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330731287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3330731287
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1164520588
Short name T417
Test name
Test status
Simulation time 105345998862 ps
CPU time 43.46 seconds
Started Aug 14 04:50:16 PM PDT 24
Finished Aug 14 04:51:00 PM PDT 24
Peak memory 183504 kb
Host smart-cd98616b-f191-439d-bfda-9ad5604a6a5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164520588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1164520588
Directory /workspace/99.rv_timer_random/latest
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