Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.36 98.73 100.00 100.00 100.00 99.77


Total test records in report: 581
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T508 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.584378499 Aug 15 05:57:45 PM PDT 24 Aug 15 05:57:46 PM PDT 24 31203507 ps
T94 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.206417386 Aug 15 05:57:29 PM PDT 24 Aug 15 05:57:30 PM PDT 24 53440370 ps
T509 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2564521448 Aug 15 05:57:15 PM PDT 24 Aug 15 05:57:17 PM PDT 24 511941672 ps
T510 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3833321900 Aug 15 05:57:21 PM PDT 24 Aug 15 05:57:23 PM PDT 24 36685872 ps
T85 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2408105149 Aug 15 05:57:21 PM PDT 24 Aug 15 05:57:22 PM PDT 24 55131498 ps
T511 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1340623024 Aug 15 05:57:33 PM PDT 24 Aug 15 05:57:34 PM PDT 24 47054111 ps
T512 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3271124548 Aug 15 05:57:30 PM PDT 24 Aug 15 05:57:32 PM PDT 24 814338169 ps
T95 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2759853207 Aug 15 05:57:22 PM PDT 24 Aug 15 05:57:23 PM PDT 24 11312753 ps
T513 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2435555954 Aug 15 05:57:58 PM PDT 24 Aug 15 05:57:58 PM PDT 24 17728748 ps
T514 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2751622844 Aug 15 05:57:37 PM PDT 24 Aug 15 05:57:38 PM PDT 24 234169397 ps
T515 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3944743627 Aug 15 05:57:32 PM PDT 24 Aug 15 05:57:33 PM PDT 24 14164138 ps
T516 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2835688773 Aug 15 05:57:35 PM PDT 24 Aug 15 05:57:36 PM PDT 24 36067031 ps
T517 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1993003415 Aug 15 05:57:45 PM PDT 24 Aug 15 05:57:46 PM PDT 24 104909618 ps
T518 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3188666769 Aug 15 05:57:57 PM PDT 24 Aug 15 05:57:58 PM PDT 24 18938118 ps
T519 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2791021966 Aug 15 05:57:34 PM PDT 24 Aug 15 05:57:36 PM PDT 24 77969918 ps
T520 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1513740171 Aug 15 05:57:49 PM PDT 24 Aug 15 05:57:50 PM PDT 24 55863043 ps
T521 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3305572269 Aug 15 05:57:38 PM PDT 24 Aug 15 05:57:39 PM PDT 24 88947307 ps
T522 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3757503440 Aug 15 05:57:38 PM PDT 24 Aug 15 05:57:39 PM PDT 24 273926561 ps
T523 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3095360074 Aug 15 05:57:21 PM PDT 24 Aug 15 05:57:22 PM PDT 24 12913386 ps
T524 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4220367012 Aug 15 05:57:23 PM PDT 24 Aug 15 05:57:24 PM PDT 24 254982975 ps
T525 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.580697973 Aug 15 05:57:58 PM PDT 24 Aug 15 05:57:59 PM PDT 24 14960725 ps
T86 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.634755594 Aug 15 05:57:37 PM PDT 24 Aug 15 05:57:38 PM PDT 24 24304350 ps
T526 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.174461075 Aug 15 05:57:45 PM PDT 24 Aug 15 05:57:46 PM PDT 24 16019610 ps
T527 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3582519017 Aug 15 05:57:28 PM PDT 24 Aug 15 05:57:29 PM PDT 24 109830751 ps
T87 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.4286290042 Aug 15 05:57:31 PM PDT 24 Aug 15 05:57:32 PM PDT 24 21541942 ps
T528 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1371363109 Aug 15 05:57:44 PM PDT 24 Aug 15 05:57:45 PM PDT 24 44920603 ps
T529 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1367951952 Aug 15 05:57:45 PM PDT 24 Aug 15 05:57:46 PM PDT 24 15284616 ps
T530 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3059865667 Aug 15 05:57:31 PM PDT 24 Aug 15 05:57:32 PM PDT 24 31726120 ps
T531 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.365292452 Aug 15 05:57:56 PM PDT 24 Aug 15 05:57:57 PM PDT 24 67793065 ps
T532 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3120764203 Aug 15 05:57:49 PM PDT 24 Aug 15 05:57:51 PM PDT 24 33447646 ps
T533 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2368383429 Aug 15 05:57:19 PM PDT 24 Aug 15 05:57:20 PM PDT 24 14547940 ps
T534 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.512748177 Aug 15 05:57:36 PM PDT 24 Aug 15 05:57:37 PM PDT 24 188154953 ps
T535 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.839054956 Aug 15 05:57:57 PM PDT 24 Aug 15 05:57:58 PM PDT 24 52872733 ps
T536 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3481116789 Aug 15 05:57:54 PM PDT 24 Aug 15 05:57:55 PM PDT 24 18638353 ps
T537 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3446947197 Aug 15 05:57:22 PM PDT 24 Aug 15 05:57:23 PM PDT 24 40241620 ps
T538 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3269188069 Aug 15 05:57:28 PM PDT 24 Aug 15 05:57:29 PM PDT 24 15004520 ps
T539 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1138767829 Aug 15 05:57:24 PM PDT 24 Aug 15 05:57:24 PM PDT 24 13151063 ps
T540 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.315394040 Aug 15 05:57:52 PM PDT 24 Aug 15 05:57:53 PM PDT 24 14620198 ps
T541 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2157359858 Aug 15 05:57:30 PM PDT 24 Aug 15 05:57:31 PM PDT 24 98886196 ps
T542 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2377162050 Aug 15 05:57:22 PM PDT 24 Aug 15 05:57:24 PM PDT 24 210823281 ps
T543 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1024437669 Aug 15 05:57:55 PM PDT 24 Aug 15 05:57:56 PM PDT 24 43090426 ps
T544 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1624514804 Aug 15 05:57:31 PM PDT 24 Aug 15 05:57:32 PM PDT 24 52688817 ps
T545 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3690077405 Aug 15 05:57:22 PM PDT 24 Aug 15 05:57:22 PM PDT 24 11624347 ps
T546 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.510045406 Aug 15 05:57:31 PM PDT 24 Aug 15 05:57:33 PM PDT 24 128117227 ps
T547 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.4135373467 Aug 15 05:57:45 PM PDT 24 Aug 15 05:57:47 PM PDT 24 113652124 ps
T88 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2304225583 Aug 15 05:57:22 PM PDT 24 Aug 15 05:57:22 PM PDT 24 30587592 ps
T548 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3473092144 Aug 15 05:57:39 PM PDT 24 Aug 15 05:57:40 PM PDT 24 26783670 ps
T549 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3684409767 Aug 15 05:57:40 PM PDT 24 Aug 15 05:57:40 PM PDT 24 13004915 ps
T550 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.763080458 Aug 15 05:57:45 PM PDT 24 Aug 15 05:57:46 PM PDT 24 39729137 ps
T551 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3267119387 Aug 15 05:57:32 PM PDT 24 Aug 15 05:57:33 PM PDT 24 45367055 ps
T552 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.413484659 Aug 15 05:57:39 PM PDT 24 Aug 15 05:57:40 PM PDT 24 22089838 ps
T553 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1563902895 Aug 15 05:57:37 PM PDT 24 Aug 15 05:57:38 PM PDT 24 52658667 ps
T554 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3820283845 Aug 15 05:57:31 PM PDT 24 Aug 15 05:57:32 PM PDT 24 75756076 ps
T555 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.67632478 Aug 15 05:57:24 PM PDT 24 Aug 15 05:57:25 PM PDT 24 131732734 ps
T556 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1713180934 Aug 15 05:57:34 PM PDT 24 Aug 15 05:57:35 PM PDT 24 29070379 ps
T557 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.949650120 Aug 15 05:57:30 PM PDT 24 Aug 15 05:57:31 PM PDT 24 22381169 ps
T558 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2581102099 Aug 15 05:57:28 PM PDT 24 Aug 15 05:57:29 PM PDT 24 83373014 ps
T559 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.214378223 Aug 15 05:57:38 PM PDT 24 Aug 15 05:57:39 PM PDT 24 13383118 ps
T560 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.993333126 Aug 15 05:57:55 PM PDT 24 Aug 15 05:57:56 PM PDT 24 103674034 ps
T561 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2052145544 Aug 15 05:57:17 PM PDT 24 Aug 15 05:57:18 PM PDT 24 45182590 ps
T562 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2438924972 Aug 15 05:57:16 PM PDT 24 Aug 15 05:57:17 PM PDT 24 209425613 ps
T563 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.465941891 Aug 15 05:57:44 PM PDT 24 Aug 15 05:57:45 PM PDT 24 18554762 ps
T564 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2588938946 Aug 15 05:57:30 PM PDT 24 Aug 15 05:57:32 PM PDT 24 95413828 ps
T565 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3134785698 Aug 15 05:57:56 PM PDT 24 Aug 15 05:57:57 PM PDT 24 19559969 ps
T566 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3775660607 Aug 15 05:57:46 PM PDT 24 Aug 15 05:57:47 PM PDT 24 49186240 ps
T567 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.514195474 Aug 15 05:57:55 PM PDT 24 Aug 15 05:57:56 PM PDT 24 16964669 ps
T568 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3743654157 Aug 15 05:57:18 PM PDT 24 Aug 15 05:57:19 PM PDT 24 52853658 ps
T569 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1875065291 Aug 15 05:57:45 PM PDT 24 Aug 15 05:57:46 PM PDT 24 17367644 ps
T570 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.999057437 Aug 15 05:57:14 PM PDT 24 Aug 15 05:57:15 PM PDT 24 34935096 ps
T571 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2953223515 Aug 15 05:57:22 PM PDT 24 Aug 15 05:57:23 PM PDT 24 59150150 ps
T572 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3950880964 Aug 15 05:57:56 PM PDT 24 Aug 15 05:57:57 PM PDT 24 84124679 ps
T573 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1816319803 Aug 15 05:57:56 PM PDT 24 Aug 15 05:57:57 PM PDT 24 13090813 ps
T574 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4226736377 Aug 15 05:57:13 PM PDT 24 Aug 15 05:57:14 PM PDT 24 16155239 ps
T575 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.75467116 Aug 15 05:57:29 PM PDT 24 Aug 15 05:57:31 PM PDT 24 382817874 ps
T576 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3720723454 Aug 15 05:57:57 PM PDT 24 Aug 15 05:57:58 PM PDT 24 42045759 ps
T577 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.752087404 Aug 15 05:57:43 PM PDT 24 Aug 15 05:57:44 PM PDT 24 20371396 ps
T578 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3069911988 Aug 15 05:57:30 PM PDT 24 Aug 15 05:57:31 PM PDT 24 189197365 ps
T579 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1787372253 Aug 15 05:57:37 PM PDT 24 Aug 15 05:57:39 PM PDT 24 20206011 ps
T580 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3022973412 Aug 15 05:57:36 PM PDT 24 Aug 15 05:57:38 PM PDT 24 95597350 ps
T581 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1074029620 Aug 15 05:57:35 PM PDT 24 Aug 15 05:57:36 PM PDT 24 57480249 ps
T89 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2089863900 Aug 15 05:57:29 PM PDT 24 Aug 15 05:57:30 PM PDT 24 57017046 ps

Test location /workspace/coverage/default/28.rv_timer_disabled.3294847055
Short name T8
Test name
Test status
Simulation time 384952839276 ps
CPU time 164.16 seconds
Started Aug 15 05:58:25 PM PDT 24
Finished Aug 15 06:01:09 PM PDT 24
Peak memory 183568 kb
Host smart-ac1e37b2-6ed7-442c-b8b3-3a8999c03dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294847055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3294847055
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.488254465
Short name T15
Test name
Test status
Simulation time 1345093999 ps
CPU time 12.25 seconds
Started Aug 15 05:58:18 PM PDT 24
Finished Aug 15 05:58:30 PM PDT 24
Peak memory 198112 kb
Host smart-2315acca-685c-4d10-8d9d-4ff847bff305
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488254465 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.488254465
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2414044927
Short name T1
Test name
Test status
Simulation time 460500144685 ps
CPU time 715.15 seconds
Started Aug 15 05:58:23 PM PDT 24
Finished Aug 15 06:10:19 PM PDT 24
Peak memory 191772 kb
Host smart-7ca0c051-dd7b-4d83-919b-533b832f58ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414044927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2414044927
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2708334699
Short name T11
Test name
Test status
Simulation time 2850959950172 ps
CPU time 1985.39 seconds
Started Aug 15 05:58:17 PM PDT 24
Finished Aug 15 06:31:23 PM PDT 24
Peak memory 191696 kb
Host smart-eb520a66-7426-4422-974a-ada7e0ad7456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708334699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2708334699
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2205732758
Short name T101
Test name
Test status
Simulation time 482448625666 ps
CPU time 3913.41 seconds
Started Aug 15 05:58:47 PM PDT 24
Finished Aug 15 07:04:01 PM PDT 24
Peak memory 191772 kb
Host smart-65d4b234-8001-4d18-8464-f21f2da32f8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205732758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2205732758
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2956970572
Short name T30
Test name
Test status
Simulation time 81384234 ps
CPU time 0.87 seconds
Started Aug 15 05:57:47 PM PDT 24
Finished Aug 15 05:57:48 PM PDT 24
Peak memory 194136 kb
Host smart-1b8e449b-efa8-41c3-b0bf-651f43a54e25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956970572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2956970572
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.606382186
Short name T69
Test name
Test status
Simulation time 4159375754219 ps
CPU time 2081.33 seconds
Started Aug 15 05:58:37 PM PDT 24
Finished Aug 15 06:33:18 PM PDT 24
Peak memory 196872 kb
Host smart-a3390a7d-0929-414f-83bb-a368af7782f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606382186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
606382186
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3678956986
Short name T169
Test name
Test status
Simulation time 392892703026 ps
CPU time 973.33 seconds
Started Aug 15 05:57:56 PM PDT 24
Finished Aug 15 06:14:10 PM PDT 24
Peak memory 197628 kb
Host smart-6777aeb0-f2bf-4e3f-b3e4-679dbc106141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678956986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3678956986
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.909240338
Short name T176
Test name
Test status
Simulation time 751833981804 ps
CPU time 2793.71 seconds
Started Aug 15 05:58:26 PM PDT 24
Finished Aug 15 06:45:00 PM PDT 24
Peak memory 191708 kb
Host smart-4f53312c-54e7-4a1d-844c-7418b83e7196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909240338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
909240338
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/193.rv_timer_random.1908499251
Short name T103
Test name
Test status
Simulation time 412175965987 ps
CPU time 364.52 seconds
Started Aug 15 05:59:58 PM PDT 24
Finished Aug 15 06:06:03 PM PDT 24
Peak memory 191776 kb
Host smart-281d6c82-c994-4709-a291-e852c5a52126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908499251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1908499251
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.619832664
Short name T53
Test name
Test status
Simulation time 58974492 ps
CPU time 0.59 seconds
Started Aug 15 05:57:20 PM PDT 24
Finished Aug 15 05:57:20 PM PDT 24
Peak memory 183380 kb
Host smart-56537824-069f-4860-b1d7-46f86f16db3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619832664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.619832664
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2183337105
Short name T187
Test name
Test status
Simulation time 5839627632804 ps
CPU time 6990.76 seconds
Started Aug 15 05:58:03 PM PDT 24
Finished Aug 15 07:54:35 PM PDT 24
Peak memory 191788 kb
Host smart-a75a6d8a-34cd-4914-915e-0b0627914eea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183337105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2183337105
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.431659748
Short name T19
Test name
Test status
Simulation time 252526647 ps
CPU time 0.87 seconds
Started Aug 15 05:57:55 PM PDT 24
Finished Aug 15 05:57:56 PM PDT 24
Peak memory 213904 kb
Host smart-8796f46a-3a6d-4afa-82f4-3203f9a274ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431659748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.431659748
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2167146868
Short name T196
Test name
Test status
Simulation time 5424513987568 ps
CPU time 1654.09 seconds
Started Aug 15 05:58:10 PM PDT 24
Finished Aug 15 06:25:44 PM PDT 24
Peak memory 191948 kb
Host smart-95abe1d7-f88d-4563-9207-46415924b723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167146868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2167146868
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1647325200
Short name T170
Test name
Test status
Simulation time 1839979633255 ps
CPU time 1576.67 seconds
Started Aug 15 05:58:54 PM PDT 24
Finished Aug 15 06:25:11 PM PDT 24
Peak memory 191748 kb
Host smart-0ec141c0-27eb-4f99-8a6e-aac0c456171e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647325200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1647325200
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.38195930
Short name T63
Test name
Test status
Simulation time 301446126539 ps
CPU time 224.97 seconds
Started Aug 15 05:59:30 PM PDT 24
Finished Aug 15 06:03:15 PM PDT 24
Peak memory 191804 kb
Host smart-65298692-33f0-411a-9eb8-16d0f4d7df00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38195930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.38195930
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1379317972
Short name T116
Test name
Test status
Simulation time 366128696640 ps
CPU time 449.03 seconds
Started Aug 15 05:59:39 PM PDT 24
Finished Aug 15 06:07:08 PM PDT 24
Peak memory 191804 kb
Host smart-e2771265-ac20-4fb7-9cd0-54b94abfaab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379317972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1379317972
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2199150984
Short name T147
Test name
Test status
Simulation time 952622189734 ps
CPU time 1184.5 seconds
Started Aug 15 05:58:40 PM PDT 24
Finished Aug 15 06:18:25 PM PDT 24
Peak memory 191784 kb
Host smart-f3b3058a-9cfc-4a00-a7cc-6997388c2ba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199150984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2199150984
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_random.1007822745
Short name T77
Test name
Test status
Simulation time 706366561152 ps
CPU time 926.21 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 06:13:39 PM PDT 24
Peak memory 191748 kb
Host smart-34d3469d-5030-4601-8bdf-b18b493cebfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007822745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1007822745
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2237017664
Short name T217
Test name
Test status
Simulation time 197425423469 ps
CPU time 522.74 seconds
Started Aug 15 05:59:42 PM PDT 24
Finished Aug 15 06:08:25 PM PDT 24
Peak memory 191796 kb
Host smart-8869126e-0fd6-417f-aaae-a21c5cabd304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237017664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2237017664
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2765303991
Short name T135
Test name
Test status
Simulation time 248213037256 ps
CPU time 2739.71 seconds
Started Aug 15 05:59:43 PM PDT 24
Finished Aug 15 06:45:23 PM PDT 24
Peak memory 191732 kb
Host smart-6412a5c5-6cf0-40de-95f2-86301eed6865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765303991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2765303991
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1008873984
Short name T317
Test name
Test status
Simulation time 2868204868360 ps
CPU time 781.94 seconds
Started Aug 15 05:58:04 PM PDT 24
Finished Aug 15 06:11:06 PM PDT 24
Peak memory 196436 kb
Host smart-9d063ad4-67bc-46d7-906a-db9a2d4d9822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008873984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1008873984
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/168.rv_timer_random.753548220
Short name T123
Test name
Test status
Simulation time 694388405998 ps
CPU time 1240.16 seconds
Started Aug 15 05:59:44 PM PDT 24
Finished Aug 15 06:20:25 PM PDT 24
Peak memory 191808 kb
Host smart-9adf6282-5d90-431a-8011-db862768a14f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753548220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.753548220
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.233341660
Short name T120
Test name
Test status
Simulation time 128999344916 ps
CPU time 233.11 seconds
Started Aug 15 05:59:17 PM PDT 24
Finished Aug 15 06:03:11 PM PDT 24
Peak memory 191764 kb
Host smart-ee45cb2f-437b-4fe5-9b5a-7a308f494763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233341660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.233341660
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3518895518
Short name T192
Test name
Test status
Simulation time 403410870090 ps
CPU time 645.17 seconds
Started Aug 15 05:58:24 PM PDT 24
Finished Aug 15 06:09:10 PM PDT 24
Peak memory 191740 kb
Host smart-bd23d812-d6bd-421c-abcd-e8ee6513bd5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518895518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3518895518
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.294972732
Short name T133
Test name
Test status
Simulation time 560545996507 ps
CPU time 536.89 seconds
Started Aug 15 05:59:21 PM PDT 24
Finished Aug 15 06:08:18 PM PDT 24
Peak memory 194484 kb
Host smart-15e4effb-48f3-4c3a-84f2-4b72ab59bffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294972732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.294972732
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2138716999
Short name T181
Test name
Test status
Simulation time 445858686871 ps
CPU time 231.61 seconds
Started Aug 15 05:59:28 PM PDT 24
Finished Aug 15 06:03:20 PM PDT 24
Peak memory 191796 kb
Host smart-9fa74ef1-5f24-46f9-9ccc-7730ac0198dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138716999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2138716999
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2090931321
Short name T228
Test name
Test status
Simulation time 134502912047 ps
CPU time 200.6 seconds
Started Aug 15 05:59:50 PM PDT 24
Finished Aug 15 06:03:10 PM PDT 24
Peak memory 195744 kb
Host smart-df301aee-d5bb-402a-a521-9c1727f650e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090931321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2090931321
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2638252244
Short name T142
Test name
Test status
Simulation time 151332168862 ps
CPU time 271.92 seconds
Started Aug 15 05:59:50 PM PDT 24
Finished Aug 15 06:04:22 PM PDT 24
Peak memory 191748 kb
Host smart-ee58d4c3-7192-4625-9ffc-9ba41e0059b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638252244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2638252244
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.311490714
Short name T202
Test name
Test status
Simulation time 160881476582 ps
CPU time 714.58 seconds
Started Aug 15 05:59:01 PM PDT 24
Finished Aug 15 06:10:56 PM PDT 24
Peak memory 191956 kb
Host smart-3a080b28-7dcd-492e-b4c7-b951d11e3bc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311490714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.311490714
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1605897556
Short name T105
Test name
Test status
Simulation time 2119064344752 ps
CPU time 956.78 seconds
Started Aug 15 05:57:57 PM PDT 24
Finished Aug 15 06:13:54 PM PDT 24
Peak memory 191704 kb
Host smart-c87d870a-f5b1-4493-a190-b99ecde8c306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605897556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1605897556
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.3559242178
Short name T194
Test name
Test status
Simulation time 716017941985 ps
CPU time 625.07 seconds
Started Aug 15 05:59:15 PM PDT 24
Finished Aug 15 06:09:41 PM PDT 24
Peak memory 191756 kb
Host smart-f9dd67c0-658a-47cd-a199-7f244b54ae29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559242178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3559242178
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2952251469
Short name T153
Test name
Test status
Simulation time 253447940520 ps
CPU time 863.9 seconds
Started Aug 15 05:59:21 PM PDT 24
Finished Aug 15 06:13:45 PM PDT 24
Peak memory 191804 kb
Host smart-1a269bc0-9405-4441-b184-94c4a1e2af37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952251469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2952251469
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.1001311651
Short name T108
Test name
Test status
Simulation time 586239784088 ps
CPU time 224.92 seconds
Started Aug 15 05:58:24 PM PDT 24
Finished Aug 15 06:02:09 PM PDT 24
Peak memory 191744 kb
Host smart-e57bc1dd-28ac-49ba-ba1d-32bdcfb84b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001311651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1001311651
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3606649942
Short name T239
Test name
Test status
Simulation time 834653343768 ps
CPU time 816.11 seconds
Started Aug 15 05:59:02 PM PDT 24
Finished Aug 15 06:12:39 PM PDT 24
Peak memory 191764 kb
Host smart-dee4ac64-dcca-4bef-9f57-bfc4dec9dffa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606649942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3606649942
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3388583834
Short name T205
Test name
Test status
Simulation time 2076205371986 ps
CPU time 603.63 seconds
Started Aug 15 05:59:09 PM PDT 24
Finished Aug 15 06:09:13 PM PDT 24
Peak memory 191744 kb
Host smart-e6934085-5e1f-424b-bd22-9784dbf7927d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388583834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3388583834
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1575478465
Short name T84
Test name
Test status
Simulation time 17012084 ps
CPU time 0.59 seconds
Started Aug 15 05:57:40 PM PDT 24
Finished Aug 15 05:57:41 PM PDT 24
Peak memory 183296 kb
Host smart-d0925225-3a55-4421-813b-e1e4997c5478
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575478465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1575478465
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/130.rv_timer_random.3233268193
Short name T263
Test name
Test status
Simulation time 289131269288 ps
CPU time 378.59 seconds
Started Aug 15 05:59:30 PM PDT 24
Finished Aug 15 06:05:49 PM PDT 24
Peak memory 191816 kb
Host smart-8f4c361a-1cf6-40b3-a090-d0ac5d679dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233268193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3233268193
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.612910319
Short name T36
Test name
Test status
Simulation time 244167510823 ps
CPU time 719.61 seconds
Started Aug 15 05:58:36 PM PDT 24
Finished Aug 15 06:10:36 PM PDT 24
Peak memory 191808 kb
Host smart-03b0417d-cc4f-4f8a-a6c1-04c2993d12c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612910319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
612910319
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_random.1982245334
Short name T278
Test name
Test status
Simulation time 403044906111 ps
CPU time 427.66 seconds
Started Aug 15 05:58:38 PM PDT 24
Finished Aug 15 06:05:45 PM PDT 24
Peak memory 191748 kb
Host smart-73dccdab-cf92-4008-8fb2-299ce6505e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982245334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1982245334
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2166208615
Short name T189
Test name
Test status
Simulation time 510817237569 ps
CPU time 357.04 seconds
Started Aug 15 05:59:02 PM PDT 24
Finished Aug 15 06:04:59 PM PDT 24
Peak memory 191776 kb
Host smart-ebcf16ac-2532-4fc8-b3d8-4847fb095bbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166208615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2166208615
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2102675767
Short name T177
Test name
Test status
Simulation time 147818717898 ps
CPU time 1105.1 seconds
Started Aug 15 05:59:22 PM PDT 24
Finished Aug 15 06:17:47 PM PDT 24
Peak memory 191780 kb
Host smart-f380af3b-7baf-4e82-86be-ee0197faf512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102675767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2102675767
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2386188153
Short name T49
Test name
Test status
Simulation time 457411750606 ps
CPU time 323.02 seconds
Started Aug 15 05:58:11 PM PDT 24
Finished Aug 15 06:03:34 PM PDT 24
Peak memory 195972 kb
Host smart-57a2bb54-1c8c-4f7d-80db-66b751f04026
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386188153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2386188153
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_random.2896720563
Short name T335
Test name
Test status
Simulation time 195627464212 ps
CPU time 111.89 seconds
Started Aug 15 05:58:17 PM PDT 24
Finished Aug 15 06:00:09 PM PDT 24
Peak memory 193776 kb
Host smart-91cb39f0-f45c-4377-bd17-37ae0fbdab4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896720563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2896720563
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.855531094
Short name T254
Test name
Test status
Simulation time 98026331021 ps
CPU time 170.09 seconds
Started Aug 15 05:59:37 PM PDT 24
Finished Aug 15 06:02:28 PM PDT 24
Peak memory 194260 kb
Host smart-a0d4b12c-b2a7-47a8-b4f2-7b25fbe5c1fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855531094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.855531094
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.367878498
Short name T233
Test name
Test status
Simulation time 467500846089 ps
CPU time 803.87 seconds
Started Aug 15 05:59:50 PM PDT 24
Finished Aug 15 06:13:15 PM PDT 24
Peak memory 191724 kb
Host smart-cd750fc5-20aa-447f-a151-45a828197ba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367878498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.367878498
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2897831105
Short name T137
Test name
Test status
Simulation time 1040750928975 ps
CPU time 1260.68 seconds
Started Aug 15 05:58:25 PM PDT 24
Finished Aug 15 06:19:26 PM PDT 24
Peak memory 194448 kb
Host smart-856d23dd-fdef-4a4e-ae57-de42bf5daa8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897831105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2897831105
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_random.3530530187
Short name T161
Test name
Test status
Simulation time 144495701259 ps
CPU time 224.61 seconds
Started Aug 15 05:58:32 PM PDT 24
Finished Aug 15 06:02:17 PM PDT 24
Peak memory 191732 kb
Host smart-1fdcab96-569a-450f-9325-48ccc0d716cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530530187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3530530187
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3041380200
Short name T321
Test name
Test status
Simulation time 605784471745 ps
CPU time 292.61 seconds
Started Aug 15 05:58:36 PM PDT 24
Finished Aug 15 06:03:29 PM PDT 24
Peak memory 192920 kb
Host smart-0cbf0fcb-ad8e-4655-92f0-0c6909d8dbed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041380200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3041380200
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_random.706221176
Short name T272
Test name
Test status
Simulation time 63263665282 ps
CPU time 1081.36 seconds
Started Aug 15 05:58:40 PM PDT 24
Finished Aug 15 06:16:42 PM PDT 24
Peak memory 191728 kb
Host smart-80525577-7981-45ed-b334-a55e7051c543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706221176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.706221176
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2082541859
Short name T26
Test name
Test status
Simulation time 291534025191 ps
CPU time 272.97 seconds
Started Aug 15 05:59:08 PM PDT 24
Finished Aug 15 06:03:42 PM PDT 24
Peak memory 191744 kb
Host smart-5065747d-6d30-4a09-87d3-a1d9e71cc429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082541859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2082541859
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1521195463
Short name T31
Test name
Test status
Simulation time 126418096 ps
CPU time 1.34 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 195888 kb
Host smart-23d2ea33-013b-4237-a773-57f8a7559360
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521195463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1521195463
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/103.rv_timer_random.2613080299
Short name T243
Test name
Test status
Simulation time 331965252166 ps
CPU time 281.28 seconds
Started Aug 15 05:59:16 PM PDT 24
Finished Aug 15 06:03:57 PM PDT 24
Peak memory 191808 kb
Host smart-d1264858-478b-432f-90ff-66ed0ef70368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613080299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2613080299
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1263481220
Short name T129
Test name
Test status
Simulation time 586139050667 ps
CPU time 313.63 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 06:03:26 PM PDT 24
Peak memory 183460 kb
Host smart-b18a7fdb-88dd-44b2-ae19-3371de4d386e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263481220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1263481220
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/115.rv_timer_random.462179894
Short name T200
Test name
Test status
Simulation time 182696938972 ps
CPU time 592.42 seconds
Started Aug 15 05:59:22 PM PDT 24
Finished Aug 15 06:09:14 PM PDT 24
Peak memory 191796 kb
Host smart-eb253c9a-6683-4c63-8993-bf90f2773e28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462179894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.462179894
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.885720648
Short name T165
Test name
Test status
Simulation time 223063386995 ps
CPU time 455.78 seconds
Started Aug 15 05:59:29 PM PDT 24
Finished Aug 15 06:07:05 PM PDT 24
Peak memory 191796 kb
Host smart-4638a517-0984-435d-830c-0f8de7cf7c60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885720648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.885720648
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.3023272586
Short name T134
Test name
Test status
Simulation time 1186328351237 ps
CPU time 181.4 seconds
Started Aug 15 05:59:37 PM PDT 24
Finished Aug 15 06:02:39 PM PDT 24
Peak memory 194160 kb
Host smart-37864fd8-86b1-4791-a225-8e3f0b7801d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023272586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3023272586
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2831716577
Short name T143
Test name
Test status
Simulation time 104565738288 ps
CPU time 243 seconds
Started Aug 15 05:59:43 PM PDT 24
Finished Aug 15 06:03:46 PM PDT 24
Peak memory 191780 kb
Host smart-0b130b1d-23e5-4e80-9cef-5883d3ec1e90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831716577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2831716577
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.4160655983
Short name T230
Test name
Test status
Simulation time 168972160815 ps
CPU time 611.3 seconds
Started Aug 15 05:58:21 PM PDT 24
Finished Aug 15 06:08:32 PM PDT 24
Peak memory 191844 kb
Host smart-dbb969f0-7feb-41d0-bf1d-7bb193c54bd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160655983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.4160655983
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.625092992
Short name T184
Test name
Test status
Simulation time 540590734682 ps
CPU time 913.46 seconds
Started Aug 15 05:58:42 PM PDT 24
Finished Aug 15 06:13:56 PM PDT 24
Peak memory 183508 kb
Host smart-7e26a762-37f9-4982-ba67-8e6ce71c2c27
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625092992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.625092992
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_random.1541759720
Short name T287
Test name
Test status
Simulation time 251201279153 ps
CPU time 185.35 seconds
Started Aug 15 05:58:47 PM PDT 24
Finished Aug 15 06:01:52 PM PDT 24
Peak memory 191808 kb
Host smart-8d3239b6-fa54-4795-ad93-4363cff85a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541759720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1541759720
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3222084858
Short name T65
Test name
Test status
Simulation time 526357973446 ps
CPU time 557.11 seconds
Started Aug 15 05:59:01 PM PDT 24
Finished Aug 15 06:08:18 PM PDT 24
Peak memory 191816 kb
Host smart-abf89e8d-e51f-4ab3-abbb-9e06af8308f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222084858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3222084858
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random.2930048654
Short name T149
Test name
Test status
Simulation time 1229385277669 ps
CPU time 1247.04 seconds
Started Aug 15 05:58:05 PM PDT 24
Finished Aug 15 06:18:53 PM PDT 24
Peak memory 191804 kb
Host smart-3cac6866-7863-4450-a2d8-3d992f780f5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930048654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2930048654
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2898153876
Short name T78
Test name
Test status
Simulation time 34309079 ps
CPU time 0.84 seconds
Started Aug 15 05:57:36 PM PDT 24
Finished Aug 15 05:57:37 PM PDT 24
Peak memory 194012 kb
Host smart-216620df-1a45-49ef-bc88-06f43ae2d1c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898153876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2898153876
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3086850890
Short name T260
Test name
Test status
Simulation time 883095125498 ps
CPU time 447.54 seconds
Started Aug 15 05:58:08 PM PDT 24
Finished Aug 15 06:05:36 PM PDT 24
Peak memory 183400 kb
Host smart-b7540d8a-d2ea-4fd8-8d70-467671771011
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086850890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3086850890
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random.870348172
Short name T179
Test name
Test status
Simulation time 657987236297 ps
CPU time 188.66 seconds
Started Aug 15 05:58:01 PM PDT 24
Finished Aug 15 06:01:09 PM PDT 24
Peak memory 191792 kb
Host smart-5e5f4154-e3c3-4378-83ff-3aa595052b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870348172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.870348172
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.752677947
Short name T199
Test name
Test status
Simulation time 57752269667 ps
CPU time 194.42 seconds
Started Aug 15 05:59:20 PM PDT 24
Finished Aug 15 06:02:35 PM PDT 24
Peak memory 193128 kb
Host smart-7e52adc7-2a14-47c0-b0b2-bd8a04c0bf49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752677947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.752677947
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1137768436
Short name T402
Test name
Test status
Simulation time 124054180220 ps
CPU time 1060.03 seconds
Started Aug 15 05:59:29 PM PDT 24
Finished Aug 15 06:17:09 PM PDT 24
Peak memory 191824 kb
Host smart-1c21e382-d372-49a4-8af4-cc65edfd88af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137768436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1137768436
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1723390833
Short name T193
Test name
Test status
Simulation time 172449541273 ps
CPU time 284.49 seconds
Started Aug 15 05:59:29 PM PDT 24
Finished Aug 15 06:04:14 PM PDT 24
Peak memory 191820 kb
Host smart-102654aa-34f0-4fd0-a97c-b820b6f721e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723390833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1723390833
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.2701476304
Short name T136
Test name
Test status
Simulation time 469920503944 ps
CPU time 198.98 seconds
Started Aug 15 05:58:09 PM PDT 24
Finished Aug 15 06:01:28 PM PDT 24
Peak memory 191780 kb
Host smart-3f97a4e0-eaff-41c0-9ac1-d6ce4d28ba6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701476304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2701476304
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.3494215880
Short name T44
Test name
Test status
Simulation time 171808202456 ps
CPU time 612.71 seconds
Started Aug 15 05:59:28 PM PDT 24
Finished Aug 15 06:09:41 PM PDT 24
Peak memory 191696 kb
Host smart-7fd68dc8-3a65-4cf4-ba85-312d34be4a26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494215880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3494215880
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.330572401
Short name T222
Test name
Test status
Simulation time 582488674536 ps
CPU time 570.73 seconds
Started Aug 15 05:59:43 PM PDT 24
Finished Aug 15 06:09:14 PM PDT 24
Peak memory 191748 kb
Host smart-c3676757-6576-454c-885f-0f0ae2d2bbb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330572401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.330572401
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2380881804
Short name T72
Test name
Test status
Simulation time 407563747128 ps
CPU time 151.48 seconds
Started Aug 15 05:59:42 PM PDT 24
Finished Aug 15 06:02:13 PM PDT 24
Peak memory 191696 kb
Host smart-59babe62-d063-4e63-a959-838e4f2abcde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380881804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2380881804
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2592876304
Short name T308
Test name
Test status
Simulation time 160325001979 ps
CPU time 3083.46 seconds
Started Aug 15 05:59:49 PM PDT 24
Finished Aug 15 06:51:13 PM PDT 24
Peak memory 191784 kb
Host smart-2a710b4f-fdb5-4177-911b-7c71f939f248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592876304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2592876304
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2115703865
Short name T234
Test name
Test status
Simulation time 272847409005 ps
CPU time 489.67 seconds
Started Aug 15 05:58:18 PM PDT 24
Finished Aug 15 06:06:28 PM PDT 24
Peak memory 183548 kb
Host smart-572b8b49-f4c8-4787-8cb0-57f9620a5974
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115703865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2115703865
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1619483451
Short name T333
Test name
Test status
Simulation time 184924559953 ps
CPU time 159.18 seconds
Started Aug 15 05:58:24 PM PDT 24
Finished Aug 15 06:01:03 PM PDT 24
Peak memory 191776 kb
Host smart-eaee6848-9055-45d5-8fa2-40916718f385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619483451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1619483451
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3283203057
Short name T218
Test name
Test status
Simulation time 86983873839 ps
CPU time 563.78 seconds
Started Aug 15 05:58:35 PM PDT 24
Finished Aug 15 06:07:59 PM PDT 24
Peak memory 191716 kb
Host smart-9de475b4-d02c-4b5b-b29f-d8696d643591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283203057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3283203057
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_random.372773246
Short name T236
Test name
Test status
Simulation time 134197534209 ps
CPU time 608.87 seconds
Started Aug 15 05:58:53 PM PDT 24
Finished Aug 15 06:09:02 PM PDT 24
Peak memory 191796 kb
Host smart-c4da9dd9-0eaf-4b86-8a9f-e63c7aaa28ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372773246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.372773246
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random.3612108753
Short name T223
Test name
Test status
Simulation time 133689968220 ps
CPU time 355.59 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 06:04:08 PM PDT 24
Peak memory 191816 kb
Host smart-1d531458-d5af-4646-8e7f-321e1ef46da6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612108753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3612108753
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.271684157
Short name T276
Test name
Test status
Simulation time 161330211875 ps
CPU time 214.79 seconds
Started Aug 15 05:58:02 PM PDT 24
Finished Aug 15 06:01:36 PM PDT 24
Peak memory 191796 kb
Host smart-41c7d4fb-3592-43eb-a4db-c70a55ba9a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271684157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.271684157
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1817808255
Short name T302
Test name
Test status
Simulation time 438796423381 ps
CPU time 214.82 seconds
Started Aug 15 05:59:14 PM PDT 24
Finished Aug 15 06:02:49 PM PDT 24
Peak memory 191784 kb
Host smart-4be19b9e-0c98-42cf-a486-040701682116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817808255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1817808255
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3656529031
Short name T298
Test name
Test status
Simulation time 355662460308 ps
CPU time 608.56 seconds
Started Aug 15 05:57:54 PM PDT 24
Finished Aug 15 06:08:03 PM PDT 24
Peak memory 183568 kb
Host smart-30629301-7764-4379-ae2b-7daa4fb633dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656529031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3656529031
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.858277953
Short name T214
Test name
Test status
Simulation time 113265408256 ps
CPU time 77.62 seconds
Started Aug 15 05:58:03 PM PDT 24
Finished Aug 15 05:59:21 PM PDT 24
Peak memory 191952 kb
Host smart-fdd35149-1584-4639-adcb-d7d3b0141473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858277953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.858277953
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.1977483084
Short name T232
Test name
Test status
Simulation time 565306402500 ps
CPU time 289.22 seconds
Started Aug 15 05:59:16 PM PDT 24
Finished Aug 15 06:04:05 PM PDT 24
Peak memory 191716 kb
Host smart-8a69cf65-85ad-4e97-b5d4-32f5215e5cda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977483084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1977483084
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1736122011
Short name T148
Test name
Test status
Simulation time 56567045770 ps
CPU time 116.25 seconds
Started Aug 15 05:59:21 PM PDT 24
Finished Aug 15 06:01:17 PM PDT 24
Peak memory 195848 kb
Host smart-41ac4ac2-7eb2-4c11-a938-242bbee445de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736122011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1736122011
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3037967358
Short name T319
Test name
Test status
Simulation time 4632577230796 ps
CPU time 697.24 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 06:09:49 PM PDT 24
Peak memory 191756 kb
Host smart-777556f4-54a7-478d-ac05-9893f3593181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037967358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3037967358
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.3599973564
Short name T25
Test name
Test status
Simulation time 185039568819 ps
CPU time 141.99 seconds
Started Aug 15 05:59:29 PM PDT 24
Finished Aug 15 06:01:51 PM PDT 24
Peak memory 191684 kb
Host smart-16fe48ad-3e4a-4dc2-abab-ebf801b4d1f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599973564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3599973564
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.4170326277
Short name T21
Test name
Test status
Simulation time 60065837724 ps
CPU time 58.84 seconds
Started Aug 15 05:59:29 PM PDT 24
Finished Aug 15 06:00:28 PM PDT 24
Peak memory 183556 kb
Host smart-69747d67-671d-4106-8519-c0130c6d57fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170326277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.4170326277
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.758142007
Short name T277
Test name
Test status
Simulation time 296964586556 ps
CPU time 1680.09 seconds
Started Aug 15 05:59:30 PM PDT 24
Finished Aug 15 06:27:30 PM PDT 24
Peak memory 191780 kb
Host smart-7097c86b-9296-4147-aa7f-bf59b5efa4e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758142007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.758142007
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3220787532
Short name T255
Test name
Test status
Simulation time 256784215596 ps
CPU time 280.09 seconds
Started Aug 15 05:59:30 PM PDT 24
Finished Aug 15 06:04:10 PM PDT 24
Peak memory 191768 kb
Host smart-af48076a-b82b-4052-bd68-78087b2bc76c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220787532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3220787532
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3381686390
Short name T67
Test name
Test status
Simulation time 62349316746 ps
CPU time 77.22 seconds
Started Aug 15 05:58:08 PM PDT 24
Finished Aug 15 05:59:25 PM PDT 24
Peak memory 195760 kb
Host smart-10382a5f-abf3-478a-984f-e4859090d7ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381686390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3381686390
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/147.rv_timer_random.941938480
Short name T185
Test name
Test status
Simulation time 70337939636 ps
CPU time 135.26 seconds
Started Aug 15 05:59:28 PM PDT 24
Finished Aug 15 06:01:44 PM PDT 24
Peak memory 191716 kb
Host smart-c84257f5-f5e3-4cc8-a809-18b2cb565784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941938480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.941938480
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3075200636
Short name T131
Test name
Test status
Simulation time 81525184183 ps
CPU time 70.21 seconds
Started Aug 15 05:59:34 PM PDT 24
Finished Aug 15 06:00:44 PM PDT 24
Peak memory 183524 kb
Host smart-dbd55a76-7e9e-439b-a5d2-e81bdfc91d5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075200636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3075200636
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3262320834
Short name T290
Test name
Test status
Simulation time 1330483784627 ps
CPU time 347.67 seconds
Started Aug 15 05:59:43 PM PDT 24
Finished Aug 15 06:05:31 PM PDT 24
Peak memory 191816 kb
Host smart-b70b6b7f-a857-4b1c-8da2-bd223cc6d6cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262320834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3262320834
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1967688589
Short name T158
Test name
Test status
Simulation time 116413355408 ps
CPU time 338.01 seconds
Started Aug 15 05:59:43 PM PDT 24
Finished Aug 15 06:05:21 PM PDT 24
Peak memory 195336 kb
Host smart-d292c901-25d0-4f99-be3b-e937987a7387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967688589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1967688589
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1210128387
Short name T267
Test name
Test status
Simulation time 108933506350 ps
CPU time 56.99 seconds
Started Aug 15 05:58:10 PM PDT 24
Finished Aug 15 05:59:07 PM PDT 24
Peak memory 183548 kb
Host smart-8ba2f493-c846-45c6-a99e-75dd6e52c2f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210128387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1210128387
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.4205951336
Short name T211
Test name
Test status
Simulation time 5377130709787 ps
CPU time 1346.19 seconds
Started Aug 15 05:58:09 PM PDT 24
Finished Aug 15 06:20:35 PM PDT 24
Peak memory 191732 kb
Host smart-87480094-e463-4a2f-89c8-6b5ed4824d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205951336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.4205951336
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2231118255
Short name T206
Test name
Test status
Simulation time 55132191591 ps
CPU time 49.26 seconds
Started Aug 15 05:58:18 PM PDT 24
Finished Aug 15 05:59:07 PM PDT 24
Peak memory 183564 kb
Host smart-e13bfa96-4251-4d8d-9d9b-74ad10a20ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231118255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2231118255
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_random.283776821
Short name T306
Test name
Test status
Simulation time 130924950587 ps
CPU time 223.5 seconds
Started Aug 15 05:58:23 PM PDT 24
Finished Aug 15 06:02:07 PM PDT 24
Peak memory 191764 kb
Host smart-ece65e87-9e66-44bf-b80e-ed76c9fe577f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283776821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.283776821
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2463632180
Short name T159
Test name
Test status
Simulation time 3741448148067 ps
CPU time 1311.11 seconds
Started Aug 15 05:58:25 PM PDT 24
Finished Aug 15 06:20:17 PM PDT 24
Peak memory 183536 kb
Host smart-0addfda7-e2c5-464d-a1fa-c1dd04e6f7ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463632180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2463632180
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random.3298284361
Short name T323
Test name
Test status
Simulation time 67147737833 ps
CPU time 117.95 seconds
Started Aug 15 05:58:24 PM PDT 24
Finished Aug 15 06:00:22 PM PDT 24
Peak memory 191704 kb
Host smart-0194bf58-e531-45cf-a16d-54a9a776493c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298284361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3298284361
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3690257703
Short name T58
Test name
Test status
Simulation time 112315327508 ps
CPU time 38.34 seconds
Started Aug 15 05:58:25 PM PDT 24
Finished Aug 15 05:59:04 PM PDT 24
Peak memory 191724 kb
Host smart-ae22ad71-d3fe-40e3-9da0-2e306f7fa034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690257703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3690257703
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2828247598
Short name T113
Test name
Test status
Simulation time 807844876298 ps
CPU time 455.2 seconds
Started Aug 15 05:58:26 PM PDT 24
Finished Aug 15 06:06:02 PM PDT 24
Peak memory 183560 kb
Host smart-caff73fc-6b82-4682-9db8-683fb7e4dc00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828247598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2828247598
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2867791279
Short name T293
Test name
Test status
Simulation time 117609260270 ps
CPU time 137.71 seconds
Started Aug 15 05:58:40 PM PDT 24
Finished Aug 15 06:00:58 PM PDT 24
Peak memory 191768 kb
Host smart-ef7e0a6c-b4b3-43b6-8344-539ead00d97a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867791279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2867791279
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_random.3235983502
Short name T174
Test name
Test status
Simulation time 134571100777 ps
CPU time 105.03 seconds
Started Aug 15 05:58:42 PM PDT 24
Finished Aug 15 06:00:27 PM PDT 24
Peak memory 191792 kb
Host smart-39499a0f-7751-48f1-841b-6d5442ed2d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235983502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3235983502
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3829585006
Short name T253
Test name
Test status
Simulation time 361231420032 ps
CPU time 493.43 seconds
Started Aug 15 05:59:09 PM PDT 24
Finished Aug 15 06:07:23 PM PDT 24
Peak memory 191784 kb
Host smart-986822e8-ee20-417e-998a-399de6a148e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829585006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3829585006
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1621934990
Short name T160
Test name
Test status
Simulation time 163714414550 ps
CPU time 133.46 seconds
Started Aug 15 05:59:08 PM PDT 24
Finished Aug 15 06:01:22 PM PDT 24
Peak memory 191804 kb
Host smart-9e5fef64-2d34-464a-85e4-f0c483409552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621934990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1621934990
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.307057558
Short name T96
Test name
Test status
Simulation time 36017376 ps
CPU time 0.83 seconds
Started Aug 15 05:57:15 PM PDT 24
Finished Aug 15 05:57:16 PM PDT 24
Peak memory 193212 kb
Host smart-a51eddaa-4862-4499-9e75-2bc8286a0470
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307057558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.307057558
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.166744389
Short name T472
Test name
Test status
Simulation time 1043488464 ps
CPU time 2.73 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 05:57:16 PM PDT 24
Peak memory 194000 kb
Host smart-6329c7c6-0060-4d6c-a242-90c832d11b36
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166744389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.166744389
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.166851572
Short name T467
Test name
Test status
Simulation time 17791615 ps
CPU time 0.67 seconds
Started Aug 15 05:57:20 PM PDT 24
Finished Aug 15 05:57:21 PM PDT 24
Peak memory 194060 kb
Host smart-630f83d6-eddf-438f-8d70-8d4eb61c98a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166851572 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.166851572
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.463404818
Short name T54
Test name
Test status
Simulation time 26965361 ps
CPU time 0.64 seconds
Started Aug 15 05:57:17 PM PDT 24
Finished Aug 15 05:57:18 PM PDT 24
Peak memory 183372 kb
Host smart-f143bc89-5c6d-4fce-a45a-c68d3c14b128
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463404818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.463404818
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2368383429
Short name T533
Test name
Test status
Simulation time 14547940 ps
CPU time 0.56 seconds
Started Aug 15 05:57:19 PM PDT 24
Finished Aug 15 05:57:20 PM PDT 24
Peak memory 183232 kb
Host smart-834366b2-2004-42c4-b837-52046cbce485
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368383429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2368383429
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3743654157
Short name T568
Test name
Test status
Simulation time 52853658 ps
CPU time 0.63 seconds
Started Aug 15 05:57:18 PM PDT 24
Finished Aug 15 05:57:19 PM PDT 24
Peak memory 192644 kb
Host smart-45c27627-f35d-4096-9c04-8d7f0e51fb0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743654157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.3743654157
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2052145544
Short name T561
Test name
Test status
Simulation time 45182590 ps
CPU time 1.23 seconds
Started Aug 15 05:57:17 PM PDT 24
Finished Aug 15 05:57:18 PM PDT 24
Peak memory 198112 kb
Host smart-c8b1671f-c411-4089-bbc1-5568006f4674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052145544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2052145544
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2564521448
Short name T509
Test name
Test status
Simulation time 511941672 ps
CPU time 1.31 seconds
Started Aug 15 05:57:15 PM PDT 24
Finished Aug 15 05:57:17 PM PDT 24
Peak memory 184044 kb
Host smart-440549cd-15b4-4a84-a9e7-28d317c25293
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564521448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2564521448
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.999057437
Short name T570
Test name
Test status
Simulation time 34935096 ps
CPU time 0.86 seconds
Started Aug 15 05:57:14 PM PDT 24
Finished Aug 15 05:57:15 PM PDT 24
Peak memory 183332 kb
Host smart-5f496d73-dbc8-4150-8784-1cb763f19ccb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999057437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.999057437
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1918088452
Short name T34
Test name
Test status
Simulation time 144398289 ps
CPU time 1.58 seconds
Started Aug 15 05:57:16 PM PDT 24
Finished Aug 15 05:57:17 PM PDT 24
Peak memory 183540 kb
Host smart-661b6222-e855-4b17-b16d-680c3a607d9a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918088452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1918088452
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1881186921
Short name T491
Test name
Test status
Simulation time 11404552 ps
CPU time 0.53 seconds
Started Aug 15 05:57:18 PM PDT 24
Finished Aug 15 05:57:19 PM PDT 24
Peak memory 183368 kb
Host smart-ecbf255b-bcb2-4414-afbc-df010df1dd47
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881186921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1881186921
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1413460561
Short name T480
Test name
Test status
Simulation time 111191604 ps
CPU time 1.52 seconds
Started Aug 15 05:57:15 PM PDT 24
Finished Aug 15 05:57:17 PM PDT 24
Peak memory 198052 kb
Host smart-2c65af1c-4fae-4ac5-bf83-40780d87397c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413460561 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1413460561
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2834895582
Short name T81
Test name
Test status
Simulation time 166523823 ps
CPU time 0.6 seconds
Started Aug 15 05:57:17 PM PDT 24
Finished Aug 15 05:57:18 PM PDT 24
Peak memory 183380 kb
Host smart-30103a18-8900-4457-acd5-f4c666f417d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834895582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2834895582
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2953223515
Short name T571
Test name
Test status
Simulation time 59150150 ps
CPU time 0.56 seconds
Started Aug 15 05:57:22 PM PDT 24
Finished Aug 15 05:57:23 PM PDT 24
Peak memory 183220 kb
Host smart-4a29f403-70c9-4e55-9843-f29229384e25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953223515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2953223515
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4226736377
Short name T574
Test name
Test status
Simulation time 16155239 ps
CPU time 0.68 seconds
Started Aug 15 05:57:13 PM PDT 24
Finished Aug 15 05:57:14 PM PDT 24
Peak memory 192328 kb
Host smart-45eec021-acc5-4d94-a619-adb7e1ac074a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226736377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4226736377
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.572826439
Short name T473
Test name
Test status
Simulation time 97363565 ps
CPU time 1.34 seconds
Started Aug 15 05:57:17 PM PDT 24
Finished Aug 15 05:57:18 PM PDT 24
Peak memory 198092 kb
Host smart-f0ed90b2-8d23-4764-b709-7612d789dcc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572826439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.572826439
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4220367012
Short name T524
Test name
Test status
Simulation time 254982975 ps
CPU time 1.03 seconds
Started Aug 15 05:57:23 PM PDT 24
Finished Aug 15 05:57:24 PM PDT 24
Peak memory 195632 kb
Host smart-8d0d8ed7-1771-49bd-83b4-5308d4a44f78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220367012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.4220367012
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2835688773
Short name T516
Test name
Test status
Simulation time 36067031 ps
CPU time 0.99 seconds
Started Aug 15 05:57:35 PM PDT 24
Finished Aug 15 05:57:36 PM PDT 24
Peak memory 197808 kb
Host smart-b0db42cb-8015-4ada-8c32-3634f3aef709
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835688773 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2835688773
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1040270525
Short name T98
Test name
Test status
Simulation time 12899396 ps
CPU time 0.57 seconds
Started Aug 15 05:57:40 PM PDT 24
Finished Aug 15 05:57:40 PM PDT 24
Peak memory 183340 kb
Host smart-07d13f72-fc45-47b0-abb0-90f75d7988bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040270525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1040270525
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1713180934
Short name T556
Test name
Test status
Simulation time 29070379 ps
CPU time 0.57 seconds
Started Aug 15 05:57:34 PM PDT 24
Finished Aug 15 05:57:35 PM PDT 24
Peak memory 183272 kb
Host smart-142d722f-ab3f-4149-8571-e78e4236dbdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713180934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1713180934
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.413484659
Short name T552
Test name
Test status
Simulation time 22089838 ps
CPU time 0.61 seconds
Started Aug 15 05:57:39 PM PDT 24
Finished Aug 15 05:57:40 PM PDT 24
Peak memory 191972 kb
Host smart-e61ed8de-3f93-45a2-a542-f32a2ef6637d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413484659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.413484659
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.998313519
Short name T66
Test name
Test status
Simulation time 219594606 ps
CPU time 1.25 seconds
Started Aug 15 05:57:31 PM PDT 24
Finished Aug 15 05:57:33 PM PDT 24
Peak memory 198080 kb
Host smart-bf50684e-7e3b-43b4-b9ed-7071e2484d6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998313519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.998313519
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1463840130
Short name T492
Test name
Test status
Simulation time 657804610 ps
CPU time 1.39 seconds
Started Aug 15 05:57:32 PM PDT 24
Finished Aug 15 05:57:33 PM PDT 24
Peak memory 183844 kb
Host smart-6c37a714-58a3-4d57-9393-07b573ebb29c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463840130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1463840130
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3874812905
Short name T502
Test name
Test status
Simulation time 78055657 ps
CPU time 0.64 seconds
Started Aug 15 05:57:37 PM PDT 24
Finished Aug 15 05:57:38 PM PDT 24
Peak memory 195108 kb
Host smart-d7166c2c-4f4a-4f2a-b8be-0eb664610140
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874812905 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3874812905
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3684409767
Short name T549
Test name
Test status
Simulation time 13004915 ps
CPU time 0.55 seconds
Started Aug 15 05:57:40 PM PDT 24
Finished Aug 15 05:57:40 PM PDT 24
Peak memory 183000 kb
Host smart-81e62002-69d1-4a5f-bc5f-b14052760669
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684409767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3684409767
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2703696317
Short name T453
Test name
Test status
Simulation time 13064935 ps
CPU time 0.58 seconds
Started Aug 15 05:57:35 PM PDT 24
Finished Aug 15 05:57:36 PM PDT 24
Peak memory 183216 kb
Host smart-f2f6d231-eed0-4890-aee5-4b1858bab4b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703696317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2703696317
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.502972855
Short name T456
Test name
Test status
Simulation time 105483157 ps
CPU time 1.71 seconds
Started Aug 15 05:57:38 PM PDT 24
Finished Aug 15 05:57:40 PM PDT 24
Peak memory 198064 kb
Host smart-191e79da-b3c8-4a10-bb26-93194180ef42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502972855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.502972855
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3757503440
Short name T522
Test name
Test status
Simulation time 273926561 ps
CPU time 1.14 seconds
Started Aug 15 05:57:38 PM PDT 24
Finished Aug 15 05:57:39 PM PDT 24
Peak memory 195932 kb
Host smart-56e48e45-f877-4ba5-9f74-a3303ca888d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757503440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3757503440
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3473092144
Short name T548
Test name
Test status
Simulation time 26783670 ps
CPU time 0.8 seconds
Started Aug 15 05:57:39 PM PDT 24
Finished Aug 15 05:57:40 PM PDT 24
Peak memory 195444 kb
Host smart-628406ef-1da5-4add-bb0e-55030595da3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473092144 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3473092144
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.214378223
Short name T559
Test name
Test status
Simulation time 13383118 ps
CPU time 0.55 seconds
Started Aug 15 05:57:38 PM PDT 24
Finished Aug 15 05:57:39 PM PDT 24
Peak memory 183332 kb
Host smart-08e7b3d1-09e2-46d5-81e3-86f7facda208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214378223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.214378223
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2751622844
Short name T514
Test name
Test status
Simulation time 234169397 ps
CPU time 0.56 seconds
Started Aug 15 05:57:37 PM PDT 24
Finished Aug 15 05:57:38 PM PDT 24
Peak memory 183272 kb
Host smart-dd8859a7-f360-44e4-b702-7612771df7fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751622844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2751622844
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1074029620
Short name T581
Test name
Test status
Simulation time 57480249 ps
CPU time 0.71 seconds
Started Aug 15 05:57:35 PM PDT 24
Finished Aug 15 05:57:36 PM PDT 24
Peak memory 193700 kb
Host smart-81605d1f-1e36-469a-8f9d-3cc3642b0b25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074029620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1074029620
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2791021966
Short name T519
Test name
Test status
Simulation time 77969918 ps
CPU time 1.54 seconds
Started Aug 15 05:57:34 PM PDT 24
Finished Aug 15 05:57:36 PM PDT 24
Peak memory 198108 kb
Host smart-a481afa8-2160-41fc-b4e2-207b865b5f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791021966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2791021966
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1855124372
Short name T494
Test name
Test status
Simulation time 427017112 ps
CPU time 1.4 seconds
Started Aug 15 05:57:37 PM PDT 24
Finished Aug 15 05:57:39 PM PDT 24
Peak memory 183836 kb
Host smart-01a7d0bb-c63d-4050-8e9d-42ca047f979a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855124372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1855124372
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.512748177
Short name T534
Test name
Test status
Simulation time 188154953 ps
CPU time 1.07 seconds
Started Aug 15 05:57:36 PM PDT 24
Finished Aug 15 05:57:37 PM PDT 24
Peak memory 197656 kb
Host smart-232085bf-c37c-41e0-8958-4801b47e49e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512748177 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.512748177
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1662546497
Short name T505
Test name
Test status
Simulation time 20541443 ps
CPU time 0.53 seconds
Started Aug 15 05:57:36 PM PDT 24
Finished Aug 15 05:57:36 PM PDT 24
Peak memory 182708 kb
Host smart-9c9070d4-8be4-4386-8717-33501f4a4b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662546497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1662546497
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4259520772
Short name T93
Test name
Test status
Simulation time 26940910 ps
CPU time 0.69 seconds
Started Aug 15 05:57:40 PM PDT 24
Finished Aug 15 05:57:41 PM PDT 24
Peak memory 192716 kb
Host smart-f68c808c-bb5e-4880-8c92-351f0e6e17a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259520772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.4259520772
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2190937977
Short name T495
Test name
Test status
Simulation time 47752202 ps
CPU time 1.99 seconds
Started Aug 15 05:57:37 PM PDT 24
Finished Aug 15 05:57:40 PM PDT 24
Peak memory 198164 kb
Host smart-76824ab6-5734-461b-a2d5-7c5974f7c194
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190937977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2190937977
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3305572269
Short name T521
Test name
Test status
Simulation time 88947307 ps
CPU time 1.03 seconds
Started Aug 15 05:57:38 PM PDT 24
Finished Aug 15 05:57:39 PM PDT 24
Peak memory 195272 kb
Host smart-53c55e4b-a5f4-420f-b776-beb4a157f759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305572269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3305572269
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.506401714
Short name T496
Test name
Test status
Simulation time 35965123 ps
CPU time 0.91 seconds
Started Aug 15 05:57:38 PM PDT 24
Finished Aug 15 05:57:39 PM PDT 24
Peak memory 197200 kb
Host smart-0dbbdce7-763f-4e25-bd34-59a2f90c1af1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506401714 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.506401714
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.634755594
Short name T86
Test name
Test status
Simulation time 24304350 ps
CPU time 0.55 seconds
Started Aug 15 05:57:37 PM PDT 24
Finished Aug 15 05:57:38 PM PDT 24
Peak memory 183172 kb
Host smart-834e95b9-13a1-4190-9d68-483867fad333
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634755594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.634755594
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1842327771
Short name T484
Test name
Test status
Simulation time 62028713 ps
CPU time 0.56 seconds
Started Aug 15 05:57:39 PM PDT 24
Finished Aug 15 05:57:40 PM PDT 24
Peak memory 183264 kb
Host smart-a9b1b496-e1e7-4ccf-afba-8fb88c34d729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842327771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1842327771
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.997712294
Short name T82
Test name
Test status
Simulation time 108581918 ps
CPU time 0.71 seconds
Started Aug 15 05:57:39 PM PDT 24
Finished Aug 15 05:57:40 PM PDT 24
Peak memory 192904 kb
Host smart-8524ba88-63b0-4d2b-a7c1-834dd7386622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997712294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.997712294
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3817254038
Short name T458
Test name
Test status
Simulation time 1021135229 ps
CPU time 2.31 seconds
Started Aug 15 05:57:35 PM PDT 24
Finished Aug 15 05:57:37 PM PDT 24
Peak memory 198044 kb
Host smart-ade180e7-464f-44f0-a7d5-dddfd44978ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817254038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3817254038
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2475312370
Short name T100
Test name
Test status
Simulation time 210708568 ps
CPU time 1.4 seconds
Started Aug 15 05:57:37 PM PDT 24
Finished Aug 15 05:57:39 PM PDT 24
Peak memory 195904 kb
Host smart-7553a5b5-f5ac-40ef-b53c-d05e8709af49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475312370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2475312370
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1591215234
Short name T501
Test name
Test status
Simulation time 47737935 ps
CPU time 1.2 seconds
Started Aug 15 05:57:47 PM PDT 24
Finished Aug 15 05:57:48 PM PDT 24
Peak memory 197908 kb
Host smart-e2bd0e3b-817d-47a4-8913-1e0f5e43d981
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591215234 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1591215234
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.292187882
Short name T481
Test name
Test status
Simulation time 31996653 ps
CPU time 0.56 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 183008 kb
Host smart-bda447a1-ce06-4730-b396-3f69dbb224dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292187882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.292187882
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2853925423
Short name T463
Test name
Test status
Simulation time 31426472 ps
CPU time 0.53 seconds
Started Aug 15 05:57:36 PM PDT 24
Finished Aug 15 05:57:36 PM PDT 24
Peak memory 183172 kb
Host smart-aef1e6f0-ba72-4fca-b7b4-13ea0c560ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853925423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2853925423
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.752087404
Short name T577
Test name
Test status
Simulation time 20371396 ps
CPU time 0.63 seconds
Started Aug 15 05:57:43 PM PDT 24
Finished Aug 15 05:57:44 PM PDT 24
Peak memory 192316 kb
Host smart-98a81899-ca4b-4e9f-9c67-3d2b97d5d0ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752087404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.752087404
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3022973412
Short name T580
Test name
Test status
Simulation time 95597350 ps
CPU time 1.78 seconds
Started Aug 15 05:57:36 PM PDT 24
Finished Aug 15 05:57:38 PM PDT 24
Peak memory 198152 kb
Host smart-b5c11ec4-2807-4bba-a2fb-f6c9e5a236e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022973412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3022973412
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1563902895
Short name T553
Test name
Test status
Simulation time 52658667 ps
CPU time 0.88 seconds
Started Aug 15 05:57:37 PM PDT 24
Finished Aug 15 05:57:38 PM PDT 24
Peak memory 194092 kb
Host smart-31e6ddca-37de-415e-b7da-2255ba24f038
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563902895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1563902895
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.584378499
Short name T508
Test name
Test status
Simulation time 31203507 ps
CPU time 1.33 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 198152 kb
Host smart-0216887d-ef21-421e-b685-02babf12e2a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584378499 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.584378499
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.687997265
Short name T33
Test name
Test status
Simulation time 52285558 ps
CPU time 0.54 seconds
Started Aug 15 05:57:49 PM PDT 24
Finished Aug 15 05:57:49 PM PDT 24
Peak memory 183380 kb
Host smart-51b1d00d-38d9-4b5c-85ab-568fffb538e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687997265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.687997265
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2111217117
Short name T485
Test name
Test status
Simulation time 19089657 ps
CPU time 0.56 seconds
Started Aug 15 05:57:44 PM PDT 24
Finished Aug 15 05:57:44 PM PDT 24
Peak memory 183292 kb
Host smart-8f5515fa-5863-4cc4-98d5-1442a2a6d3d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111217117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2111217117
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1371363109
Short name T528
Test name
Test status
Simulation time 44920603 ps
CPU time 0.76 seconds
Started Aug 15 05:57:44 PM PDT 24
Finished Aug 15 05:57:45 PM PDT 24
Peak memory 194064 kb
Host smart-e09805ef-6335-4d00-80da-e459fb81f632
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371363109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1371363109
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1791667908
Short name T454
Test name
Test status
Simulation time 24306718 ps
CPU time 1.3 seconds
Started Aug 15 05:57:44 PM PDT 24
Finished Aug 15 05:57:45 PM PDT 24
Peak memory 198116 kb
Host smart-4965a2da-bada-4b64-8bb7-3e93a1503a75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791667908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1791667908
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2031585675
Short name T32
Test name
Test status
Simulation time 82744438 ps
CPU time 1.12 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 183772 kb
Host smart-819ce407-3eb9-4acf-bf2a-4ac352ca9193
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031585675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2031585675
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1569407426
Short name T482
Test name
Test status
Simulation time 13732528 ps
CPU time 0.68 seconds
Started Aug 15 05:57:47 PM PDT 24
Finished Aug 15 05:57:48 PM PDT 24
Peak memory 194320 kb
Host smart-c39e3844-3cf6-4460-a5f4-e3550f17b108
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569407426 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1569407426
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3925442095
Short name T488
Test name
Test status
Simulation time 14337481 ps
CPU time 0.58 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 183388 kb
Host smart-bf2502a1-ca44-4416-a77e-9f7cc4cf990a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925442095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3925442095
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1367951952
Short name T529
Test name
Test status
Simulation time 15284616 ps
CPU time 0.58 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 182700 kb
Host smart-ad60cd3d-8df0-44e4-b6ec-e30dc0f62e8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367951952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1367951952
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2823810888
Short name T35
Test name
Test status
Simulation time 66222709 ps
CPU time 0.75 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 193936 kb
Host smart-9a80b4f1-b91f-490c-b5fa-ffa7090255ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823810888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2823810888
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.19771077
Short name T486
Test name
Test status
Simulation time 132466599 ps
CPU time 1.82 seconds
Started Aug 15 05:57:49 PM PDT 24
Finished Aug 15 05:57:51 PM PDT 24
Peak memory 198060 kb
Host smart-10ddc89a-2184-458b-8453-34bf682971bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19771077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.19771077
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.534684938
Short name T489
Test name
Test status
Simulation time 63870682 ps
CPU time 0.95 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 197176 kb
Host smart-cca58b52-9e0b-483e-b0d1-897a046bc122
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534684938 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.534684938
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.465941891
Short name T563
Test name
Test status
Simulation time 18554762 ps
CPU time 0.54 seconds
Started Aug 15 05:57:44 PM PDT 24
Finished Aug 15 05:57:45 PM PDT 24
Peak memory 182936 kb
Host smart-64d11c63-3094-426b-9d34-d2d535ecaec2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465941891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.465941891
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1659735503
Short name T499
Test name
Test status
Simulation time 18475328 ps
CPU time 0.57 seconds
Started Aug 15 05:57:44 PM PDT 24
Finished Aug 15 05:57:45 PM PDT 24
Peak memory 183224 kb
Host smart-d44b1da8-3ccd-49ac-8869-c819ce3d5925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659735503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1659735503
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1875065291
Short name T569
Test name
Test status
Simulation time 17367644 ps
CPU time 0.8 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 194224 kb
Host smart-edabac49-7e05-4cf3-9ff4-7de748592703
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875065291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1875065291
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3120764203
Short name T532
Test name
Test status
Simulation time 33447646 ps
CPU time 1.67 seconds
Started Aug 15 05:57:49 PM PDT 24
Finished Aug 15 05:57:51 PM PDT 24
Peak memory 198116 kb
Host smart-946a51b2-28f0-45de-ae3d-f259ecd7aa3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120764203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3120764203
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1513740171
Short name T520
Test name
Test status
Simulation time 55863043 ps
CPU time 0.79 seconds
Started Aug 15 05:57:49 PM PDT 24
Finished Aug 15 05:57:50 PM PDT 24
Peak memory 196880 kb
Host smart-0dc8b3c1-7e3e-4a05-8494-ac28e7ad2e03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513740171 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1513740171
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1698610033
Short name T55
Test name
Test status
Simulation time 71820617 ps
CPU time 0.6 seconds
Started Aug 15 05:57:47 PM PDT 24
Finished Aug 15 05:57:48 PM PDT 24
Peak memory 183356 kb
Host smart-cc7c2130-b847-42fb-ad8a-eec78d3ce9d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698610033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1698610033
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3775660607
Short name T566
Test name
Test status
Simulation time 49186240 ps
CPU time 0.56 seconds
Started Aug 15 05:57:46 PM PDT 24
Finished Aug 15 05:57:47 PM PDT 24
Peak memory 183204 kb
Host smart-49d78a6c-e96f-41dd-a4ab-7a5995715040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775660607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3775660607
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3102866192
Short name T56
Test name
Test status
Simulation time 76756967 ps
CPU time 0.84 seconds
Started Aug 15 05:57:43 PM PDT 24
Finished Aug 15 05:57:44 PM PDT 24
Peak memory 194656 kb
Host smart-4a667f30-be40-4fe9-acfb-8ca2080247be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102866192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3102866192
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.4135373467
Short name T547
Test name
Test status
Simulation time 113652124 ps
CPU time 1.55 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:47 PM PDT 24
Peak memory 191792 kb
Host smart-c524bf2e-e129-42b6-991e-2133beb7039b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135373467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.4135373467
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1993003415
Short name T517
Test name
Test status
Simulation time 104909618 ps
CPU time 1.15 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 195796 kb
Host smart-aadf58c2-9a66-4703-bef8-ff984ab2be21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993003415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1993003415
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2304225583
Short name T88
Test name
Test status
Simulation time 30587592 ps
CPU time 0.63 seconds
Started Aug 15 05:57:22 PM PDT 24
Finished Aug 15 05:57:22 PM PDT 24
Peak memory 183328 kb
Host smart-a6c4ab28-c880-4513-b0b3-8625d307fd93
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304225583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2304225583
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3446947197
Short name T537
Test name
Test status
Simulation time 40241620 ps
CPU time 1.42 seconds
Started Aug 15 05:57:22 PM PDT 24
Finished Aug 15 05:57:23 PM PDT 24
Peak memory 194480 kb
Host smart-e9548a77-79a8-4bce-96bc-43c739dceaab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446947197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3446947197
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3619238258
Short name T97
Test name
Test status
Simulation time 35356803 ps
CPU time 0.55 seconds
Started Aug 15 05:57:24 PM PDT 24
Finished Aug 15 05:57:24 PM PDT 24
Peak memory 183364 kb
Host smart-196e8cf1-966b-4b41-82d4-ce86778c07b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619238258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3619238258
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.67632478
Short name T555
Test name
Test status
Simulation time 131732734 ps
CPU time 0.76 seconds
Started Aug 15 05:57:24 PM PDT 24
Finished Aug 15 05:57:25 PM PDT 24
Peak memory 196044 kb
Host smart-60c8aab0-4204-4e37-aaac-7f65d05caa4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67632478 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.67632478
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1609365162
Short name T80
Test name
Test status
Simulation time 13164341 ps
CPU time 0.61 seconds
Started Aug 15 05:57:22 PM PDT 24
Finished Aug 15 05:57:23 PM PDT 24
Peak memory 183384 kb
Host smart-94a9f958-bf6f-4c20-b2ed-0a5d8fef8c94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609365162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1609365162
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3095360074
Short name T523
Test name
Test status
Simulation time 12913386 ps
CPU time 0.56 seconds
Started Aug 15 05:57:21 PM PDT 24
Finished Aug 15 05:57:22 PM PDT 24
Peak memory 182704 kb
Host smart-824f5a84-6a7a-4313-9785-c841edd914bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095360074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3095360074
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.926702293
Short name T91
Test name
Test status
Simulation time 39446438 ps
CPU time 0.77 seconds
Started Aug 15 05:57:24 PM PDT 24
Finished Aug 15 05:57:24 PM PDT 24
Peak memory 192256 kb
Host smart-dce11c30-d85b-4d9e-bef9-cd237d370c00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926702293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.926702293
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2438924972
Short name T562
Test name
Test status
Simulation time 209425613 ps
CPU time 1.4 seconds
Started Aug 15 05:57:16 PM PDT 24
Finished Aug 15 05:57:17 PM PDT 24
Peak memory 198140 kb
Host smart-5dd3ced9-2fa4-4414-81f3-0ac7b82ac401
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438924972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2438924972
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2377162050
Short name T542
Test name
Test status
Simulation time 210823281 ps
CPU time 1.36 seconds
Started Aug 15 05:57:22 PM PDT 24
Finished Aug 15 05:57:24 PM PDT 24
Peak memory 195940 kb
Host smart-e94ccd11-e7a8-4016-8041-d402667cc041
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377162050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2377162050
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.174461075
Short name T526
Test name
Test status
Simulation time 16019610 ps
CPU time 0.59 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 183192 kb
Host smart-22531dad-6080-48d1-98be-eb08615fb014
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174461075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.174461075
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.763080458
Short name T550
Test name
Test status
Simulation time 39729137 ps
CPU time 0.6 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 183248 kb
Host smart-2d9bc807-0cd3-49a3-b5bb-7745eebcb52d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763080458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.763080458
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1852490169
Short name T452
Test name
Test status
Simulation time 13229422 ps
CPU time 0.55 seconds
Started Aug 15 05:57:47 PM PDT 24
Finished Aug 15 05:57:47 PM PDT 24
Peak memory 183200 kb
Host smart-0136eecb-7137-48b0-a839-e961fcfb6f21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852490169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1852490169
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3699279302
Short name T500
Test name
Test status
Simulation time 177859987 ps
CPU time 0.58 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 183252 kb
Host smart-9a6b2670-9b97-49c1-bc2e-c8dd2c3a3198
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699279302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3699279302
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3682008756
Short name T461
Test name
Test status
Simulation time 14342181 ps
CPU time 0.56 seconds
Started Aug 15 05:57:45 PM PDT 24
Finished Aug 15 05:57:46 PM PDT 24
Peak memory 182676 kb
Host smart-170bc00e-b09c-4297-92f7-468f7b9e8091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682008756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3682008756
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3720723454
Short name T576
Test name
Test status
Simulation time 42045759 ps
CPU time 0.54 seconds
Started Aug 15 05:57:57 PM PDT 24
Finished Aug 15 05:57:58 PM PDT 24
Peak memory 182924 kb
Host smart-28a7b312-531a-4af0-bbc9-aa856336d69a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720723454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3720723454
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3619060995
Short name T462
Test name
Test status
Simulation time 15127273 ps
CPU time 0.6 seconds
Started Aug 15 05:57:57 PM PDT 24
Finished Aug 15 05:57:57 PM PDT 24
Peak memory 183164 kb
Host smart-0cc51927-6f40-403e-817c-db65edacd3d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619060995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3619060995
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.532176492
Short name T479
Test name
Test status
Simulation time 29258316 ps
CPU time 0.58 seconds
Started Aug 15 05:57:54 PM PDT 24
Finished Aug 15 05:57:55 PM PDT 24
Peak memory 183252 kb
Host smart-6daaf5e8-479a-44e5-bc42-6728d167adb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532176492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.532176492
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2745320505
Short name T459
Test name
Test status
Simulation time 40534103 ps
CPU time 0.53 seconds
Started Aug 15 05:57:54 PM PDT 24
Finished Aug 15 05:57:55 PM PDT 24
Peak memory 182896 kb
Host smart-27c0184a-f1bd-4d32-8c9b-da061b23041c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745320505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2745320505
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2044593001
Short name T465
Test name
Test status
Simulation time 222131476 ps
CPU time 0.55 seconds
Started Aug 15 05:57:57 PM PDT 24
Finished Aug 15 05:57:58 PM PDT 24
Peak memory 183140 kb
Host smart-4d945674-f62f-4eec-8794-6619d263182f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044593001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2044593001
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2408105149
Short name T85
Test name
Test status
Simulation time 55131498 ps
CPU time 0.73 seconds
Started Aug 15 05:57:21 PM PDT 24
Finished Aug 15 05:57:22 PM PDT 24
Peak memory 183376 kb
Host smart-b5e3e9f9-294e-4099-a4bf-08e19a415f4f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408105149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2408105149
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3456814732
Short name T493
Test name
Test status
Simulation time 491087294 ps
CPU time 1.57 seconds
Started Aug 15 05:57:21 PM PDT 24
Finished Aug 15 05:57:23 PM PDT 24
Peak memory 191712 kb
Host smart-b5007853-bcb6-4c86-9556-71dc2ff89688
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456814732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3456814732
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2421569375
Short name T478
Test name
Test status
Simulation time 15149378 ps
CPU time 0.57 seconds
Started Aug 15 05:57:22 PM PDT 24
Finished Aug 15 05:57:23 PM PDT 24
Peak memory 183348 kb
Host smart-a5a958d7-97f6-4be5-b6f7-820f6aebf2e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421569375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2421569375
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2411789417
Short name T455
Test name
Test status
Simulation time 18606299 ps
CPU time 0.91 seconds
Started Aug 15 05:57:22 PM PDT 24
Finished Aug 15 05:57:24 PM PDT 24
Peak memory 197904 kb
Host smart-cd3b493d-d749-4537-9e52-66944eeb3201
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411789417 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2411789417
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2759853207
Short name T95
Test name
Test status
Simulation time 11312753 ps
CPU time 0.57 seconds
Started Aug 15 05:57:22 PM PDT 24
Finished Aug 15 05:57:23 PM PDT 24
Peak memory 183380 kb
Host smart-c1538ca4-19a0-45f2-ac5e-87cfe1add2e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759853207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2759853207
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3690077405
Short name T545
Test name
Test status
Simulation time 11624347 ps
CPU time 0.58 seconds
Started Aug 15 05:57:22 PM PDT 24
Finished Aug 15 05:57:22 PM PDT 24
Peak memory 183212 kb
Host smart-47f93248-95ef-408c-9484-ee112115d8ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690077405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3690077405
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1138767829
Short name T539
Test name
Test status
Simulation time 13151063 ps
CPU time 0.6 seconds
Started Aug 15 05:57:24 PM PDT 24
Finished Aug 15 05:57:24 PM PDT 24
Peak memory 192584 kb
Host smart-f1556f84-888b-4d42-9c69-f1f5f848f06e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138767829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1138767829
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1510783436
Short name T506
Test name
Test status
Simulation time 100704448 ps
CPU time 1.71 seconds
Started Aug 15 05:57:22 PM PDT 24
Finished Aug 15 05:57:24 PM PDT 24
Peak memory 198080 kb
Host smart-cff849ec-ff17-4e0d-ad1b-3b9a7ac1942c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510783436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1510783436
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2077887043
Short name T503
Test name
Test status
Simulation time 617467831 ps
CPU time 1.03 seconds
Started Aug 15 05:57:20 PM PDT 24
Finished Aug 15 05:57:22 PM PDT 24
Peak memory 195584 kb
Host smart-5e9006ff-ac15-42f5-8900-d2b063841cf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077887043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2077887043
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3134785698
Short name T565
Test name
Test status
Simulation time 19559969 ps
CPU time 0.53 seconds
Started Aug 15 05:57:56 PM PDT 24
Finished Aug 15 05:57:57 PM PDT 24
Peak memory 182924 kb
Host smart-df8faa51-7e0d-48a7-82aa-5f7e18e45d75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134785698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3134785698
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.396692519
Short name T498
Test name
Test status
Simulation time 78515592 ps
CPU time 0.55 seconds
Started Aug 15 05:57:56 PM PDT 24
Finished Aug 15 05:57:57 PM PDT 24
Peak memory 183288 kb
Host smart-b3bcaa7a-15bc-416e-afac-f9faf4d5ea8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396692519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.396692519
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3188666769
Short name T518
Test name
Test status
Simulation time 18938118 ps
CPU time 0.6 seconds
Started Aug 15 05:57:57 PM PDT 24
Finished Aug 15 05:57:58 PM PDT 24
Peak memory 183180 kb
Host smart-c355dfbc-afe2-42f7-96b9-7ec431a325fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188666769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3188666769
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3481116789
Short name T536
Test name
Test status
Simulation time 18638353 ps
CPU time 0.56 seconds
Started Aug 15 05:57:54 PM PDT 24
Finished Aug 15 05:57:55 PM PDT 24
Peak memory 183108 kb
Host smart-1adcbeab-d8f6-44d4-9469-a2939b49eb72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481116789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3481116789
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2309596704
Short name T507
Test name
Test status
Simulation time 71529098 ps
CPU time 0.55 seconds
Started Aug 15 05:57:55 PM PDT 24
Finished Aug 15 05:57:56 PM PDT 24
Peak memory 183240 kb
Host smart-b603d8b0-1a70-4296-b09b-0608df5ee645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309596704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2309596704
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.315394040
Short name T540
Test name
Test status
Simulation time 14620198 ps
CPU time 0.57 seconds
Started Aug 15 05:57:52 PM PDT 24
Finished Aug 15 05:57:53 PM PDT 24
Peak memory 182728 kb
Host smart-f0799ede-ef48-44c8-a3ef-8dc71852e4f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315394040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.315394040
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.365292452
Short name T531
Test name
Test status
Simulation time 67793065 ps
CPU time 0.54 seconds
Started Aug 15 05:57:56 PM PDT 24
Finished Aug 15 05:57:57 PM PDT 24
Peak memory 183280 kb
Host smart-d92818d8-aae5-4404-9191-418e816970d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365292452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.365292452
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2348224955
Short name T468
Test name
Test status
Simulation time 12015521 ps
CPU time 0.54 seconds
Started Aug 15 05:57:55 PM PDT 24
Finished Aug 15 05:57:55 PM PDT 24
Peak memory 182700 kb
Host smart-83e0e7fa-f2fb-49e9-a4b8-459d4c27a3d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348224955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2348224955
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.580697973
Short name T525
Test name
Test status
Simulation time 14960725 ps
CPU time 0.57 seconds
Started Aug 15 05:57:58 PM PDT 24
Finished Aug 15 05:57:59 PM PDT 24
Peak memory 183160 kb
Host smart-1afd73ec-b000-469c-9600-629d072439d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580697973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.580697973
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1816319803
Short name T573
Test name
Test status
Simulation time 13090813 ps
CPU time 0.61 seconds
Started Aug 15 05:57:56 PM PDT 24
Finished Aug 15 05:57:57 PM PDT 24
Peak memory 183180 kb
Host smart-d812cd1a-1d08-4a70-a3c0-61d5d78ca69a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816319803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1816319803
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1891740311
Short name T83
Test name
Test status
Simulation time 26343697 ps
CPU time 0.74 seconds
Started Aug 15 05:57:29 PM PDT 24
Finished Aug 15 05:57:30 PM PDT 24
Peak memory 183308 kb
Host smart-5df5bdec-bf20-4b2e-b1b8-88ba3829582a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891740311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1891740311
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2765324317
Short name T470
Test name
Test status
Simulation time 37535846 ps
CPU time 1.42 seconds
Started Aug 15 05:57:30 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 191756 kb
Host smart-86c983a3-7b87-4c83-b591-542ca6f63adf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765324317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2765324317
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2089863900
Short name T89
Test name
Test status
Simulation time 57017046 ps
CPU time 0.64 seconds
Started Aug 15 05:57:29 PM PDT 24
Finished Aug 15 05:57:30 PM PDT 24
Peak memory 183376 kb
Host smart-8e112e83-111f-4435-9c10-291ce81f7266
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089863900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2089863900
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3582519017
Short name T527
Test name
Test status
Simulation time 109830751 ps
CPU time 1.38 seconds
Started Aug 15 05:57:28 PM PDT 24
Finished Aug 15 05:57:29 PM PDT 24
Peak memory 198108 kb
Host smart-4a23829b-8765-4bf2-87f7-bb7887019edd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582519017 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3582519017
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3267119387
Short name T551
Test name
Test status
Simulation time 45367055 ps
CPU time 0.57 seconds
Started Aug 15 05:57:32 PM PDT 24
Finished Aug 15 05:57:33 PM PDT 24
Peak memory 183108 kb
Host smart-bdb2f655-4f5f-4d7b-a907-e169a82eae41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267119387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3267119387
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3944743627
Short name T515
Test name
Test status
Simulation time 14164138 ps
CPU time 0.57 seconds
Started Aug 15 05:57:32 PM PDT 24
Finished Aug 15 05:57:33 PM PDT 24
Peak memory 183208 kb
Host smart-b79f9496-ee9e-42e1-82bf-41f825af0270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944743627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3944743627
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3449657917
Short name T92
Test name
Test status
Simulation time 23092018 ps
CPU time 0.77 seconds
Started Aug 15 05:57:30 PM PDT 24
Finished Aug 15 05:57:31 PM PDT 24
Peak memory 194036 kb
Host smart-89a95047-b8ad-488f-a66a-7c1b32cdf29a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449657917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3449657917
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3833321900
Short name T510
Test name
Test status
Simulation time 36685872 ps
CPU time 1.86 seconds
Started Aug 15 05:57:21 PM PDT 24
Finished Aug 15 05:57:23 PM PDT 24
Peak memory 198076 kb
Host smart-34e93562-17db-4530-bee5-e40371aae8fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833321900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3833321900
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.75467116
Short name T575
Test name
Test status
Simulation time 382817874 ps
CPU time 1.43 seconds
Started Aug 15 05:57:29 PM PDT 24
Finished Aug 15 05:57:31 PM PDT 24
Peak memory 196068 kb
Host smart-48621b7a-6910-4ffc-aa37-595d5bdc5ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75467116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg
_err.75467116
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.993333126
Short name T560
Test name
Test status
Simulation time 103674034 ps
CPU time 0.59 seconds
Started Aug 15 05:57:55 PM PDT 24
Finished Aug 15 05:57:56 PM PDT 24
Peak memory 183276 kb
Host smart-c65ef481-40f7-47e1-96a9-48cd96962ac1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993333126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.993333126
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.839054956
Short name T535
Test name
Test status
Simulation time 52872733 ps
CPU time 0.57 seconds
Started Aug 15 05:57:57 PM PDT 24
Finished Aug 15 05:57:58 PM PDT 24
Peak memory 183180 kb
Host smart-18371bf6-475b-4f56-baea-7c8f9a133334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839054956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.839054956
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1044607195
Short name T477
Test name
Test status
Simulation time 12797988 ps
CPU time 0.59 seconds
Started Aug 15 05:57:57 PM PDT 24
Finished Aug 15 05:57:57 PM PDT 24
Peak memory 183248 kb
Host smart-9827ddc8-044b-465e-a7ba-bf28fa575a82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044607195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1044607195
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.514195474
Short name T567
Test name
Test status
Simulation time 16964669 ps
CPU time 0.55 seconds
Started Aug 15 05:57:55 PM PDT 24
Finished Aug 15 05:57:56 PM PDT 24
Peak memory 183148 kb
Host smart-daf8738c-1013-4e01-96e6-e6ebea8847ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514195474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.514195474
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1024437669
Short name T543
Test name
Test status
Simulation time 43090426 ps
CPU time 0.55 seconds
Started Aug 15 05:57:55 PM PDT 24
Finished Aug 15 05:57:56 PM PDT 24
Peak memory 183276 kb
Host smart-0cd04348-9ae8-4a16-818f-e078fb1cd0f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024437669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1024437669
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2435555954
Short name T513
Test name
Test status
Simulation time 17728748 ps
CPU time 0.59 seconds
Started Aug 15 05:57:58 PM PDT 24
Finished Aug 15 05:57:58 PM PDT 24
Peak memory 183304 kb
Host smart-1d11809e-f499-4ff2-99f4-df0e2989b511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435555954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2435555954
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3950880964
Short name T572
Test name
Test status
Simulation time 84124679 ps
CPU time 0.58 seconds
Started Aug 15 05:57:56 PM PDT 24
Finished Aug 15 05:57:57 PM PDT 24
Peak memory 183168 kb
Host smart-4f9a3361-5b60-43e4-b7cc-923238026e8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950880964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3950880964
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1065950947
Short name T471
Test name
Test status
Simulation time 21697196 ps
CPU time 0.52 seconds
Started Aug 15 05:57:56 PM PDT 24
Finished Aug 15 05:57:56 PM PDT 24
Peak memory 182704 kb
Host smart-691c0971-c69c-4f68-82b2-fe64444f4ba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065950947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1065950947
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3678946912
Short name T475
Test name
Test status
Simulation time 75684375 ps
CPU time 0.57 seconds
Started Aug 15 05:57:56 PM PDT 24
Finished Aug 15 05:57:57 PM PDT 24
Peak memory 183192 kb
Host smart-71715bcf-9857-4db4-b7ec-e3200db731c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678946912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3678946912
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.681106238
Short name T487
Test name
Test status
Simulation time 22920498 ps
CPU time 0.54 seconds
Started Aug 15 05:57:55 PM PDT 24
Finished Aug 15 05:57:56 PM PDT 24
Peak memory 183212 kb
Host smart-574ebdc7-ba9b-4915-9b5e-59235ef9011b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681106238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.681106238
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.510045406
Short name T546
Test name
Test status
Simulation time 128117227 ps
CPU time 0.87 seconds
Started Aug 15 05:57:31 PM PDT 24
Finished Aug 15 05:57:33 PM PDT 24
Peak memory 197792 kb
Host smart-cc59652a-1f0a-45db-9aac-330a40d57a91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510045406 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.510045406
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1290334566
Short name T474
Test name
Test status
Simulation time 15953419 ps
CPU time 0.57 seconds
Started Aug 15 05:57:29 PM PDT 24
Finished Aug 15 05:57:30 PM PDT 24
Peak memory 183380 kb
Host smart-b5399643-4384-4231-b159-5237b8c32f7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290334566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1290334566
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3269188069
Short name T538
Test name
Test status
Simulation time 15004520 ps
CPU time 0.56 seconds
Started Aug 15 05:57:28 PM PDT 24
Finished Aug 15 05:57:29 PM PDT 24
Peak memory 183220 kb
Host smart-cce7c269-6244-4325-be79-4280e8035e23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269188069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3269188069
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1787372253
Short name T579
Test name
Test status
Simulation time 20206011 ps
CPU time 0.78 seconds
Started Aug 15 05:57:37 PM PDT 24
Finished Aug 15 05:57:39 PM PDT 24
Peak memory 192316 kb
Host smart-f1ef1bea-87b2-4bbb-af9e-6003459c7a4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787372253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1787372253
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3271124548
Short name T512
Test name
Test status
Simulation time 814338169 ps
CPU time 1.94 seconds
Started Aug 15 05:57:30 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 197936 kb
Host smart-89fec763-9227-4b18-b88f-482d4fbc5067
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271124548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3271124548
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1340623024
Short name T511
Test name
Test status
Simulation time 47054111 ps
CPU time 0.85 seconds
Started Aug 15 05:57:33 PM PDT 24
Finished Aug 15 05:57:34 PM PDT 24
Peak memory 183472 kb
Host smart-e7c267ce-2c81-47f0-984a-1b010e010d62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340623024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1340623024
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3771682916
Short name T464
Test name
Test status
Simulation time 75784240 ps
CPU time 0.69 seconds
Started Aug 15 05:57:29 PM PDT 24
Finished Aug 15 05:57:29 PM PDT 24
Peak memory 194924 kb
Host smart-f31624ce-0290-4f92-9611-4094e4ca0932
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771682916 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3771682916
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3059865667
Short name T530
Test name
Test status
Simulation time 31726120 ps
CPU time 0.56 seconds
Started Aug 15 05:57:31 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 183328 kb
Host smart-6e0a335a-d0d1-4c4c-a581-7ef653d40dfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059865667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3059865667
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.949650120
Short name T557
Test name
Test status
Simulation time 22381169 ps
CPU time 0.54 seconds
Started Aug 15 05:57:30 PM PDT 24
Finished Aug 15 05:57:31 PM PDT 24
Peak memory 182884 kb
Host smart-78f45634-73e0-472d-943c-79b42f070cd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949650120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.949650120
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2748543326
Short name T90
Test name
Test status
Simulation time 249462616 ps
CPU time 0.65 seconds
Started Aug 15 05:57:29 PM PDT 24
Finished Aug 15 05:57:30 PM PDT 24
Peak memory 192868 kb
Host smart-35f92d4f-5499-47fd-8357-83247da7b45e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748543326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2748543326
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3855196393
Short name T483
Test name
Test status
Simulation time 95774448 ps
CPU time 1.4 seconds
Started Aug 15 05:57:30 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 197028 kb
Host smart-1390e07a-c2b3-43ad-ba2d-51a0856bbee8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855196393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3855196393
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2581102099
Short name T558
Test name
Test status
Simulation time 83373014 ps
CPU time 1.15 seconds
Started Aug 15 05:57:28 PM PDT 24
Finished Aug 15 05:57:29 PM PDT 24
Peak memory 195912 kb
Host smart-1ba7faf5-2ba2-409a-bb79-01d379eb5a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581102099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2581102099
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2325078696
Short name T460
Test name
Test status
Simulation time 53850156 ps
CPU time 0.65 seconds
Started Aug 15 05:57:32 PM PDT 24
Finished Aug 15 05:57:33 PM PDT 24
Peak memory 194244 kb
Host smart-17b8eb59-6c6e-4c5c-b4c1-2129bfbd852c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325078696 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2325078696
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3456994368
Short name T79
Test name
Test status
Simulation time 23078502 ps
CPU time 0.54 seconds
Started Aug 15 05:57:29 PM PDT 24
Finished Aug 15 05:57:30 PM PDT 24
Peak memory 183368 kb
Host smart-d1f3505d-94da-449a-9cea-9b621ae53420
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456994368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3456994368
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1881474365
Short name T497
Test name
Test status
Simulation time 58730464 ps
CPU time 0.56 seconds
Started Aug 15 05:57:29 PM PDT 24
Finished Aug 15 05:57:29 PM PDT 24
Peak memory 183204 kb
Host smart-fbc67675-e7e7-45ed-b35b-264087229913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881474365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1881474365
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.206417386
Short name T94
Test name
Test status
Simulation time 53440370 ps
CPU time 0.61 seconds
Started Aug 15 05:57:29 PM PDT 24
Finished Aug 15 05:57:30 PM PDT 24
Peak memory 192192 kb
Host smart-8d94f6b1-decb-42e0-b727-930a1e1543b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206417386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.206417386
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2316672780
Short name T466
Test name
Test status
Simulation time 223211238 ps
CPU time 1.16 seconds
Started Aug 15 05:57:32 PM PDT 24
Finished Aug 15 05:57:33 PM PDT 24
Peak memory 196308 kb
Host smart-42f4f109-dd0a-42a4-8080-462821d92699
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316672780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2316672780
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.17832245
Short name T490
Test name
Test status
Simulation time 251745390 ps
CPU time 1.04 seconds
Started Aug 15 05:57:30 PM PDT 24
Finished Aug 15 05:57:31 PM PDT 24
Peak memory 195640 kb
Host smart-40cd79b9-7359-48f8-a15e-d38fe2b2a92c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17832245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg
_err.17832245
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.735385037
Short name T504
Test name
Test status
Simulation time 84659264 ps
CPU time 1.22 seconds
Started Aug 15 05:57:31 PM PDT 24
Finished Aug 15 05:57:33 PM PDT 24
Peak memory 198160 kb
Host smart-982efb52-8347-453c-87ca-b1fed940f971
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735385037 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.735385037
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.4286290042
Short name T87
Test name
Test status
Simulation time 21541942 ps
CPU time 0.58 seconds
Started Aug 15 05:57:31 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 192572 kb
Host smart-3647c2cf-db95-4c99-ba66-1ed10e36fd89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286290042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.4286290042
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1752998535
Short name T476
Test name
Test status
Simulation time 15140810 ps
CPU time 0.58 seconds
Started Aug 15 05:57:31 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 183108 kb
Host smart-def5dbfd-3eae-4646-8387-f5e36c92e2d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752998535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1752998535
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3069911988
Short name T578
Test name
Test status
Simulation time 189197365 ps
CPU time 0.67 seconds
Started Aug 15 05:57:30 PM PDT 24
Finished Aug 15 05:57:31 PM PDT 24
Peak memory 192160 kb
Host smart-71d3b8ee-8b29-4583-82a8-1d17bbe9914f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069911988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3069911988
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2588938946
Short name T564
Test name
Test status
Simulation time 95413828 ps
CPU time 1.5 seconds
Started Aug 15 05:57:30 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 198060 kb
Host smart-55d1e224-5247-4830-bdc1-56cec7d328c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588938946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2588938946
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2157359858
Short name T541
Test name
Test status
Simulation time 98886196 ps
CPU time 1.35 seconds
Started Aug 15 05:57:30 PM PDT 24
Finished Aug 15 05:57:31 PM PDT 24
Peak memory 196012 kb
Host smart-b29a2fe1-dba6-46f3-81f8-0ec2938399f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157359858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2157359858
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1263025660
Short name T52
Test name
Test status
Simulation time 38342289 ps
CPU time 0.9 seconds
Started Aug 15 05:57:31 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 197736 kb
Host smart-d823310c-12f1-4ead-886b-bd8e0dee6153
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263025660 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1263025660
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1624514804
Short name T544
Test name
Test status
Simulation time 52688817 ps
CPU time 0.6 seconds
Started Aug 15 05:57:31 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 183364 kb
Host smart-2a855e44-124b-4a12-8c2c-99a326eabffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624514804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1624514804
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3847481905
Short name T457
Test name
Test status
Simulation time 15385085 ps
CPU time 0.59 seconds
Started Aug 15 05:57:31 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 182684 kb
Host smart-5e4cba1e-a3c4-4120-888f-5ad59fe6e709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847481905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3847481905
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3820283845
Short name T554
Test name
Test status
Simulation time 75756076 ps
CPU time 0.61 seconds
Started Aug 15 05:57:31 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 191852 kb
Host smart-cda35749-7a40-41b3-9227-b31ba856416c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820283845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3820283845
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2340646072
Short name T469
Test name
Test status
Simulation time 24892476 ps
CPU time 1.18 seconds
Started Aug 15 05:57:37 PM PDT 24
Finished Aug 15 05:57:39 PM PDT 24
Peak memory 195788 kb
Host smart-0c95a533-e44f-44e2-84c4-f5b06f13f81f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340646072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2340646072
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2488238546
Short name T99
Test name
Test status
Simulation time 424088045 ps
CPU time 1.12 seconds
Started Aug 15 05:57:30 PM PDT 24
Finished Aug 15 05:57:32 PM PDT 24
Peak memory 184084 kb
Host smart-79509a30-5f0b-4899-8218-8381dda5a284
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488238546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2488238546
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1865715201
Short name T231
Test name
Test status
Simulation time 223775641205 ps
CPU time 133.58 seconds
Started Aug 15 05:57:56 PM PDT 24
Finished Aug 15 06:00:10 PM PDT 24
Peak memory 183548 kb
Host smart-b4b9166a-1016-461e-aaa7-7974116b7240
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865715201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1865715201
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3341979194
Short name T371
Test name
Test status
Simulation time 80326848353 ps
CPU time 98.64 seconds
Started Aug 15 05:57:58 PM PDT 24
Finished Aug 15 05:59:37 PM PDT 24
Peak memory 183544 kb
Host smart-ce272af9-54c7-4d66-8da5-b06b3e9e5037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341979194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3341979194
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.72587148
Short name T157
Test name
Test status
Simulation time 179986250963 ps
CPU time 435.77 seconds
Started Aug 15 05:57:55 PM PDT 24
Finished Aug 15 06:05:11 PM PDT 24
Peak memory 191756 kb
Host smart-6c424849-077d-4576-a846-35ce6fea359f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72587148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.72587148
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3549479241
Short name T250
Test name
Test status
Simulation time 63589618515 ps
CPU time 111.43 seconds
Started Aug 15 05:57:57 PM PDT 24
Finished Aug 15 05:59:49 PM PDT 24
Peak memory 191784 kb
Host smart-005300dd-fd91-4610-8657-e1e22381639c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549479241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3549479241
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3682983641
Short name T412
Test name
Test status
Simulation time 290417990945 ps
CPU time 125.76 seconds
Started Aug 15 05:57:57 PM PDT 24
Finished Aug 15 06:00:03 PM PDT 24
Peak memory 183548 kb
Host smart-f589bf00-f931-400d-a4a6-90631715c3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682983641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3682983641
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3112127792
Short name T59
Test name
Test status
Simulation time 173237367889 ps
CPU time 166.88 seconds
Started Aug 15 05:57:56 PM PDT 24
Finished Aug 15 06:00:43 PM PDT 24
Peak memory 191796 kb
Host smart-3b00c5c4-bec8-4f76-9578-cdcd577a3a60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112127792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3112127792
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1441087077
Short name T45
Test name
Test status
Simulation time 263377955985 ps
CPU time 132.19 seconds
Started Aug 15 05:57:57 PM PDT 24
Finished Aug 15 06:00:10 PM PDT 24
Peak memory 183552 kb
Host smart-d72db3ef-e742-4bf7-b26e-7634a21ac663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441087077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1441087077
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3898137764
Short name T17
Test name
Test status
Simulation time 34506130 ps
CPU time 0.75 seconds
Started Aug 15 05:58:04 PM PDT 24
Finished Aug 15 05:58:05 PM PDT 24
Peak memory 213956 kb
Host smart-7682d9af-3dfe-463d-baba-5c64f9d39978
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898137764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3898137764
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2452282831
Short name T406
Test name
Test status
Simulation time 699210415156 ps
CPU time 302.39 seconds
Started Aug 15 05:58:04 PM PDT 24
Finished Aug 15 06:03:06 PM PDT 24
Peak memory 183584 kb
Host smart-d5b89d82-80f9-4787-b763-b756dc74d3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452282831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2452282831
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/102.rv_timer_random.1702680254
Short name T171
Test name
Test status
Simulation time 46728998138 ps
CPU time 76.74 seconds
Started Aug 15 05:59:16 PM PDT 24
Finished Aug 15 06:00:33 PM PDT 24
Peak memory 183604 kb
Host smart-60279ac5-f3d5-4288-ab1e-3812b8d85ee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702680254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1702680254
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.879082353
Short name T355
Test name
Test status
Simulation time 101553321221 ps
CPU time 293.62 seconds
Started Aug 15 05:59:22 PM PDT 24
Finished Aug 15 06:04:16 PM PDT 24
Peak memory 191800 kb
Host smart-d97e4645-bf81-46c7-a2c8-373cac1add7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879082353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.879082353
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1978849910
Short name T275
Test name
Test status
Simulation time 156588475967 ps
CPU time 167.69 seconds
Started Aug 15 05:59:22 PM PDT 24
Finished Aug 15 06:02:10 PM PDT 24
Peak memory 191800 kb
Host smart-934a9763-edbb-4673-8341-99000c02c876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978849910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1978849910
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.362876389
Short name T283
Test name
Test status
Simulation time 79356104310 ps
CPU time 83.21 seconds
Started Aug 15 05:59:25 PM PDT 24
Finished Aug 15 06:00:48 PM PDT 24
Peak memory 191820 kb
Host smart-fc360b83-9bdb-41bc-9dbc-a0873f91a6f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362876389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.362876389
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3204667404
Short name T299
Test name
Test status
Simulation time 142697200819 ps
CPU time 318.96 seconds
Started Aug 15 05:59:22 PM PDT 24
Finished Aug 15 06:04:41 PM PDT 24
Peak memory 191804 kb
Host smart-3708016b-1d43-4879-b6de-5ae06bdd2613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204667404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3204667404
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3123123837
Short name T378
Test name
Test status
Simulation time 172027533375 ps
CPU time 116.05 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 183476 kb
Host smart-1040e8be-360a-4859-9bc8-42ef15f234cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123123837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3123123837
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.92741011
Short name T115
Test name
Test status
Simulation time 267825822290 ps
CPU time 48.93 seconds
Started Aug 15 05:58:08 PM PDT 24
Finished Aug 15 05:58:57 PM PDT 24
Peak memory 191740 kb
Host smart-cbedb178-fbf7-4ee3-a36d-7e3c46ea0232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92741011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.92741011
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.870180939
Short name T39
Test name
Test status
Simulation time 275211495 ps
CPU time 5 seconds
Started Aug 15 05:58:11 PM PDT 24
Finished Aug 15 05:58:16 PM PDT 24
Peak memory 198152 kb
Host smart-1c918144-1a9d-408f-b0e9-23194f072c7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870180939 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.870180939
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.3854381983
Short name T289
Test name
Test status
Simulation time 171856848401 ps
CPU time 82.18 seconds
Started Aug 15 05:59:22 PM PDT 24
Finished Aug 15 06:00:44 PM PDT 24
Peak memory 183500 kb
Host smart-49814006-a364-453b-b419-e071369814ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854381983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3854381983
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1296227410
Short name T288
Test name
Test status
Simulation time 78493339745 ps
CPU time 97.51 seconds
Started Aug 15 05:59:20 PM PDT 24
Finished Aug 15 06:00:58 PM PDT 24
Peak memory 191764 kb
Host smart-cd69a5b3-fd59-4ba9-bac1-74c7063d85ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296227410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1296227410
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3883748643
Short name T315
Test name
Test status
Simulation time 659927103774 ps
CPU time 177.38 seconds
Started Aug 15 05:59:23 PM PDT 24
Finished Aug 15 06:02:21 PM PDT 24
Peak memory 195368 kb
Host smart-7484e33f-aca7-4392-90d5-7922afb76574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883748643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3883748643
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3426568161
Short name T175
Test name
Test status
Simulation time 5133130194 ps
CPU time 41.4 seconds
Started Aug 15 05:59:20 PM PDT 24
Finished Aug 15 06:00:01 PM PDT 24
Peak memory 191820 kb
Host smart-e87da457-c3f9-4ca7-b17c-6f88b9dda114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426568161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3426568161
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3654764734
Short name T197
Test name
Test status
Simulation time 136601792043 ps
CPU time 503.44 seconds
Started Aug 15 05:59:23 PM PDT 24
Finished Aug 15 06:07:46 PM PDT 24
Peak memory 191744 kb
Host smart-040afb69-f145-44e6-9174-19f87ba1f018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654764734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3654764734
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3208476033
Short name T162
Test name
Test status
Simulation time 197578024721 ps
CPU time 974.53 seconds
Started Aug 15 05:59:23 PM PDT 24
Finished Aug 15 06:15:37 PM PDT 24
Peak memory 191812 kb
Host smart-f1873350-a53e-4552-915e-b80ce49f741e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208476033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3208476033
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3758862403
Short name T251
Test name
Test status
Simulation time 88075559807 ps
CPU time 133.41 seconds
Started Aug 15 05:59:23 PM PDT 24
Finished Aug 15 06:01:37 PM PDT 24
Peak memory 191792 kb
Host smart-2446fb11-e622-46c9-9caa-d7a57c4a74ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758862403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3758862403
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.42860464
Short name T262
Test name
Test status
Simulation time 588607986042 ps
CPU time 3056.09 seconds
Started Aug 15 05:59:21 PM PDT 24
Finished Aug 15 06:50:18 PM PDT 24
Peak memory 191776 kb
Host smart-e29ac62e-2bd9-4933-ac16-cdab21bea393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42860464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.42860464
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.821436823
Short name T106
Test name
Test status
Simulation time 299052546644 ps
CPU time 1154.37 seconds
Started Aug 15 05:59:22 PM PDT 24
Finished Aug 15 06:18:37 PM PDT 24
Peak memory 194276 kb
Host smart-152a4eb2-fb09-41ca-81ab-fd6382d99814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821436823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.821436823
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1420456097
Short name T114
Test name
Test status
Simulation time 891871238365 ps
CPU time 506.68 seconds
Started Aug 15 05:58:09 PM PDT 24
Finished Aug 15 06:06:36 PM PDT 24
Peak memory 183528 kb
Host smart-d5b1839a-8834-4f2d-8452-334f0bae7969
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420456097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1420456097
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1757597220
Short name T370
Test name
Test status
Simulation time 539922237543 ps
CPU time 220.37 seconds
Started Aug 15 05:58:13 PM PDT 24
Finished Aug 15 06:01:54 PM PDT 24
Peak memory 183560 kb
Host smart-da36b4ce-9454-4f88-9b8f-6e85aa2ce8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757597220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1757597220
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.777104492
Short name T102
Test name
Test status
Simulation time 191419377194 ps
CPU time 838.45 seconds
Started Aug 15 05:58:11 PM PDT 24
Finished Aug 15 06:12:09 PM PDT 24
Peak memory 191716 kb
Host smart-0d50ac99-fdbb-4731-b657-a101059bc568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777104492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.777104492
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2698471332
Short name T150
Test name
Test status
Simulation time 149076966146 ps
CPU time 911.98 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 06:13:24 PM PDT 24
Peak memory 183372 kb
Host smart-16fe1ade-9140-4ded-9d39-2e87a84c5301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698471332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2698471332
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.3603314336
Short name T328
Test name
Test status
Simulation time 63894264445 ps
CPU time 102.75 seconds
Started Aug 15 05:59:21 PM PDT 24
Finished Aug 15 06:01:04 PM PDT 24
Peak memory 191696 kb
Host smart-54e6a56a-e542-4235-8cfb-63c5d39c9d10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603314336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3603314336
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2386723162
Short name T6
Test name
Test status
Simulation time 67199378261 ps
CPU time 194.79 seconds
Started Aug 15 05:59:23 PM PDT 24
Finished Aug 15 06:02:38 PM PDT 24
Peak memory 192880 kb
Host smart-dd13f1ee-ddb4-4776-822d-3670456c6bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386723162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2386723162
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.4029283258
Short name T242
Test name
Test status
Simulation time 411277561121 ps
CPU time 313.45 seconds
Started Aug 15 05:59:20 PM PDT 24
Finished Aug 15 06:04:34 PM PDT 24
Peak memory 191844 kb
Host smart-73fe6496-0235-45f9-ae03-9693126dcc5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029283258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.4029283258
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2572301122
Short name T74
Test name
Test status
Simulation time 64715860250 ps
CPU time 110.02 seconds
Started Aug 15 05:59:21 PM PDT 24
Finished Aug 15 06:01:11 PM PDT 24
Peak memory 191792 kb
Host smart-c3efcc37-634c-41a7-bcf6-5fc8ec59c754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572301122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2572301122
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1400730298
Short name T311
Test name
Test status
Simulation time 142988101344 ps
CPU time 1438.7 seconds
Started Aug 15 05:59:21 PM PDT 24
Finished Aug 15 06:23:20 PM PDT 24
Peak memory 191752 kb
Host smart-88b3aa65-588f-4ae1-935c-03f6658f4915
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400730298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1400730298
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2643168902
Short name T291
Test name
Test status
Simulation time 108036402562 ps
CPU time 341.46 seconds
Started Aug 15 05:59:29 PM PDT 24
Finished Aug 15 06:05:11 PM PDT 24
Peak memory 191784 kb
Host smart-105f38e1-ea25-48b6-9bf1-eb9880699d81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643168902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2643168902
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1099444518
Short name T224
Test name
Test status
Simulation time 156499584217 ps
CPU time 267.21 seconds
Started Aug 15 05:58:11 PM PDT 24
Finished Aug 15 06:02:38 PM PDT 24
Peak memory 183540 kb
Host smart-7062e8de-8351-4267-b487-1c3596213156
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099444518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1099444518
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.644418597
Short name T424
Test name
Test status
Simulation time 72176366902 ps
CPU time 108.01 seconds
Started Aug 15 05:58:11 PM PDT 24
Finished Aug 15 05:59:59 PM PDT 24
Peak memory 183600 kb
Host smart-4992655a-6072-402d-a29b-f3e944b9607c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644418597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.644418597
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.92163311
Short name T327
Test name
Test status
Simulation time 260283089057 ps
CPU time 114.73 seconds
Started Aug 15 05:58:13 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 183600 kb
Host smart-d3ef43b2-39de-415f-9772-2214d4b326d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92163311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.92163311
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3006517939
Short name T190
Test name
Test status
Simulation time 25730546525 ps
CPU time 95.53 seconds
Started Aug 15 05:58:09 PM PDT 24
Finished Aug 15 05:59:45 PM PDT 24
Peak memory 191760 kb
Host smart-880f32c0-afd7-4623-87ca-3e8814ef43d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006517939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3006517939
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1808553012
Short name T284
Test name
Test status
Simulation time 872025167575 ps
CPU time 347.34 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 06:04:00 PM PDT 24
Peak memory 191656 kb
Host smart-3b6ad9c8-eed0-426c-a94b-0e4f81448af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808553012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1808553012
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/135.rv_timer_random.3032943116
Short name T248
Test name
Test status
Simulation time 38698609192 ps
CPU time 78.48 seconds
Started Aug 15 05:59:31 PM PDT 24
Finished Aug 15 06:00:50 PM PDT 24
Peak memory 183572 kb
Host smart-30d952cb-d628-4685-936e-357b7d2540b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032943116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3032943116
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2504131312
Short name T442
Test name
Test status
Simulation time 48673202260 ps
CPU time 88.37 seconds
Started Aug 15 05:59:29 PM PDT 24
Finished Aug 15 06:00:57 PM PDT 24
Peak memory 191756 kb
Host smart-b7f60a44-118f-42aa-929d-1e0bdd723a9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504131312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2504131312
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1540440678
Short name T303
Test name
Test status
Simulation time 454470779259 ps
CPU time 685.47 seconds
Started Aug 15 05:58:08 PM PDT 24
Finished Aug 15 06:09:34 PM PDT 24
Peak memory 183516 kb
Host smart-71c8f30c-e0fc-4ebd-9948-341e4a0115ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540440678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1540440678
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.842063036
Short name T359
Test name
Test status
Simulation time 362318774476 ps
CPU time 198.91 seconds
Started Aug 15 05:58:11 PM PDT 24
Finished Aug 15 06:01:30 PM PDT 24
Peak memory 183560 kb
Host smart-1fe7a781-9d17-4b9e-b62a-de67e2160ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842063036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.842063036
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.715250042
Short name T429
Test name
Test status
Simulation time 7622577560 ps
CPU time 12.62 seconds
Started Aug 15 05:58:11 PM PDT 24
Finished Aug 15 05:58:24 PM PDT 24
Peak memory 183484 kb
Host smart-2daaed52-8ff5-42f7-a431-7ab16a6b39f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715250042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.715250042
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/142.rv_timer_random.3756882870
Short name T109
Test name
Test status
Simulation time 453733845523 ps
CPU time 1846.41 seconds
Started Aug 15 05:59:29 PM PDT 24
Finished Aug 15 06:30:16 PM PDT 24
Peak memory 191804 kb
Host smart-9ece1c3a-595e-4cbd-8120-f771ef3e87ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756882870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3756882870
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.83588390
Short name T48
Test name
Test status
Simulation time 643154942903 ps
CPU time 1845.24 seconds
Started Aug 15 05:59:30 PM PDT 24
Finished Aug 15 06:30:15 PM PDT 24
Peak memory 191792 kb
Host smart-ef61a1d7-0661-45d0-9314-848cc0a85de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83588390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.83588390
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3429055659
Short name T3
Test name
Test status
Simulation time 305400165504 ps
CPU time 136.6 seconds
Started Aug 15 05:59:30 PM PDT 24
Finished Aug 15 06:01:47 PM PDT 24
Peak memory 194104 kb
Host smart-77735349-1d29-4105-ac8d-de83046336c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429055659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3429055659
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2069047580
Short name T354
Test name
Test status
Simulation time 187407459663 ps
CPU time 154.76 seconds
Started Aug 15 05:59:29 PM PDT 24
Finished Aug 15 06:02:04 PM PDT 24
Peak memory 191572 kb
Host smart-5bc3796f-5b32-40f2-9538-51d4d24186ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069047580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2069047580
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2075398834
Short name T249
Test name
Test status
Simulation time 121254805575 ps
CPU time 811.32 seconds
Started Aug 15 05:59:30 PM PDT 24
Finished Aug 15 06:13:02 PM PDT 24
Peak memory 191788 kb
Host smart-8c24c4a9-db1f-4f7e-bcc1-232ce6df7b57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075398834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2075398834
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.4008725186
Short name T434
Test name
Test status
Simulation time 482716845567 ps
CPU time 230.86 seconds
Started Aug 15 05:59:31 PM PDT 24
Finished Aug 15 06:03:22 PM PDT 24
Peak memory 191800 kb
Host smart-676e9cd1-024d-47eb-890d-39c76ccfed21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008725186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.4008725186
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.524932860
Short name T140
Test name
Test status
Simulation time 1123089327384 ps
CPU time 2690.48 seconds
Started Aug 15 05:59:30 PM PDT 24
Finished Aug 15 06:44:21 PM PDT 24
Peak memory 191800 kb
Host smart-5018fb5f-8894-4223-bff1-a45f1595ddb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524932860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.524932860
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2812011410
Short name T309
Test name
Test status
Simulation time 243517928362 ps
CPU time 375.64 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 06:04:28 PM PDT 24
Peak memory 183536 kb
Host smart-0eceeaa4-142d-4eb0-855c-5645cc881a26
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812011410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2812011410
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2454514488
Short name T382
Test name
Test status
Simulation time 55729644977 ps
CPU time 18.41 seconds
Started Aug 15 05:58:08 PM PDT 24
Finished Aug 15 05:58:27 PM PDT 24
Peak memory 183584 kb
Host smart-4b63fcfc-675a-49fe-a031-f7cc48569762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454514488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2454514488
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.4259682682
Short name T441
Test name
Test status
Simulation time 136860993949 ps
CPU time 1325.05 seconds
Started Aug 15 05:58:10 PM PDT 24
Finished Aug 15 06:20:15 PM PDT 24
Peak memory 191700 kb
Host smart-60225cbe-d6f0-4a05-b682-ec9507d4b70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259682682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.4259682682
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.3199865171
Short name T448
Test name
Test status
Simulation time 1745939241 ps
CPU time 4.62 seconds
Started Aug 15 05:58:11 PM PDT 24
Finished Aug 15 05:58:15 PM PDT 24
Peak memory 197940 kb
Host smart-aa24548a-da3b-43eb-8605-fe3123bc8855
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199865171 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.3199865171
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.299306388
Short name T107
Test name
Test status
Simulation time 97465143232 ps
CPU time 436.09 seconds
Started Aug 15 05:59:30 PM PDT 24
Finished Aug 15 06:06:46 PM PDT 24
Peak memory 191804 kb
Host smart-ee3a2913-df27-4dfe-9979-fe03b2f7f968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299306388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.299306388
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.303638317
Short name T320
Test name
Test status
Simulation time 49598395178 ps
CPU time 89.01 seconds
Started Aug 15 05:59:39 PM PDT 24
Finished Aug 15 06:01:08 PM PDT 24
Peak memory 183604 kb
Host smart-3fda3860-f3a9-4409-ad0f-9ddd8a09d501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303638317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.303638317
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3309066087
Short name T28
Test name
Test status
Simulation time 181112093211 ps
CPU time 315.01 seconds
Started Aug 15 05:59:36 PM PDT 24
Finished Aug 15 06:04:51 PM PDT 24
Peak memory 191784 kb
Host smart-d31c4bc5-a28c-4ea9-8222-2e572d900a51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309066087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3309066087
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1440712951
Short name T24
Test name
Test status
Simulation time 102812458545 ps
CPU time 1793.41 seconds
Started Aug 15 05:59:38 PM PDT 24
Finished Aug 15 06:29:31 PM PDT 24
Peak memory 193544 kb
Host smart-7e78fb13-2ec6-4486-8382-0752d9382a2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440712951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1440712951
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1833341784
Short name T226
Test name
Test status
Simulation time 220284515859 ps
CPU time 963.04 seconds
Started Aug 15 05:59:35 PM PDT 24
Finished Aug 15 06:15:39 PM PDT 24
Peak memory 191772 kb
Host smart-c0cb2f2f-2965-4d14-a5da-9d8498133339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833341784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1833341784
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3341298738
Short name T372
Test name
Test status
Simulation time 77643330640 ps
CPU time 289.98 seconds
Started Aug 15 05:59:38 PM PDT 24
Finished Aug 15 06:04:28 PM PDT 24
Peak memory 183588 kb
Host smart-7c8642a9-5e90-437b-a6b2-9836a45860fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341298738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3341298738
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1290122968
Short name T322
Test name
Test status
Simulation time 403967266217 ps
CPU time 99.06 seconds
Started Aug 15 05:59:36 PM PDT 24
Finished Aug 15 06:01:15 PM PDT 24
Peak memory 183600 kb
Host smart-34e76738-b9ee-46d0-ba3b-f1a099a304e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290122968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1290122968
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1381920522
Short name T410
Test name
Test status
Simulation time 389909469043 ps
CPU time 698.06 seconds
Started Aug 15 05:58:11 PM PDT 24
Finished Aug 15 06:09:50 PM PDT 24
Peak memory 183528 kb
Host smart-f8fde9ae-4d36-447c-aecf-3a6a33da4fc9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381920522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1381920522
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2514174075
Short name T374
Test name
Test status
Simulation time 146214987306 ps
CPU time 60.28 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 05:59:12 PM PDT 24
Peak memory 183520 kb
Host smart-3d6c692d-f82e-4e21-aaf6-c4e515925bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514174075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2514174075
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3345349755
Short name T411
Test name
Test status
Simulation time 16569378486 ps
CPU time 27.1 seconds
Started Aug 15 05:58:11 PM PDT 24
Finished Aug 15 05:58:38 PM PDT 24
Peak memory 183516 kb
Host smart-542bd911-0786-4801-b5b4-bea1c8d240cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345349755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3345349755
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.761568361
Short name T325
Test name
Test status
Simulation time 186680846614 ps
CPU time 144.93 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 06:00:37 PM PDT 24
Peak memory 183560 kb
Host smart-0e684605-9859-4486-8ea5-17a86210affd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761568361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.761568361
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1133213051
Short name T367
Test name
Test status
Simulation time 521565684053 ps
CPU time 714.98 seconds
Started Aug 15 05:58:14 PM PDT 24
Finished Aug 15 06:10:09 PM PDT 24
Peak memory 191772 kb
Host smart-f5f7ae8f-8441-4dfd-9dbf-ab610e0f6d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133213051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1133213051
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/161.rv_timer_random.637902651
Short name T139
Test name
Test status
Simulation time 246243101710 ps
CPU time 181.92 seconds
Started Aug 15 05:59:35 PM PDT 24
Finished Aug 15 06:02:37 PM PDT 24
Peak memory 191736 kb
Host smart-cc65bc2e-f7c7-4062-a549-b99c3d881611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637902651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.637902651
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3715664440
Short name T259
Test name
Test status
Simulation time 261008407697 ps
CPU time 563.68 seconds
Started Aug 15 05:59:36 PM PDT 24
Finished Aug 15 06:09:00 PM PDT 24
Peak memory 191768 kb
Host smart-4e701fec-9d47-4089-a803-7f0275d0c246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715664440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3715664440
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3218298728
Short name T64
Test name
Test status
Simulation time 74352671531 ps
CPU time 596.95 seconds
Started Aug 15 05:59:35 PM PDT 24
Finished Aug 15 06:09:32 PM PDT 24
Peak memory 191684 kb
Host smart-8def9ca5-9d0b-4cba-bc17-fefebf1ed4f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218298728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3218298728
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.222493953
Short name T343
Test name
Test status
Simulation time 150575149468 ps
CPU time 308.19 seconds
Started Aug 15 05:59:43 PM PDT 24
Finished Aug 15 06:04:52 PM PDT 24
Peak memory 191800 kb
Host smart-61712a94-cdeb-492f-be46-1042aec61c61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222493953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.222493953
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3916332041
Short name T337
Test name
Test status
Simulation time 6098178832 ps
CPU time 10.77 seconds
Started Aug 15 05:59:43 PM PDT 24
Finished Aug 15 05:59:54 PM PDT 24
Peak memory 183556 kb
Host smart-dcfc8f58-7c98-4516-a2eb-4e5b72736e04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916332041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3916332041
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.910563351
Short name T219
Test name
Test status
Simulation time 363298782205 ps
CPU time 576.96 seconds
Started Aug 15 05:59:44 PM PDT 24
Finished Aug 15 06:09:21 PM PDT 24
Peak memory 191756 kb
Host smart-2dde348b-ef46-401a-8f4b-d3773477dc69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910563351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.910563351
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.57433682
Short name T112
Test name
Test status
Simulation time 61477830769 ps
CPU time 35.66 seconds
Started Aug 15 05:58:09 PM PDT 24
Finished Aug 15 05:58:45 PM PDT 24
Peak memory 183572 kb
Host smart-cf73dd51-a502-4f72-9aaf-94c55ceffaa6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57433682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.rv_timer_cfg_update_on_fly.57433682
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1369673980
Short name T427
Test name
Test status
Simulation time 155642241663 ps
CPU time 66.15 seconds
Started Aug 15 05:58:10 PM PDT 24
Finished Aug 15 05:59:16 PM PDT 24
Peak memory 183588 kb
Host smart-e7be44aa-425d-4f49-875e-d7d9420e4b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369673980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1369673980
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.620842351
Short name T151
Test name
Test status
Simulation time 33058767272 ps
CPU time 55.38 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 05:59:08 PM PDT 24
Peak memory 183484 kb
Host smart-27d36762-70f7-42fa-ad78-9d4738c57063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620842351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.620842351
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1392905987
Short name T404
Test name
Test status
Simulation time 211421395 ps
CPU time 0.98 seconds
Started Aug 15 05:58:10 PM PDT 24
Finished Aug 15 05:58:12 PM PDT 24
Peak memory 183252 kb
Host smart-3228e2ca-212b-4c47-9db0-8284caa8321a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392905987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1392905987
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1442418053
Short name T408
Test name
Test status
Simulation time 119816138420 ps
CPU time 38.16 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 05:58:50 PM PDT 24
Peak memory 183560 kb
Host smart-6a10e388-0fab-486c-af0c-ea2a0ae49555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442418053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1442418053
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.419773792
Short name T43
Test name
Test status
Simulation time 5826223884 ps
CPU time 26.08 seconds
Started Aug 15 05:58:09 PM PDT 24
Finished Aug 15 05:58:36 PM PDT 24
Peak memory 198276 kb
Host smart-e105423b-e282-4996-a40b-f8f296c24be7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419773792 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.419773792
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.229191441
Short name T285
Test name
Test status
Simulation time 326453733042 ps
CPU time 1862.66 seconds
Started Aug 15 05:59:44 PM PDT 24
Finished Aug 15 06:30:47 PM PDT 24
Peak memory 191776 kb
Host smart-49612f2f-d5c7-4c1a-8773-abb0f0bf058e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229191441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.229191441
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3561405159
Short name T141
Test name
Test status
Simulation time 107375078297 ps
CPU time 1060.34 seconds
Started Aug 15 05:59:42 PM PDT 24
Finished Aug 15 06:17:23 PM PDT 24
Peak memory 191796 kb
Host smart-91ca653e-2c75-4fc5-b331-bb439ad688a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561405159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3561405159
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1640176464
Short name T300
Test name
Test status
Simulation time 376030400819 ps
CPU time 203.52 seconds
Started Aug 15 05:59:43 PM PDT 24
Finished Aug 15 06:03:07 PM PDT 24
Peak memory 191804 kb
Host smart-3d21fd05-7b3c-4205-9393-d2111851153e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640176464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1640176464
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2425244436
Short name T47
Test name
Test status
Simulation time 84069935845 ps
CPU time 67.33 seconds
Started Aug 15 05:59:42 PM PDT 24
Finished Aug 15 06:00:50 PM PDT 24
Peak memory 183380 kb
Host smart-7b8193e2-c945-48da-a298-bb9741b2f8a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425244436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2425244436
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1429131561
Short name T215
Test name
Test status
Simulation time 350533056966 ps
CPU time 377.58 seconds
Started Aug 15 05:59:42 PM PDT 24
Finished Aug 15 06:06:00 PM PDT 24
Peak memory 191768 kb
Host smart-0ebf9a96-7937-43b1-a203-b1959e3552b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429131561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1429131561
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1914414018
Short name T73
Test name
Test status
Simulation time 133317983764 ps
CPU time 197.54 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 06:01:30 PM PDT 24
Peak memory 183520 kb
Host smart-2c24ead5-1f9b-480f-8f24-9bfadec9b175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914414018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1914414018
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3748304561
Short name T76
Test name
Test status
Simulation time 175970805377 ps
CPU time 479.72 seconds
Started Aug 15 05:58:08 PM PDT 24
Finished Aug 15 06:06:08 PM PDT 24
Peak memory 191820 kb
Host smart-ff0cb712-b9d0-4deb-b4aa-ec4dbdefe313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748304561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3748304561
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3242444288
Short name T380
Test name
Test status
Simulation time 10051680006 ps
CPU time 9.8 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 05:58:21 PM PDT 24
Peak memory 191772 kb
Host smart-03622188-385f-4a7d-98d6-2fbcd4b0908c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242444288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3242444288
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.17374043
Short name T124
Test name
Test status
Simulation time 866088041273 ps
CPU time 1460.92 seconds
Started Aug 15 05:59:43 PM PDT 24
Finished Aug 15 06:24:04 PM PDT 24
Peak memory 191736 kb
Host smart-e09595ea-cc5d-48b0-af61-26d6f1fcd14d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17374043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.17374043
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2996348247
Short name T172
Test name
Test status
Simulation time 72539653111 ps
CPU time 336.38 seconds
Started Aug 15 05:59:50 PM PDT 24
Finished Aug 15 06:05:27 PM PDT 24
Peak memory 191684 kb
Host smart-c37fce55-2a06-45ee-b6a8-d1ba3bba0c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996348247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2996348247
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.886561190
Short name T338
Test name
Test status
Simulation time 548624212235 ps
CPU time 92.59 seconds
Started Aug 15 05:59:49 PM PDT 24
Finished Aug 15 06:01:22 PM PDT 24
Peak memory 191816 kb
Host smart-e5b9bbee-4071-404b-89c2-c2d2c3a5c2c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886561190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.886561190
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3186421552
Short name T201
Test name
Test status
Simulation time 370641865188 ps
CPU time 1042.57 seconds
Started Aug 15 05:59:49 PM PDT 24
Finished Aug 15 06:17:12 PM PDT 24
Peak memory 191736 kb
Host smart-38570a3d-a1e4-4c98-956f-201fad8248df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186421552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3186421552
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.130998904
Short name T180
Test name
Test status
Simulation time 129122471115 ps
CPU time 656.31 seconds
Started Aug 15 05:59:51 PM PDT 24
Finished Aug 15 06:10:47 PM PDT 24
Peak memory 194272 kb
Host smart-2fe4c8cf-a6ca-4d33-bbe0-6b72168ae262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130998904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.130998904
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.230802855
Short name T347
Test name
Test status
Simulation time 193493812979 ps
CPU time 164.56 seconds
Started Aug 15 05:59:50 PM PDT 24
Finished Aug 15 06:02:35 PM PDT 24
Peak memory 191656 kb
Host smart-01170f46-4c48-4204-bdec-f59e33207214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230802855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.230802855
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.487063552
Short name T301
Test name
Test status
Simulation time 14957445941 ps
CPU time 25.45 seconds
Started Aug 15 05:59:49 PM PDT 24
Finished Aug 15 06:00:15 PM PDT 24
Peak memory 183576 kb
Host smart-a4c78730-fe9b-40b8-b33f-b6395777d3e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487063552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.487063552
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3855005516
Short name T57
Test name
Test status
Simulation time 45718904212 ps
CPU time 16.89 seconds
Started Aug 15 05:59:51 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 183580 kb
Host smart-4da1d749-3dfd-4db1-8102-681ee48bd413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855005516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3855005516
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1987230218
Short name T212
Test name
Test status
Simulation time 2056691120474 ps
CPU time 749.19 seconds
Started Aug 15 05:58:23 PM PDT 24
Finished Aug 15 06:10:53 PM PDT 24
Peak memory 183536 kb
Host smart-94591306-ba6f-42d3-ba25-ce98d028fb77
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987230218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1987230218
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1479848985
Short name T362
Test name
Test status
Simulation time 85680634951 ps
CPU time 71.43 seconds
Started Aug 15 05:58:18 PM PDT 24
Finished Aug 15 05:59:29 PM PDT 24
Peak memory 183476 kb
Host smart-7155761b-48ce-4fc7-9408-bbdb0cdea9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479848985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1479848985
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.3367227668
Short name T393
Test name
Test status
Simulation time 10360363253 ps
CPU time 13.1 seconds
Started Aug 15 05:58:17 PM PDT 24
Finished Aug 15 05:58:30 PM PDT 24
Peak memory 183532 kb
Host smart-649f7b67-96bd-44c3-ac33-14416f4e0cf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367227668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3367227668
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.705063217
Short name T423
Test name
Test status
Simulation time 103633122104 ps
CPU time 275.19 seconds
Started Aug 15 05:58:19 PM PDT 24
Finished Aug 15 06:02:54 PM PDT 24
Peak memory 194756 kb
Host smart-54d6ef2d-25c0-4646-a2f5-ff29860c130b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705063217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.705063217
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3147010501
Short name T70
Test name
Test status
Simulation time 80170364 ps
CPU time 0.63 seconds
Started Aug 15 05:58:19 PM PDT 24
Finished Aug 15 05:58:20 PM PDT 24
Peak memory 183252 kb
Host smart-e888edf8-3c8c-41e5-a532-21e4e6803c43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147010501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3147010501
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.1328951102
Short name T154
Test name
Test status
Simulation time 51674476435 ps
CPU time 81.13 seconds
Started Aug 15 05:59:52 PM PDT 24
Finished Aug 15 06:01:13 PM PDT 24
Peak memory 193832 kb
Host smart-09159496-a8e8-4901-87af-285c4b9ed06d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328951102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1328951102
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3181874615
Short name T257
Test name
Test status
Simulation time 9724602964 ps
CPU time 11.84 seconds
Started Aug 15 05:59:57 PM PDT 24
Finished Aug 15 06:00:09 PM PDT 24
Peak memory 191784 kb
Host smart-360a6a38-19f5-4cf1-8ce0-ba6a924c3ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181874615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3181874615
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.838837484
Short name T132
Test name
Test status
Simulation time 379637380090 ps
CPU time 517.88 seconds
Started Aug 15 05:59:57 PM PDT 24
Finished Aug 15 06:08:35 PM PDT 24
Peak memory 191788 kb
Host smart-6985487d-f426-45ce-a990-7d9c3751de8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838837484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.838837484
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3579251662
Short name T46
Test name
Test status
Simulation time 416360259774 ps
CPU time 94.11 seconds
Started Aug 15 05:59:57 PM PDT 24
Finished Aug 15 06:01:31 PM PDT 24
Peak memory 191744 kb
Host smart-6d70aa6a-f080-44c1-a4ca-5bdfb126a78b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579251662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3579251662
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.813422872
Short name T168
Test name
Test status
Simulation time 289180473161 ps
CPU time 278.84 seconds
Started Aug 15 05:59:59 PM PDT 24
Finished Aug 15 06:04:38 PM PDT 24
Peak memory 191788 kb
Host smart-a45eae88-16ce-4fad-9eb4-1c81273979e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813422872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.813422872
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.773852940
Short name T29
Test name
Test status
Simulation time 127608795495 ps
CPU time 139.8 seconds
Started Aug 15 05:59:57 PM PDT 24
Finished Aug 15 06:02:17 PM PDT 24
Peak memory 191740 kb
Host smart-9f2f0759-839c-4a96-a742-c6b17b9afc53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773852940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.773852940
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1272605820
Short name T314
Test name
Test status
Simulation time 113446939249 ps
CPU time 189.8 seconds
Started Aug 15 05:59:58 PM PDT 24
Finished Aug 15 06:03:08 PM PDT 24
Peak memory 191800 kb
Host smart-0722319a-5348-401b-8082-a44b71ff403e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272605820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1272605820
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1757510025
Short name T195
Test name
Test status
Simulation time 1914242137557 ps
CPU time 970.96 seconds
Started Aug 15 05:58:03 PM PDT 24
Finished Aug 15 06:14:14 PM PDT 24
Peak memory 183736 kb
Host smart-27f302da-0e00-46a4-9a45-4c6326d040ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757510025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1757510025
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.4266545918
Short name T417
Test name
Test status
Simulation time 353847624882 ps
CPU time 253.77 seconds
Started Aug 15 05:58:01 PM PDT 24
Finished Aug 15 06:02:15 PM PDT 24
Peak memory 183576 kb
Host smart-5367a919-2f8e-4b83-8b64-dbde0c7a2dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266545918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.4266545918
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3027947453
Short name T75
Test name
Test status
Simulation time 380674013858 ps
CPU time 56.89 seconds
Started Aug 15 05:58:11 PM PDT 24
Finished Aug 15 05:59:08 PM PDT 24
Peak memory 183604 kb
Host smart-4a3bf63a-669b-4715-a2b4-bd4b550ff6cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027947453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3027947453
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3533662646
Short name T144
Test name
Test status
Simulation time 133123226558 ps
CPU time 81.29 seconds
Started Aug 15 05:58:02 PM PDT 24
Finished Aug 15 05:59:23 PM PDT 24
Peak memory 183504 kb
Host smart-21335a1b-90c2-4671-9f58-2cf4e33b26fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533662646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3533662646
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3540564134
Short name T18
Test name
Test status
Simulation time 64468192 ps
CPU time 0.91 seconds
Started Aug 15 05:58:02 PM PDT 24
Finished Aug 15 05:58:03 PM PDT 24
Peak memory 213964 kb
Host smart-7fdaaa59-c934-4a64-afdd-e6ae8e22aeef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540564134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3540564134
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.4160444973
Short name T440
Test name
Test status
Simulation time 67555675 ps
CPU time 0.59 seconds
Started Aug 15 05:58:04 PM PDT 24
Finished Aug 15 05:58:04 PM PDT 24
Peak memory 182956 kb
Host smart-20cacb0b-7bf7-40a1-b7a3-84ba8d008da2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160444973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
4160444973
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.918770130
Short name T204
Test name
Test status
Simulation time 389002774730 ps
CPU time 365.18 seconds
Started Aug 15 05:58:19 PM PDT 24
Finished Aug 15 06:04:24 PM PDT 24
Peak memory 183524 kb
Host smart-2bd8b9f9-d2b5-48f4-9602-4d19e3326776
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918770130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.918770130
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.481129382
Short name T439
Test name
Test status
Simulation time 119250494313 ps
CPU time 159.51 seconds
Started Aug 15 05:58:18 PM PDT 24
Finished Aug 15 06:00:57 PM PDT 24
Peak memory 183580 kb
Host smart-dfa0fe32-2e10-4db3-966c-46f9cc80945e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481129382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.481129382
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1382398382
Short name T173
Test name
Test status
Simulation time 102992503054 ps
CPU time 1241.75 seconds
Started Aug 15 05:58:19 PM PDT 24
Finished Aug 15 06:19:01 PM PDT 24
Peak memory 191764 kb
Host smart-d7fbb32a-6fa0-4ff8-afa0-9a8913ea4b6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382398382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1382398382
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.309237884
Short name T274
Test name
Test status
Simulation time 97953766344 ps
CPU time 123.94 seconds
Started Aug 15 05:58:20 PM PDT 24
Finished Aug 15 06:00:24 PM PDT 24
Peak memory 183556 kb
Host smart-e6f7c2e6-bf9b-496b-b72f-94fc2329365c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309237884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.309237884
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.646349449
Short name T130
Test name
Test status
Simulation time 685052068196 ps
CPU time 662.44 seconds
Started Aug 15 05:58:19 PM PDT 24
Finished Aug 15 06:09:22 PM PDT 24
Peak memory 196280 kb
Host smart-a54fb445-30aa-4e06-b82d-5e18377e680e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646349449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
646349449
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.85856087
Short name T345
Test name
Test status
Simulation time 714694160353 ps
CPU time 366 seconds
Started Aug 15 05:58:21 PM PDT 24
Finished Aug 15 06:04:28 PM PDT 24
Peak memory 183604 kb
Host smart-3e25b37d-2eb3-497b-8784-cd144ca47117
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85856087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.rv_timer_cfg_update_on_fly.85856087
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2040368865
Short name T375
Test name
Test status
Simulation time 20160485578 ps
CPU time 27.63 seconds
Started Aug 15 05:58:17 PM PDT 24
Finished Aug 15 05:58:45 PM PDT 24
Peak memory 183600 kb
Host smart-c770febf-6253-49a3-b14a-276664a35522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040368865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2040368865
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2099085474
Short name T9
Test name
Test status
Simulation time 550943180912 ps
CPU time 669.61 seconds
Started Aug 15 05:58:17 PM PDT 24
Finished Aug 15 06:09:27 PM PDT 24
Peak memory 191796 kb
Host smart-5e25b4eb-9859-435b-9b5f-f750e7fc5529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099085474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2099085474
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2835293034
Short name T229
Test name
Test status
Simulation time 115539882801 ps
CPU time 205.44 seconds
Started Aug 15 05:58:23 PM PDT 24
Finished Aug 15 06:01:48 PM PDT 24
Peak memory 191740 kb
Host smart-fb61cfda-143d-4fbf-b80a-f4a78cc00539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835293034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2835293034
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1499028163
Short name T304
Test name
Test status
Simulation time 9926815776 ps
CPU time 15.8 seconds
Started Aug 15 05:58:19 PM PDT 24
Finished Aug 15 05:58:35 PM PDT 24
Peak memory 183548 kb
Host smart-af9101d2-95b9-46ce-b4b5-ed79b40d6986
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499028163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1499028163
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3838401881
Short name T397
Test name
Test status
Simulation time 85232006540 ps
CPU time 129.21 seconds
Started Aug 15 05:58:17 PM PDT 24
Finished Aug 15 06:00:26 PM PDT 24
Peak memory 183580 kb
Host smart-cd215e17-0d9c-43fb-9ba7-8fd038c3a206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838401881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3838401881
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.423378037
Short name T203
Test name
Test status
Simulation time 183839367970 ps
CPU time 54.67 seconds
Started Aug 15 05:58:22 PM PDT 24
Finished Aug 15 05:59:17 PM PDT 24
Peak memory 194288 kb
Host smart-8f1fb043-6682-49bc-bc87-6acfcfa46c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423378037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.423378037
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.974635798
Short name T186
Test name
Test status
Simulation time 82994069966 ps
CPU time 311.54 seconds
Started Aug 15 05:58:21 PM PDT 24
Finished Aug 15 06:03:33 PM PDT 24
Peak memory 195160 kb
Host smart-8f332003-06be-49ec-945d-dca4f762e7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974635798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.974635798
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3208104510
Short name T419
Test name
Test status
Simulation time 493624720769 ps
CPU time 198.83 seconds
Started Aug 15 05:58:22 PM PDT 24
Finished Aug 15 06:01:41 PM PDT 24
Peak memory 195380 kb
Host smart-d763b27b-ede2-468d-985c-f8273e7f9421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208104510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3208104510
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.2397034158
Short name T42
Test name
Test status
Simulation time 2270621499 ps
CPU time 27.69 seconds
Started Aug 15 05:58:19 PM PDT 24
Finished Aug 15 05:58:47 PM PDT 24
Peak memory 198276 kb
Host smart-66460112-eac2-43ef-8166-dbb0cc016410
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397034158 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.2397034158
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2460947046
Short name T363
Test name
Test status
Simulation time 211901570673 ps
CPU time 330.04 seconds
Started Aug 15 05:58:22 PM PDT 24
Finished Aug 15 06:03:53 PM PDT 24
Peak memory 183588 kb
Host smart-ec0103c2-7988-4b37-aa1d-b2546d907bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460947046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2460947046
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3025285078
Short name T62
Test name
Test status
Simulation time 36030423436 ps
CPU time 20.59 seconds
Started Aug 15 05:58:21 PM PDT 24
Finished Aug 15 05:58:42 PM PDT 24
Peak memory 195204 kb
Host smart-48bf6aaf-d3e9-475f-81a1-8a43eb7fb9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025285078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3025285078
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2815288755
Short name T425
Test name
Test status
Simulation time 26269448 ps
CPU time 0.58 seconds
Started Aug 15 05:58:19 PM PDT 24
Finished Aug 15 05:58:20 PM PDT 24
Peak memory 183268 kb
Host smart-8a433b44-fb55-409f-94ec-3a9c9fba17cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815288755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2815288755
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.272144972
Short name T282
Test name
Test status
Simulation time 6151763780 ps
CPU time 11.38 seconds
Started Aug 15 05:58:17 PM PDT 24
Finished Aug 15 05:58:29 PM PDT 24
Peak memory 183524 kb
Host smart-eff9ae85-34e4-4d41-a832-7b94410929fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272144972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.272144972
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3481546484
Short name T400
Test name
Test status
Simulation time 84825703693 ps
CPU time 43.44 seconds
Started Aug 15 05:58:19 PM PDT 24
Finished Aug 15 05:59:03 PM PDT 24
Peak memory 183580 kb
Host smart-b7d27cfd-ea7e-481f-b22f-420728ac4005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481546484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3481546484
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.718800778
Short name T27
Test name
Test status
Simulation time 49931610318 ps
CPU time 88.85 seconds
Started Aug 15 05:58:19 PM PDT 24
Finished Aug 15 05:59:48 PM PDT 24
Peak memory 183524 kb
Host smart-abc83761-54cd-4b75-b45e-248f5cea0a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718800778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.718800778
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2813127161
Short name T138
Test name
Test status
Simulation time 1809930285717 ps
CPU time 4004.89 seconds
Started Aug 15 05:58:23 PM PDT 24
Finished Aug 15 07:05:08 PM PDT 24
Peak memory 191740 kb
Host smart-d942bef2-1310-4710-b5f7-314193827bbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813127161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2813127161
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1034891484
Short name T418
Test name
Test status
Simulation time 195752848223 ps
CPU time 310.96 seconds
Started Aug 15 05:58:19 PM PDT 24
Finished Aug 15 06:03:30 PM PDT 24
Peak memory 183356 kb
Host smart-6c764b11-dca3-4566-a180-2e097dea57e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034891484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1034891484
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1772518971
Short name T426
Test name
Test status
Simulation time 290914798537 ps
CPU time 107.05 seconds
Started Aug 15 05:58:20 PM PDT 24
Finished Aug 15 06:00:08 PM PDT 24
Peak memory 183548 kb
Host smart-d8f5a0f5-7005-418a-8772-b7126f01c7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772518971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1772518971
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1877381532
Short name T357
Test name
Test status
Simulation time 591692651333 ps
CPU time 694.09 seconds
Started Aug 15 05:58:22 PM PDT 24
Finished Aug 15 06:09:56 PM PDT 24
Peak memory 191796 kb
Host smart-fbdb608f-2374-4819-aa37-44a89c257ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877381532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1877381532
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.4106865397
Short name T383
Test name
Test status
Simulation time 167925278 ps
CPU time 0.91 seconds
Started Aug 15 05:58:22 PM PDT 24
Finished Aug 15 05:58:23 PM PDT 24
Peak memory 192104 kb
Host smart-1b762fc8-78de-4c71-890a-ab4973d230ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106865397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.4106865397
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3319946980
Short name T336
Test name
Test status
Simulation time 1177375952808 ps
CPU time 1185.69 seconds
Started Aug 15 05:58:22 PM PDT 24
Finished Aug 15 06:18:08 PM PDT 24
Peak memory 183568 kb
Host smart-ca3479c8-cb60-4217-b6f2-fb606f8966e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319946980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3319946980
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.789706692
Short name T409
Test name
Test status
Simulation time 374802452246 ps
CPU time 165.71 seconds
Started Aug 15 05:58:17 PM PDT 24
Finished Aug 15 06:01:03 PM PDT 24
Peak memory 183560 kb
Host smart-226f6a79-599d-43a3-bef9-2f22df34e5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789706692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.789706692
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3249198078
Short name T110
Test name
Test status
Simulation time 172820879544 ps
CPU time 156.12 seconds
Started Aug 15 05:58:19 PM PDT 24
Finished Aug 15 06:00:55 PM PDT 24
Peak memory 191812 kb
Host smart-0dacf8d9-9975-4ef9-924e-f0eb1ea8983c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249198078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3249198078
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.722290132
Short name T237
Test name
Test status
Simulation time 107487845732 ps
CPU time 300.85 seconds
Started Aug 15 05:58:25 PM PDT 24
Finished Aug 15 06:03:26 PM PDT 24
Peak memory 195252 kb
Host smart-93f854aa-1e94-4bdd-8a44-93669809d96f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722290132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
722290132
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.3792141765
Short name T14
Test name
Test status
Simulation time 5696736318 ps
CPU time 34.48 seconds
Started Aug 15 05:58:18 PM PDT 24
Finished Aug 15 05:58:53 PM PDT 24
Peak memory 198292 kb
Host smart-ac026c87-078e-4830-aa2b-5c105519a834
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792141765 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.3792141765
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.70789945
Short name T395
Test name
Test status
Simulation time 514345222609 ps
CPU time 219.45 seconds
Started Aug 15 05:58:26 PM PDT 24
Finished Aug 15 06:02:06 PM PDT 24
Peak memory 183584 kb
Host smart-886711fe-e785-445a-ac91-dce5a72fe8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70789945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.70789945
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.878222816
Short name T450
Test name
Test status
Simulation time 15817482019 ps
CPU time 33.17 seconds
Started Aug 15 05:58:26 PM PDT 24
Finished Aug 15 05:58:59 PM PDT 24
Peak memory 198308 kb
Host smart-be31cfc9-d802-49b9-895e-e6b058af0e45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878222816 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.878222816
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.4259084777
Short name T270
Test name
Test status
Simulation time 266109379903 ps
CPU time 454.4 seconds
Started Aug 15 05:58:24 PM PDT 24
Finished Aug 15 06:05:58 PM PDT 24
Peak memory 183556 kb
Host smart-b5a7fd3f-6cf5-4001-8cf8-de3a531bdb29
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259084777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.4259084777
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.4230810059
Short name T381
Test name
Test status
Simulation time 84296891 ps
CPU time 0.7 seconds
Started Aug 15 05:58:29 PM PDT 24
Finished Aug 15 05:58:30 PM PDT 24
Peak memory 183248 kb
Host smart-77c57cc2-2954-4fc3-9297-db20bb5adcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230810059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.4230810059
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.583988611
Short name T68
Test name
Test status
Simulation time 1271979846455 ps
CPU time 524.39 seconds
Started Aug 15 05:58:25 PM PDT 24
Finished Aug 15 06:07:10 PM PDT 24
Peak memory 191724 kb
Host smart-406d0966-aced-4f5a-ade6-02b4c586399a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583988611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
583988611
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.229638827
Short name T297
Test name
Test status
Simulation time 173685963826 ps
CPU time 304.8 seconds
Started Aug 15 05:58:26 PM PDT 24
Finished Aug 15 06:03:31 PM PDT 24
Peak memory 183492 kb
Host smart-37d2ad6f-9e19-4243-b94f-07cf0a354a14
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229638827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.229638827
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2640005939
Short name T428
Test name
Test status
Simulation time 106398668951 ps
CPU time 85.29 seconds
Started Aug 15 05:58:24 PM PDT 24
Finished Aug 15 05:59:50 PM PDT 24
Peak memory 183560 kb
Host smart-5be0f2f6-d764-43fd-bd7e-11589db177b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640005939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2640005939
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1850556593
Short name T207
Test name
Test status
Simulation time 838285518167 ps
CPU time 332.55 seconds
Started Aug 15 05:58:32 PM PDT 24
Finished Aug 15 06:04:05 PM PDT 24
Peak memory 191732 kb
Host smart-6c37aca1-cc6f-4cf4-8dc5-7b69bb84f699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850556593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1850556593
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2463448278
Short name T447
Test name
Test status
Simulation time 36914375407 ps
CPU time 195.95 seconds
Started Aug 15 05:58:25 PM PDT 24
Finished Aug 15 06:01:41 PM PDT 24
Peak memory 191772 kb
Host smart-b81d59e2-208c-47a2-a9f5-6b9c37dbc6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463448278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2463448278
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.816477799
Short name T13
Test name
Test status
Simulation time 3608177284 ps
CPU time 28.75 seconds
Started Aug 15 05:58:25 PM PDT 24
Finished Aug 15 05:58:54 PM PDT 24
Peak memory 198268 kb
Host smart-79b3cf97-288e-474f-abfc-0934f1fbfd2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816477799 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.816477799
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2040400580
Short name T210
Test name
Test status
Simulation time 1048687484804 ps
CPU time 239.03 seconds
Started Aug 15 05:58:06 PM PDT 24
Finished Aug 15 06:02:05 PM PDT 24
Peak memory 183544 kb
Host smart-7026d1ea-97d9-4ff0-ac5f-1c8dceda76e8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040400580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2040400580
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3046684694
Short name T368
Test name
Test status
Simulation time 28194194275 ps
CPU time 42.03 seconds
Started Aug 15 05:58:04 PM PDT 24
Finished Aug 15 05:58:46 PM PDT 24
Peak memory 183580 kb
Host smart-42711bcd-2e78-4934-9893-0e9d36b9c3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046684694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3046684694
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.664363208
Short name T61
Test name
Test status
Simulation time 433380106748 ps
CPU time 407.44 seconds
Started Aug 15 05:58:04 PM PDT 24
Finished Aug 15 06:04:52 PM PDT 24
Peak memory 191760 kb
Host smart-fa9cc430-3189-414a-94a1-9ef083559c4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664363208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.664363208
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2156609615
Short name T247
Test name
Test status
Simulation time 402124845134 ps
CPU time 165.37 seconds
Started Aug 15 05:58:08 PM PDT 24
Finished Aug 15 06:00:54 PM PDT 24
Peak memory 191776 kb
Host smart-97a97ac7-2cfe-498a-bc90-e1861670f9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156609615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2156609615
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2571420163
Short name T20
Test name
Test status
Simulation time 33017110 ps
CPU time 0.73 seconds
Started Aug 15 05:58:06 PM PDT 24
Finished Aug 15 05:58:07 PM PDT 24
Peak memory 213788 kb
Host smart-0b4a9ba6-6364-45b0-bc3e-dcf37bbe9ba0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571420163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2571420163
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.965051407
Short name T280
Test name
Test status
Simulation time 248042217935 ps
CPU time 983.52 seconds
Started Aug 15 05:58:02 PM PDT 24
Finished Aug 15 06:14:26 PM PDT 24
Peak memory 196188 kb
Host smart-00136922-1e26-44f5-a54f-099d03cd2f2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965051407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.965051407
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3997719427
Short name T385
Test name
Test status
Simulation time 349512525124 ps
CPU time 273.37 seconds
Started Aug 15 05:58:29 PM PDT 24
Finished Aug 15 06:03:02 PM PDT 24
Peak memory 183536 kb
Host smart-54f8dff4-c852-43a0-9f13-84468d7b7314
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997719427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3997719427
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3880847287
Short name T392
Test name
Test status
Simulation time 988247743305 ps
CPU time 258.03 seconds
Started Aug 15 05:58:26 PM PDT 24
Finished Aug 15 06:02:45 PM PDT 24
Peak memory 183496 kb
Host smart-516879a0-1e14-4f69-858f-7eb5ffed3d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880847287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3880847287
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2398628595
Short name T50
Test name
Test status
Simulation time 301861276666 ps
CPU time 278.34 seconds
Started Aug 15 05:58:34 PM PDT 24
Finished Aug 15 06:03:12 PM PDT 24
Peak memory 191720 kb
Host smart-f5dd285e-0c2f-4d76-a961-567dc6e30d6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398628595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2398628595
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3540414785
Short name T445
Test name
Test status
Simulation time 233558305336 ps
CPU time 96.15 seconds
Started Aug 15 05:58:27 PM PDT 24
Finished Aug 15 06:00:03 PM PDT 24
Peak memory 191784 kb
Host smart-5d4c287f-ea87-4e42-8089-98717c5f35cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540414785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3540414785
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1137133366
Short name T332
Test name
Test status
Simulation time 807064380543 ps
CPU time 1720.42 seconds
Started Aug 15 05:58:24 PM PDT 24
Finished Aug 15 06:27:05 PM PDT 24
Peak memory 191720 kb
Host smart-2600ef54-95c3-4cb0-871e-086b5aa4f9b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137133366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1137133366
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2182093178
Short name T413
Test name
Test status
Simulation time 10823022741 ps
CPU time 22.43 seconds
Started Aug 15 05:58:24 PM PDT 24
Finished Aug 15 05:58:46 PM PDT 24
Peak memory 198300 kb
Host smart-4fb6291b-3587-49ee-bd3c-87eabf5101dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182093178 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2182093178
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3226941078
Short name T121
Test name
Test status
Simulation time 534673732809 ps
CPU time 429.42 seconds
Started Aug 15 05:58:26 PM PDT 24
Finished Aug 15 06:05:35 PM PDT 24
Peak memory 183548 kb
Host smart-4e35ee5d-c24d-4464-b118-34d81a833161
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226941078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3226941078
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.229774677
Short name T394
Test name
Test status
Simulation time 416469789967 ps
CPU time 103.27 seconds
Started Aug 15 05:58:23 PM PDT 24
Finished Aug 15 06:00:06 PM PDT 24
Peak memory 183488 kb
Host smart-c3327a92-5d28-49ec-bd52-06df23486a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229774677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.229774677
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1629872824
Short name T344
Test name
Test status
Simulation time 229514532241 ps
CPU time 100.59 seconds
Started Aug 15 05:58:25 PM PDT 24
Finished Aug 15 06:00:06 PM PDT 24
Peak memory 191800 kb
Host smart-2d294577-dced-4aa7-bf8d-d18693c1b305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629872824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1629872824
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.704096659
Short name T125
Test name
Test status
Simulation time 1674680580183 ps
CPU time 680.13 seconds
Started Aug 15 05:58:24 PM PDT 24
Finished Aug 15 06:09:45 PM PDT 24
Peak memory 191788 kb
Host smart-8e3e84de-9b16-4b87-a16e-dedc0e7fc448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704096659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
704096659
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2791932423
Short name T256
Test name
Test status
Simulation time 69015148381 ps
CPU time 39.11 seconds
Started Aug 15 05:58:25 PM PDT 24
Finished Aug 15 05:59:05 PM PDT 24
Peak memory 183528 kb
Host smart-ea603d23-43d8-48d4-9011-635d3a153b12
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791932423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2791932423
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.457475897
Short name T366
Test name
Test status
Simulation time 932367268612 ps
CPU time 234.48 seconds
Started Aug 15 05:58:24 PM PDT 24
Finished Aug 15 06:02:19 PM PDT 24
Peak memory 183564 kb
Host smart-0dafc3f2-dced-4877-82f5-0c59b0c9b0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457475897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.457475897
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.677180182
Short name T220
Test name
Test status
Simulation time 75272985446 ps
CPU time 132.41 seconds
Started Aug 15 05:58:23 PM PDT 24
Finished Aug 15 06:00:36 PM PDT 24
Peak memory 191820 kb
Host smart-2b82def6-12e8-4bb5-b398-88fb20aad7c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677180182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.677180182
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.731817514
Short name T340
Test name
Test status
Simulation time 715176926717 ps
CPU time 235.49 seconds
Started Aug 15 05:58:32 PM PDT 24
Finished Aug 15 06:02:28 PM PDT 24
Peak memory 191712 kb
Host smart-4fbbc76e-da14-46a2-b231-84a85b062b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731817514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.731817514
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2201532731
Short name T312
Test name
Test status
Simulation time 3501619418648 ps
CPU time 776.26 seconds
Started Aug 15 05:58:25 PM PDT 24
Finished Aug 15 06:11:22 PM PDT 24
Peak memory 191776 kb
Host smart-028ca54b-5508-48b8-93a4-ef89881057e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201532731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2201532731
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1205303933
Short name T376
Test name
Test status
Simulation time 470990384171 ps
CPU time 255.23 seconds
Started Aug 15 05:58:27 PM PDT 24
Finished Aug 15 06:02:42 PM PDT 24
Peak memory 183532 kb
Host smart-b8930ba5-05f1-4080-b244-a12f804962a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205303933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1205303933
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.863493370
Short name T271
Test name
Test status
Simulation time 149265946243 ps
CPU time 69.1 seconds
Started Aug 15 05:58:27 PM PDT 24
Finished Aug 15 05:59:36 PM PDT 24
Peak memory 191792 kb
Host smart-ea99405a-a0fb-4f7a-ab36-d4c9f97ec8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863493370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.863493370
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1854290655
Short name T23
Test name
Test status
Simulation time 71335644204 ps
CPU time 647.56 seconds
Started Aug 15 05:58:27 PM PDT 24
Finished Aug 15 06:09:14 PM PDT 24
Peak memory 183516 kb
Host smart-58817b04-c462-4a04-9b65-5419b97fe50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854290655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1854290655
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1392160219
Short name T258
Test name
Test status
Simulation time 24896858796 ps
CPU time 44.89 seconds
Started Aug 15 05:58:26 PM PDT 24
Finished Aug 15 05:59:11 PM PDT 24
Peak memory 183504 kb
Host smart-02aeaad6-1df2-453c-aeb4-02c7c3e0dffc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392160219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1392160219
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.1567648175
Short name T111
Test name
Test status
Simulation time 173267979133 ps
CPU time 600.97 seconds
Started Aug 15 05:58:27 PM PDT 24
Finished Aug 15 06:08:28 PM PDT 24
Peak memory 191744 kb
Host smart-7dbaa76c-c6fc-4ac8-a9df-24ccac17b7ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567648175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1567648175
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1340764603
Short name T430
Test name
Test status
Simulation time 6910159480 ps
CPU time 66.96 seconds
Started Aug 15 05:58:25 PM PDT 24
Finished Aug 15 05:59:33 PM PDT 24
Peak memory 183540 kb
Host smart-c87e3321-79e3-4cf9-a341-d38a99499b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340764603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1340764603
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3896282712
Short name T104
Test name
Test status
Simulation time 219153104698 ps
CPU time 315.6 seconds
Started Aug 15 05:58:24 PM PDT 24
Finished Aug 15 06:03:40 PM PDT 24
Peak memory 191732 kb
Host smart-cc5af63f-78b2-4755-8e82-7080c31f2f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896282712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3896282712
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3322233101
Short name T294
Test name
Test status
Simulation time 218277263077 ps
CPU time 351.69 seconds
Started Aug 15 05:58:36 PM PDT 24
Finished Aug 15 06:04:27 PM PDT 24
Peak memory 183552 kb
Host smart-5838f3ee-9d0c-4780-abdb-58f62b5709b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322233101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3322233101
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1665575195
Short name T386
Test name
Test status
Simulation time 59061249568 ps
CPU time 86.29 seconds
Started Aug 15 05:58:37 PM PDT 24
Finished Aug 15 06:00:04 PM PDT 24
Peak memory 183548 kb
Host smart-ace0bc7f-2f38-4ea4-81c6-14e8e366c54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665575195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1665575195
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.88600666
Short name T350
Test name
Test status
Simulation time 259391802004 ps
CPU time 119.1 seconds
Started Aug 15 05:58:36 PM PDT 24
Finished Aug 15 06:00:36 PM PDT 24
Peak memory 191776 kb
Host smart-a1a64e40-b6fc-4bda-9557-eb7c112f0c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88600666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.88600666
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.919636098
Short name T365
Test name
Test status
Simulation time 466998074027 ps
CPU time 770.84 seconds
Started Aug 15 05:58:36 PM PDT 24
Finished Aug 15 06:11:27 PM PDT 24
Peak memory 191764 kb
Host smart-a58e199f-f00d-40d7-9842-9db2662d870b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919636098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
919636098
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1112619848
Short name T313
Test name
Test status
Simulation time 486285391207 ps
CPU time 396.02 seconds
Started Aug 15 05:58:38 PM PDT 24
Finished Aug 15 06:05:14 PM PDT 24
Peak memory 183528 kb
Host smart-e083c22e-c144-4716-a50a-cec66d2e959e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112619848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1112619848
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2076835965
Short name T398
Test name
Test status
Simulation time 146852959853 ps
CPU time 234.99 seconds
Started Aug 15 05:58:34 PM PDT 24
Finished Aug 15 06:02:30 PM PDT 24
Peak memory 183516 kb
Host smart-410233d8-844f-4918-a1f1-58fbc1488922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076835965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2076835965
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.4243369085
Short name T5
Test name
Test status
Simulation time 342364222682 ps
CPU time 516.82 seconds
Started Aug 15 05:58:36 PM PDT 24
Finished Aug 15 06:07:13 PM PDT 24
Peak memory 191792 kb
Host smart-e60dbbf5-3cf5-4bb4-bc6a-3959943127c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243369085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.4243369085
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3470683326
Short name T449
Test name
Test status
Simulation time 80144694508 ps
CPU time 289.48 seconds
Started Aug 15 05:58:36 PM PDT 24
Finished Aug 15 06:03:25 PM PDT 24
Peak memory 183560 kb
Host smart-5ac1fee4-11e1-43b6-9206-f7751887eba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470683326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3470683326
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.205403489
Short name T40
Test name
Test status
Simulation time 1149475733 ps
CPU time 10.11 seconds
Started Aug 15 05:58:36 PM PDT 24
Finished Aug 15 05:58:47 PM PDT 24
Peak memory 193912 kb
Host smart-acda35b7-a211-4aa3-b3ae-67c50197fa61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205403489 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.205403489
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2290291379
Short name T281
Test name
Test status
Simulation time 1031038219474 ps
CPU time 359.08 seconds
Started Aug 15 05:58:39 PM PDT 24
Finished Aug 15 06:04:38 PM PDT 24
Peak memory 183540 kb
Host smart-e73492b7-d964-4b8f-9d99-925eee38c101
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290291379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2290291379
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_random.3626875005
Short name T296
Test name
Test status
Simulation time 172793065970 ps
CPU time 524.45 seconds
Started Aug 15 05:58:36 PM PDT 24
Finished Aug 15 06:07:21 PM PDT 24
Peak memory 191784 kb
Host smart-e177d1bd-dd9c-4f13-ad30-617bb426baec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626875005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3626875005
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3743310166
Short name T208
Test name
Test status
Simulation time 421496459973 ps
CPU time 552.37 seconds
Started Aug 15 05:58:36 PM PDT 24
Finished Aug 15 06:07:49 PM PDT 24
Peak memory 191756 kb
Host smart-27918226-b2fb-4e21-8cd4-b8c67e6c8040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743310166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3743310166
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.886146056
Short name T261
Test name
Test status
Simulation time 8377646249775 ps
CPU time 2026.29 seconds
Started Aug 15 05:58:36 PM PDT 24
Finished Aug 15 06:32:23 PM PDT 24
Peak memory 191704 kb
Host smart-216b131d-7f9c-4508-8110-3907913e6eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886146056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
886146056
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.397337762
Short name T191
Test name
Test status
Simulation time 256171032186 ps
CPU time 132.48 seconds
Started Aug 15 05:58:37 PM PDT 24
Finished Aug 15 06:00:50 PM PDT 24
Peak memory 183524 kb
Host smart-354fb77c-adfc-416d-b417-7e9adaad056d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397337762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.397337762
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2416182111
Short name T399
Test name
Test status
Simulation time 550622448990 ps
CPU time 285.78 seconds
Started Aug 15 05:58:39 PM PDT 24
Finished Aug 15 06:03:25 PM PDT 24
Peak memory 183512 kb
Host smart-691d9c73-7ff7-4646-aa38-5128ba63f82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416182111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2416182111
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2338388373
Short name T438
Test name
Test status
Simulation time 177574562226 ps
CPU time 150.5 seconds
Started Aug 15 05:58:36 PM PDT 24
Finished Aug 15 06:01:07 PM PDT 24
Peak memory 191844 kb
Host smart-5f16fe1c-9604-4a08-92bb-303971266749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338388373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2338388373
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1524189715
Short name T126
Test name
Test status
Simulation time 27447772564 ps
CPU time 44.72 seconds
Started Aug 15 05:58:38 PM PDT 24
Finished Aug 15 05:59:23 PM PDT 24
Peak memory 191728 kb
Host smart-e9f4feaa-b1b4-436b-97a4-121369b94223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524189715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1524189715
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.2683158931
Short name T38
Test name
Test status
Simulation time 13535924039 ps
CPU time 20.47 seconds
Started Aug 15 05:58:35 PM PDT 24
Finished Aug 15 05:58:56 PM PDT 24
Peak memory 198272 kb
Host smart-6edaad68-a687-4849-8863-6f9d33d6b44d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683158931 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.2683158931
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1093439302
Short name T435
Test name
Test status
Simulation time 421297711878 ps
CPU time 372.69 seconds
Started Aug 15 05:58:37 PM PDT 24
Finished Aug 15 06:04:50 PM PDT 24
Peak memory 183560 kb
Host smart-60f8433e-ccc9-4645-a11b-f1ee19784ebe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093439302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1093439302
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.331359279
Short name T414
Test name
Test status
Simulation time 78792622391 ps
CPU time 38.07 seconds
Started Aug 15 05:58:38 PM PDT 24
Finished Aug 15 05:59:16 PM PDT 24
Peak memory 183548 kb
Host smart-815ef4c0-49b8-4396-8376-6106b0c687c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331359279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.331359279
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.53078420
Short name T388
Test name
Test status
Simulation time 33048967886 ps
CPU time 378.28 seconds
Started Aug 15 05:58:39 PM PDT 24
Finished Aug 15 06:04:58 PM PDT 24
Peak memory 183576 kb
Host smart-a3956c93-049e-44f1-ab1b-e19a959fa043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53078420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.53078420
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.4007186752
Short name T225
Test name
Test status
Simulation time 1770420920499 ps
CPU time 1651.93 seconds
Started Aug 15 05:58:06 PM PDT 24
Finished Aug 15 06:25:38 PM PDT 24
Peak memory 183560 kb
Host smart-ff516a19-c019-4d5a-99af-c4c31ffd1f48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007186752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.4007186752
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1761389123
Short name T384
Test name
Test status
Simulation time 123725446504 ps
CPU time 155.31 seconds
Started Aug 15 05:58:06 PM PDT 24
Finished Aug 15 06:00:41 PM PDT 24
Peak memory 183568 kb
Host smart-f2b00056-6d74-495f-87a6-d7d390015783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761389123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1761389123
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3883588829
Short name T273
Test name
Test status
Simulation time 126095164133 ps
CPU time 640.92 seconds
Started Aug 15 05:58:06 PM PDT 24
Finished Aug 15 06:08:47 PM PDT 24
Peak memory 191600 kb
Host smart-c2162817-b250-4fd8-b74d-e8a2bf4ed72b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883588829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3883588829
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1475815056
Short name T396
Test name
Test status
Simulation time 44185454034 ps
CPU time 514.19 seconds
Started Aug 15 05:58:02 PM PDT 24
Finished Aug 15 06:06:37 PM PDT 24
Peak memory 191736 kb
Host smart-737d090a-b305-4d83-b01c-7c450514d967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475815056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1475815056
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3243925759
Short name T16
Test name
Test status
Simulation time 125792021 ps
CPU time 0.75 seconds
Started Aug 15 05:58:00 PM PDT 24
Finished Aug 15 05:58:01 PM PDT 24
Peak memory 213884 kb
Host smart-9abd4df1-d65f-452d-bf9a-bf1b629d9f3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243925759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3243925759
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1794817503
Short name T209
Test name
Test status
Simulation time 1194300062820 ps
CPU time 543.2 seconds
Started Aug 15 05:58:41 PM PDT 24
Finished Aug 15 06:07:44 PM PDT 24
Peak memory 183500 kb
Host smart-110b0503-b0d9-4c79-bf80-1e6d1a738b07
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794817503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1794817503
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.854584936
Short name T451
Test name
Test status
Simulation time 15656953111 ps
CPU time 12.55 seconds
Started Aug 15 05:58:39 PM PDT 24
Finished Aug 15 05:58:52 PM PDT 24
Peak memory 183568 kb
Host smart-c5c97aa2-f950-4c9a-a60c-c8f5f6937371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854584936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.854584936
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.697985149
Short name T188
Test name
Test status
Simulation time 440945534702 ps
CPU time 373.9 seconds
Started Aug 15 05:58:39 PM PDT 24
Finished Aug 15 06:04:53 PM PDT 24
Peak memory 191784 kb
Host smart-4cd303b3-6482-447b-9792-547c76cf384f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697985149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.697985149
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2205223728
Short name T420
Test name
Test status
Simulation time 385769309 ps
CPU time 1.09 seconds
Started Aug 15 05:58:40 PM PDT 24
Finished Aug 15 05:58:41 PM PDT 24
Peak memory 183256 kb
Host smart-9f3e2220-351d-42c3-abb2-3d8970ef2683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205223728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2205223728
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.147783985
Short name T269
Test name
Test status
Simulation time 288757919790 ps
CPU time 155.24 seconds
Started Aug 15 05:58:42 PM PDT 24
Finished Aug 15 06:01:17 PM PDT 24
Peak memory 183548 kb
Host smart-f6338d66-235c-4650-bdf2-b048f987fbde
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147783985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.147783985
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2708358870
Short name T387
Test name
Test status
Simulation time 281974968108 ps
CPU time 125.54 seconds
Started Aug 15 05:58:40 PM PDT 24
Finished Aug 15 06:00:46 PM PDT 24
Peak memory 183580 kb
Host smart-5d745ff9-6ae2-4383-9944-8ea19ee97fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708358870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2708358870
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.954905561
Short name T334
Test name
Test status
Simulation time 43290590542 ps
CPU time 69.84 seconds
Started Aug 15 05:58:39 PM PDT 24
Finished Aug 15 05:59:49 PM PDT 24
Peak memory 183512 kb
Host smart-de35b1bf-757f-4203-a0bc-081b798f7165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954905561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.954905561
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2827504786
Short name T241
Test name
Test status
Simulation time 4183098248379 ps
CPU time 1550.05 seconds
Started Aug 15 05:58:41 PM PDT 24
Finished Aug 15 06:24:32 PM PDT 24
Peak memory 183544 kb
Host smart-42619817-acf0-45eb-be3f-e72affb3c72a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827504786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2827504786
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3128588733
Short name T389
Test name
Test status
Simulation time 174037930485 ps
CPU time 64.34 seconds
Started Aug 15 05:58:42 PM PDT 24
Finished Aug 15 05:59:47 PM PDT 24
Peak memory 183576 kb
Host smart-71d47ca0-4d55-4fb5-b500-24aa5bb15dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128588733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3128588733
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1943533153
Short name T245
Test name
Test status
Simulation time 151661887307 ps
CPU time 446.99 seconds
Started Aug 15 05:58:40 PM PDT 24
Finished Aug 15 06:06:07 PM PDT 24
Peak memory 195512 kb
Host smart-fe13674f-284e-4626-9a95-0e92f011a17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943533153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1943533153
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2702295880
Short name T310
Test name
Test status
Simulation time 525235510309 ps
CPU time 611.33 seconds
Started Aug 15 05:58:42 PM PDT 24
Finished Aug 15 06:08:53 PM PDT 24
Peak memory 195180 kb
Host smart-fab6418a-f4d1-4454-bc59-996abd543f29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702295880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2702295880
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.1552122322
Short name T446
Test name
Test status
Simulation time 3818011046 ps
CPU time 37.34 seconds
Started Aug 15 05:58:42 PM PDT 24
Finished Aug 15 05:59:19 PM PDT 24
Peak memory 198224 kb
Host smart-b40d1e0f-542d-44fa-87f9-29e278fd136c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552122322 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.1552122322
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3001263155
Short name T7
Test name
Test status
Simulation time 129190499207 ps
CPU time 101.02 seconds
Started Aug 15 05:58:40 PM PDT 24
Finished Aug 15 06:00:21 PM PDT 24
Peak memory 183500 kb
Host smart-ff024dfb-40f1-4d3b-9a0f-a4d267a331a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001263155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3001263155
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1380647215
Short name T433
Test name
Test status
Simulation time 81245298972 ps
CPU time 126.1 seconds
Started Aug 15 05:58:41 PM PDT 24
Finished Aug 15 06:00:47 PM PDT 24
Peak memory 195400 kb
Host smart-33c55a68-21c7-4b74-95fa-cc935fea5572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380647215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1380647215
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.898762536
Short name T324
Test name
Test status
Simulation time 7236965184 ps
CPU time 13.55 seconds
Started Aug 15 05:58:41 PM PDT 24
Finished Aug 15 05:58:55 PM PDT 24
Peak memory 191768 kb
Host smart-814855a9-ed5a-4de0-98cb-270ffe8dd22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898762536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.898762536
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3259670012
Short name T60
Test name
Test status
Simulation time 500297143949 ps
CPU time 272.76 seconds
Started Aug 15 05:58:45 PM PDT 24
Finished Aug 15 06:03:18 PM PDT 24
Peak memory 191572 kb
Host smart-7773f249-636e-450a-ba83-bf7c2602f2dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259670012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3259670012
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.497162627
Short name T71
Test name
Test status
Simulation time 848441901406 ps
CPU time 459.4 seconds
Started Aug 15 05:58:50 PM PDT 24
Finished Aug 15 06:06:29 PM PDT 24
Peak memory 183564 kb
Host smart-8619437d-2b1f-4c6b-8d9f-0f93cb12df68
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497162627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.497162627
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1246513240
Short name T364
Test name
Test status
Simulation time 78852861323 ps
CPU time 101.66 seconds
Started Aug 15 05:58:49 PM PDT 24
Finished Aug 15 06:00:31 PM PDT 24
Peak memory 183608 kb
Host smart-54bcf487-9d81-473d-be0c-0c80353740d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246513240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1246513240
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.102251994
Short name T352
Test name
Test status
Simulation time 54715304939 ps
CPU time 108.87 seconds
Started Aug 15 05:58:46 PM PDT 24
Finished Aug 15 06:00:35 PM PDT 24
Peak memory 183592 kb
Host smart-1e9ae24e-5481-4785-85ff-264ffbcea054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102251994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.102251994
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.345864067
Short name T377
Test name
Test status
Simulation time 2768046639 ps
CPU time 5.29 seconds
Started Aug 15 05:58:48 PM PDT 24
Finished Aug 15 05:58:53 PM PDT 24
Peak memory 183564 kb
Host smart-ffa10f19-94aa-4db1-9674-d031fb3bd29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345864067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.345864067
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1319736029
Short name T22
Test name
Test status
Simulation time 22947611 ps
CPU time 0.58 seconds
Started Aug 15 05:58:49 PM PDT 24
Finished Aug 15 05:58:50 PM PDT 24
Peak memory 183292 kb
Host smart-d08d2622-0d0c-4da9-8d58-e4a87675b8e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319736029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1319736029
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.1251140919
Short name T37
Test name
Test status
Simulation time 3087725941 ps
CPU time 37.45 seconds
Started Aug 15 05:58:49 PM PDT 24
Finished Aug 15 05:59:26 PM PDT 24
Peak memory 198280 kb
Host smart-6ba1c118-a7f7-4e9e-a005-f8787b0d8c1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251140919 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.1251140919
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1074914816
Short name T183
Test name
Test status
Simulation time 87058609508 ps
CPU time 53.54 seconds
Started Aug 15 05:58:46 PM PDT 24
Finished Aug 15 05:59:40 PM PDT 24
Peak memory 183536 kb
Host smart-322ee10f-f3fa-4dd6-a86f-70e944127905
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074914816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1074914816
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.43064355
Short name T373
Test name
Test status
Simulation time 402640943061 ps
CPU time 173.5 seconds
Started Aug 15 05:58:47 PM PDT 24
Finished Aug 15 06:01:41 PM PDT 24
Peak memory 183572 kb
Host smart-ef6f6f5c-bed9-43a4-92d5-c48942114b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43064355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.43064355
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.38369623
Short name T244
Test name
Test status
Simulation time 176891531734 ps
CPU time 282.2 seconds
Started Aug 15 05:58:47 PM PDT 24
Finished Aug 15 06:03:30 PM PDT 24
Peak memory 191732 kb
Host smart-e6b075ff-16e6-4813-9b11-c0e8776b72fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38369623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.38369623
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1482978503
Short name T221
Test name
Test status
Simulation time 3574745009 ps
CPU time 1.99 seconds
Started Aug 15 05:58:46 PM PDT 24
Finished Aug 15 05:58:48 PM PDT 24
Peak memory 183548 kb
Host smart-ce6b723e-b33d-4aef-98a3-7eb6c25d226e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482978503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1482978503
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1251262597
Short name T164
Test name
Test status
Simulation time 83279641601 ps
CPU time 42.98 seconds
Started Aug 15 05:58:48 PM PDT 24
Finished Aug 15 05:59:31 PM PDT 24
Peak memory 183548 kb
Host smart-29b05027-ea5c-447e-a232-68da6803ca16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251262597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1251262597
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2412840869
Short name T416
Test name
Test status
Simulation time 48121592325 ps
CPU time 70.03 seconds
Started Aug 15 05:58:47 PM PDT 24
Finished Aug 15 05:59:57 PM PDT 24
Peak memory 183584 kb
Host smart-103e8a51-29d1-4b04-a657-6abe8ce7b3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412840869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2412840869
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3842510980
Short name T348
Test name
Test status
Simulation time 60045799926 ps
CPU time 184.39 seconds
Started Aug 15 05:58:45 PM PDT 24
Finished Aug 15 06:01:49 PM PDT 24
Peak memory 191772 kb
Host smart-fa76a9d7-1dd7-4ef6-a17d-5af3bfa06227
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842510980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3842510980
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1018987515
Short name T216
Test name
Test status
Simulation time 124475804791 ps
CPU time 110.69 seconds
Started Aug 15 05:58:47 PM PDT 24
Finished Aug 15 06:00:38 PM PDT 24
Peak memory 191748 kb
Host smart-37d2c9cf-08e4-40e5-aff5-403829599fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018987515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1018987515
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1327440088
Short name T295
Test name
Test status
Simulation time 29182179722 ps
CPU time 48.46 seconds
Started Aug 15 05:58:46 PM PDT 24
Finished Aug 15 05:59:35 PM PDT 24
Peak memory 183588 kb
Host smart-6431fade-ea35-4fdd-a9f2-0a9ac6a3b689
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327440088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1327440088
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2138570423
Short name T356
Test name
Test status
Simulation time 110594132496 ps
CPU time 181.27 seconds
Started Aug 15 05:58:48 PM PDT 24
Finished Aug 15 06:01:49 PM PDT 24
Peak memory 183532 kb
Host smart-cac0d7bf-539f-4b61-a442-fe6fd35a0e65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138570423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2138570423
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3008710003
Short name T421
Test name
Test status
Simulation time 183173654381 ps
CPU time 126.97 seconds
Started Aug 15 05:58:50 PM PDT 24
Finished Aug 15 06:00:57 PM PDT 24
Peak memory 183564 kb
Host smart-529f6464-01ef-492d-9e81-e7eb3a564595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008710003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3008710003
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2558611090
Short name T437
Test name
Test status
Simulation time 626597447 ps
CPU time 3.23 seconds
Started Aug 15 05:58:46 PM PDT 24
Finished Aug 15 05:58:49 PM PDT 24
Peak memory 191656 kb
Host smart-78b74df3-4241-469b-b29f-5bd89e75827c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558611090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2558611090
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2074017076
Short name T12
Test name
Test status
Simulation time 770003699278 ps
CPU time 1139.47 seconds
Started Aug 15 05:58:47 PM PDT 24
Finished Aug 15 06:17:46 PM PDT 24
Peak memory 191720 kb
Host smart-c140b3b0-77eb-4bff-ac98-64d8eeb29207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074017076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2074017076
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.708274009
Short name T279
Test name
Test status
Simulation time 115538394875 ps
CPU time 173.16 seconds
Started Aug 15 05:58:52 PM PDT 24
Finished Aug 15 06:01:45 PM PDT 24
Peak memory 183608 kb
Host smart-4fc4982f-35ce-4ab8-b546-7f1d6cfec561
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708274009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.708274009
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3810007234
Short name T379
Test name
Test status
Simulation time 176598182972 ps
CPU time 67.44 seconds
Started Aug 15 05:58:54 PM PDT 24
Finished Aug 15 06:00:02 PM PDT 24
Peak memory 183564 kb
Host smart-81c69a86-49b2-44e6-92af-81c1b1474bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810007234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3810007234
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1937756416
Short name T326
Test name
Test status
Simulation time 46326388947 ps
CPU time 84.06 seconds
Started Aug 15 05:58:52 PM PDT 24
Finished Aug 15 06:00:16 PM PDT 24
Peak memory 183564 kb
Host smart-e0df4e0e-dfd5-47e8-8043-458b9b404c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937756416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1937756416
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.592806251
Short name T10
Test name
Test status
Simulation time 306512984385 ps
CPU time 523.48 seconds
Started Aug 15 05:58:54 PM PDT 24
Finished Aug 15 06:07:38 PM PDT 24
Peak memory 183568 kb
Host smart-f451d687-71ba-4fee-97f5-ba7f9cfbbfa8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592806251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.592806251
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1657845022
Short name T2
Test name
Test status
Simulation time 142884550985 ps
CPU time 229.56 seconds
Started Aug 15 05:58:56 PM PDT 24
Finished Aug 15 06:02:46 PM PDT 24
Peak memory 183592 kb
Host smart-72eab39d-21e7-4fc3-9910-361916350faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657845022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1657845022
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.450967850
Short name T264
Test name
Test status
Simulation time 315927272748 ps
CPU time 218.78 seconds
Started Aug 15 05:58:52 PM PDT 24
Finished Aug 15 06:02:31 PM PDT 24
Peak memory 191760 kb
Host smart-e693abea-dc91-45dc-8435-a88f9b0fbedf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450967850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.450967850
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1088092674
Short name T436
Test name
Test status
Simulation time 27262967306 ps
CPU time 53.18 seconds
Started Aug 15 05:58:52 PM PDT 24
Finished Aug 15 05:59:45 PM PDT 24
Peak memory 191676 kb
Host smart-94ec8dfe-b091-496f-9928-dd2da7fcbe61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088092674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1088092674
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1653264096
Short name T407
Test name
Test status
Simulation time 30593056 ps
CPU time 0.54 seconds
Started Aug 15 05:58:54 PM PDT 24
Finished Aug 15 05:58:55 PM PDT 24
Peak memory 183064 kb
Host smart-6dd91077-0473-497b-aa54-62d6ce8dd7f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653264096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1653264096
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.908755289
Short name T41
Test name
Test status
Simulation time 4330154838 ps
CPU time 36.44 seconds
Started Aug 15 05:58:53 PM PDT 24
Finished Aug 15 05:59:30 PM PDT 24
Peak memory 195220 kb
Host smart-82e21d19-8ff2-403b-8690-9ea8d6bb1e1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908755289 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.908755289
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3163237984
Short name T266
Test name
Test status
Simulation time 218925248236 ps
CPU time 349.7 seconds
Started Aug 15 05:58:06 PM PDT 24
Finished Aug 15 06:03:56 PM PDT 24
Peak memory 183392 kb
Host smart-c16dd042-26ca-4ca5-ba87-02068e54ec2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163237984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3163237984
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.506110707
Short name T369
Test name
Test status
Simulation time 133855095621 ps
CPU time 190.98 seconds
Started Aug 15 05:58:03 PM PDT 24
Finished Aug 15 06:01:14 PM PDT 24
Peak memory 183524 kb
Host smart-5f2f4322-dc48-44db-ac22-639eb819a5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506110707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.506110707
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3954941597
Short name T358
Test name
Test status
Simulation time 294419779 ps
CPU time 2.25 seconds
Started Aug 15 05:58:02 PM PDT 24
Finished Aug 15 05:58:05 PM PDT 24
Peak memory 183460 kb
Host smart-22243e4d-7688-4616-b89e-729f2782479a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954941597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3954941597
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.1964537157
Short name T51
Test name
Test status
Simulation time 58614021475 ps
CPU time 1116.63 seconds
Started Aug 15 05:58:54 PM PDT 24
Finished Aug 15 06:17:31 PM PDT 24
Peak memory 191748 kb
Host smart-099ba189-fd93-4293-9e05-71d80d67cc00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964537157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1964537157
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3045772994
Short name T240
Test name
Test status
Simulation time 42708137305 ps
CPU time 239.2 seconds
Started Aug 15 05:58:54 PM PDT 24
Finished Aug 15 06:02:53 PM PDT 24
Peak memory 191756 kb
Host smart-96bb566e-087c-4863-83e9-4d72be30d137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045772994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3045772994
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1509799068
Short name T346
Test name
Test status
Simulation time 98008794419 ps
CPU time 101.88 seconds
Started Aug 15 05:58:55 PM PDT 24
Finished Aug 15 06:00:37 PM PDT 24
Peak memory 192868 kb
Host smart-229cfb44-0de7-4dd2-9aa2-6a7859327945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509799068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1509799068
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.488748579
Short name T268
Test name
Test status
Simulation time 6803903980 ps
CPU time 11.6 seconds
Started Aug 15 05:58:59 PM PDT 24
Finished Aug 15 05:59:11 PM PDT 24
Peak memory 191780 kb
Host smart-efafbd77-c0d9-4795-a82a-49560a08f968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488748579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.488748579
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1795450900
Short name T119
Test name
Test status
Simulation time 759223665434 ps
CPU time 2785.54 seconds
Started Aug 15 05:59:01 PM PDT 24
Finished Aug 15 06:45:27 PM PDT 24
Peak memory 191760 kb
Host smart-4ad79cc0-ef9b-46ad-8e6e-4ef3c97d302f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795450900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1795450900
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1027658592
Short name T122
Test name
Test status
Simulation time 1917371736936 ps
CPU time 582.69 seconds
Started Aug 15 05:59:03 PM PDT 24
Finished Aug 15 06:08:46 PM PDT 24
Peak memory 191756 kb
Host smart-0ad76ced-b7d3-432c-8170-b5b1c1117842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027658592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1027658592
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.4103631546
Short name T318
Test name
Test status
Simulation time 24454531878 ps
CPU time 12.21 seconds
Started Aug 15 05:58:02 PM PDT 24
Finished Aug 15 05:58:14 PM PDT 24
Peak memory 183572 kb
Host smart-9e883bb5-32fd-4e54-bdf9-09b4c6839cd8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103631546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.4103631546
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1580882150
Short name T360
Test name
Test status
Simulation time 10467082727 ps
CPU time 7.42 seconds
Started Aug 15 05:58:01 PM PDT 24
Finished Aug 15 05:58:08 PM PDT 24
Peak memory 183556 kb
Host smart-28764877-468e-4053-ba0f-82f27a343eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580882150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1580882150
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.583339381
Short name T156
Test name
Test status
Simulation time 331121717862 ps
CPU time 100.01 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 05:59:52 PM PDT 24
Peak memory 195372 kb
Host smart-76e76fc9-e64a-47e1-9307-527c8328a93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583339381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.583339381
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1587866435
Short name T401
Test name
Test status
Simulation time 358546284775 ps
CPU time 296.99 seconds
Started Aug 15 05:58:05 PM PDT 24
Finished Aug 15 06:03:03 PM PDT 24
Peak memory 183580 kb
Host smart-4ca4c00d-1cdd-4eef-912f-51581625737f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587866435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1587866435
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/61.rv_timer_random.750533544
Short name T286
Test name
Test status
Simulation time 166888424017 ps
CPU time 80.02 seconds
Started Aug 15 05:59:00 PM PDT 24
Finished Aug 15 06:00:20 PM PDT 24
Peak memory 191804 kb
Host smart-3f038ff7-fb6d-484c-b6e8-b9a9b82304bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750533544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.750533544
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.161012623
Short name T166
Test name
Test status
Simulation time 223273277596 ps
CPU time 230.65 seconds
Started Aug 15 05:59:01 PM PDT 24
Finished Aug 15 06:02:52 PM PDT 24
Peak memory 191784 kb
Host smart-66d42d18-d66a-448b-835b-01267c975508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161012623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.161012623
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3844422160
Short name T118
Test name
Test status
Simulation time 75350674960 ps
CPU time 2196.49 seconds
Started Aug 15 05:59:02 PM PDT 24
Finished Aug 15 06:35:39 PM PDT 24
Peak memory 195624 kb
Host smart-af09c864-582e-4c18-97c1-780154a0f5b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844422160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3844422160
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3549253475
Short name T339
Test name
Test status
Simulation time 488871667646 ps
CPU time 1118.29 seconds
Started Aug 15 05:59:02 PM PDT 24
Finished Aug 15 06:17:40 PM PDT 24
Peak memory 191756 kb
Host smart-d543d6c9-b16a-4cf1-81d9-a4137cb4e131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549253475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3549253475
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3471198682
Short name T431
Test name
Test status
Simulation time 83008977805 ps
CPU time 1688.8 seconds
Started Aug 15 05:59:00 PM PDT 24
Finished Aug 15 06:27:09 PM PDT 24
Peak memory 191784 kb
Host smart-cf0ed5bb-0dd9-41b0-b068-6f0c07fc67eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471198682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3471198682
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1616907106
Short name T341
Test name
Test status
Simulation time 345790011492 ps
CPU time 249.82 seconds
Started Aug 15 05:59:02 PM PDT 24
Finished Aug 15 06:03:12 PM PDT 24
Peak memory 191788 kb
Host smart-2be6d0b5-7194-4976-b7ab-3025be373e1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616907106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1616907106
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2964109978
Short name T127
Test name
Test status
Simulation time 162790973315 ps
CPU time 78.88 seconds
Started Aug 15 05:58:59 PM PDT 24
Finished Aug 15 06:00:18 PM PDT 24
Peak memory 191752 kb
Host smart-c15a6bd0-918e-4e81-bfa1-cc69b9c66b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964109978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2964109978
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.102029168
Short name T246
Test name
Test status
Simulation time 183580026286 ps
CPU time 104.02 seconds
Started Aug 15 05:59:12 PM PDT 24
Finished Aug 15 06:00:56 PM PDT 24
Peak memory 191760 kb
Host smart-798298ea-e34c-433e-a8b8-566a87ac5c66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102029168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.102029168
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.732975099
Short name T238
Test name
Test status
Simulation time 86034748326 ps
CPU time 555.94 seconds
Started Aug 15 05:59:08 PM PDT 24
Finished Aug 15 06:08:25 PM PDT 24
Peak memory 195396 kb
Host smart-793cd28f-d597-46e0-94e5-13f4680f020e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732975099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.732975099
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1412031817
Short name T353
Test name
Test status
Simulation time 838694740615 ps
CPU time 443.45 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 06:05:36 PM PDT 24
Peak memory 183592 kb
Host smart-cc0c9a4c-ad45-4cc4-8a5b-01ca4a33fbab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412031817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1412031817
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1701978834
Short name T390
Test name
Test status
Simulation time 102515420996 ps
CPU time 38.05 seconds
Started Aug 15 05:58:12 PM PDT 24
Finished Aug 15 05:58:50 PM PDT 24
Peak memory 183588 kb
Host smart-154e088f-0728-415c-8c83-6c1c21dc73fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701978834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1701978834
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.842316210
Short name T265
Test name
Test status
Simulation time 80022849181 ps
CPU time 130.68 seconds
Started Aug 15 05:58:10 PM PDT 24
Finished Aug 15 06:00:21 PM PDT 24
Peak memory 195524 kb
Host smart-2e490626-8972-4e16-8ea5-09897d99fa80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842316210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.842316210
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1627495005
Short name T403
Test name
Test status
Simulation time 853958615 ps
CPU time 1.85 seconds
Started Aug 15 05:58:00 PM PDT 24
Finished Aug 15 05:58:02 PM PDT 24
Peak memory 183464 kb
Host smart-8e241393-032d-4ed8-b707-1e7518930233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627495005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1627495005
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.872445464
Short name T415
Test name
Test status
Simulation time 531471028725 ps
CPU time 403.96 seconds
Started Aug 15 05:58:02 PM PDT 24
Finished Aug 15 06:04:47 PM PDT 24
Peak memory 194716 kb
Host smart-df3f6a03-8fec-4473-ad83-bb71e5969608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872445464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.872445464
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.657977621
Short name T163
Test name
Test status
Simulation time 2108844185272 ps
CPU time 386.84 seconds
Started Aug 15 05:59:07 PM PDT 24
Finished Aug 15 06:05:34 PM PDT 24
Peak memory 191732 kb
Host smart-3501fd6a-23cf-46e5-b676-c410760e62bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657977621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.657977621
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1858040779
Short name T331
Test name
Test status
Simulation time 70387327801 ps
CPU time 59.3 seconds
Started Aug 15 05:59:07 PM PDT 24
Finished Aug 15 06:00:06 PM PDT 24
Peak memory 183484 kb
Host smart-71dd2e75-8235-4f4f-8af5-63fb161f4cbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858040779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1858040779
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1028780975
Short name T227
Test name
Test status
Simulation time 89472357625 ps
CPU time 139.81 seconds
Started Aug 15 05:59:11 PM PDT 24
Finished Aug 15 06:01:31 PM PDT 24
Peak memory 191756 kb
Host smart-0557ce96-8252-4264-93cf-b42dceb718a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028780975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1028780975
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2184782018
Short name T167
Test name
Test status
Simulation time 78703573763 ps
CPU time 79.14 seconds
Started Aug 15 05:59:07 PM PDT 24
Finished Aug 15 06:00:27 PM PDT 24
Peak memory 191572 kb
Host smart-aec999ee-d8bd-4eb9-a07a-a48cc974adaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184782018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2184782018
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2320002031
Short name T252
Test name
Test status
Simulation time 58504985101 ps
CPU time 46.14 seconds
Started Aug 15 05:59:08 PM PDT 24
Finished Aug 15 05:59:55 PM PDT 24
Peak memory 183604 kb
Host smart-7ed27c41-583f-4c27-9450-77d38760de89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320002031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2320002031
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3722475018
Short name T422
Test name
Test status
Simulation time 430285757978 ps
CPU time 628.61 seconds
Started Aug 15 05:59:08 PM PDT 24
Finished Aug 15 06:09:36 PM PDT 24
Peak memory 191740 kb
Host smart-b191e923-f1ef-4d9a-b218-9940775fb191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722475018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3722475018
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1460232690
Short name T342
Test name
Test status
Simulation time 44391888125 ps
CPU time 640.79 seconds
Started Aug 15 05:59:08 PM PDT 24
Finished Aug 15 06:09:49 PM PDT 24
Peak memory 183504 kb
Host smart-8589aebe-5673-46dd-a139-bd556892d97b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460232690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1460232690
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.272839804
Short name T145
Test name
Test status
Simulation time 819239515970 ps
CPU time 443.29 seconds
Started Aug 15 05:58:08 PM PDT 24
Finished Aug 15 06:05:32 PM PDT 24
Peak memory 183456 kb
Host smart-d27f2a32-0fe5-47f1-b423-7d20bbf49b32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272839804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.272839804
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2988337418
Short name T432
Test name
Test status
Simulation time 349887833985 ps
CPU time 115.45 seconds
Started Aug 15 05:58:06 PM PDT 24
Finished Aug 15 06:00:01 PM PDT 24
Peak memory 183556 kb
Host smart-096b43c0-dcb6-4505-a7ce-ac142e5bf671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988337418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2988337418
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3528633172
Short name T351
Test name
Test status
Simulation time 29873121969 ps
CPU time 16.73 seconds
Started Aug 15 05:58:11 PM PDT 24
Finished Aug 15 05:58:28 PM PDT 24
Peak memory 195160 kb
Host smart-cada37bc-ae44-4c34-bfaa-75fa2219a7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528633172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3528633172
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2128453531
Short name T391
Test name
Test status
Simulation time 206567264 ps
CPU time 0.57 seconds
Started Aug 15 05:58:05 PM PDT 24
Finished Aug 15 05:58:06 PM PDT 24
Peak memory 183244 kb
Host smart-4f45e5a5-b383-4da2-819d-ed2b5a0c82cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128453531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2128453531
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.1879875042
Short name T330
Test name
Test status
Simulation time 183248206218 ps
CPU time 461 seconds
Started Aug 15 05:59:08 PM PDT 24
Finished Aug 15 06:06:49 PM PDT 24
Peak memory 191708 kb
Host smart-1988e0d0-12f3-48d4-bfd6-c9d71243935a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879875042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1879875042
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1172220393
Short name T155
Test name
Test status
Simulation time 451133913013 ps
CPU time 857.4 seconds
Started Aug 15 05:59:08 PM PDT 24
Finished Aug 15 06:13:26 PM PDT 24
Peak memory 191784 kb
Host smart-e50001e4-dc24-458e-80bf-e392c4ee9b12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172220393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1172220393
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.489825954
Short name T405
Test name
Test status
Simulation time 629959879 ps
CPU time 1.49 seconds
Started Aug 15 05:59:07 PM PDT 24
Finished Aug 15 05:59:08 PM PDT 24
Peak memory 183284 kb
Host smart-5895b50a-041a-4ffa-8966-11f8d69c4678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489825954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.489825954
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1800619097
Short name T307
Test name
Test status
Simulation time 400943054686 ps
CPU time 205.25 seconds
Started Aug 15 05:59:08 PM PDT 24
Finished Aug 15 06:02:33 PM PDT 24
Peak memory 195612 kb
Host smart-5530dc26-477d-4b3f-9452-50c12b288b2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800619097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1800619097
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1485759727
Short name T316
Test name
Test status
Simulation time 50001976075 ps
CPU time 98.51 seconds
Started Aug 15 05:59:09 PM PDT 24
Finished Aug 15 06:00:47 PM PDT 24
Peak memory 183520 kb
Host smart-0fabe4d1-492f-4142-8951-961d219b476f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485759727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1485759727
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3597235469
Short name T4
Test name
Test status
Simulation time 294433191963 ps
CPU time 395.76 seconds
Started Aug 15 05:59:09 PM PDT 24
Finished Aug 15 06:05:45 PM PDT 24
Peak memory 191772 kb
Host smart-86ec0761-64c4-4782-9267-55fcab65c40b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597235469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3597235469
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2379856214
Short name T292
Test name
Test status
Simulation time 78129762029 ps
CPU time 33.59 seconds
Started Aug 15 05:59:08 PM PDT 24
Finished Aug 15 05:59:42 PM PDT 24
Peak memory 183528 kb
Host smart-aa1b2fe0-f03c-4696-bb03-43367ab8fff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379856214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2379856214
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.431532499
Short name T178
Test name
Test status
Simulation time 36859203626 ps
CPU time 60.24 seconds
Started Aug 15 05:59:15 PM PDT 24
Finished Aug 15 06:00:16 PM PDT 24
Peak memory 183400 kb
Host smart-c66297ee-5ba2-40f6-b15d-1e127cf1d2f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431532499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.431532499
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2652509346
Short name T349
Test name
Test status
Simulation time 45639927746 ps
CPU time 97.13 seconds
Started Aug 15 05:59:15 PM PDT 24
Finished Aug 15 06:00:52 PM PDT 24
Peak memory 191768 kb
Host smart-0adf4e93-0d15-4dff-a339-90f23fa8f4e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652509346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2652509346
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2398773759
Short name T444
Test name
Test status
Simulation time 155467380858 ps
CPU time 145.46 seconds
Started Aug 15 05:58:04 PM PDT 24
Finished Aug 15 06:00:30 PM PDT 24
Peak memory 183544 kb
Host smart-26a655be-5bd3-47f2-b723-6b5bba41eba0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398773759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2398773759
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.823408195
Short name T361
Test name
Test status
Simulation time 294972061898 ps
CPU time 304.01 seconds
Started Aug 15 05:58:08 PM PDT 24
Finished Aug 15 06:03:13 PM PDT 24
Peak memory 183536 kb
Host smart-71fc50c9-18c3-4a96-996c-9607baaf4bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823408195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.823408195
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.928465059
Short name T128
Test name
Test status
Simulation time 166998787721 ps
CPU time 285.7 seconds
Started Aug 15 05:58:06 PM PDT 24
Finished Aug 15 06:02:52 PM PDT 24
Peak memory 191796 kb
Host smart-5234455f-c293-41bc-afda-a302b225033a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928465059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.928465059
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2475139036
Short name T329
Test name
Test status
Simulation time 164300779110 ps
CPU time 90.91 seconds
Started Aug 15 05:58:03 PM PDT 24
Finished Aug 15 05:59:34 PM PDT 24
Peak memory 195160 kb
Host smart-71257d5b-3ca1-44ef-8f9b-a2f4ffce451a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475139036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2475139036
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.65473781
Short name T146
Test name
Test status
Simulation time 1462098580412 ps
CPU time 360.77 seconds
Started Aug 15 05:58:05 PM PDT 24
Finished Aug 15 06:04:06 PM PDT 24
Peak memory 196196 kb
Host smart-83d4653b-982f-49f4-8870-02d81d6de79d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65473781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.65473781
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.4154399092
Short name T235
Test name
Test status
Simulation time 236502932693 ps
CPU time 404.69 seconds
Started Aug 15 05:59:22 PM PDT 24
Finished Aug 15 06:06:07 PM PDT 24
Peak memory 191792 kb
Host smart-11784bcf-024d-47c3-80d9-8d182df0642e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154399092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.4154399092
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.4084515813
Short name T305
Test name
Test status
Simulation time 296541895461 ps
CPU time 167.25 seconds
Started Aug 15 05:59:14 PM PDT 24
Finished Aug 15 06:02:02 PM PDT 24
Peak memory 191820 kb
Host smart-0fdb3544-a6a8-47ea-9925-0d0afeff8f9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084515813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.4084515813
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1852302829
Short name T443
Test name
Test status
Simulation time 276963645999 ps
CPU time 270.39 seconds
Started Aug 15 05:59:14 PM PDT 24
Finished Aug 15 06:03:45 PM PDT 24
Peak memory 193128 kb
Host smart-7d616315-7bf8-49b9-bbeb-74e68a0ea432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852302829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1852302829
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.4013281425
Short name T152
Test name
Test status
Simulation time 544444670103 ps
CPU time 479.15 seconds
Started Aug 15 05:59:16 PM PDT 24
Finished Aug 15 06:07:15 PM PDT 24
Peak memory 191772 kb
Host smart-248bf99c-59a0-454c-969d-ae6ea93239cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013281425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.4013281425
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2317292264
Short name T213
Test name
Test status
Simulation time 120578764038 ps
CPU time 350.2 seconds
Started Aug 15 05:59:14 PM PDT 24
Finished Aug 15 06:05:05 PM PDT 24
Peak memory 191752 kb
Host smart-77cefbcf-5dac-4fd7-878b-56b96de387af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317292264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2317292264
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.872334489
Short name T117
Test name
Test status
Simulation time 69991605959 ps
CPU time 97.57 seconds
Started Aug 15 05:59:15 PM PDT 24
Finished Aug 15 06:00:53 PM PDT 24
Peak memory 191792 kb
Host smart-93e9c448-4b08-4435-9a1b-f68b9bdf7d55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872334489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.872334489
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3328758253
Short name T182
Test name
Test status
Simulation time 22605957976 ps
CPU time 46.4 seconds
Started Aug 15 05:59:16 PM PDT 24
Finished Aug 15 06:00:03 PM PDT 24
Peak memory 191736 kb
Host smart-bd3617ed-90b8-4d5f-bdd2-4d273409b7ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328758253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3328758253
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.4220763072
Short name T198
Test name
Test status
Simulation time 658407521266 ps
CPU time 1190.23 seconds
Started Aug 15 05:59:16 PM PDT 24
Finished Aug 15 06:19:06 PM PDT 24
Peak memory 191748 kb
Host smart-329a2f69-0bbe-4da1-891f-4c01c9b52207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220763072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.4220763072
Directory /workspace/99.rv_timer_random/latest
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