Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
125458158 |
1 |
|
|
T1 |
495895 |
|
T2 |
1906 |
|
T3 |
20058 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
67404544 |
1 |
|
|
T1 |
480886 |
|
T2 |
1906 |
|
T3 |
12044 |
auto[1] |
58053614 |
1 |
|
|
T1 |
15009 |
|
T3 |
8014 |
|
T4 |
968842 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
125452131 |
1 |
|
|
T1 |
495883 |
|
T2 |
1906 |
|
T3 |
20058 |
auto[1] |
6027 |
1 |
|
|
T1 |
12 |
|
T4 |
18 |
|
T6 |
8 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
67401520 |
1 |
|
|
T1 |
480878 |
|
T2 |
1906 |
|
T3 |
12044 |
all_values[0] |
auto[0] |
auto[1] |
3024 |
1 |
|
|
T1 |
8 |
|
T4 |
4 |
|
T6 |
4 |
all_values[0] |
auto[1] |
auto[0] |
58050611 |
1 |
|
|
T1 |
15005 |
|
T3 |
8014 |
|
T4 |
968828 |
all_values[0] |
auto[1] |
auto[1] |
3003 |
1 |
|
|
T1 |
4 |
|
T4 |
14 |
|
T6 |
4 |