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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.58 99.36 99.04 100.00 100.00 100.00 99.09


Total test records in report: 581
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T509 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2436123571 Aug 16 05:32:26 PM PDT 24 Aug 16 05:32:27 PM PDT 24 22872352 ps
T510 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2045094059 Aug 16 05:32:26 PM PDT 24 Aug 16 05:32:27 PM PDT 24 37491649 ps
T511 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.569064942 Aug 16 05:32:26 PM PDT 24 Aug 16 05:32:27 PM PDT 24 95214566 ps
T512 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2981344263 Aug 16 05:32:28 PM PDT 24 Aug 16 05:32:29 PM PDT 24 14855098 ps
T513 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.527275727 Aug 16 05:32:22 PM PDT 24 Aug 16 05:32:23 PM PDT 24 49616768 ps
T514 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3193929577 Aug 16 05:32:27 PM PDT 24 Aug 16 05:32:28 PM PDT 24 108457378 ps
T515 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.760012445 Aug 16 05:32:13 PM PDT 24 Aug 16 05:32:14 PM PDT 24 17840273 ps
T516 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.243010105 Aug 16 05:32:08 PM PDT 24 Aug 16 05:32:08 PM PDT 24 231195191 ps
T517 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.34180288 Aug 16 05:32:23 PM PDT 24 Aug 16 05:32:24 PM PDT 24 49192725 ps
T518 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3448737217 Aug 16 05:32:15 PM PDT 24 Aug 16 05:32:16 PM PDT 24 21849087 ps
T519 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.457617320 Aug 16 05:32:08 PM PDT 24 Aug 16 05:32:09 PM PDT 24 48072432 ps
T520 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1309048484 Aug 16 05:32:22 PM PDT 24 Aug 16 05:32:23 PM PDT 24 50030708 ps
T521 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1000760852 Aug 16 05:32:08 PM PDT 24 Aug 16 05:32:09 PM PDT 24 38518246 ps
T522 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4032349448 Aug 16 05:32:16 PM PDT 24 Aug 16 05:32:17 PM PDT 24 36159919 ps
T523 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3127526614 Aug 16 05:32:35 PM PDT 24 Aug 16 05:32:36 PM PDT 24 41904524 ps
T524 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1263209329 Aug 16 05:32:22 PM PDT 24 Aug 16 05:32:23 PM PDT 24 76151161 ps
T525 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.4191302202 Aug 16 05:32:14 PM PDT 24 Aug 16 05:32:16 PM PDT 24 124238261 ps
T526 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3304375861 Aug 16 05:32:09 PM PDT 24 Aug 16 05:32:12 PM PDT 24 938549813 ps
T527 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1995126106 Aug 16 05:32:07 PM PDT 24 Aug 16 05:32:08 PM PDT 24 34544177 ps
T528 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.4208866805 Aug 16 05:32:15 PM PDT 24 Aug 16 05:32:15 PM PDT 24 173717534 ps
T529 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.363263014 Aug 16 05:32:23 PM PDT 24 Aug 16 05:32:24 PM PDT 24 33734237 ps
T530 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4072371381 Aug 16 05:32:29 PM PDT 24 Aug 16 05:32:30 PM PDT 24 43150637 ps
T531 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2816167822 Aug 16 05:32:24 PM PDT 24 Aug 16 05:32:25 PM PDT 24 183156335 ps
T532 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.968264374 Aug 16 05:32:15 PM PDT 24 Aug 16 05:32:16 PM PDT 24 75853012 ps
T533 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3023017720 Aug 16 05:32:19 PM PDT 24 Aug 16 05:32:19 PM PDT 24 30253076 ps
T534 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3454159838 Aug 16 05:32:21 PM PDT 24 Aug 16 05:32:24 PM PDT 24 193352954 ps
T535 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3126694305 Aug 16 05:32:20 PM PDT 24 Aug 16 05:32:21 PM PDT 24 168879858 ps
T536 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1305012301 Aug 16 05:32:27 PM PDT 24 Aug 16 05:32:28 PM PDT 24 32782844 ps
T537 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1980353226 Aug 16 05:32:22 PM PDT 24 Aug 16 05:32:23 PM PDT 24 14400550 ps
T538 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4144194503 Aug 16 05:32:09 PM PDT 24 Aug 16 05:32:10 PM PDT 24 19055190 ps
T539 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.512150974 Aug 16 05:32:14 PM PDT 24 Aug 16 05:32:17 PM PDT 24 155814515 ps
T540 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1315029766 Aug 16 05:32:19 PM PDT 24 Aug 16 05:32:20 PM PDT 24 16602953 ps
T541 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1326166933 Aug 16 05:32:21 PM PDT 24 Aug 16 05:32:22 PM PDT 24 229116646 ps
T542 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1209493930 Aug 16 05:32:07 PM PDT 24 Aug 16 05:32:08 PM PDT 24 48533635 ps
T543 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1048432994 Aug 16 05:32:24 PM PDT 24 Aug 16 05:32:25 PM PDT 24 14182543 ps
T544 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3278153067 Aug 16 05:32:14 PM PDT 24 Aug 16 05:32:15 PM PDT 24 58057577 ps
T545 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1263837007 Aug 16 05:32:15 PM PDT 24 Aug 16 05:32:16 PM PDT 24 62332116 ps
T546 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.594167739 Aug 16 05:32:29 PM PDT 24 Aug 16 05:32:30 PM PDT 24 28842645 ps
T547 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1660092378 Aug 16 05:32:14 PM PDT 24 Aug 16 05:32:15 PM PDT 24 17133966 ps
T548 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3292704483 Aug 16 05:32:17 PM PDT 24 Aug 16 05:32:19 PM PDT 24 41080899 ps
T549 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.636596496 Aug 16 05:32:16 PM PDT 24 Aug 16 05:32:16 PM PDT 24 15346495 ps
T550 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4031464498 Aug 16 05:32:21 PM PDT 24 Aug 16 05:32:22 PM PDT 24 29083716 ps
T551 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1981554655 Aug 16 05:32:28 PM PDT 24 Aug 16 05:32:29 PM PDT 24 22391363 ps
T552 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.200797800 Aug 16 05:32:23 PM PDT 24 Aug 16 05:32:25 PM PDT 24 120325444 ps
T81 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3132973383 Aug 16 05:32:07 PM PDT 24 Aug 16 05:32:08 PM PDT 24 17202388 ps
T82 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1311587123 Aug 16 05:32:09 PM PDT 24 Aug 16 05:32:09 PM PDT 24 34907612 ps
T553 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3666943208 Aug 16 05:32:10 PM PDT 24 Aug 16 05:32:11 PM PDT 24 31868143 ps
T83 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1357528070 Aug 16 05:32:12 PM PDT 24 Aug 16 05:32:13 PM PDT 24 159137432 ps
T84 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3034357225 Aug 16 05:32:09 PM PDT 24 Aug 16 05:32:10 PM PDT 24 25612347 ps
T554 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1037457070 Aug 16 05:32:13 PM PDT 24 Aug 16 05:32:14 PM PDT 24 59012793 ps
T555 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2895287785 Aug 16 05:32:18 PM PDT 24 Aug 16 05:32:19 PM PDT 24 35780331 ps
T556 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1121417054 Aug 16 05:32:25 PM PDT 24 Aug 16 05:32:25 PM PDT 24 51364108 ps
T557 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2290869876 Aug 16 05:32:15 PM PDT 24 Aug 16 05:32:16 PM PDT 24 16361625 ps
T558 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3480746969 Aug 16 05:32:20 PM PDT 24 Aug 16 05:32:23 PM PDT 24 151723911 ps
T559 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.647011614 Aug 16 05:32:09 PM PDT 24 Aug 16 05:32:10 PM PDT 24 12142226 ps
T560 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.166192273 Aug 16 05:32:14 PM PDT 24 Aug 16 05:32:14 PM PDT 24 15348951 ps
T561 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1040511866 Aug 16 05:32:13 PM PDT 24 Aug 16 05:32:13 PM PDT 24 16556299 ps
T562 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2226145530 Aug 16 05:32:26 PM PDT 24 Aug 16 05:32:27 PM PDT 24 30372089 ps
T563 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.761872117 Aug 16 05:32:09 PM PDT 24 Aug 16 05:32:11 PM PDT 24 149972215 ps
T564 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3973254079 Aug 16 05:32:17 PM PDT 24 Aug 16 05:32:21 PM PDT 24 589373948 ps
T565 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2581797564 Aug 16 05:32:26 PM PDT 24 Aug 16 05:32:26 PM PDT 24 46304720 ps
T85 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.96834727 Aug 16 05:32:26 PM PDT 24 Aug 16 05:32:27 PM PDT 24 11577374 ps
T566 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3684076510 Aug 16 05:32:21 PM PDT 24 Aug 16 05:32:22 PM PDT 24 206636838 ps
T567 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1910624225 Aug 16 05:32:19 PM PDT 24 Aug 16 05:32:20 PM PDT 24 89050421 ps
T568 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1472352029 Aug 16 05:32:23 PM PDT 24 Aug 16 05:32:24 PM PDT 24 63310526 ps
T569 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.85687458 Aug 16 05:32:09 PM PDT 24 Aug 16 05:32:11 PM PDT 24 33314957 ps
T570 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2889301536 Aug 16 05:32:22 PM PDT 24 Aug 16 05:32:23 PM PDT 24 11947435 ps
T571 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1132750354 Aug 16 05:32:19 PM PDT 24 Aug 16 05:32:20 PM PDT 24 57959594 ps
T572 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3943051153 Aug 16 05:32:18 PM PDT 24 Aug 16 05:32:19 PM PDT 24 15054176 ps
T88 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2584562898 Aug 16 05:32:16 PM PDT 24 Aug 16 05:32:16 PM PDT 24 52595850 ps
T573 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3983154850 Aug 16 05:32:18 PM PDT 24 Aug 16 05:32:19 PM PDT 24 48000148 ps
T574 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3899288809 Aug 16 05:32:23 PM PDT 24 Aug 16 05:32:24 PM PDT 24 12257189 ps
T575 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3015170063 Aug 16 05:32:27 PM PDT 24 Aug 16 05:32:27 PM PDT 24 46540861 ps
T576 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1457805933 Aug 16 05:32:09 PM PDT 24 Aug 16 05:32:12 PM PDT 24 749462155 ps
T86 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.484193248 Aug 16 05:32:20 PM PDT 24 Aug 16 05:32:20 PM PDT 24 18335820 ps
T577 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2414492575 Aug 16 05:32:13 PM PDT 24 Aug 16 05:32:14 PM PDT 24 76451212 ps
T578 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3988581683 Aug 16 05:32:15 PM PDT 24 Aug 16 05:32:15 PM PDT 24 55592657 ps
T579 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.865461935 Aug 16 05:32:20 PM PDT 24 Aug 16 05:32:21 PM PDT 24 22531734 ps
T580 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2742835678 Aug 16 05:32:28 PM PDT 24 Aug 16 05:32:29 PM PDT 24 19227579 ps
T87 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.68543454 Aug 16 05:32:09 PM PDT 24 Aug 16 05:32:09 PM PDT 24 12532994 ps
T581 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1520647517 Aug 16 05:32:26 PM PDT 24 Aug 16 05:32:27 PM PDT 24 12052760 ps

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2619607012
Short name T9
Test name
Test status
Simulation time 14299720814 ps
CPU time 30.18 seconds
Started Aug 16 06:27:15 PM PDT 24
Finished Aug 16 06:27:45 PM PDT 24
Peak memory 198292 kb
Host smart-6cd5d0c6-61cf-45ee-90a6-b137fb5ba0ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619607012 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2619607012
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2789378285
Short name T8
Test name
Test status
Simulation time 2311895119587 ps
CPU time 749.96 seconds
Started Aug 16 06:27:32 PM PDT 24
Finished Aug 16 06:40:02 PM PDT 24
Peak memory 197592 kb
Host smart-d2356ee7-9c48-4544-86d9-0e2af4b7feae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789378285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2789378285
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1428423623
Short name T62
Test name
Test status
Simulation time 1968609181288 ps
CPU time 1486.79 seconds
Started Aug 16 06:27:51 PM PDT 24
Finished Aug 16 06:52:39 PM PDT 24
Peak memory 196016 kb
Host smart-f1641f07-8948-44d4-bcf5-01539c008b04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428423623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1428423623
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2875849101
Short name T123
Test name
Test status
Simulation time 2219862463533 ps
CPU time 2831.18 seconds
Started Aug 16 06:27:40 PM PDT 24
Finished Aug 16 07:14:52 PM PDT 24
Peak memory 196832 kb
Host smart-6eca3eae-fe69-45cf-a7fb-2ed3ebee1600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875849101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2875849101
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2472647281
Short name T25
Test name
Test status
Simulation time 378719719 ps
CPU time 1.44 seconds
Started Aug 16 05:32:12 PM PDT 24
Finished Aug 16 05:32:14 PM PDT 24
Peak memory 195744 kb
Host smart-bc3195a5-c101-4b57-b4d9-c9f6a6c3bad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472647281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2472647281
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.258742109
Short name T64
Test name
Test status
Simulation time 2400174088150 ps
CPU time 2119.04 seconds
Started Aug 16 06:27:41 PM PDT 24
Finished Aug 16 07:03:00 PM PDT 24
Peak memory 191772 kb
Host smart-59b82915-dbd6-46c2-9d22-d97075440225
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258742109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
258742109
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1853746322
Short name T29
Test name
Test status
Simulation time 58059147 ps
CPU time 0.56 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:08 PM PDT 24
Peak memory 183304 kb
Host smart-5ad009c8-797d-4e7c-9b29-368f920961b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853746322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1853746322
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1322590738
Short name T204
Test name
Test status
Simulation time 3695903538837 ps
CPU time 1545.67 seconds
Started Aug 16 06:27:18 PM PDT 24
Finished Aug 16 06:53:04 PM PDT 24
Peak memory 191840 kb
Host smart-a920eb89-2706-4127-89c0-b5c7cbfef5fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322590738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1322590738
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1307268610
Short name T61
Test name
Test status
Simulation time 2256463788576 ps
CPU time 1338.08 seconds
Started Aug 16 06:27:52 PM PDT 24
Finished Aug 16 06:50:10 PM PDT 24
Peak memory 196592 kb
Host smart-d5aa4f6a-9776-4724-be47-3442eb485098
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307268610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1307268610
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1047921932
Short name T323
Test name
Test status
Simulation time 657351532602 ps
CPU time 978.47 seconds
Started Aug 16 06:27:46 PM PDT 24
Finished Aug 16 06:44:05 PM PDT 24
Peak memory 191752 kb
Host smart-a6b4a6ab-a918-4cfd-9dce-4c63a7ec3156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047921932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1047921932
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.796813440
Short name T215
Test name
Test status
Simulation time 2538630167564 ps
CPU time 2113.89 seconds
Started Aug 16 06:27:35 PM PDT 24
Finished Aug 16 07:02:49 PM PDT 24
Peak memory 191792 kb
Host smart-80125e45-4b4d-48b4-9525-c8321f09505d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796813440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
796813440
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3463273825
Short name T66
Test name
Test status
Simulation time 6740970522590 ps
CPU time 1481.92 seconds
Started Aug 16 06:27:41 PM PDT 24
Finished Aug 16 06:52:23 PM PDT 24
Peak memory 196592 kb
Host smart-a73794d9-9c0f-4d4d-827b-fa3f44cac719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463273825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3463273825
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3802148037
Short name T149
Test name
Test status
Simulation time 1206878642497 ps
CPU time 1897.07 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:59:31 PM PDT 24
Peak memory 196352 kb
Host smart-08e605f4-2b36-4d49-8877-f7f2bbda532b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802148037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3802148037
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1136433989
Short name T125
Test name
Test status
Simulation time 2029448429201 ps
CPU time 1940.52 seconds
Started Aug 16 06:27:36 PM PDT 24
Finished Aug 16 06:59:57 PM PDT 24
Peak memory 196348 kb
Host smart-1495ffe3-6a8e-4f63-93ea-d464421afa4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136433989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1136433989
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.11788066
Short name T297
Test name
Test status
Simulation time 503710630464 ps
CPU time 925.02 seconds
Started Aug 16 06:28:13 PM PDT 24
Finished Aug 16 06:43:38 PM PDT 24
Peak memory 195376 kb
Host smart-8d50a3a1-91ea-49f4-af15-e72103a35e15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11788066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.11788066
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2140793075
Short name T13
Test name
Test status
Simulation time 85956372 ps
CPU time 0.91 seconds
Started Aug 16 06:27:15 PM PDT 24
Finished Aug 16 06:27:16 PM PDT 24
Peak memory 214880 kb
Host smart-b5cdbcbf-95e4-4e50-84e0-0ee4c4f3ce51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140793075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2140793075
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.666622253
Short name T145
Test name
Test status
Simulation time 711305496529 ps
CPU time 734.75 seconds
Started Aug 16 06:27:26 PM PDT 24
Finished Aug 16 06:39:41 PM PDT 24
Peak memory 191780 kb
Host smart-72640cc0-66c6-42a8-bd4e-a4a6c37e62f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666622253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
666622253
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.33254526
Short name T190
Test name
Test status
Simulation time 220070969004 ps
CPU time 777.48 seconds
Started Aug 16 06:27:55 PM PDT 24
Finished Aug 16 06:40:53 PM PDT 24
Peak memory 191688 kb
Host smart-cea6aba8-a324-45c3-b71c-3a6f2dd0a3e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33254526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.33254526
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2213433576
Short name T30
Test name
Test status
Simulation time 1554898085953 ps
CPU time 4022.32 seconds
Started Aug 16 06:27:55 PM PDT 24
Finished Aug 16 07:34:58 PM PDT 24
Peak memory 191760 kb
Host smart-769847d5-3109-48a1-9883-87b40568e8ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213433576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2213433576
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/162.rv_timer_random.1807036410
Short name T244
Test name
Test status
Simulation time 405284639443 ps
CPU time 396.77 seconds
Started Aug 16 06:28:32 PM PDT 24
Finished Aug 16 06:35:10 PM PDT 24
Peak memory 191720 kb
Host smart-32fd853d-5f21-4d92-a9e4-6b5b34ead3f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807036410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1807036410
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.4070891881
Short name T191
Test name
Test status
Simulation time 1575996035664 ps
CPU time 834.94 seconds
Started Aug 16 06:27:58 PM PDT 24
Finished Aug 16 06:41:53 PM PDT 24
Peak memory 195896 kb
Host smart-8139beb4-4220-47df-b151-b7bad8dbc93a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070891881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.4070891881
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/106.rv_timer_random.2520989864
Short name T138
Test name
Test status
Simulation time 941285324403 ps
CPU time 495.45 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:36:18 PM PDT 24
Peak memory 191792 kb
Host smart-58a479f5-6b1d-4883-a55f-7a16a34c8241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520989864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2520989864
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1605129754
Short name T193
Test name
Test status
Simulation time 1830871327714 ps
CPU time 2676.27 seconds
Started Aug 16 06:27:57 PM PDT 24
Finished Aug 16 07:12:34 PM PDT 24
Peak memory 191780 kb
Host smart-8cbe4e15-4be8-4771-81b3-f3fec8b98481
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605129754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1605129754
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.686212124
Short name T152
Test name
Test status
Simulation time 885639887098 ps
CPU time 510.49 seconds
Started Aug 16 06:27:52 PM PDT 24
Finished Aug 16 06:36:22 PM PDT 24
Peak memory 196016 kb
Host smart-42a67ea9-3238-49ea-a83c-bdbfdafe83c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686212124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
686212124
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_random.1189893216
Short name T249
Test name
Test status
Simulation time 195791700153 ps
CPU time 428.12 seconds
Started Aug 16 06:27:29 PM PDT 24
Finished Aug 16 06:34:38 PM PDT 24
Peak memory 191800 kb
Host smart-e5ebcaab-79e2-4ca7-8b25-6d3effcfb088
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189893216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1189893216
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2787250530
Short name T22
Test name
Test status
Simulation time 135282881874 ps
CPU time 450.64 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:35:38 PM PDT 24
Peak memory 191768 kb
Host smart-7952a8f4-b460-49c9-ba6b-7e170bb4501c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787250530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2787250530
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3966835760
Short name T287
Test name
Test status
Simulation time 104399202298 ps
CPU time 244.17 seconds
Started Aug 16 06:28:24 PM PDT 24
Finished Aug 16 06:32:28 PM PDT 24
Peak memory 191772 kb
Host smart-891bd198-c36d-4e9d-98b8-c0ba5d61df82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966835760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3966835760
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2444173998
Short name T184
Test name
Test status
Simulation time 2306203121082 ps
CPU time 639.5 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:38:33 PM PDT 24
Peak memory 183500 kb
Host smart-67e4167f-e335-49a1-9682-174bc133a75a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444173998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2444173998
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random.538605171
Short name T165
Test name
Test status
Simulation time 105911023472 ps
CPU time 177.83 seconds
Started Aug 16 06:27:18 PM PDT 24
Finished Aug 16 06:30:16 PM PDT 24
Peak memory 191792 kb
Host smart-f52fd0ce-c019-4cbb-841e-303da438d42b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538605171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.538605171
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1132985830
Short name T147
Test name
Test status
Simulation time 378139725731 ps
CPU time 1143.02 seconds
Started Aug 16 06:27:21 PM PDT 24
Finished Aug 16 06:46:25 PM PDT 24
Peak memory 191768 kb
Host smart-339fda4a-bda6-4fa4-93c6-a5e4796aee2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132985830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1132985830
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/89.rv_timer_random.256804443
Short name T301
Test name
Test status
Simulation time 175782489200 ps
CPU time 279.35 seconds
Started Aug 16 06:27:59 PM PDT 24
Finished Aug 16 06:32:38 PM PDT 24
Peak memory 191720 kb
Host smart-3051964a-5b01-4d03-afe3-587fd6beea50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256804443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.256804443
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.4280170887
Short name T49
Test name
Test status
Simulation time 621446044 ps
CPU time 2.68 seconds
Started Aug 16 05:32:13 PM PDT 24
Finished Aug 16 05:32:16 PM PDT 24
Peak memory 198108 kb
Host smart-a872534f-be1b-4a62-936f-9cd3b5b7e91a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280170887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.4280170887
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/default/139.rv_timer_random.4241301703
Short name T209
Test name
Test status
Simulation time 424895477793 ps
CPU time 306.63 seconds
Started Aug 16 06:28:14 PM PDT 24
Finished Aug 16 06:33:20 PM PDT 24
Peak memory 195928 kb
Host smart-a06ee945-74d7-4027-b346-8f4cdc74f7a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241301703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.4241301703
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1035973796
Short name T196
Test name
Test status
Simulation time 357991145391 ps
CPU time 406.05 seconds
Started Aug 16 06:28:26 PM PDT 24
Finished Aug 16 06:35:12 PM PDT 24
Peak memory 191812 kb
Host smart-03bd1ef2-87db-4a46-a920-50fd5751dc59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035973796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1035973796
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.435227634
Short name T307
Test name
Test status
Simulation time 142130053949 ps
CPU time 1533.79 seconds
Started Aug 16 06:27:27 PM PDT 24
Finished Aug 16 06:53:01 PM PDT 24
Peak memory 191732 kb
Host smart-57fa4d63-df6a-4314-bb28-d352a2cb955a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435227634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.435227634
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.887158078
Short name T236
Test name
Test status
Simulation time 178676802199 ps
CPU time 269.72 seconds
Started Aug 16 06:27:52 PM PDT 24
Finished Aug 16 06:32:22 PM PDT 24
Peak memory 183584 kb
Host smart-8fcba726-77b9-4e66-9572-35417f4f84c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887158078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.887158078
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1217726288
Short name T4
Test name
Test status
Simulation time 6025122340799 ps
CPU time 1651.97 seconds
Started Aug 16 06:27:57 PM PDT 24
Finished Aug 16 06:55:29 PM PDT 24
Peak memory 191788 kb
Host smart-a31a8457-7d04-42e2-8ccb-65dd381a024a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217726288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1217726288
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/61.rv_timer_random.805037165
Short name T285
Test name
Test status
Simulation time 135859043598 ps
CPU time 509.57 seconds
Started Aug 16 06:27:57 PM PDT 24
Finished Aug 16 06:36:27 PM PDT 24
Peak memory 183592 kb
Host smart-39da2ca7-1d54-4f61-ae8b-992931636f76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805037165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.805037165
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1626672466
Short name T259
Test name
Test status
Simulation time 332142686741 ps
CPU time 521.49 seconds
Started Aug 16 06:28:00 PM PDT 24
Finished Aug 16 06:36:42 PM PDT 24
Peak memory 195848 kb
Host smart-b6971a8b-aa56-4fa7-ba1b-a1a55170eed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626672466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1626672466
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.359230252
Short name T120
Test name
Test status
Simulation time 264633833134 ps
CPU time 370.44 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:34:13 PM PDT 24
Peak memory 191804 kb
Host smart-13bffe69-7da1-4e64-851c-5e409d42d91c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359230252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.359230252
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3849840703
Short name T262
Test name
Test status
Simulation time 529114356903 ps
CPU time 798.81 seconds
Started Aug 16 06:27:37 PM PDT 24
Finished Aug 16 06:40:56 PM PDT 24
Peak memory 196708 kb
Host smart-f60bba56-cfa1-4315-a137-5bf7f5b4498e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849840703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3849840703
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_random.223896907
Short name T162
Test name
Test status
Simulation time 458474089754 ps
CPU time 597.72 seconds
Started Aug 16 06:27:17 PM PDT 24
Finished Aug 16 06:37:15 PM PDT 24
Peak memory 191724 kb
Host smart-39373e21-6bd1-48a9-9c01-aab33de557e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223896907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.223896907
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1087125221
Short name T226
Test name
Test status
Simulation time 278445654632 ps
CPU time 215.77 seconds
Started Aug 16 06:28:10 PM PDT 24
Finished Aug 16 06:31:45 PM PDT 24
Peak memory 191736 kb
Host smart-f6584345-dd1f-467f-a950-a27ffd460387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087125221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1087125221
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2998956366
Short name T261
Test name
Test status
Simulation time 1632063963659 ps
CPU time 3201.94 seconds
Started Aug 16 06:27:15 PM PDT 24
Finished Aug 16 07:20:38 PM PDT 24
Peak memory 196388 kb
Host smart-efbc61a5-257c-46be-b272-d9b38eee249a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998956366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2998956366
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/79.rv_timer_random.4230927053
Short name T159
Test name
Test status
Simulation time 2962660728156 ps
CPU time 1266.66 seconds
Started Aug 16 06:28:05 PM PDT 24
Finished Aug 16 06:49:12 PM PDT 24
Peak memory 191812 kb
Host smart-c636e31a-0933-400f-9e18-61ea19d13671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230927053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.4230927053
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3885871155
Short name T126
Test name
Test status
Simulation time 309751192124 ps
CPU time 284.37 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:32:48 PM PDT 24
Peak memory 191800 kb
Host smart-f5cae5df-0d54-4433-80d5-2e0a3300f83b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885871155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3885871155
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3339782076
Short name T282
Test name
Test status
Simulation time 284148075547 ps
CPU time 417.33 seconds
Started Aug 16 06:27:16 PM PDT 24
Finished Aug 16 06:34:13 PM PDT 24
Peak memory 191764 kb
Host smart-157c1d70-8947-40e4-aa70-1c666d2d3c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339782076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3339782076
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_random.2004454819
Short name T230
Test name
Test status
Simulation time 129011407814 ps
CPU time 186.5 seconds
Started Aug 16 06:27:59 PM PDT 24
Finished Aug 16 06:31:05 PM PDT 24
Peak memory 191716 kb
Host smart-dd615d44-459c-4f0e-ace8-4eaeb407f428
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004454819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2004454819
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random.1650297028
Short name T212
Test name
Test status
Simulation time 206672940073 ps
CPU time 730.85 seconds
Started Aug 16 06:27:57 PM PDT 24
Finished Aug 16 06:40:08 PM PDT 24
Peak memory 191776 kb
Host smart-e9052913-9282-4841-8760-d7337e230c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650297028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1650297028
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1341172992
Short name T92
Test name
Test status
Simulation time 24882035 ps
CPU time 0.73 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:10 PM PDT 24
Peak memory 192224 kb
Host smart-c68a1538-383a-48d4-9cac-b70cd8db0934
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341172992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1341172992
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/103.rv_timer_random.648396005
Short name T116
Test name
Test status
Simulation time 106897751524 ps
CPU time 219.8 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:31:42 PM PDT 24
Peak memory 191740 kb
Host smart-e138259a-0f04-464f-841d-29a8ce46d78d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648396005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.648396005
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2620410312
Short name T229
Test name
Test status
Simulation time 53670483226 ps
CPU time 102.45 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:29:50 PM PDT 24
Peak memory 191768 kb
Host smart-5692350f-2c4f-4e55-98a4-ee3a616ec3bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620410312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2620410312
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.621437884
Short name T258
Test name
Test status
Simulation time 108700843320 ps
CPU time 302.05 seconds
Started Aug 16 06:27:58 PM PDT 24
Finished Aug 16 06:33:00 PM PDT 24
Peak memory 191776 kb
Host smart-f3618f99-0bc1-4564-8ccc-1640930c446d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621437884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.621437884
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.776714456
Short name T187
Test name
Test status
Simulation time 501412125372 ps
CPU time 325.14 seconds
Started Aug 16 06:28:04 PM PDT 24
Finished Aug 16 06:33:29 PM PDT 24
Peak memory 191780 kb
Host smart-2a027093-d79f-4e40-abb5-0157cb2abdcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776714456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.776714456
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1324420879
Short name T298
Test name
Test status
Simulation time 158063976802 ps
CPU time 205.91 seconds
Started Aug 16 06:28:08 PM PDT 24
Finished Aug 16 06:31:34 PM PDT 24
Peak memory 191624 kb
Host smart-bac1736e-0033-46b7-bfe9-282096f29d30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324420879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1324420879
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.1411847992
Short name T109
Test name
Test status
Simulation time 131960107969 ps
CPU time 436.04 seconds
Started Aug 16 06:28:09 PM PDT 24
Finished Aug 16 06:35:25 PM PDT 24
Peak memory 191804 kb
Host smart-1e301227-e208-4e1b-85c4-432f0402c5b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411847992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1411847992
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.786674404
Short name T23
Test name
Test status
Simulation time 813652248444 ps
CPU time 817.74 seconds
Started Aug 16 06:28:10 PM PDT 24
Finished Aug 16 06:41:53 PM PDT 24
Peak memory 191744 kb
Host smart-7254752f-0616-49bf-8735-85e6d4e15270
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786674404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.786674404
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.1076566763
Short name T277
Test name
Test status
Simulation time 135074811683 ps
CPU time 261.47 seconds
Started Aug 16 06:27:41 PM PDT 24
Finished Aug 16 06:32:03 PM PDT 24
Peak memory 191760 kb
Host smart-fe36b477-0cd3-41be-8267-7de2b028c300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076566763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1076566763
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3472516587
Short name T104
Test name
Test status
Simulation time 167199006950 ps
CPU time 202.46 seconds
Started Aug 16 06:28:16 PM PDT 24
Finished Aug 16 06:31:38 PM PDT 24
Peak memory 191756 kb
Host smart-b161cd1c-ffc2-4711-95e8-65c0714733d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472516587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3472516587
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.986091641
Short name T140
Test name
Test status
Simulation time 315963405304 ps
CPU time 251.96 seconds
Started Aug 16 06:28:17 PM PDT 24
Finished Aug 16 06:32:29 PM PDT 24
Peak memory 191832 kb
Host smart-3569cca9-e93d-46b0-903d-5dcd1e671123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986091641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.986091641
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1663796265
Short name T233
Test name
Test status
Simulation time 336308012166 ps
CPU time 153.38 seconds
Started Aug 16 06:27:47 PM PDT 24
Finished Aug 16 06:30:21 PM PDT 24
Peak memory 183560 kb
Host smart-0ff45a53-c63d-4256-9fd3-ca56d1abd9aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663796265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1663796265
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/171.rv_timer_random.2174141471
Short name T199
Test name
Test status
Simulation time 291764323390 ps
CPU time 309.54 seconds
Started Aug 16 06:28:17 PM PDT 24
Finished Aug 16 06:33:26 PM PDT 24
Peak memory 191740 kb
Host smart-27534416-a4d0-4866-b2d3-e4b2855a5c2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174141471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2174141471
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2881500595
Short name T198
Test name
Test status
Simulation time 265420259844 ps
CPU time 507.16 seconds
Started Aug 16 06:28:23 PM PDT 24
Finished Aug 16 06:36:51 PM PDT 24
Peak memory 191864 kb
Host smart-1afa0aa7-99b5-4284-8c15-94bc4092f9bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881500595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2881500595
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2932146040
Short name T269
Test name
Test status
Simulation time 7702041511 ps
CPU time 35.21 seconds
Started Aug 16 06:27:26 PM PDT 24
Finished Aug 16 06:28:01 PM PDT 24
Peak memory 191788 kb
Host smart-939c38b8-4aa7-4264-a83b-354eb033269d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932146040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2932146040
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_random.1902949708
Short name T163
Test name
Test status
Simulation time 1090011802003 ps
CPU time 323.76 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:33:17 PM PDT 24
Peak memory 191776 kb
Host smart-f4bf1592-8bff-4ae3-a94c-2bcd0205e1b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902949708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1902949708
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2691511874
Short name T231
Test name
Test status
Simulation time 90056802440 ps
CPU time 128.18 seconds
Started Aug 16 06:27:16 PM PDT 24
Finished Aug 16 06:29:25 PM PDT 24
Peak memory 191864 kb
Host smart-e5ab2314-b543-4ed8-ba2e-05d4d2d5a2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691511874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2691511874
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2566037902
Short name T220
Test name
Test status
Simulation time 364629811420 ps
CPU time 2114.7 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 07:03:17 PM PDT 24
Peak memory 191696 kb
Host smart-f728228b-9ddf-4191-862c-3850697d970e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566037902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2566037902
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_random.602515343
Short name T260
Test name
Test status
Simulation time 517587470782 ps
CPU time 939.49 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:43:34 PM PDT 24
Peak memory 191808 kb
Host smart-0636419b-e244-4ef1-8bce-5fc61be530aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602515343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.602515343
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.261161508
Short name T134
Test name
Test status
Simulation time 159470890513 ps
CPU time 265.16 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:32:33 PM PDT 24
Peak memory 183560 kb
Host smart-fde8d6b8-c309-44ac-bb46-94aa30c15901
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261161508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.261161508
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/66.rv_timer_random.4284845459
Short name T232
Test name
Test status
Simulation time 186082772453 ps
CPU time 153.59 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:30:37 PM PDT 24
Peak memory 191800 kb
Host smart-434eae90-9ab3-4c3d-8a50-253b5fcc753f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284845459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.4284845459
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1870711225
Short name T169
Test name
Test status
Simulation time 399300130924 ps
CPU time 533.85 seconds
Started Aug 16 06:28:05 PM PDT 24
Finished Aug 16 06:36:59 PM PDT 24
Peak memory 191804 kb
Host smart-5acaee32-0c37-4e4b-9335-c4422b6f0904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870711225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1870711225
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2497100980
Short name T135
Test name
Test status
Simulation time 767112661141 ps
CPU time 511.24 seconds
Started Aug 16 06:28:01 PM PDT 24
Finished Aug 16 06:36:32 PM PDT 24
Peak memory 191800 kb
Host smart-457dac33-8e51-4e66-b2ba-7e4a6a9ce0be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497100980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2497100980
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1638618428
Short name T51
Test name
Test status
Simulation time 1122807503951 ps
CPU time 617.21 seconds
Started Aug 16 06:27:24 PM PDT 24
Finished Aug 16 06:37:41 PM PDT 24
Peak memory 183520 kb
Host smart-aa556b76-0835-4e41-a7fc-15f74d2d4727
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638618428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1638618428
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/135.rv_timer_random.1499053213
Short name T103
Test name
Test status
Simulation time 703457299554 ps
CPU time 767.04 seconds
Started Aug 16 06:28:07 PM PDT 24
Finished Aug 16 06:40:54 PM PDT 24
Peak memory 191804 kb
Host smart-f7813629-7314-4e13-b613-b0579f280cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499053213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1499053213
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.960083109
Short name T127
Test name
Test status
Simulation time 34022267288 ps
CPU time 273 seconds
Started Aug 16 06:28:18 PM PDT 24
Finished Aug 16 06:32:51 PM PDT 24
Peak memory 191784 kb
Host smart-b9f29aeb-5cd0-43b8-8123-3e10ea3a00b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960083109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.960083109
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1647199643
Short name T281
Test name
Test status
Simulation time 242450832217 ps
CPU time 147.25 seconds
Started Aug 16 06:28:11 PM PDT 24
Finished Aug 16 06:30:39 PM PDT 24
Peak memory 191816 kb
Host smart-f052cb9d-8d3e-4ab1-989f-e06c1952a4c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647199643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1647199643
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.87029627
Short name T107
Test name
Test status
Simulation time 104328235200 ps
CPU time 1028.94 seconds
Started Aug 16 06:28:23 PM PDT 24
Finished Aug 16 06:45:32 PM PDT 24
Peak memory 191796 kb
Host smart-8ab10c96-4a26-4654-afe7-0e528fb3ea45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87029627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.87029627
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.4226092492
Short name T333
Test name
Test status
Simulation time 1268422774696 ps
CPU time 514.42 seconds
Started Aug 16 06:27:58 PM PDT 24
Finished Aug 16 06:36:32 PM PDT 24
Peak memory 183564 kb
Host smart-ea1a90d7-980f-43c5-ae1b-80cfede04d37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226092492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.4226092492
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random.2650907509
Short name T160
Test name
Test status
Simulation time 150350299630 ps
CPU time 3070.01 seconds
Started Aug 16 06:27:35 PM PDT 24
Finished Aug 16 07:18:45 PM PDT 24
Peak memory 191720 kb
Host smart-3b657bf8-fed6-4ec6-8400-7b449e4261c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650907509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2650907509
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.1458172664
Short name T148
Test name
Test status
Simulation time 149705525200 ps
CPU time 886.79 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:42:41 PM PDT 24
Peak memory 191660 kb
Host smart-688f84ca-8fcb-469a-9c73-589c4299c248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458172664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1458172664
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.1967450916
Short name T54
Test name
Test status
Simulation time 118580315252 ps
CPU time 196.01 seconds
Started Aug 16 06:27:33 PM PDT 24
Finished Aug 16 06:30:49 PM PDT 24
Peak memory 193920 kb
Host smart-b33c8b35-9f21-485c-990a-adb334fa5250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967450916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1967450916
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3347482663
Short name T251
Test name
Test status
Simulation time 132148666226 ps
CPU time 63.71 seconds
Started Aug 16 06:27:55 PM PDT 24
Finished Aug 16 06:28:59 PM PDT 24
Peak memory 195176 kb
Host smart-00344521-c15f-40fb-95c3-30a3edac2e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347482663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3347482663
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_random.335063153
Short name T56
Test name
Test status
Simulation time 851905228257 ps
CPU time 671.64 seconds
Started Aug 16 06:27:56 PM PDT 24
Finished Aug 16 06:39:08 PM PDT 24
Peak memory 191780 kb
Host smart-44ec7b03-25e4-403b-929d-2203a4b7e6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335063153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.335063153
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random.405760694
Short name T153
Test name
Test status
Simulation time 373406726386 ps
CPU time 184.78 seconds
Started Aug 16 06:27:41 PM PDT 24
Finished Aug 16 06:30:46 PM PDT 24
Peak memory 191808 kb
Host smart-cb4dbf09-547e-4a32-8be2-d1560d335f69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405760694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.405760694
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2043730323
Short name T63
Test name
Test status
Simulation time 496678779745 ps
CPU time 814.81 seconds
Started Aug 16 06:27:45 PM PDT 24
Finished Aug 16 06:41:20 PM PDT 24
Peak memory 191728 kb
Host smart-91cec917-4bce-48e3-87ab-7beea8762a47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043730323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2043730323
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3071477338
Short name T331
Test name
Test status
Simulation time 31609298267 ps
CPU time 299.44 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:32:53 PM PDT 24
Peak memory 191780 kb
Host smart-8d222d5d-f6e1-4eac-b992-65ac33deb8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071477338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3071477338
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.22749421
Short name T256
Test name
Test status
Simulation time 122876967038 ps
CPU time 118.07 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:29:51 PM PDT 24
Peak memory 191784 kb
Host smart-97144b23-0d24-495b-a6ef-7863ded2ae3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22749421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.22749421
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_random.412564060
Short name T206
Test name
Test status
Simulation time 92440894027 ps
CPU time 506.21 seconds
Started Aug 16 06:27:24 PM PDT 24
Finished Aug 16 06:35:50 PM PDT 24
Peak memory 191788 kb
Host smart-3e672de1-577b-4e89-9786-4ec98933c3b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412564060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.412564060
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3930386490
Short name T225
Test name
Test status
Simulation time 12400064808 ps
CPU time 21.52 seconds
Started Aug 16 06:28:05 PM PDT 24
Finished Aug 16 06:28:29 PM PDT 24
Peak memory 183520 kb
Host smart-5340adbb-cd85-4600-83df-9dd64bebe914
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930386490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3930386490
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2673113005
Short name T95
Test name
Test status
Simulation time 93660521 ps
CPU time 0.75 seconds
Started Aug 16 05:32:07 PM PDT 24
Finished Aug 16 05:32:08 PM PDT 24
Peak memory 193196 kb
Host smart-0a31a772-a2e4-4806-a8ff-06b75b317fdd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673113005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2673113005
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1081170136
Short name T488
Test name
Test status
Simulation time 88550530 ps
CPU time 3.21 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:11 PM PDT 24
Peak memory 194676 kb
Host smart-2d78e49c-ec9d-463a-8c28-03f06f6038ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081170136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1081170136
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4144194503
Short name T538
Test name
Test status
Simulation time 19055190 ps
CPU time 0.62 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:10 PM PDT 24
Peak memory 183384 kb
Host smart-27f8475f-16b6-40da-8944-1e276cbe398b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144194503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.4144194503
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1418291515
Short name T464
Test name
Test status
Simulation time 477527150 ps
CPU time 0.99 seconds
Started Aug 16 05:32:14 PM PDT 24
Finished Aug 16 05:32:15 PM PDT 24
Peak memory 197768 kb
Host smart-a103c6f7-5d09-49b6-b00b-3bc6cfd4b075
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418291515 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1418291515
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1311587123
Short name T82
Test name
Test status
Simulation time 34907612 ps
CPU time 0.62 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:09 PM PDT 24
Peak memory 183308 kb
Host smart-c42fa58c-5ec1-488c-932b-b2abcad00679
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311587123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1311587123
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3884780904
Short name T491
Test name
Test status
Simulation time 51501628 ps
CPU time 0.59 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:09 PM PDT 24
Peak memory 183220 kb
Host smart-e8e3a882-1d97-4991-9a8d-131c5a82e568
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884780904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3884780904
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1995126106
Short name T527
Test name
Test status
Simulation time 34544177 ps
CPU time 0.83 seconds
Started Aug 16 05:32:07 PM PDT 24
Finished Aug 16 05:32:08 PM PDT 24
Peak memory 193880 kb
Host smart-46443040-c996-4296-b54b-fd639c8c5b96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995126106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1995126106
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3304375861
Short name T526
Test name
Test status
Simulation time 938549813 ps
CPU time 2.96 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:12 PM PDT 24
Peak memory 198112 kb
Host smart-b9c48af4-dd3f-4192-a3e3-73e4f21976b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304375861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3304375861
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3059519721
Short name T97
Test name
Test status
Simulation time 102355673 ps
CPU time 1.32 seconds
Started Aug 16 05:32:10 PM PDT 24
Finished Aug 16 05:32:11 PM PDT 24
Peak memory 184060 kb
Host smart-38a8e20b-f0c0-4ee2-9503-95136220b717
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059519721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3059519721
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3067504066
Short name T499
Test name
Test status
Simulation time 39647428 ps
CPU time 0.63 seconds
Started Aug 16 05:32:10 PM PDT 24
Finished Aug 16 05:32:10 PM PDT 24
Peak memory 183360 kb
Host smart-afa9ba9c-b1f2-4bda-97c8-fa812051623c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067504066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3067504066
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.761872117
Short name T563
Test name
Test status
Simulation time 149972215 ps
CPU time 1.68 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:11 PM PDT 24
Peak memory 193904 kb
Host smart-70728c8f-d727-49e2-9323-8d6f85ac6b0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761872117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.761872117
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3034357225
Short name T84
Test name
Test status
Simulation time 25612347 ps
CPU time 0.56 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:10 PM PDT 24
Peak memory 183364 kb
Host smart-307e5cf0-e505-4b22-95f7-be45896def38
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034357225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3034357225
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.85687458
Short name T569
Test name
Test status
Simulation time 33314957 ps
CPU time 0.99 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:11 PM PDT 24
Peak memory 197508 kb
Host smart-95554924-b3db-4f5a-8af6-f7cfce1bddd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85687458 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.85687458
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3385929687
Short name T481
Test name
Test status
Simulation time 14688130 ps
CPU time 0.59 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:09 PM PDT 24
Peak memory 183292 kb
Host smart-58b0c389-9ad7-4903-babc-bb7859be03ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385929687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3385929687
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3889073317
Short name T479
Test name
Test status
Simulation time 463409440 ps
CPU time 2.53 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:11 PM PDT 24
Peak memory 198132 kb
Host smart-bfdbbf7c-9348-46f8-bacc-e050af92256f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889073317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3889073317
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1936519944
Short name T497
Test name
Test status
Simulation time 331327745 ps
CPU time 1.31 seconds
Started Aug 16 05:32:07 PM PDT 24
Finished Aug 16 05:32:08 PM PDT 24
Peak memory 196056 kb
Host smart-99bcb106-9800-432b-a87e-b3ea79a08185
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936519944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1936519944
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1037457070
Short name T554
Test name
Test status
Simulation time 59012793 ps
CPU time 0.87 seconds
Started Aug 16 05:32:13 PM PDT 24
Finished Aug 16 05:32:14 PM PDT 24
Peak memory 197692 kb
Host smart-60d4ce15-64d0-4668-8ef7-0e580336794d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037457070 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1037457070
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1660092378
Short name T547
Test name
Test status
Simulation time 17133966 ps
CPU time 0.61 seconds
Started Aug 16 05:32:14 PM PDT 24
Finished Aug 16 05:32:15 PM PDT 24
Peak memory 183336 kb
Host smart-95029521-a647-43e5-9a21-d9b7edf8a228
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660092378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1660092378
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1040511866
Short name T561
Test name
Test status
Simulation time 16556299 ps
CPU time 0.59 seconds
Started Aug 16 05:32:13 PM PDT 24
Finished Aug 16 05:32:13 PM PDT 24
Peak memory 183192 kb
Host smart-902150bd-337c-4acf-b5ff-5eec472b0410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040511866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1040511866
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1132750354
Short name T571
Test name
Test status
Simulation time 57959594 ps
CPU time 0.74 seconds
Started Aug 16 05:32:19 PM PDT 24
Finished Aug 16 05:32:20 PM PDT 24
Peak memory 192880 kb
Host smart-bb388638-797d-44e4-bae7-0216a19ea7c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132750354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1132750354
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.4208866805
Short name T528
Test name
Test status
Simulation time 173717534 ps
CPU time 0.78 seconds
Started Aug 16 05:32:15 PM PDT 24
Finished Aug 16 05:32:15 PM PDT 24
Peak memory 183760 kb
Host smart-7ff18cb8-f965-48f2-a5c1-db9291cf6402
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208866805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.4208866805
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3278153067
Short name T544
Test name
Test status
Simulation time 58057577 ps
CPU time 0.88 seconds
Started Aug 16 05:32:14 PM PDT 24
Finished Aug 16 05:32:15 PM PDT 24
Peak memory 196872 kb
Host smart-8ed1d6e2-a290-48d9-8f08-a1aa5a779030
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278153067 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3278153067
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.166192273
Short name T560
Test name
Test status
Simulation time 15348951 ps
CPU time 0.58 seconds
Started Aug 16 05:32:14 PM PDT 24
Finished Aug 16 05:32:14 PM PDT 24
Peak memory 183360 kb
Host smart-49b4d207-2161-4fb4-9fa1-1b9247e9c3b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166192273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.166192273
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.82352401
Short name T506
Test name
Test status
Simulation time 253888597 ps
CPU time 0.59 seconds
Started Aug 16 05:32:14 PM PDT 24
Finished Aug 16 05:32:15 PM PDT 24
Peak memory 183224 kb
Host smart-ae4610f0-e21c-4889-a103-c9f78f6541d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82352401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.82352401
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.971963073
Short name T90
Test name
Test status
Simulation time 81519466 ps
CPU time 0.87 seconds
Started Aug 16 05:32:15 PM PDT 24
Finished Aug 16 05:32:16 PM PDT 24
Peak memory 194020 kb
Host smart-429a000e-c88f-4935-b8ce-174e128a8975
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971963073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.971963073
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3164168605
Short name T484
Test name
Test status
Simulation time 160056182 ps
CPU time 2.55 seconds
Started Aug 16 05:32:17 PM PDT 24
Finished Aug 16 05:32:20 PM PDT 24
Peak memory 198136 kb
Host smart-406e647c-aadc-4697-a3d8-e8244d958045
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164168605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3164168605
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3935349754
Short name T480
Test name
Test status
Simulation time 216589291 ps
CPU time 1.41 seconds
Started Aug 16 05:32:18 PM PDT 24
Finished Aug 16 05:32:19 PM PDT 24
Peak memory 183760 kb
Host smart-ea751359-8c9e-40a4-b933-ba21d615ebef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935349754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3935349754
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1263837007
Short name T545
Test name
Test status
Simulation time 62332116 ps
CPU time 0.8 seconds
Started Aug 16 05:32:15 PM PDT 24
Finished Aug 16 05:32:16 PM PDT 24
Peak memory 196272 kb
Host smart-b4010bc9-2170-4961-94d6-a33a0f463237
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263837007 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1263837007
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1357528070
Short name T83
Test name
Test status
Simulation time 159137432 ps
CPU time 0.55 seconds
Started Aug 16 05:32:12 PM PDT 24
Finished Aug 16 05:32:13 PM PDT 24
Peak memory 183300 kb
Host smart-1170eb87-1d80-45fd-8d25-5f2bd0b70d7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357528070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1357528070
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.890549183
Short name T455
Test name
Test status
Simulation time 15377313 ps
CPU time 0.55 seconds
Started Aug 16 05:32:17 PM PDT 24
Finished Aug 16 05:32:17 PM PDT 24
Peak memory 182724 kb
Host smart-4dc83fa5-a5e5-4f21-ba7d-e9c6c6670f8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890549183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.890549183
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1494223997
Short name T77
Test name
Test status
Simulation time 63125366 ps
CPU time 0.75 seconds
Started Aug 16 05:32:15 PM PDT 24
Finished Aug 16 05:32:16 PM PDT 24
Peak memory 193356 kb
Host smart-bd3e0a8f-2d9e-4ed9-969c-ea4a1b6e5e37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494223997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1494223997
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1671318232
Short name T494
Test name
Test status
Simulation time 737030142 ps
CPU time 2.55 seconds
Started Aug 16 05:32:14 PM PDT 24
Finished Aug 16 05:32:17 PM PDT 24
Peak memory 198092 kb
Host smart-ccbd7bde-ea30-4162-8510-3dde25536905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671318232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1671318232
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3075046225
Short name T462
Test name
Test status
Simulation time 42484683 ps
CPU time 0.85 seconds
Started Aug 16 05:32:13 PM PDT 24
Finished Aug 16 05:32:14 PM PDT 24
Peak memory 194476 kb
Host smart-166ba0aa-6ede-4fee-a1a7-256e975d2f29
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075046225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3075046225
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.34180288
Short name T517
Test name
Test status
Simulation time 49192725 ps
CPU time 0.85 seconds
Started Aug 16 05:32:23 PM PDT 24
Finished Aug 16 05:32:24 PM PDT 24
Peak memory 197336 kb
Host smart-bf2674e1-21c5-46aa-b236-cd8e517e1007
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34180288 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.34180288
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2493352954
Short name T490
Test name
Test status
Simulation time 15784836 ps
CPU time 0.58 seconds
Started Aug 16 05:32:18 PM PDT 24
Finished Aug 16 05:32:19 PM PDT 24
Peak memory 183348 kb
Host smart-34312856-0919-4103-b548-213f79ca19e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493352954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2493352954
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3998693363
Short name T460
Test name
Test status
Simulation time 17831767 ps
CPU time 0.58 seconds
Started Aug 16 05:32:21 PM PDT 24
Finished Aug 16 05:32:22 PM PDT 24
Peak memory 183280 kb
Host smart-7ed7aaf7-154c-4c6f-9bb5-2748faddebf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998693363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3998693363
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4031464498
Short name T550
Test name
Test status
Simulation time 29083716 ps
CPU time 0.58 seconds
Started Aug 16 05:32:21 PM PDT 24
Finished Aug 16 05:32:22 PM PDT 24
Peak memory 191904 kb
Host smart-fa2acd25-5140-495f-8781-550714d7af11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031464498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.4031464498
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.4191302202
Short name T525
Test name
Test status
Simulation time 124238261 ps
CPU time 2.38 seconds
Started Aug 16 05:32:14 PM PDT 24
Finished Aug 16 05:32:16 PM PDT 24
Peak memory 198080 kb
Host smart-2f0dee78-d870-4fd3-8b70-7616ead5efaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191302202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.4191302202
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.283697868
Short name T461
Test name
Test status
Simulation time 389792764 ps
CPU time 1.41 seconds
Started Aug 16 05:32:16 PM PDT 24
Finished Aug 16 05:32:18 PM PDT 24
Peak memory 183848 kb
Host smart-4c9918d0-5856-4baf-9154-70502cab840c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283697868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.283697868
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3854972494
Short name T498
Test name
Test status
Simulation time 31943339 ps
CPU time 0.85 seconds
Started Aug 16 05:32:23 PM PDT 24
Finished Aug 16 05:32:24 PM PDT 24
Peak memory 197292 kb
Host smart-140e309c-460c-4ea0-b250-4fd0ffa43bd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854972494 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3854972494
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.484193248
Short name T86
Test name
Test status
Simulation time 18335820 ps
CPU time 0.61 seconds
Started Aug 16 05:32:20 PM PDT 24
Finished Aug 16 05:32:20 PM PDT 24
Peak memory 183296 kb
Host smart-cc685664-cfe1-4c22-b417-1b2badec2c3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484193248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.484193248
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2889301536
Short name T570
Test name
Test status
Simulation time 11947435 ps
CPU time 0.54 seconds
Started Aug 16 05:32:22 PM PDT 24
Finished Aug 16 05:32:23 PM PDT 24
Peak memory 182644 kb
Host smart-01a763fa-398a-43b2-b529-52fefca207d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889301536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2889301536
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4212537033
Short name T91
Test name
Test status
Simulation time 31828779 ps
CPU time 0.71 seconds
Started Aug 16 05:32:23 PM PDT 24
Finished Aug 16 05:32:24 PM PDT 24
Peak memory 192348 kb
Host smart-1397ae39-cd82-481e-927e-b4db0cd8ecf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212537033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.4212537033
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3480746969
Short name T558
Test name
Test status
Simulation time 151723911 ps
CPU time 2.2 seconds
Started Aug 16 05:32:20 PM PDT 24
Finished Aug 16 05:32:23 PM PDT 24
Peak memory 198140 kb
Host smart-5143de22-4e97-441e-85fc-f6d771f06d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480746969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3480746969
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1326166933
Short name T541
Test name
Test status
Simulation time 229116646 ps
CPU time 1.37 seconds
Started Aug 16 05:32:21 PM PDT 24
Finished Aug 16 05:32:22 PM PDT 24
Peak memory 195932 kb
Host smart-9cefda0c-d2e0-4f23-ba12-450e6b30094e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326166933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1326166933
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1309048484
Short name T520
Test name
Test status
Simulation time 50030708 ps
CPU time 0.68 seconds
Started Aug 16 05:32:22 PM PDT 24
Finished Aug 16 05:32:23 PM PDT 24
Peak memory 194936 kb
Host smart-0b3d641d-a83d-4408-8f8c-b3f22dc3005b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309048484 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1309048484
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.759548407
Short name T503
Test name
Test status
Simulation time 15092668 ps
CPU time 0.56 seconds
Started Aug 16 05:32:19 PM PDT 24
Finished Aug 16 05:32:20 PM PDT 24
Peak memory 183296 kb
Host smart-e81b90e3-f0e4-4e66-9e06-648e23c9e8fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759548407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.759548407
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3943051153
Short name T572
Test name
Test status
Simulation time 15054176 ps
CPU time 0.56 seconds
Started Aug 16 05:32:18 PM PDT 24
Finished Aug 16 05:32:19 PM PDT 24
Peak memory 182696 kb
Host smart-933e5d28-1777-4544-8d9d-0b0510717be9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943051153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3943051153
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.527275727
Short name T513
Test name
Test status
Simulation time 49616768 ps
CPU time 0.89 seconds
Started Aug 16 05:32:22 PM PDT 24
Finished Aug 16 05:32:23 PM PDT 24
Peak memory 191544 kb
Host smart-52466e91-6596-4ec5-98c8-ccbf50ab2a71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527275727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.527275727
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3684076510
Short name T566
Test name
Test status
Simulation time 206636838 ps
CPU time 1.61 seconds
Started Aug 16 05:32:21 PM PDT 24
Finished Aug 16 05:32:22 PM PDT 24
Peak memory 198100 kb
Host smart-5413bb57-ad87-4594-bb39-1416bf272405
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684076510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3684076510
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1910624225
Short name T567
Test name
Test status
Simulation time 89050421 ps
CPU time 1.06 seconds
Started Aug 16 05:32:19 PM PDT 24
Finished Aug 16 05:32:20 PM PDT 24
Peak memory 195596 kb
Host smart-dbd9b3e2-5d5a-46ca-8531-ec95ca7174da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910624225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1910624225
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.569064942
Short name T511
Test name
Test status
Simulation time 95214566 ps
CPU time 1.09 seconds
Started Aug 16 05:32:26 PM PDT 24
Finished Aug 16 05:32:27 PM PDT 24
Peak memory 198072 kb
Host smart-2f710dd2-04b2-471c-a955-1d6cff5f89d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569064942 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.569064942
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.374984429
Short name T80
Test name
Test status
Simulation time 48145405 ps
CPU time 0.58 seconds
Started Aug 16 05:32:25 PM PDT 24
Finished Aug 16 05:32:25 PM PDT 24
Peak memory 183364 kb
Host smart-bc1e719e-0aff-4e5d-b4f4-7c1028c22e53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374984429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.374984429
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1213972064
Short name T469
Test name
Test status
Simulation time 48681273 ps
CPU time 0.56 seconds
Started Aug 16 05:33:01 PM PDT 24
Finished Aug 16 05:33:01 PM PDT 24
Peak memory 182936 kb
Host smart-bc9a167f-2b64-4f61-a9dd-d4505f7f783e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213972064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1213972064
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1472352029
Short name T568
Test name
Test status
Simulation time 63310526 ps
CPU time 0.81 seconds
Started Aug 16 05:32:23 PM PDT 24
Finished Aug 16 05:32:24 PM PDT 24
Peak memory 194020 kb
Host smart-729a7d0e-c90b-48c6-a5c5-7228be3f4b5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472352029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1472352029
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3544344708
Short name T47
Test name
Test status
Simulation time 625880746 ps
CPU time 2.78 seconds
Started Aug 16 05:32:27 PM PDT 24
Finished Aug 16 05:32:30 PM PDT 24
Peak memory 198212 kb
Host smart-2fcd97cc-69b7-4f87-bacd-0ed009b11674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544344708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3544344708
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2816167822
Short name T531
Test name
Test status
Simulation time 183156335 ps
CPU time 0.9 seconds
Started Aug 16 05:32:24 PM PDT 24
Finished Aug 16 05:32:25 PM PDT 24
Peak memory 194200 kb
Host smart-b68e65c4-7438-4c6a-ac4d-4813eb5356c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816167822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2816167822
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1305012301
Short name T536
Test name
Test status
Simulation time 32782844 ps
CPU time 0.86 seconds
Started Aug 16 05:32:27 PM PDT 24
Finished Aug 16 05:32:28 PM PDT 24
Peak memory 196284 kb
Host smart-86fee8ca-2081-4279-b80f-60e93159357e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305012301 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1305012301
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.96834727
Short name T85
Test name
Test status
Simulation time 11577374 ps
CPU time 0.55 seconds
Started Aug 16 05:32:26 PM PDT 24
Finished Aug 16 05:32:27 PM PDT 24
Peak memory 183292 kb
Host smart-ec487c27-952a-4348-a389-141f24bb4ea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96834727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.96834727
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1019407773
Short name T496
Test name
Test status
Simulation time 12917955 ps
CPU time 0.55 seconds
Started Aug 16 05:32:21 PM PDT 24
Finished Aug 16 05:32:22 PM PDT 24
Peak memory 183224 kb
Host smart-13c3aa14-22b3-47b7-81a0-9fa0d28a30eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019407773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1019407773
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3415384617
Short name T93
Test name
Test status
Simulation time 26495505 ps
CPU time 0.69 seconds
Started Aug 16 05:32:23 PM PDT 24
Finished Aug 16 05:32:24 PM PDT 24
Peak memory 192312 kb
Host smart-b28fa35f-9499-4feb-a540-58fad2586197
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415384617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3415384617
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.200797800
Short name T552
Test name
Test status
Simulation time 120325444 ps
CPU time 1.72 seconds
Started Aug 16 05:32:23 PM PDT 24
Finished Aug 16 05:32:25 PM PDT 24
Peak memory 198120 kb
Host smart-46654fa1-9a77-4923-909f-016c199d379f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200797800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.200797800
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.603472823
Short name T99
Test name
Test status
Simulation time 169762412 ps
CPU time 1.11 seconds
Started Aug 16 05:32:23 PM PDT 24
Finished Aug 16 05:32:25 PM PDT 24
Peak memory 183780 kb
Host smart-f82e60ee-ecea-4e1c-9ab4-ea0a37b85f30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603472823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.603472823
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2742835678
Short name T580
Test name
Test status
Simulation time 19227579 ps
CPU time 0.7 seconds
Started Aug 16 05:32:28 PM PDT 24
Finished Aug 16 05:32:29 PM PDT 24
Peak memory 194900 kb
Host smart-c0c38cf2-7fa4-4106-b32b-e565cfb1b3ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742835678 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2742835678
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2818846071
Short name T96
Test name
Test status
Simulation time 16439582 ps
CPU time 0.61 seconds
Started Aug 16 05:32:20 PM PDT 24
Finished Aug 16 05:32:21 PM PDT 24
Peak memory 192556 kb
Host smart-f0840dcd-45eb-4d91-84f2-4886ea1fb734
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818846071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2818846071
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1344910635
Short name T459
Test name
Test status
Simulation time 17135380 ps
CPU time 0.61 seconds
Started Aug 16 05:32:22 PM PDT 24
Finished Aug 16 05:32:23 PM PDT 24
Peak memory 183212 kb
Host smart-9d151247-963e-46ec-a252-ef22df40be37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344910635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1344910635
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3015170063
Short name T575
Test name
Test status
Simulation time 46540861 ps
CPU time 0.69 seconds
Started Aug 16 05:32:27 PM PDT 24
Finished Aug 16 05:32:27 PM PDT 24
Peak memory 192288 kb
Host smart-ec8f902a-99d6-4246-9178-a7fb12daff87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015170063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3015170063
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3454159838
Short name T534
Test name
Test status
Simulation time 193352954 ps
CPU time 3 seconds
Started Aug 16 05:32:21 PM PDT 24
Finished Aug 16 05:32:24 PM PDT 24
Peak memory 198104 kb
Host smart-96f7c6ed-4bf9-42b8-9a87-fb26a3d465f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454159838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3454159838
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3689416219
Short name T98
Test name
Test status
Simulation time 125594611 ps
CPU time 1.4 seconds
Started Aug 16 05:32:21 PM PDT 24
Finished Aug 16 05:32:23 PM PDT 24
Peak memory 196052 kb
Host smart-ac44c75c-2195-47ab-87ff-2ad27fc0e26b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689416219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3689416219
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2987003641
Short name T504
Test name
Test status
Simulation time 62380975 ps
CPU time 0.97 seconds
Started Aug 16 05:32:21 PM PDT 24
Finished Aug 16 05:32:22 PM PDT 24
Peak memory 197884 kb
Host smart-608bf527-dac0-4b93-aafc-0299061d4028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987003641 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2987003641
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3899288809
Short name T574
Test name
Test status
Simulation time 12257189 ps
CPU time 0.58 seconds
Started Aug 16 05:32:23 PM PDT 24
Finished Aug 16 05:32:24 PM PDT 24
Peak memory 183376 kb
Host smart-e3b558c5-e6ae-4d2c-8703-afd33b285e87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899288809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3899288809
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.865461935
Short name T579
Test name
Test status
Simulation time 22531734 ps
CPU time 0.55 seconds
Started Aug 16 05:32:20 PM PDT 24
Finished Aug 16 05:32:21 PM PDT 24
Peak memory 183208 kb
Host smart-c5a3f1e4-3a2f-4b2f-a6b1-84c8f95d294d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865461935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.865461935
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1315029766
Short name T540
Test name
Test status
Simulation time 16602953 ps
CPU time 0.68 seconds
Started Aug 16 05:32:19 PM PDT 24
Finished Aug 16 05:32:20 PM PDT 24
Peak memory 192892 kb
Host smart-91959e03-d02b-4fdf-8e5c-c2bad78ed879
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315029766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1315029766
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3828555798
Short name T471
Test name
Test status
Simulation time 82276281 ps
CPU time 1.02 seconds
Started Aug 16 05:32:23 PM PDT 24
Finished Aug 16 05:32:24 PM PDT 24
Peak memory 197468 kb
Host smart-e461e0ff-b41d-46c9-9b9b-dc7dce10b3ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828555798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3828555798
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3126694305
Short name T535
Test name
Test status
Simulation time 168879858 ps
CPU time 0.82 seconds
Started Aug 16 05:32:20 PM PDT 24
Finished Aug 16 05:32:21 PM PDT 24
Peak memory 194408 kb
Host smart-4909c966-48a1-4901-8f61-9a50026dc862
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126694305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.3126694305
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3132973383
Short name T81
Test name
Test status
Simulation time 17202388 ps
CPU time 0.82 seconds
Started Aug 16 05:32:07 PM PDT 24
Finished Aug 16 05:32:08 PM PDT 24
Peak memory 183284 kb
Host smart-9225de5e-28d5-4bd8-b502-adf00364d016
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132973383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3132973383
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1457805933
Short name T576
Test name
Test status
Simulation time 749462155 ps
CPU time 2.54 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:12 PM PDT 24
Peak memory 191736 kb
Host smart-9e37d8c2-8135-4d0a-b142-f87fe803774c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457805933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1457805933
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2999219420
Short name T50
Test name
Test status
Simulation time 15887663 ps
CPU time 0.57 seconds
Started Aug 16 05:32:07 PM PDT 24
Finished Aug 16 05:32:08 PM PDT 24
Peak memory 183360 kb
Host smart-8098f13b-f5ff-4d7a-8dca-8b611560cbe7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999219420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2999219420
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3968344250
Short name T468
Test name
Test status
Simulation time 55824274 ps
CPU time 1.24 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:10 PM PDT 24
Peak memory 198268 kb
Host smart-25509793-b82d-43be-ab44-d19935de5045
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968344250 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3968344250
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1474333933
Short name T474
Test name
Test status
Simulation time 10531106 ps
CPU time 0.54 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:09 PM PDT 24
Peak memory 182988 kb
Host smart-41cd7b49-2255-403b-be51-2551a08a0a6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474333933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1474333933
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.311192291
Short name T470
Test name
Test status
Simulation time 50266833 ps
CPU time 0.59 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:10 PM PDT 24
Peak memory 183184 kb
Host smart-f3fd5d82-4053-41d7-b2c4-41ad988e3ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311192291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.311192291
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3208951051
Short name T89
Test name
Test status
Simulation time 113651436 ps
CPU time 0.68 seconds
Started Aug 16 05:32:06 PM PDT 24
Finished Aug 16 05:32:07 PM PDT 24
Peak memory 192188 kb
Host smart-f7132f6c-d9a8-4f57-868e-1cfbf9e435eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208951051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3208951051
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.143584462
Short name T483
Test name
Test status
Simulation time 466559089 ps
CPU time 2.84 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:11 PM PDT 24
Peak memory 198036 kb
Host smart-e31c53eb-5e09-4859-8795-5019619d0f5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143584462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.143584462
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2820766365
Short name T502
Test name
Test status
Simulation time 12223575 ps
CPU time 0.53 seconds
Started Aug 16 05:32:23 PM PDT 24
Finished Aug 16 05:32:23 PM PDT 24
Peak memory 182632 kb
Host smart-aa862072-6187-4a88-8ca8-86826ff872bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820766365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2820766365
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.973837225
Short name T507
Test name
Test status
Simulation time 41840655 ps
CPU time 0.56 seconds
Started Aug 16 05:32:25 PM PDT 24
Finished Aug 16 05:32:25 PM PDT 24
Peak memory 182680 kb
Host smart-002a21f1-ef28-459e-9c3d-b586990ba166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973837225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.973837225
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.807513734
Short name T472
Test name
Test status
Simulation time 49907497 ps
CPU time 0.58 seconds
Started Aug 16 05:32:23 PM PDT 24
Finished Aug 16 05:32:24 PM PDT 24
Peak memory 183200 kb
Host smart-465a7a2d-ba39-4ac1-8ffe-dd52cdf31c0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807513734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.807513734
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.363263014
Short name T529
Test name
Test status
Simulation time 33734237 ps
CPU time 0.61 seconds
Started Aug 16 05:32:23 PM PDT 24
Finished Aug 16 05:32:24 PM PDT 24
Peak memory 183232 kb
Host smart-1b6aa76c-4ee1-4218-ad24-08ae99ac6df5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363263014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.363263014
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.954237180
Short name T463
Test name
Test status
Simulation time 20457270 ps
CPU time 0.58 seconds
Started Aug 16 05:32:27 PM PDT 24
Finished Aug 16 05:32:27 PM PDT 24
Peak memory 183208 kb
Host smart-d3167beb-2358-42e2-a330-d2fcb37ba342
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954237180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.954237180
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1520647517
Short name T581
Test name
Test status
Simulation time 12052760 ps
CPU time 0.65 seconds
Started Aug 16 05:32:26 PM PDT 24
Finished Aug 16 05:32:27 PM PDT 24
Peak memory 183196 kb
Host smart-ce4ba4ae-4fb3-43d9-8aaf-a606b40875c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520647517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1520647517
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2981344263
Short name T512
Test name
Test status
Simulation time 14855098 ps
CPU time 0.56 seconds
Started Aug 16 05:32:28 PM PDT 24
Finished Aug 16 05:32:29 PM PDT 24
Peak memory 183172 kb
Host smart-83f59c22-384c-4b91-82e0-0345034391c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981344263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2981344263
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3953540029
Short name T456
Test name
Test status
Simulation time 14509267 ps
CPU time 0.56 seconds
Started Aug 16 05:32:21 PM PDT 24
Finished Aug 16 05:32:22 PM PDT 24
Peak memory 183168 kb
Host smart-d0b1ace4-8f1b-4d2a-b7fd-3fa46c3c1cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953540029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3953540029
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.886805490
Short name T467
Test name
Test status
Simulation time 36838270 ps
CPU time 0.55 seconds
Started Aug 16 05:32:18 PM PDT 24
Finished Aug 16 05:32:19 PM PDT 24
Peak memory 183148 kb
Host smart-753b0294-7bf6-4ce4-bf66-a20d59f3dd42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886805490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.886805490
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2045094059
Short name T510
Test name
Test status
Simulation time 37491649 ps
CPU time 0.56 seconds
Started Aug 16 05:32:26 PM PDT 24
Finished Aug 16 05:32:27 PM PDT 24
Peak memory 183252 kb
Host smart-e324f23f-0d35-43b4-8050-b8ba9b03cf4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045094059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2045094059
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.486243709
Short name T475
Test name
Test status
Simulation time 94798993 ps
CPU time 0.72 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:09 PM PDT 24
Peak memory 193184 kb
Host smart-e1a12134-b32a-4972-86f8-6c8fd04f4cbf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486243709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.486243709
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2379084903
Short name T495
Test name
Test status
Simulation time 126935411 ps
CPU time 1.46 seconds
Started Aug 16 05:32:13 PM PDT 24
Finished Aug 16 05:32:15 PM PDT 24
Peak memory 191656 kb
Host smart-27b76d2e-237e-497c-945a-9176262370f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379084903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2379084903
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1145688446
Short name T60
Test name
Test status
Simulation time 13490713 ps
CPU time 0.6 seconds
Started Aug 16 05:32:11 PM PDT 24
Finished Aug 16 05:32:12 PM PDT 24
Peak memory 182456 kb
Host smart-cde625be-fdfc-4026-96a2-f51f19f38ade
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145688446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1145688446
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.153100297
Short name T508
Test name
Test status
Simulation time 184730997 ps
CPU time 0.97 seconds
Started Aug 16 05:32:12 PM PDT 24
Finished Aug 16 05:32:13 PM PDT 24
Peak memory 197656 kb
Host smart-fb92a05d-a807-41a2-bbf3-91a20821fe05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153100297 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.153100297
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.68543454
Short name T87
Test name
Test status
Simulation time 12532994 ps
CPU time 0.56 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:09 PM PDT 24
Peak memory 183380 kb
Host smart-a91641a9-f51b-443f-ad85-72cf469ce08e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68543454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.68543454
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3817840
Short name T505
Test name
Test status
Simulation time 32662480 ps
CPU time 0.52 seconds
Started Aug 16 05:32:10 PM PDT 24
Finished Aug 16 05:32:11 PM PDT 24
Peak memory 183316 kb
Host smart-bb369990-2f4a-4db8-8d9c-048a843ca2b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3817840
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1002290081
Short name T74
Test name
Test status
Simulation time 36329704 ps
CPU time 0.62 seconds
Started Aug 16 05:32:11 PM PDT 24
Finished Aug 16 05:32:12 PM PDT 24
Peak memory 192240 kb
Host smart-a0c1d0e1-2c30-4f4f-a11b-941ba01f726f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002290081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1002290081
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3798227028
Short name T465
Test name
Test status
Simulation time 179502501 ps
CPU time 2.29 seconds
Started Aug 16 05:32:11 PM PDT 24
Finished Aug 16 05:32:14 PM PDT 24
Peak memory 198056 kb
Host smart-a05a0c58-c5ac-41d5-b33f-a023da61ee19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798227028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3798227028
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1958304423
Short name T26
Test name
Test status
Simulation time 93277917 ps
CPU time 0.89 seconds
Started Aug 16 05:32:10 PM PDT 24
Finished Aug 16 05:32:11 PM PDT 24
Peak memory 194096 kb
Host smart-8969a5ee-707a-4c0e-8f38-8c4aaa3292cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958304423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1958304423
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1121417054
Short name T556
Test name
Test status
Simulation time 51364108 ps
CPU time 0.6 seconds
Started Aug 16 05:32:25 PM PDT 24
Finished Aug 16 05:32:25 PM PDT 24
Peak memory 183184 kb
Host smart-4f4363b1-6e82-4550-a751-52c16741c2c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121417054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1121417054
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1048432994
Short name T543
Test name
Test status
Simulation time 14182543 ps
CPU time 0.54 seconds
Started Aug 16 05:32:24 PM PDT 24
Finished Aug 16 05:32:25 PM PDT 24
Peak memory 182900 kb
Host smart-9edfbc35-1d43-4012-8ad4-483b82859244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048432994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1048432994
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1980353226
Short name T537
Test name
Test status
Simulation time 14400550 ps
CPU time 0.57 seconds
Started Aug 16 05:32:22 PM PDT 24
Finished Aug 16 05:32:23 PM PDT 24
Peak memory 182652 kb
Host smart-0e1983ac-aab6-4d6f-8234-89cc9c3d4b09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980353226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1980353226
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3933817504
Short name T501
Test name
Test status
Simulation time 48634896 ps
CPU time 0.55 seconds
Started Aug 16 05:32:28 PM PDT 24
Finished Aug 16 05:32:29 PM PDT 24
Peak memory 183152 kb
Host smart-7eed26d0-68a1-4fe6-9d12-fa14671f7b4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933817504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3933817504
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2226145530
Short name T562
Test name
Test status
Simulation time 30372089 ps
CPU time 0.55 seconds
Started Aug 16 05:32:26 PM PDT 24
Finished Aug 16 05:32:27 PM PDT 24
Peak memory 182780 kb
Host smart-38eec805-7d11-41db-b542-589eb5c34ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226145530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2226145530
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2436123571
Short name T509
Test name
Test status
Simulation time 22872352 ps
CPU time 0.57 seconds
Started Aug 16 05:32:26 PM PDT 24
Finished Aug 16 05:32:27 PM PDT 24
Peak memory 183160 kb
Host smart-f6cd3162-7bcd-480f-9a74-0c224f521a82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436123571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2436123571
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3392117498
Short name T457
Test name
Test status
Simulation time 42334591 ps
CPU time 0.55 seconds
Started Aug 16 05:32:26 PM PDT 24
Finished Aug 16 05:32:27 PM PDT 24
Peak memory 182872 kb
Host smart-f1714287-c79d-4a93-b685-289c58279f12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392117498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3392117498
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2750233682
Short name T473
Test name
Test status
Simulation time 13309140 ps
CPU time 0.55 seconds
Started Aug 16 05:32:20 PM PDT 24
Finished Aug 16 05:32:21 PM PDT 24
Peak memory 183120 kb
Host smart-a624057f-86c0-45fe-aff8-35066035838e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750233682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2750233682
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.4083944320
Short name T454
Test name
Test status
Simulation time 19607739 ps
CPU time 0.58 seconds
Started Aug 16 05:32:29 PM PDT 24
Finished Aug 16 05:32:30 PM PDT 24
Peak memory 183168 kb
Host smart-a8c5a5ab-8732-4091-9a44-89ee50ae8549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083944320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.4083944320
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4096203907
Short name T466
Test name
Test status
Simulation time 14198168 ps
CPU time 0.56 seconds
Started Aug 16 05:32:26 PM PDT 24
Finished Aug 16 05:32:26 PM PDT 24
Peak memory 183252 kb
Host smart-961ef04d-fc22-44c7-835a-a914b6beaea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096203907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4096203907
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1109776127
Short name T75
Test name
Test status
Simulation time 15886761 ps
CPU time 0.65 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:10 PM PDT 24
Peak memory 192740 kb
Host smart-cb2e08b8-4010-44b8-9e53-751c34bbcc1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109776127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1109776127
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3072490383
Short name T94
Test name
Test status
Simulation time 530326468 ps
CPU time 3.64 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:12 PM PDT 24
Peak memory 183476 kb
Host smart-1c26291e-0501-4f58-9d88-2cf7994b6030
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072490383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3072490383
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1000760852
Short name T521
Test name
Test status
Simulation time 38518246 ps
CPU time 0.57 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:09 PM PDT 24
Peak memory 183372 kb
Host smart-1bffdf9a-e573-4e3a-8d15-d98391acb1aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000760852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1000760852
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3666943208
Short name T553
Test name
Test status
Simulation time 31868143 ps
CPU time 1.42 seconds
Started Aug 16 05:32:10 PM PDT 24
Finished Aug 16 05:32:11 PM PDT 24
Peak memory 198100 kb
Host smart-f3dbabdb-8d51-4e6d-84c1-60f130360577
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666943208 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3666943208
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.647011614
Short name T559
Test name
Test status
Simulation time 12142226 ps
CPU time 0.58 seconds
Started Aug 16 05:32:09 PM PDT 24
Finished Aug 16 05:32:10 PM PDT 24
Peak memory 182988 kb
Host smart-d5727aa6-f648-47ed-bc2f-c1b90df4bd11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647011614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.647011614
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1300767482
Short name T492
Test name
Test status
Simulation time 20290403 ps
CPU time 0.53 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:09 PM PDT 24
Peak memory 182664 kb
Host smart-660d644f-4be0-48b9-af8b-878f5c6c15fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300767482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1300767482
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.855885615
Short name T78
Test name
Test status
Simulation time 142865265 ps
CPU time 0.76 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:09 PM PDT 24
Peak memory 193660 kb
Host smart-c117feee-0e84-41af-be7a-c2bf10dac833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855885615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.855885615
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2644285881
Short name T453
Test name
Test status
Simulation time 140272530 ps
CPU time 2 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:10 PM PDT 24
Peak memory 198028 kb
Host smart-e09a225c-6932-4e0d-9384-48fe99e14ebd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644285881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2644285881
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1209493930
Short name T542
Test name
Test status
Simulation time 48533635 ps
CPU time 0.89 seconds
Started Aug 16 05:32:07 PM PDT 24
Finished Aug 16 05:32:08 PM PDT 24
Peak memory 194336 kb
Host smart-b6b96f35-6240-4dd9-a637-7aaba8f2301a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209493930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1209493930
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2971484836
Short name T477
Test name
Test status
Simulation time 16316188 ps
CPU time 0.54 seconds
Started Aug 16 05:32:23 PM PDT 24
Finished Aug 16 05:32:24 PM PDT 24
Peak memory 182884 kb
Host smart-a40ee2db-9bab-4c28-9811-8bf8eff1fc1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971484836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2971484836
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2581797564
Short name T565
Test name
Test status
Simulation time 46304720 ps
CPU time 0.56 seconds
Started Aug 16 05:32:26 PM PDT 24
Finished Aug 16 05:32:26 PM PDT 24
Peak memory 183244 kb
Host smart-0a3aefe6-4415-4829-9982-9f32d595dab1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581797564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2581797564
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1263209329
Short name T524
Test name
Test status
Simulation time 76151161 ps
CPU time 0.57 seconds
Started Aug 16 05:32:22 PM PDT 24
Finished Aug 16 05:32:23 PM PDT 24
Peak memory 182684 kb
Host smart-02b150c5-76df-4079-b75f-c067267cfb18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263209329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1263209329
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.4072371381
Short name T530
Test name
Test status
Simulation time 43150637 ps
CPU time 0.57 seconds
Started Aug 16 05:32:29 PM PDT 24
Finished Aug 16 05:32:30 PM PDT 24
Peak memory 183264 kb
Host smart-a96e1400-6961-4ead-bab5-2151519004f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072371381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.4072371381
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.1174843806
Short name T478
Test name
Test status
Simulation time 31234161 ps
CPU time 0.53 seconds
Started Aug 16 05:32:29 PM PDT 24
Finished Aug 16 05:32:29 PM PDT 24
Peak memory 182844 kb
Host smart-e65d11f4-a561-427e-bd02-4c85983831d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174843806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1174843806
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1672591526
Short name T485
Test name
Test status
Simulation time 15208058 ps
CPU time 0.54 seconds
Started Aug 16 05:32:31 PM PDT 24
Finished Aug 16 05:32:31 PM PDT 24
Peak memory 182648 kb
Host smart-1eb3aed2-5a87-46b1-aa95-c53b8c040b41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672591526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1672591526
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3127526614
Short name T523
Test name
Test status
Simulation time 41904524 ps
CPU time 0.57 seconds
Started Aug 16 05:32:35 PM PDT 24
Finished Aug 16 05:32:36 PM PDT 24
Peak memory 183160 kb
Host smart-6d9358b9-cebc-4fee-b15e-b6e10e83eec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127526614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3127526614
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.594167739
Short name T546
Test name
Test status
Simulation time 28842645 ps
CPU time 0.55 seconds
Started Aug 16 05:32:29 PM PDT 24
Finished Aug 16 05:32:30 PM PDT 24
Peak memory 182672 kb
Host smart-87dc621e-ad78-4561-92c7-666cf68aac04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594167739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.594167739
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1981554655
Short name T551
Test name
Test status
Simulation time 22391363 ps
CPU time 0.57 seconds
Started Aug 16 05:32:28 PM PDT 24
Finished Aug 16 05:32:29 PM PDT 24
Peak memory 182692 kb
Host smart-a8ca8635-63f9-40c3-89e5-f492a24cf070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981554655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1981554655
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3193929577
Short name T514
Test name
Test status
Simulation time 108457378 ps
CPU time 0.54 seconds
Started Aug 16 05:32:27 PM PDT 24
Finished Aug 16 05:32:28 PM PDT 24
Peak memory 182928 kb
Host smart-bcddd1d1-f416-487b-a34c-a8312b51aa6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193929577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3193929577
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.457617320
Short name T519
Test name
Test status
Simulation time 48072432 ps
CPU time 0.84 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:09 PM PDT 24
Peak memory 196536 kb
Host smart-089775a5-c0b8-4872-ad6c-0501b6343a91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457617320 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.457617320
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3077691250
Short name T489
Test name
Test status
Simulation time 17389537 ps
CPU time 0.61 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:09 PM PDT 24
Peak memory 183376 kb
Host smart-87429d79-174f-4e59-b61a-edfb9e62729e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077691250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3077691250
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3392816581
Short name T482
Test name
Test status
Simulation time 30621363 ps
CPU time 0.56 seconds
Started Aug 16 05:32:16 PM PDT 24
Finished Aug 16 05:32:17 PM PDT 24
Peak memory 183216 kb
Host smart-78e2b0ad-fac6-4b3b-a7e1-6cde4d64e93d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392816581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3392816581
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.243010105
Short name T516
Test name
Test status
Simulation time 231195191 ps
CPU time 0.61 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:08 PM PDT 24
Peak memory 192340 kb
Host smart-38ac94f8-39f0-471d-8967-38982120ef7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243010105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.243010105
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1894843216
Short name T487
Test name
Test status
Simulation time 203687078 ps
CPU time 2.7 seconds
Started Aug 16 05:32:08 PM PDT 24
Finished Aug 16 05:32:11 PM PDT 24
Peak memory 198116 kb
Host smart-eb68d0e0-deb0-4df7-bad1-2ab61375c616
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894843216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1894843216
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2050003846
Short name T493
Test name
Test status
Simulation time 65730259 ps
CPU time 1.12 seconds
Started Aug 16 05:32:07 PM PDT 24
Finished Aug 16 05:32:08 PM PDT 24
Peak memory 195976 kb
Host smart-8a3ec231-1608-45d9-adc8-cb6bc5529404
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050003846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2050003846
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.968264374
Short name T532
Test name
Test status
Simulation time 75853012 ps
CPU time 0.72 seconds
Started Aug 16 05:32:15 PM PDT 24
Finished Aug 16 05:32:16 PM PDT 24
Peak memory 195336 kb
Host smart-6e5a48cb-eef2-4500-b19f-a3a2cd0a17df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968264374 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.968264374
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1405290055
Short name T76
Test name
Test status
Simulation time 14067076 ps
CPU time 0.6 seconds
Started Aug 16 05:32:18 PM PDT 24
Finished Aug 16 05:32:19 PM PDT 24
Peak memory 183288 kb
Host smart-3f3df915-4a36-401e-8b3c-5d8560e51488
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405290055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1405290055
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3023017720
Short name T533
Test name
Test status
Simulation time 30253076 ps
CPU time 0.56 seconds
Started Aug 16 05:32:19 PM PDT 24
Finished Aug 16 05:32:19 PM PDT 24
Peak memory 183184 kb
Host smart-ddc6adf8-c6fb-44d1-9448-0e0765e9344f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023017720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3023017720
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2895287785
Short name T555
Test name
Test status
Simulation time 35780331 ps
CPU time 0.65 seconds
Started Aug 16 05:32:18 PM PDT 24
Finished Aug 16 05:32:19 PM PDT 24
Peak memory 192696 kb
Host smart-a3e3a215-7eff-4e04-b3e9-7d7ae9f021ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895287785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2895287785
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4032349448
Short name T522
Test name
Test status
Simulation time 36159919 ps
CPU time 0.92 seconds
Started Aug 16 05:32:16 PM PDT 24
Finished Aug 16 05:32:17 PM PDT 24
Peak memory 191728 kb
Host smart-09778f83-f1e0-4db3-9c75-8048e8a0a933
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032349448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.4032349448
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.869366452
Short name T458
Test name
Test status
Simulation time 51575427 ps
CPU time 0.92 seconds
Started Aug 16 05:32:14 PM PDT 24
Finished Aug 16 05:32:15 PM PDT 24
Peak memory 194440 kb
Host smart-52e76ffe-4a17-4ab9-bba0-d3f859ebd721
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869366452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.869366452
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3864993346
Short name T486
Test name
Test status
Simulation time 33820148 ps
CPU time 0.95 seconds
Started Aug 16 05:32:19 PM PDT 24
Finished Aug 16 05:32:20 PM PDT 24
Peak memory 197284 kb
Host smart-5d1092a2-a4ee-4dfd-ab97-56bd24ef9945
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864993346 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3864993346
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2584562898
Short name T88
Test name
Test status
Simulation time 52595850 ps
CPU time 0.58 seconds
Started Aug 16 05:32:16 PM PDT 24
Finished Aug 16 05:32:16 PM PDT 24
Peak memory 183324 kb
Host smart-073543f7-e438-4b4a-9c4e-137a6604a257
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584562898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2584562898
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.760012445
Short name T515
Test name
Test status
Simulation time 17840273 ps
CPU time 0.57 seconds
Started Aug 16 05:32:13 PM PDT 24
Finished Aug 16 05:32:14 PM PDT 24
Peak memory 183152 kb
Host smart-d45dcb90-2306-4008-a59e-ff01d96817ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760012445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.760012445
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3988581683
Short name T578
Test name
Test status
Simulation time 55592657 ps
CPU time 0.74 seconds
Started Aug 16 05:32:15 PM PDT 24
Finished Aug 16 05:32:15 PM PDT 24
Peak memory 192204 kb
Host smart-0855e94a-c209-40ad-a473-43b3c212f5f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988581683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3988581683
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3973254079
Short name T564
Test name
Test status
Simulation time 589373948 ps
CPU time 3.48 seconds
Started Aug 16 05:32:17 PM PDT 24
Finished Aug 16 05:32:21 PM PDT 24
Peak memory 198108 kb
Host smart-9c3bb23a-a6c3-4b70-b502-bb6fac10951a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973254079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3973254079
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1211760038
Short name T27
Test name
Test status
Simulation time 94568887 ps
CPU time 0.86 seconds
Started Aug 16 05:32:12 PM PDT 24
Finished Aug 16 05:32:13 PM PDT 24
Peak memory 194084 kb
Host smart-08b6b7b2-4718-43b4-bd17-60de1b8cfcae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211760038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1211760038
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1739528907
Short name T28
Test name
Test status
Simulation time 57563114 ps
CPU time 0.89 seconds
Started Aug 16 05:32:12 PM PDT 24
Finished Aug 16 05:32:13 PM PDT 24
Peak memory 197092 kb
Host smart-9fe0318f-6bf3-41d0-8804-28df823ed285
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739528907 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1739528907
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2290869876
Short name T557
Test name
Test status
Simulation time 16361625 ps
CPU time 0.58 seconds
Started Aug 16 05:32:15 PM PDT 24
Finished Aug 16 05:32:16 PM PDT 24
Peak memory 183336 kb
Host smart-1d8aa403-1135-4b56-8845-41cfd8ac8e25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290869876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2290869876
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3983154850
Short name T573
Test name
Test status
Simulation time 48000148 ps
CPU time 0.54 seconds
Started Aug 16 05:32:18 PM PDT 24
Finished Aug 16 05:32:19 PM PDT 24
Peak memory 182916 kb
Host smart-a78f4db5-3809-4b3a-be82-6beb8692d511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983154850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3983154850
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1563170669
Short name T500
Test name
Test status
Simulation time 31967038 ps
CPU time 0.74 seconds
Started Aug 16 05:32:14 PM PDT 24
Finished Aug 16 05:32:15 PM PDT 24
Peak memory 193636 kb
Host smart-6f5e7f80-1036-4f28-895f-73503698dcfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563170669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1563170669
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.512150974
Short name T539
Test name
Test status
Simulation time 155814515 ps
CPU time 2.08 seconds
Started Aug 16 05:32:14 PM PDT 24
Finished Aug 16 05:32:17 PM PDT 24
Peak memory 198164 kb
Host smart-d7c08175-3c3a-4b2c-887b-8513d74d5d70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512150974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.512150974
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1837538404
Short name T48
Test name
Test status
Simulation time 300749687 ps
CPU time 1.1 seconds
Started Aug 16 05:32:20 PM PDT 24
Finished Aug 16 05:32:21 PM PDT 24
Peak memory 195796 kb
Host smart-89723129-4fce-4e88-a799-038c017f8467
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837538404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1837538404
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3223584452
Short name T476
Test name
Test status
Simulation time 19959035 ps
CPU time 0.69 seconds
Started Aug 16 05:32:16 PM PDT 24
Finished Aug 16 05:32:16 PM PDT 24
Peak memory 193444 kb
Host smart-c0eadf7b-8220-41cc-8bfb-bb7067282893
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223584452 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3223584452
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.636596496
Short name T549
Test name
Test status
Simulation time 15346495 ps
CPU time 0.6 seconds
Started Aug 16 05:32:16 PM PDT 24
Finished Aug 16 05:32:16 PM PDT 24
Peak memory 183384 kb
Host smart-b6ba8139-e9b8-4f0c-9764-a003cc48838f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636596496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.636596496
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3448737217
Short name T518
Test name
Test status
Simulation time 21849087 ps
CPU time 0.55 seconds
Started Aug 16 05:32:15 PM PDT 24
Finished Aug 16 05:32:16 PM PDT 24
Peak memory 182816 kb
Host smart-8d0c37e0-99f8-44e8-b21e-05a0d94e8efc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448737217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3448737217
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1780850338
Short name T79
Test name
Test status
Simulation time 22440418 ps
CPU time 0.83 seconds
Started Aug 16 05:32:15 PM PDT 24
Finished Aug 16 05:32:16 PM PDT 24
Peak memory 194084 kb
Host smart-27b8ca8b-7ac9-4dcf-8fb2-a859ff42b940
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780850338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1780850338
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3292704483
Short name T548
Test name
Test status
Simulation time 41080899 ps
CPU time 1.98 seconds
Started Aug 16 05:32:17 PM PDT 24
Finished Aug 16 05:32:19 PM PDT 24
Peak memory 198140 kb
Host smart-5cfa8d18-c287-44b2-a164-0dc64c07b152
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292704483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3292704483
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2414492575
Short name T577
Test name
Test status
Simulation time 76451212 ps
CPU time 0.87 seconds
Started Aug 16 05:32:13 PM PDT 24
Finished Aug 16 05:32:14 PM PDT 24
Peak memory 193944 kb
Host smart-30782fc8-393d-434a-a0d7-2a8f9594b99c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414492575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2414492575
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.558684313
Short name T254
Test name
Test status
Simulation time 1389738332110 ps
CPU time 644.6 seconds
Started Aug 16 06:27:20 PM PDT 24
Finished Aug 16 06:38:05 PM PDT 24
Peak memory 183568 kb
Host smart-aacb9b36-aea6-4b1c-97f8-97c752ee0376
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558684313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.558684313
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.647296801
Short name T360
Test name
Test status
Simulation time 58883725528 ps
CPU time 87.57 seconds
Started Aug 16 06:27:12 PM PDT 24
Finished Aug 16 06:28:40 PM PDT 24
Peak memory 183596 kb
Host smart-61b441fd-acab-4d53-8e79-aa7b095bbbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647296801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.647296801
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.757861351
Short name T431
Test name
Test status
Simulation time 131961802308 ps
CPU time 82.9 seconds
Started Aug 16 06:27:13 PM PDT 24
Finished Aug 16 06:28:36 PM PDT 24
Peak memory 183552 kb
Host smart-e1815e9d-e208-4f2b-8f8b-ba7822908d9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757861351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.757861351
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.396340843
Short name T326
Test name
Test status
Simulation time 145639376190 ps
CPU time 712.01 seconds
Started Aug 16 06:27:19 PM PDT 24
Finished Aug 16 06:39:11 PM PDT 24
Peak memory 191708 kb
Host smart-d9c88eec-dda5-49c2-920e-f098d985ab76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396340843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.396340843
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1201837803
Short name T176
Test name
Test status
Simulation time 432442048489 ps
CPU time 226.69 seconds
Started Aug 16 06:27:26 PM PDT 24
Finished Aug 16 06:31:13 PM PDT 24
Peak memory 183580 kb
Host smart-7f5f48c4-93ce-4cd3-9920-a26d8d8f10aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201837803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1201837803
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.27154347
Short name T359
Test name
Test status
Simulation time 268425058045 ps
CPU time 164.94 seconds
Started Aug 16 06:27:15 PM PDT 24
Finished Aug 16 06:30:00 PM PDT 24
Peak memory 183384 kb
Host smart-9ccff9f9-495f-4cb1-9498-d9016afbb21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27154347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.27154347
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2095037804
Short name T450
Test name
Test status
Simulation time 934340523 ps
CPU time 0.78 seconds
Started Aug 16 06:27:32 PM PDT 24
Finished Aug 16 06:27:33 PM PDT 24
Peak memory 183264 kb
Host smart-103c7676-c921-4a61-8205-6662885e40e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095037804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2095037804
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2379687427
Short name T16
Test name
Test status
Simulation time 86296325 ps
CPU time 0.71 seconds
Started Aug 16 06:27:15 PM PDT 24
Finished Aug 16 06:27:16 PM PDT 24
Peak memory 214552 kb
Host smart-8f864c0f-d3c5-45a5-b136-18d51539b9fe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379687427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2379687427
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3448224509
Short name T42
Test name
Test status
Simulation time 1501528996186 ps
CPU time 482.81 seconds
Started Aug 16 06:27:15 PM PDT 24
Finished Aug 16 06:35:18 PM PDT 24
Peak memory 196672 kb
Host smart-c973414b-1fb1-4e70-81fa-f063df96a5d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448224509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3448224509
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.929280615
Short name T364
Test name
Test status
Simulation time 261295155290 ps
CPU time 248.9 seconds
Started Aug 16 06:27:27 PM PDT 24
Finished Aug 16 06:31:36 PM PDT 24
Peak memory 183528 kb
Host smart-974c5ecc-bf9d-4a3e-80d2-14dae11132b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929280615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.929280615
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.117390867
Short name T387
Test name
Test status
Simulation time 352816912847 ps
CPU time 235.26 seconds
Started Aug 16 06:27:20 PM PDT 24
Finished Aug 16 06:31:15 PM PDT 24
Peak memory 183612 kb
Host smart-69beacbe-3f15-4a38-a711-3eceabb3a0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117390867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.117390867
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.135833538
Short name T342
Test name
Test status
Simulation time 15688855534 ps
CPU time 127.75 seconds
Started Aug 16 06:27:26 PM PDT 24
Finished Aug 16 06:29:34 PM PDT 24
Peak memory 183564 kb
Host smart-f1865829-960c-4efc-9793-f022baeab776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135833538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.135833538
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.160598288
Short name T65
Test name
Test status
Simulation time 46100987816 ps
CPU time 63.69 seconds
Started Aug 16 06:27:22 PM PDT 24
Finished Aug 16 06:28:26 PM PDT 24
Peak memory 183516 kb
Host smart-723b81ce-5af6-4271-8d46-dd7ffee8fd9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160598288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
160598288
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.1521556609
Short name T45
Test name
Test status
Simulation time 6695222329 ps
CPU time 47.37 seconds
Started Aug 16 06:27:43 PM PDT 24
Finished Aug 16 06:28:30 PM PDT 24
Peak memory 198260 kb
Host smart-a7c12f57-ccb3-4328-a87c-3724334f2f4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521556609 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.1521556609
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.2216482037
Short name T143
Test name
Test status
Simulation time 321453006043 ps
CPU time 468.92 seconds
Started Aug 16 06:28:00 PM PDT 24
Finished Aug 16 06:35:49 PM PDT 24
Peak memory 191760 kb
Host smart-678d3e35-a589-4593-95fe-cc1b558303bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216482037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2216482037
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3797065145
Short name T53
Test name
Test status
Simulation time 54356664386 ps
CPU time 86.65 seconds
Started Aug 16 06:28:05 PM PDT 24
Finished Aug 16 06:29:32 PM PDT 24
Peak memory 191812 kb
Host smart-b50e8129-f87b-45de-90a1-f0d074c9c5bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797065145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3797065145
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1769659098
Short name T136
Test name
Test status
Simulation time 192191832062 ps
CPU time 1543.45 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:53:46 PM PDT 24
Peak memory 191740 kb
Host smart-b3ea736e-9104-4ed9-98fd-701a54827780
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769659098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1769659098
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3441342331
Short name T266
Test name
Test status
Simulation time 264414664551 ps
CPU time 364.62 seconds
Started Aug 16 06:28:04 PM PDT 24
Finished Aug 16 06:34:09 PM PDT 24
Peak memory 191780 kb
Host smart-f209acd2-fd4d-45b3-9fbb-ad24a4ed7b2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441342331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3441342331
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3520774548
Short name T444
Test name
Test status
Simulation time 38957364664 ps
CPU time 104.65 seconds
Started Aug 16 06:28:08 PM PDT 24
Finished Aug 16 06:29:53 PM PDT 24
Peak memory 183396 kb
Host smart-a548b566-07a4-43a7-9e5f-9d16b422adc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520774548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3520774548
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3494996147
Short name T214
Test name
Test status
Simulation time 10916778689 ps
CPU time 6.44 seconds
Started Aug 16 06:27:40 PM PDT 24
Finished Aug 16 06:27:47 PM PDT 24
Peak memory 183532 kb
Host smart-ee01219a-eba0-484f-89a9-2c8ca7ca6d0f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494996147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3494996147
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2069410229
Short name T396
Test name
Test status
Simulation time 79095418412 ps
CPU time 119.65 seconds
Started Aug 16 06:27:25 PM PDT 24
Finished Aug 16 06:29:25 PM PDT 24
Peak memory 183528 kb
Host smart-de6aaa5c-4f71-4ab6-b82d-d1e27ac04463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069410229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2069410229
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2174166404
Short name T451
Test name
Test status
Simulation time 200638257589 ps
CPU time 156.09 seconds
Started Aug 16 06:27:34 PM PDT 24
Finished Aug 16 06:30:11 PM PDT 24
Peak memory 183532 kb
Host smart-d41f9701-30af-4541-bb34-bb48ae438cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174166404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2174166404
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1154024166
Short name T292
Test name
Test status
Simulation time 74824102869 ps
CPU time 319.06 seconds
Started Aug 16 06:27:18 PM PDT 24
Finished Aug 16 06:32:37 PM PDT 24
Peak memory 193872 kb
Host smart-6983feb3-a5a9-4377-91d2-c7e6269d1384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154024166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1154024166
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.613970838
Short name T129
Test name
Test status
Simulation time 295381243928 ps
CPU time 495.16 seconds
Started Aug 16 06:27:24 PM PDT 24
Finished Aug 16 06:35:39 PM PDT 24
Peak memory 191768 kb
Host smart-ee33be0f-cfe2-4c32-b626-f3d05871bf97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613970838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
613970838
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.754549528
Short name T35
Test name
Test status
Simulation time 2394395998 ps
CPU time 26 seconds
Started Aug 16 06:27:17 PM PDT 24
Finished Aug 16 06:27:43 PM PDT 24
Peak memory 198276 kb
Host smart-641a7c59-8801-4b76-a62b-b50868d0ea29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754549528 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.754549528
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.1826965648
Short name T173
Test name
Test status
Simulation time 243321919471 ps
CPU time 581.25 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:37:43 PM PDT 24
Peak memory 191800 kb
Host smart-13361ab6-6433-4051-8417-1e1f0d4abf39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826965648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1826965648
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2196151074
Short name T21
Test name
Test status
Simulation time 472603210307 ps
CPU time 387.19 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:34:30 PM PDT 24
Peak memory 191756 kb
Host smart-d60d6968-4f74-4e03-bda9-7a405129a8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196151074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2196151074
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3466665007
Short name T168
Test name
Test status
Simulation time 85105983154 ps
CPU time 143.94 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:30:27 PM PDT 24
Peak memory 191756 kb
Host smart-41000820-2d0b-4104-8a5c-dc8ea0268810
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466665007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3466665007
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.4283241379
Short name T39
Test name
Test status
Simulation time 36016961543 ps
CPU time 310.59 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:33:13 PM PDT 24
Peak memory 183552 kb
Host smart-f93fa3cc-ca97-4eda-93f7-f2150373a9d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283241379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.4283241379
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3426450296
Short name T337
Test name
Test status
Simulation time 228051885114 ps
CPU time 73.6 seconds
Started Aug 16 06:28:04 PM PDT 24
Finished Aug 16 06:29:21 PM PDT 24
Peak memory 194172 kb
Host smart-a4bf25db-67b0-46a5-a039-331d037866d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426450296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3426450296
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2251952077
Short name T423
Test name
Test status
Simulation time 51981894331 ps
CPU time 83.23 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:29:25 PM PDT 24
Peak memory 191804 kb
Host smart-8d32a40e-6156-46bf-99f7-bccaa79a3439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251952077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2251952077
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.44942171
Short name T371
Test name
Test status
Simulation time 26199993409 ps
CPU time 41 seconds
Started Aug 16 06:27:20 PM PDT 24
Finished Aug 16 06:28:01 PM PDT 24
Peak memory 183572 kb
Host smart-716c914a-424b-46b2-944a-a62ec2dc8b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44942171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.44942171
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2958936607
Short name T248
Test name
Test status
Simulation time 277576877610 ps
CPU time 984.72 seconds
Started Aug 16 06:27:17 PM PDT 24
Finished Aug 16 06:43:42 PM PDT 24
Peak memory 191788 kb
Host smart-7177e9a1-a694-4e0c-b7aa-c5913876eecf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958936607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2958936607
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1285081809
Short name T377
Test name
Test status
Simulation time 341745034 ps
CPU time 1.08 seconds
Started Aug 16 06:27:16 PM PDT 24
Finished Aug 16 06:27:17 PM PDT 24
Peak memory 191660 kb
Host smart-2e72ba53-45e3-4932-b767-9bbf59e54a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285081809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1285081809
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.848767092
Short name T36
Test name
Test status
Simulation time 2569047640 ps
CPU time 31.21 seconds
Started Aug 16 06:27:15 PM PDT 24
Finished Aug 16 06:27:47 PM PDT 24
Peak memory 194736 kb
Host smart-37a569d0-6208-4350-b371-7fe43ccd3c5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848767092 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.848767092
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.3090670193
Short name T310
Test name
Test status
Simulation time 50946675921 ps
CPU time 76.3 seconds
Started Aug 16 06:28:00 PM PDT 24
Finished Aug 16 06:29:17 PM PDT 24
Peak memory 183616 kb
Host smart-73f0e567-1dfc-4b74-975f-8085cce57fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090670193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3090670193
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2652466283
Short name T186
Test name
Test status
Simulation time 711920364517 ps
CPU time 399.45 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:34:42 PM PDT 24
Peak memory 191800 kb
Host smart-6e958d24-2444-4f56-ad13-308210aa344c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652466283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2652466283
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.4217779382
Short name T273
Test name
Test status
Simulation time 423918214611 ps
CPU time 856.62 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:42:20 PM PDT 24
Peak memory 191776 kb
Host smart-9ee6da87-3e22-439a-a9ed-f8f681c7c1df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217779382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.4217779382
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1822864413
Short name T309
Test name
Test status
Simulation time 145111165341 ps
CPU time 144.47 seconds
Started Aug 16 06:28:01 PM PDT 24
Finished Aug 16 06:30:26 PM PDT 24
Peak memory 191804 kb
Host smart-2002a436-700f-420e-80a9-5261fa1f19bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822864413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1822864413
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.525820360
Short name T121
Test name
Test status
Simulation time 106058916797 ps
CPU time 414.73 seconds
Started Aug 16 06:28:04 PM PDT 24
Finished Aug 16 06:34:59 PM PDT 24
Peak memory 191792 kb
Host smart-1b6ec5c2-5954-4874-8494-27f1ab08d388
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525820360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.525820360
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3578128018
Short name T115
Test name
Test status
Simulation time 122250380580 ps
CPU time 140.1 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:30:22 PM PDT 24
Peak memory 191800 kb
Host smart-dd462486-e809-474a-91ac-6c16e85aab88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578128018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3578128018
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1506680032
Short name T170
Test name
Test status
Simulation time 252102951257 ps
CPU time 492.6 seconds
Started Aug 16 06:28:01 PM PDT 24
Finished Aug 16 06:36:14 PM PDT 24
Peak memory 191812 kb
Host smart-b9fad321-78b8-470e-9faf-8c6771070c67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506680032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1506680032
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2338406365
Short name T188
Test name
Test status
Simulation time 378671944174 ps
CPU time 394.21 seconds
Started Aug 16 06:28:01 PM PDT 24
Finished Aug 16 06:34:35 PM PDT 24
Peak memory 191792 kb
Host smart-33912b76-2c76-495b-bd2b-2d4b682a49b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338406365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2338406365
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1194269372
Short name T325
Test name
Test status
Simulation time 68871931882 ps
CPU time 135.6 seconds
Started Aug 16 06:28:07 PM PDT 24
Finished Aug 16 06:30:23 PM PDT 24
Peak memory 191816 kb
Host smart-e5d55a23-ab4d-418a-8a20-324d585853ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194269372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1194269372
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3676638383
Short name T208
Test name
Test status
Simulation time 125501651679 ps
CPU time 107.26 seconds
Started Aug 16 06:28:08 PM PDT 24
Finished Aug 16 06:29:56 PM PDT 24
Peak memory 191816 kb
Host smart-4d6577e1-7f6e-429b-9d30-f135e47fc8ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676638383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3676638383
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.169980023
Short name T197
Test name
Test status
Simulation time 504231848557 ps
CPU time 228.52 seconds
Started Aug 16 06:27:18 PM PDT 24
Finished Aug 16 06:31:07 PM PDT 24
Peak memory 183636 kb
Host smart-cb85b560-a931-46d3-b45b-84a899afbc3f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169980023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.169980023
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1695078770
Short name T413
Test name
Test status
Simulation time 559701918109 ps
CPU time 235 seconds
Started Aug 16 06:27:36 PM PDT 24
Finished Aug 16 06:31:32 PM PDT 24
Peak memory 183564 kb
Host smart-e026835d-d4f5-4fe1-87ae-a0583871392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695078770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1695078770
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1558071786
Short name T327
Test name
Test status
Simulation time 330865586860 ps
CPU time 178.56 seconds
Started Aug 16 06:27:48 PM PDT 24
Finished Aug 16 06:30:46 PM PDT 24
Peak memory 191776 kb
Host smart-5fe96318-d6fb-45b6-b5d3-c828068580c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558071786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1558071786
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2850536422
Short name T228
Test name
Test status
Simulation time 797769890088 ps
CPU time 696.54 seconds
Started Aug 16 06:27:18 PM PDT 24
Finished Aug 16 06:38:54 PM PDT 24
Peak memory 191800 kb
Host smart-403d06f0-0673-4182-8fe3-9cff9f31b9b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850536422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2850536422
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.2899166163
Short name T11
Test name
Test status
Simulation time 1163191235 ps
CPU time 11.51 seconds
Started Aug 16 06:27:24 PM PDT 24
Finished Aug 16 06:27:35 PM PDT 24
Peak memory 198168 kb
Host smart-3434f36f-2822-459d-848e-bf572b08d7db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899166163 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.2899166163
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.766058513
Short name T320
Test name
Test status
Simulation time 59897664374 ps
CPU time 106.7 seconds
Started Aug 16 06:28:24 PM PDT 24
Finished Aug 16 06:30:11 PM PDT 24
Peak memory 191812 kb
Host smart-40f59e17-4ff1-4dd9-b578-ab054f237a03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766058513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.766058513
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3009704477
Short name T178
Test name
Test status
Simulation time 153196222511 ps
CPU time 280.95 seconds
Started Aug 16 06:28:06 PM PDT 24
Finished Aug 16 06:32:48 PM PDT 24
Peak memory 191724 kb
Host smart-e512e9e2-533f-4346-a886-359c3bf2a41f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009704477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3009704477
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1363900922
Short name T293
Test name
Test status
Simulation time 723188979146 ps
CPU time 1717 seconds
Started Aug 16 06:28:07 PM PDT 24
Finished Aug 16 06:56:44 PM PDT 24
Peak memory 193892 kb
Host smart-6b21d22d-faf5-479d-914e-9b5434801316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363900922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1363900922
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1551648778
Short name T247
Test name
Test status
Simulation time 196371386754 ps
CPU time 337.85 seconds
Started Aug 16 06:28:15 PM PDT 24
Finished Aug 16 06:33:53 PM PDT 24
Peak memory 191768 kb
Host smart-424cffb6-e5c0-4dd5-8238-18216ec89b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551648778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1551648778
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3299763484
Short name T1
Test name
Test status
Simulation time 436845344056 ps
CPU time 550.12 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:37:18 PM PDT 24
Peak memory 191712 kb
Host smart-0d5b4a61-1eb0-42c0-92ff-19b935f35167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299763484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3299763484
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3815278401
Short name T203
Test name
Test status
Simulation time 316849296125 ps
CPU time 747.87 seconds
Started Aug 16 06:28:05 PM PDT 24
Finished Aug 16 06:40:33 PM PDT 24
Peak memory 191792 kb
Host smart-7ffccdd4-100e-4ba6-aaf8-f67bdab3c2dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815278401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3815278401
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1056859188
Short name T302
Test name
Test status
Simulation time 185096438864 ps
CPU time 589.22 seconds
Started Aug 16 06:28:04 PM PDT 24
Finished Aug 16 06:37:53 PM PDT 24
Peak memory 191792 kb
Host smart-a34c297e-db4a-4f84-86f6-90b6f6ac3c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056859188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1056859188
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.127506996
Short name T329
Test name
Test status
Simulation time 14027886305 ps
CPU time 11.97 seconds
Started Aug 16 06:27:20 PM PDT 24
Finished Aug 16 06:27:32 PM PDT 24
Peak memory 183596 kb
Host smart-cce4acfd-efa9-4986-b1b6-3e66bbfc38aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127506996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.127506996
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2127861775
Short name T392
Test name
Test status
Simulation time 171913000315 ps
CPU time 221.88 seconds
Started Aug 16 06:27:19 PM PDT 24
Finished Aug 16 06:31:01 PM PDT 24
Peak memory 183608 kb
Host smart-110f896e-83a2-4017-9cb6-24fed3ba046a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127861775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2127861775
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.112218857
Short name T427
Test name
Test status
Simulation time 257405966087 ps
CPU time 116.87 seconds
Started Aug 16 06:27:17 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 191756 kb
Host smart-289c6373-07eb-4716-aed9-fb42368fa50d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112218857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.112218857
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1380301977
Short name T433
Test name
Test status
Simulation time 44638315622 ps
CPU time 61.88 seconds
Started Aug 16 06:27:19 PM PDT 24
Finished Aug 16 06:28:21 PM PDT 24
Peak memory 191768 kb
Host smart-120bbdc4-9ac5-45ca-b096-3bd1ae156cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380301977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1380301977
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3596112079
Short name T356
Test name
Test status
Simulation time 32952070 ps
CPU time 0.58 seconds
Started Aug 16 06:27:47 PM PDT 24
Finished Aug 16 06:27:47 PM PDT 24
Peak memory 183248 kb
Host smart-4a370f49-ff9e-4f37-afe1-67607ef3461e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596112079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3596112079
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/142.rv_timer_random.4156726232
Short name T221
Test name
Test status
Simulation time 737896739295 ps
CPU time 1830.44 seconds
Started Aug 16 06:28:08 PM PDT 24
Finished Aug 16 06:58:39 PM PDT 24
Peak memory 191796 kb
Host smart-3f21239c-4f43-4e44-b531-c291761496fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156726232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4156726232
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1664256063
Short name T276
Test name
Test status
Simulation time 86001243746 ps
CPU time 130.05 seconds
Started Aug 16 06:28:10 PM PDT 24
Finished Aug 16 06:30:20 PM PDT 24
Peak memory 191852 kb
Host smart-d24b06e0-1080-44b8-a02d-9bd8f0e16489
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664256063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1664256063
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2402662774
Short name T284
Test name
Test status
Simulation time 491276776194 ps
CPU time 263.03 seconds
Started Aug 16 06:28:13 PM PDT 24
Finished Aug 16 06:32:36 PM PDT 24
Peak memory 191764 kb
Host smart-547eb671-65db-4b18-acaa-909287b3bd8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402662774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2402662774
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3812214817
Short name T151
Test name
Test status
Simulation time 488793890897 ps
CPU time 335.32 seconds
Started Aug 16 06:28:16 PM PDT 24
Finished Aug 16 06:33:51 PM PDT 24
Peak memory 191720 kb
Host smart-4383e1d9-8028-4e0f-8d29-0b4bae143d79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812214817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3812214817
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2335556620
Short name T304
Test name
Test status
Simulation time 636235290374 ps
CPU time 658.59 seconds
Started Aug 16 06:28:09 PM PDT 24
Finished Aug 16 06:39:08 PM PDT 24
Peak memory 191824 kb
Host smart-9421d1f0-9380-428b-89a3-582e0375ab7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335556620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2335556620
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1094830998
Short name T114
Test name
Test status
Simulation time 52919918512 ps
CPU time 83.72 seconds
Started Aug 16 06:28:08 PM PDT 24
Finished Aug 16 06:29:32 PM PDT 24
Peak memory 191784 kb
Host smart-6e0a3b71-d258-423e-9e70-64197bba1ce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094830998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1094830998
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.54829986
Short name T296
Test name
Test status
Simulation time 2353156132 ps
CPU time 4.66 seconds
Started Aug 16 06:27:45 PM PDT 24
Finished Aug 16 06:27:50 PM PDT 24
Peak memory 183588 kb
Host smart-e0b9725e-ca2d-4df3-b663-f736b22ee512
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54829986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.rv_timer_cfg_update_on_fly.54829986
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3721777320
Short name T24
Test name
Test status
Simulation time 18028690247 ps
CPU time 15.55 seconds
Started Aug 16 06:27:46 PM PDT 24
Finished Aug 16 06:28:02 PM PDT 24
Peak memory 183584 kb
Host smart-39f01319-4157-445f-ab2e-afd1df7c73e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721777320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3721777320
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1626107056
Short name T386
Test name
Test status
Simulation time 43236581792 ps
CPU time 252.86 seconds
Started Aug 16 06:27:26 PM PDT 24
Finished Aug 16 06:31:39 PM PDT 24
Peak memory 183480 kb
Host smart-94315688-bed9-4307-ae3c-95fd388e4461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626107056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1626107056
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.1068856990
Short name T122
Test name
Test status
Simulation time 316699717487 ps
CPU time 485.89 seconds
Started Aug 16 06:28:15 PM PDT 24
Finished Aug 16 06:36:21 PM PDT 24
Peak memory 191724 kb
Host smart-14c9e639-b58a-4b7b-ade5-39d060d6ab73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068856990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1068856990
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3733830947
Short name T180
Test name
Test status
Simulation time 80532281357 ps
CPU time 81.78 seconds
Started Aug 16 06:28:12 PM PDT 24
Finished Aug 16 06:29:34 PM PDT 24
Peak memory 183652 kb
Host smart-7db5d4e0-25ca-45cd-8b8f-7249b8c00492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733830947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3733830947
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.433510712
Short name T194
Test name
Test status
Simulation time 12200123352 ps
CPU time 19.83 seconds
Started Aug 16 06:28:09 PM PDT 24
Finished Aug 16 06:28:29 PM PDT 24
Peak memory 183600 kb
Host smart-1335747c-1bba-4ef0-bb31-26852ab09497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433510712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.433510712
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.725969047
Short name T57
Test name
Test status
Simulation time 89877682507 ps
CPU time 79.32 seconds
Started Aug 16 06:28:11 PM PDT 24
Finished Aug 16 06:29:30 PM PDT 24
Peak memory 183608 kb
Host smart-1089866c-bde1-4697-aafe-ce8b04f1e663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725969047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.725969047
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3017525636
Short name T175
Test name
Test status
Simulation time 215212827633 ps
CPU time 1216.54 seconds
Started Aug 16 06:28:08 PM PDT 24
Finished Aug 16 06:48:25 PM PDT 24
Peak memory 191788 kb
Host smart-77157b72-001b-492f-a371-dd4ab60ad88c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017525636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3017525636
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3289236627
Short name T303
Test name
Test status
Simulation time 10365931334 ps
CPU time 41.34 seconds
Started Aug 16 06:28:25 PM PDT 24
Finished Aug 16 06:29:07 PM PDT 24
Peak memory 191768 kb
Host smart-a58573ba-7bb0-44a8-bb9f-72ce4e744d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289236627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3289236627
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.4260816563
Short name T270
Test name
Test status
Simulation time 421385591085 ps
CPU time 259.31 seconds
Started Aug 16 06:28:12 PM PDT 24
Finished Aug 16 06:32:32 PM PDT 24
Peak memory 195292 kb
Host smart-669e47d9-c4ae-46bf-afce-a999e2a88c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260816563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.4260816563
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2108336677
Short name T179
Test name
Test status
Simulation time 138113222721 ps
CPU time 249.82 seconds
Started Aug 16 06:28:17 PM PDT 24
Finished Aug 16 06:32:27 PM PDT 24
Peak memory 191740 kb
Host smart-0c2d58b8-cd56-4152-92a4-18c64db993c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108336677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2108336677
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.656448540
Short name T339
Test name
Test status
Simulation time 2606926658492 ps
CPU time 728.97 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:40:02 PM PDT 24
Peak memory 183580 kb
Host smart-9a467151-ec23-4f8d-98f0-a1b6dded0c95
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656448540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.656448540
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3423018330
Short name T353
Test name
Test status
Simulation time 355359129764 ps
CPU time 159.03 seconds
Started Aug 16 06:27:44 PM PDT 24
Finished Aug 16 06:30:23 PM PDT 24
Peak memory 183568 kb
Host smart-ba9e4642-6294-4fdd-b8f6-25235a08d217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423018330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3423018330
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.1075876373
Short name T246
Test name
Test status
Simulation time 676569169002 ps
CPU time 497.19 seconds
Started Aug 16 06:27:47 PM PDT 24
Finished Aug 16 06:36:04 PM PDT 24
Peak memory 191788 kb
Host smart-4bd99609-8a74-4cc2-955e-808695b3c19a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075876373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1075876373
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.35102603
Short name T105
Test name
Test status
Simulation time 541572176625 ps
CPU time 188.25 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:31:01 PM PDT 24
Peak memory 194296 kb
Host smart-b13bb582-09c5-400d-985f-2c6c2b66e4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35102603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.35102603
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2880572412
Short name T227
Test name
Test status
Simulation time 732816073891 ps
CPU time 907.32 seconds
Started Aug 16 06:27:26 PM PDT 24
Finished Aug 16 06:42:33 PM PDT 24
Peak memory 191708 kb
Host smart-1646b145-11d5-4367-b569-a3dcb4e202cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880572412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2880572412
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.274361567
Short name T142
Test name
Test status
Simulation time 158865824321 ps
CPU time 85.97 seconds
Started Aug 16 06:28:32 PM PDT 24
Finished Aug 16 06:29:58 PM PDT 24
Peak memory 191828 kb
Host smart-22a0a265-7f22-468a-bc69-b5bfb0e84b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274361567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.274361567
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1270303875
Short name T241
Test name
Test status
Simulation time 284900653018 ps
CPU time 162.13 seconds
Started Aug 16 06:28:29 PM PDT 24
Finished Aug 16 06:31:12 PM PDT 24
Peak memory 191768 kb
Host smart-5b82ab35-8928-4261-945c-68e82c0de6cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270303875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1270303875
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2946501740
Short name T137
Test name
Test status
Simulation time 1693332372377 ps
CPU time 325.29 seconds
Started Aug 16 06:28:28 PM PDT 24
Finished Aug 16 06:33:53 PM PDT 24
Peak memory 191756 kb
Host smart-8f3fc8d5-a403-4467-964f-8e917465db6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946501740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2946501740
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2839019997
Short name T164
Test name
Test status
Simulation time 302909539353 ps
CPU time 278.57 seconds
Started Aug 16 06:28:20 PM PDT 24
Finished Aug 16 06:32:58 PM PDT 24
Peak memory 191716 kb
Host smart-38ca19bc-1507-4c9f-bcc1-e434d34e96b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839019997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2839019997
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1204648190
Short name T19
Test name
Test status
Simulation time 495122818159 ps
CPU time 335.48 seconds
Started Aug 16 06:28:35 PM PDT 24
Finished Aug 16 06:34:11 PM PDT 24
Peak memory 191780 kb
Host smart-bb18514e-f4cd-4104-b2d9-1a30afa30ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204648190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1204648190
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.4044540471
Short name T283
Test name
Test status
Simulation time 92956432067 ps
CPU time 144.28 seconds
Started Aug 16 06:28:17 PM PDT 24
Finished Aug 16 06:30:42 PM PDT 24
Peak memory 191788 kb
Host smart-6a82a82a-aa83-4832-a839-d603422fd4f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044540471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.4044540471
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3941546378
Short name T376
Test name
Test status
Simulation time 58913885389 ps
CPU time 127.43 seconds
Started Aug 16 06:28:16 PM PDT 24
Finished Aug 16 06:30:24 PM PDT 24
Peak memory 191820 kb
Host smart-98139e28-8854-4f35-b3fb-a5a94f246aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941546378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3941546378
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1340225406
Short name T324
Test name
Test status
Simulation time 145724770173 ps
CPU time 67.74 seconds
Started Aug 16 06:28:15 PM PDT 24
Finished Aug 16 06:29:23 PM PDT 24
Peak memory 183580 kb
Host smart-052c8c56-1d17-4a27-a603-e0dedb824172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340225406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1340225406
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2545931413
Short name T428
Test name
Test status
Simulation time 251791731607 ps
CPU time 170.63 seconds
Started Aug 16 06:27:27 PM PDT 24
Finished Aug 16 06:30:18 PM PDT 24
Peak memory 183520 kb
Host smart-cfde8f39-7765-45b8-a1a1-8ce34e0bd4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545931413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2545931413
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3701398058
Short name T110
Test name
Test status
Simulation time 114418678362 ps
CPU time 420.66 seconds
Started Aug 16 06:27:25 PM PDT 24
Finished Aug 16 06:34:26 PM PDT 24
Peak memory 191800 kb
Host smart-01769819-7b98-44e1-881e-d7f320b5d465
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701398058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3701398058
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.800853686
Short name T68
Test name
Test status
Simulation time 24726104489 ps
CPU time 38.9 seconds
Started Aug 16 06:27:39 PM PDT 24
Finished Aug 16 06:28:18 PM PDT 24
Peak memory 195288 kb
Host smart-904200c3-a3a9-473b-83c4-bf3a6dce2c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800853686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.800853686
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.4071944537
Short name T41
Test name
Test status
Simulation time 208317372732 ps
CPU time 130.64 seconds
Started Aug 16 06:28:32 PM PDT 24
Finished Aug 16 06:30:43 PM PDT 24
Peak memory 183576 kb
Host smart-1793980a-89e2-4381-8930-78563622c1bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071944537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.4071944537
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3728189800
Short name T223
Test name
Test status
Simulation time 227152998104 ps
CPU time 655.99 seconds
Started Aug 16 06:28:16 PM PDT 24
Finished Aug 16 06:39:12 PM PDT 24
Peak memory 191796 kb
Host smart-7ae3c97a-9393-4afa-b6c8-e08a77d5aebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728189800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3728189800
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3747197276
Short name T288
Test name
Test status
Simulation time 212387435907 ps
CPU time 400.12 seconds
Started Aug 16 06:28:36 PM PDT 24
Finished Aug 16 06:35:16 PM PDT 24
Peak memory 191776 kb
Host smart-b17379bc-bc40-4130-b6d3-0e107b8100b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747197276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3747197276
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3173834714
Short name T150
Test name
Test status
Simulation time 428875118283 ps
CPU time 206.85 seconds
Started Aug 16 06:28:30 PM PDT 24
Finished Aug 16 06:31:57 PM PDT 24
Peak memory 191768 kb
Host smart-865eeff7-fd72-4e8f-ac5e-1539a32361af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173834714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3173834714
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2750613097
Short name T243
Test name
Test status
Simulation time 19784863501 ps
CPU time 39.21 seconds
Started Aug 16 06:28:34 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 191756 kb
Host smart-41cfe2a2-c26e-4662-88a0-52d440506745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750613097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2750613097
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2447674252
Short name T252
Test name
Test status
Simulation time 301553568302 ps
CPU time 161.05 seconds
Started Aug 16 06:28:30 PM PDT 24
Finished Aug 16 06:31:11 PM PDT 24
Peak memory 191768 kb
Host smart-c65eb84d-e7ca-42a2-a514-b368c6e7eac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447674252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2447674252
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3373547318
Short name T290
Test name
Test status
Simulation time 21210427142 ps
CPU time 129.43 seconds
Started Aug 16 06:28:25 PM PDT 24
Finished Aug 16 06:30:35 PM PDT 24
Peak memory 183584 kb
Host smart-a3d20055-151b-4a0d-875a-2bb3d73ab221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373547318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3373547318
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.713931164
Short name T318
Test name
Test status
Simulation time 31693968560 ps
CPU time 53.18 seconds
Started Aug 16 06:27:25 PM PDT 24
Finished Aug 16 06:28:18 PM PDT 24
Peak memory 183592 kb
Host smart-203d2180-a1da-49e9-8905-20b12fa39ea1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713931164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.713931164
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2183259543
Short name T350
Test name
Test status
Simulation time 199211628337 ps
CPU time 77.25 seconds
Started Aug 16 06:27:27 PM PDT 24
Finished Aug 16 06:28:45 PM PDT 24
Peak memory 183572 kb
Host smart-3db77d73-f578-495d-9d24-813cbbbb0b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183259543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2183259543
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1797842478
Short name T210
Test name
Test status
Simulation time 372415235349 ps
CPU time 205.29 seconds
Started Aug 16 06:27:27 PM PDT 24
Finished Aug 16 06:30:52 PM PDT 24
Peak memory 191792 kb
Host smart-16e43eaa-41dc-4177-821b-71973737c79c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797842478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1797842478
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2803361863
Short name T211
Test name
Test status
Simulation time 218243037777 ps
CPU time 352.61 seconds
Started Aug 16 06:27:38 PM PDT 24
Finished Aug 16 06:33:31 PM PDT 24
Peak memory 191772 kb
Host smart-c8fc2a2d-d80a-4d28-bdb1-c5d3a6847819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803361863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2803361863
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1358281845
Short name T358
Test name
Test status
Simulation time 79447826 ps
CPU time 0.56 seconds
Started Aug 16 06:27:49 PM PDT 24
Finished Aug 16 06:27:49 PM PDT 24
Peak memory 183244 kb
Host smart-547b3f39-f909-4ec1-ac59-9fc3f5993d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358281845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1358281845
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.1365074452
Short name T328
Test name
Test status
Simulation time 320447781703 ps
CPU time 306.79 seconds
Started Aug 16 06:28:32 PM PDT 24
Finished Aug 16 06:33:39 PM PDT 24
Peak memory 191812 kb
Host smart-8b19de09-017d-4505-bf35-caa2b52aefa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365074452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1365074452
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3594805686
Short name T313
Test name
Test status
Simulation time 124498437398 ps
CPU time 483.01 seconds
Started Aug 16 06:28:25 PM PDT 24
Finished Aug 16 06:36:28 PM PDT 24
Peak memory 191772 kb
Host smart-419df3ff-459c-42e1-a637-06e8fb299db3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594805686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3594805686
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1052746287
Short name T341
Test name
Test status
Simulation time 192750217225 ps
CPU time 877.17 seconds
Started Aug 16 06:28:26 PM PDT 24
Finished Aug 16 06:43:04 PM PDT 24
Peak memory 191840 kb
Host smart-490c2292-af97-4956-863f-d8a4bb41fa96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052746287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1052746287
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3830106958
Short name T182
Test name
Test status
Simulation time 122643647588 ps
CPU time 594.14 seconds
Started Aug 16 06:28:33 PM PDT 24
Finished Aug 16 06:38:27 PM PDT 24
Peak memory 191716 kb
Host smart-20239303-1077-4f36-8f64-29c72ff4ba61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830106958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3830106958
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1268469504
Short name T286
Test name
Test status
Simulation time 52025107613 ps
CPU time 80.06 seconds
Started Aug 16 06:28:24 PM PDT 24
Finished Aug 16 06:29:44 PM PDT 24
Peak memory 191712 kb
Host smart-1306e1fd-556d-4524-ae47-6a82f27e29be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268469504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1268469504
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2367692861
Short name T275
Test name
Test status
Simulation time 126917764655 ps
CPU time 112.91 seconds
Started Aug 16 06:28:27 PM PDT 24
Finished Aug 16 06:30:20 PM PDT 24
Peak memory 191832 kb
Host smart-d41bf2ed-b8a2-4422-abb3-a87c086d945b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367692861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2367692861
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.577248129
Short name T400
Test name
Test status
Simulation time 401665631572 ps
CPU time 146.44 seconds
Started Aug 16 06:28:35 PM PDT 24
Finished Aug 16 06:31:01 PM PDT 24
Peak memory 191752 kb
Host smart-c5abd09d-b0e6-4ef8-a252-6afc8cbd70a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577248129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.577248129
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.818172395
Short name T375
Test name
Test status
Simulation time 30865557266 ps
CPU time 27 seconds
Started Aug 16 06:28:29 PM PDT 24
Finished Aug 16 06:28:56 PM PDT 24
Peak memory 183532 kb
Host smart-2056f78c-5481-4e1c-9ca3-855e1ab98f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818172395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.818172395
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2894291554
Short name T314
Test name
Test status
Simulation time 575756594348 ps
CPU time 878.68 seconds
Started Aug 16 06:28:33 PM PDT 24
Finished Aug 16 06:43:12 PM PDT 24
Peak memory 191756 kb
Host smart-c426989a-3109-4fa1-ae3f-6642d7022f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894291554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2894291554
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1736910926
Short name T102
Test name
Test status
Simulation time 344520967481 ps
CPU time 197.26 seconds
Started Aug 16 06:27:22 PM PDT 24
Finished Aug 16 06:30:39 PM PDT 24
Peak memory 183552 kb
Host smart-bae2944d-7996-4643-aeda-ebd2f3a3b5d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736910926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1736910926
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1257224773
Short name T348
Test name
Test status
Simulation time 52778954848 ps
CPU time 48.91 seconds
Started Aug 16 06:27:28 PM PDT 24
Finished Aug 16 06:28:17 PM PDT 24
Peak memory 183556 kb
Host smart-cc5a3bc4-cc6a-4aed-a957-ed35d3b9253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257224773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1257224773
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.3974697909
Short name T315
Test name
Test status
Simulation time 209519252718 ps
CPU time 317.92 seconds
Started Aug 16 06:27:44 PM PDT 24
Finished Aug 16 06:33:02 PM PDT 24
Peak memory 191760 kb
Host smart-b1680a53-5fb1-42c3-8321-0c6ac5a48389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974697909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3974697909
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1476539040
Short name T434
Test name
Test status
Simulation time 815591208696 ps
CPU time 167.48 seconds
Started Aug 16 06:27:23 PM PDT 24
Finished Aug 16 06:30:10 PM PDT 24
Peak memory 183580 kb
Host smart-e501c120-993c-491b-8455-b120792a4369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476539040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1476539040
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.1729858282
Short name T46
Test name
Test status
Simulation time 12851121251 ps
CPU time 28.2 seconds
Started Aug 16 06:27:27 PM PDT 24
Finished Aug 16 06:27:55 PM PDT 24
Peak memory 198180 kb
Host smart-0d5f269d-3315-4d69-a104-94e4ce6bde71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729858282 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.1729858282
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.2059906424
Short name T124
Test name
Test status
Simulation time 485060398123 ps
CPU time 218.83 seconds
Started Aug 16 06:28:33 PM PDT 24
Finished Aug 16 06:32:12 PM PDT 24
Peak memory 191772 kb
Host smart-4451ea88-5305-477c-adf7-01e6b0e2b8d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059906424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2059906424
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2604893236
Short name T306
Test name
Test status
Simulation time 249890069851 ps
CPU time 1415.41 seconds
Started Aug 16 06:28:23 PM PDT 24
Finished Aug 16 06:51:59 PM PDT 24
Peak memory 191780 kb
Host smart-86187482-98a8-4f37-b710-81cf054b308f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604893236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2604893236
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.243241718
Short name T403
Test name
Test status
Simulation time 139763932013 ps
CPU time 245.91 seconds
Started Aug 16 06:28:24 PM PDT 24
Finished Aug 16 06:32:30 PM PDT 24
Peak memory 191840 kb
Host smart-882332d0-183f-4baf-ae9c-7557ebf79d8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243241718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.243241718
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1903968524
Short name T69
Test name
Test status
Simulation time 166421182674 ps
CPU time 110.53 seconds
Started Aug 16 06:28:23 PM PDT 24
Finished Aug 16 06:30:14 PM PDT 24
Peak memory 183604 kb
Host smart-acd0d250-6cfa-478c-abb0-c154de6ff675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903968524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1903968524
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3643210045
Short name T430
Test name
Test status
Simulation time 28090494834 ps
CPU time 9.86 seconds
Started Aug 16 06:28:26 PM PDT 24
Finished Aug 16 06:28:36 PM PDT 24
Peak memory 183612 kb
Host smart-04f7a7f7-e0d9-4385-8b73-55e113aad744
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643210045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3643210045
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1616676017
Short name T335
Test name
Test status
Simulation time 14987374143 ps
CPU time 14.6 seconds
Started Aug 16 06:28:38 PM PDT 24
Finished Aug 16 06:28:52 PM PDT 24
Peak memory 183544 kb
Host smart-67c42038-e7dc-4eb3-bb07-4e76037e4267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616676017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1616676017
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.249279017
Short name T207
Test name
Test status
Simulation time 152570630829 ps
CPU time 264.28 seconds
Started Aug 16 06:28:26 PM PDT 24
Finished Aug 16 06:32:51 PM PDT 24
Peak memory 191852 kb
Host smart-f09a8a5a-40d7-4ced-8de0-c09c38bc9df1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249279017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.249279017
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3315936967
Short name T38
Test name
Test status
Simulation time 158640957810 ps
CPU time 140.5 seconds
Started Aug 16 06:28:34 PM PDT 24
Finished Aug 16 06:30:55 PM PDT 24
Peak memory 191764 kb
Host smart-200f943e-2b9e-4896-b76d-f942918bfb6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315936967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3315936967
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.98512034
Short name T422
Test name
Test status
Simulation time 860613031462 ps
CPU time 225.87 seconds
Started Aug 16 06:28:38 PM PDT 24
Finished Aug 16 06:32:24 PM PDT 24
Peak memory 191784 kb
Host smart-57c770f4-ee17-42fc-8593-8f6b74715103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98512034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.98512034
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.489899868
Short name T73
Test name
Test status
Simulation time 42309201555 ps
CPU time 69.12 seconds
Started Aug 16 06:28:34 PM PDT 24
Finished Aug 16 06:29:44 PM PDT 24
Peak memory 183388 kb
Host smart-8331d5f3-7619-4a79-876a-06dad7b072df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489899868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.489899868
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.401804110
Short name T216
Test name
Test status
Simulation time 192628038094 ps
CPU time 341.1 seconds
Started Aug 16 06:27:12 PM PDT 24
Finished Aug 16 06:32:54 PM PDT 24
Peak memory 183552 kb
Host smart-84ec6315-740c-48b5-b985-7918f980d492
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401804110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.401804110
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3632196962
Short name T372
Test name
Test status
Simulation time 657344705209 ps
CPU time 277.19 seconds
Started Aug 16 06:27:15 PM PDT 24
Finished Aug 16 06:31:52 PM PDT 24
Peak memory 183564 kb
Host smart-ac0d35f2-9ba1-4c4c-bd79-7189e256ca31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632196962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3632196962
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.725758741
Short name T108
Test name
Test status
Simulation time 318413014893 ps
CPU time 497.2 seconds
Started Aug 16 06:27:10 PM PDT 24
Finished Aug 16 06:35:27 PM PDT 24
Peak memory 191796 kb
Host smart-f62befcd-dbd3-4ec1-8116-9972c1e36185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725758741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.725758741
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1922678457
Short name T429
Test name
Test status
Simulation time 58631593392 ps
CPU time 25.31 seconds
Started Aug 16 06:27:45 PM PDT 24
Finished Aug 16 06:28:11 PM PDT 24
Peak memory 191804 kb
Host smart-2e44571d-4e89-43e0-91a7-159169ccff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922678457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1922678457
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.416407286
Short name T14
Test name
Test status
Simulation time 87074810 ps
CPU time 0.89 seconds
Started Aug 16 06:27:13 PM PDT 24
Finished Aug 16 06:27:15 PM PDT 24
Peak memory 215036 kb
Host smart-2da75728-b23a-43b7-ba8f-f6bbee19eb19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416407286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.416407286
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.947443095
Short name T407
Test name
Test status
Simulation time 586119068210 ps
CPU time 492.14 seconds
Started Aug 16 06:27:40 PM PDT 24
Finished Aug 16 06:35:52 PM PDT 24
Peak memory 183572 kb
Host smart-4f93e885-bdd7-495c-8d36-68ea8636845f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947443095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.947443095
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3396151519
Short name T380
Test name
Test status
Simulation time 57083075848 ps
CPU time 92.57 seconds
Started Aug 16 06:27:26 PM PDT 24
Finished Aug 16 06:28:59 PM PDT 24
Peak memory 183588 kb
Host smart-cac4ce20-bd63-4f52-b632-bc0697e2d5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396151519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3396151519
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2549008952
Short name T183
Test name
Test status
Simulation time 590135396855 ps
CPU time 513.91 seconds
Started Aug 16 06:27:26 PM PDT 24
Finished Aug 16 06:36:00 PM PDT 24
Peak memory 191752 kb
Host smart-1fb14af9-b52d-4347-8929-1655afc20a1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549008952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2549008952
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2506910834
Short name T361
Test name
Test status
Simulation time 123016447 ps
CPU time 0.7 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:27:55 PM PDT 24
Peak memory 191948 kb
Host smart-98cfd5be-07df-4640-bb31-2a1afeaecef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506910834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2506910834
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3801445104
Short name T222
Test name
Test status
Simulation time 1381258944367 ps
CPU time 712.25 seconds
Started Aug 16 06:27:41 PM PDT 24
Finished Aug 16 06:39:33 PM PDT 24
Peak memory 183572 kb
Host smart-80e04d90-2e9e-4582-92b1-91227c9ceaa8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801445104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3801445104
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.4164972655
Short name T378
Test name
Test status
Simulation time 67779474742 ps
CPU time 59.11 seconds
Started Aug 16 06:27:24 PM PDT 24
Finished Aug 16 06:28:23 PM PDT 24
Peak memory 183564 kb
Host smart-946f0e9a-5178-40da-980a-5f24188097f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164972655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.4164972655
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.616529823
Short name T406
Test name
Test status
Simulation time 36834018 ps
CPU time 0.57 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:27:53 PM PDT 24
Peak memory 183260 kb
Host smart-019438de-a70d-4627-9f5c-4f29ddf00b0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616529823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
616529823
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2666934017
Short name T354
Test name
Test status
Simulation time 111824413927 ps
CPU time 75.23 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:29:09 PM PDT 24
Peak memory 183492 kb
Host smart-0e383eb3-2d90-4730-b2be-90f39dc560b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666934017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2666934017
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1051346182
Short name T440
Test name
Test status
Simulation time 426453870 ps
CPU time 4.33 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:27:58 PM PDT 24
Peak memory 183412 kb
Host smart-def3eda0-301b-4cf5-aeb8-8ff330df0d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051346182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1051346182
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1497515674
Short name T213
Test name
Test status
Simulation time 1201161132269 ps
CPU time 2705.7 seconds
Started Aug 16 06:27:57 PM PDT 24
Finished Aug 16 07:13:03 PM PDT 24
Peak memory 191812 kb
Host smart-ee2c6f16-5c9a-47e7-8b95-a1f123f76252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497515674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1497515674
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.805887944
Short name T237
Test name
Test status
Simulation time 6662322503 ps
CPU time 12.32 seconds
Started Aug 16 06:27:34 PM PDT 24
Finished Aug 16 06:27:46 PM PDT 24
Peak memory 183616 kb
Host smart-8bf033cc-9e41-4ef1-b6f7-eb0f40b60d6b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805887944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.805887944
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.230136381
Short name T373
Test name
Test status
Simulation time 179993491988 ps
CPU time 59.91 seconds
Started Aug 16 06:27:55 PM PDT 24
Finished Aug 16 06:28:55 PM PDT 24
Peak memory 183620 kb
Host smart-4ecbc45f-0806-4536-8130-039382970036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230136381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.230136381
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3007306181
Short name T334
Test name
Test status
Simulation time 135948335722 ps
CPU time 135.79 seconds
Started Aug 16 06:27:35 PM PDT 24
Finished Aug 16 06:29:51 PM PDT 24
Peak memory 194988 kb
Host smart-24ef5918-31e7-4c17-b766-cf88b27e82ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007306181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3007306181
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1400103358
Short name T412
Test name
Test status
Simulation time 2023075602881 ps
CPU time 736.16 seconds
Started Aug 16 06:27:58 PM PDT 24
Finished Aug 16 06:40:14 PM PDT 24
Peak memory 191760 kb
Host smart-d5ae39fb-0697-477c-9d3d-44a06ae22005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400103358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1400103358
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1691670258
Short name T264
Test name
Test status
Simulation time 334804134036 ps
CPU time 520.9 seconds
Started Aug 16 06:27:51 PM PDT 24
Finished Aug 16 06:36:33 PM PDT 24
Peak memory 183552 kb
Host smart-a82ab598-cb9c-4df4-a986-2666f43d86ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691670258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1691670258
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3659290641
Short name T448
Test name
Test status
Simulation time 195960883680 ps
CPU time 77.92 seconds
Started Aug 16 06:27:47 PM PDT 24
Finished Aug 16 06:29:05 PM PDT 24
Peak memory 183540 kb
Host smart-c1f00cb7-96d6-48ce-bb3e-046e9880a237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659290641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3659290641
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1012474901
Short name T366
Test name
Test status
Simulation time 177746387 ps
CPU time 0.58 seconds
Started Aug 16 06:27:56 PM PDT 24
Finished Aug 16 06:27:57 PM PDT 24
Peak memory 183248 kb
Host smart-65ab9c62-cd35-47df-9020-d3129f0ef4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012474901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1012474901
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3937456185
Short name T435
Test name
Test status
Simulation time 256428934118 ps
CPU time 210.45 seconds
Started Aug 16 06:27:58 PM PDT 24
Finished Aug 16 06:31:28 PM PDT 24
Peak memory 183548 kb
Host smart-ad63e64a-094f-491d-8595-2da2046e03ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937456185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3937456185
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2480978690
Short name T405
Test name
Test status
Simulation time 193865244318 ps
CPU time 286.6 seconds
Started Aug 16 06:27:35 PM PDT 24
Finished Aug 16 06:32:22 PM PDT 24
Peak memory 183600 kb
Host smart-f5d28cad-1f35-4007-a1e1-7329b2c3aa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480978690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2480978690
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1121387902
Short name T294
Test name
Test status
Simulation time 184567039498 ps
CPU time 375.1 seconds
Started Aug 16 06:27:56 PM PDT 24
Finished Aug 16 06:34:11 PM PDT 24
Peak memory 191780 kb
Host smart-a11b748f-8f83-412a-8ad6-e2dfa140021e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121387902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1121387902
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.4200178104
Short name T44
Test name
Test status
Simulation time 179319202095 ps
CPU time 166.86 seconds
Started Aug 16 06:28:00 PM PDT 24
Finished Aug 16 06:30:47 PM PDT 24
Peak memory 183592 kb
Host smart-e845aa99-d7f1-4bc5-8ee4-c62aeaaf9976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200178104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.4200178104
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3511066793
Short name T224
Test name
Test status
Simulation time 336742148070 ps
CPU time 782.31 seconds
Started Aug 16 06:27:33 PM PDT 24
Finished Aug 16 06:40:36 PM PDT 24
Peak memory 191784 kb
Host smart-349102c8-1f10-4303-ae92-979fa25515fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511066793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3511066793
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3970426759
Short name T369
Test name
Test status
Simulation time 3287989896 ps
CPU time 5.24 seconds
Started Aug 16 06:27:49 PM PDT 24
Finished Aug 16 06:27:54 PM PDT 24
Peak memory 183524 kb
Host smart-643f0b19-e38a-4431-a5a5-3177f4208c37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970426759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3970426759
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3287257670
Short name T367
Test name
Test status
Simulation time 330936451958 ps
CPU time 138.56 seconds
Started Aug 16 06:27:56 PM PDT 24
Finished Aug 16 06:30:14 PM PDT 24
Peak memory 183588 kb
Host smart-cb658d65-ab7d-4b7c-bf9a-ae99db041372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287257670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3287257670
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1077256251
Short name T389
Test name
Test status
Simulation time 324069985989 ps
CPU time 149.26 seconds
Started Aug 16 06:27:34 PM PDT 24
Finished Aug 16 06:30:04 PM PDT 24
Peak memory 183552 kb
Host smart-e47cf81e-72a8-47a0-8299-39701fafd3e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077256251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1077256251
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.23167165
Short name T368
Test name
Test status
Simulation time 277601728367 ps
CPU time 95.34 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:29:30 PM PDT 24
Peak memory 183528 kb
Host smart-36d4184f-8724-4f87-8046-f42a110a12d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23167165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.23167165
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3039140172
Short name T382
Test name
Test status
Simulation time 51222612523 ps
CPU time 18.58 seconds
Started Aug 16 06:27:55 PM PDT 24
Finished Aug 16 06:28:14 PM PDT 24
Peak memory 183520 kb
Host smart-b60aea98-cad9-4a2a-ae53-0a3e6d0a8890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039140172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3039140172
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2492974504
Short name T322
Test name
Test status
Simulation time 331255498977 ps
CPU time 125.97 seconds
Started Aug 16 06:27:49 PM PDT 24
Finished Aug 16 06:29:55 PM PDT 24
Peak memory 191700 kb
Host smart-1408f105-bef2-4638-ab1f-4697c40da2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492974504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2492974504
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3912897402
Short name T347
Test name
Test status
Simulation time 35074030 ps
CPU time 0.62 seconds
Started Aug 16 06:27:48 PM PDT 24
Finished Aug 16 06:27:49 PM PDT 24
Peak memory 183244 kb
Host smart-6de6a97e-1574-4cd5-9c84-332eb924a447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912897402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3912897402
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2849781791
Short name T40
Test name
Test status
Simulation time 19627031681 ps
CPU time 11.31 seconds
Started Aug 16 06:27:35 PM PDT 24
Finished Aug 16 06:27:46 PM PDT 24
Peak memory 183588 kb
Host smart-278503e0-acae-4089-b43b-5b5808c1124c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849781791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2849781791
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3180504412
Short name T436
Test name
Test status
Simulation time 7252342125 ps
CPU time 12.05 seconds
Started Aug 16 06:27:36 PM PDT 24
Finished Aug 16 06:27:49 PM PDT 24
Peak memory 183372 kb
Host smart-9676668a-cd22-4d6b-bff6-4e6de7004bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180504412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3180504412
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3708034672
Short name T253
Test name
Test status
Simulation time 23630112107 ps
CPU time 252.27 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:32:05 PM PDT 24
Peak memory 191744 kb
Host smart-5fbbc953-acc7-492f-96da-50095847b489
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708034672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3708034672
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3523761148
Short name T332
Test name
Test status
Simulation time 44664454928 ps
CPU time 80.31 seconds
Started Aug 16 06:27:35 PM PDT 24
Finished Aug 16 06:28:55 PM PDT 24
Peak memory 191768 kb
Host smart-00076d1c-588a-4dc8-ad43-3bd48a887663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523761148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3523761148
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.4140141071
Short name T67
Test name
Test status
Simulation time 105557261654 ps
CPU time 104.22 seconds
Started Aug 16 06:27:33 PM PDT 24
Finished Aug 16 06:29:18 PM PDT 24
Peak memory 191768 kb
Host smart-223a6d5d-9a9a-4048-9a7b-75eddc3ab982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140141071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.4140141071
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.898915633
Short name T295
Test name
Test status
Simulation time 2851657869768 ps
CPU time 1368.06 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:50:41 PM PDT 24
Peak memory 183568 kb
Host smart-1ff7dcf2-8495-4e7a-97ec-8444d61b8111
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898915633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.898915633
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1661076019
Short name T71
Test name
Test status
Simulation time 4033730845 ps
CPU time 6.56 seconds
Started Aug 16 06:27:55 PM PDT 24
Finished Aug 16 06:28:02 PM PDT 24
Peak memory 183392 kb
Host smart-36ed1433-d193-43d9-88f9-a131efb524d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661076019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1661076019
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2708392343
Short name T449
Test name
Test status
Simulation time 45475868336 ps
CPU time 439.72 seconds
Started Aug 16 06:27:50 PM PDT 24
Finished Aug 16 06:35:10 PM PDT 24
Peak memory 183564 kb
Host smart-74df18a0-7980-407f-8802-e016e976a9f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708392343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2708392343
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1962352061
Short name T340
Test name
Test status
Simulation time 81061532552 ps
CPU time 145.96 seconds
Started Aug 16 06:27:59 PM PDT 24
Finished Aug 16 06:30:25 PM PDT 24
Peak memory 195660 kb
Host smart-d3cdd55d-9f10-4eed-b559-4dddcfcf9040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962352061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1962352061
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.546856200
Short name T383
Test name
Test status
Simulation time 476851212 ps
CPU time 1.37 seconds
Started Aug 16 06:27:13 PM PDT 24
Finished Aug 16 06:27:15 PM PDT 24
Peak memory 183240 kb
Host smart-8d999e9d-d70f-4091-a699-3de197d7a41b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546856200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.546856200
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2535771466
Short name T357
Test name
Test status
Simulation time 182619755393 ps
CPU time 118.15 seconds
Started Aug 16 06:27:27 PM PDT 24
Finished Aug 16 06:29:25 PM PDT 24
Peak memory 183568 kb
Host smart-1ba24dff-0953-46d5-a814-a0187b220278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535771466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2535771466
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.3877109500
Short name T172
Test name
Test status
Simulation time 373385988261 ps
CPU time 419.82 seconds
Started Aug 16 06:27:38 PM PDT 24
Finished Aug 16 06:34:38 PM PDT 24
Peak memory 191764 kb
Host smart-8d9272c0-3877-4fb0-8cae-1facdc802e7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877109500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3877109500
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.539155298
Short name T15
Test name
Test status
Simulation time 318684292 ps
CPU time 0.89 seconds
Started Aug 16 06:27:40 PM PDT 24
Finished Aug 16 06:27:41 PM PDT 24
Peak memory 215116 kb
Host smart-a3139444-45b0-4c7c-9631-e573641ce050
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539155298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.539155298
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.4111832348
Short name T388
Test name
Test status
Simulation time 240055757247 ps
CPU time 93.16 seconds
Started Aug 16 06:27:13 PM PDT 24
Finished Aug 16 06:28:46 PM PDT 24
Peak memory 183592 kb
Host smart-b42bea13-3790-48bf-9188-87c1cc7fa07e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111832348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
4111832348
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3826003603
Short name T305
Test name
Test status
Simulation time 522990569873 ps
CPU time 496.61 seconds
Started Aug 16 06:27:37 PM PDT 24
Finished Aug 16 06:35:53 PM PDT 24
Peak memory 183552 kb
Host smart-18e8166e-0823-4407-afb8-e76bec5a9b53
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826003603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3826003603
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.722789576
Short name T5
Test name
Test status
Simulation time 33236055810 ps
CPU time 25.75 seconds
Started Aug 16 06:27:33 PM PDT 24
Finished Aug 16 06:27:59 PM PDT 24
Peak memory 183584 kb
Host smart-40a3f738-93d0-4b88-900d-64c7962ae550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722789576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.722789576
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.148659781
Short name T385
Test name
Test status
Simulation time 191430527 ps
CPU time 1.68 seconds
Started Aug 16 06:27:34 PM PDT 24
Finished Aug 16 06:27:36 PM PDT 24
Peak memory 183476 kb
Host smart-3fb4f793-96e9-4298-9646-8771c75047cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148659781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.148659781
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2125179726
Short name T106
Test name
Test status
Simulation time 60458948581 ps
CPU time 59.77 seconds
Started Aug 16 06:27:52 PM PDT 24
Finished Aug 16 06:28:51 PM PDT 24
Peak memory 183596 kb
Host smart-6b49c27e-33ca-417a-bb23-7eb9528aa3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125179726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2125179726
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1692125560
Short name T437
Test name
Test status
Simulation time 82270055527 ps
CPU time 65.66 seconds
Started Aug 16 06:27:57 PM PDT 24
Finished Aug 16 06:29:03 PM PDT 24
Peak memory 183560 kb
Host smart-5fb4f603-5b24-48e4-8735-f0eca221c55b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692125560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1692125560
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1913903723
Short name T416
Test name
Test status
Simulation time 205365765104 ps
CPU time 322.91 seconds
Started Aug 16 06:27:34 PM PDT 24
Finished Aug 16 06:32:57 PM PDT 24
Peak memory 183556 kb
Host smart-dc851706-3d7f-4b6c-b8fa-934911a9e8fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913903723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1913903723
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3538969853
Short name T395
Test name
Test status
Simulation time 48502647485 ps
CPU time 70.14 seconds
Started Aug 16 06:27:33 PM PDT 24
Finished Aug 16 06:28:43 PM PDT 24
Peak memory 183488 kb
Host smart-fbd4e1a5-eb1e-4f06-9d30-a91085afb950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538969853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3538969853
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1069459479
Short name T402
Test name
Test status
Simulation time 105263973384 ps
CPU time 51.21 seconds
Started Aug 16 06:27:51 PM PDT 24
Finished Aug 16 06:28:43 PM PDT 24
Peak memory 191728 kb
Host smart-9529aea4-3a58-4b15-b062-45e60d1805f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069459479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1069459479
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.4025850921
Short name T205
Test name
Test status
Simulation time 67759793349 ps
CPU time 104.45 seconds
Started Aug 16 06:27:52 PM PDT 24
Finished Aug 16 06:29:37 PM PDT 24
Peak memory 183560 kb
Host smart-f1a84a72-192a-4cf5-8738-1a8064ca76f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025850921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.4025850921
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3564838388
Short name T17
Test name
Test status
Simulation time 691503377406 ps
CPU time 305.59 seconds
Started Aug 16 06:27:35 PM PDT 24
Finished Aug 16 06:32:41 PM PDT 24
Peak memory 183588 kb
Host smart-2dccfc6b-17ee-40a3-842c-f5e7d2eea1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564838388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3564838388
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.777730194
Short name T312
Test name
Test status
Simulation time 56336837643 ps
CPU time 220.71 seconds
Started Aug 16 06:27:36 PM PDT 24
Finished Aug 16 06:31:17 PM PDT 24
Peak memory 191792 kb
Host smart-ab803610-1ee3-4cea-adf0-ecb7809f1274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777730194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.777730194
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.580294284
Short name T374
Test name
Test status
Simulation time 582124326 ps
CPU time 0.8 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:27:54 PM PDT 24
Peak memory 183260 kb
Host smart-5ab2186d-24e5-4c9e-98e6-5302226f6ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580294284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.580294284
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.1513114989
Short name T10
Test name
Test status
Simulation time 3484108185 ps
CPU time 12.99 seconds
Started Aug 16 06:27:34 PM PDT 24
Finished Aug 16 06:27:47 PM PDT 24
Peak memory 198384 kb
Host smart-1919018b-944d-45ad-80a8-7e81747d1d7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513114989 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.1513114989
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.322622376
Short name T166
Test name
Test status
Simulation time 928282147163 ps
CPU time 463.1 seconds
Started Aug 16 06:27:58 PM PDT 24
Finished Aug 16 06:35:41 PM PDT 24
Peak memory 183576 kb
Host smart-70421e77-b25f-4345-bf0b-02ab366c9e48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322622376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.322622376
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3273767388
Short name T409
Test name
Test status
Simulation time 101421086546 ps
CPU time 158.96 seconds
Started Aug 16 06:27:55 PM PDT 24
Finished Aug 16 06:30:34 PM PDT 24
Peak memory 183492 kb
Host smart-49d880c0-de1e-46fc-be26-98c2fb70434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273767388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3273767388
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1952942935
Short name T408
Test name
Test status
Simulation time 400532943 ps
CPU time 1.05 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:28:03 PM PDT 24
Peak memory 183240 kb
Host smart-a8cec3c9-9d36-4468-ad39-96c6e6672362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952942935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1952942935
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1452009581
Short name T344
Test name
Test status
Simulation time 26234197763 ps
CPU time 35.09 seconds
Started Aug 16 06:28:05 PM PDT 24
Finished Aug 16 06:28:40 PM PDT 24
Peak memory 183568 kb
Host smart-95a2c48b-cb06-4051-b024-81c178a5ef53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452009581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1452009581
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.2684899739
Short name T441
Test name
Test status
Simulation time 5943055015 ps
CPU time 22.49 seconds
Started Aug 16 06:27:58 PM PDT 24
Finished Aug 16 06:28:20 PM PDT 24
Peak memory 195272 kb
Host smart-2757b10e-a5f8-4aa6-813e-b63bf09d3b40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684899739 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.2684899739
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1994227721
Short name T330
Test name
Test status
Simulation time 337267342211 ps
CPU time 319.47 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:33:13 PM PDT 24
Peak memory 183500 kb
Host smart-a1f953e9-edfb-44c4-8ad5-aafb30f45e34
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994227721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1994227721
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3600359774
Short name T421
Test name
Test status
Simulation time 138037009499 ps
CPU time 209.16 seconds
Started Aug 16 06:27:42 PM PDT 24
Finished Aug 16 06:31:11 PM PDT 24
Peak memory 183496 kb
Host smart-c4e0bab9-1fd5-4085-82c1-75b562571bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600359774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3600359774
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.781932158
Short name T20
Test name
Test status
Simulation time 1127952434986 ps
CPU time 1134.47 seconds
Started Aug 16 06:27:58 PM PDT 24
Finished Aug 16 06:46:53 PM PDT 24
Peak memory 191768 kb
Host smart-2fba5397-27b7-422a-96ea-13778fd866cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781932158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.781932158
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1095546296
Short name T355
Test name
Test status
Simulation time 6509993057 ps
CPU time 11.78 seconds
Started Aug 16 06:27:58 PM PDT 24
Finished Aug 16 06:28:10 PM PDT 24
Peak memory 183568 kb
Host smart-910ecdb8-93d5-4b27-a1eb-2ea22417dd2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095546296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1095546296
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3013135177
Short name T410
Test name
Test status
Simulation time 675256097878 ps
CPU time 165.58 seconds
Started Aug 16 06:27:39 PM PDT 24
Finished Aug 16 06:30:25 PM PDT 24
Peak memory 183560 kb
Host smart-75b1517e-8305-4884-9b75-0ad5ef762dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013135177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3013135177
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.884901989
Short name T189
Test name
Test status
Simulation time 76069947255 ps
CPU time 111.48 seconds
Started Aug 16 06:27:42 PM PDT 24
Finished Aug 16 06:29:34 PM PDT 24
Peak memory 183632 kb
Host smart-0dbe306f-a7e7-4cec-ac28-f273ccbc6adc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884901989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.884901989
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2667063464
Short name T345
Test name
Test status
Simulation time 501618582318 ps
CPU time 232.78 seconds
Started Aug 16 06:27:59 PM PDT 24
Finished Aug 16 06:31:52 PM PDT 24
Peak memory 183556 kb
Host smart-158aa222-becd-4ffe-91ef-40eded1a51b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667063464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2667063464
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.486108249
Short name T133
Test name
Test status
Simulation time 211601734741 ps
CPU time 133.38 seconds
Started Aug 16 06:27:57 PM PDT 24
Finished Aug 16 06:30:10 PM PDT 24
Peak memory 194152 kb
Host smart-0fc8729d-6de6-4fe2-ac69-c7fadf6e4a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486108249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.486108249
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1999027543
Short name T452
Test name
Test status
Simulation time 37898868883 ps
CPU time 63.8 seconds
Started Aug 16 06:27:40 PM PDT 24
Finished Aug 16 06:28:44 PM PDT 24
Peak memory 195096 kb
Host smart-62a57dd1-ad85-4fd6-af2f-f9c403ead3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999027543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1999027543
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.1893493147
Short name T33
Test name
Test status
Simulation time 1663311140 ps
CPU time 14.95 seconds
Started Aug 16 06:27:59 PM PDT 24
Finished Aug 16 06:28:14 PM PDT 24
Peak memory 194148 kb
Host smart-ea4be54c-1734-4c77-abe8-3b68354f56c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893493147 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.1893493147
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1626533106
Short name T167
Test name
Test status
Simulation time 5756616182 ps
CPU time 9.9 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:28:03 PM PDT 24
Peak memory 183600 kb
Host smart-d8c1c318-4716-4ce4-9a8d-d92750a35c90
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626533106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1626533106
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.388179413
Short name T349
Test name
Test status
Simulation time 307108943576 ps
CPU time 115.28 seconds
Started Aug 16 06:27:59 PM PDT 24
Finished Aug 16 06:29:54 PM PDT 24
Peak memory 183496 kb
Host smart-1aea1eeb-8a96-431d-97ba-1b56ec063582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388179413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.388179413
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2931990741
Short name T144
Test name
Test status
Simulation time 175811409181 ps
CPU time 545.62 seconds
Started Aug 16 06:27:56 PM PDT 24
Finished Aug 16 06:37:02 PM PDT 24
Peak memory 191756 kb
Host smart-5768f88e-c3ab-4137-8056-58068ca2a444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931990741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2931990741
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.2106270135
Short name T32
Test name
Test status
Simulation time 10746229231 ps
CPU time 23.16 seconds
Started Aug 16 06:27:42 PM PDT 24
Finished Aug 16 06:28:05 PM PDT 24
Peak memory 198188 kb
Host smart-e85bdbee-d85c-4ec1-a829-cc9bc621c044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106270135 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.2106270135
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.894335080
Short name T52
Test name
Test status
Simulation time 86319411208 ps
CPU time 82.05 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:29:15 PM PDT 24
Peak memory 183580 kb
Host smart-931a5946-df94-4273-917b-f1b27af27a76
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894335080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.894335080
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2636732899
Short name T399
Test name
Test status
Simulation time 112722484915 ps
CPU time 33.7 seconds
Started Aug 16 06:27:43 PM PDT 24
Finished Aug 16 06:28:17 PM PDT 24
Peak memory 183584 kb
Host smart-a5e8cc61-b3d0-479b-aec5-9d98f682c557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636732899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2636732899
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.130976106
Short name T156
Test name
Test status
Simulation time 290881730465 ps
CPU time 289.78 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:32:44 PM PDT 24
Peak memory 191732 kb
Host smart-614d6eb2-fe5e-4685-a948-291239ce6510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130976106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.130976106
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.3178586563
Short name T34
Test name
Test status
Simulation time 9651641360 ps
CPU time 13.9 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:28:07 PM PDT 24
Peak memory 198348 kb
Host smart-1459591f-4e82-41da-870a-b6db8802e7d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178586563 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.3178586563
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1007664066
Short name T308
Test name
Test status
Simulation time 4007962761296 ps
CPU time 2391.79 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 07:07:46 PM PDT 24
Peak memory 183476 kb
Host smart-1005ca32-a4bd-4ed0-b12d-ce512232be87
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007664066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1007664066
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.448248447
Short name T411
Test name
Test status
Simulation time 280060342603 ps
CPU time 250.72 seconds
Started Aug 16 06:28:00 PM PDT 24
Finished Aug 16 06:32:11 PM PDT 24
Peak memory 183556 kb
Host smart-119538c5-aaa9-4e26-8cb0-8537e2ed3784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448248447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.448248447
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1664598943
Short name T279
Test name
Test status
Simulation time 21544255662 ps
CPU time 30.42 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:28:34 PM PDT 24
Peak memory 183320 kb
Host smart-458606a4-20fb-4667-8114-db5389eb3cae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664598943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1664598943
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.4202314545
Short name T201
Test name
Test status
Simulation time 21758391233 ps
CPU time 18.59 seconds
Started Aug 16 06:27:51 PM PDT 24
Finished Aug 16 06:28:09 PM PDT 24
Peak memory 183560 kb
Host smart-bd4680cd-c805-42b7-93a0-29f438e9e282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202314545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.4202314545
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3904871983
Short name T363
Test name
Test status
Simulation time 35610157 ps
CPU time 0.55 seconds
Started Aug 16 06:27:50 PM PDT 24
Finished Aug 16 06:27:50 PM PDT 24
Peak memory 182928 kb
Host smart-fd518043-0576-4a4f-9f79-2c509d58fc96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904871983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3904871983
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.2220493150
Short name T37
Test name
Test status
Simulation time 5885236832 ps
CPU time 33.07 seconds
Started Aug 16 06:27:59 PM PDT 24
Finished Aug 16 06:28:32 PM PDT 24
Peak memory 198280 kb
Host smart-7a04392c-2c43-4977-808d-0a0e6a00031e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220493150 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.2220493150
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2503047502
Short name T379
Test name
Test status
Simulation time 29852486663 ps
CPU time 16.62 seconds
Started Aug 16 06:27:52 PM PDT 24
Finished Aug 16 06:28:09 PM PDT 24
Peak memory 183552 kb
Host smart-2faa3f6f-f30c-4630-a3a5-fd3aa4487c44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503047502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2503047502
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3166468251
Short name T426
Test name
Test status
Simulation time 138350702541 ps
CPU time 196.02 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:31:10 PM PDT 24
Peak memory 183520 kb
Host smart-a646b2c8-8020-41b2-a088-8b5baa72f248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166468251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3166468251
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1491929422
Short name T414
Test name
Test status
Simulation time 668398859 ps
CPU time 2.22 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:27:57 PM PDT 24
Peak memory 183444 kb
Host smart-03e4448a-97fe-4cff-b633-bade723f3a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491929422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1491929422
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3703067005
Short name T417
Test name
Test status
Simulation time 1158038146842 ps
CPU time 355.64 seconds
Started Aug 16 06:27:25 PM PDT 24
Finished Aug 16 06:33:21 PM PDT 24
Peak memory 183544 kb
Host smart-1c9a04b2-260f-425f-861d-012719493e9f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703067005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3703067005
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.991388501
Short name T365
Test name
Test status
Simulation time 80409975411 ps
CPU time 104.65 seconds
Started Aug 16 06:27:17 PM PDT 24
Finished Aug 16 06:29:02 PM PDT 24
Peak memory 183468 kb
Host smart-ba262e42-12bb-41d3-aa17-9ac56752154e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991388501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.991388501
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3114309678
Short name T155
Test name
Test status
Simulation time 154055193657 ps
CPU time 36 seconds
Started Aug 16 06:27:13 PM PDT 24
Finished Aug 16 06:27:50 PM PDT 24
Peak memory 191780 kb
Host smart-d78bc183-bc6a-46fa-8cce-49536caad097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114309678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3114309678
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.692427688
Short name T12
Test name
Test status
Simulation time 81839506 ps
CPU time 0.86 seconds
Started Aug 16 06:27:16 PM PDT 24
Finished Aug 16 06:27:17 PM PDT 24
Peak memory 214724 kb
Host smart-ffecb0e9-4a9e-41ef-9a73-6e24d8906194
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692427688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.692427688
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3270746929
Short name T447
Test name
Test status
Simulation time 172295953 ps
CPU time 0.57 seconds
Started Aug 16 06:27:18 PM PDT 24
Finished Aug 16 06:27:19 PM PDT 24
Peak memory 183260 kb
Host smart-423366a8-a4bc-47cd-904f-ddb5d569b6a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270746929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3270746929
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.863047314
Short name T238
Test name
Test status
Simulation time 112863058249 ps
CPU time 103.24 seconds
Started Aug 16 06:28:04 PM PDT 24
Finished Aug 16 06:29:47 PM PDT 24
Peak memory 183576 kb
Host smart-3452c308-8f10-4a6d-9e6c-356fae467f1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863047314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.863047314
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1509400012
Short name T442
Test name
Test status
Simulation time 273311558885 ps
CPU time 151.85 seconds
Started Aug 16 06:27:51 PM PDT 24
Finished Aug 16 06:30:23 PM PDT 24
Peak memory 183512 kb
Host smart-e5d6615c-bffd-40e2-aa66-87880ee940e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509400012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1509400012
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3237701745
Short name T443
Test name
Test status
Simulation time 21959466872 ps
CPU time 25.08 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:28:33 PM PDT 24
Peak memory 193616 kb
Host smart-51f6b260-a884-4759-a13a-bc93fc15d4d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237701745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3237701745
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3759408922
Short name T280
Test name
Test status
Simulation time 3259408522 ps
CPU time 2.27 seconds
Started Aug 16 06:27:52 PM PDT 24
Finished Aug 16 06:27:55 PM PDT 24
Peak memory 183480 kb
Host smart-60ab5228-4388-40f9-806b-f2b2a8154d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759408922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3759408922
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3780342645
Short name T59
Test name
Test status
Simulation time 168174188 ps
CPU time 0.64 seconds
Started Aug 16 06:28:00 PM PDT 24
Finished Aug 16 06:28:00 PM PDT 24
Peak memory 183260 kb
Host smart-27134f88-7c18-43ea-b477-35fe5ce3d346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780342645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3780342645
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.122003819
Short name T446
Test name
Test status
Simulation time 21569059553 ps
CPU time 60.73 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:28:55 PM PDT 24
Peak memory 198272 kb
Host smart-95faea9d-06d6-4d44-a3a8-7337b28bd84b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122003819 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.122003819
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2309982832
Short name T43
Test name
Test status
Simulation time 1919925566 ps
CPU time 3.91 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:28:06 PM PDT 24
Peak memory 183296 kb
Host smart-cc4c534f-e669-4ece-b0ce-fb538c98b4d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309982832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2309982832
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.538259445
Short name T2
Test name
Test status
Simulation time 29725022106 ps
CPU time 20.56 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:28:14 PM PDT 24
Peak memory 183520 kb
Host smart-fa414777-cf1e-458d-a814-435c7433e115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538259445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.538259445
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2173085562
Short name T391
Test name
Test status
Simulation time 44657225596 ps
CPU time 744.38 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:40:17 PM PDT 24
Peak memory 191688 kb
Host smart-af192eb0-714e-4c8f-87af-a39c6d30f635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173085562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2173085562
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2901067685
Short name T425
Test name
Test status
Simulation time 217454626118 ps
CPU time 163.99 seconds
Started Aug 16 06:27:55 PM PDT 24
Finished Aug 16 06:30:39 PM PDT 24
Peak memory 183552 kb
Host smart-df3c1e70-4c93-4677-9180-cfad75be0866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901067685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2901067685
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3454629451
Short name T346
Test name
Test status
Simulation time 526290820 ps
CPU time 0.77 seconds
Started Aug 16 06:28:07 PM PDT 24
Finished Aug 16 06:28:08 PM PDT 24
Peak memory 191960 kb
Host smart-b03684ed-7d34-4cd1-a152-12da18edba62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454629451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3454629451
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3603370828
Short name T384
Test name
Test status
Simulation time 570034098558 ps
CPU time 233.81 seconds
Started Aug 16 06:27:56 PM PDT 24
Finished Aug 16 06:31:50 PM PDT 24
Peak memory 191760 kb
Host smart-b35b1838-8576-49ee-b1f3-e0bad3ace460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603370828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3603370828
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.4099008293
Short name T18
Test name
Test status
Simulation time 26989777581 ps
CPU time 45.88 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:28:48 PM PDT 24
Peak memory 183520 kb
Host smart-1430c1b5-f886-4e23-8680-6ff5cd8553b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099008293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.4099008293
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3085536591
Short name T3
Test name
Test status
Simulation time 330068044932 ps
CPU time 253.62 seconds
Started Aug 16 06:27:50 PM PDT 24
Finished Aug 16 06:32:04 PM PDT 24
Peak memory 183604 kb
Host smart-baa7b6ce-6aa3-4261-b67e-4bf062ef141e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085536591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3085536591
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3141876886
Short name T202
Test name
Test status
Simulation time 459414272820 ps
CPU time 287.56 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:32:51 PM PDT 24
Peak memory 191744 kb
Host smart-94edb47a-d10b-4192-93f4-784619cd470e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141876886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3141876886
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.441840814
Short name T111
Test name
Test status
Simulation time 43280321695 ps
CPU time 31.27 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:28:24 PM PDT 24
Peak memory 183528 kb
Host smart-116014d7-2599-4a74-a7fc-21967cc1f171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441840814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.441840814
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.482962578
Short name T289
Test name
Test status
Simulation time 461565991246 ps
CPU time 1100.44 seconds
Started Aug 16 06:27:52 PM PDT 24
Finished Aug 16 06:46:12 PM PDT 24
Peak memory 195200 kb
Host smart-3ad8f5f9-2d58-4c59-a41a-433bf6f6ec9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482962578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
482962578
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3192261627
Short name T404
Test name
Test status
Simulation time 261187867751 ps
CPU time 187.68 seconds
Started Aug 16 06:27:56 PM PDT 24
Finished Aug 16 06:31:04 PM PDT 24
Peak memory 183612 kb
Host smart-e76f6625-a71c-4e05-a801-b82e2cdda74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192261627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3192261627
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3727574028
Short name T439
Test name
Test status
Simulation time 272462248507 ps
CPU time 149.6 seconds
Started Aug 16 06:27:57 PM PDT 24
Finished Aug 16 06:30:26 PM PDT 24
Peak memory 191716 kb
Host smart-4cd1d0a8-f36c-4e7f-943a-4bd535bf21d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727574028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3727574028
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3142795766
Short name T319
Test name
Test status
Simulation time 31446305195 ps
CPU time 48.98 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:28:43 PM PDT 24
Peak memory 183568 kb
Host smart-b459b4b4-8e85-4438-bd08-21c55d9f5b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142795766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3142795766
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1212412616
Short name T401
Test name
Test status
Simulation time 116299898794 ps
CPU time 162.28 seconds
Started Aug 16 06:27:50 PM PDT 24
Finished Aug 16 06:30:32 PM PDT 24
Peak memory 183576 kb
Host smart-02026d59-6939-4a72-9733-0a4ca6a96dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212412616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1212412616
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1700229447
Short name T235
Test name
Test status
Simulation time 114365800510 ps
CPU time 189.77 seconds
Started Aug 16 06:28:05 PM PDT 24
Finished Aug 16 06:31:15 PM PDT 24
Peak memory 191752 kb
Host smart-3ea1cfb8-6f24-411d-8781-95905b3071ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700229447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1700229447
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.628539706
Short name T263
Test name
Test status
Simulation time 79853179203 ps
CPU time 125.83 seconds
Started Aug 16 06:28:01 PM PDT 24
Finished Aug 16 06:30:07 PM PDT 24
Peak memory 191768 kb
Host smart-38e47d6e-79d0-4b2c-9917-6c6d4da831ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628539706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.628539706
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1429823531
Short name T242
Test name
Test status
Simulation time 961414760500 ps
CPU time 524.45 seconds
Started Aug 16 06:27:57 PM PDT 24
Finished Aug 16 06:36:42 PM PDT 24
Peak memory 183576 kb
Host smart-0e506af8-cac4-45fa-84d3-a83b406d09bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429823531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1429823531
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.384682194
Short name T352
Test name
Test status
Simulation time 655718830588 ps
CPU time 149.93 seconds
Started Aug 16 06:27:51 PM PDT 24
Finished Aug 16 06:30:22 PM PDT 24
Peak memory 183572 kb
Host smart-94a6d883-483b-4142-9d82-58bc75bbae15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384682194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.384682194
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2986858166
Short name T257
Test name
Test status
Simulation time 152846962170 ps
CPU time 84.5 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:29:19 PM PDT 24
Peak memory 191796 kb
Host smart-0012d1fa-d2b7-45ae-b707-527808382641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986858166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2986858166
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1407183090
Short name T393
Test name
Test status
Simulation time 34333845884 ps
CPU time 55.99 seconds
Started Aug 16 06:28:00 PM PDT 24
Finished Aug 16 06:28:56 PM PDT 24
Peak memory 194896 kb
Host smart-58fb7032-127b-437e-b48e-524115791ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407183090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1407183090
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.633693885
Short name T100
Test name
Test status
Simulation time 1452670882793 ps
CPU time 400.38 seconds
Started Aug 16 06:27:57 PM PDT 24
Finished Aug 16 06:34:38 PM PDT 24
Peak memory 183608 kb
Host smart-8cb71f6f-ce53-4689-833c-807fa12e18a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633693885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.633693885
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_random.451820838
Short name T192
Test name
Test status
Simulation time 103909884883 ps
CPU time 387.44 seconds
Started Aug 16 06:27:53 PM PDT 24
Finished Aug 16 06:34:20 PM PDT 24
Peak memory 191852 kb
Host smart-ee062afc-b680-493a-8eed-2177f4ac824c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451820838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.451820838
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2130439387
Short name T154
Test name
Test status
Simulation time 303024793147 ps
CPU time 249.49 seconds
Started Aug 16 06:27:51 PM PDT 24
Finished Aug 16 06:32:01 PM PDT 24
Peak memory 191708 kb
Host smart-d9956b37-5d98-44e5-a182-b3f50cb6832b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130439387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2130439387
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.991305918
Short name T195
Test name
Test status
Simulation time 312870263553 ps
CPU time 444.52 seconds
Started Aug 16 06:27:57 PM PDT 24
Finished Aug 16 06:35:21 PM PDT 24
Peak memory 183584 kb
Host smart-936fbbb5-df58-46ec-aa58-2a5f5194a3c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991305918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.991305918
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.214609595
Short name T424
Test name
Test status
Simulation time 16869310596 ps
CPU time 12 seconds
Started Aug 16 06:27:58 PM PDT 24
Finished Aug 16 06:28:10 PM PDT 24
Peak memory 183572 kb
Host smart-35f61e1b-f586-4853-ae6c-bcf9b174724b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214609595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.214609595
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3655397567
Short name T128
Test name
Test status
Simulation time 78038565591 ps
CPU time 969.48 seconds
Started Aug 16 06:28:00 PM PDT 24
Finished Aug 16 06:44:09 PM PDT 24
Peak memory 191764 kb
Host smart-653b1cf9-f62f-4b17-a333-0b4fd84111c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655397567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3655397567
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.492620180
Short name T394
Test name
Test status
Simulation time 132885823 ps
CPU time 0.82 seconds
Started Aug 16 06:27:58 PM PDT 24
Finished Aug 16 06:27:59 PM PDT 24
Peak memory 183256 kb
Host smart-944d6988-1964-4ca0-bb47-db534fb7194e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492620180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.492620180
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2721159523
Short name T272
Test name
Test status
Simulation time 355371408991 ps
CPU time 433.33 seconds
Started Aug 16 06:27:57 PM PDT 24
Finished Aug 16 06:35:10 PM PDT 24
Peak memory 191808 kb
Host smart-9ade820a-bcce-4c86-b73a-76455673dd33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721159523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2721159523
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2452584003
Short name T174
Test name
Test status
Simulation time 91531734219 ps
CPU time 45.17 seconds
Started Aug 16 06:28:12 PM PDT 24
Finished Aug 16 06:28:57 PM PDT 24
Peak memory 183588 kb
Host smart-dd4fb56f-7aa8-412d-a28f-8a4a74b123b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452584003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2452584003
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3973193969
Short name T370
Test name
Test status
Simulation time 370819178130 ps
CPU time 160.62 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:30:43 PM PDT 24
Peak memory 183568 kb
Host smart-debc840c-c48d-44d8-abc4-b323dcc39e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973193969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3973193969
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3752194686
Short name T267
Test name
Test status
Simulation time 278124246742 ps
CPU time 2644.18 seconds
Started Aug 16 06:27:55 PM PDT 24
Finished Aug 16 07:12:00 PM PDT 24
Peak memory 191784 kb
Host smart-383abd3c-c00a-4200-8cbc-d5ce257f128c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752194686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3752194686
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3659414880
Short name T240
Test name
Test status
Simulation time 86322168695 ps
CPU time 59.64 seconds
Started Aug 16 06:27:49 PM PDT 24
Finished Aug 16 06:28:49 PM PDT 24
Peak memory 191800 kb
Host smart-1e65d4c1-c2c0-4e58-9239-340b649696c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659414880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3659414880
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.280964625
Short name T278
Test name
Test status
Simulation time 600393449432 ps
CPU time 498.34 seconds
Started Aug 16 06:27:15 PM PDT 24
Finished Aug 16 06:35:34 PM PDT 24
Peak memory 183568 kb
Host smart-946afb89-b52f-4d4f-8dce-2e47bb542419
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280964625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.280964625
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1051054797
Short name T351
Test name
Test status
Simulation time 594414300354 ps
CPU time 218.27 seconds
Started Aug 16 06:27:20 PM PDT 24
Finished Aug 16 06:31:03 PM PDT 24
Peak memory 183580 kb
Host smart-3b96e24c-8c96-41ef-a388-52db2fe09b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051054797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1051054797
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3924633349
Short name T418
Test name
Test status
Simulation time 83339624715 ps
CPU time 72.75 seconds
Started Aug 16 06:27:13 PM PDT 24
Finished Aug 16 06:28:27 PM PDT 24
Peak memory 183564 kb
Host smart-4b2f9b15-0fda-4374-a265-e30c51556f20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924633349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3924633349
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1741917583
Short name T390
Test name
Test status
Simulation time 120675651820 ps
CPU time 46.36 seconds
Started Aug 16 06:27:12 PM PDT 24
Finished Aug 16 06:27:59 PM PDT 24
Peak memory 193740 kb
Host smart-20c1ae15-b7fd-45ab-9e76-1cb00f1749cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741917583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1741917583
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3636052674
Short name T119
Test name
Test status
Simulation time 126995504086 ps
CPU time 691.37 seconds
Started Aug 16 06:27:17 PM PDT 24
Finished Aug 16 06:38:48 PM PDT 24
Peak memory 191852 kb
Host smart-29cc7b83-b59f-4c12-8a4f-8c3cdd300828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636052674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3636052674
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1328601550
Short name T31
Test name
Test status
Simulation time 5445823551 ps
CPU time 60.19 seconds
Started Aug 16 06:27:20 PM PDT 24
Finished Aug 16 06:28:20 PM PDT 24
Peak memory 198204 kb
Host smart-77c9bbf2-d861-4bf8-9efd-32d8b95800c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328601550 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1328601550
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.2110409478
Short name T132
Test name
Test status
Simulation time 1000598315724 ps
CPU time 312.42 seconds
Started Aug 16 06:27:59 PM PDT 24
Finished Aug 16 06:33:11 PM PDT 24
Peak memory 191724 kb
Host smart-fce791c5-e083-4a80-8ffd-dc2b1ecf6454
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110409478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2110409478
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3068801451
Short name T300
Test name
Test status
Simulation time 5890602493 ps
CPU time 9.54 seconds
Started Aug 16 06:28:05 PM PDT 24
Finished Aug 16 06:28:14 PM PDT 24
Peak memory 183612 kb
Host smart-75b6a8f7-c901-492c-b5ce-aaca15ade670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068801451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3068801451
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1841220246
Short name T131
Test name
Test status
Simulation time 646000610241 ps
CPU time 272.37 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:32:27 PM PDT 24
Peak memory 191796 kb
Host smart-581baae9-3ef6-427c-ab65-4456789ed707
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841220246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1841220246
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.441997483
Short name T291
Test name
Test status
Simulation time 206548064407 ps
CPU time 612.73 seconds
Started Aug 16 06:27:59 PM PDT 24
Finished Aug 16 06:38:12 PM PDT 24
Peak memory 191740 kb
Host smart-9c98936f-b1e8-432b-b1db-3a3ad921e8f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441997483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.441997483
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.401797195
Short name T245
Test name
Test status
Simulation time 79097201092 ps
CPU time 1645.55 seconds
Started Aug 16 06:28:05 PM PDT 24
Finished Aug 16 06:55:31 PM PDT 24
Peak memory 191792 kb
Host smart-775dcbdf-9e44-4b7b-aab4-630b9f74818e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401797195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.401797195
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.4109990756
Short name T161
Test name
Test status
Simulation time 53212681927 ps
CPU time 155.62 seconds
Started Aug 16 06:27:59 PM PDT 24
Finished Aug 16 06:30:34 PM PDT 24
Peak memory 191776 kb
Host smart-bb9cb2ac-68a4-441c-89a3-24d0fcce3150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109990756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.4109990756
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2623253890
Short name T177
Test name
Test status
Simulation time 291309640762 ps
CPU time 151.17 seconds
Started Aug 16 06:28:05 PM PDT 24
Finished Aug 16 06:30:36 PM PDT 24
Peak memory 191780 kb
Host smart-80f43229-2998-4b51-89ad-d87d3c742f81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623253890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2623253890
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3991600146
Short name T117
Test name
Test status
Simulation time 189198978427 ps
CPU time 601.05 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:37:56 PM PDT 24
Peak memory 191804 kb
Host smart-c7c58cd2-dec6-4add-b271-9594a45c00c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991600146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3991600146
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3821128360
Short name T271
Test name
Test status
Simulation time 1175955604300 ps
CPU time 1719.73 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:56:43 PM PDT 24
Peak memory 191756 kb
Host smart-03c5ca6f-ce55-4680-9bac-3ec4a80881cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821128360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3821128360
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.889375321
Short name T398
Test name
Test status
Simulation time 1296164034481 ps
CPU time 776.72 seconds
Started Aug 16 06:27:17 PM PDT 24
Finished Aug 16 06:40:14 PM PDT 24
Peak memory 183568 kb
Host smart-70826a3d-50b8-461c-946f-29d0707f284a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889375321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.889375321
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1425366240
Short name T419
Test name
Test status
Simulation time 187024649938 ps
CPU time 61.07 seconds
Started Aug 16 06:27:14 PM PDT 24
Finished Aug 16 06:28:15 PM PDT 24
Peak memory 183508 kb
Host smart-d0701516-fc8c-48b9-940b-454ab34605e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425366240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1425366240
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.1624621083
Short name T219
Test name
Test status
Simulation time 36266101234 ps
CPU time 804.73 seconds
Started Aug 16 06:27:14 PM PDT 24
Finished Aug 16 06:40:39 PM PDT 24
Peak memory 191820 kb
Host smart-8fbd6e88-4ef9-485b-a9a8-ecc6f54199f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624621083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1624621083
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.4292451431
Short name T343
Test name
Test status
Simulation time 159377753 ps
CPU time 0.69 seconds
Started Aug 16 06:27:21 PM PDT 24
Finished Aug 16 06:27:21 PM PDT 24
Peak memory 183252 kb
Host smart-f674cfac-c7da-416b-8480-17f9e8c0a4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292451431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4292451431
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3721659223
Short name T113
Test name
Test status
Simulation time 1414115987772 ps
CPU time 713.96 seconds
Started Aug 16 06:27:16 PM PDT 24
Finished Aug 16 06:39:11 PM PDT 24
Peak memory 191760 kb
Host smart-edfe9af1-52ca-4a7b-b33e-aa59b8340a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721659223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3721659223
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.4184757384
Short name T171
Test name
Test status
Simulation time 298816353641 ps
CPU time 1872.3 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:59:16 PM PDT 24
Peak memory 191796 kb
Host smart-659be811-8b0e-4d2a-b5de-477c739990c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184757384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.4184757384
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3680219467
Short name T239
Test name
Test status
Simulation time 2699742511734 ps
CPU time 943.91 seconds
Started Aug 16 06:28:06 PM PDT 24
Finished Aug 16 06:43:50 PM PDT 24
Peak memory 191740 kb
Host smart-e17eede2-2261-459a-a051-4996e9a25222
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680219467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3680219467
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2896985720
Short name T55
Test name
Test status
Simulation time 80420439709 ps
CPU time 78.21 seconds
Started Aug 16 06:27:55 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 191772 kb
Host smart-02cda07d-3828-42c5-961a-f2f47e291ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896985720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2896985720
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2871691485
Short name T118
Test name
Test status
Simulation time 363390443764 ps
CPU time 211.96 seconds
Started Aug 16 06:27:55 PM PDT 24
Finished Aug 16 06:31:27 PM PDT 24
Peak memory 191864 kb
Host smart-f94af22d-3f23-498f-9891-c19ee1f7801e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871691485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2871691485
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1682843609
Short name T6
Test name
Test status
Simulation time 345497535873 ps
CPU time 152.48 seconds
Started Aug 16 06:28:01 PM PDT 24
Finished Aug 16 06:30:33 PM PDT 24
Peak memory 191720 kb
Host smart-c541c881-6809-446e-865f-b339cc9b3aa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682843609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1682843609
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1120883130
Short name T336
Test name
Test status
Simulation time 35238069389 ps
CPU time 20.43 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:28:24 PM PDT 24
Peak memory 191808 kb
Host smart-11d1b4ba-5a4b-49cf-8bd1-9792127eb44a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120883130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1120883130
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1877297317
Short name T130
Test name
Test status
Simulation time 20001430643 ps
CPU time 69.04 seconds
Started Aug 16 06:28:00 PM PDT 24
Finished Aug 16 06:29:09 PM PDT 24
Peak memory 183480 kb
Host smart-848513f4-31cd-47e7-aa07-dc0ae920e119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877297317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1877297317
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.82591444
Short name T218
Test name
Test status
Simulation time 86987571789 ps
CPU time 81.91 seconds
Started Aug 16 06:28:01 PM PDT 24
Finished Aug 16 06:29:23 PM PDT 24
Peak memory 183572 kb
Host smart-def21303-9f46-4b6d-848a-44a5f6e18512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82591444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.82591444
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.847449811
Short name T274
Test name
Test status
Simulation time 55183944820 ps
CPU time 47.84 seconds
Started Aug 16 06:27:20 PM PDT 24
Finished Aug 16 06:28:08 PM PDT 24
Peak memory 183612 kb
Host smart-e0ab90f7-d22b-4a79-acc9-14679094ba3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847449811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.847449811
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3912795269
Short name T397
Test name
Test status
Simulation time 79766021876 ps
CPU time 109.93 seconds
Started Aug 16 06:27:17 PM PDT 24
Finished Aug 16 06:29:07 PM PDT 24
Peak memory 183504 kb
Host smart-4ee9f914-b063-4fa3-a786-261c85d601fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912795269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3912795269
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3032076876
Short name T58
Test name
Test status
Simulation time 180500640640 ps
CPU time 315.77 seconds
Started Aug 16 06:27:20 PM PDT 24
Finished Aug 16 06:32:36 PM PDT 24
Peak memory 191800 kb
Host smart-752b5584-8427-43f3-a04f-c7780e4e6f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032076876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3032076876
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/70.rv_timer_random.913023427
Short name T432
Test name
Test status
Simulation time 1089653816317 ps
CPU time 272.67 seconds
Started Aug 16 06:28:04 PM PDT 24
Finished Aug 16 06:32:40 PM PDT 24
Peak memory 191804 kb
Host smart-1d7589e9-9425-4c1c-8bf5-79c543b5200d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913023427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.913023427
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.925624219
Short name T268
Test name
Test status
Simulation time 46002622649 ps
CPU time 37.09 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:28:40 PM PDT 24
Peak memory 191772 kb
Host smart-e77e1bda-adc6-47c2-98fb-1a8c85fe4ffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925624219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.925624219
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3808044991
Short name T200
Test name
Test status
Simulation time 787463034352 ps
CPU time 591.8 seconds
Started Aug 16 06:27:57 PM PDT 24
Finished Aug 16 06:37:49 PM PDT 24
Peak memory 191804 kb
Host smart-80de494d-7c94-4fad-af39-4ca880dfce25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808044991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3808044991
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2477380590
Short name T141
Test name
Test status
Simulation time 167206659284 ps
CPU time 75.56 seconds
Started Aug 16 06:27:58 PM PDT 24
Finished Aug 16 06:29:14 PM PDT 24
Peak memory 191776 kb
Host smart-e2b93c1b-e7ae-4a27-818d-d91cf9151b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477380590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2477380590
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1325396442
Short name T420
Test name
Test status
Simulation time 161058577012 ps
CPU time 175.57 seconds
Started Aug 16 06:27:56 PM PDT 24
Finished Aug 16 06:30:52 PM PDT 24
Peak memory 191780 kb
Host smart-4e0772fc-589e-4d89-8c52-756cea537192
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325396442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1325396442
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.623574440
Short name T381
Test name
Test status
Simulation time 80630459046 ps
CPU time 194.1 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:31:18 PM PDT 24
Peak memory 191796 kb
Host smart-09529902-6b48-46d6-9d96-75415819883c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623574440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.623574440
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3427957376
Short name T185
Test name
Test status
Simulation time 579317223246 ps
CPU time 337.76 seconds
Started Aug 16 06:27:54 PM PDT 24
Finished Aug 16 06:33:32 PM PDT 24
Peak memory 191740 kb
Host smart-80d98c99-c743-44bb-9f8b-9fa30e51e84b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427957376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3427957376
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3731512597
Short name T321
Test name
Test status
Simulation time 460990899094 ps
CPU time 327.26 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:33:29 PM PDT 24
Peak memory 191800 kb
Host smart-f134c2bc-524c-4e86-815b-d71d2609c640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731512597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3731512597
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1453278098
Short name T72
Test name
Test status
Simulation time 125220634236 ps
CPU time 175.03 seconds
Started Aug 16 06:27:30 PM PDT 24
Finished Aug 16 06:30:25 PM PDT 24
Peak memory 183632 kb
Host smart-8f898cb3-467e-4ec7-9bcd-fe2af2d65481
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453278098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1453278098
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3599513375
Short name T415
Test name
Test status
Simulation time 204515638228 ps
CPU time 219.45 seconds
Started Aug 16 06:27:20 PM PDT 24
Finished Aug 16 06:30:59 PM PDT 24
Peak memory 183568 kb
Host smart-ae857928-eb12-48af-905a-fb1d1581f2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599513375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3599513375
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.479742805
Short name T158
Test name
Test status
Simulation time 167189447567 ps
CPU time 392.72 seconds
Started Aug 16 06:27:18 PM PDT 24
Finished Aug 16 06:33:51 PM PDT 24
Peak memory 191864 kb
Host smart-91691e7b-e2cc-428c-98fe-6079e5fcc146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479742805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.479742805
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.339138854
Short name T139
Test name
Test status
Simulation time 138095762699 ps
CPU time 46.78 seconds
Started Aug 16 06:27:20 PM PDT 24
Finished Aug 16 06:28:07 PM PDT 24
Peak memory 191780 kb
Host smart-6389bdf6-ba9e-44ef-ba0c-32e7025225dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339138854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.339138854
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3060243788
Short name T101
Test name
Test status
Simulation time 462799022389 ps
CPU time 86.07 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:29:29 PM PDT 24
Peak memory 183548 kb
Host smart-74f1fa1a-c6c7-4a22-8849-d4f78e53c57e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060243788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3060243788
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1517972954
Short name T70
Test name
Test status
Simulation time 232367522601 ps
CPU time 282.79 seconds
Started Aug 16 06:28:05 PM PDT 24
Finished Aug 16 06:32:48 PM PDT 24
Peak memory 191780 kb
Host smart-5b848ae2-206c-45b9-a362-21459fc10abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517972954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1517972954
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.830604872
Short name T181
Test name
Test status
Simulation time 182571843796 ps
CPU time 326.48 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:33:29 PM PDT 24
Peak memory 191756 kb
Host smart-9c7a43e6-0995-4459-a7cb-2ffce6e1449b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830604872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.830604872
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2319131628
Short name T316
Test name
Test status
Simulation time 98168907082 ps
CPU time 153.7 seconds
Started Aug 16 06:27:59 PM PDT 24
Finished Aug 16 06:30:33 PM PDT 24
Peak memory 195216 kb
Host smart-a737cfd9-443d-4863-97f1-46406b314d91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319131628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2319131628
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1197055032
Short name T265
Test name
Test status
Simulation time 307888711195 ps
CPU time 181.51 seconds
Started Aug 16 06:28:06 PM PDT 24
Finished Aug 16 06:31:07 PM PDT 24
Peak memory 191788 kb
Host smart-55a7b983-5b0c-42ca-b70b-375823297ff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197055032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1197055032
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3570809458
Short name T250
Test name
Test status
Simulation time 246047829231 ps
CPU time 767.81 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:40:50 PM PDT 24
Peak memory 191816 kb
Host smart-6cf3ab6a-e4a2-4226-8daf-3f546c4a75ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570809458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3570809458
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3487171470
Short name T217
Test name
Test status
Simulation time 56281317432 ps
CPU time 573.13 seconds
Started Aug 16 06:28:04 PM PDT 24
Finished Aug 16 06:37:38 PM PDT 24
Peak memory 191800 kb
Host smart-3fc46bd4-c2ec-49b7-89b3-547c1d525096
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487171470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3487171470
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1514743009
Short name T146
Test name
Test status
Simulation time 42571253968 ps
CPU time 70.83 seconds
Started Aug 16 06:27:19 PM PDT 24
Finished Aug 16 06:28:30 PM PDT 24
Peak memory 183584 kb
Host smart-c4f83f3f-c701-4299-b7e8-6e1b32536366
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514743009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1514743009
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.107442926
Short name T362
Test name
Test status
Simulation time 10866452411 ps
CPU time 5.23 seconds
Started Aug 16 06:27:19 PM PDT 24
Finished Aug 16 06:27:24 PM PDT 24
Peak memory 183596 kb
Host smart-3098b35d-153b-4a3c-8e6b-bedd9d1deff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107442926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.107442926
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2728569800
Short name T311
Test name
Test status
Simulation time 101236637224 ps
CPU time 1919.39 seconds
Started Aug 16 06:27:18 PM PDT 24
Finished Aug 16 06:59:17 PM PDT 24
Peak memory 191736 kb
Host smart-bdc95417-c16f-4b06-b3c7-6c626dc05f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728569800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2728569800
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1931236425
Short name T299
Test name
Test status
Simulation time 20803039101 ps
CPU time 86.3 seconds
Started Aug 16 06:27:31 PM PDT 24
Finished Aug 16 06:28:57 PM PDT 24
Peak memory 191776 kb
Host smart-1a4c824b-82a9-4426-9767-ce2298ef7836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931236425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1931236425
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.1637818335
Short name T338
Test name
Test status
Simulation time 37588026959 ps
CPU time 232.5 seconds
Started Aug 16 06:28:02 PM PDT 24
Finished Aug 16 06:31:55 PM PDT 24
Peak memory 192492 kb
Host smart-981774b0-6ba1-468b-8df7-3dbffeb8e53a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637818335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1637818335
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2675050084
Short name T438
Test name
Test status
Simulation time 175298563979 ps
CPU time 327.44 seconds
Started Aug 16 06:28:05 PM PDT 24
Finished Aug 16 06:33:33 PM PDT 24
Peak memory 183576 kb
Host smart-79e086d7-ba58-46de-9588-051163da4f5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675050084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2675050084
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3151510668
Short name T234
Test name
Test status
Simulation time 21896251838 ps
CPU time 82.98 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:29:26 PM PDT 24
Peak memory 183556 kb
Host smart-02639526-f589-472e-b550-59636a6cebe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151510668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3151510668
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1050562963
Short name T7
Test name
Test status
Simulation time 379475352677 ps
CPU time 875.15 seconds
Started Aug 16 06:27:58 PM PDT 24
Finished Aug 16 06:42:33 PM PDT 24
Peak memory 191800 kb
Host smart-11d73212-69d5-42e9-b28f-ab47f303be6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050562963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1050562963
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1828005721
Short name T255
Test name
Test status
Simulation time 141154282622 ps
CPU time 278.3 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:32:42 PM PDT 24
Peak memory 192900 kb
Host smart-09a95fb4-8d54-4e84-860b-689701be38bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828005721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1828005721
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.708794921
Short name T445
Test name
Test status
Simulation time 245596429204 ps
CPU time 388.71 seconds
Started Aug 16 06:28:00 PM PDT 24
Finished Aug 16 06:34:29 PM PDT 24
Peak memory 191784 kb
Host smart-ddbb1be6-c6e4-4365-9092-41934ebe2d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708794921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.708794921
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3786182406
Short name T317
Test name
Test status
Simulation time 1396662120121 ps
CPU time 1499.84 seconds
Started Aug 16 06:28:03 PM PDT 24
Finished Aug 16 06:53:03 PM PDT 24
Peak memory 191744 kb
Host smart-047200c7-7f7d-4c49-bf23-fa03817d2ab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786182406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3786182406
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2114909261
Short name T157
Test name
Test status
Simulation time 780042291250 ps
CPU time 1300.09 seconds
Started Aug 16 06:28:01 PM PDT 24
Finished Aug 16 06:49:41 PM PDT 24
Peak memory 191764 kb
Host smart-19abdcef-0f7b-439a-b711-318606035ba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114909261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2114909261
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2178279782
Short name T112
Test name
Test status
Simulation time 171820867478 ps
CPU time 271.95 seconds
Started Aug 16 06:28:06 PM PDT 24
Finished Aug 16 06:32:39 PM PDT 24
Peak memory 191780 kb
Host smart-18e5a2d4-3b6b-4a11-bdcc-6a56d5661c90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178279782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2178279782
Directory /workspace/99.rv_timer_random/latest
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