Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.51 99.36 99.04 100.00 100.00 100.00 98.64


Total test records in report: 582
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T511 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1768894338 Aug 17 05:36:09 PM PDT 24 Aug 17 05:36:10 PM PDT 24 93922419 ps
T512 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3295626890 Aug 17 05:36:07 PM PDT 24 Aug 17 05:36:08 PM PDT 24 68167199 ps
T513 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.4263416523 Aug 17 05:36:02 PM PDT 24 Aug 17 05:36:03 PM PDT 24 165232449 ps
T94 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.407368139 Aug 17 05:35:49 PM PDT 24 Aug 17 05:35:50 PM PDT 24 43188659 ps
T514 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2501855287 Aug 17 05:36:02 PM PDT 24 Aug 17 05:36:03 PM PDT 24 123290036 ps
T515 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2790103045 Aug 17 05:35:51 PM PDT 24 Aug 17 05:35:53 PM PDT 24 42522235 ps
T516 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1579972782 Aug 17 05:35:51 PM PDT 24 Aug 17 05:35:52 PM PDT 24 30937410 ps
T517 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1663513322 Aug 17 05:35:54 PM PDT 24 Aug 17 05:35:55 PM PDT 24 15356944 ps
T518 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3022383662 Aug 17 05:36:07 PM PDT 24 Aug 17 05:36:08 PM PDT 24 57624533 ps
T519 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1279439673 Aug 17 05:35:47 PM PDT 24 Aug 17 05:35:49 PM PDT 24 125400807 ps
T520 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4234054490 Aug 17 05:35:51 PM PDT 24 Aug 17 05:35:53 PM PDT 24 115055610 ps
T521 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.848342040 Aug 17 05:35:58 PM PDT 24 Aug 17 05:35:59 PM PDT 24 360647973 ps
T98 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1849080615 Aug 17 05:35:49 PM PDT 24 Aug 17 05:35:51 PM PDT 24 422362409 ps
T95 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.8210081 Aug 17 05:36:14 PM PDT 24 Aug 17 05:36:16 PM PDT 24 377923525 ps
T522 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2687444053 Aug 17 05:36:13 PM PDT 24 Aug 17 05:36:14 PM PDT 24 65453999 ps
T523 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.678767231 Aug 17 05:35:55 PM PDT 24 Aug 17 05:35:58 PM PDT 24 476131485 ps
T86 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.60492879 Aug 17 05:35:54 PM PDT 24 Aug 17 05:35:55 PM PDT 24 57399139 ps
T524 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1203629099 Aug 17 05:35:53 PM PDT 24 Aug 17 05:35:55 PM PDT 24 134655822 ps
T87 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.253208774 Aug 17 05:36:14 PM PDT 24 Aug 17 05:36:14 PM PDT 24 16907535 ps
T525 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1143772087 Aug 17 05:35:59 PM PDT 24 Aug 17 05:36:00 PM PDT 24 62654471 ps
T526 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2441378827 Aug 17 05:35:55 PM PDT 24 Aug 17 05:35:56 PM PDT 24 154980245 ps
T99 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3706927500 Aug 17 05:36:00 PM PDT 24 Aug 17 05:36:01 PM PDT 24 146575130 ps
T527 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1872073003 Aug 17 05:35:51 PM PDT 24 Aug 17 05:35:51 PM PDT 24 77669916 ps
T528 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1135885800 Aug 17 05:36:18 PM PDT 24 Aug 17 05:36:19 PM PDT 24 16485655 ps
T529 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3150957633 Aug 17 05:35:46 PM PDT 24 Aug 17 05:35:47 PM PDT 24 24293239 ps
T530 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3987584877 Aug 17 05:35:52 PM PDT 24 Aug 17 05:35:53 PM PDT 24 20057308 ps
T531 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2102254876 Aug 17 05:35:52 PM PDT 24 Aug 17 05:35:53 PM PDT 24 41148699 ps
T532 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4019434902 Aug 17 05:36:01 PM PDT 24 Aug 17 05:36:02 PM PDT 24 27155172 ps
T533 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2169925718 Aug 17 05:36:10 PM PDT 24 Aug 17 05:36:13 PM PDT 24 469092480 ps
T534 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.592161318 Aug 17 05:36:17 PM PDT 24 Aug 17 05:36:17 PM PDT 24 16623887 ps
T535 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3495997024 Aug 17 05:35:48 PM PDT 24 Aug 17 05:35:48 PM PDT 24 14606141 ps
T536 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1947094103 Aug 17 05:35:51 PM PDT 24 Aug 17 05:35:52 PM PDT 24 15618599 ps
T537 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3461330006 Aug 17 05:35:52 PM PDT 24 Aug 17 05:35:53 PM PDT 24 19799281 ps
T538 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3620260258 Aug 17 05:35:44 PM PDT 24 Aug 17 05:35:45 PM PDT 24 34584235 ps
T96 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.964461896 Aug 17 05:35:52 PM PDT 24 Aug 17 05:35:53 PM PDT 24 84054927 ps
T539 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1308236464 Aug 17 05:35:47 PM PDT 24 Aug 17 05:35:48 PM PDT 24 30560372 ps
T540 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1653976386 Aug 17 05:35:58 PM PDT 24 Aug 17 05:35:59 PM PDT 24 24802399 ps
T541 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.912845111 Aug 17 05:35:47 PM PDT 24 Aug 17 05:35:47 PM PDT 24 14375486 ps
T88 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2665631786 Aug 17 05:35:54 PM PDT 24 Aug 17 05:35:55 PM PDT 24 11385115 ps
T542 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1764000947 Aug 17 05:36:00 PM PDT 24 Aug 17 05:36:01 PM PDT 24 14137335 ps
T543 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2640623486 Aug 17 05:36:13 PM PDT 24 Aug 17 05:36:14 PM PDT 24 11696616 ps
T544 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2216627807 Aug 17 05:36:03 PM PDT 24 Aug 17 05:36:04 PM PDT 24 333081901 ps
T545 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3523206119 Aug 17 05:35:58 PM PDT 24 Aug 17 05:36:00 PM PDT 24 48147964 ps
T546 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.623212957 Aug 17 05:36:00 PM PDT 24 Aug 17 05:36:01 PM PDT 24 107999983 ps
T547 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3814636374 Aug 17 05:36:00 PM PDT 24 Aug 17 05:36:01 PM PDT 24 29302258 ps
T548 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.642793050 Aug 17 05:36:01 PM PDT 24 Aug 17 05:36:03 PM PDT 24 159719482 ps
T549 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.271224092 Aug 17 05:36:15 PM PDT 24 Aug 17 05:36:16 PM PDT 24 43027271 ps
T550 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2873276370 Aug 17 05:35:58 PM PDT 24 Aug 17 05:35:59 PM PDT 24 95374432 ps
T551 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.4151991603 Aug 17 05:36:10 PM PDT 24 Aug 17 05:36:11 PM PDT 24 39833751 ps
T552 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2659611795 Aug 17 05:36:15 PM PDT 24 Aug 17 05:36:16 PM PDT 24 11931552 ps
T90 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3148814429 Aug 17 05:35:48 PM PDT 24 Aug 17 05:35:48 PM PDT 24 41391145 ps
T553 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.4069513064 Aug 17 05:36:02 PM PDT 24 Aug 17 05:36:04 PM PDT 24 197921748 ps
T554 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3019775076 Aug 17 05:36:14 PM PDT 24 Aug 17 05:36:15 PM PDT 24 14545754 ps
T555 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.868011989 Aug 17 05:36:13 PM PDT 24 Aug 17 05:36:14 PM PDT 24 17981910 ps
T556 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1861433169 Aug 17 05:35:46 PM PDT 24 Aug 17 05:35:47 PM PDT 24 19757466 ps
T557 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.582221966 Aug 17 05:36:14 PM PDT 24 Aug 17 05:36:15 PM PDT 24 286616947 ps
T558 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.318477768 Aug 17 05:35:53 PM PDT 24 Aug 17 05:35:54 PM PDT 24 74001589 ps
T559 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2279051903 Aug 17 05:36:07 PM PDT 24 Aug 17 05:36:08 PM PDT 24 13446826 ps
T560 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2350967996 Aug 17 05:36:14 PM PDT 24 Aug 17 05:36:15 PM PDT 24 18753303 ps
T561 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3272659326 Aug 17 05:35:44 PM PDT 24 Aug 17 05:35:46 PM PDT 24 88225219 ps
T562 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1137739406 Aug 17 05:35:44 PM PDT 24 Aug 17 05:35:45 PM PDT 24 116453212 ps
T563 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3054507336 Aug 17 05:36:00 PM PDT 24 Aug 17 05:36:01 PM PDT 24 33970780 ps
T564 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.163276650 Aug 17 05:35:52 PM PDT 24 Aug 17 05:35:53 PM PDT 24 12518117 ps
T565 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1151015659 Aug 17 05:36:07 PM PDT 24 Aug 17 05:36:08 PM PDT 24 158332512 ps
T566 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3676043203 Aug 17 05:36:06 PM PDT 24 Aug 17 05:36:08 PM PDT 24 76141797 ps
T567 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.645070446 Aug 17 05:36:14 PM PDT 24 Aug 17 05:36:15 PM PDT 24 84663753 ps
T568 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.56923577 Aug 17 05:35:45 PM PDT 24 Aug 17 05:35:46 PM PDT 24 29868853 ps
T569 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.387057045 Aug 17 05:36:14 PM PDT 24 Aug 17 05:36:14 PM PDT 24 31480467 ps
T570 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2898225350 Aug 17 05:36:06 PM PDT 24 Aug 17 05:36:06 PM PDT 24 14455596 ps
T571 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3470529912 Aug 17 05:35:51 PM PDT 24 Aug 17 05:35:53 PM PDT 24 192707091 ps
T89 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2844744812 Aug 17 05:36:06 PM PDT 24 Aug 17 05:36:06 PM PDT 24 31578758 ps
T572 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2253453319 Aug 17 05:35:50 PM PDT 24 Aug 17 05:35:51 PM PDT 24 47776853 ps
T573 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3444684619 Aug 17 05:35:58 PM PDT 24 Aug 17 05:35:58 PM PDT 24 78140761 ps
T574 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.791178326 Aug 17 05:35:49 PM PDT 24 Aug 17 05:35:51 PM PDT 24 402076984 ps
T575 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2621511725 Aug 17 05:36:05 PM PDT 24 Aug 17 05:36:06 PM PDT 24 180002096 ps
T576 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.755144763 Aug 17 05:35:56 PM PDT 24 Aug 17 05:35:58 PM PDT 24 148710762 ps
T577 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3328982241 Aug 17 05:35:52 PM PDT 24 Aug 17 05:35:53 PM PDT 24 27280752 ps
T578 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.483280623 Aug 17 05:36:10 PM PDT 24 Aug 17 05:36:10 PM PDT 24 155202090 ps
T579 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3518203937 Aug 17 05:36:17 PM PDT 24 Aug 17 05:36:18 PM PDT 24 15020285 ps
T580 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.751148558 Aug 17 05:35:58 PM PDT 24 Aug 17 05:35:59 PM PDT 24 139905513 ps
T581 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2000194579 Aug 17 05:35:47 PM PDT 24 Aug 17 05:35:48 PM PDT 24 64533922 ps
T582 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1878049187 Aug 17 05:35:47 PM PDT 24 Aug 17 05:35:48 PM PDT 24 44422279 ps

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1161719606
Short name T4
Test name
Test status
Simulation time 514575435879 ps
CPU time 285.43 seconds
Started Aug 17 05:36:52 PM PDT 24
Finished Aug 17 05:41:38 PM PDT 24
Peak memory 183560 kb
Host smart-69c9fdf4-247b-42ef-adc3-ca0dd57605e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161719606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1161719606
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.2729765886
Short name T12
Test name
Test status
Simulation time 3134049454 ps
CPU time 33.4 seconds
Started Aug 17 05:37:14 PM PDT 24
Finished Aug 17 05:37:47 PM PDT 24
Peak memory 198276 kb
Host smart-fdfdfcd7-ca9e-42d1-8920-3e7812f44386
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729765886 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.2729765886
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1670552702
Short name T48
Test name
Test status
Simulation time 3807237365719 ps
CPU time 2285.15 seconds
Started Aug 17 05:36:53 PM PDT 24
Finished Aug 17 06:14:58 PM PDT 24
Peak memory 191732 kb
Host smart-e8f0e354-ba96-407c-acdd-b47dec9577dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670552702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1670552702
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3997124796
Short name T29
Test name
Test status
Simulation time 67413806 ps
CPU time 1.1 seconds
Started Aug 17 05:35:46 PM PDT 24
Finished Aug 17 05:35:47 PM PDT 24
Peak memory 196008 kb
Host smart-2da2434c-ce7d-4af3-b11d-9b730f09f8a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997124796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3997124796
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.4064542052
Short name T102
Test name
Test status
Simulation time 850095030212 ps
CPU time 956.08 seconds
Started Aug 17 05:36:54 PM PDT 24
Finished Aug 17 05:52:50 PM PDT 24
Peak memory 195996 kb
Host smart-b58307ea-0d0d-4935-839f-346180931711
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064542052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.4064542052
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2268482469
Short name T146
Test name
Test status
Simulation time 3375376269087 ps
CPU time 2428.69 seconds
Started Aug 17 05:37:17 PM PDT 24
Finished Aug 17 06:17:46 PM PDT 24
Peak memory 191668 kb
Host smart-a350d9e6-3035-4cc8-bc17-b7355dec6b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268482469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2268482469
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1574458236
Short name T116
Test name
Test status
Simulation time 1392672986036 ps
CPU time 3556.51 seconds
Started Aug 17 05:37:01 PM PDT 24
Finished Aug 17 06:36:18 PM PDT 24
Peak memory 191700 kb
Host smart-fb4e37cf-dcb3-4836-a52b-ab9d3ec96fe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574458236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1574458236
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3360661842
Short name T178
Test name
Test status
Simulation time 1272513760052 ps
CPU time 1805.06 seconds
Started Aug 17 05:36:29 PM PDT 24
Finished Aug 17 06:06:35 PM PDT 24
Peak memory 191708 kb
Host smart-4488abf6-2383-4b4f-8578-368b6e6ec723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360661842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3360661842
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.661905050
Short name T135
Test name
Test status
Simulation time 1231519613127 ps
CPU time 1007.39 seconds
Started Aug 17 05:37:08 PM PDT 24
Finished Aug 17 05:53:56 PM PDT 24
Peak memory 191768 kb
Host smart-5e0a79e4-ae59-407e-b0b5-317ffd44b494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661905050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
661905050
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3327754436
Short name T77
Test name
Test status
Simulation time 17265633 ps
CPU time 0.59 seconds
Started Aug 17 05:35:47 PM PDT 24
Finished Aug 17 05:35:48 PM PDT 24
Peak memory 183388 kb
Host smart-2940c085-9d29-4d85-b0e2-0a3e27c254ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327754436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3327754436
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.4091296703
Short name T121
Test name
Test status
Simulation time 751555910848 ps
CPU time 992.44 seconds
Started Aug 17 05:36:34 PM PDT 24
Finished Aug 17 05:53:07 PM PDT 24
Peak memory 196216 kb
Host smart-45907b47-b6a3-48b4-bd01-01c506358c7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091296703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.4091296703
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/96.rv_timer_random.1720986351
Short name T11
Test name
Test status
Simulation time 1094685976341 ps
CPU time 3381.22 seconds
Started Aug 17 05:37:36 PM PDT 24
Finished Aug 17 06:33:58 PM PDT 24
Peak memory 191788 kb
Host smart-610e86f5-4ffa-4b09-bc66-11a15a0c5621
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720986351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1720986351
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3671769881
Short name T19
Test name
Test status
Simulation time 74552670 ps
CPU time 0.85 seconds
Started Aug 17 05:36:15 PM PDT 24
Finished Aug 17 05:36:16 PM PDT 24
Peak memory 213976 kb
Host smart-015509c1-416c-4d37-b158-3bb5080ee982
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671769881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3671769881
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.214403863
Short name T52
Test name
Test status
Simulation time 210914741 ps
CPU time 0.77 seconds
Started Aug 17 05:35:45 PM PDT 24
Finished Aug 17 05:35:46 PM PDT 24
Peak memory 193940 kb
Host smart-7cc5c153-42af-48f1-a28b-a9c932e95894
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214403863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.214403863
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/124.rv_timer_random.1442596489
Short name T60
Test name
Test status
Simulation time 623113437279 ps
CPU time 972.39 seconds
Started Aug 17 05:37:40 PM PDT 24
Finished Aug 17 05:53:52 PM PDT 24
Peak memory 191732 kb
Host smart-db5d4a38-417c-458f-8c04-47c5679da618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442596489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1442596489
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3361316306
Short name T205
Test name
Test status
Simulation time 712741831630 ps
CPU time 443.65 seconds
Started Aug 17 05:37:24 PM PDT 24
Finished Aug 17 05:44:48 PM PDT 24
Peak memory 191740 kb
Host smart-79aa47d5-0e9e-47f3-ac89-f94972e32228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361316306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3361316306
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3823559265
Short name T119
Test name
Test status
Simulation time 2155262245054 ps
CPU time 1923.44 seconds
Started Aug 17 05:36:28 PM PDT 24
Finished Aug 17 06:08:31 PM PDT 24
Peak memory 191772 kb
Host smart-0ae47312-555b-4721-a313-b98ae8e02d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823559265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3823559265
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1543801108
Short name T167
Test name
Test status
Simulation time 460760447205 ps
CPU time 793.32 seconds
Started Aug 17 05:36:29 PM PDT 24
Finished Aug 17 05:49:43 PM PDT 24
Peak memory 197356 kb
Host smart-48cd52e4-acd2-4abe-b55b-695d0bd80af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543801108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1543801108
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3733945918
Short name T310
Test name
Test status
Simulation time 1747237865124 ps
CPU time 1001.42 seconds
Started Aug 17 05:36:30 PM PDT 24
Finished Aug 17 05:53:12 PM PDT 24
Peak memory 196788 kb
Host smart-29110528-21cb-409b-a204-5ccf020dd039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733945918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3733945918
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.496720698
Short name T265
Test name
Test status
Simulation time 3110423279460 ps
CPU time 5435.06 seconds
Started Aug 17 05:36:58 PM PDT 24
Finished Aug 17 07:07:34 PM PDT 24
Peak memory 191764 kb
Host smart-057a42aa-07e7-4f04-b5b4-2b6ff12e9cf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496720698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
496720698
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.257183837
Short name T355
Test name
Test status
Simulation time 1501429786552 ps
CPU time 1020.93 seconds
Started Aug 17 05:36:15 PM PDT 24
Finished Aug 17 05:53:16 PM PDT 24
Peak memory 191732 kb
Host smart-4b79047e-5ee3-411a-8db3-605b379b5c8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257183837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.257183837
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_random.4145385217
Short name T130
Test name
Test status
Simulation time 964022371769 ps
CPU time 470.28 seconds
Started Aug 17 05:36:17 PM PDT 24
Finished Aug 17 05:44:07 PM PDT 24
Peak memory 191792 kb
Host smart-0a9acf98-662d-4cfc-8efb-0ff4f4157c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145385217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.4145385217
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3550434346
Short name T1
Test name
Test status
Simulation time 2608075880150 ps
CPU time 858.32 seconds
Started Aug 17 05:37:54 PM PDT 24
Finished Aug 17 05:52:13 PM PDT 24
Peak memory 191800 kb
Host smart-bdfd2868-3b4a-4a75-b666-445c6b520d9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550434346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3550434346
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random.1816246381
Short name T181
Test name
Test status
Simulation time 279655208313 ps
CPU time 274.59 seconds
Started Aug 17 05:36:55 PM PDT 24
Finished Aug 17 05:41:29 PM PDT 24
Peak memory 191804 kb
Host smart-45e68f69-5b04-41fd-9374-997833e5c5e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816246381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1816246381
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2579634184
Short name T250
Test name
Test status
Simulation time 387431592374 ps
CPU time 669.57 seconds
Started Aug 17 05:37:09 PM PDT 24
Finished Aug 17 05:48:19 PM PDT 24
Peak memory 191760 kb
Host smart-73b92bb4-25e6-4bf7-9191-74210b0f831c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579634184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2579634184
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.1520082697
Short name T27
Test name
Test status
Simulation time 581769129845 ps
CPU time 2052.55 seconds
Started Aug 17 05:37:24 PM PDT 24
Finished Aug 17 06:11:37 PM PDT 24
Peak memory 191788 kb
Host smart-dc8cda15-14a0-4f2d-abc1-7635e5628736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520082697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1520082697
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.206273808
Short name T172
Test name
Test status
Simulation time 956249325866 ps
CPU time 878.47 seconds
Started Aug 17 05:36:27 PM PDT 24
Finished Aug 17 05:51:06 PM PDT 24
Peak memory 191820 kb
Host smart-5546aea8-8f5b-43d0-8392-a8fa2ac7573f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206273808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.206273808
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3624412035
Short name T267
Test name
Test status
Simulation time 65706274131 ps
CPU time 96.31 seconds
Started Aug 17 05:36:32 PM PDT 24
Finished Aug 17 05:38:09 PM PDT 24
Peak memory 191752 kb
Host smart-d4ca7fe6-6547-4d9c-a512-c68cdc6b1d82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624412035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3624412035
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/179.rv_timer_random.466815989
Short name T63
Test name
Test status
Simulation time 1484334576964 ps
CPU time 464.6 seconds
Started Aug 17 05:38:13 PM PDT 24
Finished Aug 17 05:45:57 PM PDT 24
Peak memory 191780 kb
Host smart-9bd3f62a-fd01-4f40-9366-35bbfa4d9a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466815989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.466815989
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random.3218540645
Short name T49
Test name
Test status
Simulation time 89516566059 ps
CPU time 253.68 seconds
Started Aug 17 05:36:55 PM PDT 24
Finished Aug 17 05:41:09 PM PDT 24
Peak memory 194120 kb
Host smart-39e38c4a-494a-4f24-b006-418b075f713f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218540645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3218540645
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1582004816
Short name T292
Test name
Test status
Simulation time 104521795150 ps
CPU time 149.43 seconds
Started Aug 17 05:37:07 PM PDT 24
Finished Aug 17 05:39:36 PM PDT 24
Peak memory 183568 kb
Host smart-2c6d5bfa-a6b1-409b-98dd-980622b8cbef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582004816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1582004816
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random.3737695579
Short name T74
Test name
Test status
Simulation time 202403674408 ps
CPU time 716.05 seconds
Started Aug 17 05:37:05 PM PDT 24
Finished Aug 17 05:49:01 PM PDT 24
Peak memory 191812 kb
Host smart-fc1eae0c-4f6d-4c69-9f53-a2336d257b50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737695579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3737695579
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1103539849
Short name T200
Test name
Test status
Simulation time 590031476658 ps
CPU time 453.57 seconds
Started Aug 17 05:37:33 PM PDT 24
Finished Aug 17 05:45:07 PM PDT 24
Peak memory 191804 kb
Host smart-62b45f93-bb72-4b64-858b-0572f3156fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103539849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1103539849
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3927648575
Short name T315
Test name
Test status
Simulation time 124009792359 ps
CPU time 318.11 seconds
Started Aug 17 05:37:39 PM PDT 24
Finished Aug 17 05:42:57 PM PDT 24
Peak memory 191996 kb
Host smart-88292bb0-b7fd-448b-b0ca-eb52f8318be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927648575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3927648575
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.964430672
Short name T220
Test name
Test status
Simulation time 75016260959 ps
CPU time 727.21 seconds
Started Aug 17 05:38:04 PM PDT 24
Finished Aug 17 05:50:11 PM PDT 24
Peak memory 191800 kb
Host smart-3c653528-b837-4e5a-b5b4-6c4b3e3280b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964430672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.964430672
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1297810815
Short name T214
Test name
Test status
Simulation time 701112502368 ps
CPU time 634.46 seconds
Started Aug 17 05:38:01 PM PDT 24
Finished Aug 17 05:48:36 PM PDT 24
Peak memory 191812 kb
Host smart-6ab01a1a-cdfe-4fe4-8e5e-d99ab404c579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297810815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1297810815
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2073410720
Short name T273
Test name
Test status
Simulation time 1383301882811 ps
CPU time 1070.54 seconds
Started Aug 17 05:36:39 PM PDT 24
Finished Aug 17 05:54:30 PM PDT 24
Peak memory 191680 kb
Host smart-e8fcac1f-3522-49d7-a813-1416932dfe3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073410720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2073410720
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/59.rv_timer_random.2502809805
Short name T294
Test name
Test status
Simulation time 144014153155 ps
CPU time 751.81 seconds
Started Aug 17 05:37:15 PM PDT 24
Finished Aug 17 05:49:47 PM PDT 24
Peak memory 191776 kb
Host smart-23cfa3f0-d1af-4e30-821c-d242f05f758c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502809805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2502809805
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3432410601
Short name T70
Test name
Test status
Simulation time 1858501370563 ps
CPU time 1235.9 seconds
Started Aug 17 05:36:30 PM PDT 24
Finished Aug 17 05:57:06 PM PDT 24
Peak memory 191764 kb
Host smart-2b004607-bd05-4bb4-abae-5f75d6ded8c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432410601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3432410601
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/94.rv_timer_random.3818264242
Short name T44
Test name
Test status
Simulation time 94280515881 ps
CPU time 85.44 seconds
Started Aug 17 05:37:35 PM PDT 24
Finished Aug 17 05:39:00 PM PDT 24
Peak memory 195288 kb
Host smart-bdcc6dbe-dc14-4f82-a71f-3d63c49b0dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818264242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3818264242
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.1927958081
Short name T115
Test name
Test status
Simulation time 803256419956 ps
CPU time 785.38 seconds
Started Aug 17 05:37:42 PM PDT 24
Finished Aug 17 05:50:48 PM PDT 24
Peak memory 191748 kb
Host smart-298fbb8d-f842-4671-93d8-d3add2d815a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927958081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1927958081
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.100818536
Short name T229
Test name
Test status
Simulation time 584651979749 ps
CPU time 456.61 seconds
Started Aug 17 05:36:30 PM PDT 24
Finished Aug 17 05:44:07 PM PDT 24
Peak memory 191712 kb
Host smart-422295ee-1630-46ec-b613-74c39024e1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100818536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.100818536
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_random.589466323
Short name T212
Test name
Test status
Simulation time 85456143369 ps
CPU time 202.1 seconds
Started Aug 17 05:36:46 PM PDT 24
Finished Aug 17 05:40:08 PM PDT 24
Peak memory 183600 kb
Host smart-4bccb972-ec30-4393-af63-812fa54c3578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589466323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.589466323
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random.1584853473
Short name T129
Test name
Test status
Simulation time 111624903156 ps
CPU time 166.58 seconds
Started Aug 17 05:37:16 PM PDT 24
Finished Aug 17 05:40:03 PM PDT 24
Peak memory 191812 kb
Host smart-37d3dbf5-df95-4733-80bc-e4688191577d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584853473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1584853473
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3396973622
Short name T217
Test name
Test status
Simulation time 687396757743 ps
CPU time 784.28 seconds
Started Aug 17 05:37:35 PM PDT 24
Finished Aug 17 05:50:40 PM PDT 24
Peak memory 193916 kb
Host smart-002a33dd-569d-4791-8490-11cc5ba3da84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396973622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3396973622
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3967805842
Short name T106
Test name
Test status
Simulation time 545409651102 ps
CPU time 405.75 seconds
Started Aug 17 05:37:34 PM PDT 24
Finished Aug 17 05:44:20 PM PDT 24
Peak memory 191780 kb
Host smart-31b35bde-d5cc-4f72-8768-ace4d24e79a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967805842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3967805842
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3574340540
Short name T237
Test name
Test status
Simulation time 1627280412025 ps
CPU time 583.88 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:45:58 PM PDT 24
Peak memory 183500 kb
Host smart-15ae81d3-88b6-4a59-9a95-ad4fd834a53d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574340540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3574340540
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/129.rv_timer_random.2197882417
Short name T238
Test name
Test status
Simulation time 130041465769 ps
CPU time 168.21 seconds
Started Aug 17 05:37:46 PM PDT 24
Finished Aug 17 05:40:35 PM PDT 24
Peak memory 193428 kb
Host smart-85587da2-61ff-4893-b65c-6f8dcf787535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197882417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2197882417
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1446864364
Short name T184
Test name
Test status
Simulation time 88370393751 ps
CPU time 149 seconds
Started Aug 17 05:37:46 PM PDT 24
Finished Aug 17 05:40:15 PM PDT 24
Peak memory 191784 kb
Host smart-da1cffd3-75e1-4858-aa80-11c84e426cfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446864364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1446864364
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.199226365
Short name T262
Test name
Test status
Simulation time 429832564439 ps
CPU time 697.4 seconds
Started Aug 17 05:36:32 PM PDT 24
Finished Aug 17 05:48:10 PM PDT 24
Peak memory 191744 kb
Host smart-2b2d3e93-555e-44b1-a50b-6a59ad6097d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199226365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
199226365
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2061012596
Short name T168
Test name
Test status
Simulation time 240082001961 ps
CPU time 379.85 seconds
Started Aug 17 05:36:32 PM PDT 24
Finished Aug 17 05:42:52 PM PDT 24
Peak memory 183556 kb
Host smart-c7345f90-b2ca-4765-940e-55495e44819c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061012596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2061012596
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/186.rv_timer_random.142405162
Short name T282
Test name
Test status
Simulation time 729248638932 ps
CPU time 325.09 seconds
Started Aug 17 05:38:13 PM PDT 24
Finished Aug 17 05:43:38 PM PDT 24
Peak memory 191736 kb
Host smart-e5c6b073-796c-4cd7-9df8-6728676d5fd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142405162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.142405162
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.558567153
Short name T145
Test name
Test status
Simulation time 96531443118 ps
CPU time 88.5 seconds
Started Aug 17 05:36:33 PM PDT 24
Finished Aug 17 05:38:02 PM PDT 24
Peak memory 183532 kb
Host smart-cd9c8fc4-9bc6-44dc-878d-b18bc737c9d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558567153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.558567153
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2466900728
Short name T147
Test name
Test status
Simulation time 2912498569186 ps
CPU time 1011.75 seconds
Started Aug 17 05:36:45 PM PDT 24
Finished Aug 17 05:53:37 PM PDT 24
Peak memory 191780 kb
Host smart-fd8d1f52-2b0c-4895-8771-f15f3877167b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466900728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2466900728
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_random.3499690834
Short name T293
Test name
Test status
Simulation time 120304927423 ps
CPU time 112.74 seconds
Started Aug 17 05:36:58 PM PDT 24
Finished Aug 17 05:38:51 PM PDT 24
Peak memory 191768 kb
Host smart-d812d6a4-f19e-405f-bc9d-bd5aadce01a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499690834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3499690834
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3444450156
Short name T321
Test name
Test status
Simulation time 407568351197 ps
CPU time 194.92 seconds
Started Aug 17 05:37:18 PM PDT 24
Finished Aug 17 05:40:33 PM PDT 24
Peak memory 191724 kb
Host smart-67c54158-343e-471a-b8f8-5b61ac71d13e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444450156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3444450156
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3148814429
Short name T90
Test name
Test status
Simulation time 41391145 ps
CPU time 0.55 seconds
Started Aug 17 05:35:48 PM PDT 24
Finished Aug 17 05:35:48 PM PDT 24
Peak memory 183384 kb
Host smart-c3981e04-4cac-4240-b739-e820a214302c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148814429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3148814429
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/103.rv_timer_random.1702625287
Short name T331
Test name
Test status
Simulation time 87035480411 ps
CPU time 196.04 seconds
Started Aug 17 05:37:33 PM PDT 24
Finished Aug 17 05:40:50 PM PDT 24
Peak memory 195332 kb
Host smart-29fb6f4b-c940-45bd-b648-03d4c4d8ff35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702625287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1702625287
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.1396223358
Short name T134
Test name
Test status
Simulation time 146815039258 ps
CPU time 123.78 seconds
Started Aug 17 05:37:39 PM PDT 24
Finished Aug 17 05:39:43 PM PDT 24
Peak memory 191812 kb
Host smart-a4aa2aa9-a770-4cc2-a266-c7be022eac91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396223358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1396223358
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1024279665
Short name T277
Test name
Test status
Simulation time 124103781429 ps
CPU time 117.98 seconds
Started Aug 17 05:37:40 PM PDT 24
Finished Aug 17 05:39:38 PM PDT 24
Peak memory 191780 kb
Host smart-ac262aba-5a4b-4f66-9fdc-891c9d52c495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024279665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1024279665
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.870002605
Short name T252
Test name
Test status
Simulation time 837903552477 ps
CPU time 525.99 seconds
Started Aug 17 05:37:48 PM PDT 24
Finished Aug 17 05:46:34 PM PDT 24
Peak memory 191816 kb
Host smart-648bb655-e552-4b76-97b3-d466838af3d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870002605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.870002605
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1447162896
Short name T226
Test name
Test status
Simulation time 579776401584 ps
CPU time 167.45 seconds
Started Aug 17 05:38:02 PM PDT 24
Finished Aug 17 05:40:50 PM PDT 24
Peak memory 191748 kb
Host smart-e3dfd18d-9b24-48b5-8015-9e579b29fc30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447162896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1447162896
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2989149658
Short name T235
Test name
Test status
Simulation time 372187441769 ps
CPU time 425.04 seconds
Started Aug 17 05:38:05 PM PDT 24
Finished Aug 17 05:45:10 PM PDT 24
Peak memory 191812 kb
Host smart-f486daff-00dd-4c47-86a3-4264b4ad8c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989149658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2989149658
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.1745495933
Short name T240
Test name
Test status
Simulation time 524234003454 ps
CPU time 611.05 seconds
Started Aug 17 05:36:30 PM PDT 24
Finished Aug 17 05:46:42 PM PDT 24
Peak memory 191780 kb
Host smart-87ed73eb-c2ee-4761-86b6-893d7a603054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745495933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1745495933
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3630658628
Short name T284
Test name
Test status
Simulation time 2682852188877 ps
CPU time 2345.85 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 06:15:37 PM PDT 24
Peak memory 191776 kb
Host smart-b9149d9f-6924-4f65-9c88-58761fca4733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630658628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3630658628
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.654918938
Short name T255
Test name
Test status
Simulation time 111729746940 ps
CPU time 111.43 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:38:22 PM PDT 24
Peak memory 191804 kb
Host smart-0ce54a7b-06fb-4fa1-921a-fc65cf29f5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654918938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.654918938
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/183.rv_timer_random.3039790486
Short name T159
Test name
Test status
Simulation time 186620836726 ps
CPU time 300.64 seconds
Started Aug 17 05:38:13 PM PDT 24
Finished Aug 17 05:43:14 PM PDT 24
Peak memory 191696 kb
Host smart-cc93e702-81f4-4e3b-9427-5d1558415181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039790486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3039790486
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.444135986
Short name T165
Test name
Test status
Simulation time 77909539572 ps
CPU time 139.23 seconds
Started Aug 17 05:38:12 PM PDT 24
Finished Aug 17 05:40:31 PM PDT 24
Peak memory 191792 kb
Host smart-eb2b4021-4a27-4268-97b8-1dc3b1aed828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444135986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.444135986
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3684163256
Short name T351
Test name
Test status
Simulation time 46283519865 ps
CPU time 22.2 seconds
Started Aug 17 05:36:40 PM PDT 24
Finished Aug 17 05:37:03 PM PDT 24
Peak memory 183584 kb
Host smart-91fbc6c1-3c97-4ebb-97ab-44a9b183ec6b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684163256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3684163256
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.284498777
Short name T195
Test name
Test status
Simulation time 242124926753 ps
CPU time 230.27 seconds
Started Aug 17 05:36:38 PM PDT 24
Finished Aug 17 05:40:28 PM PDT 24
Peak memory 183472 kb
Host smart-1aae1d34-5d2a-421a-8b83-aacc3692833b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284498777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.284498777
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_random.501556081
Short name T100
Test name
Test status
Simulation time 881323503586 ps
CPU time 60.28 seconds
Started Aug 17 05:36:48 PM PDT 24
Finished Aug 17 05:37:48 PM PDT 24
Peak memory 191732 kb
Host smart-201d0616-af6b-4e66-a4a8-8f206ed807ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501556081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.501556081
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.2913461459
Short name T108
Test name
Test status
Simulation time 85053124430 ps
CPU time 126.23 seconds
Started Aug 17 05:36:54 PM PDT 24
Finished Aug 17 05:39:00 PM PDT 24
Peak memory 191768 kb
Host smart-3fbf3ca7-0b24-430c-b3fe-6ea9465064e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913461459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2913461459
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.186051704
Short name T232
Test name
Test status
Simulation time 89510295884 ps
CPU time 46.63 seconds
Started Aug 17 05:37:14 PM PDT 24
Finished Aug 17 05:38:01 PM PDT 24
Peak memory 183596 kb
Host smart-29dd0db9-7430-42fe-b201-9d521866e3e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186051704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.186051704
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/62.rv_timer_random.3788746899
Short name T254
Test name
Test status
Simulation time 636778856325 ps
CPU time 2707.98 seconds
Started Aug 17 05:37:26 PM PDT 24
Finished Aug 17 06:22:34 PM PDT 24
Peak memory 191728 kb
Host smart-77c49dff-d2c8-4305-953c-61e46ce945d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788746899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3788746899
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.4164602223
Short name T156
Test name
Test status
Simulation time 44507915258 ps
CPU time 377.43 seconds
Started Aug 17 05:37:24 PM PDT 24
Finished Aug 17 05:43:41 PM PDT 24
Peak memory 191796 kb
Host smart-02c66c80-37b8-402a-803e-ccca8af85cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164602223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.4164602223
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3706927500
Short name T99
Test name
Test status
Simulation time 146575130 ps
CPU time 1.32 seconds
Started Aug 17 05:36:00 PM PDT 24
Finished Aug 17 05:36:01 PM PDT 24
Peak memory 196052 kb
Host smart-58f44bc4-8a82-4b33-ada5-6b81bacbb1cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706927500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3706927500
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.8210081
Short name T95
Test name
Test status
Simulation time 377923525 ps
CPU time 1.16 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:36:16 PM PDT 24
Peak memory 195692 kb
Host smart-dbee6012-33ea-4f3f-b36b-ba12f634355a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8210081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg
_err.8210081
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/100.rv_timer_random.3361558025
Short name T251
Test name
Test status
Simulation time 18667196275 ps
CPU time 172.9 seconds
Started Aug 17 05:37:36 PM PDT 24
Finished Aug 17 05:40:29 PM PDT 24
Peak memory 183592 kb
Host smart-34b2c7e4-eb26-4bcf-ad85-2180da3b1e8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361558025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3361558025
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3146257896
Short name T45
Test name
Test status
Simulation time 6740627968 ps
CPU time 9.3 seconds
Started Aug 17 05:37:39 PM PDT 24
Finished Aug 17 05:37:48 PM PDT 24
Peak memory 191524 kb
Host smart-e3124d6d-4a52-4e3b-82b0-141fcf1a4f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146257896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3146257896
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1882554539
Short name T169
Test name
Test status
Simulation time 9145467132 ps
CPU time 15.18 seconds
Started Aug 17 05:36:29 PM PDT 24
Finished Aug 17 05:36:44 PM PDT 24
Peak memory 183552 kb
Host smart-fff1afff-639b-45a5-af30-0c3013053a4e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882554539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1882554539
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3596377770
Short name T155
Test name
Test status
Simulation time 26654090900 ps
CPU time 42.42 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:37:14 PM PDT 24
Peak memory 183532 kb
Host smart-413887fe-0481-4bc6-9ce0-a3c57eb052d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596377770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3596377770
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/120.rv_timer_random.2827706473
Short name T21
Test name
Test status
Simulation time 14542430746 ps
CPU time 23.46 seconds
Started Aug 17 05:37:41 PM PDT 24
Finished Aug 17 05:38:04 PM PDT 24
Peak memory 191768 kb
Host smart-0f06e789-c00d-4d3e-9aa3-99d10174514d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827706473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2827706473
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1181942804
Short name T221
Test name
Test status
Simulation time 584247608469 ps
CPU time 313.54 seconds
Started Aug 17 05:37:39 PM PDT 24
Finished Aug 17 05:42:53 PM PDT 24
Peak memory 191812 kb
Host smart-506f7677-2aa2-44e9-a207-a3c626b0c20a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181942804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1181942804
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2832866170
Short name T280
Test name
Test status
Simulation time 54694532353 ps
CPU time 209.41 seconds
Started Aug 17 05:37:54 PM PDT 24
Finished Aug 17 05:41:23 PM PDT 24
Peak memory 191712 kb
Host smart-82bae003-70a0-46bf-b2e6-68fc68476bc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832866170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2832866170
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2753044040
Short name T180
Test name
Test status
Simulation time 107136130755 ps
CPU time 89.22 seconds
Started Aug 17 05:38:05 PM PDT 24
Finished Aug 17 05:39:35 PM PDT 24
Peak memory 191780 kb
Host smart-63d5764f-b78d-4636-aadd-c5d93296684e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753044040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2753044040
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.922547090
Short name T153
Test name
Test status
Simulation time 153552336809 ps
CPU time 1223.86 seconds
Started Aug 17 05:38:10 PM PDT 24
Finished Aug 17 05:58:34 PM PDT 24
Peak memory 191812 kb
Host smart-9f7dea82-3a13-4816-bbc6-75f9b86775f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922547090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.922547090
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.548485604
Short name T150
Test name
Test status
Simulation time 60943436472 ps
CPU time 95.37 seconds
Started Aug 17 05:38:13 PM PDT 24
Finished Aug 17 05:39:48 PM PDT 24
Peak memory 191728 kb
Host smart-deeca03f-0984-4c76-aa85-4044382055e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548485604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.548485604
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2468459474
Short name T256
Test name
Test status
Simulation time 154504484856 ps
CPU time 964.43 seconds
Started Aug 17 05:38:19 PM PDT 24
Finished Aug 17 05:54:23 PM PDT 24
Peak memory 183516 kb
Host smart-b179dec2-38b8-4c39-b5a8-3d73c320c790
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468459474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2468459474
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2876769781
Short name T259
Test name
Test status
Simulation time 176048835853 ps
CPU time 83.69 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:37:37 PM PDT 24
Peak memory 195184 kb
Host smart-5b24e1f8-a84f-4912-9d91-be1fc58e6437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876769781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2876769781
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_random.1841672370
Short name T154
Test name
Test status
Simulation time 237966393967 ps
CPU time 184.45 seconds
Started Aug 17 05:36:36 PM PDT 24
Finished Aug 17 05:39:40 PM PDT 24
Peak memory 191812 kb
Host smart-b8e3a67b-5b9d-46cb-bf09-d7dbd84d7c5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841672370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1841672370
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1917947978
Short name T112
Test name
Test status
Simulation time 2732553689395 ps
CPU time 1416.45 seconds
Started Aug 17 05:36:39 PM PDT 24
Finished Aug 17 06:00:16 PM PDT 24
Peak memory 191788 kb
Host smart-6ad0efdb-28db-4114-abf0-f8459d1be7f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917947978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1917947978
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random.186517560
Short name T133
Test name
Test status
Simulation time 400712044977 ps
CPU time 241.44 seconds
Started Aug 17 05:36:47 PM PDT 24
Finished Aug 17 05:40:48 PM PDT 24
Peak memory 191724 kb
Host smart-cd239da7-1e7a-4173-a5d5-9903e537ea17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186517560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.186517560
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2810871270
Short name T297
Test name
Test status
Simulation time 316350423830 ps
CPU time 569.67 seconds
Started Aug 17 05:36:48 PM PDT 24
Finished Aug 17 05:46:18 PM PDT 24
Peak memory 191768 kb
Host smart-d4901a7c-55fc-46cb-b810-5c3b1d5d9bac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810871270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2810871270
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_random.2335239871
Short name T171
Test name
Test status
Simulation time 740656668260 ps
CPU time 588.97 seconds
Started Aug 17 05:36:46 PM PDT 24
Finished Aug 17 05:46:35 PM PDT 24
Peak memory 191780 kb
Host smart-b0f0def4-57bd-4519-b869-40e403f14648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335239871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2335239871
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3305120375
Short name T219
Test name
Test status
Simulation time 826628741227 ps
CPU time 452.34 seconds
Started Aug 17 05:37:03 PM PDT 24
Finished Aug 17 05:44:35 PM PDT 24
Peak memory 183632 kb
Host smart-998cac23-ee27-4e39-bc9e-d7a5f18f205a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305120375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3305120375
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3976005677
Short name T257
Test name
Test status
Simulation time 367885353709 ps
CPU time 160.52 seconds
Started Aug 17 05:37:14 PM PDT 24
Finished Aug 17 05:39:54 PM PDT 24
Peak memory 183512 kb
Host smart-f09ad03c-7e61-4218-b21c-8c214118e993
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976005677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3976005677
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1003231755
Short name T316
Test name
Test status
Simulation time 321168335737 ps
CPU time 476.02 seconds
Started Aug 17 05:36:20 PM PDT 24
Finished Aug 17 05:44:17 PM PDT 24
Peak memory 183572 kb
Host smart-b761945a-571f-42cd-b810-194ccbd5bed2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003231755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1003231755
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/55.rv_timer_random.1126190905
Short name T164
Test name
Test status
Simulation time 450548652574 ps
CPU time 269.16 seconds
Started Aug 17 05:37:17 PM PDT 24
Finished Aug 17 05:41:46 PM PDT 24
Peak memory 191676 kb
Host smart-24a6141d-c57c-40a1-9b99-abd669cd6b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126190905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1126190905
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.3218001777
Short name T275
Test name
Test status
Simulation time 520164576025 ps
CPU time 868.92 seconds
Started Aug 17 05:37:25 PM PDT 24
Finished Aug 17 05:51:54 PM PDT 24
Peak memory 191768 kb
Host smart-2f1d62d3-da8a-4e9f-807f-97f36853d449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218001777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3218001777
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.786969592
Short name T170
Test name
Test status
Simulation time 99418461053 ps
CPU time 527.64 seconds
Started Aug 17 05:37:25 PM PDT 24
Finished Aug 17 05:46:13 PM PDT 24
Peak memory 191832 kb
Host smart-530665a3-ab95-47c5-81ab-92a8e73230ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786969592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.786969592
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.157808164
Short name T173
Test name
Test status
Simulation time 59398696793 ps
CPU time 63.24 seconds
Started Aug 17 05:37:24 PM PDT 24
Finished Aug 17 05:38:28 PM PDT 24
Peak memory 191984 kb
Host smart-f0db67e3-b369-4567-8ed5-e4e1af791a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157808164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.157808164
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.1323733205
Short name T190
Test name
Test status
Simulation time 432012255203 ps
CPU time 321.94 seconds
Started Aug 17 05:37:33 PM PDT 24
Finished Aug 17 05:42:55 PM PDT 24
Peak memory 191768 kb
Host smart-1efeee97-e840-415c-85b3-180b1a512786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323733205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1323733205
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4122297763
Short name T83
Test name
Test status
Simulation time 23388077 ps
CPU time 0.59 seconds
Started Aug 17 05:35:45 PM PDT 24
Finished Aug 17 05:35:45 PM PDT 24
Peak memory 183272 kb
Host smart-1c3c4ef4-bdea-4de3-b62a-8207d0dba527
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122297763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.4122297763
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.4113276413
Short name T491
Test name
Test status
Simulation time 142013936 ps
CPU time 1.43 seconds
Started Aug 17 05:35:45 PM PDT 24
Finished Aug 17 05:35:47 PM PDT 24
Peak memory 191708 kb
Host smart-1c8c0ebd-1f61-486e-8c2b-4e8b35e8ae11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113276413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.4113276413
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3150957633
Short name T529
Test name
Test status
Simulation time 24293239 ps
CPU time 0.6 seconds
Started Aug 17 05:35:46 PM PDT 24
Finished Aug 17 05:35:47 PM PDT 24
Peak memory 183372 kb
Host smart-717ec625-4a26-4066-ae7b-38a8194c88cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150957633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3150957633
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3495997024
Short name T535
Test name
Test status
Simulation time 14606141 ps
CPU time 0.64 seconds
Started Aug 17 05:35:48 PM PDT 24
Finished Aug 17 05:35:48 PM PDT 24
Peak memory 193876 kb
Host smart-52ea2e17-30f2-4e4e-b47d-24bc6481d0be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495997024 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3495997024
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1445414724
Short name T462
Test name
Test status
Simulation time 16966627 ps
CPU time 0.56 seconds
Started Aug 17 05:35:45 PM PDT 24
Finished Aug 17 05:35:46 PM PDT 24
Peak memory 183264 kb
Host smart-4afb744a-949d-43ed-aea7-083b01187c90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445414724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1445414724
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1137739406
Short name T562
Test name
Test status
Simulation time 116453212 ps
CPU time 0.78 seconds
Started Aug 17 05:35:44 PM PDT 24
Finished Aug 17 05:35:45 PM PDT 24
Peak memory 194020 kb
Host smart-842fb47d-be64-4c6a-97eb-5fe2748e969d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137739406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1137739406
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3272659326
Short name T561
Test name
Test status
Simulation time 88225219 ps
CPU time 1.45 seconds
Started Aug 17 05:35:44 PM PDT 24
Finished Aug 17 05:35:46 PM PDT 24
Peak memory 198096 kb
Host smart-4cc22226-4a61-4e05-81bc-ca488e66cbc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272659326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3272659326
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2253453319
Short name T572
Test name
Test status
Simulation time 47776853 ps
CPU time 0.68 seconds
Started Aug 17 05:35:50 PM PDT 24
Finished Aug 17 05:35:51 PM PDT 24
Peak memory 192744 kb
Host smart-271444c4-1da2-496b-9e5e-0fa709de2d64
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253453319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2253453319
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3616991494
Short name T75
Test name
Test status
Simulation time 285912021 ps
CPU time 3.45 seconds
Started Aug 17 05:35:48 PM PDT 24
Finished Aug 17 05:35:51 PM PDT 24
Peak memory 193080 kb
Host smart-ce207e19-e644-49ea-a2d8-ff151a1019a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616991494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3616991494
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4026370009
Short name T93
Test name
Test status
Simulation time 19897306 ps
CPU time 0.54 seconds
Started Aug 17 05:35:47 PM PDT 24
Finished Aug 17 05:35:47 PM PDT 24
Peak memory 182840 kb
Host smart-322d192c-cdfe-4193-b8ce-ca6380cba1d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026370009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.4026370009
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1308236464
Short name T539
Test name
Test status
Simulation time 30560372 ps
CPU time 0.8 seconds
Started Aug 17 05:35:47 PM PDT 24
Finished Aug 17 05:35:48 PM PDT 24
Peak memory 197464 kb
Host smart-e349c7cf-ddb8-41c3-83c1-9580c7c09eb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308236464 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1308236464
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3620260258
Short name T538
Test name
Test status
Simulation time 34584235 ps
CPU time 0.57 seconds
Started Aug 17 05:35:44 PM PDT 24
Finished Aug 17 05:35:45 PM PDT 24
Peak memory 183356 kb
Host smart-85d1f09b-7172-459e-ac54-21415d447548
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620260258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3620260258
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1310881483
Short name T471
Test name
Test status
Simulation time 30938614 ps
CPU time 0.55 seconds
Started Aug 17 05:35:47 PM PDT 24
Finished Aug 17 05:35:48 PM PDT 24
Peak memory 183280 kb
Host smart-46a919d2-6317-435f-8f8e-c8911df3eebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310881483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1310881483
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1878049187
Short name T582
Test name
Test status
Simulation time 44422279 ps
CPU time 0.99 seconds
Started Aug 17 05:35:47 PM PDT 24
Finished Aug 17 05:35:48 PM PDT 24
Peak memory 196280 kb
Host smart-375cd1f7-8fed-45c1-b188-71399fd32bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878049187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1878049187
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.791178326
Short name T574
Test name
Test status
Simulation time 402076984 ps
CPU time 1.34 seconds
Started Aug 17 05:35:49 PM PDT 24
Finished Aug 17 05:35:51 PM PDT 24
Peak memory 184012 kb
Host smart-f961e59a-c1e4-4e85-9ae5-afd44f7308f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791178326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.791178326
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2402600160
Short name T493
Test name
Test status
Simulation time 34209898 ps
CPU time 0.75 seconds
Started Aug 17 05:35:57 PM PDT 24
Finished Aug 17 05:35:58 PM PDT 24
Peak memory 195556 kb
Host smart-2fdd308a-7cdd-448d-8640-74d09527f171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402600160 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2402600160
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2299761299
Short name T483
Test name
Test status
Simulation time 11925038 ps
CPU time 0.56 seconds
Started Aug 17 05:35:58 PM PDT 24
Finished Aug 17 05:35:59 PM PDT 24
Peak memory 183064 kb
Host smart-282367bb-67df-4cd4-a739-d348d7c7ea4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299761299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2299761299
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3814636374
Short name T547
Test name
Test status
Simulation time 29302258 ps
CPU time 0.52 seconds
Started Aug 17 05:36:00 PM PDT 24
Finished Aug 17 05:36:01 PM PDT 24
Peak memory 182912 kb
Host smart-4165d941-815e-4c34-abcc-31e48dbc7a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814636374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3814636374
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4019434902
Short name T532
Test name
Test status
Simulation time 27155172 ps
CPU time 0.71 seconds
Started Aug 17 05:36:01 PM PDT 24
Finished Aug 17 05:36:02 PM PDT 24
Peak memory 192752 kb
Host smart-ec54acd1-addf-4453-9efb-c9521692a325
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019434902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4019434902
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2216627807
Short name T544
Test name
Test status
Simulation time 333081901 ps
CPU time 1.5 seconds
Started Aug 17 05:36:03 PM PDT 24
Finished Aug 17 05:36:04 PM PDT 24
Peak memory 198100 kb
Host smart-a9318d06-aeda-4604-9437-2dcea7b66a69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216627807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2216627807
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.4263416523
Short name T513
Test name
Test status
Simulation time 165232449 ps
CPU time 0.87 seconds
Started Aug 17 05:36:02 PM PDT 24
Finished Aug 17 05:36:03 PM PDT 24
Peak memory 193968 kb
Host smart-0442c7c1-5218-4792-8cdc-c84e690ddcad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263416523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.4263416523
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.848342040
Short name T521
Test name
Test status
Simulation time 360647973 ps
CPU time 0.85 seconds
Started Aug 17 05:35:58 PM PDT 24
Finished Aug 17 05:35:59 PM PDT 24
Peak memory 197792 kb
Host smart-c8568ff4-da95-4f26-9b08-04def511aa66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848342040 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.848342040
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1653976386
Short name T540
Test name
Test status
Simulation time 24802399 ps
CPU time 0.54 seconds
Started Aug 17 05:35:58 PM PDT 24
Finished Aug 17 05:35:59 PM PDT 24
Peak memory 183284 kb
Host smart-19f7c635-39f0-4b17-a1df-f0721c30ac33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653976386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1653976386
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.414464883
Short name T497
Test name
Test status
Simulation time 14854651 ps
CPU time 0.56 seconds
Started Aug 17 05:36:02 PM PDT 24
Finished Aug 17 05:36:02 PM PDT 24
Peak memory 183172 kb
Host smart-4d530a7c-ee03-4468-a9a8-bbe6dd943614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414464883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.414464883
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2193656208
Short name T53
Test name
Test status
Simulation time 44068675 ps
CPU time 0.75 seconds
Started Aug 17 05:36:01 PM PDT 24
Finished Aug 17 05:36:02 PM PDT 24
Peak memory 193728 kb
Host smart-c3177f2f-1d8d-46a9-b884-a5a755bea0b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193656208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2193656208
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.755144763
Short name T576
Test name
Test status
Simulation time 148710762 ps
CPU time 1.63 seconds
Started Aug 17 05:35:56 PM PDT 24
Finished Aug 17 05:35:58 PM PDT 24
Peak memory 198060 kb
Host smart-c2272b3e-edd5-4f1e-b4df-1832746a4c65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755144763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.755144763
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.269968025
Short name T31
Test name
Test status
Simulation time 61239413 ps
CPU time 0.83 seconds
Started Aug 17 05:35:58 PM PDT 24
Finished Aug 17 05:35:59 PM PDT 24
Peak memory 183860 kb
Host smart-350eb44d-7e23-4e20-8fbe-71a43a283e58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269968025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.269968025
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3054507336
Short name T563
Test name
Test status
Simulation time 33970780 ps
CPU time 0.88 seconds
Started Aug 17 05:36:00 PM PDT 24
Finished Aug 17 05:36:01 PM PDT 24
Peak memory 197220 kb
Host smart-cd1b58a5-2038-49db-8b71-fa33087e1a8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054507336 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3054507336
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.814976556
Short name T85
Test name
Test status
Simulation time 43866794 ps
CPU time 0.61 seconds
Started Aug 17 05:36:01 PM PDT 24
Finished Aug 17 05:36:01 PM PDT 24
Peak memory 183392 kb
Host smart-bfcc1b4f-6184-4db5-a051-580bfe2d3a03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814976556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.814976556
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3808910742
Short name T466
Test name
Test status
Simulation time 29616496 ps
CPU time 0.53 seconds
Started Aug 17 05:35:59 PM PDT 24
Finished Aug 17 05:36:00 PM PDT 24
Peak memory 183140 kb
Host smart-08323e25-08bd-4d2f-b26f-885e5f504aaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808910742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3808910742
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2851810844
Short name T66
Test name
Test status
Simulation time 114943752 ps
CPU time 0.63 seconds
Started Aug 17 05:36:03 PM PDT 24
Finished Aug 17 05:36:04 PM PDT 24
Peak memory 192580 kb
Host smart-d827bf0e-deda-4400-8636-23b9c0b4afff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851810844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2851810844
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.4267093530
Short name T487
Test name
Test status
Simulation time 202098920 ps
CPU time 2.15 seconds
Started Aug 17 05:36:01 PM PDT 24
Finished Aug 17 05:36:03 PM PDT 24
Peak memory 198116 kb
Host smart-82bf8f10-1cd9-48c5-8ec5-81bda43b72ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267093530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.4267093530
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.642793050
Short name T548
Test name
Test status
Simulation time 159719482 ps
CPU time 1.15 seconds
Started Aug 17 05:36:01 PM PDT 24
Finished Aug 17 05:36:03 PM PDT 24
Peak memory 195208 kb
Host smart-751d1241-095c-446d-b57a-56ecffd61ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642793050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.642793050
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1143772087
Short name T525
Test name
Test status
Simulation time 62654471 ps
CPU time 0.64 seconds
Started Aug 17 05:35:59 PM PDT 24
Finished Aug 17 05:36:00 PM PDT 24
Peak memory 194452 kb
Host smart-bcdd3c2e-868d-4da0-8f7e-af282e98e624
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143772087 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1143772087
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1171464261
Short name T80
Test name
Test status
Simulation time 26898475 ps
CPU time 0.59 seconds
Started Aug 17 05:35:57 PM PDT 24
Finished Aug 17 05:35:58 PM PDT 24
Peak memory 192572 kb
Host smart-aca51ccc-f240-4010-9fd9-705889a78da7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171464261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1171464261
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3444684619
Short name T573
Test name
Test status
Simulation time 78140761 ps
CPU time 0.55 seconds
Started Aug 17 05:35:58 PM PDT 24
Finished Aug 17 05:35:58 PM PDT 24
Peak memory 183196 kb
Host smart-ac39a767-7ac4-4ca6-90b8-40b3229c5522
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444684619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3444684619
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2658248657
Short name T55
Test name
Test status
Simulation time 44611493 ps
CPU time 0.84 seconds
Started Aug 17 05:36:00 PM PDT 24
Finished Aug 17 05:36:01 PM PDT 24
Peak memory 194028 kb
Host smart-5c549952-576a-4572-a03c-9ec4b3086bb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658248657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2658248657
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2967131776
Short name T54
Test name
Test status
Simulation time 775604222 ps
CPU time 3.15 seconds
Started Aug 17 05:35:59 PM PDT 24
Finished Aug 17 05:36:02 PM PDT 24
Peak memory 198112 kb
Host smart-e52be1a7-1e97-434e-9d73-6f958116d423
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967131776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2967131776
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.310195006
Short name T56
Test name
Test status
Simulation time 30273518 ps
CPU time 0.77 seconds
Started Aug 17 05:35:58 PM PDT 24
Finished Aug 17 05:35:59 PM PDT 24
Peak memory 195912 kb
Host smart-60cfc40a-428c-46ad-a8d6-faca5b729583
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310195006 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.310195006
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1764000947
Short name T542
Test name
Test status
Simulation time 14137335 ps
CPU time 0.57 seconds
Started Aug 17 05:36:00 PM PDT 24
Finished Aug 17 05:36:01 PM PDT 24
Peak memory 183368 kb
Host smart-6a47e8c0-3b43-407c-b5fc-97f159f4dfc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764000947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1764000947
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3116329375
Short name T506
Test name
Test status
Simulation time 15075785 ps
CPU time 0.54 seconds
Started Aug 17 05:35:59 PM PDT 24
Finished Aug 17 05:36:00 PM PDT 24
Peak memory 183204 kb
Host smart-32301e5b-bb80-47bc-9794-58302b252b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116329375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3116329375
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2873276370
Short name T550
Test name
Test status
Simulation time 95374432 ps
CPU time 0.69 seconds
Started Aug 17 05:35:58 PM PDT 24
Finished Aug 17 05:35:59 PM PDT 24
Peak memory 193756 kb
Host smart-20bb13a5-f72b-4a73-b6db-3c34956f032c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873276370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2873276370
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.4069513064
Short name T553
Test name
Test status
Simulation time 197921748 ps
CPU time 2.06 seconds
Started Aug 17 05:36:02 PM PDT 24
Finished Aug 17 05:36:04 PM PDT 24
Peak memory 198212 kb
Host smart-0ff02ede-a793-4760-b611-1b66a0362a8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069513064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.4069513064
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.249610844
Short name T30
Test name
Test status
Simulation time 540800398 ps
CPU time 1.28 seconds
Started Aug 17 05:35:57 PM PDT 24
Finished Aug 17 05:35:59 PM PDT 24
Peak memory 195952 kb
Host smart-d1b2e1aa-54f2-4750-b3c3-4c37537b5c25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249610844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.249610844
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2805088308
Short name T482
Test name
Test status
Simulation time 35395799 ps
CPU time 0.64 seconds
Started Aug 17 05:36:08 PM PDT 24
Finished Aug 17 05:36:09 PM PDT 24
Peak memory 194432 kb
Host smart-54173e82-15cc-463b-80d3-8b386e2cac01
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805088308 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2805088308
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2844744812
Short name T89
Test name
Test status
Simulation time 31578758 ps
CPU time 0.54 seconds
Started Aug 17 05:36:06 PM PDT 24
Finished Aug 17 05:36:06 PM PDT 24
Peak memory 183348 kb
Host smart-42ed2d20-415a-4a5b-b32b-d9a7a28597a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844744812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2844744812
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.4151991603
Short name T551
Test name
Test status
Simulation time 39833751 ps
CPU time 0.53 seconds
Started Aug 17 05:36:10 PM PDT 24
Finished Aug 17 05:36:11 PM PDT 24
Peak memory 182656 kb
Host smart-d2296319-8c73-4d5c-8545-20476d8746ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151991603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.4151991603
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.4240685927
Short name T508
Test name
Test status
Simulation time 72887920 ps
CPU time 0.8 seconds
Started Aug 17 05:36:11 PM PDT 24
Finished Aug 17 05:36:12 PM PDT 24
Peak memory 194056 kb
Host smart-e6c242f0-7def-42d2-b707-8b9e149615f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240685927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.4240685927
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1151015659
Short name T565
Test name
Test status
Simulation time 158332512 ps
CPU time 1.21 seconds
Started Aug 17 05:36:07 PM PDT 24
Finished Aug 17 05:36:08 PM PDT 24
Peak memory 198096 kb
Host smart-939d4dc1-2c1f-4562-8d05-e46555eb30d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151015659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1151015659
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1768894338
Short name T511
Test name
Test status
Simulation time 93922419 ps
CPU time 0.77 seconds
Started Aug 17 05:36:09 PM PDT 24
Finished Aug 17 05:36:10 PM PDT 24
Peak memory 183672 kb
Host smart-17133bd7-5609-408a-bcad-71dc0734c918
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768894338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1768894338
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1857005403
Short name T468
Test name
Test status
Simulation time 25785978 ps
CPU time 1.18 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:36:15 PM PDT 24
Peak memory 198140 kb
Host smart-8f41d96b-4578-4cfa-8deb-a3e0bc18bb02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857005403 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1857005403
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3974788898
Short name T84
Test name
Test status
Simulation time 39377483 ps
CPU time 0.55 seconds
Started Aug 17 05:36:06 PM PDT 24
Finished Aug 17 05:36:07 PM PDT 24
Peak memory 183340 kb
Host smart-3bba3c89-998d-43bc-8f3a-8bd3248ae192
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974788898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3974788898
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2279051903
Short name T559
Test name
Test status
Simulation time 13446826 ps
CPU time 0.53 seconds
Started Aug 17 05:36:07 PM PDT 24
Finished Aug 17 05:36:08 PM PDT 24
Peak memory 183152 kb
Host smart-1737f4ac-431a-44a6-a6d1-ddf1045a21ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279051903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2279051903
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.483280623
Short name T578
Test name
Test status
Simulation time 155202090 ps
CPU time 0.83 seconds
Started Aug 17 05:36:10 PM PDT 24
Finished Aug 17 05:36:10 PM PDT 24
Peak memory 192360 kb
Host smart-b0208f33-f54f-4e37-bda2-06a4f79668bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483280623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.483280623
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3022383662
Short name T518
Test name
Test status
Simulation time 57624533 ps
CPU time 1.32 seconds
Started Aug 17 05:36:07 PM PDT 24
Finished Aug 17 05:36:08 PM PDT 24
Peak memory 198028 kb
Host smart-c79f2a68-8610-460b-808b-8dbed582443d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022383662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3022383662
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2621511725
Short name T575
Test name
Test status
Simulation time 180002096 ps
CPU time 0.81 seconds
Started Aug 17 05:36:05 PM PDT 24
Finished Aug 17 05:36:06 PM PDT 24
Peak memory 194284 kb
Host smart-c4126826-6ee5-4ea8-8caa-f67a21a6a118
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621511725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2621511725
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.645070446
Short name T567
Test name
Test status
Simulation time 84663753 ps
CPU time 0.98 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:36:15 PM PDT 24
Peak memory 198012 kb
Host smart-37597276-e091-4eba-a4e7-f5f6a3c3649b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645070446 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.645070446
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.785252904
Short name T82
Test name
Test status
Simulation time 35216854 ps
CPU time 0.57 seconds
Started Aug 17 05:36:07 PM PDT 24
Finished Aug 17 05:36:07 PM PDT 24
Peak memory 183248 kb
Host smart-61fa81e5-64c3-4e19-b22f-99e3393bd588
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785252904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.785252904
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.914541596
Short name T459
Test name
Test status
Simulation time 13619417 ps
CPU time 0.54 seconds
Started Aug 17 05:36:08 PM PDT 24
Finished Aug 17 05:36:09 PM PDT 24
Peak memory 183224 kb
Host smart-918ed834-0524-46f9-8b1e-245f0c6d4b42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914541596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.914541596
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.28374864
Short name T498
Test name
Test status
Simulation time 27206095 ps
CPU time 0.7 seconds
Started Aug 17 05:36:08 PM PDT 24
Finished Aug 17 05:36:09 PM PDT 24
Peak memory 193784 kb
Host smart-40da0eae-7f35-446e-8165-4632d72cd459
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28374864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_tim
er_same_csr_outstanding.28374864
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2169925718
Short name T533
Test name
Test status
Simulation time 469092480 ps
CPU time 2.39 seconds
Started Aug 17 05:36:10 PM PDT 24
Finished Aug 17 05:36:13 PM PDT 24
Peak memory 198080 kb
Host smart-7f1f4fca-051d-47a5-a776-9493d232fc3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169925718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2169925718
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4192524466
Short name T501
Test name
Test status
Simulation time 33831626 ps
CPU time 1.55 seconds
Started Aug 17 05:36:15 PM PDT 24
Finished Aug 17 05:36:16 PM PDT 24
Peak memory 198144 kb
Host smart-7e6ce80e-08e3-4bc6-9e88-3f1158370666
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192524466 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4192524466
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.253208774
Short name T87
Test name
Test status
Simulation time 16907535 ps
CPU time 0.59 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:36:14 PM PDT 24
Peak memory 183372 kb
Host smart-2f30b1c8-c0f3-4a6a-bcb7-5d49860b773f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253208774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.253208774
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2898225350
Short name T570
Test name
Test status
Simulation time 14455596 ps
CPU time 0.53 seconds
Started Aug 17 05:36:06 PM PDT 24
Finished Aug 17 05:36:06 PM PDT 24
Peak memory 183252 kb
Host smart-4cd4a41c-b76b-439c-ac33-6cb5f1cd7373
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898225350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2898225350
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3295626890
Short name T512
Test name
Test status
Simulation time 68167199 ps
CPU time 0.81 seconds
Started Aug 17 05:36:07 PM PDT 24
Finished Aug 17 05:36:08 PM PDT 24
Peak memory 192308 kb
Host smart-f95b14c2-e7db-45d7-9123-1ba8f1731d70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295626890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3295626890
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3369296372
Short name T499
Test name
Test status
Simulation time 32773207 ps
CPU time 1.45 seconds
Started Aug 17 05:36:05 PM PDT 24
Finished Aug 17 05:36:07 PM PDT 24
Peak memory 198144 kb
Host smart-223f9432-20c1-4eaa-b7c9-5bf82760aba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369296372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3369296372
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1023884460
Short name T489
Test name
Test status
Simulation time 121663045 ps
CPU time 1.28 seconds
Started Aug 17 05:36:05 PM PDT 24
Finished Aug 17 05:36:06 PM PDT 24
Peak memory 196164 kb
Host smart-bc393502-0338-4901-8fe6-74418a4573f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023884460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1023884460
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2535087641
Short name T67
Test name
Test status
Simulation time 435040520 ps
CPU time 0.82 seconds
Started Aug 17 05:36:10 PM PDT 24
Finished Aug 17 05:36:11 PM PDT 24
Peak memory 197088 kb
Host smart-aa453f6c-fccc-4893-9522-947dc2e83938
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535087641 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2535087641
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1144799424
Short name T78
Test name
Test status
Simulation time 18435903 ps
CPU time 0.52 seconds
Started Aug 17 05:36:06 PM PDT 24
Finished Aug 17 05:36:07 PM PDT 24
Peak memory 183348 kb
Host smart-4e7bd3bb-898d-4f42-b0cf-cfc81923c60f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144799424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1144799424
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3019775076
Short name T554
Test name
Test status
Simulation time 14545754 ps
CPU time 0.55 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:36:15 PM PDT 24
Peak memory 182720 kb
Host smart-1d5aac26-ceb5-409f-9b8c-a31ffc6ecc4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019775076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3019775076
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.855077663
Short name T76
Test name
Test status
Simulation time 20020702 ps
CPU time 0.76 seconds
Started Aug 17 05:36:07 PM PDT 24
Finished Aug 17 05:36:07 PM PDT 24
Peak memory 194160 kb
Host smart-327bc5a0-6c4d-4b47-ade2-2cb9e140568b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855077663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.855077663
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3676043203
Short name T566
Test name
Test status
Simulation time 76141797 ps
CPU time 2.15 seconds
Started Aug 17 05:36:06 PM PDT 24
Finished Aug 17 05:36:08 PM PDT 24
Peak memory 198104 kb
Host smart-007fbd66-312e-43b2-8b95-76462675381b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676043203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3676043203
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.582221966
Short name T557
Test name
Test status
Simulation time 286616947 ps
CPU time 1.09 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:36:15 PM PDT 24
Peak memory 195572 kb
Host smart-4b0cd8d9-cc01-46ef-af48-0d8ead7fb9b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582221966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.582221966
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1190925577
Short name T492
Test name
Test status
Simulation time 52686007 ps
CPU time 0.69 seconds
Started Aug 17 05:35:44 PM PDT 24
Finished Aug 17 05:35:45 PM PDT 24
Peak memory 183252 kb
Host smart-dd61f3f7-4329-4a0d-a414-ac2a7869a6ec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190925577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1190925577
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1279439673
Short name T519
Test name
Test status
Simulation time 125400807 ps
CPU time 2.29 seconds
Started Aug 17 05:35:47 PM PDT 24
Finished Aug 17 05:35:49 PM PDT 24
Peak memory 193384 kb
Host smart-fcceed6f-8bf3-4803-b805-226830f9c873
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279439673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1279439673
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3565487702
Short name T79
Test name
Test status
Simulation time 18434524 ps
CPU time 0.57 seconds
Started Aug 17 05:35:45 PM PDT 24
Finished Aug 17 05:35:46 PM PDT 24
Peak memory 183308 kb
Host smart-7c65bd0c-d326-471d-8907-0eebe7c65115
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565487702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3565487702
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.56923577
Short name T568
Test name
Test status
Simulation time 29868853 ps
CPU time 0.62 seconds
Started Aug 17 05:35:45 PM PDT 24
Finished Aug 17 05:35:46 PM PDT 24
Peak memory 194280 kb
Host smart-a5460363-6d5a-460c-835f-54c3166c33dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56923577 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.56923577
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.461196126
Short name T510
Test name
Test status
Simulation time 16980931 ps
CPU time 0.55 seconds
Started Aug 17 05:35:46 PM PDT 24
Finished Aug 17 05:35:47 PM PDT 24
Peak memory 183364 kb
Host smart-159c11b1-56e0-4f5c-899b-07cdb4d46646
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461196126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.461196126
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1861433169
Short name T556
Test name
Test status
Simulation time 19757466 ps
CPU time 0.56 seconds
Started Aug 17 05:35:46 PM PDT 24
Finished Aug 17 05:35:47 PM PDT 24
Peak memory 183260 kb
Host smart-f2c81e31-f037-4621-a88c-a4dc04d25746
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861433169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1861433169
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2286193882
Short name T33
Test name
Test status
Simulation time 18194917 ps
CPU time 0.61 seconds
Started Aug 17 05:35:47 PM PDT 24
Finished Aug 17 05:35:48 PM PDT 24
Peak memory 192212 kb
Host smart-cf6c982a-a017-4a00-89fc-804f48619ffe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286193882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2286193882
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.463714981
Short name T461
Test name
Test status
Simulation time 47619678 ps
CPU time 2.19 seconds
Started Aug 17 05:35:49 PM PDT 24
Finished Aug 17 05:35:51 PM PDT 24
Peak memory 198168 kb
Host smart-14034cbd-f770-4eff-87c5-2ba9ce7c267d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463714981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.463714981
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1441246145
Short name T496
Test name
Test status
Simulation time 45509541 ps
CPU time 0.82 seconds
Started Aug 17 05:35:48 PM PDT 24
Finished Aug 17 05:35:49 PM PDT 24
Peak memory 194300 kb
Host smart-9a6622fd-55f5-4f4f-9cbc-e2cd3ef97d3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441246145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1441246145
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3663928207
Short name T460
Test name
Test status
Simulation time 17757727 ps
CPU time 0.56 seconds
Started Aug 17 05:36:07 PM PDT 24
Finished Aug 17 05:36:08 PM PDT 24
Peak memory 183212 kb
Host smart-4c9a6404-2590-4f51-89cc-043d29a7f6c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663928207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3663928207
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2943226035
Short name T463
Test name
Test status
Simulation time 17005041 ps
CPU time 0.59 seconds
Started Aug 17 05:36:11 PM PDT 24
Finished Aug 17 05:36:11 PM PDT 24
Peak memory 183188 kb
Host smart-4b24fc47-1d1e-4a74-8510-ab2c7e6983ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943226035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2943226035
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.197047713
Short name T474
Test name
Test status
Simulation time 18029594 ps
CPU time 0.57 seconds
Started Aug 17 05:36:06 PM PDT 24
Finished Aug 17 05:36:07 PM PDT 24
Peak memory 183228 kb
Host smart-1ccd0c57-d60c-4931-a98c-5471ab837813
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197047713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.197047713
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.4015449555
Short name T475
Test name
Test status
Simulation time 14891614 ps
CPU time 0.54 seconds
Started Aug 17 05:36:06 PM PDT 24
Finished Aug 17 05:36:07 PM PDT 24
Peak memory 182660 kb
Host smart-79614446-3ccf-4fe9-85db-97434c853901
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015449555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.4015449555
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1413213811
Short name T477
Test name
Test status
Simulation time 13903637 ps
CPU time 0.55 seconds
Started Aug 17 05:36:08 PM PDT 24
Finished Aug 17 05:36:08 PM PDT 24
Peak memory 183312 kb
Host smart-ea1ef9c5-1e23-4799-8974-813643c132ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413213811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1413213811
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3665962217
Short name T495
Test name
Test status
Simulation time 15750070 ps
CPU time 0.57 seconds
Started Aug 17 05:36:07 PM PDT 24
Finished Aug 17 05:36:08 PM PDT 24
Peak memory 183304 kb
Host smart-89190665-7e05-4d2c-9fe5-5933996c60aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665962217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3665962217
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1135885800
Short name T528
Test name
Test status
Simulation time 16485655 ps
CPU time 0.54 seconds
Started Aug 17 05:36:18 PM PDT 24
Finished Aug 17 05:36:19 PM PDT 24
Peak memory 182672 kb
Host smart-8debce6f-a98d-48c3-842b-e715651bd4d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135885800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1135885800
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2640623486
Short name T543
Test name
Test status
Simulation time 11696616 ps
CPU time 0.55 seconds
Started Aug 17 05:36:13 PM PDT 24
Finished Aug 17 05:36:14 PM PDT 24
Peak memory 183140 kb
Host smart-8267996f-b684-47c1-b837-70325ee7d517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640623486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2640623486
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2350967996
Short name T560
Test name
Test status
Simulation time 18753303 ps
CPU time 0.54 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:36:15 PM PDT 24
Peak memory 183216 kb
Host smart-df3d8acd-9791-4854-a707-b73d06aec2e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350967996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2350967996
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2687444053
Short name T522
Test name
Test status
Simulation time 65453999 ps
CPU time 0.55 seconds
Started Aug 17 05:36:13 PM PDT 24
Finished Aug 17 05:36:14 PM PDT 24
Peak memory 183220 kb
Host smart-66de4b5f-e0a8-4d62-ba2c-9de6f25b2ab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687444053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2687444053
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2107969855
Short name T81
Test name
Test status
Simulation time 58700515 ps
CPU time 0.8 seconds
Started Aug 17 05:35:50 PM PDT 24
Finished Aug 17 05:35:50 PM PDT 24
Peak memory 193216 kb
Host smart-1fa8c482-5ce3-4814-be4c-74bad7fe468e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107969855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2107969855
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2853239352
Short name T507
Test name
Test status
Simulation time 291053211 ps
CPU time 3.51 seconds
Started Aug 17 05:35:51 PM PDT 24
Finished Aug 17 05:35:54 PM PDT 24
Peak memory 191656 kb
Host smart-67e5b3ed-e5aa-48b9-89cb-0e10a3ef8568
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853239352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2853239352
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3224183675
Short name T32
Test name
Test status
Simulation time 15268930 ps
CPU time 0.54 seconds
Started Aug 17 05:35:47 PM PDT 24
Finished Aug 17 05:35:47 PM PDT 24
Peak memory 182804 kb
Host smart-44454804-c7e1-4e20-b3d3-332dc0006712
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224183675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3224183675
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.890628266
Short name T476
Test name
Test status
Simulation time 74831649 ps
CPU time 0.91 seconds
Started Aug 17 05:35:49 PM PDT 24
Finished Aug 17 05:35:50 PM PDT 24
Peak memory 197988 kb
Host smart-4f049bf6-463f-41af-b8fa-a34777ef48ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890628266 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.890628266
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1814058898
Short name T478
Test name
Test status
Simulation time 31266613 ps
CPU time 0.56 seconds
Started Aug 17 05:35:49 PM PDT 24
Finished Aug 17 05:35:50 PM PDT 24
Peak memory 183388 kb
Host smart-6909ddf7-462c-4793-bb7f-50fdc837099a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814058898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1814058898
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1124841876
Short name T503
Test name
Test status
Simulation time 116516399 ps
CPU time 0.55 seconds
Started Aug 17 05:35:45 PM PDT 24
Finished Aug 17 05:35:46 PM PDT 24
Peak memory 183204 kb
Host smart-fd98bc96-f63d-429c-a3a3-e077b34e6337
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124841876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1124841876
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2000194579
Short name T581
Test name
Test status
Simulation time 64533922 ps
CPU time 0.67 seconds
Started Aug 17 05:35:47 PM PDT 24
Finished Aug 17 05:35:48 PM PDT 24
Peak memory 193776 kb
Host smart-8a0cf145-73d6-472a-84e1-829ef517ec7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000194579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2000194579
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.162734261
Short name T479
Test name
Test status
Simulation time 869873467 ps
CPU time 2.81 seconds
Started Aug 17 05:35:47 PM PDT 24
Finished Aug 17 05:35:50 PM PDT 24
Peak memory 198080 kb
Host smart-8dfba194-7808-4eca-8cc4-150d6f416814
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162734261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.162734261
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1143118535
Short name T97
Test name
Test status
Simulation time 112397552 ps
CPU time 1.46 seconds
Started Aug 17 05:35:50 PM PDT 24
Finished Aug 17 05:35:52 PM PDT 24
Peak memory 195832 kb
Host smart-f769008a-88fc-4672-ada7-e502acbaf6ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143118535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1143118535
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3132103626
Short name T509
Test name
Test status
Simulation time 29325071 ps
CPU time 0.56 seconds
Started Aug 17 05:36:17 PM PDT 24
Finished Aug 17 05:36:18 PM PDT 24
Peak memory 183192 kb
Host smart-d2f33a58-9f82-4ebf-9448-1f551eed5af9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132103626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3132103626
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.592161318
Short name T534
Test name
Test status
Simulation time 16623887 ps
CPU time 0.55 seconds
Started Aug 17 05:36:17 PM PDT 24
Finished Aug 17 05:36:17 PM PDT 24
Peak memory 183152 kb
Host smart-84e88891-b22b-4e6a-a6f1-574c7dab5ff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592161318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.592161318
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4259693132
Short name T488
Test name
Test status
Simulation time 37985048 ps
CPU time 0.56 seconds
Started Aug 17 05:36:17 PM PDT 24
Finished Aug 17 05:36:18 PM PDT 24
Peak memory 183212 kb
Host smart-98b1f56a-f7b1-4c97-bc67-527a852a82ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259693132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4259693132
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2254435909
Short name T504
Test name
Test status
Simulation time 17827002 ps
CPU time 0.59 seconds
Started Aug 17 05:36:18 PM PDT 24
Finished Aug 17 05:36:19 PM PDT 24
Peak memory 183112 kb
Host smart-7de25add-0dbe-40e8-a6f4-4fd9221baa96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254435909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2254435909
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3049870642
Short name T480
Test name
Test status
Simulation time 12436378 ps
CPU time 0.57 seconds
Started Aug 17 05:36:13 PM PDT 24
Finished Aug 17 05:36:14 PM PDT 24
Peak memory 182652 kb
Host smart-8ddb8f1f-ea88-4d02-9a5a-6fe396e43936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049870642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3049870642
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3892702711
Short name T494
Test name
Test status
Simulation time 33335422 ps
CPU time 0.56 seconds
Started Aug 17 05:36:20 PM PDT 24
Finished Aug 17 05:36:20 PM PDT 24
Peak memory 183280 kb
Host smart-16a385e5-f7f2-406b-9c48-c9b9ed1fbd1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892702711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3892702711
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1672278955
Short name T470
Test name
Test status
Simulation time 257520553 ps
CPU time 0.58 seconds
Started Aug 17 05:36:15 PM PDT 24
Finished Aug 17 05:36:16 PM PDT 24
Peak memory 183280 kb
Host smart-4a4fc1bd-9065-4940-add8-e0156bbfb166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672278955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1672278955
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.271224092
Short name T549
Test name
Test status
Simulation time 43027271 ps
CPU time 0.53 seconds
Started Aug 17 05:36:15 PM PDT 24
Finished Aug 17 05:36:16 PM PDT 24
Peak memory 183236 kb
Host smart-a8ec7200-02b3-4d1d-9abe-3aa3f181e6af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271224092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.271224092
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.244576556
Short name T486
Test name
Test status
Simulation time 34736643 ps
CPU time 0.55 seconds
Started Aug 17 05:36:17 PM PDT 24
Finished Aug 17 05:36:18 PM PDT 24
Peak memory 183292 kb
Host smart-cb7c51c8-9148-4342-8751-576d4c3f0bc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244576556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.244576556
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2492611120
Short name T481
Test name
Test status
Simulation time 14889388 ps
CPU time 0.56 seconds
Started Aug 17 05:36:15 PM PDT 24
Finished Aug 17 05:36:16 PM PDT 24
Peak memory 183216 kb
Host smart-7552d2ed-e570-4c96-b04f-d47bc86533dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492611120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2492611120
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.93113670
Short name T500
Test name
Test status
Simulation time 44106934 ps
CPU time 0.67 seconds
Started Aug 17 05:35:51 PM PDT 24
Finished Aug 17 05:35:51 PM PDT 24
Peak memory 183292 kb
Host smart-43bdf7cb-1633-444c-acfd-65da20ffc240
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93113670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasi
ng.93113670
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.678767231
Short name T523
Test name
Test status
Simulation time 476131485 ps
CPU time 3.04 seconds
Started Aug 17 05:35:55 PM PDT 24
Finished Aug 17 05:35:58 PM PDT 24
Peak memory 193096 kb
Host smart-ff6a9f05-e361-4851-bb90-0b5441058814
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678767231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.678767231
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3987584877
Short name T530
Test name
Test status
Simulation time 20057308 ps
CPU time 0.93 seconds
Started Aug 17 05:35:52 PM PDT 24
Finished Aug 17 05:35:53 PM PDT 24
Peak memory 197148 kb
Host smart-fae84105-08dd-4507-ad4e-143cbccf20f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987584877 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3987584877
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.912845111
Short name T541
Test name
Test status
Simulation time 14375486 ps
CPU time 0.57 seconds
Started Aug 17 05:35:47 PM PDT 24
Finished Aug 17 05:35:47 PM PDT 24
Peak memory 183024 kb
Host smart-3597809c-47dd-4118-a374-c84b1f1d1489
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912845111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.912845111
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2578634187
Short name T465
Test name
Test status
Simulation time 39253983 ps
CPU time 0.56 seconds
Started Aug 17 05:35:46 PM PDT 24
Finished Aug 17 05:35:47 PM PDT 24
Peak memory 183188 kb
Host smart-76786e63-f0cc-45e0-8171-ca47001d2bc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578634187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2578634187
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3787452886
Short name T34
Test name
Test status
Simulation time 76846934 ps
CPU time 0.61 seconds
Started Aug 17 05:35:51 PM PDT 24
Finished Aug 17 05:35:53 PM PDT 24
Peak memory 192144 kb
Host smart-614daa6c-7fee-4c35-bd60-691f0094991d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787452886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3787452886
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2987152203
Short name T473
Test name
Test status
Simulation time 65765742 ps
CPU time 2.51 seconds
Started Aug 17 05:35:47 PM PDT 24
Finished Aug 17 05:35:49 PM PDT 24
Peak memory 198156 kb
Host smart-e3aa1e80-11f5-4d29-b094-cfe9849f6aa2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987152203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2987152203
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1849080615
Short name T98
Test name
Test status
Simulation time 422362409 ps
CPU time 1.38 seconds
Started Aug 17 05:35:49 PM PDT 24
Finished Aug 17 05:35:51 PM PDT 24
Peak memory 183712 kb
Host smart-cc8b24f2-6de5-40b5-bd0d-797c0becff91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849080615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1849080615
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3295400376
Short name T490
Test name
Test status
Simulation time 24204015 ps
CPU time 0.56 seconds
Started Aug 17 05:36:13 PM PDT 24
Finished Aug 17 05:36:14 PM PDT 24
Peak memory 183200 kb
Host smart-b5a19075-b827-4a85-83af-c6266918e6ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295400376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3295400376
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.128603303
Short name T502
Test name
Test status
Simulation time 37526393 ps
CPU time 0.54 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:36:15 PM PDT 24
Peak memory 183216 kb
Host smart-f951d6b0-7c2e-4b7f-8616-bb117a0b8129
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128603303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.128603303
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2517458160
Short name T469
Test name
Test status
Simulation time 14639063 ps
CPU time 0.55 seconds
Started Aug 17 05:36:20 PM PDT 24
Finished Aug 17 05:36:20 PM PDT 24
Peak memory 182708 kb
Host smart-2527a973-5daa-4c75-bf37-65ff664c541c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517458160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2517458160
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2659611795
Short name T552
Test name
Test status
Simulation time 11931552 ps
CPU time 0.54 seconds
Started Aug 17 05:36:15 PM PDT 24
Finished Aug 17 05:36:16 PM PDT 24
Peak memory 182740 kb
Host smart-5191cff5-38e0-4a92-b632-c3baa7f0cf0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659611795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2659611795
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3773078986
Short name T458
Test name
Test status
Simulation time 16807432 ps
CPU time 0.56 seconds
Started Aug 17 05:36:17 PM PDT 24
Finished Aug 17 05:36:18 PM PDT 24
Peak memory 183276 kb
Host smart-884573af-3165-42d1-8bcf-d44d6bc06846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773078986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3773078986
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2356246359
Short name T464
Test name
Test status
Simulation time 47169492 ps
CPU time 0.56 seconds
Started Aug 17 05:36:18 PM PDT 24
Finished Aug 17 05:36:19 PM PDT 24
Peak memory 183100 kb
Host smart-338afcbf-201f-4b0d-b06f-f3c2ce505638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356246359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2356246359
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.868011989
Short name T555
Test name
Test status
Simulation time 17981910 ps
CPU time 0.59 seconds
Started Aug 17 05:36:13 PM PDT 24
Finished Aug 17 05:36:14 PM PDT 24
Peak memory 183260 kb
Host smart-75f16d73-2776-4a57-b87c-b3db8dd48875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868011989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.868011989
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.262700811
Short name T472
Test name
Test status
Simulation time 17342296 ps
CPU time 0.57 seconds
Started Aug 17 05:36:20 PM PDT 24
Finished Aug 17 05:36:20 PM PDT 24
Peak memory 183188 kb
Host smart-43cd2648-2115-4bdc-8244-e03da83d2884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262700811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.262700811
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.387057045
Short name T569
Test name
Test status
Simulation time 31480467 ps
CPU time 0.54 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:36:14 PM PDT 24
Peak memory 182636 kb
Host smart-a6d0d4d4-01a0-40af-94be-a4fad292f124
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387057045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.387057045
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3518203937
Short name T579
Test name
Test status
Simulation time 15020285 ps
CPU time 0.53 seconds
Started Aug 17 05:36:17 PM PDT 24
Finished Aug 17 05:36:18 PM PDT 24
Peak memory 182908 kb
Host smart-ccfbd590-72f2-49ba-9c36-f6e3dd829d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518203937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3518203937
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2318982827
Short name T485
Test name
Test status
Simulation time 49141644 ps
CPU time 0.61 seconds
Started Aug 17 05:35:53 PM PDT 24
Finished Aug 17 05:35:54 PM PDT 24
Peak memory 193812 kb
Host smart-1f771f2b-9f2f-45b1-b277-a4942572f85c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318982827 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2318982827
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2665631786
Short name T88
Test name
Test status
Simulation time 11385115 ps
CPU time 0.54 seconds
Started Aug 17 05:35:54 PM PDT 24
Finished Aug 17 05:35:55 PM PDT 24
Peak memory 183064 kb
Host smart-4443e10b-e91e-4ea7-9390-ce857c5c0e52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665631786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2665631786
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1947094103
Short name T536
Test name
Test status
Simulation time 15618599 ps
CPU time 0.54 seconds
Started Aug 17 05:35:51 PM PDT 24
Finished Aug 17 05:35:52 PM PDT 24
Peak memory 182920 kb
Host smart-9b1e0e7f-081a-4055-a3f9-e456969b0fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947094103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1947094103
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2102254876
Short name T531
Test name
Test status
Simulation time 41148699 ps
CPU time 0.81 seconds
Started Aug 17 05:35:52 PM PDT 24
Finished Aug 17 05:35:53 PM PDT 24
Peak memory 191564 kb
Host smart-91cd5ed6-131b-48a9-b872-fea674d07140
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102254876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2102254876
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.723789611
Short name T68
Test name
Test status
Simulation time 104528290 ps
CPU time 1.84 seconds
Started Aug 17 05:35:54 PM PDT 24
Finished Aug 17 05:35:56 PM PDT 24
Peak memory 198140 kb
Host smart-745592cc-7cb1-4e4b-8ade-8709197bbd36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723789611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.723789611
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.809213156
Short name T484
Test name
Test status
Simulation time 144943917 ps
CPU time 0.8 seconds
Started Aug 17 05:35:55 PM PDT 24
Finished Aug 17 05:35:56 PM PDT 24
Peak memory 194140 kb
Host smart-30f0e239-210c-4b41-8ba1-37535e4aa30b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809213156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.809213156
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1579972782
Short name T516
Test name
Test status
Simulation time 30937410 ps
CPU time 0.91 seconds
Started Aug 17 05:35:51 PM PDT 24
Finished Aug 17 05:35:52 PM PDT 24
Peak memory 197776 kb
Host smart-d43400f4-26a2-4e5c-a365-b4de65b15530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579972782 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1579972782
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1663513322
Short name T517
Test name
Test status
Simulation time 15356944 ps
CPU time 0.62 seconds
Started Aug 17 05:35:54 PM PDT 24
Finished Aug 17 05:35:55 PM PDT 24
Peak memory 183336 kb
Host smart-589f1c8b-f064-479b-a59b-b19b4d1eb57e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663513322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1663513322
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2335910125
Short name T457
Test name
Test status
Simulation time 14603810 ps
CPU time 0.55 seconds
Started Aug 17 05:35:51 PM PDT 24
Finished Aug 17 05:35:53 PM PDT 24
Peak memory 183168 kb
Host smart-910ded5e-d160-42fb-aa11-b909ec1e2304
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335910125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2335910125
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.436053953
Short name T505
Test name
Test status
Simulation time 14624566 ps
CPU time 0.63 seconds
Started Aug 17 05:35:55 PM PDT 24
Finished Aug 17 05:35:56 PM PDT 24
Peak memory 192160 kb
Host smart-a1f5ea42-2a7f-4b37-9337-063ca5cc52f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436053953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.436053953
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3470529912
Short name T571
Test name
Test status
Simulation time 192707091 ps
CPU time 1.05 seconds
Started Aug 17 05:35:51 PM PDT 24
Finished Aug 17 05:35:53 PM PDT 24
Peak memory 191768 kb
Host smart-2d83f30c-1f35-447e-ad81-1d385a1b98de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470529912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3470529912
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.964461896
Short name T96
Test name
Test status
Simulation time 84054927 ps
CPU time 1.07 seconds
Started Aug 17 05:35:52 PM PDT 24
Finished Aug 17 05:35:53 PM PDT 24
Peak memory 184028 kb
Host smart-07a69084-a199-4478-b6d4-5dec8b2c3d25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964461896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.964461896
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3328982241
Short name T577
Test name
Test status
Simulation time 27280752 ps
CPU time 0.79 seconds
Started Aug 17 05:35:52 PM PDT 24
Finished Aug 17 05:35:53 PM PDT 24
Peak memory 195916 kb
Host smart-b0e4fc26-ef29-47e4-8dfc-aed7ef79db5c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328982241 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3328982241
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3461330006
Short name T537
Test name
Test status
Simulation time 19799281 ps
CPU time 0.58 seconds
Started Aug 17 05:35:52 PM PDT 24
Finished Aug 17 05:35:53 PM PDT 24
Peak memory 183288 kb
Host smart-ea475890-d1ba-4a62-ab5e-99f2070fd4f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461330006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3461330006
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1872073003
Short name T527
Test name
Test status
Simulation time 77669916 ps
CPU time 0.54 seconds
Started Aug 17 05:35:51 PM PDT 24
Finished Aug 17 05:35:51 PM PDT 24
Peak memory 183272 kb
Host smart-5ee38da2-7fb7-4b92-aad7-a51bd489227f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872073003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1872073003
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.163276650
Short name T564
Test name
Test status
Simulation time 12518117 ps
CPU time 0.6 seconds
Started Aug 17 05:35:52 PM PDT 24
Finished Aug 17 05:35:53 PM PDT 24
Peak memory 192604 kb
Host smart-dd9fdec5-2267-481f-a039-06e1facb905a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163276650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.163276650
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2379410237
Short name T467
Test name
Test status
Simulation time 101132285 ps
CPU time 2.46 seconds
Started Aug 17 05:36:00 PM PDT 24
Finished Aug 17 05:36:03 PM PDT 24
Peak memory 198092 kb
Host smart-16d62666-5a5f-4641-85a8-88bfc7b568ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379410237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2379410237
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.407368139
Short name T94
Test name
Test status
Simulation time 43188659 ps
CPU time 0.86 seconds
Started Aug 17 05:35:49 PM PDT 24
Finished Aug 17 05:35:50 PM PDT 24
Peak memory 194560 kb
Host smart-1127643c-801f-4bb2-af1f-948215443cda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407368139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.407368139
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.4234054490
Short name T520
Test name
Test status
Simulation time 115055610 ps
CPU time 0.69 seconds
Started Aug 17 05:35:51 PM PDT 24
Finished Aug 17 05:35:53 PM PDT 24
Peak memory 194824 kb
Host smart-73fbcf28-0da0-453b-b60b-c66b21d93e64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234054490 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.4234054490
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1088663753
Short name T91
Test name
Test status
Simulation time 13512368 ps
CPU time 0.52 seconds
Started Aug 17 05:35:54 PM PDT 24
Finished Aug 17 05:35:54 PM PDT 24
Peak memory 183060 kb
Host smart-48fe68e9-399b-4fe4-aaa9-083363c21df6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088663753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1088663753
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2790103045
Short name T515
Test name
Test status
Simulation time 42522235 ps
CPU time 0.55 seconds
Started Aug 17 05:35:51 PM PDT 24
Finished Aug 17 05:35:53 PM PDT 24
Peak memory 182728 kb
Host smart-25b507e6-1f25-4cd2-9d81-82729d1a88b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790103045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2790103045
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4270382557
Short name T92
Test name
Test status
Simulation time 105811032 ps
CPU time 0.74 seconds
Started Aug 17 05:35:48 PM PDT 24
Finished Aug 17 05:35:49 PM PDT 24
Peak memory 194060 kb
Host smart-4e4929eb-0b66-48bd-b4da-5afe5edd80ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270382557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.4270382557
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1203629099
Short name T524
Test name
Test status
Simulation time 134655822 ps
CPU time 2.62 seconds
Started Aug 17 05:35:53 PM PDT 24
Finished Aug 17 05:35:55 PM PDT 24
Peak memory 198124 kb
Host smart-24e71c94-dabe-4ac3-850f-2c18160e3e6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203629099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1203629099
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.623212957
Short name T546
Test name
Test status
Simulation time 107999983 ps
CPU time 1.13 seconds
Started Aug 17 05:36:00 PM PDT 24
Finished Aug 17 05:36:01 PM PDT 24
Peak memory 195784 kb
Host smart-cffc85cc-ac8a-41ad-aba8-c1dd0c94b788
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623212957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.623212957
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2501855287
Short name T514
Test name
Test status
Simulation time 123290036 ps
CPU time 0.8 seconds
Started Aug 17 05:36:02 PM PDT 24
Finished Aug 17 05:36:03 PM PDT 24
Peak memory 196264 kb
Host smart-89d7d55e-c27c-4db8-bf8f-09929e3e6740
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501855287 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2501855287
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.60492879
Short name T86
Test name
Test status
Simulation time 57399139 ps
CPU time 0.58 seconds
Started Aug 17 05:35:54 PM PDT 24
Finished Aug 17 05:35:55 PM PDT 24
Peak memory 183372 kb
Host smart-03194951-98bb-44da-9e28-2e82a810aaff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60492879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.60492879
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.318477768
Short name T558
Test name
Test status
Simulation time 74001589 ps
CPU time 0.56 seconds
Started Aug 17 05:35:53 PM PDT 24
Finished Aug 17 05:35:54 PM PDT 24
Peak memory 183208 kb
Host smart-da1c8593-7c2a-46c2-a1a7-2774b1da4d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318477768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.318477768
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.751148558
Short name T580
Test name
Test status
Simulation time 139905513 ps
CPU time 0.85 seconds
Started Aug 17 05:35:58 PM PDT 24
Finished Aug 17 05:35:59 PM PDT 24
Peak memory 191504 kb
Host smart-20df4585-7ba6-4dd2-81e8-3fea9548daa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751148558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.751148558
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3523206119
Short name T545
Test name
Test status
Simulation time 48147964 ps
CPU time 2.33 seconds
Started Aug 17 05:35:58 PM PDT 24
Finished Aug 17 05:36:00 PM PDT 24
Peak memory 198092 kb
Host smart-67e529d2-6790-4782-8108-e51ba78db78d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523206119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3523206119
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2441378827
Short name T526
Test name
Test status
Simulation time 154980245 ps
CPU time 1.08 seconds
Started Aug 17 05:35:55 PM PDT 24
Finished Aug 17 05:35:56 PM PDT 24
Peak memory 196060 kb
Host smart-fc8197c9-d1c9-4bb3-b62e-e6b5271f5150
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441378827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2441378827
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3729662224
Short name T384
Test name
Test status
Simulation time 434332555071 ps
CPU time 150.85 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:38:45 PM PDT 24
Peak memory 183476 kb
Host smart-90c91934-e998-4eaf-910e-b9f37978bd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729662224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3729662224
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.782922589
Short name T343
Test name
Test status
Simulation time 301074645197 ps
CPU time 201.87 seconds
Started Aug 17 05:36:17 PM PDT 24
Finished Aug 17 05:39:39 PM PDT 24
Peak memory 191796 kb
Host smart-fe6cfd3b-797c-43cc-901b-7ca327226e94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782922589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.782922589
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.4144798896
Short name T104
Test name
Test status
Simulation time 362832902930 ps
CPU time 139.28 seconds
Started Aug 17 05:36:13 PM PDT 24
Finished Aug 17 05:38:33 PM PDT 24
Peak memory 195152 kb
Host smart-d684269f-05c4-41b3-9e0a-9dc554edfafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144798896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.4144798896
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1726651854
Short name T419
Test name
Test status
Simulation time 722859298 ps
CPU time 0.63 seconds
Started Aug 17 05:36:17 PM PDT 24
Finished Aug 17 05:36:18 PM PDT 24
Peak memory 183268 kb
Host smart-bc4b965f-d91c-4c7e-a65f-8f18679ac35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726651854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1726651854
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2701722305
Short name T139
Test name
Test status
Simulation time 712574229565 ps
CPU time 720.85 seconds
Started Aug 17 05:36:15 PM PDT 24
Finished Aug 17 05:48:16 PM PDT 24
Peak memory 183588 kb
Host smart-2955164c-1e74-402d-ac8a-d7707cc5e9a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701722305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2701722305
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1362979031
Short name T430
Test name
Test status
Simulation time 76086192417 ps
CPU time 121.41 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:38:15 PM PDT 24
Peak memory 183612 kb
Host smart-5b3fe492-99ee-498d-8cd2-f96710dd3704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362979031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1362979031
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2356443796
Short name T332
Test name
Test status
Simulation time 1874924013 ps
CPU time 3.67 seconds
Started Aug 17 05:36:17 PM PDT 24
Finished Aug 17 05:36:21 PM PDT 24
Peak memory 183200 kb
Host smart-b0a66624-55b9-4876-a9e1-73f253e855bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356443796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2356443796
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2671778580
Short name T452
Test name
Test status
Simulation time 30707917931 ps
CPU time 24.17 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:36:38 PM PDT 24
Peak memory 183604 kb
Host smart-491dba38-55f1-4943-81a8-5cd792a2ef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671778580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2671778580
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3494917339
Short name T15
Test name
Test status
Simulation time 130608862 ps
CPU time 0.79 seconds
Started Aug 17 05:36:16 PM PDT 24
Finished Aug 17 05:36:17 PM PDT 24
Peak memory 213888 kb
Host smart-f0ceb981-865b-4fc2-a5ea-6dea08045dc0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494917339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3494917339
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2537498425
Short name T40
Test name
Test status
Simulation time 1852149145 ps
CPU time 17.66 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:36:32 PM PDT 24
Peak memory 198168 kb
Host smart-f4261cb6-b3b2-4787-86d9-c6d5ee2c325c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537498425 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2537498425
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.673278503
Short name T120
Test name
Test status
Simulation time 16118379476 ps
CPU time 8.31 seconds
Started Aug 17 05:36:27 PM PDT 24
Finished Aug 17 05:36:36 PM PDT 24
Peak memory 183528 kb
Host smart-72eaeb1c-9625-49e6-95f7-a8be3276ce80
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673278503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.673278503
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3443736253
Short name T418
Test name
Test status
Simulation time 554640712067 ps
CPU time 218.22 seconds
Started Aug 17 05:36:28 PM PDT 24
Finished Aug 17 05:40:06 PM PDT 24
Peak memory 183548 kb
Host smart-14a38f20-99f7-440a-b19b-8877fb7ad1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443736253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3443736253
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.2012008053
Short name T454
Test name
Test status
Simulation time 11376059540 ps
CPU time 9.08 seconds
Started Aug 17 05:36:30 PM PDT 24
Finished Aug 17 05:36:39 PM PDT 24
Peak memory 183572 kb
Host smart-51945520-8c0f-4b0f-bdcd-2da658ea0277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012008053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2012008053
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2570048254
Short name T445
Test name
Test status
Simulation time 284931102 ps
CPU time 0.89 seconds
Started Aug 17 05:36:28 PM PDT 24
Finished Aug 17 05:36:29 PM PDT 24
Peak memory 183208 kb
Host smart-692de277-9f9c-42f8-a102-fb20a28f2eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570048254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2570048254
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1287968531
Short name T114
Test name
Test status
Simulation time 1020173193306 ps
CPU time 432.53 seconds
Started Aug 17 05:36:30 PM PDT 24
Finished Aug 17 05:43:42 PM PDT 24
Peak memory 191692 kb
Host smart-a2091439-f3f8-4ab4-a8be-09d84a3d17d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287968531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1287968531
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.1341013825
Short name T152
Test name
Test status
Simulation time 129568667598 ps
CPU time 106.24 seconds
Started Aug 17 05:37:34 PM PDT 24
Finished Aug 17 05:39:20 PM PDT 24
Peak memory 191712 kb
Host smart-28c32369-50ac-4447-a5ce-15e2f0b3595e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341013825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1341013825
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2375920128
Short name T295
Test name
Test status
Simulation time 147286969101 ps
CPU time 87.79 seconds
Started Aug 17 05:37:32 PM PDT 24
Finished Aug 17 05:39:00 PM PDT 24
Peak memory 192788 kb
Host smart-0fd4622d-d660-4d99-b1ee-a3793646726c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375920128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2375920128
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3389070044
Short name T320
Test name
Test status
Simulation time 289186478890 ps
CPU time 185.49 seconds
Started Aug 17 05:37:41 PM PDT 24
Finished Aug 17 05:40:47 PM PDT 24
Peak memory 191800 kb
Host smart-6da7d655-7dd0-4cc9-9059-67ca39defd65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389070044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3389070044
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.734861371
Short name T408
Test name
Test status
Simulation time 111248616197 ps
CPU time 120.54 seconds
Started Aug 17 05:37:39 PM PDT 24
Finished Aug 17 05:39:40 PM PDT 24
Peak memory 191700 kb
Host smart-57785a59-5633-42a9-94b3-69c99e7d0708
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734861371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.734861371
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.31006358
Short name T260
Test name
Test status
Simulation time 137160986233 ps
CPU time 143.96 seconds
Started Aug 17 05:37:40 PM PDT 24
Finished Aug 17 05:40:04 PM PDT 24
Peak memory 191788 kb
Host smart-b3944025-0f42-48de-86dc-2683265afe9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31006358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.31006358
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.450603372
Short name T323
Test name
Test status
Simulation time 347355785918 ps
CPU time 461.88 seconds
Started Aug 17 05:37:43 PM PDT 24
Finished Aug 17 05:45:25 PM PDT 24
Peak memory 191748 kb
Host smart-97a3c87b-1b88-4cc2-a41c-32054eaf966d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450603372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.450603372
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.3521766322
Short name T123
Test name
Test status
Simulation time 501146972170 ps
CPU time 386.41 seconds
Started Aug 17 05:36:28 PM PDT 24
Finished Aug 17 05:42:55 PM PDT 24
Peak memory 191824 kb
Host smart-3ea9aca8-e85d-4f78-b03a-226e032e4ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521766322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3521766322
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.273432362
Short name T401
Test name
Test status
Simulation time 1578553967 ps
CPU time 2.96 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:36:34 PM PDT 24
Peak memory 183272 kb
Host smart-79220a73-367a-4755-9b65-1c5732f7bb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273432362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.273432362
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.294498707
Short name T37
Test name
Test status
Simulation time 7180610817 ps
CPU time 31.19 seconds
Started Aug 17 05:36:32 PM PDT 24
Finished Aug 17 05:37:03 PM PDT 24
Peak memory 198276 kb
Host smart-070f17f3-68ea-4461-86aa-fd1cb3aa77f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294498707 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.294498707
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.478741151
Short name T239
Test name
Test status
Simulation time 1799582390 ps
CPU time 3.96 seconds
Started Aug 17 05:37:40 PM PDT 24
Finished Aug 17 05:37:44 PM PDT 24
Peak memory 183460 kb
Host smart-54fdd2de-ea4e-4fd8-8836-e56fa8186a21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478741151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.478741151
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2081810440
Short name T230
Test name
Test status
Simulation time 384619765948 ps
CPU time 1316.72 seconds
Started Aug 17 05:37:45 PM PDT 24
Finished Aug 17 05:59:42 PM PDT 24
Peak memory 191700 kb
Host smart-477bb737-2938-4970-baa8-df0d82442493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081810440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2081810440
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1391661994
Short name T422
Test name
Test status
Simulation time 102063261624 ps
CPU time 151.28 seconds
Started Aug 17 05:37:42 PM PDT 24
Finished Aug 17 05:40:14 PM PDT 24
Peak memory 191796 kb
Host smart-d91a1cb2-06ae-4948-81d1-799313f6a89b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391661994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1391661994
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.942364280
Short name T46
Test name
Test status
Simulation time 19001965213 ps
CPU time 6.75 seconds
Started Aug 17 05:37:41 PM PDT 24
Finished Aug 17 05:37:47 PM PDT 24
Peak memory 183316 kb
Host smart-efadb094-f248-4686-92bc-f58baac6f931
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942364280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.942364280
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1924497005
Short name T243
Test name
Test status
Simulation time 146178536483 ps
CPU time 213.36 seconds
Started Aug 17 05:37:40 PM PDT 24
Finished Aug 17 05:41:14 PM PDT 24
Peak memory 191784 kb
Host smart-3c45676d-08fe-44fc-8c67-a39539d66e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924497005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1924497005
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3451860587
Short name T176
Test name
Test status
Simulation time 695292307088 ps
CPU time 955.49 seconds
Started Aug 17 05:37:41 PM PDT 24
Finished Aug 17 05:53:36 PM PDT 24
Peak memory 191812 kb
Host smart-a728625e-23a1-4138-ad9f-63e799dffa9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451860587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3451860587
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1896549447
Short name T216
Test name
Test status
Simulation time 1614297140688 ps
CPU time 440.86 seconds
Started Aug 17 05:37:39 PM PDT 24
Finished Aug 17 05:45:00 PM PDT 24
Peak memory 191720 kb
Host smart-b5bd1748-ebb7-40b9-9e83-4c3a07c716c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896549447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1896549447
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.974411801
Short name T364
Test name
Test status
Simulation time 189529159675 ps
CPU time 250.04 seconds
Started Aug 17 05:36:29 PM PDT 24
Finished Aug 17 05:40:39 PM PDT 24
Peak memory 183580 kb
Host smart-2ba55651-184e-4d4b-88fe-bc8b68708a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974411801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.974411801
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3276671932
Short name T223
Test name
Test status
Simulation time 272263502413 ps
CPU time 264.88 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:40:56 PM PDT 24
Peak memory 183536 kb
Host smart-cc3b541e-00a9-4905-a103-d0e9db743394
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276671932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3276671932
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1349629580
Short name T407
Test name
Test status
Simulation time 142353666 ps
CPU time 1.35 seconds
Started Aug 17 05:36:30 PM PDT 24
Finished Aug 17 05:36:32 PM PDT 24
Peak memory 191660 kb
Host smart-ac1bd7e0-cf16-4482-8261-78a1f16c4d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349629580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1349629580
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1207156467
Short name T8
Test name
Test status
Simulation time 214236187215 ps
CPU time 329.91 seconds
Started Aug 17 05:36:33 PM PDT 24
Finished Aug 17 05:42:03 PM PDT 24
Peak memory 191312 kb
Host smart-a525ae2f-ba5e-4200-b2c2-5e97bbd0e80d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207156467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1207156467
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.3283162619
Short name T411
Test name
Test status
Simulation time 16290649009 ps
CPU time 29.28 seconds
Started Aug 17 05:37:40 PM PDT 24
Finished Aug 17 05:38:10 PM PDT 24
Peak memory 183548 kb
Host smart-dc33287f-d735-4ce7-a986-d41c4aedf981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283162619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3283162619
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.332604002
Short name T253
Test name
Test status
Simulation time 290362289473 ps
CPU time 101.94 seconds
Started Aug 17 05:37:46 PM PDT 24
Finished Aug 17 05:39:28 PM PDT 24
Peak memory 183512 kb
Host smart-5e9dff78-f8c2-4e6c-aa21-9bee8f11a141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332604002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.332604002
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1484866951
Short name T187
Test name
Test status
Simulation time 279284180248 ps
CPU time 1491.19 seconds
Started Aug 17 05:37:46 PM PDT 24
Finished Aug 17 06:02:37 PM PDT 24
Peak memory 191780 kb
Host smart-c75d60f0-ed1c-4b7b-b687-2f83d1c9731f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484866951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1484866951
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2608198715
Short name T309
Test name
Test status
Simulation time 179361168859 ps
CPU time 1799.12 seconds
Started Aug 17 05:37:45 PM PDT 24
Finished Aug 17 06:07:44 PM PDT 24
Peak memory 190764 kb
Host smart-1d466a77-bd51-451a-9511-6c914c9358d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608198715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2608198715
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3607203379
Short name T109
Test name
Test status
Simulation time 549260264191 ps
CPU time 180.58 seconds
Started Aug 17 05:37:48 PM PDT 24
Finished Aug 17 05:40:48 PM PDT 24
Peak memory 191700 kb
Host smart-8f999fe4-a064-408d-9b6a-63300f26ec92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607203379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3607203379
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3663013538
Short name T193
Test name
Test status
Simulation time 275357693642 ps
CPU time 201.63 seconds
Started Aug 17 05:36:35 PM PDT 24
Finished Aug 17 05:39:57 PM PDT 24
Peak memory 183472 kb
Host smart-f912fa91-999e-46f3-b489-17ec2acd7c6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663013538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3663013538
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.71832700
Short name T394
Test name
Test status
Simulation time 155889130822 ps
CPU time 225.56 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:40:16 PM PDT 24
Peak memory 183572 kb
Host smart-83164419-7cd0-46d1-93fc-874b5bb667ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71832700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.71832700
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2456641692
Short name T307
Test name
Test status
Simulation time 362149295670 ps
CPU time 231.89 seconds
Started Aug 17 05:36:28 PM PDT 24
Finished Aug 17 05:40:20 PM PDT 24
Peak memory 191804 kb
Host smart-d6ab189d-db05-4d0b-9b4b-8fe6779ce85a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456641692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2456641692
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1907908278
Short name T198
Test name
Test status
Simulation time 371323278762 ps
CPU time 405.26 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:43:17 PM PDT 24
Peak memory 191720 kb
Host smart-f07eb2b9-4e1f-4584-8955-6945aee311c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907908278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1907908278
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2679933723
Short name T380
Test name
Test status
Simulation time 31169653204 ps
CPU time 6.96 seconds
Started Aug 17 05:36:28 PM PDT 24
Finished Aug 17 05:36:35 PM PDT 24
Peak memory 183620 kb
Host smart-69366b7d-40e2-405a-b46a-45000f6efc20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679933723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2679933723
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.1327769979
Short name T439
Test name
Test status
Simulation time 6230872210 ps
CPU time 54.76 seconds
Started Aug 17 05:36:27 PM PDT 24
Finished Aug 17 05:37:22 PM PDT 24
Peak memory 198276 kb
Host smart-40b2d5dc-ad77-4a13-b48c-062f1876d108
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327769979 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.1327769979
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2199120853
Short name T185
Test name
Test status
Simulation time 227154781968 ps
CPU time 243.32 seconds
Started Aug 17 05:37:45 PM PDT 24
Finished Aug 17 05:41:48 PM PDT 24
Peak memory 195328 kb
Host smart-395f0163-9fec-4343-8f79-62da76d52388
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199120853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2199120853
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1013310840
Short name T334
Test name
Test status
Simulation time 832761584376 ps
CPU time 1133.83 seconds
Started Aug 17 05:37:46 PM PDT 24
Finished Aug 17 05:56:40 PM PDT 24
Peak memory 191752 kb
Host smart-3a7b4170-e69e-4717-85fc-fcc8288ecfe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013310840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1013310840
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.604516515
Short name T203
Test name
Test status
Simulation time 261763552156 ps
CPU time 133.89 seconds
Started Aug 17 05:37:46 PM PDT 24
Finished Aug 17 05:40:00 PM PDT 24
Peak memory 191800 kb
Host smart-d2e2a879-bc1b-4da5-a916-c45c36c0c66c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604516515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.604516515
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2450099161
Short name T274
Test name
Test status
Simulation time 163581489210 ps
CPU time 77.09 seconds
Started Aug 17 05:37:48 PM PDT 24
Finished Aug 17 05:39:05 PM PDT 24
Peak memory 191796 kb
Host smart-6a68f3e2-bfc8-4a99-a19b-56882301f4b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450099161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2450099161
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.4061816638
Short name T450
Test name
Test status
Simulation time 32668576343 ps
CPU time 1163.23 seconds
Started Aug 17 05:37:46 PM PDT 24
Finished Aug 17 05:57:10 PM PDT 24
Peak memory 183568 kb
Host smart-61810e12-cd9a-4f8d-b9c9-7be8a17e8cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061816638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4061816638
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2829970045
Short name T449
Test name
Test status
Simulation time 28989441810 ps
CPU time 42.96 seconds
Started Aug 17 05:37:47 PM PDT 24
Finished Aug 17 05:38:30 PM PDT 24
Peak memory 183604 kb
Host smart-1a8a3e2d-9491-4c79-a714-5c2abdb2e47a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829970045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2829970045
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3253735220
Short name T325
Test name
Test status
Simulation time 18008609539 ps
CPU time 23.06 seconds
Started Aug 17 05:37:47 PM PDT 24
Finished Aug 17 05:38:10 PM PDT 24
Peak memory 183612 kb
Host smart-014c2419-36a0-47f7-b0fa-01c5c2d450e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253735220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3253735220
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1281840255
Short name T151
Test name
Test status
Simulation time 111431859539 ps
CPU time 99.07 seconds
Started Aug 17 05:37:46 PM PDT 24
Finished Aug 17 05:39:25 PM PDT 24
Peak memory 191832 kb
Host smart-e29b3f24-5e17-4db6-91fc-5ec3f6e174da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281840255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1281840255
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.144842668
Short name T25
Test name
Test status
Simulation time 417761609081 ps
CPU time 237.8 seconds
Started Aug 17 05:37:46 PM PDT 24
Finished Aug 17 05:41:44 PM PDT 24
Peak memory 191760 kb
Host smart-59c0d3cc-22d0-4d5b-af9c-10e3b11fb565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144842668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.144842668
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.86520194
Short name T247
Test name
Test status
Simulation time 104076264403 ps
CPU time 169.58 seconds
Started Aug 17 05:36:30 PM PDT 24
Finished Aug 17 05:39:19 PM PDT 24
Peak memory 183612 kb
Host smart-5ad31372-7e92-4d68-b2d8-0b8ad11e0921
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86520194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.rv_timer_cfg_update_on_fly.86520194
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1550078571
Short name T395
Test name
Test status
Simulation time 201658648590 ps
CPU time 59.17 seconds
Started Aug 17 05:36:30 PM PDT 24
Finished Aug 17 05:37:29 PM PDT 24
Peak memory 183580 kb
Host smart-e5b2ec9d-79e5-4bf7-9cac-3f10a7680760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550078571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1550078571
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1873825731
Short name T140
Test name
Test status
Simulation time 296544138064 ps
CPU time 322.98 seconds
Started Aug 17 05:36:30 PM PDT 24
Finished Aug 17 05:41:53 PM PDT 24
Peak memory 191804 kb
Host smart-458c7d6d-d88b-414a-8481-16ee2cfa0ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873825731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1873825731
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.311295053
Short name T314
Test name
Test status
Simulation time 24966244022 ps
CPU time 229.75 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:40:21 PM PDT 24
Peak memory 191784 kb
Host smart-5170ea8b-f3af-431c-bd5b-702ec522b9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311295053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.311295053
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.4122442689
Short name T9
Test name
Test status
Simulation time 337245670303 ps
CPU time 168.1 seconds
Started Aug 17 05:37:47 PM PDT 24
Finished Aug 17 05:40:35 PM PDT 24
Peak memory 191748 kb
Host smart-b45bd6e5-9f9f-4811-9f91-b6c5f5d59c49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122442689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4122442689
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.236876367
Short name T263
Test name
Test status
Simulation time 39398939350 ps
CPU time 63.06 seconds
Started Aug 17 05:37:50 PM PDT 24
Finished Aug 17 05:38:53 PM PDT 24
Peak memory 191712 kb
Host smart-e90ace99-0d44-43ce-af63-4153b56fec37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236876367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.236876367
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2338003107
Short name T456
Test name
Test status
Simulation time 28200371620 ps
CPU time 73.95 seconds
Started Aug 17 05:37:45 PM PDT 24
Finished Aug 17 05:38:59 PM PDT 24
Peak memory 183800 kb
Host smart-dc105956-3ccb-4b1e-9353-3aead604ce65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338003107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2338003107
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3034977374
Short name T327
Test name
Test status
Simulation time 206841127691 ps
CPU time 51.48 seconds
Started Aug 17 05:37:56 PM PDT 24
Finished Aug 17 05:38:47 PM PDT 24
Peak memory 183600 kb
Host smart-d199f8b8-cd8c-48e0-a100-51d98f1392be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034977374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3034977374
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.869678956
Short name T414
Test name
Test status
Simulation time 73988280443 ps
CPU time 67.71 seconds
Started Aug 17 05:37:54 PM PDT 24
Finished Aug 17 05:39:01 PM PDT 24
Peak memory 183572 kb
Host smart-98d14a88-d440-4f73-ac11-d2bef41cf0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869678956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.869678956
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2590100175
Short name T126
Test name
Test status
Simulation time 481355316491 ps
CPU time 179.69 seconds
Started Aug 17 05:37:56 PM PDT 24
Finished Aug 17 05:40:55 PM PDT 24
Peak memory 191800 kb
Host smart-4f2613d9-f9d0-4f72-85f2-4128ba4d2ae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590100175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2590100175
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1637614665
Short name T338
Test name
Test status
Simulation time 106722256876 ps
CPU time 310.46 seconds
Started Aug 17 05:37:56 PM PDT 24
Finished Aug 17 05:43:06 PM PDT 24
Peak memory 183592 kb
Host smart-9fffd5a5-9d9c-4274-b7f4-d9c7368d599a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637614665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1637614665
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.3905928929
Short name T201
Test name
Test status
Simulation time 520395112960 ps
CPU time 272.03 seconds
Started Aug 17 05:36:28 PM PDT 24
Finished Aug 17 05:41:01 PM PDT 24
Peak memory 183476 kb
Host smart-1edff041-f6c0-4bb5-b6c8-19133982a687
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905928929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.3905928929
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2054795068
Short name T399
Test name
Test status
Simulation time 20712040053 ps
CPU time 18.31 seconds
Started Aug 17 05:36:28 PM PDT 24
Finished Aug 17 05:36:46 PM PDT 24
Peak memory 183604 kb
Host smart-e0c5d89b-0070-4349-8b78-8dc363db3d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054795068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2054795068
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/150.rv_timer_random.444531618
Short name T298
Test name
Test status
Simulation time 33299545987 ps
CPU time 26 seconds
Started Aug 17 05:37:55 PM PDT 24
Finished Aug 17 05:38:21 PM PDT 24
Peak memory 183600 kb
Host smart-ffe6750a-8fc8-4eef-b671-526c820a9c33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444531618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.444531618
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3259675451
Short name T329
Test name
Test status
Simulation time 55708457432 ps
CPU time 339.78 seconds
Started Aug 17 05:37:57 PM PDT 24
Finished Aug 17 05:43:36 PM PDT 24
Peak memory 191800 kb
Host smart-c8ccb41c-da9b-490c-a421-4f0a0eeae05d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259675451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3259675451
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.421731101
Short name T189
Test name
Test status
Simulation time 111630173864 ps
CPU time 63.32 seconds
Started Aug 17 05:37:56 PM PDT 24
Finished Aug 17 05:38:59 PM PDT 24
Peak memory 191760 kb
Host smart-50c91cff-b726-48f7-b341-9bc17463b24a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421731101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.421731101
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3213147472
Short name T317
Test name
Test status
Simulation time 4035928775 ps
CPU time 6.31 seconds
Started Aug 17 05:38:03 PM PDT 24
Finished Aug 17 05:38:09 PM PDT 24
Peak memory 191780 kb
Host smart-782a898d-ec9d-4265-a50e-8a95a05e4e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213147472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3213147472
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1250693576
Short name T339
Test name
Test status
Simulation time 104408263302 ps
CPU time 155.35 seconds
Started Aug 17 05:38:04 PM PDT 24
Finished Aug 17 05:40:40 PM PDT 24
Peak memory 191704 kb
Host smart-64a00d1d-bed1-492c-b12e-5fc79b6154aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250693576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1250693576
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3715152519
Short name T271
Test name
Test status
Simulation time 144541987817 ps
CPU time 1347.38 seconds
Started Aug 17 05:38:05 PM PDT 24
Finished Aug 17 06:00:32 PM PDT 24
Peak memory 192940 kb
Host smart-7af174e5-be7a-40ea-9964-e5353c756dc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715152519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3715152519
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.801758358
Short name T196
Test name
Test status
Simulation time 290260003744 ps
CPU time 471.52 seconds
Started Aug 17 05:38:03 PM PDT 24
Finished Aug 17 05:45:55 PM PDT 24
Peak memory 191800 kb
Host smart-4b71aa97-22ea-49d5-9903-879626bf908a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801758358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.801758358
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1525706669
Short name T125
Test name
Test status
Simulation time 129567943628 ps
CPU time 231.12 seconds
Started Aug 17 05:38:05 PM PDT 24
Finished Aug 17 05:41:56 PM PDT 24
Peak memory 191776 kb
Host smart-8bbd7d9f-77ef-4baf-8d2a-bccb4375a071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525706669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1525706669
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.603980262
Short name T110
Test name
Test status
Simulation time 630862973653 ps
CPU time 300.88 seconds
Started Aug 17 05:36:29 PM PDT 24
Finished Aug 17 05:41:30 PM PDT 24
Peak memory 183572 kb
Host smart-2f19f549-b05b-422a-85e4-35a021fc392c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603980262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.603980262
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.994377683
Short name T446
Test name
Test status
Simulation time 646354441917 ps
CPU time 77.8 seconds
Started Aug 17 05:36:32 PM PDT 24
Finished Aug 17 05:37:50 PM PDT 24
Peak memory 183512 kb
Host smart-97c013dd-b361-4449-8e83-7cf9522331f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994377683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.994377683
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2126032003
Short name T308
Test name
Test status
Simulation time 47146777873 ps
CPU time 61.1 seconds
Started Aug 17 05:36:28 PM PDT 24
Finished Aug 17 05:37:29 PM PDT 24
Peak memory 183544 kb
Host smart-9990f93f-e418-4831-98e0-20fb478d075b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126032003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2126032003
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.2500775829
Short name T113
Test name
Test status
Simulation time 628549199133 ps
CPU time 741.06 seconds
Started Aug 17 05:38:03 PM PDT 24
Finished Aug 17 05:50:25 PM PDT 24
Peak memory 191764 kb
Host smart-d714c542-4d36-4bb8-b3f4-dfb976e22f99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500775829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2500775829
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2404390109
Short name T20
Test name
Test status
Simulation time 85514381797 ps
CPU time 128.71 seconds
Started Aug 17 05:38:04 PM PDT 24
Finished Aug 17 05:40:13 PM PDT 24
Peak memory 194588 kb
Host smart-61376e14-7edf-4faa-9ba2-babfb64a4651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404390109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2404390109
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2121094315
Short name T356
Test name
Test status
Simulation time 184797306779 ps
CPU time 189.81 seconds
Started Aug 17 05:38:03 PM PDT 24
Finished Aug 17 05:41:12 PM PDT 24
Peak memory 191812 kb
Host smart-ae1b36d9-2a26-43d9-a9d5-83b99d2446e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121094315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2121094315
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.4200363631
Short name T197
Test name
Test status
Simulation time 53230466520 ps
CPU time 295.17 seconds
Started Aug 17 05:38:06 PM PDT 24
Finished Aug 17 05:43:01 PM PDT 24
Peak memory 191796 kb
Host smart-5e8f3585-2e3b-435e-b8a0-0107946b110d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200363631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.4200363631
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3988514782
Short name T204
Test name
Test status
Simulation time 1966910400241 ps
CPU time 718.09 seconds
Started Aug 17 05:38:04 PM PDT 24
Finished Aug 17 05:50:02 PM PDT 24
Peak memory 193824 kb
Host smart-0f2565fc-5dcd-4f87-8b68-860c75c450bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988514782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3988514782
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2354863396
Short name T261
Test name
Test status
Simulation time 331566611190 ps
CPU time 235.95 seconds
Started Aug 17 05:38:03 PM PDT 24
Finished Aug 17 05:41:59 PM PDT 24
Peak memory 191800 kb
Host smart-aec8b212-95cb-401b-9c95-10270b75b7dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354863396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2354863396
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.574530702
Short name T177
Test name
Test status
Simulation time 208194232720 ps
CPU time 531.41 seconds
Started Aug 17 05:38:03 PM PDT 24
Finished Aug 17 05:46:55 PM PDT 24
Peak memory 196392 kb
Host smart-70007825-de32-428b-a99e-aa6d6108393f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574530702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.574530702
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.110602076
Short name T264
Test name
Test status
Simulation time 689649705806 ps
CPU time 443.59 seconds
Started Aug 17 05:38:02 PM PDT 24
Finished Aug 17 05:45:25 PM PDT 24
Peak memory 191788 kb
Host smart-82b4b55d-7a94-4e92-a895-cf97f2ee41db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110602076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.110602076
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3077144412
Short name T241
Test name
Test status
Simulation time 31151320148 ps
CPU time 54.73 seconds
Started Aug 17 05:36:35 PM PDT 24
Finished Aug 17 05:37:30 PM PDT 24
Peak memory 183432 kb
Host smart-018c8586-8803-4d23-8b34-adac7148127a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077144412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3077144412
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3596344455
Short name T2
Test name
Test status
Simulation time 240721170196 ps
CPU time 156.38 seconds
Started Aug 17 05:36:34 PM PDT 24
Finished Aug 17 05:39:10 PM PDT 24
Peak memory 183468 kb
Host smart-1e2d831e-4639-44c6-a8ed-37d07fdea1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596344455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3596344455
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3884927891
Short name T138
Test name
Test status
Simulation time 400305204138 ps
CPU time 172.81 seconds
Started Aug 17 05:36:29 PM PDT 24
Finished Aug 17 05:39:22 PM PDT 24
Peak memory 191812 kb
Host smart-a482190a-8f54-4fc7-a4cd-5b271adc4dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884927891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3884927891
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1097342484
Short name T246
Test name
Test status
Simulation time 28905359056 ps
CPU time 26.44 seconds
Started Aug 17 05:36:32 PM PDT 24
Finished Aug 17 05:36:59 PM PDT 24
Peak memory 191780 kb
Host smart-13daf93e-5040-4a3f-8793-69ee8fb76318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097342484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1097342484
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2786053930
Short name T14
Test name
Test status
Simulation time 5932517344 ps
CPU time 12.08 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:36:43 PM PDT 24
Peak memory 198280 kb
Host smart-ba6584d8-f733-4edb-99c1-9cd9dff200a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786053930 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2786053930
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.145321722
Short name T354
Test name
Test status
Simulation time 19352045934 ps
CPU time 679.12 seconds
Started Aug 17 05:38:03 PM PDT 24
Finished Aug 17 05:49:22 PM PDT 24
Peak memory 183556 kb
Host smart-ac10182b-0a20-463f-b882-45f2b62b4699
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145321722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.145321722
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.798344995
Short name T57
Test name
Test status
Simulation time 111703176929 ps
CPU time 178.38 seconds
Started Aug 17 05:38:03 PM PDT 24
Finished Aug 17 05:41:01 PM PDT 24
Peak memory 191708 kb
Host smart-2e74f8e8-6c41-42c7-9d04-9a96bab770a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798344995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.798344995
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1018710707
Short name T405
Test name
Test status
Simulation time 62361334891 ps
CPU time 80.66 seconds
Started Aug 17 05:38:09 PM PDT 24
Finished Aug 17 05:39:30 PM PDT 24
Peak memory 183556 kb
Host smart-19ad0e49-2ff0-4f37-b84b-e2f1039761b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018710707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1018710707
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2252789116
Short name T318
Test name
Test status
Simulation time 45424956037 ps
CPU time 63.02 seconds
Started Aug 17 05:38:12 PM PDT 24
Finished Aug 17 05:39:15 PM PDT 24
Peak memory 183512 kb
Host smart-ff102c2d-42c4-41f8-b83e-fc860d63a07b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252789116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2252789116
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3417151969
Short name T301
Test name
Test status
Simulation time 186618614911 ps
CPU time 1818.26 seconds
Started Aug 17 05:38:10 PM PDT 24
Finished Aug 17 06:08:28 PM PDT 24
Peak memory 191804 kb
Host smart-b158b053-f710-4d2f-ac3a-bb2b80b1620a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417151969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3417151969
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2558566918
Short name T348
Test name
Test status
Simulation time 41939799524 ps
CPU time 682.68 seconds
Started Aug 17 05:38:10 PM PDT 24
Finished Aug 17 05:49:33 PM PDT 24
Peak memory 191764 kb
Host smart-a12303b5-f835-4fd3-9490-33c5a6774c3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558566918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2558566918
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3631466945
Short name T228
Test name
Test status
Simulation time 101605295527 ps
CPU time 1691.5 seconds
Started Aug 17 05:38:11 PM PDT 24
Finished Aug 17 06:06:23 PM PDT 24
Peak memory 194980 kb
Host smart-0f4c3269-ec8e-4b48-99af-61da7a9acb27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631466945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3631466945
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.4212948135
Short name T427
Test name
Test status
Simulation time 315016859891 ps
CPU time 137.32 seconds
Started Aug 17 05:36:28 PM PDT 24
Finished Aug 17 05:38:45 PM PDT 24
Peak memory 183540 kb
Host smart-2b62e442-25a4-4e11-9a2f-ae237ea34852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212948135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.4212948135
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2421913075
Short name T336
Test name
Test status
Simulation time 87718753177 ps
CPU time 93.12 seconds
Started Aug 17 05:36:29 PM PDT 24
Finished Aug 17 05:38:02 PM PDT 24
Peak memory 191716 kb
Host smart-d3247be5-f670-432e-af7e-6c3e9c46358a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421913075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2421913075
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.1285418617
Short name T38
Test name
Test status
Simulation time 1300735015 ps
CPU time 14.22 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:36:46 PM PDT 24
Peak memory 193656 kb
Host smart-9ebd8de9-4dfe-46f5-98ae-23f128014e5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285418617 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.1285418617
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.2930317824
Short name T352
Test name
Test status
Simulation time 157569261239 ps
CPU time 114.95 seconds
Started Aug 17 05:38:10 PM PDT 24
Finished Aug 17 05:40:05 PM PDT 24
Peak memory 183552 kb
Host smart-8d6dab54-e5f0-484b-aa79-01d7399c2d7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930317824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2930317824
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2729749571
Short name T141
Test name
Test status
Simulation time 90916821614 ps
CPU time 394.07 seconds
Started Aug 17 05:38:13 PM PDT 24
Finished Aug 17 05:44:47 PM PDT 24
Peak memory 191700 kb
Host smart-f8ad0597-9977-4cb4-9a0b-b6768b25e4af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729749571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2729749571
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1489890994
Short name T234
Test name
Test status
Simulation time 32574022436 ps
CPU time 90.45 seconds
Started Aug 17 05:38:10 PM PDT 24
Finished Aug 17 05:39:41 PM PDT 24
Peak memory 183568 kb
Host smart-ed221d10-6a8b-44ac-a8e4-e608c813579a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489890994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1489890994
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1294668678
Short name T244
Test name
Test status
Simulation time 99971981426 ps
CPU time 261.46 seconds
Started Aug 17 05:38:11 PM PDT 24
Finished Aug 17 05:42:32 PM PDT 24
Peak memory 191760 kb
Host smart-d9920e00-8597-422d-8208-17725f2762f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294668678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1294668678
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.858913775
Short name T269
Test name
Test status
Simulation time 127965099341 ps
CPU time 319.77 seconds
Started Aug 17 05:38:11 PM PDT 24
Finished Aug 17 05:43:31 PM PDT 24
Peak memory 191712 kb
Host smart-384d0a11-ed79-4eb4-b6ab-52f21ecfd9b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858913775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.858913775
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1121880047
Short name T183
Test name
Test status
Simulation time 218882233161 ps
CPU time 128.1 seconds
Started Aug 17 05:38:13 PM PDT 24
Finished Aug 17 05:40:22 PM PDT 24
Peak memory 191748 kb
Host smart-c6823500-9c20-497e-8627-84cdaecf33a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121880047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1121880047
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2628406790
Short name T213
Test name
Test status
Simulation time 654796699789 ps
CPU time 1192.37 seconds
Started Aug 17 05:36:35 PM PDT 24
Finished Aug 17 05:56:28 PM PDT 24
Peak memory 183368 kb
Host smart-6ba7d1ad-16cd-439b-b30b-94708a707dd6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628406790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2628406790
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1080204688
Short name T455
Test name
Test status
Simulation time 123532132396 ps
CPU time 163.75 seconds
Started Aug 17 05:36:32 PM PDT 24
Finished Aug 17 05:39:16 PM PDT 24
Peak memory 183432 kb
Host smart-604edfa8-b307-4e07-b122-ecb722d65aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080204688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1080204688
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2993821330
Short name T107
Test name
Test status
Simulation time 115125205767 ps
CPU time 247.2 seconds
Started Aug 17 05:36:30 PM PDT 24
Finished Aug 17 05:40:37 PM PDT 24
Peak memory 191816 kb
Host smart-e74a06d1-fdee-4165-b518-2dfbf47b09b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993821330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2993821330
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.146722198
Short name T6
Test name
Test status
Simulation time 62570449856 ps
CPU time 79.43 seconds
Started Aug 17 05:36:34 PM PDT 24
Finished Aug 17 05:37:54 PM PDT 24
Peak memory 194084 kb
Host smart-eab76da4-c4bb-468a-89b8-ad6854735397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146722198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.146722198
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.2951635756
Short name T441
Test name
Test status
Simulation time 7714672945 ps
CPU time 20.04 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:36:51 PM PDT 24
Peak memory 198260 kb
Host smart-e0424ee1-70d2-4dbd-8307-d11eb8d6874f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951635756 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.2951635756
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.1495465429
Short name T305
Test name
Test status
Simulation time 71989809808 ps
CPU time 45.89 seconds
Started Aug 17 05:38:20 PM PDT 24
Finished Aug 17 05:39:06 PM PDT 24
Peak memory 183496 kb
Host smart-759d30a9-4534-4f9b-b9c4-ca3761bf1edc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495465429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1495465429
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3619906113
Short name T28
Test name
Test status
Simulation time 351880355440 ps
CPU time 1370.7 seconds
Started Aug 17 05:38:20 PM PDT 24
Finished Aug 17 06:01:11 PM PDT 24
Peak memory 191796 kb
Host smart-75642707-6a36-471c-b38c-4ab3ec90a452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619906113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3619906113
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1799583890
Short name T131
Test name
Test status
Simulation time 110853489985 ps
CPU time 177.17 seconds
Started Aug 17 05:38:20 PM PDT 24
Finished Aug 17 05:41:17 PM PDT 24
Peak memory 191520 kb
Host smart-2e187a0e-2688-4265-9877-d721da1bd226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799583890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1799583890
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.872145306
Short name T268
Test name
Test status
Simulation time 155867350734 ps
CPU time 223.32 seconds
Started Aug 17 05:38:23 PM PDT 24
Finished Aug 17 05:42:06 PM PDT 24
Peak memory 191784 kb
Host smart-bee3f8b1-37f4-4123-af85-db7e17b23ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872145306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.872145306
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.94025724
Short name T105
Test name
Test status
Simulation time 1596974020353 ps
CPU time 593.86 seconds
Started Aug 17 05:38:20 PM PDT 24
Finished Aug 17 05:48:14 PM PDT 24
Peak memory 191508 kb
Host smart-caa7bf53-5c91-409f-a7ad-4433709e1a86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94025724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.94025724
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.873932991
Short name T438
Test name
Test status
Simulation time 47969271771 ps
CPU time 78.67 seconds
Started Aug 17 05:38:19 PM PDT 24
Finished Aug 17 05:39:38 PM PDT 24
Peak memory 183544 kb
Host smart-71c0196f-0b6d-475d-a3e1-74d3c7a634ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873932991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.873932991
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.627885939
Short name T64
Test name
Test status
Simulation time 91526667512 ps
CPU time 76.81 seconds
Started Aug 17 05:38:20 PM PDT 24
Finished Aug 17 05:39:37 PM PDT 24
Peak memory 191712 kb
Host smart-1ae3ee70-58d6-4224-8b4e-700c3ea997b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627885939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.627885939
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2495111819
Short name T270
Test name
Test status
Simulation time 707450495369 ps
CPU time 448.79 seconds
Started Aug 17 05:38:19 PM PDT 24
Finished Aug 17 05:45:48 PM PDT 24
Peak memory 191764 kb
Host smart-fa036fe1-4a09-4581-b09e-7f27e6d9b24b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495111819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2495111819
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3407060352
Short name T149
Test name
Test status
Simulation time 64270423129 ps
CPU time 82.62 seconds
Started Aug 17 05:38:22 PM PDT 24
Finished Aug 17 05:39:45 PM PDT 24
Peak memory 191720 kb
Host smart-9a0b1b7c-a390-4028-87c5-293f448530d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407060352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3407060352
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2264227531
Short name T207
Test name
Test status
Simulation time 376877131862 ps
CPU time 190.74 seconds
Started Aug 17 05:36:14 PM PDT 24
Finished Aug 17 05:39:25 PM PDT 24
Peak memory 183580 kb
Host smart-3bc16392-9a58-429d-9299-040229ca57ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264227531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2264227531
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.78707987
Short name T375
Test name
Test status
Simulation time 74069303015 ps
CPU time 111.38 seconds
Started Aug 17 05:36:18 PM PDT 24
Finished Aug 17 05:38:09 PM PDT 24
Peak memory 183468 kb
Host smart-1fd54d8c-bd61-4554-b6a9-b55322cfabb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78707987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.78707987
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3929164016
Short name T16
Test name
Test status
Simulation time 340240285 ps
CPU time 0.96 seconds
Started Aug 17 05:36:20 PM PDT 24
Finished Aug 17 05:36:21 PM PDT 24
Peak memory 215112 kb
Host smart-497d344c-ae3d-4cc5-a91c-66caa8b17ee2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929164016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3929164016
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1571209413
Short name T410
Test name
Test status
Simulation time 123465635227 ps
CPU time 201.71 seconds
Started Aug 17 05:36:16 PM PDT 24
Finished Aug 17 05:39:37 PM PDT 24
Peak memory 195424 kb
Host smart-b96872f0-a11c-4dae-bbdf-017e4cb0dc4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571209413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1571209413
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1338051095
Short name T426
Test name
Test status
Simulation time 342753322437 ps
CPU time 162.09 seconds
Started Aug 17 05:36:32 PM PDT 24
Finished Aug 17 05:39:14 PM PDT 24
Peak memory 183544 kb
Host smart-e8f9cc72-67f6-4901-a5b3-4609d95b9007
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338051095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1338051095
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3529099353
Short name T383
Test name
Test status
Simulation time 292677754530 ps
CPU time 241.4 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:40:32 PM PDT 24
Peak memory 183516 kb
Host smart-39ac4f70-bc1a-497b-ba54-2f1681eafe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529099353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3529099353
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1405395528
Short name T208
Test name
Test status
Simulation time 99269699879 ps
CPU time 506.34 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:44:57 PM PDT 24
Peak memory 191776 kb
Host smart-7e8e3507-8749-4c7f-bde9-b760f48b785d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405395528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1405395528
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.4244433423
Short name T296
Test name
Test status
Simulation time 257668631077 ps
CPU time 373.17 seconds
Started Aug 17 05:36:36 PM PDT 24
Finished Aug 17 05:42:49 PM PDT 24
Peak memory 196340 kb
Host smart-d7a15fe9-7d92-4499-9332-62b3fccfa434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244433423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.4244433423
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3125542293
Short name T206
Test name
Test status
Simulation time 81706851967 ps
CPU time 124.5 seconds
Started Aug 17 05:36:40 PM PDT 24
Finished Aug 17 05:38:45 PM PDT 24
Peak memory 183584 kb
Host smart-b74de7ce-271b-4ff2-9ad3-57145886b226
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125542293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3125542293
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1033139414
Short name T377
Test name
Test status
Simulation time 208966887465 ps
CPU time 75.93 seconds
Started Aug 17 05:36:39 PM PDT 24
Finished Aug 17 05:37:55 PM PDT 24
Peak memory 183584 kb
Host smart-0cde3468-dd74-4b50-8524-54aca8444a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033139414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1033139414
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.69005760
Short name T443
Test name
Test status
Simulation time 480913180975 ps
CPU time 1843.42 seconds
Started Aug 17 05:36:37 PM PDT 24
Finished Aug 17 06:07:21 PM PDT 24
Peak memory 191792 kb
Host smart-7ef17173-cee7-4e6b-a9ef-545c077ad1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69005760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.69005760
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.596295700
Short name T362
Test name
Test status
Simulation time 280795758900 ps
CPU time 231.78 seconds
Started Aug 17 05:36:38 PM PDT 24
Finished Aug 17 05:40:30 PM PDT 24
Peak memory 183468 kb
Host smart-71592f57-d8d4-430c-b887-1b2303f6b72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596295700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.596295700
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3826087279
Short name T73
Test name
Test status
Simulation time 135735218549 ps
CPU time 211.92 seconds
Started Aug 17 05:36:37 PM PDT 24
Finished Aug 17 05:40:09 PM PDT 24
Peak memory 191808 kb
Host smart-0c4e43ea-0b3f-42a7-a3b6-1509c9e91174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826087279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3826087279
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3426400949
Short name T440
Test name
Test status
Simulation time 353538058938 ps
CPU time 172.53 seconds
Started Aug 17 05:36:37 PM PDT 24
Finished Aug 17 05:39:29 PM PDT 24
Peak memory 183568 kb
Host smart-69ce57b7-418e-48d2-94bc-d42e0ef77ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426400949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3426400949
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.3065959264
Short name T416
Test name
Test status
Simulation time 10838093817 ps
CPU time 30.83 seconds
Started Aug 17 05:36:39 PM PDT 24
Finished Aug 17 05:37:10 PM PDT 24
Peak memory 198288 kb
Host smart-f17557ce-3463-4a6d-b274-92c238f4f1d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065959264 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.3065959264
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2598361160
Short name T350
Test name
Test status
Simulation time 30149326850 ps
CPU time 43.34 seconds
Started Aug 17 05:36:39 PM PDT 24
Finished Aug 17 05:37:23 PM PDT 24
Peak memory 183604 kb
Host smart-ea329939-721f-4d71-8d8b-89ab7f82fd42
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598361160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2598361160
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.752170122
Short name T361
Test name
Test status
Simulation time 146136052422 ps
CPU time 208.8 seconds
Started Aug 17 05:36:41 PM PDT 24
Finished Aug 17 05:40:10 PM PDT 24
Peak memory 183572 kb
Host smart-7b0ee257-d174-41c1-8c31-9570ed6f72fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752170122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.752170122
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2748796044
Short name T127
Test name
Test status
Simulation time 13271647157 ps
CPU time 460.89 seconds
Started Aug 17 05:36:35 PM PDT 24
Finished Aug 17 05:44:17 PM PDT 24
Peak memory 183540 kb
Host smart-014d17ef-4cbc-4b43-8132-262c26f72113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748796044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2748796044
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1111900506
Short name T371
Test name
Test status
Simulation time 200887287 ps
CPU time 0.8 seconds
Started Aug 17 05:36:37 PM PDT 24
Finished Aug 17 05:36:38 PM PDT 24
Peak memory 183264 kb
Host smart-8972de71-ef9a-4233-bd78-12caacf4775a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111900506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1111900506
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.924948938
Short name T24
Test name
Test status
Simulation time 189951687884 ps
CPU time 349.29 seconds
Started Aug 17 05:36:40 PM PDT 24
Finished Aug 17 05:42:29 PM PDT 24
Peak memory 195376 kb
Host smart-526ef29f-8af9-464d-b5ba-6fe2348b459d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924948938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
924948938
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.4253637197
Short name T194
Test name
Test status
Simulation time 11065785275 ps
CPU time 14.39 seconds
Started Aug 17 05:36:40 PM PDT 24
Finished Aug 17 05:36:55 PM PDT 24
Peak memory 183560 kb
Host smart-04dda3fc-7407-4490-88df-568c87f06562
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253637197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.4253637197
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.533302524
Short name T397
Test name
Test status
Simulation time 169731085203 ps
CPU time 118.55 seconds
Started Aug 17 05:36:36 PM PDT 24
Finished Aug 17 05:38:35 PM PDT 24
Peak memory 183564 kb
Host smart-bc0ec354-5618-4f20-b279-d5534b1fbb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533302524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.533302524
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2735817708
Short name T429
Test name
Test status
Simulation time 9863900401 ps
CPU time 9.97 seconds
Started Aug 17 05:36:38 PM PDT 24
Finished Aug 17 05:36:48 PM PDT 24
Peak memory 183536 kb
Host smart-fedb024e-85f4-453a-a157-d86bf10cdfa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735817708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2735817708
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.385926684
Short name T451
Test name
Test status
Simulation time 28710133078 ps
CPU time 1028.56 seconds
Started Aug 17 05:36:42 PM PDT 24
Finished Aug 17 05:53:50 PM PDT 24
Peak memory 183568 kb
Host smart-773573f0-3772-4a6b-a8d6-17a68997361f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385926684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.385926684
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.469120003
Short name T433
Test name
Test status
Simulation time 3030950975648 ps
CPU time 635.23 seconds
Started Aug 17 05:36:35 PM PDT 24
Finished Aug 17 05:47:11 PM PDT 24
Peak memory 183552 kb
Host smart-f1909d08-4503-4498-af27-035ad54169a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469120003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.469120003
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2063246757
Short name T372
Test name
Test status
Simulation time 587587228610 ps
CPU time 201.33 seconds
Started Aug 17 05:36:37 PM PDT 24
Finished Aug 17 05:39:58 PM PDT 24
Peak memory 183560 kb
Host smart-82828a8b-7a2f-48c3-bc46-ae0ab6b05ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063246757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2063246757
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1399362261
Short name T218
Test name
Test status
Simulation time 135428677873 ps
CPU time 1177.47 seconds
Started Aug 17 05:36:36 PM PDT 24
Finished Aug 17 05:56:13 PM PDT 24
Peak memory 191804 kb
Host smart-fed6b730-eb8b-4ad9-8b27-1b5ea77e8539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399362261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1399362261
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1801126927
Short name T192
Test name
Test status
Simulation time 245335311000 ps
CPU time 158.74 seconds
Started Aug 17 05:36:36 PM PDT 24
Finished Aug 17 05:39:15 PM PDT 24
Peak memory 191752 kb
Host smart-298968e5-e4d9-404f-aedd-d45ee6280782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801126927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1801126927
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2894919902
Short name T279
Test name
Test status
Simulation time 647750836496 ps
CPU time 1527.57 seconds
Started Aug 17 05:36:43 PM PDT 24
Finished Aug 17 06:02:11 PM PDT 24
Peak memory 191720 kb
Host smart-2812ee46-6bf4-4ca7-b204-def4d35be475
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894919902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2894919902
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2383309667
Short name T319
Test name
Test status
Simulation time 1114237982279 ps
CPU time 591.06 seconds
Started Aug 17 05:36:43 PM PDT 24
Finished Aug 17 05:46:34 PM PDT 24
Peak memory 183508 kb
Host smart-6d020ddb-caaf-4deb-8fa0-827db182aa87
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383309667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2383309667
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.166583644
Short name T421
Test name
Test status
Simulation time 91447962972 ps
CPU time 68.15 seconds
Started Aug 17 05:36:35 PM PDT 24
Finished Aug 17 05:37:43 PM PDT 24
Peak memory 183552 kb
Host smart-42db7ffd-25a0-43cc-a3c3-e50916b65094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166583644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.166583644
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3844678911
Short name T303
Test name
Test status
Simulation time 154905852642 ps
CPU time 88.76 seconds
Started Aug 17 05:36:36 PM PDT 24
Finished Aug 17 05:38:05 PM PDT 24
Peak memory 183532 kb
Host smart-6b554d3d-e4cd-46aa-9d75-312dde58bc7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844678911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3844678911
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.859417351
Short name T447
Test name
Test status
Simulation time 65126836655 ps
CPU time 43.87 seconds
Started Aug 17 05:36:41 PM PDT 24
Finished Aug 17 05:37:24 PM PDT 24
Peak memory 195120 kb
Host smart-712e23a7-78c0-496a-93a3-823fdb73a630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859417351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.859417351
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3930234488
Short name T435
Test name
Test status
Simulation time 102149876220 ps
CPU time 133.71 seconds
Started Aug 17 05:36:35 PM PDT 24
Finished Aug 17 05:38:48 PM PDT 24
Peak memory 183568 kb
Host smart-62fdf3b3-9554-4621-a64e-4713fd6fa2cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930234488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3930234488
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.1089621110
Short name T39
Test name
Test status
Simulation time 527849751 ps
CPU time 6.88 seconds
Started Aug 17 05:36:41 PM PDT 24
Finished Aug 17 05:36:47 PM PDT 24
Peak memory 198148 kb
Host smart-af85240b-9151-4b36-8659-430af2afc622
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089621110 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.1089621110
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2817741909
Short name T288
Test name
Test status
Simulation time 3232562206768 ps
CPU time 1147.88 seconds
Started Aug 17 05:36:39 PM PDT 24
Finished Aug 17 05:55:47 PM PDT 24
Peak memory 183588 kb
Host smart-1c6b3e5d-d3fa-47ae-8823-ff1092ef3d53
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817741909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2817741909
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3627070515
Short name T388
Test name
Test status
Simulation time 174816416973 ps
CPU time 234.69 seconds
Started Aug 17 05:36:43 PM PDT 24
Finished Aug 17 05:40:38 PM PDT 24
Peak memory 183508 kb
Host smart-1f9a8784-d070-4af3-bc84-39b104e78db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627070515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3627070515
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.4174767536
Short name T122
Test name
Test status
Simulation time 136180293324 ps
CPU time 1453.67 seconds
Started Aug 17 05:36:39 PM PDT 24
Finished Aug 17 06:00:53 PM PDT 24
Peak memory 183572 kb
Host smart-345f17b9-aa81-45e8-91c2-a3eb001772cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174767536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.4174767536
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3515653705
Short name T389
Test name
Test status
Simulation time 361615656 ps
CPU time 1.54 seconds
Started Aug 17 05:36:39 PM PDT 24
Finished Aug 17 05:36:41 PM PDT 24
Peak memory 191552 kb
Host smart-0f81f8f5-ae5d-4ba3-aad6-a29046316e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515653705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3515653705
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.2798085424
Short name T36
Test name
Test status
Simulation time 2545923243 ps
CPU time 6.07 seconds
Started Aug 17 05:36:35 PM PDT 24
Finished Aug 17 05:36:41 PM PDT 24
Peak memory 198264 kb
Host smart-db4813b7-3d26-4519-9d1d-b81f5fe6b8d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798085424 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.2798085424
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1189214366
Short name T391
Test name
Test status
Simulation time 223105063756 ps
CPU time 140.33 seconds
Started Aug 17 05:36:43 PM PDT 24
Finished Aug 17 05:39:03 PM PDT 24
Peak memory 183520 kb
Host smart-623ced57-0ec8-481c-9435-f68f16ed0fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189214366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1189214366
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.1274951724
Short name T211
Test name
Test status
Simulation time 228339475509 ps
CPU time 3440.74 seconds
Started Aug 17 05:36:39 PM PDT 24
Finished Aug 17 06:34:01 PM PDT 24
Peak memory 191696 kb
Host smart-0ff9e652-4388-4523-94dd-73c9cc674ec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274951724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1274951724
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2686426059
Short name T368
Test name
Test status
Simulation time 135912180584 ps
CPU time 24.56 seconds
Started Aug 17 05:36:44 PM PDT 24
Finished Aug 17 05:37:09 PM PDT 24
Peak memory 183540 kb
Host smart-a871fee9-de82-4caf-8ee8-f56b8bf17d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686426059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2686426059
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1985803630
Short name T242
Test name
Test status
Simulation time 1440978208513 ps
CPU time 842.41 seconds
Started Aug 17 05:36:44 PM PDT 24
Finished Aug 17 05:50:47 PM PDT 24
Peak memory 183508 kb
Host smart-c4963810-9d41-4f49-9fbd-280c1b3562a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985803630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1985803630
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1800359435
Short name T437
Test name
Test status
Simulation time 385497665630 ps
CPU time 94.79 seconds
Started Aug 17 05:36:46 PM PDT 24
Finished Aug 17 05:38:21 PM PDT 24
Peak memory 183556 kb
Host smart-ac914485-55f1-486f-bb96-f459bc99a8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800359435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1800359435
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.105899417
Short name T324
Test name
Test status
Simulation time 131026852960 ps
CPU time 124.25 seconds
Started Aug 17 05:36:47 PM PDT 24
Finished Aug 17 05:38:51 PM PDT 24
Peak memory 191784 kb
Host smart-8bab26d0-f914-42ad-b0c9-3acb7a819ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105899417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.105899417
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2693935098
Short name T69
Test name
Test status
Simulation time 1056084986676 ps
CPU time 615.28 seconds
Started Aug 17 05:36:47 PM PDT 24
Finished Aug 17 05:47:02 PM PDT 24
Peak memory 191732 kb
Host smart-dc47f2c8-fdef-4ec5-b08f-ca3d01d818e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693935098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2693935098
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2910842191
Short name T231
Test name
Test status
Simulation time 57672811295 ps
CPU time 83.65 seconds
Started Aug 17 05:36:33 PM PDT 24
Finished Aug 17 05:37:57 PM PDT 24
Peak memory 183144 kb
Host smart-669abb3e-312e-4e03-b435-b1ed86947e19
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910842191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2910842191
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2256681324
Short name T58
Test name
Test status
Simulation time 21307588308 ps
CPU time 16.99 seconds
Started Aug 17 05:36:21 PM PDT 24
Finished Aug 17 05:36:38 PM PDT 24
Peak memory 183512 kb
Host smart-633411f9-6937-4a4e-ae17-79fc80ca4367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256681324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2256681324
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.249319647
Short name T302
Test name
Test status
Simulation time 86660578369 ps
CPU time 129.89 seconds
Started Aug 17 05:36:20 PM PDT 24
Finished Aug 17 05:38:30 PM PDT 24
Peak memory 191764 kb
Host smart-45e06b06-43d9-4fa5-a297-e405387b953c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249319647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.249319647
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.659520845
Short name T448
Test name
Test status
Simulation time 167292361049 ps
CPU time 76.51 seconds
Started Aug 17 05:36:32 PM PDT 24
Finished Aug 17 05:37:48 PM PDT 24
Peak memory 191768 kb
Host smart-59577f75-54b3-487c-9778-075eb3144c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659520845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.659520845
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.798993520
Short name T17
Test name
Test status
Simulation time 63400581 ps
CPU time 0.81 seconds
Started Aug 17 05:36:20 PM PDT 24
Finished Aug 17 05:36:21 PM PDT 24
Peak memory 213976 kb
Host smart-b8f9b5da-7702-40bc-bab9-cb06eb9dd3df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798993520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.798993520
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.4231739110
Short name T400
Test name
Test status
Simulation time 147804678 ps
CPU time 0.62 seconds
Started Aug 17 05:36:32 PM PDT 24
Finished Aug 17 05:36:33 PM PDT 24
Peak memory 183188 kb
Host smart-e8affe77-81c4-424f-aad1-5060e5ecca63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231739110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
4231739110
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.4003324845
Short name T51
Test name
Test status
Simulation time 6288874773 ps
CPU time 13.29 seconds
Started Aug 17 05:36:20 PM PDT 24
Finished Aug 17 05:36:34 PM PDT 24
Peak memory 198268 kb
Host smart-71454e4a-8154-47b8-a534-9d5a4fdc554e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003324845 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.4003324845
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2457184056
Short name T304
Test name
Test status
Simulation time 1991246196538 ps
CPU time 1506.97 seconds
Started Aug 17 05:36:47 PM PDT 24
Finished Aug 17 06:01:54 PM PDT 24
Peak memory 183464 kb
Host smart-bc868895-3274-4a9b-b565-2d100c201835
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457184056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2457184056
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3727514984
Short name T398
Test name
Test status
Simulation time 389592903410 ps
CPU time 167.63 seconds
Started Aug 17 05:36:43 PM PDT 24
Finished Aug 17 05:39:31 PM PDT 24
Peak memory 183580 kb
Host smart-42c85de7-67a2-4c37-8e95-06e09d7b3d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727514984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3727514984
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.588857985
Short name T337
Test name
Test status
Simulation time 12002036474 ps
CPU time 100.29 seconds
Started Aug 17 05:36:45 PM PDT 24
Finished Aug 17 05:38:25 PM PDT 24
Peak memory 191756 kb
Host smart-02f4ab95-d987-46b6-b1e1-a4d675f87b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588857985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.588857985
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.4023014001
Short name T158
Test name
Test status
Simulation time 50263179384 ps
CPU time 109.32 seconds
Started Aug 17 05:36:44 PM PDT 24
Finished Aug 17 05:38:33 PM PDT 24
Peak memory 191744 kb
Host smart-2bf95d49-1aee-4bca-a065-dd45f69b662b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023014001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.4023014001
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.4253224522
Short name T143
Test name
Test status
Simulation time 133194053239 ps
CPU time 236.04 seconds
Started Aug 17 05:36:44 PM PDT 24
Finished Aug 17 05:40:40 PM PDT 24
Peak memory 183548 kb
Host smart-3889b010-181a-482b-9b2b-6781f0bff27f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253224522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.4253224522
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2956297343
Short name T62
Test name
Test status
Simulation time 249340437694 ps
CPU time 192.44 seconds
Started Aug 17 05:36:45 PM PDT 24
Finished Aug 17 05:39:57 PM PDT 24
Peak memory 183588 kb
Host smart-5ee94e8a-cce7-4f30-97b5-8450fc741cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956297343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2956297343
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1499003923
Short name T286
Test name
Test status
Simulation time 346869050931 ps
CPU time 456.31 seconds
Started Aug 17 05:36:46 PM PDT 24
Finished Aug 17 05:44:22 PM PDT 24
Peak memory 191708 kb
Host smart-e34af054-5f0b-4271-aa65-d4ad690bb0da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499003923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1499003923
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1381337315
Short name T340
Test name
Test status
Simulation time 208690232250 ps
CPU time 391.94 seconds
Started Aug 17 05:36:44 PM PDT 24
Finished Aug 17 05:43:16 PM PDT 24
Peak memory 191740 kb
Host smart-af795e50-fd68-4305-be7e-abc740ceb70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381337315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1381337315
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.490062609
Short name T47
Test name
Test status
Simulation time 3944628994277 ps
CPU time 480.99 seconds
Started Aug 17 05:36:48 PM PDT 24
Finished Aug 17 05:44:49 PM PDT 24
Peak memory 191760 kb
Host smart-af57a368-398c-4d61-a4fb-d039b332e291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490062609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
490062609
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1893887963
Short name T148
Test name
Test status
Simulation time 608031176242 ps
CPU time 307.41 seconds
Started Aug 17 05:36:45 PM PDT 24
Finished Aug 17 05:41:52 PM PDT 24
Peak memory 183544 kb
Host smart-79a24505-feac-46fc-a5b5-7bac8893485f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893887963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1893887963
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.450105392
Short name T402
Test name
Test status
Simulation time 465846585315 ps
CPU time 185.16 seconds
Started Aug 17 05:36:44 PM PDT 24
Finished Aug 17 05:39:49 PM PDT 24
Peak memory 183584 kb
Host smart-f3ac685a-fee7-46bc-9e62-62d78ac8b6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450105392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.450105392
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.949711998
Short name T26
Test name
Test status
Simulation time 26161883230 ps
CPU time 12.29 seconds
Started Aug 17 05:36:47 PM PDT 24
Finished Aug 17 05:36:59 PM PDT 24
Peak memory 183784 kb
Host smart-99110ad5-febe-45fd-a059-10aa726458bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949711998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.949711998
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1648944605
Short name T428
Test name
Test status
Simulation time 14480355694 ps
CPU time 19.85 seconds
Started Aug 17 05:36:45 PM PDT 24
Finished Aug 17 05:37:05 PM PDT 24
Peak memory 183508 kb
Host smart-898ffe1e-fa9c-464c-a8af-3a3b7406a727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648944605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1648944605
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.862604357
Short name T224
Test name
Test status
Simulation time 5504957168 ps
CPU time 2.7 seconds
Started Aug 17 05:36:49 PM PDT 24
Finished Aug 17 05:36:52 PM PDT 24
Peak memory 183544 kb
Host smart-7ac2c757-b7d6-4f34-b2ce-4bff6bc39575
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862604357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.862604357
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3847446061
Short name T386
Test name
Test status
Simulation time 109997864276 ps
CPU time 169.24 seconds
Started Aug 17 05:36:46 PM PDT 24
Finished Aug 17 05:39:35 PM PDT 24
Peak memory 183584 kb
Host smart-a9670eef-aab8-4520-9ed4-f3e080822ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847446061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3847446061
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1283405806
Short name T248
Test name
Test status
Simulation time 676117145628 ps
CPU time 1569.44 seconds
Started Aug 17 05:36:46 PM PDT 24
Finished Aug 17 06:02:56 PM PDT 24
Peak memory 191656 kb
Host smart-e655ed00-2c14-4e88-90ed-90750e2f59dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283405806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1283405806
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.4229575807
Short name T409
Test name
Test status
Simulation time 747731433 ps
CPU time 0.75 seconds
Started Aug 17 05:36:46 PM PDT 24
Finished Aug 17 05:36:46 PM PDT 24
Peak memory 183256 kb
Host smart-b4603831-2f85-4b48-acc9-ec396f04cc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229575807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.4229575807
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1582713263
Short name T425
Test name
Test status
Simulation time 417583978119 ps
CPU time 345.71 seconds
Started Aug 17 05:36:47 PM PDT 24
Finished Aug 17 05:42:33 PM PDT 24
Peak memory 183452 kb
Host smart-b58a6282-9c9b-4ef7-b9c8-17fad9e1677b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582713263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1582713263
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.995702895
Short name T390
Test name
Test status
Simulation time 770498037702 ps
CPU time 104.13 seconds
Started Aug 17 05:36:46 PM PDT 24
Finished Aug 17 05:38:30 PM PDT 24
Peak memory 183512 kb
Host smart-60bb69c3-3b51-4c30-884b-2e0d67fd808c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995702895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.995702895
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.751006116
Short name T358
Test name
Test status
Simulation time 3142671406 ps
CPU time 2.6 seconds
Started Aug 17 05:36:45 PM PDT 24
Finished Aug 17 05:36:47 PM PDT 24
Peak memory 195108 kb
Host smart-ed26293b-f158-447d-925b-6cc0c790c29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751006116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.751006116
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.579164130
Short name T330
Test name
Test status
Simulation time 1001851421661 ps
CPU time 922.85 seconds
Started Aug 17 05:36:55 PM PDT 24
Finished Aug 17 05:52:18 PM PDT 24
Peak memory 183612 kb
Host smart-546b9035-7fb8-4af1-87ec-4d6585f44c44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579164130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.579164130
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1606643025
Short name T381
Test name
Test status
Simulation time 132675788950 ps
CPU time 194.42 seconds
Started Aug 17 05:36:54 PM PDT 24
Finished Aug 17 05:40:08 PM PDT 24
Peak memory 183580 kb
Host smart-d7958fab-fddc-41fc-82bf-fe5ff552523c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606643025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1606643025
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1960198200
Short name T276
Test name
Test status
Simulation time 116689233125 ps
CPU time 220.16 seconds
Started Aug 17 05:36:52 PM PDT 24
Finished Aug 17 05:40:32 PM PDT 24
Peak memory 191756 kb
Host smart-865af4f4-0674-42cd-84e1-8b6bfdf43019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960198200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1960198200
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.913687546
Short name T347
Test name
Test status
Simulation time 13411709793 ps
CPU time 10.72 seconds
Started Aug 17 05:36:55 PM PDT 24
Finished Aug 17 05:37:06 PM PDT 24
Peak memory 192240 kb
Host smart-590fc2be-9378-4f0c-a948-f015d488c8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913687546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.913687546
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3211056936
Short name T412
Test name
Test status
Simulation time 533599505633 ps
CPU time 230.13 seconds
Started Aug 17 05:36:58 PM PDT 24
Finished Aug 17 05:40:49 PM PDT 24
Peak memory 191708 kb
Host smart-cc4d26e8-e205-48e9-8124-1946e3867807
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211056936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3211056936
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2098661031
Short name T322
Test name
Test status
Simulation time 203711085349 ps
CPU time 96.82 seconds
Started Aug 17 05:36:58 PM PDT 24
Finished Aug 17 05:38:35 PM PDT 24
Peak memory 183464 kb
Host smart-efa62575-ab5c-44b6-8f9c-dd6e71c2c9de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098661031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2098661031
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2814698615
Short name T415
Test name
Test status
Simulation time 46035359898 ps
CPU time 65.6 seconds
Started Aug 17 05:37:01 PM PDT 24
Finished Aug 17 05:38:07 PM PDT 24
Peak memory 183580 kb
Host smart-798cfd3b-7e65-4d7d-9024-fbab226fa485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814698615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2814698615
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2432381566
Short name T442
Test name
Test status
Simulation time 77596924271 ps
CPU time 539.24 seconds
Started Aug 17 05:37:01 PM PDT 24
Finished Aug 17 05:46:00 PM PDT 24
Peak memory 183612 kb
Host smart-2d7f29a7-04e5-4686-ad96-62f3ec64e126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432381566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2432381566
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1464275203
Short name T43
Test name
Test status
Simulation time 27455641231 ps
CPU time 208.95 seconds
Started Aug 17 05:36:56 PM PDT 24
Finished Aug 17 05:40:25 PM PDT 24
Peak memory 183592 kb
Host smart-4514a5ec-f6d4-4fb3-8458-d30ea0ddefda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464275203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1464275203
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1258772448
Short name T341
Test name
Test status
Simulation time 48946283926 ps
CPU time 43.46 seconds
Started Aug 17 05:36:56 PM PDT 24
Finished Aug 17 05:37:39 PM PDT 24
Peak memory 183512 kb
Host smart-225c79b2-f788-41ca-a5de-f46bd2de867f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258772448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1258772448
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3428340754
Short name T366
Test name
Test status
Simulation time 141865006663 ps
CPU time 107.6 seconds
Started Aug 17 05:36:54 PM PDT 24
Finished Aug 17 05:38:42 PM PDT 24
Peak memory 183588 kb
Host smart-8af3f2b5-3d24-426b-951d-7109c8bc49b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428340754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3428340754
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.4130559929
Short name T365
Test name
Test status
Simulation time 500380769 ps
CPU time 0.71 seconds
Started Aug 17 05:37:01 PM PDT 24
Finished Aug 17 05:37:02 PM PDT 24
Peak memory 183264 kb
Host smart-072b552d-51e0-4542-88e1-351b83cd75f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130559929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.4130559929
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3967404161
Short name T326
Test name
Test status
Simulation time 148716340447 ps
CPU time 264.73 seconds
Started Aug 17 05:36:56 PM PDT 24
Finished Aug 17 05:41:21 PM PDT 24
Peak memory 183552 kb
Host smart-df0905ca-88ac-47bb-ac7c-a93bfaf88f67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967404161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3967404161
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1780959483
Short name T382
Test name
Test status
Simulation time 29202101228 ps
CPU time 45.52 seconds
Started Aug 17 05:36:56 PM PDT 24
Finished Aug 17 05:37:42 PM PDT 24
Peak memory 183592 kb
Host smart-332d9c71-71dd-4e91-ab6b-0d3ecd03178b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780959483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1780959483
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.886781955
Short name T290
Test name
Test status
Simulation time 37611745155 ps
CPU time 229.08 seconds
Started Aug 17 05:37:01 PM PDT 24
Finished Aug 17 05:40:51 PM PDT 24
Peak memory 191780 kb
Host smart-710b8f89-c2a9-42dd-a475-170ade91701c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886781955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.886781955
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3496621806
Short name T374
Test name
Test status
Simulation time 343362695666 ps
CPU time 476.68 seconds
Started Aug 17 05:36:54 PM PDT 24
Finished Aug 17 05:44:51 PM PDT 24
Peak memory 191700 kb
Host smart-d8fa8986-8dd3-43ec-90dd-b574709cc92f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496621806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3496621806
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.227491642
Short name T222
Test name
Test status
Simulation time 517495739160 ps
CPU time 231.18 seconds
Started Aug 17 05:37:01 PM PDT 24
Finished Aug 17 05:40:52 PM PDT 24
Peak memory 183588 kb
Host smart-88e262a3-65ae-4861-a45d-98b413cc2dd2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227491642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.227491642
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3287450331
Short name T436
Test name
Test status
Simulation time 26240332075 ps
CPU time 40.06 seconds
Started Aug 17 05:36:54 PM PDT 24
Finished Aug 17 05:37:34 PM PDT 24
Peak memory 183540 kb
Host smart-87fb3b70-c5ca-4ca8-8c62-91fea91fec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287450331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3287450331
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1486068814
Short name T174
Test name
Test status
Simulation time 695446246183 ps
CPU time 637.18 seconds
Started Aug 17 05:36:52 PM PDT 24
Finished Aug 17 05:47:30 PM PDT 24
Peak memory 191740 kb
Host smart-50951b57-d649-4eb5-9bd6-efc9c5a40595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486068814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1486068814
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2569285457
Short name T393
Test name
Test status
Simulation time 31128587523 ps
CPU time 44.24 seconds
Started Aug 17 05:36:59 PM PDT 24
Finished Aug 17 05:37:44 PM PDT 24
Peak memory 191712 kb
Host smart-037129de-6a3c-4972-b116-945f5976defd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569285457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2569285457
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.4059309608
Short name T117
Test name
Test status
Simulation time 824914390580 ps
CPU time 741.03 seconds
Started Aug 17 05:36:54 PM PDT 24
Finished Aug 17 05:49:16 PM PDT 24
Peak memory 191780 kb
Host smart-828dd6a0-d361-4e07-8c1f-3a776303411e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059309608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.4059309608
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.2817454299
Short name T41
Test name
Test status
Simulation time 8402828571 ps
CPU time 22.89 seconds
Started Aug 17 05:36:53 PM PDT 24
Finished Aug 17 05:37:16 PM PDT 24
Peak memory 195368 kb
Host smart-d2ba7e4e-b558-4ddf-aa25-f7398222f5d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817454299 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.2817454299
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2605157371
Short name T3
Test name
Test status
Simulation time 108693380561 ps
CPU time 192.39 seconds
Started Aug 17 05:36:21 PM PDT 24
Finished Aug 17 05:39:33 PM PDT 24
Peak memory 183588 kb
Host smart-5307abf9-62b9-4b6f-8cb8-08999d66e925
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605157371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2605157371
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3956582820
Short name T373
Test name
Test status
Simulation time 706946362168 ps
CPU time 91.92 seconds
Started Aug 17 05:36:21 PM PDT 24
Finished Aug 17 05:37:53 PM PDT 24
Peak memory 183576 kb
Host smart-bfc96ab4-d974-4d4e-b8ec-62e543ee4887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956582820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3956582820
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1143442046
Short name T249
Test name
Test status
Simulation time 322808779554 ps
CPU time 169.46 seconds
Started Aug 17 05:36:21 PM PDT 24
Finished Aug 17 05:39:11 PM PDT 24
Peak memory 194736 kb
Host smart-0d10165b-d29e-47b3-aa85-9ff5fe6e2f94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143442046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1143442046
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3260540973
Short name T344
Test name
Test status
Simulation time 46933464105 ps
CPU time 52.73 seconds
Started Aug 17 05:36:32 PM PDT 24
Finished Aug 17 05:37:25 PM PDT 24
Peak memory 183492 kb
Host smart-b470a0e2-61c4-43be-966b-28952c5ba7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260540973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3260540973
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3729557875
Short name T18
Test name
Test status
Simulation time 40096094 ps
CPU time 0.77 seconds
Started Aug 17 05:36:32 PM PDT 24
Finished Aug 17 05:36:33 PM PDT 24
Peak memory 213860 kb
Host smart-ca094680-6b9b-4dac-a8e2-c0ab627ffc47
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729557875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3729557875
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1681595179
Short name T22
Test name
Test status
Simulation time 30712744208 ps
CPU time 52.32 seconds
Started Aug 17 05:36:33 PM PDT 24
Finished Aug 17 05:37:25 PM PDT 24
Peak memory 195344 kb
Host smart-dc2eec20-1f22-4a19-804d-e395b960f83d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681595179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1681595179
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.1397553518
Short name T42
Test name
Test status
Simulation time 1492951005 ps
CPU time 10.69 seconds
Started Aug 17 05:36:21 PM PDT 24
Finished Aug 17 05:36:32 PM PDT 24
Peak memory 198172 kb
Host smart-0c2c92ac-6055-47df-b7b5-592014df76f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397553518 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.1397553518
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2246965501
Short name T404
Test name
Test status
Simulation time 810945705505 ps
CPU time 712.25 seconds
Started Aug 17 05:36:56 PM PDT 24
Finished Aug 17 05:48:49 PM PDT 24
Peak memory 183496 kb
Host smart-a51dd716-7699-4565-b1e6-b5a211f56b44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246965501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2246965501
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2826960107
Short name T376
Test name
Test status
Simulation time 200441210848 ps
CPU time 77.86 seconds
Started Aug 17 05:36:55 PM PDT 24
Finished Aug 17 05:38:13 PM PDT 24
Peak memory 183580 kb
Host smart-bc45e0b1-7a6c-4c2d-8700-31d8b3c33171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826960107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2826960107
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1429018169
Short name T387
Test name
Test status
Simulation time 1331048338 ps
CPU time 0.97 seconds
Started Aug 17 05:36:53 PM PDT 24
Finished Aug 17 05:36:54 PM PDT 24
Peak memory 193384 kb
Host smart-76d1eec5-6f13-447a-9649-c269460af67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429018169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1429018169
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3079022983
Short name T420
Test name
Test status
Simulation time 204909325554 ps
CPU time 226.81 seconds
Started Aug 17 05:36:53 PM PDT 24
Finished Aug 17 05:40:40 PM PDT 24
Peak memory 183580 kb
Host smart-a37a3445-f450-45f5-a286-e9eef5eb6abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079022983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3079022983
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3351664100
Short name T385
Test name
Test status
Simulation time 674561756770 ps
CPU time 148.58 seconds
Started Aug 17 05:36:53 PM PDT 24
Finished Aug 17 05:39:22 PM PDT 24
Peak memory 183568 kb
Host smart-ae6bd1a0-3fc4-4c9e-a359-7c8ce6067b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351664100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3351664100
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2185028073
Short name T182
Test name
Test status
Simulation time 509310265833 ps
CPU time 440.74 seconds
Started Aug 17 05:36:54 PM PDT 24
Finished Aug 17 05:44:15 PM PDT 24
Peak memory 191668 kb
Host smart-32ce056e-0b7c-4ef9-b63e-8fcffb7c048f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185028073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2185028073
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.1681367526
Short name T406
Test name
Test status
Simulation time 197228827902 ps
CPU time 114.26 seconds
Started Aug 17 05:36:58 PM PDT 24
Finished Aug 17 05:38:53 PM PDT 24
Peak memory 183500 kb
Host smart-a4378226-c13c-4199-a5f1-c85fd42e569c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681367526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.1681367526
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3245624583
Short name T370
Test name
Test status
Simulation time 294737430938 ps
CPU time 231.7 seconds
Started Aug 17 05:36:54 PM PDT 24
Finished Aug 17 05:40:46 PM PDT 24
Peak memory 183492 kb
Host smart-d9b170bf-fa5f-43c4-ac4c-bad4b70a6ee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245624583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3245624583
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2974432888
Short name T432
Test name
Test status
Simulation time 196661863168 ps
CPU time 256.75 seconds
Started Aug 17 05:37:05 PM PDT 24
Finished Aug 17 05:41:22 PM PDT 24
Peak memory 183584 kb
Host smart-a47025fb-44f6-46f7-b6a9-2516d3af27ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974432888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2974432888
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.563708785
Short name T335
Test name
Test status
Simulation time 336280522328 ps
CPU time 1438.61 seconds
Started Aug 17 05:36:56 PM PDT 24
Finished Aug 17 06:00:55 PM PDT 24
Peak memory 191820 kb
Host smart-72cf1295-49d3-4a74-aaea-73e7a7037fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563708785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.563708785
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1136941240
Short name T359
Test name
Test status
Simulation time 84352828337 ps
CPU time 110.42 seconds
Started Aug 17 05:36:59 PM PDT 24
Finished Aug 17 05:38:50 PM PDT 24
Peak memory 195344 kb
Host smart-a975c3b6-547f-4b44-ba46-e05ec99e4960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136941240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1136941240
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3195879036
Short name T403
Test name
Test status
Simulation time 432103270760 ps
CPU time 179.16 seconds
Started Aug 17 05:37:06 PM PDT 24
Finished Aug 17 05:40:06 PM PDT 24
Peak memory 183568 kb
Host smart-637cf009-ac97-4bdb-ac7b-25a0e2fef8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195879036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3195879036
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.4044039465
Short name T210
Test name
Test status
Simulation time 117336643923 ps
CPU time 590.75 seconds
Started Aug 17 05:37:00 PM PDT 24
Finished Aug 17 05:46:50 PM PDT 24
Peak memory 191788 kb
Host smart-3c301375-dca6-4952-9776-704321822e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044039465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.4044039465
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.242055249
Short name T35
Test name
Test status
Simulation time 986033946448 ps
CPU time 384.93 seconds
Started Aug 17 05:37:03 PM PDT 24
Finished Aug 17 05:43:28 PM PDT 24
Peak memory 191676 kb
Host smart-8bff79dd-aaea-4752-9eb1-3a9b175d790a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242055249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
242055249
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2453488916
Short name T61
Test name
Test status
Simulation time 50970546516 ps
CPU time 86.79 seconds
Started Aug 17 05:37:02 PM PDT 24
Finished Aug 17 05:38:28 PM PDT 24
Peak memory 183472 kb
Host smart-a83614cf-0c41-47df-885a-6b159a0fe09e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453488916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2453488916
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.976768165
Short name T360
Test name
Test status
Simulation time 342200337542 ps
CPU time 167.14 seconds
Started Aug 17 05:37:02 PM PDT 24
Finished Aug 17 05:39:49 PM PDT 24
Peak memory 183456 kb
Host smart-c19e78a5-9fe9-42e1-ae93-e3d8c8771995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976768165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.976768165
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.4060397219
Short name T424
Test name
Test status
Simulation time 121469373606 ps
CPU time 111 seconds
Started Aug 17 05:37:09 PM PDT 24
Finished Aug 17 05:39:00 PM PDT 24
Peak memory 191760 kb
Host smart-6f0e1dee-f516-4de8-bdb7-00ee3364e5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060397219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.4060397219
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3916587593
Short name T434
Test name
Test status
Simulation time 111294881955 ps
CPU time 95.99 seconds
Started Aug 17 05:37:10 PM PDT 24
Finished Aug 17 05:38:46 PM PDT 24
Peak memory 183568 kb
Host smart-8b656009-1a30-4ec3-a3cd-2420d8c2a250
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916587593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3916587593
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.871243437
Short name T417
Test name
Test status
Simulation time 233588298982 ps
CPU time 90.49 seconds
Started Aug 17 05:37:05 PM PDT 24
Finished Aug 17 05:38:36 PM PDT 24
Peak memory 183548 kb
Host smart-509db8a8-2c26-486d-b508-0fb734a99d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871243437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.871243437
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2437514426
Short name T444
Test name
Test status
Simulation time 128096077213 ps
CPU time 557.16 seconds
Started Aug 17 05:36:59 PM PDT 24
Finished Aug 17 05:46:16 PM PDT 24
Peak memory 191788 kb
Host smart-cc76c999-201d-4727-a046-e0adc620cdfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437514426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2437514426
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3307504772
Short name T328
Test name
Test status
Simulation time 92527002956 ps
CPU time 201.51 seconds
Started Aug 17 05:37:04 PM PDT 24
Finished Aug 17 05:40:25 PM PDT 24
Peak memory 183552 kb
Host smart-d5f163bf-9758-44ec-8833-b7fb93fe1959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307504772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3307504772
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.318245016
Short name T166
Test name
Test status
Simulation time 84042194508 ps
CPU time 123.68 seconds
Started Aug 17 05:37:01 PM PDT 24
Finished Aug 17 05:39:05 PM PDT 24
Peak memory 183588 kb
Host smart-ec38c5a9-916b-4208-be78-51d4f9e5be48
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318245016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.318245016
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1235800135
Short name T378
Test name
Test status
Simulation time 129720586267 ps
CPU time 55.55 seconds
Started Aug 17 05:37:04 PM PDT 24
Finished Aug 17 05:37:59 PM PDT 24
Peak memory 183560 kb
Host smart-3bdb5528-2cd8-46f8-b3a0-56d766181b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235800135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1235800135
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2802558034
Short name T161
Test name
Test status
Simulation time 459590151587 ps
CPU time 256.42 seconds
Started Aug 17 05:37:00 PM PDT 24
Finished Aug 17 05:41:16 PM PDT 24
Peak memory 191748 kb
Host smart-75234ea9-0610-41cb-886d-a2dde4807cd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802558034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2802558034
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2937773205
Short name T132
Test name
Test status
Simulation time 3348614597 ps
CPU time 5.73 seconds
Started Aug 17 05:37:04 PM PDT 24
Finished Aug 17 05:37:10 PM PDT 24
Peak memory 183560 kb
Host smart-fd706607-5364-4f7e-bd46-9c0bc2d7babd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937773205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2937773205
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1335397333
Short name T5
Test name
Test status
Simulation time 400956923609 ps
CPU time 834.66 seconds
Started Aug 17 05:37:06 PM PDT 24
Finished Aug 17 05:51:00 PM PDT 24
Peak memory 191752 kb
Host smart-3ed71799-88a3-4d0d-bdc1-57920cb5dd2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335397333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1335397333
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.2109564237
Short name T13
Test name
Test status
Simulation time 1910962336 ps
CPU time 21.1 seconds
Started Aug 17 05:37:04 PM PDT 24
Finished Aug 17 05:37:25 PM PDT 24
Peak memory 198156 kb
Host smart-fd1d6eb8-b47a-428c-9d8a-437f428d53c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109564237 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.2109564237
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1746581402
Short name T392
Test name
Test status
Simulation time 136570743247 ps
CPU time 60.54 seconds
Started Aug 17 05:37:13 PM PDT 24
Finished Aug 17 05:38:14 PM PDT 24
Peak memory 183548 kb
Host smart-4f527c27-bfa8-4845-bcf5-402297b6ef3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746581402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1746581402
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.3285286359
Short name T353
Test name
Test status
Simulation time 48497839265 ps
CPU time 110.6 seconds
Started Aug 17 05:37:01 PM PDT 24
Finished Aug 17 05:38:52 PM PDT 24
Peak memory 183612 kb
Host smart-04debbf2-d31f-4400-b259-c20c38b520d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285286359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3285286359
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3778611007
Short name T379
Test name
Test status
Simulation time 140363012 ps
CPU time 0.8 seconds
Started Aug 17 05:37:13 PM PDT 24
Finished Aug 17 05:37:14 PM PDT 24
Peak memory 183208 kb
Host smart-905fccc9-69db-4222-bce4-1bcb1a6d0c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778611007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3778611007
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1310672000
Short name T72
Test name
Test status
Simulation time 305891631992 ps
CPU time 173.39 seconds
Started Aug 17 05:37:14 PM PDT 24
Finished Aug 17 05:40:07 PM PDT 24
Peak memory 191784 kb
Host smart-ec3e6568-a939-4a99-9976-0129eec4425b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310672000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1310672000
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3585838361
Short name T65
Test name
Test status
Simulation time 141623361330 ps
CPU time 49.91 seconds
Started Aug 17 05:37:15 PM PDT 24
Finished Aug 17 05:38:05 PM PDT 24
Peak memory 183624 kb
Host smart-98076db9-6d6f-499b-8e0a-aa3d73376fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585838361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3585838361
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1950155287
Short name T186
Test name
Test status
Simulation time 90074177064 ps
CPU time 158.34 seconds
Started Aug 17 05:37:14 PM PDT 24
Finished Aug 17 05:39:53 PM PDT 24
Peak memory 195304 kb
Host smart-b81fe207-e9a3-492e-b5b5-b654f53c2592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950155287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1950155287
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3466370274
Short name T225
Test name
Test status
Simulation time 129723117119 ps
CPU time 160.81 seconds
Started Aug 17 05:37:14 PM PDT 24
Finished Aug 17 05:39:55 PM PDT 24
Peak memory 191752 kb
Host smart-37d61d7c-c542-4289-9ab3-fac63fbfe017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466370274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3466370274
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2081479944
Short name T157
Test name
Test status
Simulation time 83018844847 ps
CPU time 107.88 seconds
Started Aug 17 05:37:18 PM PDT 24
Finished Aug 17 05:39:06 PM PDT 24
Peak memory 183500 kb
Host smart-69a9b2b2-42f2-496f-8782-d68cd85349b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081479944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2081479944
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3017946391
Short name T369
Test name
Test status
Simulation time 739514383 ps
CPU time 1.43 seconds
Started Aug 17 05:37:17 PM PDT 24
Finished Aug 17 05:37:19 PM PDT 24
Peak memory 183188 kb
Host smart-9c81ed3e-266f-464a-afd6-2f1e72ad0533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017946391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3017946391
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1340198339
Short name T103
Test name
Test status
Simulation time 24761693181 ps
CPU time 14.77 seconds
Started Aug 17 05:37:19 PM PDT 24
Finished Aug 17 05:37:34 PM PDT 24
Peak memory 194048 kb
Host smart-a2936c5c-8695-4b2b-a4db-fe7c3a44f3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340198339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1340198339
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1698801172
Short name T423
Test name
Test status
Simulation time 518557366322 ps
CPU time 199.29 seconds
Started Aug 17 05:37:18 PM PDT 24
Finished Aug 17 05:40:37 PM PDT 24
Peak memory 183500 kb
Host smart-c5aa9061-3e90-428a-ad70-8207e00cdcb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698801172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1698801172
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.551974268
Short name T10
Test name
Test status
Simulation time 22763622916 ps
CPU time 31.46 seconds
Started Aug 17 05:36:23 PM PDT 24
Finished Aug 17 05:36:55 PM PDT 24
Peak memory 183568 kb
Host smart-6ef855b1-4484-412d-bdb4-68dd6dd9024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551974268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.551974268
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2202867853
Short name T188
Test name
Test status
Simulation time 50420863022 ps
CPU time 148.42 seconds
Started Aug 17 05:36:21 PM PDT 24
Finished Aug 17 05:38:50 PM PDT 24
Peak memory 195448 kb
Host smart-945b0433-503e-4750-ad92-3637da8b4ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202867853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2202867853
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1377421406
Short name T363
Test name
Test status
Simulation time 67585173 ps
CPU time 0.64 seconds
Started Aug 17 05:36:22 PM PDT 24
Finished Aug 17 05:36:22 PM PDT 24
Peak memory 183280 kb
Host smart-0f8d3866-8cce-443a-8324-31e5d854457f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377421406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1377421406
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3968774721
Short name T227
Test name
Test status
Simulation time 1884281047832 ps
CPU time 892.01 seconds
Started Aug 17 05:36:19 PM PDT 24
Finished Aug 17 05:51:11 PM PDT 24
Peak memory 191744 kb
Host smart-edbc9831-1d9d-4f73-b401-507e6c67a4c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968774721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3968774721
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.836597219
Short name T289
Test name
Test status
Simulation time 61408905616 ps
CPU time 33.54 seconds
Started Aug 17 05:37:18 PM PDT 24
Finished Aug 17 05:37:52 PM PDT 24
Peak memory 183544 kb
Host smart-58d141b9-205b-4319-853f-604f25eca2c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836597219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.836597219
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.501272280
Short name T233
Test name
Test status
Simulation time 95929408408 ps
CPU time 697.69 seconds
Started Aug 17 05:37:18 PM PDT 24
Finished Aug 17 05:48:56 PM PDT 24
Peak memory 194224 kb
Host smart-ba542ca8-895b-4eac-ab7d-d6c116d8d8cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501272280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.501272280
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3450565498
Short name T283
Test name
Test status
Simulation time 405940729445 ps
CPU time 355.65 seconds
Started Aug 17 05:37:16 PM PDT 24
Finished Aug 17 05:43:12 PM PDT 24
Peak memory 191764 kb
Host smart-fdf585a6-bb9f-4c0a-9f47-699085a438d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450565498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3450565498
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2631179369
Short name T291
Test name
Test status
Simulation time 46847487938 ps
CPU time 110.94 seconds
Started Aug 17 05:37:15 PM PDT 24
Finished Aug 17 05:39:06 PM PDT 24
Peak memory 193856 kb
Host smart-1fffe961-f181-44f5-9ce7-1f76523ec898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631179369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2631179369
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.4075773510
Short name T285
Test name
Test status
Simulation time 725025818086 ps
CPU time 286.53 seconds
Started Aug 17 05:37:18 PM PDT 24
Finished Aug 17 05:42:05 PM PDT 24
Peak memory 191824 kb
Host smart-3e2b2aff-115a-4c2f-95af-f77d461aeb9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075773510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.4075773510
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3432224862
Short name T236
Test name
Test status
Simulation time 219923613142 ps
CPU time 550.29 seconds
Started Aug 17 05:37:16 PM PDT 24
Finished Aug 17 05:46:27 PM PDT 24
Peak memory 191792 kb
Host smart-629abf2a-436d-46f6-ba51-06f1c810526f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432224862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3432224862
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3793630804
Short name T345
Test name
Test status
Simulation time 113360132473 ps
CPU time 520.45 seconds
Started Aug 17 05:37:20 PM PDT 24
Finished Aug 17 05:46:00 PM PDT 24
Peak memory 191788 kb
Host smart-21ac85a3-2d6e-4d78-af78-64a5a5c5875e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793630804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3793630804
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1557179391
Short name T118
Test name
Test status
Simulation time 1902967434849 ps
CPU time 1001.74 seconds
Started Aug 17 05:36:22 PM PDT 24
Finished Aug 17 05:53:03 PM PDT 24
Peak memory 182564 kb
Host smart-f30b4b68-7d24-498c-b7ae-fa902827e8f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557179391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1557179391
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.1529098575
Short name T367
Test name
Test status
Simulation time 727811627695 ps
CPU time 225.11 seconds
Started Aug 17 05:36:21 PM PDT 24
Finished Aug 17 05:40:06 PM PDT 24
Peak memory 183572 kb
Host smart-b6757a24-65a7-41f0-9fb5-2fda82d4cec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529098575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1529098575
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.739876639
Short name T311
Test name
Test status
Simulation time 139690076687 ps
CPU time 375.81 seconds
Started Aug 17 05:36:21 PM PDT 24
Finished Aug 17 05:42:37 PM PDT 24
Peak memory 191700 kb
Host smart-3090841e-1715-45b0-8073-5c09282fb6cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739876639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.739876639
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3319348828
Short name T278
Test name
Test status
Simulation time 583796514144 ps
CPU time 124.96 seconds
Started Aug 17 05:36:19 PM PDT 24
Finished Aug 17 05:38:24 PM PDT 24
Peak memory 191776 kb
Host smart-3cc7846a-2399-4efc-8328-549d2116c84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319348828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3319348828
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3141025178
Short name T349
Test name
Test status
Simulation time 708785446946 ps
CPU time 553.81 seconds
Started Aug 17 05:36:18 PM PDT 24
Finished Aug 17 05:45:32 PM PDT 24
Peak memory 191748 kb
Host smart-d3437f72-91c5-4e7d-a7e0-ea2ba9d6e6bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141025178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3141025178
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/63.rv_timer_random.2593852099
Short name T142
Test name
Test status
Simulation time 106872747763 ps
CPU time 586.39 seconds
Started Aug 17 05:37:25 PM PDT 24
Finished Aug 17 05:47:11 PM PDT 24
Peak memory 191772 kb
Host smart-9894821f-523b-49d1-8b75-a28515347b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593852099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2593852099
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2251872965
Short name T160
Test name
Test status
Simulation time 204032706847 ps
CPU time 311.55 seconds
Started Aug 17 05:37:25 PM PDT 24
Finished Aug 17 05:42:36 PM PDT 24
Peak memory 191780 kb
Host smart-b7cadabb-94eb-4c18-aec0-fd6ccd58bc72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251872965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2251872965
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2017758626
Short name T272
Test name
Test status
Simulation time 417990541432 ps
CPU time 271.71 seconds
Started Aug 17 05:37:25 PM PDT 24
Finished Aug 17 05:41:57 PM PDT 24
Peak memory 191788 kb
Host smart-f1e7eb65-21a4-417c-8335-d17805c4eae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017758626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2017758626
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3436014608
Short name T245
Test name
Test status
Simulation time 147133946375 ps
CPU time 1249.25 seconds
Started Aug 17 05:37:24 PM PDT 24
Finished Aug 17 05:58:13 PM PDT 24
Peak memory 191804 kb
Host smart-06bc53bd-5989-48b9-b071-00dd7d674b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436014608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3436014608
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.4234764349
Short name T191
Test name
Test status
Simulation time 45830592553 ps
CPU time 76.47 seconds
Started Aug 17 05:37:25 PM PDT 24
Finished Aug 17 05:38:41 PM PDT 24
Peak memory 195236 kb
Host smart-12328bcf-7d7b-401d-b4d3-ce04cea3ec6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234764349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4234764349
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3432287716
Short name T342
Test name
Test status
Simulation time 54164623025 ps
CPU time 187.18 seconds
Started Aug 17 05:37:26 PM PDT 24
Finished Aug 17 05:40:33 PM PDT 24
Peak memory 191708 kb
Host smart-4dd2b100-32f6-4f24-b142-58cb6bc32e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432287716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3432287716
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3826205389
Short name T137
Test name
Test status
Simulation time 51031569139 ps
CPU time 524.07 seconds
Started Aug 17 05:37:25 PM PDT 24
Finished Aug 17 05:46:10 PM PDT 24
Peak memory 191740 kb
Host smart-621a2c90-bdf6-40c0-a16b-6ec81aeaf607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826205389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3826205389
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.24108576
Short name T124
Test name
Test status
Simulation time 33182724433 ps
CPU time 49.09 seconds
Started Aug 17 05:36:20 PM PDT 24
Finished Aug 17 05:37:10 PM PDT 24
Peak memory 183512 kb
Host smart-014edc30-acac-4856-8ed4-0da778e5d1ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24108576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
rv_timer_cfg_update_on_fly.24108576
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3745248783
Short name T431
Test name
Test status
Simulation time 214192158882 ps
CPU time 79.92 seconds
Started Aug 17 05:36:19 PM PDT 24
Finished Aug 17 05:37:39 PM PDT 24
Peak memory 183544 kb
Host smart-f5d73b24-1cec-41f3-9230-70f28f8baa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745248783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3745248783
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2658873406
Short name T59
Test name
Test status
Simulation time 77605147781 ps
CPU time 180.86 seconds
Started Aug 17 05:36:21 PM PDT 24
Finished Aug 17 05:39:22 PM PDT 24
Peak memory 191736 kb
Host smart-04acfa80-5335-49aa-a91f-e2946f29d579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658873406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2658873406
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.302073103
Short name T413
Test name
Test status
Simulation time 50954766 ps
CPU time 0.59 seconds
Started Aug 17 05:36:20 PM PDT 24
Finished Aug 17 05:36:21 PM PDT 24
Peak memory 183196 kb
Host smart-f927d8bd-cda3-4177-97d0-2d682f745707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302073103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.302073103
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2417752725
Short name T71
Test name
Test status
Simulation time 292075171949 ps
CPU time 607.67 seconds
Started Aug 17 05:36:23 PM PDT 24
Finished Aug 17 05:46:30 PM PDT 24
Peak memory 196148 kb
Host smart-a63b5099-4e01-4878-a832-67f2d949577d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417752725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2417752725
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.2773145554
Short name T453
Test name
Test status
Simulation time 27336846579 ps
CPU time 41.07 seconds
Started Aug 17 05:37:25 PM PDT 24
Finished Aug 17 05:38:06 PM PDT 24
Peak memory 183540 kb
Host smart-38087037-3020-486e-9ebe-c64a42e47095
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773145554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2773145554
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.633352208
Short name T136
Test name
Test status
Simulation time 167178319829 ps
CPU time 126.58 seconds
Started Aug 17 05:37:24 PM PDT 24
Finished Aug 17 05:39:31 PM PDT 24
Peak memory 183592 kb
Host smart-fe9793c1-d67a-4be6-a9e2-b7635602663a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633352208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.633352208
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.390446044
Short name T128
Test name
Test status
Simulation time 162866522352 ps
CPU time 168.3 seconds
Started Aug 17 05:37:24 PM PDT 24
Finished Aug 17 05:40:13 PM PDT 24
Peak memory 191700 kb
Host smart-6026bb72-6746-4735-9867-6f16adb9ee20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390446044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.390446044
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2487159201
Short name T199
Test name
Test status
Simulation time 434568973279 ps
CPU time 359.82 seconds
Started Aug 17 05:37:24 PM PDT 24
Finished Aug 17 05:43:24 PM PDT 24
Peak memory 191800 kb
Host smart-9bdbfe23-6504-4555-92a7-4eb2e285a05c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487159201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2487159201
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3928200599
Short name T163
Test name
Test status
Simulation time 365072897165 ps
CPU time 699.48 seconds
Started Aug 17 05:37:25 PM PDT 24
Finished Aug 17 05:49:05 PM PDT 24
Peak memory 191756 kb
Host smart-70e3d072-424c-4f68-a104-dd86fd357ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928200599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3928200599
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.4267726471
Short name T111
Test name
Test status
Simulation time 134584332412 ps
CPU time 375.85 seconds
Started Aug 17 05:37:25 PM PDT 24
Finished Aug 17 05:43:41 PM PDT 24
Peak memory 191812 kb
Host smart-ce3ff44d-1b12-456f-9009-3a0de631d057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267726471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4267726471
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2143862749
Short name T175
Test name
Test status
Simulation time 187625449562 ps
CPU time 332.65 seconds
Started Aug 17 05:37:25 PM PDT 24
Finished Aug 17 05:42:58 PM PDT 24
Peak memory 191804 kb
Host smart-82a4dd70-a53b-4431-b4e9-58d2ad5366c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143862749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2143862749
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2406495897
Short name T258
Test name
Test status
Simulation time 118900276671 ps
CPU time 213.21 seconds
Started Aug 17 05:37:27 PM PDT 24
Finished Aug 17 05:41:00 PM PDT 24
Peak memory 191768 kb
Host smart-ab0f044e-ebeb-4b1a-9c2d-31f392989563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406495897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2406495897
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2725974955
Short name T312
Test name
Test status
Simulation time 302992955795 ps
CPU time 2002.25 seconds
Started Aug 17 05:37:24 PM PDT 24
Finished Aug 17 06:10:47 PM PDT 24
Peak memory 191772 kb
Host smart-f1f54633-e936-4745-9e7b-5c0fc4ffc813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725974955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2725974955
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3919164845
Short name T306
Test name
Test status
Simulation time 446551028230 ps
CPU time 718.4 seconds
Started Aug 17 05:36:21 PM PDT 24
Finished Aug 17 05:48:19 PM PDT 24
Peak memory 183536 kb
Host smart-0770f3f2-078a-4cfa-8799-96e1e92ba7da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919164845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3919164845
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.4230382746
Short name T23
Test name
Test status
Simulation time 5650856864 ps
CPU time 2.39 seconds
Started Aug 17 05:36:32 PM PDT 24
Finished Aug 17 05:36:34 PM PDT 24
Peak memory 183512 kb
Host smart-630ada45-eed7-4235-aed0-69e2b5093a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230382746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.4230382746
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2354626184
Short name T144
Test name
Test status
Simulation time 446992343165 ps
CPU time 467.71 seconds
Started Aug 17 05:36:21 PM PDT 24
Finished Aug 17 05:44:09 PM PDT 24
Peak memory 190788 kb
Host smart-f21a2c30-19be-481e-8721-2fb8c0d1f58c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354626184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2354626184
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.353398022
Short name T357
Test name
Test status
Simulation time 23151324191 ps
CPU time 40.68 seconds
Started Aug 17 05:36:22 PM PDT 24
Finished Aug 17 05:37:03 PM PDT 24
Peak memory 195432 kb
Host smart-e1e9fed1-99f5-4fe1-9c68-1a8c3350b10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353398022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.353398022
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.176095277
Short name T7
Test name
Test status
Simulation time 243867914585 ps
CPU time 400.23 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:43:12 PM PDT 24
Peak memory 191712 kb
Host smart-bee297bc-e2c8-4fb9-b79d-fc6e0bde6f07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176095277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.176095277
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/82.rv_timer_random.3585694696
Short name T313
Test name
Test status
Simulation time 23427797795 ps
CPU time 40.79 seconds
Started Aug 17 05:37:25 PM PDT 24
Finished Aug 17 05:38:06 PM PDT 24
Peak memory 183572 kb
Host smart-e992fca6-7bdd-41c7-89c2-0053009c5397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585694696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3585694696
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1529695225
Short name T50
Test name
Test status
Simulation time 582483620995 ps
CPU time 1247.49 seconds
Started Aug 17 05:37:33 PM PDT 24
Finished Aug 17 05:58:21 PM PDT 24
Peak memory 191804 kb
Host smart-6a0b9429-8bce-4338-8d2f-809fc3bf423a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529695225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1529695225
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3084497552
Short name T299
Test name
Test status
Simulation time 304787524999 ps
CPU time 197.96 seconds
Started Aug 17 05:37:34 PM PDT 24
Finished Aug 17 05:40:52 PM PDT 24
Peak memory 191768 kb
Host smart-d3407687-c59e-4e38-a699-e618b480a278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084497552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3084497552
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4262538422
Short name T179
Test name
Test status
Simulation time 445083967353 ps
CPU time 239.47 seconds
Started Aug 17 05:37:36 PM PDT 24
Finished Aug 17 05:41:35 PM PDT 24
Peak memory 191732 kb
Host smart-3f2bde71-7845-4bea-acb4-1c19d765da5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262538422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4262538422
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2225326584
Short name T101
Test name
Test status
Simulation time 584929326373 ps
CPU time 445.11 seconds
Started Aug 17 05:37:33 PM PDT 24
Finished Aug 17 05:44:58 PM PDT 24
Peak memory 191772 kb
Host smart-05becf42-e9df-489a-bddd-17b2c1fcc34a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225326584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2225326584
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1532178460
Short name T346
Test name
Test status
Simulation time 29626376348 ps
CPU time 50.59 seconds
Started Aug 17 05:37:32 PM PDT 24
Finished Aug 17 05:38:23 PM PDT 24
Peak memory 183596 kb
Host smart-2418c97a-6738-4108-8ce8-857fef596177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532178460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1532178460
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2982403070
Short name T202
Test name
Test status
Simulation time 1051283069109 ps
CPU time 440.83 seconds
Started Aug 17 05:37:35 PM PDT 24
Finished Aug 17 05:44:56 PM PDT 24
Peak memory 191784 kb
Host smart-916c8d36-c613-4842-9e92-a74c7ff87a53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982403070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2982403070
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.430155924
Short name T300
Test name
Test status
Simulation time 783275863816 ps
CPU time 458.45 seconds
Started Aug 17 05:36:30 PM PDT 24
Finished Aug 17 05:44:09 PM PDT 24
Peak memory 183560 kb
Host smart-0fd032da-17ff-41da-bad4-8b562983663a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430155924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.430155924
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1075041994
Short name T396
Test name
Test status
Simulation time 118469166183 ps
CPU time 182.94 seconds
Started Aug 17 05:36:21 PM PDT 24
Finished Aug 17 05:39:24 PM PDT 24
Peak memory 183500 kb
Host smart-9a375ee1-7512-4b71-91a3-6a6e9ea32e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075041994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1075041994
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3277159621
Short name T162
Test name
Test status
Simulation time 421949175599 ps
CPU time 1705.93 seconds
Started Aug 17 05:36:21 PM PDT 24
Finished Aug 17 06:04:47 PM PDT 24
Peak memory 191772 kb
Host smart-2634d1bb-a0c5-495b-a28e-6821caf62cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277159621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3277159621
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.934594563
Short name T333
Test name
Test status
Simulation time 121795680721 ps
CPU time 112.77 seconds
Started Aug 17 05:36:31 PM PDT 24
Finished Aug 17 05:38:24 PM PDT 24
Peak memory 183600 kb
Host smart-d612aeed-455c-4dfe-8ce7-bf6fd1ca4e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934594563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.934594563
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/91.rv_timer_random.322412278
Short name T266
Test name
Test status
Simulation time 50148873146 ps
CPU time 1667.59 seconds
Started Aug 17 05:37:36 PM PDT 24
Finished Aug 17 06:05:23 PM PDT 24
Peak memory 191736 kb
Host smart-e013eabb-30db-44ae-b2c4-48257a4a1b94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322412278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.322412278
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3738643044
Short name T287
Test name
Test status
Simulation time 99949984160 ps
CPU time 49.37 seconds
Started Aug 17 05:37:33 PM PDT 24
Finished Aug 17 05:38:23 PM PDT 24
Peak memory 183556 kb
Host smart-bbba9255-bfc0-4f50-b7ff-d48535e4c995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738643044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3738643044
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.4176104185
Short name T215
Test name
Test status
Simulation time 576544504199 ps
CPU time 1120.96 seconds
Started Aug 17 05:37:33 PM PDT 24
Finished Aug 17 05:56:14 PM PDT 24
Peak memory 191788 kb
Host smart-dc346647-2565-4b04-b2d7-14d28dfddce9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176104185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.4176104185
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3012723936
Short name T281
Test name
Test status
Simulation time 805034979708 ps
CPU time 476.21 seconds
Started Aug 17 05:37:36 PM PDT 24
Finished Aug 17 05:45:32 PM PDT 24
Peak memory 191732 kb
Host smart-482726fd-260e-44bd-8d1e-f8b0030385d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012723936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3012723936
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3933194546
Short name T209
Test name
Test status
Simulation time 89182394861 ps
CPU time 214.74 seconds
Started Aug 17 05:37:33 PM PDT 24
Finished Aug 17 05:41:08 PM PDT 24
Peak memory 191760 kb
Host smart-934c7046-33c2-49a7-8e69-c981eea72099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933194546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3933194546
Directory /workspace/99.rv_timer_random/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%