Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.36 99.04 100.00 100.00 100.00 99.55


Total test records in report: 582
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T510 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2853332394 Aug 18 04:40:28 PM PDT 24 Aug 18 04:40:28 PM PDT 24 46519680 ps
T511 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.82895382 Aug 18 04:40:05 PM PDT 24 Aug 18 04:40:05 PM PDT 24 53734683 ps
T512 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2166937264 Aug 18 04:39:59 PM PDT 24 Aug 18 04:39:59 PM PDT 24 190302095 ps
T513 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.192105260 Aug 18 04:40:25 PM PDT 24 Aug 18 04:40:25 PM PDT 24 40711488 ps
T514 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1705234584 Aug 18 04:40:24 PM PDT 24 Aug 18 04:40:25 PM PDT 24 21592172 ps
T65 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.511394297 Aug 18 04:40:15 PM PDT 24 Aug 18 04:40:16 PM PDT 24 55167447 ps
T515 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3693936403 Aug 18 04:40:27 PM PDT 24 Aug 18 04:40:27 PM PDT 24 13908465 ps
T516 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2207387786 Aug 18 04:39:59 PM PDT 24 Aug 18 04:40:00 PM PDT 24 57776234 ps
T517 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3170463749 Aug 18 04:40:22 PM PDT 24 Aug 18 04:40:23 PM PDT 24 263432877 ps
T518 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1089310208 Aug 18 04:40:28 PM PDT 24 Aug 18 04:40:29 PM PDT 24 13106488 ps
T519 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2143156518 Aug 18 04:39:58 PM PDT 24 Aug 18 04:39:59 PM PDT 24 37440365 ps
T86 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.846603754 Aug 18 04:40:27 PM PDT 24 Aug 18 04:40:28 PM PDT 24 85365973 ps
T520 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2194974342 Aug 18 04:40:27 PM PDT 24 Aug 18 04:40:28 PM PDT 24 26243817 ps
T521 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.528810906 Aug 18 04:40:04 PM PDT 24 Aug 18 04:40:05 PM PDT 24 28374121 ps
T522 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.233280656 Aug 18 04:40:25 PM PDT 24 Aug 18 04:40:26 PM PDT 24 18146591 ps
T66 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2397835037 Aug 18 04:39:58 PM PDT 24 Aug 18 04:39:59 PM PDT 24 15598880 ps
T523 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1676449320 Aug 18 04:40:25 PM PDT 24 Aug 18 04:40:26 PM PDT 24 35060190 ps
T524 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3996501098 Aug 18 04:40:04 PM PDT 24 Aug 18 04:40:05 PM PDT 24 122244204 ps
T525 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.677433683 Aug 18 04:40:23 PM PDT 24 Aug 18 04:40:24 PM PDT 24 66560226 ps
T67 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2664204634 Aug 18 04:40:03 PM PDT 24 Aug 18 04:40:04 PM PDT 24 32906102 ps
T526 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3078908162 Aug 18 04:40:23 PM PDT 24 Aug 18 04:40:24 PM PDT 24 22202610 ps
T527 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2929688076 Aug 18 04:40:17 PM PDT 24 Aug 18 04:40:18 PM PDT 24 48498003 ps
T528 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1575339055 Aug 18 04:39:56 PM PDT 24 Aug 18 04:39:57 PM PDT 24 46276457 ps
T529 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3325179434 Aug 18 04:40:22 PM PDT 24 Aug 18 04:40:23 PM PDT 24 50904569 ps
T530 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3454377613 Aug 18 04:40:16 PM PDT 24 Aug 18 04:40:17 PM PDT 24 33426299 ps
T531 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3572990000 Aug 18 04:40:16 PM PDT 24 Aug 18 04:40:17 PM PDT 24 15088680 ps
T532 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3681628231 Aug 18 04:39:56 PM PDT 24 Aug 18 04:39:57 PM PDT 24 33412378 ps
T533 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2113776613 Aug 18 04:40:23 PM PDT 24 Aug 18 04:40:24 PM PDT 24 142071185 ps
T534 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3898443052 Aug 18 04:40:24 PM PDT 24 Aug 18 04:40:24 PM PDT 24 34903844 ps
T535 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.243808595 Aug 18 04:40:31 PM PDT 24 Aug 18 04:40:32 PM PDT 24 15846577 ps
T536 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2223885938 Aug 18 04:39:56 PM PDT 24 Aug 18 04:39:57 PM PDT 24 25468823 ps
T537 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3959054670 Aug 18 04:40:05 PM PDT 24 Aug 18 04:40:06 PM PDT 24 133497249 ps
T538 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3803262800 Aug 18 04:39:59 PM PDT 24 Aug 18 04:40:00 PM PDT 24 16767031 ps
T539 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2743073707 Aug 18 04:40:18 PM PDT 24 Aug 18 04:40:20 PM PDT 24 500476066 ps
T68 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2660028477 Aug 18 04:40:06 PM PDT 24 Aug 18 04:40:07 PM PDT 24 20985105 ps
T540 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2553697043 Aug 18 04:40:23 PM PDT 24 Aug 18 04:40:24 PM PDT 24 23932384 ps
T69 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.225828291 Aug 18 04:39:55 PM PDT 24 Aug 18 04:39:56 PM PDT 24 25477225 ps
T541 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1845675190 Aug 18 04:40:08 PM PDT 24 Aug 18 04:40:09 PM PDT 24 37688079 ps
T542 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4212694789 Aug 18 04:40:15 PM PDT 24 Aug 18 04:40:17 PM PDT 24 31287669 ps
T543 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.326684077 Aug 18 04:39:57 PM PDT 24 Aug 18 04:40:00 PM PDT 24 173976762 ps
T544 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2923040363 Aug 18 04:40:24 PM PDT 24 Aug 18 04:40:25 PM PDT 24 14996088 ps
T545 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2249378971 Aug 18 04:40:05 PM PDT 24 Aug 18 04:40:06 PM PDT 24 26684201 ps
T546 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2537305468 Aug 18 04:40:04 PM PDT 24 Aug 18 04:40:05 PM PDT 24 81503128 ps
T547 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2785893085 Aug 18 04:40:16 PM PDT 24 Aug 18 04:40:18 PM PDT 24 249603495 ps
T548 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.936977037 Aug 18 04:39:57 PM PDT 24 Aug 18 04:39:58 PM PDT 24 93487548 ps
T549 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2639072426 Aug 18 04:40:04 PM PDT 24 Aug 18 04:40:07 PM PDT 24 294442940 ps
T550 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.244652317 Aug 18 04:40:15 PM PDT 24 Aug 18 04:40:16 PM PDT 24 27094395 ps
T551 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2237446598 Aug 18 04:40:18 PM PDT 24 Aug 18 04:40:19 PM PDT 24 33210519 ps
T552 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3754612377 Aug 18 04:40:28 PM PDT 24 Aug 18 04:40:28 PM PDT 24 198900626 ps
T553 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3830952748 Aug 18 04:40:24 PM PDT 24 Aug 18 04:40:25 PM PDT 24 40356851 ps
T554 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.521137144 Aug 18 04:40:04 PM PDT 24 Aug 18 04:40:06 PM PDT 24 794066180 ps
T555 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2248997767 Aug 18 04:40:16 PM PDT 24 Aug 18 04:40:18 PM PDT 24 112041204 ps
T556 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1857704454 Aug 18 04:40:15 PM PDT 24 Aug 18 04:40:17 PM PDT 24 245099751 ps
T557 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3699428201 Aug 18 04:40:20 PM PDT 24 Aug 18 04:40:21 PM PDT 24 226331097 ps
T558 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.4242636379 Aug 18 04:40:15 PM PDT 24 Aug 18 04:40:15 PM PDT 24 41727846 ps
T559 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.639019293 Aug 18 04:40:06 PM PDT 24 Aug 18 04:40:07 PM PDT 24 14698526 ps
T560 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3130812219 Aug 18 04:40:04 PM PDT 24 Aug 18 04:40:04 PM PDT 24 110309169 ps
T561 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.658846888 Aug 18 04:40:16 PM PDT 24 Aug 18 04:40:17 PM PDT 24 82108065 ps
T70 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3576746532 Aug 18 04:40:22 PM PDT 24 Aug 18 04:40:23 PM PDT 24 55254192 ps
T562 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2567350676 Aug 18 04:39:53 PM PDT 24 Aug 18 04:39:54 PM PDT 24 35756487 ps
T563 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2039511659 Aug 18 04:40:18 PM PDT 24 Aug 18 04:40:19 PM PDT 24 13771773 ps
T564 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1175495263 Aug 18 04:40:25 PM PDT 24 Aug 18 04:40:26 PM PDT 24 22981578 ps
T565 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3835579205 Aug 18 04:40:17 PM PDT 24 Aug 18 04:40:17 PM PDT 24 17537205 ps
T566 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.549791883 Aug 18 04:40:24 PM PDT 24 Aug 18 04:40:25 PM PDT 24 71075116 ps
T567 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1605098647 Aug 18 04:39:58 PM PDT 24 Aug 18 04:40:00 PM PDT 24 927990351 ps
T568 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2892646700 Aug 18 04:40:23 PM PDT 24 Aug 18 04:40:24 PM PDT 24 14420161 ps
T569 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1532220846 Aug 18 04:40:16 PM PDT 24 Aug 18 04:40:17 PM PDT 24 29062159 ps
T570 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1568927452 Aug 18 04:39:59 PM PDT 24 Aug 18 04:40:01 PM PDT 24 27453052 ps
T571 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.959412787 Aug 18 04:40:25 PM PDT 24 Aug 18 04:40:27 PM PDT 24 126288666 ps
T572 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.547389290 Aug 18 04:40:25 PM PDT 24 Aug 18 04:40:26 PM PDT 24 40203346 ps
T573 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3875997688 Aug 18 04:40:02 PM PDT 24 Aug 18 04:40:03 PM PDT 24 305974784 ps
T574 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1921061185 Aug 18 04:39:50 PM PDT 24 Aug 18 04:39:51 PM PDT 24 277914153 ps
T575 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.82681417 Aug 18 04:40:22 PM PDT 24 Aug 18 04:40:23 PM PDT 24 20247013 ps
T576 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4177177979 Aug 18 04:39:57 PM PDT 24 Aug 18 04:39:59 PM PDT 24 351270973 ps
T577 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.4186707764 Aug 18 04:40:24 PM PDT 24 Aug 18 04:40:24 PM PDT 24 18963812 ps
T578 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.943459523 Aug 18 04:39:58 PM PDT 24 Aug 18 04:39:59 PM PDT 24 23786887 ps
T71 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.199112767 Aug 18 04:39:54 PM PDT 24 Aug 18 04:39:55 PM PDT 24 13880722 ps
T579 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1586366521 Aug 18 04:39:50 PM PDT 24 Aug 18 04:39:51 PM PDT 24 67042485 ps
T580 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2505900494 Aug 18 04:40:05 PM PDT 24 Aug 18 04:40:06 PM PDT 24 67868207 ps
T72 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3647392563 Aug 18 04:39:48 PM PDT 24 Aug 18 04:39:49 PM PDT 24 62879034 ps
T581 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2971385535 Aug 18 04:40:15 PM PDT 24 Aug 18 04:40:18 PM PDT 24 594973772 ps
T582 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2650985938 Aug 18 04:40:28 PM PDT 24 Aug 18 04:40:29 PM PDT 24 14715562 ps

Test location /workspace/coverage/default/155.rv_timer_random.3212376858
Short name T3
Test name
Test status
Simulation time 171215481496 ps
CPU time 619.01 seconds
Started Aug 18 05:21:39 PM PDT 24
Finished Aug 18 05:31:59 PM PDT 24
Peak memory 191764 kb
Host smart-f3f9a5b1-2978-4918-8cb6-473e82ef8a11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212376858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3212376858
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.2697704412
Short name T14
Test name
Test status
Simulation time 3852734617 ps
CPU time 31.22 seconds
Started Aug 18 05:20:40 PM PDT 24
Finished Aug 18 05:21:11 PM PDT 24
Peak memory 198212 kb
Host smart-358658dc-8e22-4ba2-83d1-9efb0ce25dd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697704412 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.2697704412
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1085109629
Short name T138
Test name
Test status
Simulation time 872261661356 ps
CPU time 3430.1 seconds
Started Aug 18 05:20:41 PM PDT 24
Finished Aug 18 06:17:51 PM PDT 24
Peak memory 191688 kb
Host smart-26805496-d27a-425d-b2ff-ebf0834e30ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085109629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1085109629
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.248491900
Short name T23
Test name
Test status
Simulation time 117705708 ps
CPU time 1.32 seconds
Started Aug 18 04:40:15 PM PDT 24
Finished Aug 18 04:40:16 PM PDT 24
Peak memory 183784 kb
Host smart-acbe7223-3a5f-445f-8e4b-4c0fded9675a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248491900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.248491900
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2056139204
Short name T11
Test name
Test status
Simulation time 716327035739 ps
CPU time 1762.47 seconds
Started Aug 18 05:20:15 PM PDT 24
Finished Aug 18 05:49:38 PM PDT 24
Peak memory 191700 kb
Host smart-cf6c3149-0ef6-4525-a3f6-67eb3bf01625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056139204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2056139204
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3513338070
Short name T52
Test name
Test status
Simulation time 769597624662 ps
CPU time 2020.1 seconds
Started Aug 18 05:21:00 PM PDT 24
Finished Aug 18 05:54:41 PM PDT 24
Peak memory 191668 kb
Host smart-3db7fb67-f701-4944-8b74-8e89d5da3b89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513338070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3513338070
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.908213554
Short name T121
Test name
Test status
Simulation time 190860099789 ps
CPU time 650.64 seconds
Started Aug 18 05:20:44 PM PDT 24
Finished Aug 18 05:31:35 PM PDT 24
Peak memory 191696 kb
Host smart-4b42ece2-8974-40af-85c5-1f5a30fadf6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908213554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
908213554
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1083406964
Short name T152
Test name
Test status
Simulation time 997656503328 ps
CPU time 721.57 seconds
Started Aug 18 05:20:17 PM PDT 24
Finished Aug 18 05:32:19 PM PDT 24
Peak memory 195416 kb
Host smart-4c03564a-5d82-4ce1-b1cd-ebeb3c221052
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083406964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1083406964
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1550942442
Short name T149
Test name
Test status
Simulation time 1769878018371 ps
CPU time 1746.12 seconds
Started Aug 18 05:20:55 PM PDT 24
Finished Aug 18 05:50:02 PM PDT 24
Peak memory 196560 kb
Host smart-2f615397-f424-4497-b2da-50c603088aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550942442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1550942442
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2370553973
Short name T238
Test name
Test status
Simulation time 1772229510989 ps
CPU time 3273.67 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 06:15:27 PM PDT 24
Peak memory 191668 kb
Host smart-f6eb9ad9-45fc-4fc5-a97f-0c992bce0951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370553973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2370553973
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2025406939
Short name T26
Test name
Test status
Simulation time 59744151 ps
CPU time 0.59 seconds
Started Aug 18 04:40:16 PM PDT 24
Finished Aug 18 04:40:16 PM PDT 24
Peak memory 192576 kb
Host smart-2461f03d-58cc-4b2c-96a6-854eecada091
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025406939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2025406939
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.340764606
Short name T164
Test name
Test status
Simulation time 1785124739149 ps
CPU time 772.7 seconds
Started Aug 18 05:20:28 PM PDT 24
Finished Aug 18 05:33:21 PM PDT 24
Peak memory 195900 kb
Host smart-3c4017ad-f774-41f3-97e5-084d31bc73d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340764606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
340764606
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1817794780
Short name T148
Test name
Test status
Simulation time 7216255345646 ps
CPU time 2304.27 seconds
Started Aug 18 05:20:15 PM PDT 24
Finished Aug 18 05:58:39 PM PDT 24
Peak memory 196868 kb
Host smart-55005c80-b6e6-4159-b429-0c99a5a66f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817794780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1817794780
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1119345352
Short name T17
Test name
Test status
Simulation time 165514087 ps
CPU time 0.94 seconds
Started Aug 18 05:20:07 PM PDT 24
Finished Aug 18 05:20:08 PM PDT 24
Peak memory 214524 kb
Host smart-c7cdb94a-7a7a-4425-a2b0-5e4b9018af7f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119345352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1119345352
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2671135963
Short name T57
Test name
Test status
Simulation time 411447332037 ps
CPU time 978.74 seconds
Started Aug 18 05:20:24 PM PDT 24
Finished Aug 18 05:36:43 PM PDT 24
Peak memory 195724 kb
Host smart-4f1e94a0-dd24-4950-8dcf-880d46b1c54d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671135963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2671135963
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.4243536878
Short name T254
Test name
Test status
Simulation time 4716916991404 ps
CPU time 2160.64 seconds
Started Aug 18 05:20:31 PM PDT 24
Finished Aug 18 05:56:32 PM PDT 24
Peak memory 191740 kb
Host smart-8f3b38d1-b35c-4713-b6fd-28edb0736283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243536878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.4243536878
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1318774375
Short name T228
Test name
Test status
Simulation time 1469013742598 ps
CPU time 1352.53 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:43:26 PM PDT 24
Peak memory 196508 kb
Host smart-30dee237-410e-4841-86b2-ccf930654299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318774375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1318774375
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1242182686
Short name T306
Test name
Test status
Simulation time 9640465768648 ps
CPU time 1918.14 seconds
Started Aug 18 05:20:58 PM PDT 24
Finished Aug 18 05:52:56 PM PDT 24
Peak memory 191696 kb
Host smart-4d2b2a99-5789-4e1f-8804-7238b31a276f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242182686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1242182686
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/123.rv_timer_random.2074406620
Short name T156
Test name
Test status
Simulation time 139004938108 ps
CPU time 240.9 seconds
Started Aug 18 05:21:19 PM PDT 24
Finished Aug 18 05:25:20 PM PDT 24
Peak memory 191668 kb
Host smart-136a1ca8-3f38-4dd1-988f-650a56f425c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074406620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2074406620
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.4058433492
Short name T190
Test name
Test status
Simulation time 9733218041577 ps
CPU time 1915.96 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:52:19 PM PDT 24
Peak memory 196532 kb
Host smart-119532c3-534f-4116-8f59-a474ebba8fb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058433492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.4058433492
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_random.2824278640
Short name T97
Test name
Test status
Simulation time 190948437889 ps
CPU time 254.4 seconds
Started Aug 18 05:20:30 PM PDT 24
Finished Aug 18 05:24:45 PM PDT 24
Peak memory 193844 kb
Host smart-1b77bd7f-74b9-430c-abfa-c32096acffb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824278640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2824278640
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.356035515
Short name T284
Test name
Test status
Simulation time 251921376620 ps
CPU time 634.16 seconds
Started Aug 18 05:20:15 PM PDT 24
Finished Aug 18 05:30:49 PM PDT 24
Peak memory 195016 kb
Host smart-afcd517a-cfef-4f64-a214-f1277eb221da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356035515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.356035515
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/197.rv_timer_random.3726352767
Short name T157
Test name
Test status
Simulation time 106100148222 ps
CPU time 427.86 seconds
Started Aug 18 05:21:50 PM PDT 24
Finished Aug 18 05:28:58 PM PDT 24
Peak memory 192864 kb
Host smart-b1fa3a41-a8c4-4ea8-96ef-6ce5393182a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726352767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3726352767
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2275221932
Short name T161
Test name
Test status
Simulation time 203661327753 ps
CPU time 913.21 seconds
Started Aug 18 05:21:11 PM PDT 24
Finished Aug 18 05:36:24 PM PDT 24
Peak memory 191756 kb
Host smart-098152c5-e393-4d4b-b4b0-f6aa730c8c28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275221932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2275221932
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1277464455
Short name T210
Test name
Test status
Simulation time 609233652492 ps
CPU time 391.33 seconds
Started Aug 18 05:21:12 PM PDT 24
Finished Aug 18 05:27:44 PM PDT 24
Peak memory 191720 kb
Host smart-e1e95446-0cc6-4e1f-91dc-0b34a398d7d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277464455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1277464455
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3907228212
Short name T314
Test name
Test status
Simulation time 1409279342637 ps
CPU time 401.41 seconds
Started Aug 18 05:21:19 PM PDT 24
Finished Aug 18 05:28:01 PM PDT 24
Peak memory 191684 kb
Host smart-f4895859-b2c3-4767-b3f5-88eb6bd50e26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907228212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3907228212
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2573720031
Short name T5
Test name
Test status
Simulation time 2394037833294 ps
CPU time 1069.72 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:38:03 PM PDT 24
Peak memory 191716 kb
Host smart-0deda816-c266-4e1c-901e-9d6395daec1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573720031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2573720031
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/149.rv_timer_random.2337412989
Short name T250
Test name
Test status
Simulation time 89659760641 ps
CPU time 156.53 seconds
Started Aug 18 05:21:32 PM PDT 24
Finished Aug 18 05:24:09 PM PDT 24
Peak memory 183480 kb
Host smart-33db0ac3-9d70-449c-8d1b-7bddb7578012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337412989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2337412989
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.4173428204
Short name T143
Test name
Test status
Simulation time 194283045462 ps
CPU time 381.48 seconds
Started Aug 18 05:21:42 PM PDT 24
Finished Aug 18 05:28:03 PM PDT 24
Peak memory 191744 kb
Host smart-38071149-e414-45bc-97bc-3b2d3547dc0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173428204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.4173428204
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2030704350
Short name T246
Test name
Test status
Simulation time 689964541884 ps
CPU time 740.39 seconds
Started Aug 18 05:20:22 PM PDT 24
Finished Aug 18 05:32:42 PM PDT 24
Peak memory 196796 kb
Host smart-82069f8a-e285-4d89-bb7f-f989f16683ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030704350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2030704350
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_random.2234569399
Short name T240
Test name
Test status
Simulation time 217817115037 ps
CPU time 678.1 seconds
Started Aug 18 05:20:10 PM PDT 24
Finished Aug 18 05:31:28 PM PDT 24
Peak memory 191596 kb
Host smart-954254e4-63af-42e7-8a45-40125e9d8e0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234569399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2234569399
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.4006450559
Short name T361
Test name
Test status
Simulation time 124353897661 ps
CPU time 270.74 seconds
Started Aug 18 05:21:39 PM PDT 24
Finished Aug 18 05:26:10 PM PDT 24
Peak memory 191772 kb
Host smart-eab1fa8d-6f08-45da-9b66-93e7ed2c7335
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006450559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.4006450559
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random.2406242227
Short name T233
Test name
Test status
Simulation time 168196619776 ps
CPU time 329.97 seconds
Started Aug 18 05:20:12 PM PDT 24
Finished Aug 18 05:25:42 PM PDT 24
Peak memory 191576 kb
Host smart-0a7aaa81-ef90-4483-9996-22cfc1856936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406242227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2406242227
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.2929554773
Short name T214
Test name
Test status
Simulation time 1306878193157 ps
CPU time 1788.68 seconds
Started Aug 18 05:21:02 PM PDT 24
Finished Aug 18 05:50:51 PM PDT 24
Peak memory 191764 kb
Host smart-20f8f596-c9fa-45ee-9ba0-b9e4afdfec95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929554773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2929554773
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3696177689
Short name T234
Test name
Test status
Simulation time 142776564045 ps
CPU time 197.42 seconds
Started Aug 18 05:21:44 PM PDT 24
Finished Aug 18 05:25:01 PM PDT 24
Peak memory 191784 kb
Host smart-97f66a8f-ffd1-404c-b8a6-c6bab44f909e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696177689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3696177689
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1700003976
Short name T177
Test name
Test status
Simulation time 483161690702 ps
CPU time 849.55 seconds
Started Aug 18 05:20:37 PM PDT 24
Finished Aug 18 05:34:47 PM PDT 24
Peak memory 191764 kb
Host smart-3da6a3d9-6330-4fbe-8bdc-9e5f12a17c65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700003976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1700003976
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.4238590401
Short name T53
Test name
Test status
Simulation time 362310097897 ps
CPU time 1199.49 seconds
Started Aug 18 05:20:31 PM PDT 24
Finished Aug 18 05:40:31 PM PDT 24
Peak memory 195680 kb
Host smart-c1a5d7b1-8a27-4916-8524-c92d834dd211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238590401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.4238590401
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3679045229
Short name T184
Test name
Test status
Simulation time 1004764078315 ps
CPU time 662.55 seconds
Started Aug 18 05:20:54 PM PDT 24
Finished Aug 18 05:31:57 PM PDT 24
Peak memory 191664 kb
Host smart-147ab652-d86d-4e3f-b645-14a0bdac4c24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679045229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3679045229
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/72.rv_timer_random.2192006307
Short name T170
Test name
Test status
Simulation time 114219688337 ps
CPU time 210.02 seconds
Started Aug 18 05:21:08 PM PDT 24
Finished Aug 18 05:24:38 PM PDT 24
Peak memory 191768 kb
Host smart-266c1b64-a152-4e61-849b-1df9bdc58a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192006307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2192006307
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.2988897135
Short name T181
Test name
Test status
Simulation time 128833133626 ps
CPU time 506.62 seconds
Started Aug 18 05:21:11 PM PDT 24
Finished Aug 18 05:29:38 PM PDT 24
Peak memory 195252 kb
Host smart-f004182f-f7e7-484e-ac5e-f54bb739dadc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988897135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2988897135
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1236558155
Short name T312
Test name
Test status
Simulation time 416557898062 ps
CPU time 453.88 seconds
Started Aug 18 05:21:20 PM PDT 24
Finished Aug 18 05:28:54 PM PDT 24
Peak memory 191700 kb
Host smart-c7d626b9-f529-4664-850b-89b52aa9e3c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236558155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1236558155
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.1922039384
Short name T110
Test name
Test status
Simulation time 496144487641 ps
CPU time 280.49 seconds
Started Aug 18 05:21:21 PM PDT 24
Finished Aug 18 05:26:02 PM PDT 24
Peak memory 191784 kb
Host smart-81350e71-6336-42ce-9457-9d662c798209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922039384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1922039384
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.3530741461
Short name T315
Test name
Test status
Simulation time 235484148675 ps
CPU time 262.29 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:24:36 PM PDT 24
Peak memory 195280 kb
Host smart-18caaf3a-5013-47f5-9cd4-ab5889de85f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530741461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3530741461
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2438262057
Short name T106
Test name
Test status
Simulation time 85461970808 ps
CPU time 314.57 seconds
Started Aug 18 05:21:37 PM PDT 24
Finished Aug 18 05:26:52 PM PDT 24
Peak memory 191712 kb
Host smart-ed1d88b0-5eff-4ca8-87ed-b6cddc3b7330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438262057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2438262057
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.197477654
Short name T368
Test name
Test status
Simulation time 93768934721 ps
CPU time 198.56 seconds
Started Aug 18 05:21:06 PM PDT 24
Finished Aug 18 05:24:25 PM PDT 24
Peak memory 190072 kb
Host smart-28087ec3-8ffd-4442-a0ca-b3990252ce34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197477654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.197477654
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1507704559
Short name T311
Test name
Test status
Simulation time 138857093537 ps
CPU time 228.28 seconds
Started Aug 18 05:21:06 PM PDT 24
Finished Aug 18 05:24:55 PM PDT 24
Peak memory 191760 kb
Host smart-719504c8-045b-411b-b119-76982327c51c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507704559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1507704559
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3139988447
Short name T218
Test name
Test status
Simulation time 451133179171 ps
CPU time 353.61 seconds
Started Aug 18 05:21:01 PM PDT 24
Finished Aug 18 05:26:55 PM PDT 24
Peak memory 191744 kb
Host smart-7bd0a9ab-7272-4d45-a17c-4468587c110d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139988447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3139988447
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.653342237
Short name T227
Test name
Test status
Simulation time 118986508872 ps
CPU time 188.52 seconds
Started Aug 18 05:21:21 PM PDT 24
Finished Aug 18 05:24:29 PM PDT 24
Peak memory 191776 kb
Host smart-bf53d9a0-44af-454b-beee-0e24f83d2e5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653342237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.653342237
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.2275646069
Short name T145
Test name
Test status
Simulation time 597248630826 ps
CPU time 417.72 seconds
Started Aug 18 05:20:16 PM PDT 24
Finished Aug 18 05:27:13 PM PDT 24
Peak memory 191808 kb
Host smart-dabb1c2e-0e7c-4f86-b30e-bc5eca7485e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275646069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2275646069
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2205661000
Short name T154
Test name
Test status
Simulation time 619768314850 ps
CPU time 673.88 seconds
Started Aug 18 05:21:39 PM PDT 24
Finished Aug 18 05:32:53 PM PDT 24
Peak memory 191764 kb
Host smart-ca485e59-980a-4c88-9c3d-673e1f624795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205661000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2205661000
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.784792446
Short name T88
Test name
Test status
Simulation time 624056996735 ps
CPU time 418.37 seconds
Started Aug 18 05:21:49 PM PDT 24
Finished Aug 18 05:28:47 PM PDT 24
Peak memory 191696 kb
Host smart-cdd32899-2290-4005-8692-352f959fb937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784792446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.784792446
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random.319407234
Short name T330
Test name
Test status
Simulation time 358769521613 ps
CPU time 221.61 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:24:35 PM PDT 24
Peak memory 191764 kb
Host smart-ad3d0cdf-75a6-4843-9c60-7dd078b7b36a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319407234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.319407234
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2980257478
Short name T318
Test name
Test status
Simulation time 88737483819 ps
CPU time 154.67 seconds
Started Aug 18 05:21:00 PM PDT 24
Finished Aug 18 05:23:34 PM PDT 24
Peak memory 183440 kb
Host smart-e41746e5-2b1d-4512-8a97-96618e98ac1f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980257478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2980257478
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.199112767
Short name T71
Test name
Test status
Simulation time 13880722 ps
CPU time 0.59 seconds
Started Aug 18 04:39:54 PM PDT 24
Finished Aug 18 04:39:55 PM PDT 24
Peak memory 183304 kb
Host smart-5fa76ead-a627-46a6-97d3-7785f07394b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199112767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.199112767
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2642533545
Short name T27
Test name
Test status
Simulation time 56973419 ps
CPU time 0.79 seconds
Started Aug 18 04:39:50 PM PDT 24
Finished Aug 18 04:39:51 PM PDT 24
Peak memory 193836 kb
Host smart-7c3e80ce-79a0-4b76-b337-e6f285b63a22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642533545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2642533545
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.846603754
Short name T86
Test name
Test status
Simulation time 85365973 ps
CPU time 1.11 seconds
Started Aug 18 04:40:27 PM PDT 24
Finished Aug 18 04:40:28 PM PDT 24
Peak memory 183884 kb
Host smart-6ef51f3f-f6ca-4f23-a809-e2aa52e08dee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846603754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.846603754
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/100.rv_timer_random.3519790399
Short name T182
Test name
Test status
Simulation time 127500657810 ps
CPU time 196.48 seconds
Started Aug 18 05:21:11 PM PDT 24
Finished Aug 18 05:24:27 PM PDT 24
Peak memory 191664 kb
Host smart-6fa17132-25e8-4eb7-932d-60f3c3835c14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519790399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3519790399
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.2126475074
Short name T99
Test name
Test status
Simulation time 116059009728 ps
CPU time 568.4 seconds
Started Aug 18 05:21:11 PM PDT 24
Finished Aug 18 05:30:40 PM PDT 24
Peak memory 195016 kb
Host smart-21f370bc-c94f-403f-8f4c-a456ab5b08f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126475074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2126475074
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3938874607
Short name T354
Test name
Test status
Simulation time 617835450352 ps
CPU time 346.97 seconds
Started Aug 18 05:21:10 PM PDT 24
Finished Aug 18 05:26:57 PM PDT 24
Peak memory 195680 kb
Host smart-014431c6-1a72-4061-9816-b8e41d2060c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938874607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3938874607
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.764436055
Short name T203
Test name
Test status
Simulation time 152379243800 ps
CPU time 349.09 seconds
Started Aug 18 05:21:34 PM PDT 24
Finished Aug 18 05:27:23 PM PDT 24
Peak memory 191756 kb
Host smart-f60a6099-f3dc-4351-ac53-a6924627e8a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764436055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.764436055
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.2382984882
Short name T325
Test name
Test status
Simulation time 77174762520 ps
CPU time 429.12 seconds
Started Aug 18 05:20:15 PM PDT 24
Finished Aug 18 05:27:25 PM PDT 24
Peak memory 195456 kb
Host smart-22ff9cfb-5dcb-4dd2-99ce-1b690c1634ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382984882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2382984882
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.1891896457
Short name T420
Test name
Test status
Simulation time 659822683088 ps
CPU time 652.51 seconds
Started Aug 18 05:21:40 PM PDT 24
Finished Aug 18 05:32:33 PM PDT 24
Peak memory 191736 kb
Host smart-2722b1b4-4108-455f-ba27-33e5ba24948d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891896457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1891896457
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2613463491
Short name T295
Test name
Test status
Simulation time 265788683819 ps
CPU time 250.48 seconds
Started Aug 18 05:21:41 PM PDT 24
Finished Aug 18 05:25:52 PM PDT 24
Peak memory 191692 kb
Host smart-b41ea32e-1488-4df7-870a-1ed45579412a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613463491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2613463491
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2322360004
Short name T259
Test name
Test status
Simulation time 24644838143 ps
CPU time 24.72 seconds
Started Aug 18 05:21:40 PM PDT 24
Finished Aug 18 05:22:05 PM PDT 24
Peak memory 183556 kb
Host smart-98c77950-cc0d-4cc0-8f2f-64d3953dffa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322360004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2322360004
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1499534396
Short name T209
Test name
Test status
Simulation time 122830154977 ps
CPU time 573.68 seconds
Started Aug 18 05:21:43 PM PDT 24
Finished Aug 18 05:31:17 PM PDT 24
Peak memory 194840 kb
Host smart-9c7ce06f-f243-49a5-8cd0-677c13cdbba2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499534396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1499534396
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2625492207
Short name T9
Test name
Test status
Simulation time 75197644843 ps
CPU time 751.28 seconds
Started Aug 18 05:21:56 PM PDT 24
Finished Aug 18 05:34:27 PM PDT 24
Peak memory 191764 kb
Host smart-d07df2f8-c519-4f8b-bde5-c0220bc379b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625492207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2625492207
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.28408788
Short name T236
Test name
Test status
Simulation time 104323083630 ps
CPU time 154.17 seconds
Started Aug 18 05:21:49 PM PDT 24
Finished Aug 18 05:24:23 PM PDT 24
Peak memory 191584 kb
Host smart-c28ae656-43d2-4991-8e44-78b55a25e7ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28408788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.28408788
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.766540065
Short name T103
Test name
Test status
Simulation time 238445247524 ps
CPU time 209.93 seconds
Started Aug 18 05:20:24 PM PDT 24
Finished Aug 18 05:23:54 PM PDT 24
Peak memory 183488 kb
Host smart-2bb653af-1082-4be3-858a-6c582a8d3e44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766540065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.766540065
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/58.rv_timer_random.569845554
Short name T232
Test name
Test status
Simulation time 487258601303 ps
CPU time 1099.01 seconds
Started Aug 18 05:21:02 PM PDT 24
Finished Aug 18 05:39:22 PM PDT 24
Peak memory 191680 kb
Host smart-8fb9d3d0-08d8-4fa7-acd1-4863ef675585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569845554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.569845554
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.755668024
Short name T302
Test name
Test status
Simulation time 340767325098 ps
CPU time 168.71 seconds
Started Aug 18 05:21:01 PM PDT 24
Finished Aug 18 05:23:50 PM PDT 24
Peak memory 191776 kb
Host smart-e53b1edf-711f-40c7-998c-c93e472c54ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755668024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.755668024
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1075728895
Short name T257
Test name
Test status
Simulation time 119517273448 ps
CPU time 169.95 seconds
Started Aug 18 05:21:19 PM PDT 24
Finished Aug 18 05:24:09 PM PDT 24
Peak memory 191816 kb
Host smart-49284b24-6842-4abf-a33f-4a34f4cd5ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075728895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1075728895
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3540964634
Short name T317
Test name
Test status
Simulation time 554856615740 ps
CPU time 633.8 seconds
Started Aug 18 05:21:20 PM PDT 24
Finished Aug 18 05:31:54 PM PDT 24
Peak memory 191584 kb
Host smart-7a82e330-caff-41e7-9d84-aa05bd3a9351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540964634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3540964634
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.6803917
Short name T235
Test name
Test status
Simulation time 84825007656 ps
CPU time 178.15 seconds
Started Aug 18 05:21:26 PM PDT 24
Finished Aug 18 05:24:24 PM PDT 24
Peak memory 191764 kb
Host smart-2f1138bc-8296-4a1e-9f15-55e69380adee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6803917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.6803917
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2994954427
Short name T263
Test name
Test status
Simulation time 460919922952 ps
CPU time 1151.53 seconds
Started Aug 18 05:21:22 PM PDT 24
Finished Aug 18 05:40:33 PM PDT 24
Peak memory 191752 kb
Host smart-f9d34f07-27eb-4346-8bce-b7925c12d4bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994954427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2994954427
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.970206939
Short name T194
Test name
Test status
Simulation time 70374307811 ps
CPU time 102.67 seconds
Started Aug 18 05:20:18 PM PDT 24
Finished Aug 18 05:22:01 PM PDT 24
Peak memory 191784 kb
Host smart-315ee4b7-c3e0-4643-812f-5fbefe98c9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970206939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.970206939
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/136.rv_timer_random.3822154344
Short name T193
Test name
Test status
Simulation time 98800821059 ps
CPU time 155.16 seconds
Started Aug 18 05:21:31 PM PDT 24
Finished Aug 18 05:24:06 PM PDT 24
Peak memory 195188 kb
Host smart-54e1b3c6-e40b-4761-99b0-2c0a04720964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822154344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3822154344
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1047903756
Short name T344
Test name
Test status
Simulation time 136356216573 ps
CPU time 298.32 seconds
Started Aug 18 05:21:29 PM PDT 24
Finished Aug 18 05:26:28 PM PDT 24
Peak memory 191816 kb
Host smart-d1b16e73-8e05-4f7c-96b1-86dd68523dc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047903756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1047903756
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.165065869
Short name T253
Test name
Test status
Simulation time 101466992006 ps
CPU time 542.19 seconds
Started Aug 18 05:21:32 PM PDT 24
Finished Aug 18 05:30:34 PM PDT 24
Peak memory 191824 kb
Host smart-bb7da4fb-e541-4f8b-bc5d-a9334c32f005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165065869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.165065869
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2059276111
Short name T4
Test name
Test status
Simulation time 35813599080 ps
CPU time 58.01 seconds
Started Aug 18 05:21:31 PM PDT 24
Finished Aug 18 05:22:30 PM PDT 24
Peak memory 183508 kb
Host smart-3809e4f3-0015-4109-ad76-2b3a3686f28b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059276111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2059276111
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1996674100
Short name T435
Test name
Test status
Simulation time 423030374487 ps
CPU time 406.83 seconds
Started Aug 18 05:20:18 PM PDT 24
Finished Aug 18 05:27:05 PM PDT 24
Peak memory 183572 kb
Host smart-ca677b46-6aa0-42ac-a692-f2a49ec11b65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996674100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1996674100
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/159.rv_timer_random.3641370777
Short name T363
Test name
Test status
Simulation time 181077857513 ps
CPU time 160.26 seconds
Started Aug 18 05:21:39 PM PDT 24
Finished Aug 18 05:24:20 PM PDT 24
Peak memory 192764 kb
Host smart-22ac1e1a-bb14-410c-ab51-fa65740dace8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641370777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3641370777
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1944884661
Short name T102
Test name
Test status
Simulation time 4807766639 ps
CPU time 16.86 seconds
Started Aug 18 05:21:41 PM PDT 24
Finished Aug 18 05:21:58 PM PDT 24
Peak memory 183528 kb
Host smart-61ed1617-28b5-4b1d-9984-bf866164300b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944884661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1944884661
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2202405601
Short name T40
Test name
Test status
Simulation time 549770802801 ps
CPU time 239.83 seconds
Started Aug 18 05:21:43 PM PDT 24
Finished Aug 18 05:25:43 PM PDT 24
Peak memory 191640 kb
Host smart-5efa915e-d6fd-4fbf-800e-5d7c78dabb09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202405601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2202405601
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.782265764
Short name T341
Test name
Test status
Simulation time 194098028456 ps
CPU time 265.3 seconds
Started Aug 18 05:21:41 PM PDT 24
Finished Aug 18 05:26:06 PM PDT 24
Peak memory 192868 kb
Host smart-d763a5c2-fa65-43e2-b243-606a8f85e647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782265764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.782265764
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1846952168
Short name T185
Test name
Test status
Simulation time 175834206261 ps
CPU time 177.49 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:23:20 PM PDT 24
Peak memory 183448 kb
Host smart-8bddd0eb-cfc7-47e5-84dc-7905b24e5e8d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846952168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1846952168
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/183.rv_timer_random.43361531
Short name T309
Test name
Test status
Simulation time 63130489385 ps
CPU time 128.91 seconds
Started Aug 18 05:21:49 PM PDT 24
Finished Aug 18 05:23:59 PM PDT 24
Peak memory 191796 kb
Host smart-8b34d632-34f7-4a9b-bca5-bb2b50436f5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43361531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.43361531
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2141182636
Short name T204
Test name
Test status
Simulation time 84222083532 ps
CPU time 589.34 seconds
Started Aug 18 05:21:50 PM PDT 24
Finished Aug 18 05:31:40 PM PDT 24
Peak memory 195516 kb
Host smart-f341379e-b894-4cf3-ba8c-d33c822243a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141182636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2141182636
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1542201975
Short name T187
Test name
Test status
Simulation time 795368379387 ps
CPU time 472.19 seconds
Started Aug 18 05:21:56 PM PDT 24
Finished Aug 18 05:29:48 PM PDT 24
Peak memory 191784 kb
Host smart-c26201df-c446-4f7a-aac7-1a9d3fb11d49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542201975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1542201975
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1873120254
Short name T294
Test name
Test status
Simulation time 837266562781 ps
CPU time 709.69 seconds
Started Aug 18 05:20:39 PM PDT 24
Finished Aug 18 05:32:29 PM PDT 24
Peak memory 183548 kb
Host smart-f5d1b074-34bc-48b9-815a-3abc8859cb63
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873120254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1873120254
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_random.3753228570
Short name T262
Test name
Test status
Simulation time 885314752374 ps
CPU time 356.72 seconds
Started Aug 18 05:20:38 PM PDT 24
Finished Aug 18 05:26:34 PM PDT 24
Peak memory 191720 kb
Host smart-a711e24d-1743-4630-87d6-b346bd5a730c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753228570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3753228570
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1373471155
Short name T87
Test name
Test status
Simulation time 384305977766 ps
CPU time 223.23 seconds
Started Aug 18 05:20:45 PM PDT 24
Finished Aug 18 05:24:29 PM PDT 24
Peak memory 183468 kb
Host smart-7ffd1a5d-a851-4e01-8edd-eca3b0d45da5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373471155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1373471155
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.2216149977
Short name T305
Test name
Test status
Simulation time 146607837049 ps
CPU time 451.82 seconds
Started Aug 18 05:20:45 PM PDT 24
Finished Aug 18 05:28:16 PM PDT 24
Peak memory 191724 kb
Host smart-0c708947-d27f-4a33-abbd-70e38c798800
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216149977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2216149977
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2363211880
Short name T351
Test name
Test status
Simulation time 406926024367 ps
CPU time 368.54 seconds
Started Aug 18 05:20:55 PM PDT 24
Finished Aug 18 05:27:03 PM PDT 24
Peak memory 183540 kb
Host smart-918ff117-7116-4508-b04e-ac835b73761e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363211880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2363211880
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1594192475
Short name T241
Test name
Test status
Simulation time 1184199163157 ps
CPU time 592.97 seconds
Started Aug 18 05:20:52 PM PDT 24
Finished Aug 18 05:30:46 PM PDT 24
Peak memory 196528 kb
Host smart-781b4496-88d1-4b45-b055-76487c5f3a9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594192475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1594192475
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.4157868621
Short name T215
Test name
Test status
Simulation time 271540052770 ps
CPU time 140.19 seconds
Started Aug 18 05:20:54 PM PDT 24
Finished Aug 18 05:23:15 PM PDT 24
Peak memory 183588 kb
Host smart-e06b13b6-d79c-4cca-85d2-0c327c4633f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157868621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.4157868621
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random.412528428
Short name T100
Test name
Test status
Simulation time 314102675188 ps
CPU time 201.23 seconds
Started Aug 18 05:20:52 PM PDT 24
Finished Aug 18 05:24:13 PM PDT 24
Peak memory 191672 kb
Host smart-b57a6f32-c689-4e11-a931-a72c340df475
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412528428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.412528428
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3189004586
Short name T266
Test name
Test status
Simulation time 48188727565 ps
CPU time 93.08 seconds
Started Aug 18 05:20:55 PM PDT 24
Finished Aug 18 05:22:28 PM PDT 24
Peak memory 191776 kb
Host smart-af0c89c4-1206-4e3f-b65a-aaa282395947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189004586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3189004586
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1521509967
Short name T338
Test name
Test status
Simulation time 26000040193 ps
CPU time 39.05 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:20:53 PM PDT 24
Peak memory 183540 kb
Host smart-c4c0e43e-12a6-4c02-9a48-3a1f1c737acd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521509967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1521509967
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_random.1607241517
Short name T42
Test name
Test status
Simulation time 66721984559 ps
CPU time 58.84 seconds
Started Aug 18 05:20:54 PM PDT 24
Finished Aug 18 05:21:53 PM PDT 24
Peak memory 183484 kb
Host smart-07935817-1b29-4a03-86df-dec5f350bf0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607241517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1607241517
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2374167074
Short name T283
Test name
Test status
Simulation time 768833879531 ps
CPU time 355.5 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:26:48 PM PDT 24
Peak memory 191764 kb
Host smart-21016e22-beb6-4198-b0de-c71d405ab4be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374167074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2374167074
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/54.rv_timer_random.2049738666
Short name T196
Test name
Test status
Simulation time 127613219869 ps
CPU time 202.74 seconds
Started Aug 18 05:21:03 PM PDT 24
Finished Aug 18 05:24:26 PM PDT 24
Peak memory 191680 kb
Host smart-6b3863b7-6d52-4d5d-aeba-8891d03af0da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049738666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2049738666
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2934782809
Short name T208
Test name
Test status
Simulation time 154611152035 ps
CPU time 67.37 seconds
Started Aug 18 05:21:03 PM PDT 24
Finished Aug 18 05:22:11 PM PDT 24
Peak memory 191680 kb
Host smart-699b8ec3-ba7b-4843-a7be-1ba47ad39c28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934782809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2934782809
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.696554796
Short name T186
Test name
Test status
Simulation time 132118289859 ps
CPU time 102.26 seconds
Started Aug 18 05:21:03 PM PDT 24
Finished Aug 18 05:22:45 PM PDT 24
Peak memory 191756 kb
Host smart-78e98c63-311d-4fbd-aac5-a9d7ca459653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696554796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.696554796
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3282308710
Short name T300
Test name
Test status
Simulation time 483036293723 ps
CPU time 2791.51 seconds
Started Aug 18 05:21:11 PM PDT 24
Finished Aug 18 06:07:43 PM PDT 24
Peak memory 191740 kb
Host smart-840554ae-57f0-4bb8-a865-ca5a36196665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282308710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3282308710
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.3158007529
Short name T288
Test name
Test status
Simulation time 113645637128 ps
CPU time 229.1 seconds
Started Aug 18 05:20:13 PM PDT 24
Finished Aug 18 05:24:03 PM PDT 24
Peak memory 191692 kb
Host smart-b48c553c-4176-4dcf-ac92-4ca7698d2289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158007529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3158007529
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.495622472
Short name T499
Test name
Test status
Simulation time 40420132 ps
CPU time 1.38 seconds
Started Aug 18 04:39:50 PM PDT 24
Finished Aug 18 04:39:52 PM PDT 24
Peak memory 191740 kb
Host smart-729dc38c-87dc-432c-9d73-b32d48eff23c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495622472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.495622472
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3647392563
Short name T72
Test name
Test status
Simulation time 62879034 ps
CPU time 0.6 seconds
Started Aug 18 04:39:48 PM PDT 24
Finished Aug 18 04:39:49 PM PDT 24
Peak memory 192612 kb
Host smart-16fd1479-8158-4fd7-b3ff-946bec89e026
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647392563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3647392563
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1586366521
Short name T579
Test name
Test status
Simulation time 67042485 ps
CPU time 1.57 seconds
Started Aug 18 04:39:50 PM PDT 24
Finished Aug 18 04:39:51 PM PDT 24
Peak memory 198116 kb
Host smart-6eb9a5d1-b694-4efa-a483-e6670c89ebbd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586366521 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1586366521
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1318828887
Short name T60
Test name
Test status
Simulation time 29091665 ps
CPU time 0.58 seconds
Started Aug 18 04:39:51 PM PDT 24
Finished Aug 18 04:39:51 PM PDT 24
Peak memory 183224 kb
Host smart-d607528c-a8e6-41df-a14c-87f82485a6e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318828887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1318828887
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2567350676
Short name T562
Test name
Test status
Simulation time 35756487 ps
CPU time 0.57 seconds
Started Aug 18 04:39:53 PM PDT 24
Finished Aug 18 04:39:54 PM PDT 24
Peak memory 183176 kb
Host smart-4fa94b86-0dfd-43c6-96e3-bca40c6629da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567350676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2567350676
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.567747094
Short name T505
Test name
Test status
Simulation time 90890442 ps
CPU time 1.79 seconds
Started Aug 18 04:39:49 PM PDT 24
Finished Aug 18 04:39:52 PM PDT 24
Peak memory 197664 kb
Host smart-cf0136e4-85b9-4d6b-9e47-ad21101fca1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567747094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.567747094
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1921061185
Short name T574
Test name
Test status
Simulation time 277914153 ps
CPU time 1.11 seconds
Started Aug 18 04:39:50 PM PDT 24
Finished Aug 18 04:39:51 PM PDT 24
Peak memory 195628 kb
Host smart-e2d8fee0-ee48-41e4-ad4a-5de17ce3290f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921061185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1921061185
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.225828291
Short name T69
Test name
Test status
Simulation time 25477225 ps
CPU time 0.68 seconds
Started Aug 18 04:39:55 PM PDT 24
Finished Aug 18 04:39:56 PM PDT 24
Peak memory 183224 kb
Host smart-d1ca1272-5edc-4df3-bc42-f826fd6e0099
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225828291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.225828291
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.326684077
Short name T543
Test name
Test status
Simulation time 173976762 ps
CPU time 3.12 seconds
Started Aug 18 04:39:57 PM PDT 24
Finished Aug 18 04:40:00 PM PDT 24
Peak memory 191688 kb
Host smart-ca6afa8f-a044-46f0-a462-5ecec855c49b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326684077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.326684077
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2207387786
Short name T516
Test name
Test status
Simulation time 57776234 ps
CPU time 0.65 seconds
Started Aug 18 04:39:59 PM PDT 24
Finished Aug 18 04:40:00 PM PDT 24
Peak memory 183336 kb
Host smart-e15c58f2-de51-4374-ba75-fdf196cb59ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207387786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2207387786
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.178084627
Short name T461
Test name
Test status
Simulation time 145969303 ps
CPU time 1.78 seconds
Started Aug 18 04:39:56 PM PDT 24
Finished Aug 18 04:39:58 PM PDT 24
Peak memory 198052 kb
Host smart-04d7b87c-c59a-4573-92f7-af5265b32783
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178084627 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.178084627
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.290800746
Short name T486
Test name
Test status
Simulation time 23261624 ps
CPU time 0.58 seconds
Started Aug 18 04:39:56 PM PDT 24
Finished Aug 18 04:39:57 PM PDT 24
Peak memory 192520 kb
Host smart-79601383-5c59-44f4-99c1-498c53966143
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290800746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.290800746
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.535987403
Short name T458
Test name
Test status
Simulation time 12254150 ps
CPU time 0.58 seconds
Started Aug 18 04:39:57 PM PDT 24
Finished Aug 18 04:39:58 PM PDT 24
Peak memory 183240 kb
Host smart-02cb1c24-b79f-4681-abee-45e6ad2e5237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535987403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.535987403
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3681628231
Short name T532
Test name
Test status
Simulation time 33412378 ps
CPU time 0.7 seconds
Started Aug 18 04:39:56 PM PDT 24
Finished Aug 18 04:39:57 PM PDT 24
Peak memory 192136 kb
Host smart-586e04ed-00d3-418d-8210-d85a0f6c00f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681628231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3681628231
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2685571309
Short name T473
Test name
Test status
Simulation time 27233355 ps
CPU time 1.37 seconds
Started Aug 18 04:39:54 PM PDT 24
Finished Aug 18 04:39:55 PM PDT 24
Peak memory 197840 kb
Host smart-3fb8c8a2-624f-4c6e-b59c-7765a9c5fb41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685571309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2685571309
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1605098647
Short name T567
Test name
Test status
Simulation time 927990351 ps
CPU time 1.39 seconds
Started Aug 18 04:39:58 PM PDT 24
Finished Aug 18 04:40:00 PM PDT 24
Peak memory 183808 kb
Host smart-c6a325d5-ac49-415e-94f2-ae241a1e1de5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605098647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1605098647
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3699428201
Short name T557
Test name
Test status
Simulation time 226331097 ps
CPU time 0.78 seconds
Started Aug 18 04:40:20 PM PDT 24
Finished Aug 18 04:40:21 PM PDT 24
Peak memory 195544 kb
Host smart-bd243dd1-29ba-4816-9278-d4f44db1587e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699428201 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3699428201
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.714858889
Short name T63
Test name
Test status
Simulation time 47921899 ps
CPU time 0.59 seconds
Started Aug 18 04:40:18 PM PDT 24
Finished Aug 18 04:40:19 PM PDT 24
Peak memory 183308 kb
Host smart-f9e5df23-1d05-49eb-acbd-6b84d15313ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714858889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.714858889
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3835579205
Short name T565
Test name
Test status
Simulation time 17537205 ps
CPU time 0.54 seconds
Started Aug 18 04:40:17 PM PDT 24
Finished Aug 18 04:40:17 PM PDT 24
Peak memory 182924 kb
Host smart-5145ae39-04df-4322-91bc-1203a03b3c9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835579205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3835579205
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1532220846
Short name T569
Test name
Test status
Simulation time 29062159 ps
CPU time 0.66 seconds
Started Aug 18 04:40:16 PM PDT 24
Finished Aug 18 04:40:17 PM PDT 24
Peak memory 192644 kb
Host smart-664ed8d9-7191-4190-9b46-e7d704c4df7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532220846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1532220846
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.775094292
Short name T508
Test name
Test status
Simulation time 170755840 ps
CPU time 1.97 seconds
Started Aug 18 04:40:05 PM PDT 24
Finished Aug 18 04:40:07 PM PDT 24
Peak memory 198084 kb
Host smart-3dca96ad-40dc-4fa2-8bf0-24105af8458f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775094292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.775094292
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1857704454
Short name T556
Test name
Test status
Simulation time 245099751 ps
CPU time 1.06 seconds
Started Aug 18 04:40:15 PM PDT 24
Finished Aug 18 04:40:17 PM PDT 24
Peak memory 195444 kb
Host smart-8799755d-9df6-4dba-b412-04c73ef2f393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857704454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1857704454
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4212694789
Short name T542
Test name
Test status
Simulation time 31287669 ps
CPU time 1.34 seconds
Started Aug 18 04:40:15 PM PDT 24
Finished Aug 18 04:40:17 PM PDT 24
Peak memory 198068 kb
Host smart-992f2e86-abc8-45e8-9c4a-b60a2c845662
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212694789 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.4212694789
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3964280291
Short name T501
Test name
Test status
Simulation time 18330355 ps
CPU time 0.6 seconds
Started Aug 18 04:40:17 PM PDT 24
Finished Aug 18 04:40:18 PM PDT 24
Peak memory 183344 kb
Host smart-7c4e4a22-3cfd-423c-a235-ff8a20b7514a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964280291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3964280291
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.683770369
Short name T509
Test name
Test status
Simulation time 29533077 ps
CPU time 0.58 seconds
Started Aug 18 04:40:18 PM PDT 24
Finished Aug 18 04:40:19 PM PDT 24
Peak memory 183212 kb
Host smart-aced7b93-93b6-4066-b295-77afba4d671a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683770369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.683770369
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3286331243
Short name T64
Test name
Test status
Simulation time 85206841 ps
CPU time 0.65 seconds
Started Aug 18 04:40:19 PM PDT 24
Finished Aug 18 04:40:20 PM PDT 24
Peak memory 192164 kb
Host smart-473e688b-dc9a-4680-baeb-f64d9252db4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286331243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3286331243
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3864086562
Short name T481
Test name
Test status
Simulation time 116283606 ps
CPU time 1.21 seconds
Started Aug 18 04:40:16 PM PDT 24
Finished Aug 18 04:40:17 PM PDT 24
Peak memory 197332 kb
Host smart-3acd40d3-e651-4ebb-b543-6cfc453565bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864086562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3864086562
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.673846154
Short name T81
Test name
Test status
Simulation time 71560796 ps
CPU time 0.78 seconds
Started Aug 18 04:40:16 PM PDT 24
Finished Aug 18 04:40:17 PM PDT 24
Peak memory 194068 kb
Host smart-ebbaec7f-dc0f-45ef-bc8b-8d0e473ea5fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673846154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.673846154
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3779959202
Short name T488
Test name
Test status
Simulation time 62771876 ps
CPU time 0.92 seconds
Started Aug 18 04:40:15 PM PDT 24
Finished Aug 18 04:40:16 PM PDT 24
Peak memory 197668 kb
Host smart-34aec398-a38a-4ecd-a1b7-c2192d97a329
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779959202 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3779959202
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.4242636379
Short name T558
Test name
Test status
Simulation time 41727846 ps
CPU time 0.56 seconds
Started Aug 18 04:40:15 PM PDT 24
Finished Aug 18 04:40:15 PM PDT 24
Peak memory 183248 kb
Host smart-fa7e052c-334f-44ad-a964-5315690035ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242636379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.4242636379
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3454377613
Short name T530
Test name
Test status
Simulation time 33426299 ps
CPU time 0.58 seconds
Started Aug 18 04:40:16 PM PDT 24
Finished Aug 18 04:40:17 PM PDT 24
Peak memory 183252 kb
Host smart-fef08d81-49fb-4355-86ff-1da61b87512f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454377613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3454377613
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3572990000
Short name T531
Test name
Test status
Simulation time 15088680 ps
CPU time 0.64 seconds
Started Aug 18 04:40:16 PM PDT 24
Finished Aug 18 04:40:17 PM PDT 24
Peak memory 192748 kb
Host smart-37e9bcca-ced4-4a57-a8b6-b0a4ef4b4c60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572990000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3572990000
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3901082742
Short name T464
Test name
Test status
Simulation time 178602689 ps
CPU time 2.18 seconds
Started Aug 18 04:40:16 PM PDT 24
Finished Aug 18 04:40:18 PM PDT 24
Peak memory 197984 kb
Host smart-403d3edf-f2df-4003-860c-c3d39636a70d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901082742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3901082742
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2785893085
Short name T547
Test name
Test status
Simulation time 249603495 ps
CPU time 1.35 seconds
Started Aug 18 04:40:16 PM PDT 24
Finished Aug 18 04:40:18 PM PDT 24
Peak memory 183900 kb
Host smart-686fb4cf-9d75-4bc9-9835-ea7ea2537cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785893085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2785893085
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2039511659
Short name T563
Test name
Test status
Simulation time 13771773 ps
CPU time 0.69 seconds
Started Aug 18 04:40:18 PM PDT 24
Finished Aug 18 04:40:19 PM PDT 24
Peak memory 194724 kb
Host smart-e4635baf-571d-40fd-a48f-d65024b651ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039511659 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2039511659
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.75554988
Short name T45
Test name
Test status
Simulation time 15228546 ps
CPU time 0.55 seconds
Started Aug 18 04:40:14 PM PDT 24
Finished Aug 18 04:40:15 PM PDT 24
Peak memory 183288 kb
Host smart-5a147d6b-2e74-432f-bd9d-0eed872587a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75554988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.75554988
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2929688076
Short name T527
Test name
Test status
Simulation time 48498003 ps
CPU time 0.54 seconds
Started Aug 18 04:40:17 PM PDT 24
Finished Aug 18 04:40:18 PM PDT 24
Peak memory 182852 kb
Host smart-a2e537d0-2fa1-4794-b3b4-3bf569a39318
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929688076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2929688076
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4048631146
Short name T59
Test name
Test status
Simulation time 15042380 ps
CPU time 0.67 seconds
Started Aug 18 04:40:19 PM PDT 24
Finished Aug 18 04:40:20 PM PDT 24
Peak memory 192604 kb
Host smart-bd696779-7180-4925-8692-876235f3722b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048631146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.4048631146
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1875807015
Short name T496
Test name
Test status
Simulation time 520014009 ps
CPU time 2.12 seconds
Started Aug 18 04:40:16 PM PDT 24
Finished Aug 18 04:40:19 PM PDT 24
Peak memory 198020 kb
Host smart-711a6d69-08a0-4b7c-8c32-789457604992
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875807015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1875807015
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3880818502
Short name T479
Test name
Test status
Simulation time 126219441 ps
CPU time 0.89 seconds
Started Aug 18 04:40:18 PM PDT 24
Finished Aug 18 04:40:19 PM PDT 24
Peak memory 197192 kb
Host smart-96932928-f2aa-4022-8efe-7a7b01efd0a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880818502 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3880818502
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1498308879
Short name T489
Test name
Test status
Simulation time 12362054 ps
CPU time 0.55 seconds
Started Aug 18 04:40:17 PM PDT 24
Finished Aug 18 04:40:17 PM PDT 24
Peak memory 182732 kb
Host smart-4aa6304c-faee-4ff4-845b-92109f30e4fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498308879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1498308879
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.244652317
Short name T550
Test name
Test status
Simulation time 27094395 ps
CPU time 0.7 seconds
Started Aug 18 04:40:15 PM PDT 24
Finished Aug 18 04:40:16 PM PDT 24
Peak memory 192856 kb
Host smart-de9f2064-69a8-4b1d-ad55-9d96c0a7067f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244652317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.244652317
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2971385535
Short name T581
Test name
Test status
Simulation time 594973772 ps
CPU time 3.01 seconds
Started Aug 18 04:40:15 PM PDT 24
Finished Aug 18 04:40:18 PM PDT 24
Peak memory 198064 kb
Host smart-b84854ae-dfa3-40ae-8474-8e9a94cf7043
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971385535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2971385535
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.658846888
Short name T561
Test name
Test status
Simulation time 82108065 ps
CPU time 0.81 seconds
Started Aug 18 04:40:16 PM PDT 24
Finished Aug 18 04:40:17 PM PDT 24
Peak memory 183564 kb
Host smart-ed0eeeb7-53d4-4052-a0c0-2acbd88e8c6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658846888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.658846888
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.217499668
Short name T483
Test name
Test status
Simulation time 33954563 ps
CPU time 1.53 seconds
Started Aug 18 04:40:22 PM PDT 24
Finished Aug 18 04:40:24 PM PDT 24
Peak memory 198136 kb
Host smart-139a127a-ca4d-47d9-a740-eb948b39ac05
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217499668 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.217499668
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3576746532
Short name T70
Test name
Test status
Simulation time 55254192 ps
CPU time 0.58 seconds
Started Aug 18 04:40:22 PM PDT 24
Finished Aug 18 04:40:23 PM PDT 24
Peak memory 183312 kb
Host smart-0cd7bb9f-1219-4884-b375-99f7284a36d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576746532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3576746532
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3548035133
Short name T484
Test name
Test status
Simulation time 15929797 ps
CPU time 0.53 seconds
Started Aug 18 04:40:16 PM PDT 24
Finished Aug 18 04:40:17 PM PDT 24
Peak memory 183196 kb
Host smart-ab39a7ce-d90f-418b-ac13-ad6d5dc794d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548035133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3548035133
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.549791883
Short name T566
Test name
Test status
Simulation time 71075116 ps
CPU time 0.81 seconds
Started Aug 18 04:40:24 PM PDT 24
Finished Aug 18 04:40:25 PM PDT 24
Peak memory 193728 kb
Host smart-3ec09ab1-685f-47e1-9992-fbd3de3c24fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549791883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.549791883
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2248997767
Short name T555
Test name
Test status
Simulation time 112041204 ps
CPU time 2.06 seconds
Started Aug 18 04:40:16 PM PDT 24
Finished Aug 18 04:40:18 PM PDT 24
Peak memory 198064 kb
Host smart-b78f08b5-623f-490f-acb2-5e49d7300e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248997767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2248997767
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4228057207
Short name T85
Test name
Test status
Simulation time 42908405 ps
CPU time 0.86 seconds
Started Aug 18 04:40:17 PM PDT 24
Finished Aug 18 04:40:18 PM PDT 24
Peak memory 194084 kb
Host smart-610c6055-8b2e-4607-9bc2-fb5e70444c59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228057207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.4228057207
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.959412787
Short name T571
Test name
Test status
Simulation time 126288666 ps
CPU time 1.63 seconds
Started Aug 18 04:40:25 PM PDT 24
Finished Aug 18 04:40:27 PM PDT 24
Peak memory 198072 kb
Host smart-cbb4254c-bd7f-42a7-8511-cfb32dbfc159
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959412787 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.959412787
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.286727100
Short name T75
Test name
Test status
Simulation time 33416805 ps
CPU time 0.54 seconds
Started Aug 18 04:40:23 PM PDT 24
Finished Aug 18 04:40:24 PM PDT 24
Peak memory 183388 kb
Host smart-79593f54-403f-41b3-b19e-a72e34d2cb66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286727100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.286727100
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2749396407
Short name T457
Test name
Test status
Simulation time 20535205 ps
CPU time 0.6 seconds
Started Aug 18 04:40:23 PM PDT 24
Finished Aug 18 04:40:24 PM PDT 24
Peak memory 183144 kb
Host smart-e9589104-6409-4ef6-b218-9dff41cc5da9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749396407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2749396407
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1149159866
Short name T76
Test name
Test status
Simulation time 55731162 ps
CPU time 0.68 seconds
Started Aug 18 04:40:25 PM PDT 24
Finished Aug 18 04:40:26 PM PDT 24
Peak memory 192160 kb
Host smart-1a1160ec-f392-4915-9d47-546c22f3c64f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149159866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1149159866
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.277110235
Short name T478
Test name
Test status
Simulation time 134322271 ps
CPU time 1.44 seconds
Started Aug 18 04:40:24 PM PDT 24
Finished Aug 18 04:40:26 PM PDT 24
Peak memory 198048 kb
Host smart-d1d71224-c871-4dea-a8d2-125f0ea3111b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277110235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.277110235
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2113776613
Short name T533
Test name
Test status
Simulation time 142071185 ps
CPU time 0.81 seconds
Started Aug 18 04:40:23 PM PDT 24
Finished Aug 18 04:40:24 PM PDT 24
Peak memory 194332 kb
Host smart-d663676b-3b54-4ce0-a8f3-2aa1c78594c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113776613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2113776613
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1615398324
Short name T475
Test name
Test status
Simulation time 36274072 ps
CPU time 0.91 seconds
Started Aug 18 04:40:24 PM PDT 24
Finished Aug 18 04:40:25 PM PDT 24
Peak memory 197560 kb
Host smart-4079ac96-60c4-4a89-8542-f58fdffcf8a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615398324 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1615398324
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.192105260
Short name T513
Test name
Test status
Simulation time 40711488 ps
CPU time 0.61 seconds
Started Aug 18 04:40:25 PM PDT 24
Finished Aug 18 04:40:25 PM PDT 24
Peak memory 183292 kb
Host smart-13a8d980-7c24-416c-93de-9b5b91ece8d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192105260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.192105260
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.233280656
Short name T522
Test name
Test status
Simulation time 18146591 ps
CPU time 0.59 seconds
Started Aug 18 04:40:25 PM PDT 24
Finished Aug 18 04:40:26 PM PDT 24
Peak memory 183096 kb
Host smart-45488ac2-62ab-4919-b590-f2cae7c2831b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233280656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.233280656
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2947704658
Short name T73
Test name
Test status
Simulation time 28259239 ps
CPU time 0.69 seconds
Started Aug 18 04:40:26 PM PDT 24
Finished Aug 18 04:40:26 PM PDT 24
Peak memory 192344 kb
Host smart-9836caca-9cc0-446d-8a27-7ebdeda4f70d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947704658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2947704658
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.679970245
Short name T493
Test name
Test status
Simulation time 234938236 ps
CPU time 1.85 seconds
Started Aug 18 04:40:27 PM PDT 24
Finished Aug 18 04:40:29 PM PDT 24
Peak memory 198072 kb
Host smart-6c01577a-71f7-402e-b255-86cc3e7f4248
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679970245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.679970245
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1773258059
Short name T83
Test name
Test status
Simulation time 104637685 ps
CPU time 1.32 seconds
Started Aug 18 04:40:22 PM PDT 24
Finished Aug 18 04:40:24 PM PDT 24
Peak memory 183664 kb
Host smart-dde0cb12-29f5-4821-9a65-04d2ebfaaa38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773258059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1773258059
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3217095351
Short name T500
Test name
Test status
Simulation time 150447604 ps
CPU time 0.81 seconds
Started Aug 18 04:40:25 PM PDT 24
Finished Aug 18 04:40:26 PM PDT 24
Peak memory 196040 kb
Host smart-95ea0d05-1817-4ba7-a8d3-9012092dff93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217095351 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3217095351
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3642171104
Short name T80
Test name
Test status
Simulation time 127919172 ps
CPU time 0.59 seconds
Started Aug 18 04:40:23 PM PDT 24
Finished Aug 18 04:40:23 PM PDT 24
Peak memory 183292 kb
Host smart-37d7ced0-2a70-4ec8-93f1-8060b40281d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642171104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3642171104
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3693936403
Short name T515
Test name
Test status
Simulation time 13908465 ps
CPU time 0.54 seconds
Started Aug 18 04:40:27 PM PDT 24
Finished Aug 18 04:40:27 PM PDT 24
Peak memory 182588 kb
Host smart-7638190f-9e43-442b-89a7-9d95efb185fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693936403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3693936403
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2331932868
Short name T503
Test name
Test status
Simulation time 47263431 ps
CPU time 0.73 seconds
Started Aug 18 04:40:28 PM PDT 24
Finished Aug 18 04:40:29 PM PDT 24
Peak memory 193840 kb
Host smart-eff9f670-61e7-422d-86f7-4eaacbacb0ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331932868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2331932868
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1782726012
Short name T460
Test name
Test status
Simulation time 289281964 ps
CPU time 1.13 seconds
Started Aug 18 04:40:24 PM PDT 24
Finished Aug 18 04:40:26 PM PDT 24
Peak memory 197932 kb
Host smart-952cfc05-9866-48cc-adf1-96aae726dae0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782726012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1782726012
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3170463749
Short name T517
Test name
Test status
Simulation time 263432877 ps
CPU time 1.02 seconds
Started Aug 18 04:40:22 PM PDT 24
Finished Aug 18 04:40:23 PM PDT 24
Peak memory 195696 kb
Host smart-229da5e4-8481-41e5-9c7e-e1a2489d85a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170463749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3170463749
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2553697043
Short name T540
Test name
Test status
Simulation time 23932384 ps
CPU time 1.1 seconds
Started Aug 18 04:40:23 PM PDT 24
Finished Aug 18 04:40:24 PM PDT 24
Peak memory 197936 kb
Host smart-6004a6d3-ad4a-48f3-8d14-d5adddefcee3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553697043 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2553697043
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.82681417
Short name T575
Test name
Test status
Simulation time 20247013 ps
CPU time 0.58 seconds
Started Aug 18 04:40:22 PM PDT 24
Finished Aug 18 04:40:23 PM PDT 24
Peak memory 182956 kb
Host smart-07dbd62e-9bc9-45bd-939d-a1bc8b41570d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82681417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.82681417
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1089310208
Short name T518
Test name
Test status
Simulation time 13106488 ps
CPU time 0.6 seconds
Started Aug 18 04:40:28 PM PDT 24
Finished Aug 18 04:40:29 PM PDT 24
Peak memory 183120 kb
Host smart-b5d98e60-9b3c-42f9-9041-326369942d70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089310208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1089310208
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3754612377
Short name T552
Test name
Test status
Simulation time 198900626 ps
CPU time 0.71 seconds
Started Aug 18 04:40:28 PM PDT 24
Finished Aug 18 04:40:28 PM PDT 24
Peak memory 193564 kb
Host smart-ba64bf1f-8583-4ed7-ab15-00401a718e38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754612377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3754612377
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2813034075
Short name T498
Test name
Test status
Simulation time 187734653 ps
CPU time 1.11 seconds
Started Aug 18 04:40:28 PM PDT 24
Finished Aug 18 04:40:29 PM PDT 24
Peak memory 196700 kb
Host smart-582b4321-6c62-4765-9766-76c8531edcfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813034075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2813034075
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.936977037
Short name T548
Test name
Test status
Simulation time 93487548 ps
CPU time 0.73 seconds
Started Aug 18 04:39:57 PM PDT 24
Finished Aug 18 04:39:58 PM PDT 24
Peak memory 183468 kb
Host smart-58de9b33-b4d9-43b0-bc8d-2c897f00c680
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936977037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.936977037
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2639072426
Short name T549
Test name
Test status
Simulation time 294442940 ps
CPU time 3.57 seconds
Started Aug 18 04:40:04 PM PDT 24
Finished Aug 18 04:40:07 PM PDT 24
Peak memory 193368 kb
Host smart-a13926de-58cc-4fc6-8658-1bb538223a41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639072426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2639072426
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2397835037
Short name T66
Test name
Test status
Simulation time 15598880 ps
CPU time 0.57 seconds
Started Aug 18 04:39:58 PM PDT 24
Finished Aug 18 04:39:59 PM PDT 24
Peak memory 183292 kb
Host smart-e18381eb-81c1-483c-8cdb-f6cfc046741e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397835037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2397835037
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2223885938
Short name T536
Test name
Test status
Simulation time 25468823 ps
CPU time 0.8 seconds
Started Aug 18 04:39:56 PM PDT 24
Finished Aug 18 04:39:57 PM PDT 24
Peak memory 195904 kb
Host smart-69c35fd1-e94c-482c-bda6-2d1cadfc9794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223885938 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2223885938
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3803262800
Short name T538
Test name
Test status
Simulation time 16767031 ps
CPU time 0.55 seconds
Started Aug 18 04:39:59 PM PDT 24
Finished Aug 18 04:40:00 PM PDT 24
Peak memory 183284 kb
Host smart-c5c250d3-289f-4da4-ace9-2aa063fe4c90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803262800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3803262800
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.4135686397
Short name T463
Test name
Test status
Simulation time 13264098 ps
CPU time 0.57 seconds
Started Aug 18 04:40:00 PM PDT 24
Finished Aug 18 04:40:01 PM PDT 24
Peak memory 183208 kb
Host smart-1de34d06-163e-4244-9020-d8dcbf6e9ad4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135686397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.4135686397
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.642223642
Short name T78
Test name
Test status
Simulation time 85757442 ps
CPU time 0.78 seconds
Started Aug 18 04:39:58 PM PDT 24
Finished Aug 18 04:39:59 PM PDT 24
Peak memory 192332 kb
Host smart-1eade899-7a39-4c83-bfb7-587c25764a18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642223642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.642223642
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1568927452
Short name T570
Test name
Test status
Simulation time 27453052 ps
CPU time 1.32 seconds
Started Aug 18 04:39:59 PM PDT 24
Finished Aug 18 04:40:01 PM PDT 24
Peak memory 198128 kb
Host smart-7a8b7545-6f92-494a-a716-514067db1abe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568927452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1568927452
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1199990139
Short name T24
Test name
Test status
Simulation time 348198208 ps
CPU time 0.89 seconds
Started Aug 18 04:39:59 PM PDT 24
Finished Aug 18 04:40:00 PM PDT 24
Peak memory 194180 kb
Host smart-67ca3f81-2add-4389-8de8-886d68d22848
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199990139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1199990139
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1676449320
Short name T523
Test name
Test status
Simulation time 35060190 ps
CPU time 0.58 seconds
Started Aug 18 04:40:25 PM PDT 24
Finished Aug 18 04:40:26 PM PDT 24
Peak memory 183180 kb
Host smart-21e1a34e-06c6-453b-9b40-75c094ef2116
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676449320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1676449320
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3337007744
Short name T474
Test name
Test status
Simulation time 51074501 ps
CPU time 0.58 seconds
Started Aug 18 04:40:28 PM PDT 24
Finished Aug 18 04:40:29 PM PDT 24
Peak memory 183224 kb
Host smart-a36bfce5-a922-4525-9369-3c5b8abe763f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337007744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3337007744
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3376059661
Short name T502
Test name
Test status
Simulation time 58353574 ps
CPU time 0.56 seconds
Started Aug 18 04:40:24 PM PDT 24
Finished Aug 18 04:40:25 PM PDT 24
Peak memory 183208 kb
Host smart-862e2152-2820-42b2-bc89-6c56cf8a2663
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376059661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3376059661
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.953541280
Short name T470
Test name
Test status
Simulation time 106433276 ps
CPU time 0.56 seconds
Started Aug 18 04:40:25 PM PDT 24
Finished Aug 18 04:40:26 PM PDT 24
Peak memory 183232 kb
Host smart-a10f6c11-32af-40d0-8fb6-2dbae691dea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953541280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.953541280
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1175495263
Short name T564
Test name
Test status
Simulation time 22981578 ps
CPU time 0.59 seconds
Started Aug 18 04:40:25 PM PDT 24
Finished Aug 18 04:40:26 PM PDT 24
Peak memory 182852 kb
Host smart-a6e76c3e-6834-484d-81d6-b349cc2fa78f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175495263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1175495263
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3325179434
Short name T529
Test name
Test status
Simulation time 50904569 ps
CPU time 0.55 seconds
Started Aug 18 04:40:22 PM PDT 24
Finished Aug 18 04:40:23 PM PDT 24
Peak memory 183260 kb
Host smart-519eb61b-20d2-41ce-ae22-901a492834c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325179434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3325179434
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.4186707764
Short name T577
Test name
Test status
Simulation time 18963812 ps
CPU time 0.6 seconds
Started Aug 18 04:40:24 PM PDT 24
Finished Aug 18 04:40:24 PM PDT 24
Peak memory 183312 kb
Host smart-b0439b12-3df7-440b-a351-1799e29025f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186707764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.4186707764
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2194974342
Short name T520
Test name
Test status
Simulation time 26243817 ps
CPU time 0.61 seconds
Started Aug 18 04:40:27 PM PDT 24
Finished Aug 18 04:40:28 PM PDT 24
Peak memory 183168 kb
Host smart-80c2b18c-d328-4b8a-b4d7-ec11e60eb88d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194974342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2194974342
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2853332394
Short name T510
Test name
Test status
Simulation time 46519680 ps
CPU time 0.58 seconds
Started Aug 18 04:40:28 PM PDT 24
Finished Aug 18 04:40:28 PM PDT 24
Peak memory 183232 kb
Host smart-12f8c42a-e5ed-4728-a163-6554c5d48520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853332394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2853332394
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2024230369
Short name T472
Test name
Test status
Simulation time 21804350 ps
CPU time 0.54 seconds
Started Aug 18 04:40:24 PM PDT 24
Finished Aug 18 04:40:24 PM PDT 24
Peak memory 182636 kb
Host smart-8006bb1b-63de-4654-8ca2-8665a9672afb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024230369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2024230369
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1562611803
Short name T79
Test name
Test status
Simulation time 33829062 ps
CPU time 0.85 seconds
Started Aug 18 04:39:57 PM PDT 24
Finished Aug 18 04:39:58 PM PDT 24
Peak memory 183392 kb
Host smart-93d58bc2-1167-4f4a-b229-00fe9ec3ff9a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562611803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1562611803
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4177177979
Short name T576
Test name
Test status
Simulation time 351270973 ps
CPU time 2.55 seconds
Started Aug 18 04:39:57 PM PDT 24
Finished Aug 18 04:39:59 PM PDT 24
Peak memory 191664 kb
Host smart-568acf86-59a7-435c-8902-5f06d5fee97d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177177979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.4177177979
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3524438874
Short name T51
Test name
Test status
Simulation time 18499844 ps
CPU time 0.6 seconds
Started Aug 18 04:40:00 PM PDT 24
Finished Aug 18 04:40:01 PM PDT 24
Peak memory 183188 kb
Host smart-5346f40e-0b43-4b9a-930b-c361c2b6ff0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524438874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3524438874
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2143156518
Short name T519
Test name
Test status
Simulation time 37440365 ps
CPU time 1.26 seconds
Started Aug 18 04:39:58 PM PDT 24
Finished Aug 18 04:39:59 PM PDT 24
Peak memory 198096 kb
Host smart-03f2dc16-12df-4fb2-8f1c-bc76c92ef748
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143156518 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2143156518
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1842587462
Short name T62
Test name
Test status
Simulation time 51228120 ps
CPU time 0.57 seconds
Started Aug 18 04:39:58 PM PDT 24
Finished Aug 18 04:39:59 PM PDT 24
Peak memory 183388 kb
Host smart-9b6b944f-2ed3-40ec-a8fe-81acbb75494c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842587462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1842587462
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.864414218
Short name T482
Test name
Test status
Simulation time 53620192 ps
CPU time 0.57 seconds
Started Aug 18 04:39:57 PM PDT 24
Finished Aug 18 04:39:58 PM PDT 24
Peak memory 183216 kb
Host smart-90bdedc0-1baf-4b26-84e7-d9659792376c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864414218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.864414218
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1575339055
Short name T528
Test name
Test status
Simulation time 46276457 ps
CPU time 0.89 seconds
Started Aug 18 04:39:56 PM PDT 24
Finished Aug 18 04:39:57 PM PDT 24
Peak memory 193860 kb
Host smart-a92e2a8a-6ca4-480b-a1b4-0bbd60063aac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575339055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1575339055
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2769779237
Short name T465
Test name
Test status
Simulation time 177551093 ps
CPU time 2.07 seconds
Started Aug 18 04:39:57 PM PDT 24
Finished Aug 18 04:40:00 PM PDT 24
Peak memory 198148 kb
Host smart-66528ca0-0dbe-4bac-a1e6-308938ef46d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769779237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2769779237
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.753246212
Short name T84
Test name
Test status
Simulation time 283153013 ps
CPU time 1.12 seconds
Started Aug 18 04:39:58 PM PDT 24
Finished Aug 18 04:39:59 PM PDT 24
Peak memory 195740 kb
Host smart-cffb09ad-22cc-4df1-bdb1-41b51b0542cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753246212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.753246212
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1630326048
Short name T471
Test name
Test status
Simulation time 33197168 ps
CPU time 0.52 seconds
Started Aug 18 04:40:25 PM PDT 24
Finished Aug 18 04:40:25 PM PDT 24
Peak memory 182652 kb
Host smart-1efa1ff5-e8ae-48d5-8dcc-7d9758aa9694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630326048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1630326048
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1373046429
Short name T497
Test name
Test status
Simulation time 18249727 ps
CPU time 0.56 seconds
Started Aug 18 04:40:24 PM PDT 24
Finished Aug 18 04:40:25 PM PDT 24
Peak memory 183212 kb
Host smart-636a4ee6-86a7-4e0c-aa7d-0c0384a9383b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373046429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1373046429
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.677433683
Short name T525
Test name
Test status
Simulation time 66560226 ps
CPU time 0.54 seconds
Started Aug 18 04:40:23 PM PDT 24
Finished Aug 18 04:40:24 PM PDT 24
Peak memory 183192 kb
Host smart-2ca8b859-106b-41e5-a309-a92b3b61b5de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677433683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.677433683
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1960190686
Short name T462
Test name
Test status
Simulation time 13816381 ps
CPU time 0.58 seconds
Started Aug 18 04:40:25 PM PDT 24
Finished Aug 18 04:40:25 PM PDT 24
Peak memory 182720 kb
Host smart-9a521c89-2792-45ec-9d63-662088efc790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960190686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1960190686
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.323316679
Short name T480
Test name
Test status
Simulation time 16248269 ps
CPU time 0.54 seconds
Started Aug 18 04:40:25 PM PDT 24
Finished Aug 18 04:40:25 PM PDT 24
Peak memory 182596 kb
Host smart-60137238-49d3-4eeb-9ece-c1ccc8e4400b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323316679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.323316679
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2650985938
Short name T582
Test name
Test status
Simulation time 14715562 ps
CPU time 0.55 seconds
Started Aug 18 04:40:28 PM PDT 24
Finished Aug 18 04:40:29 PM PDT 24
Peak memory 183188 kb
Host smart-8bd6389c-e9ea-4ff2-a643-36b06db26947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650985938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2650985938
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2892646700
Short name T568
Test name
Test status
Simulation time 14420161 ps
CPU time 0.57 seconds
Started Aug 18 04:40:23 PM PDT 24
Finished Aug 18 04:40:24 PM PDT 24
Peak memory 183100 kb
Host smart-77d65c5e-c9b7-47fb-9cde-31b34f0dd94b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892646700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2892646700
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1254051376
Short name T459
Test name
Test status
Simulation time 35593280 ps
CPU time 0.55 seconds
Started Aug 18 04:40:28 PM PDT 24
Finished Aug 18 04:40:28 PM PDT 24
Peak memory 182860 kb
Host smart-8696a24d-5669-4729-a947-70d9b6b8ab80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254051376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1254051376
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1353409598
Short name T467
Test name
Test status
Simulation time 121500310 ps
CPU time 0.55 seconds
Started Aug 18 04:40:25 PM PDT 24
Finished Aug 18 04:40:25 PM PDT 24
Peak memory 182716 kb
Host smart-0ef69fba-2913-4ddc-b382-8ef0242e0761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353409598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1353409598
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3078908162
Short name T526
Test name
Test status
Simulation time 22202610 ps
CPU time 0.54 seconds
Started Aug 18 04:40:23 PM PDT 24
Finished Aug 18 04:40:24 PM PDT 24
Peak memory 182592 kb
Host smart-caf84337-0122-44ed-9eab-09132d5fe6ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078908162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3078908162
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.943459523
Short name T578
Test name
Test status
Simulation time 23786887 ps
CPU time 0.73 seconds
Started Aug 18 04:39:58 PM PDT 24
Finished Aug 18 04:39:59 PM PDT 24
Peak memory 183256 kb
Host smart-251ed52f-6cc8-4ad1-a1e5-afd3693e90b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943459523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.943459523
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.509947070
Short name T61
Test name
Test status
Simulation time 1010060545 ps
CPU time 3.52 seconds
Started Aug 18 04:40:00 PM PDT 24
Finished Aug 18 04:40:03 PM PDT 24
Peak memory 194592 kb
Host smart-1ad69792-ac0b-46d7-9336-db19afb1dec8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509947070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.509947070
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2166937264
Short name T512
Test name
Test status
Simulation time 190302095 ps
CPU time 0.54 seconds
Started Aug 18 04:39:59 PM PDT 24
Finished Aug 18 04:39:59 PM PDT 24
Peak memory 182800 kb
Host smart-46c33b0b-17d0-49c7-93d3-5d67ea953468
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166937264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2166937264
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3875997688
Short name T573
Test name
Test status
Simulation time 305974784 ps
CPU time 0.79 seconds
Started Aug 18 04:40:02 PM PDT 24
Finished Aug 18 04:40:03 PM PDT 24
Peak memory 194956 kb
Host smart-497a1476-82b9-49b9-91f1-66cde2596c16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875997688 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3875997688
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1122316149
Short name T487
Test name
Test status
Simulation time 31965792 ps
CPU time 0.56 seconds
Started Aug 18 04:40:03 PM PDT 24
Finished Aug 18 04:40:04 PM PDT 24
Peak memory 183008 kb
Host smart-f86a9a53-1089-43fd-b13e-51dac56d558a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122316149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1122316149
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3825201351
Short name T466
Test name
Test status
Simulation time 22996114 ps
CPU time 0.59 seconds
Started Aug 18 04:39:57 PM PDT 24
Finished Aug 18 04:39:58 PM PDT 24
Peak memory 183152 kb
Host smart-c6b544e2-c49c-425c-b7ac-5fd74d3001bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825201351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3825201351
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2221525103
Short name T507
Test name
Test status
Simulation time 17824624 ps
CPU time 0.59 seconds
Started Aug 18 04:39:55 PM PDT 24
Finished Aug 18 04:39:56 PM PDT 24
Peak memory 192520 kb
Host smart-8096d417-01ec-4579-b416-ceb5ded8260d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221525103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2221525103
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2868236548
Short name T492
Test name
Test status
Simulation time 367005634 ps
CPU time 2.13 seconds
Started Aug 18 04:40:03 PM PDT 24
Finished Aug 18 04:40:05 PM PDT 24
Peak memory 197944 kb
Host smart-6440ae43-4426-46f5-842a-ccb2c3c673a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868236548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2868236548
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4293219342
Short name T25
Test name
Test status
Simulation time 134048172 ps
CPU time 1.08 seconds
Started Aug 18 04:40:00 PM PDT 24
Finished Aug 18 04:40:01 PM PDT 24
Peak memory 195600 kb
Host smart-21abdea3-08bf-4021-9aee-8c00f761a42d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293219342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.4293219342
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.547389290
Short name T572
Test name
Test status
Simulation time 40203346 ps
CPU time 0.57 seconds
Started Aug 18 04:40:25 PM PDT 24
Finished Aug 18 04:40:26 PM PDT 24
Peak memory 183160 kb
Host smart-0efcdb37-8772-46d9-ba4a-8bed5bdad5c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547389290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.547389290
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1705234584
Short name T514
Test name
Test status
Simulation time 21592172 ps
CPU time 0.55 seconds
Started Aug 18 04:40:24 PM PDT 24
Finished Aug 18 04:40:25 PM PDT 24
Peak memory 182440 kb
Host smart-d489ecbc-b37a-4690-b9fe-6d6d13bee779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705234584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1705234584
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3830952748
Short name T553
Test name
Test status
Simulation time 40356851 ps
CPU time 0.55 seconds
Started Aug 18 04:40:24 PM PDT 24
Finished Aug 18 04:40:25 PM PDT 24
Peak memory 183116 kb
Host smart-6769ffbc-e4cb-473a-909f-7ce9291e411c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830952748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3830952748
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2527379840
Short name T468
Test name
Test status
Simulation time 76474160 ps
CPU time 0.56 seconds
Started Aug 18 04:40:22 PM PDT 24
Finished Aug 18 04:40:23 PM PDT 24
Peak memory 183196 kb
Host smart-0614fe61-c628-4c3b-be23-4353f5ad444b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527379840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2527379840
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3898443052
Short name T534
Test name
Test status
Simulation time 34903844 ps
CPU time 0.56 seconds
Started Aug 18 04:40:24 PM PDT 24
Finished Aug 18 04:40:24 PM PDT 24
Peak memory 182864 kb
Host smart-32cd11f7-7e54-4bc5-b2e2-65ef30a323dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898443052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3898443052
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2923040363
Short name T544
Test name
Test status
Simulation time 14996088 ps
CPU time 0.54 seconds
Started Aug 18 04:40:24 PM PDT 24
Finished Aug 18 04:40:25 PM PDT 24
Peak memory 182576 kb
Host smart-4c624339-d806-437d-a333-0451052d3279
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923040363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2923040363
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.64671869
Short name T477
Test name
Test status
Simulation time 29497796 ps
CPU time 0.58 seconds
Started Aug 18 04:40:28 PM PDT 24
Finished Aug 18 04:40:29 PM PDT 24
Peak memory 183060 kb
Host smart-201d078c-3425-487c-8555-31c84b7844ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64671869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.64671869
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3715987041
Short name T485
Test name
Test status
Simulation time 52753255 ps
CPU time 0.59 seconds
Started Aug 18 04:40:29 PM PDT 24
Finished Aug 18 04:40:29 PM PDT 24
Peak memory 183136 kb
Host smart-bcd7fa18-c8c7-4fb6-a119-5c17f1cfb5d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715987041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3715987041
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3887313803
Short name T491
Test name
Test status
Simulation time 15771121 ps
CPU time 0.63 seconds
Started Aug 18 04:40:29 PM PDT 24
Finished Aug 18 04:40:30 PM PDT 24
Peak memory 183148 kb
Host smart-6bed5850-9f15-49b8-9c2a-d131a2c29737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887313803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3887313803
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.243808595
Short name T535
Test name
Test status
Simulation time 15846577 ps
CPU time 0.58 seconds
Started Aug 18 04:40:31 PM PDT 24
Finished Aug 18 04:40:32 PM PDT 24
Peak memory 183136 kb
Host smart-e8f67e4b-5882-42f1-aeb5-f11e10334200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243808595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.243808595
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2505900494
Short name T580
Test name
Test status
Simulation time 67868207 ps
CPU time 0.86 seconds
Started Aug 18 04:40:05 PM PDT 24
Finished Aug 18 04:40:06 PM PDT 24
Peak memory 197772 kb
Host smart-54dda843-ead5-4380-b3a1-921d30b50da6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505900494 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2505900494
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2249378971
Short name T545
Test name
Test status
Simulation time 26684201 ps
CPU time 0.59 seconds
Started Aug 18 04:40:05 PM PDT 24
Finished Aug 18 04:40:06 PM PDT 24
Peak memory 183368 kb
Host smart-d73d4c5e-b3d2-4ae8-ab62-76e60ac3d1ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249378971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2249378971
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2237446598
Short name T551
Test name
Test status
Simulation time 33210519 ps
CPU time 0.53 seconds
Started Aug 18 04:40:18 PM PDT 24
Finished Aug 18 04:40:19 PM PDT 24
Peak memory 182444 kb
Host smart-fa4a98e0-6af7-45d9-8e11-7cee21ed2101
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237446598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2237446598
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1173382379
Short name T74
Test name
Test status
Simulation time 185025437 ps
CPU time 0.79 seconds
Started Aug 18 04:40:18 PM PDT 24
Finished Aug 18 04:40:19 PM PDT 24
Peak memory 192296 kb
Host smart-e2a5c88f-c342-4f5b-8737-12bfb9b8e251
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173382379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1173382379
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4098268243
Short name T46
Test name
Test status
Simulation time 150203466 ps
CPU time 2.63 seconds
Started Aug 18 04:40:18 PM PDT 24
Finished Aug 18 04:40:21 PM PDT 24
Peak memory 198076 kb
Host smart-e0638ddc-e1b9-448e-b923-7d25f3441db6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098268243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.4098268243
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.521137144
Short name T554
Test name
Test status
Simulation time 794066180 ps
CPU time 1.27 seconds
Started Aug 18 04:40:04 PM PDT 24
Finished Aug 18 04:40:06 PM PDT 24
Peak memory 195828 kb
Host smart-d4465dec-bd9f-418e-9d61-93e898d1e1ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521137144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.521137144
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3973921582
Short name T28
Test name
Test status
Simulation time 38781906 ps
CPU time 0.88 seconds
Started Aug 18 04:40:06 PM PDT 24
Finished Aug 18 04:40:07 PM PDT 24
Peak memory 197860 kb
Host smart-29e0aa99-3f52-4c8a-b7e6-f1c2325bb53c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973921582 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3973921582
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2664204634
Short name T67
Test name
Test status
Simulation time 32906102 ps
CPU time 0.58 seconds
Started Aug 18 04:40:03 PM PDT 24
Finished Aug 18 04:40:04 PM PDT 24
Peak memory 183388 kb
Host smart-ece0b3b8-f3fd-4fc6-a1f1-bf08951d3c63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664204634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2664204634
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.82895382
Short name T511
Test name
Test status
Simulation time 53734683 ps
CPU time 0.51 seconds
Started Aug 18 04:40:05 PM PDT 24
Finished Aug 18 04:40:05 PM PDT 24
Peak memory 182616 kb
Host smart-2988be80-7b0a-4149-ace3-90c81d0b5cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82895382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.82895382
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3069417887
Short name T77
Test name
Test status
Simulation time 60127634 ps
CPU time 0.76 seconds
Started Aug 18 04:40:05 PM PDT 24
Finished Aug 18 04:40:06 PM PDT 24
Peak memory 193836 kb
Host smart-dd9bfe5c-8d82-481e-b13f-b08a8358797d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069417887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3069417887
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.806974564
Short name T476
Test name
Test status
Simulation time 669160795 ps
CPU time 3.56 seconds
Started Aug 18 04:40:07 PM PDT 24
Finished Aug 18 04:40:10 PM PDT 24
Peak memory 198152 kb
Host smart-e208ae64-0286-4353-8a84-51cb01c5d1c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806974564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.806974564
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2743073707
Short name T539
Test name
Test status
Simulation time 500476066 ps
CPU time 1.87 seconds
Started Aug 18 04:40:18 PM PDT 24
Finished Aug 18 04:40:20 PM PDT 24
Peak memory 194740 kb
Host smart-0f4624e8-b656-4791-8c2d-d0aba8b7f33b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743073707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2743073707
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1845675190
Short name T541
Test name
Test status
Simulation time 37688079 ps
CPU time 0.92 seconds
Started Aug 18 04:40:08 PM PDT 24
Finished Aug 18 04:40:09 PM PDT 24
Peak memory 197792 kb
Host smart-4c0b5e14-8db9-470e-8faf-b48d5e544913
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845675190 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1845675190
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.511394297
Short name T65
Test name
Test status
Simulation time 55167447 ps
CPU time 0.56 seconds
Started Aug 18 04:40:15 PM PDT 24
Finished Aug 18 04:40:16 PM PDT 24
Peak memory 183328 kb
Host smart-ac641947-c749-44d8-a9e4-23da12b32af1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511394297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.511394297
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.639019293
Short name T559
Test name
Test status
Simulation time 14698526 ps
CPU time 0.57 seconds
Started Aug 18 04:40:06 PM PDT 24
Finished Aug 18 04:40:07 PM PDT 24
Peak memory 183380 kb
Host smart-60d7cc47-72b3-4f62-95f4-3040a7b48cd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639019293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.639019293
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3679960884
Short name T48
Test name
Test status
Simulation time 112264920 ps
CPU time 0.63 seconds
Started Aug 18 04:40:18 PM PDT 24
Finished Aug 18 04:40:19 PM PDT 24
Peak memory 192484 kb
Host smart-a01e6dac-4349-4b6d-8855-258cfd3d1cb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679960884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3679960884
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4195572913
Short name T469
Test name
Test status
Simulation time 338237711 ps
CPU time 1.85 seconds
Started Aug 18 04:40:07 PM PDT 24
Finished Aug 18 04:40:09 PM PDT 24
Peak memory 198132 kb
Host smart-2ea36e06-b378-4ac1-8ef5-1e99488f345a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195572913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.4195572913
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.339415151
Short name T82
Test name
Test status
Simulation time 84776346 ps
CPU time 1.13 seconds
Started Aug 18 04:40:04 PM PDT 24
Finished Aug 18 04:40:06 PM PDT 24
Peak memory 184020 kb
Host smart-6951b8c2-ff32-4a2d-8168-1db0fde63aab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339415151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.339415151
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3445904889
Short name T504
Test name
Test status
Simulation time 26851864 ps
CPU time 0.82 seconds
Started Aug 18 04:40:04 PM PDT 24
Finished Aug 18 04:40:05 PM PDT 24
Peak memory 196712 kb
Host smart-7c86922d-2238-4f05-9cd1-59987ca68f3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445904889 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3445904889
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.4188541817
Short name T495
Test name
Test status
Simulation time 13814374 ps
CPU time 0.58 seconds
Started Aug 18 04:40:08 PM PDT 24
Finished Aug 18 04:40:09 PM PDT 24
Peak memory 183344 kb
Host smart-f5e3f3f3-87b2-4a19-979d-0085fe200d25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188541817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.4188541817
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.882598095
Short name T490
Test name
Test status
Simulation time 40332564 ps
CPU time 0.6 seconds
Started Aug 18 04:40:18 PM PDT 24
Finished Aug 18 04:40:19 PM PDT 24
Peak memory 183124 kb
Host smart-56aa3a17-800e-40ef-ac5c-4b13248de14f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882598095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.882598095
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2537305468
Short name T546
Test name
Test status
Simulation time 81503128 ps
CPU time 0.72 seconds
Started Aug 18 04:40:04 PM PDT 24
Finished Aug 18 04:40:05 PM PDT 24
Peak memory 192212 kb
Host smart-d0218da3-9e98-414c-9756-42a760afe0b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537305468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2537305468
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1062482856
Short name T494
Test name
Test status
Simulation time 235225233 ps
CPU time 1.87 seconds
Started Aug 18 04:40:07 PM PDT 24
Finished Aug 18 04:40:09 PM PDT 24
Peak memory 197864 kb
Host smart-a50035bb-7307-4cd8-9563-a5d4ac838555
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062482856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1062482856
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3996501098
Short name T524
Test name
Test status
Simulation time 122244204 ps
CPU time 1.11 seconds
Started Aug 18 04:40:04 PM PDT 24
Finished Aug 18 04:40:05 PM PDT 24
Peak memory 183972 kb
Host smart-9edea137-7b67-47b3-b346-f849626576fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996501098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3996501098
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3130812219
Short name T560
Test name
Test status
Simulation time 110309169 ps
CPU time 0.58 seconds
Started Aug 18 04:40:04 PM PDT 24
Finished Aug 18 04:40:04 PM PDT 24
Peak memory 193000 kb
Host smart-cce3fea0-02af-4533-b1a7-404872f70e59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130812219 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3130812219
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2660028477
Short name T68
Test name
Test status
Simulation time 20985105 ps
CPU time 0.55 seconds
Started Aug 18 04:40:06 PM PDT 24
Finished Aug 18 04:40:07 PM PDT 24
Peak memory 183312 kb
Host smart-8ca54647-6633-4c64-8598-c485e0d654a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660028477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2660028477
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3676971709
Short name T506
Test name
Test status
Simulation time 26999334 ps
CPU time 0.56 seconds
Started Aug 18 04:40:04 PM PDT 24
Finished Aug 18 04:40:05 PM PDT 24
Peak memory 183272 kb
Host smart-e44c06b0-037e-442c-940d-18a9519c39c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676971709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3676971709
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.528810906
Short name T521
Test name
Test status
Simulation time 28374121 ps
CPU time 0.66 seconds
Started Aug 18 04:40:04 PM PDT 24
Finished Aug 18 04:40:05 PM PDT 24
Peak memory 192276 kb
Host smart-40c20d2a-25a1-4973-baf0-e58da4f89b85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528810906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.528810906
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1552074011
Short name T47
Test name
Test status
Simulation time 1427850466 ps
CPU time 2.99 seconds
Started Aug 18 04:40:03 PM PDT 24
Finished Aug 18 04:40:06 PM PDT 24
Peak memory 198096 kb
Host smart-29a14d03-dd5f-41cd-889e-ceba8e19f364
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552074011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1552074011
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3959054670
Short name T537
Test name
Test status
Simulation time 133497249 ps
CPU time 1.15 seconds
Started Aug 18 04:40:05 PM PDT 24
Finished Aug 18 04:40:06 PM PDT 24
Peak memory 183732 kb
Host smart-4b2c4317-40bc-4a66-976b-f389469535b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959054670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3959054670
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.874219841
Short name T350
Test name
Test status
Simulation time 180450676169 ps
CPU time 264.54 seconds
Started Aug 18 05:20:13 PM PDT 24
Finished Aug 18 05:24:38 PM PDT 24
Peak memory 183472 kb
Host smart-b73cb805-30d6-4dbd-9b81-639193fb9f95
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874219841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.874219841
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2654641172
Short name T375
Test name
Test status
Simulation time 56601607502 ps
CPU time 43.18 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:20:57 PM PDT 24
Peak memory 183732 kb
Host smart-079b67e0-8a7b-4fc0-8f98-ee8c11e282da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654641172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2654641172
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.3673863379
Short name T171
Test name
Test status
Simulation time 93193547974 ps
CPU time 159.66 seconds
Started Aug 18 05:20:09 PM PDT 24
Finished Aug 18 05:22:49 PM PDT 24
Peak memory 191584 kb
Host smart-fa9e0342-a898-46b9-9159-e6709c6c4a55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673863379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3673863379
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2173339087
Short name T165
Test name
Test status
Simulation time 108470384543 ps
CPU time 945.33 seconds
Started Aug 18 05:20:13 PM PDT 24
Finished Aug 18 05:35:59 PM PDT 24
Peak memory 191668 kb
Host smart-b790fe99-19fe-4f47-b96d-dd0a3f678986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173339087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2173339087
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2836939347
Short name T438
Test name
Test status
Simulation time 41151129801 ps
CPU time 62.89 seconds
Started Aug 18 05:20:10 PM PDT 24
Finished Aug 18 05:21:13 PM PDT 24
Peak memory 183384 kb
Host smart-3872360a-503e-47b7-9ec9-da08baf1f5a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836939347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2836939347
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.3320685049
Short name T419
Test name
Test status
Simulation time 3010190509 ps
CPU time 34.96 seconds
Started Aug 18 05:20:05 PM PDT 24
Finished Aug 18 05:20:40 PM PDT 24
Peak memory 198276 kb
Host smart-f79b24cb-83ad-4195-a401-22ef19446e3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320685049 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.3320685049
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.81087964
Short name T329
Test name
Test status
Simulation time 296311156275 ps
CPU time 432.82 seconds
Started Aug 18 05:20:12 PM PDT 24
Finished Aug 18 05:27:25 PM PDT 24
Peak memory 183536 kb
Host smart-81e0b307-bdf0-4a25-92ac-7b0a13a0ce5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81087964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
rv_timer_cfg_update_on_fly.81087964
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3369128147
Short name T395
Test name
Test status
Simulation time 116882971524 ps
CPU time 47.99 seconds
Started Aug 18 05:20:07 PM PDT 24
Finished Aug 18 05:20:55 PM PDT 24
Peak memory 183444 kb
Host smart-4dfd883b-5c6f-4344-860d-9a7a2f0263fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369128147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3369128147
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.234149776
Short name T410
Test name
Test status
Simulation time 177243292756 ps
CPU time 1111.96 seconds
Started Aug 18 05:20:05 PM PDT 24
Finished Aug 18 05:38:38 PM PDT 24
Peak memory 195160 kb
Host smart-20cba333-ca94-4c7f-93aa-ee0f2ec831ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234149776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.234149776
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.302462216
Short name T16
Test name
Test status
Simulation time 37825352 ps
CPU time 0.73 seconds
Started Aug 18 05:20:10 PM PDT 24
Finished Aug 18 05:20:11 PM PDT 24
Peak memory 213792 kb
Host smart-a5e2925f-c3cb-4623-97dc-9d29a240275e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302462216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.302462216
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.289263043
Short name T195
Test name
Test status
Simulation time 1571551290076 ps
CPU time 405.42 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:27:00 PM PDT 24
Peak memory 195068 kb
Host smart-b288f93b-6f12-435b-893a-ab88fd30677c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289263043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.289263043
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.720234512
Short name T449
Test name
Test status
Simulation time 1222376389 ps
CPU time 17.59 seconds
Started Aug 18 05:20:10 PM PDT 24
Finished Aug 18 05:20:27 PM PDT 24
Peak memory 197952 kb
Host smart-f70430c8-d190-4a23-bcad-591293933767
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720234512 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.720234512
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2301418002
Short name T360
Test name
Test status
Simulation time 776888199663 ps
CPU time 176.55 seconds
Started Aug 18 05:20:13 PM PDT 24
Finished Aug 18 05:23:09 PM PDT 24
Peak memory 183460 kb
Host smart-0952e76d-4267-468f-841a-2d2ed626039b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301418002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2301418002
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2008891778
Short name T388
Test name
Test status
Simulation time 610512878401 ps
CPU time 149.16 seconds
Started Aug 18 05:20:12 PM PDT 24
Finished Aug 18 05:22:42 PM PDT 24
Peak memory 183552 kb
Host smart-dba3f5cb-8f5a-4104-89a8-fb2c0b02135e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008891778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2008891778
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.290868106
Short name T293
Test name
Test status
Simulation time 74820786014 ps
CPU time 101.2 seconds
Started Aug 18 05:20:11 PM PDT 24
Finished Aug 18 05:21:53 PM PDT 24
Peak memory 191784 kb
Host smart-40a9c945-5e28-485e-8de6-d7d052364484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290868106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.290868106
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.4142962272
Short name T107
Test name
Test status
Simulation time 205832610328 ps
CPU time 138.83 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:22:33 PM PDT 24
Peak memory 191776 kb
Host smart-0eee1433-1df8-488d-bb7d-77d5a3e727fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142962272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.4142962272
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1289498511
Short name T265
Test name
Test status
Simulation time 1622776205337 ps
CPU time 981.1 seconds
Started Aug 18 05:20:13 PM PDT 24
Finished Aug 18 05:36:35 PM PDT 24
Peak memory 191700 kb
Host smart-6cbff45a-7596-4f54-b9b7-d132c53ac7cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289498511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1289498511
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2956904939
Short name T31
Test name
Test status
Simulation time 3804913059 ps
CPU time 43.16 seconds
Started Aug 18 05:20:15 PM PDT 24
Finished Aug 18 05:20:58 PM PDT 24
Peak memory 198296 kb
Host smart-3c7b1a6f-37e7-4be5-9ebb-444f5388363f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956904939 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2956904939
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.2220005798
Short name T135
Test name
Test status
Simulation time 69864300009 ps
CPU time 32.87 seconds
Started Aug 18 05:21:10 PM PDT 24
Finished Aug 18 05:21:43 PM PDT 24
Peak memory 183476 kb
Host smart-1e882129-1f6d-445a-9a03-5a19458c7ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220005798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2220005798
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1753379464
Short name T223
Test name
Test status
Simulation time 762577702866 ps
CPU time 1531.02 seconds
Started Aug 18 05:21:11 PM PDT 24
Finished Aug 18 05:46:43 PM PDT 24
Peak memory 191728 kb
Host smart-979e2de2-939a-4839-a83e-6e0450571bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753379464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1753379464
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3285687491
Short name T1
Test name
Test status
Simulation time 325177427515 ps
CPU time 152.54 seconds
Started Aug 18 05:21:21 PM PDT 24
Finished Aug 18 05:23:53 PM PDT 24
Peak memory 191788 kb
Host smart-8b7cccb2-d331-424c-9642-4956da95b49c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285687491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3285687491
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2331944997
Short name T243
Test name
Test status
Simulation time 261249462178 ps
CPU time 451.67 seconds
Started Aug 18 05:20:18 PM PDT 24
Finished Aug 18 05:27:50 PM PDT 24
Peak memory 183544 kb
Host smart-190d8de5-b027-43c0-ae41-1b367c7c3ad0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331944997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2331944997
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.38710560
Short name T428
Test name
Test status
Simulation time 223683684158 ps
CPU time 164.37 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:22:59 PM PDT 24
Peak memory 183564 kb
Host smart-dc921f6b-08d7-48ed-87c4-4aae24f43b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38710560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.38710560
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2498472675
Short name T197
Test name
Test status
Simulation time 18361081972 ps
CPU time 56.17 seconds
Started Aug 18 05:20:17 PM PDT 24
Finished Aug 18 05:21:13 PM PDT 24
Peak memory 183576 kb
Host smart-82daa52e-a1f0-45da-ab89-c804ba6dbb1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498472675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2498472675
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.577247677
Short name T285
Test name
Test status
Simulation time 270537689762 ps
CPU time 438.28 seconds
Started Aug 18 05:20:13 PM PDT 24
Finished Aug 18 05:27:31 PM PDT 24
Peak memory 183572 kb
Host smart-10d82d93-2944-4d8a-81cc-30c351fc9271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577247677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.577247677
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.3010143779
Short name T307
Test name
Test status
Simulation time 114682053645 ps
CPU time 62.2 seconds
Started Aug 18 05:21:18 PM PDT 24
Finished Aug 18 05:22:20 PM PDT 24
Peak memory 183540 kb
Host smart-335e62c1-a21a-424d-9030-fc5f91e72cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010143779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3010143779
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.848093377
Short name T432
Test name
Test status
Simulation time 304431729701 ps
CPU time 146.19 seconds
Started Aug 18 05:21:22 PM PDT 24
Finished Aug 18 05:23:48 PM PDT 24
Peak memory 191816 kb
Host smart-af1fb5ce-6c6d-4e52-8bc6-d991add2d893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848093377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.848093377
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.388393944
Short name T22
Test name
Test status
Simulation time 532238658626 ps
CPU time 443.91 seconds
Started Aug 18 05:21:21 PM PDT 24
Finished Aug 18 05:28:45 PM PDT 24
Peak memory 194040 kb
Host smart-fca3193b-91bc-483a-955f-636483605ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388393944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.388393944
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1514901251
Short name T221
Test name
Test status
Simulation time 147877294407 ps
CPU time 787.31 seconds
Started Aug 18 05:21:20 PM PDT 24
Finished Aug 18 05:34:28 PM PDT 24
Peak memory 191768 kb
Host smart-da86b338-9065-4cbf-a8c4-d4a2dfffd6a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514901251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1514901251
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2094404360
Short name T96
Test name
Test status
Simulation time 335945113095 ps
CPU time 163.23 seconds
Started Aug 18 05:21:21 PM PDT 24
Finished Aug 18 05:24:05 PM PDT 24
Peak memory 191764 kb
Host smart-f2e47a89-e64e-4023-b6b5-c00478161408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094404360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2094404360
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2994762491
Short name T134
Test name
Test status
Simulation time 280589956795 ps
CPU time 176.37 seconds
Started Aug 18 05:21:23 PM PDT 24
Finished Aug 18 05:24:20 PM PDT 24
Peak memory 191740 kb
Host smart-216c93ea-716f-412c-bb2a-eb0e815563cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994762491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2994762491
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.777564399
Short name T291
Test name
Test status
Simulation time 701972457187 ps
CPU time 339.21 seconds
Started Aug 18 05:21:20 PM PDT 24
Finished Aug 18 05:27:00 PM PDT 24
Peak memory 191780 kb
Host smart-a82992bb-760f-4dc7-acfa-eb0a443e0087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777564399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.777564399
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3861200194
Short name T43
Test name
Test status
Simulation time 75911120397 ps
CPU time 39.79 seconds
Started Aug 18 05:21:20 PM PDT 24
Finished Aug 18 05:22:00 PM PDT 24
Peak memory 183524 kb
Host smart-53c51d61-e454-419d-81d3-b498c94134cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861200194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3861200194
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3275359811
Short name T237
Test name
Test status
Simulation time 645848387961 ps
CPU time 1020.42 seconds
Started Aug 18 05:20:15 PM PDT 24
Finished Aug 18 05:37:16 PM PDT 24
Peak memory 183544 kb
Host smart-0cccc140-bc73-4914-a9de-58d9299b58c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275359811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3275359811
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2708079081
Short name T12
Test name
Test status
Simulation time 26179864921 ps
CPU time 11.43 seconds
Started Aug 18 05:20:17 PM PDT 24
Finished Aug 18 05:20:29 PM PDT 24
Peak memory 183548 kb
Host smart-b2ee498b-a052-4b9a-ac2e-7a8e547a2514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708079081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2708079081
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3411532565
Short name T37
Test name
Test status
Simulation time 153813725 ps
CPU time 0.69 seconds
Started Aug 18 05:20:16 PM PDT 24
Finished Aug 18 05:20:17 PM PDT 24
Peak memory 192188 kb
Host smart-9db8d128-5794-47ec-80ef-6931adda59cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411532565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3411532565
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2311463185
Short name T276
Test name
Test status
Simulation time 1205986564210 ps
CPU time 813.36 seconds
Started Aug 18 05:20:16 PM PDT 24
Finished Aug 18 05:33:49 PM PDT 24
Peak memory 191776 kb
Host smart-c86aaf56-d89b-408e-a43b-ea122cc6b32c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311463185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2311463185
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.2854724167
Short name T116
Test name
Test status
Simulation time 2454740686582 ps
CPU time 1793.96 seconds
Started Aug 18 05:21:20 PM PDT 24
Finished Aug 18 05:51:14 PM PDT 24
Peak memory 191752 kb
Host smart-f952f791-056c-4b35-b05c-59e9106ed5bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854724167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2854724167
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2248527141
Short name T362
Test name
Test status
Simulation time 37634399786 ps
CPU time 55.85 seconds
Started Aug 18 05:21:19 PM PDT 24
Finished Aug 18 05:22:15 PM PDT 24
Peak memory 191772 kb
Host smart-065e55f5-071e-40d0-9da0-8055f112137c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248527141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2248527141
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.474157714
Short name T125
Test name
Test status
Simulation time 40456542774 ps
CPU time 116.58 seconds
Started Aug 18 05:21:20 PM PDT 24
Finished Aug 18 05:23:16 PM PDT 24
Peak memory 191820 kb
Host smart-b96f82f2-5686-42c9-9519-ed0a5b0ffc63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474157714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.474157714
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3062220403
Short name T10
Test name
Test status
Simulation time 13253408573 ps
CPU time 21.8 seconds
Started Aug 18 05:21:22 PM PDT 24
Finished Aug 18 05:21:44 PM PDT 24
Peak memory 183576 kb
Host smart-cfe3197e-4971-45ed-a449-5ab0540035fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062220403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3062220403
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3389482859
Short name T282
Test name
Test status
Simulation time 31376954551 ps
CPU time 50.87 seconds
Started Aug 18 05:21:21 PM PDT 24
Finished Aug 18 05:22:12 PM PDT 24
Peak memory 183564 kb
Host smart-fafb9253-92da-432d-a4cf-ea75ef880a31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389482859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3389482859
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2222619618
Short name T166
Test name
Test status
Simulation time 42005271054 ps
CPU time 83.98 seconds
Started Aug 18 05:21:33 PM PDT 24
Finished Aug 18 05:22:57 PM PDT 24
Peak memory 183744 kb
Host smart-06313800-553b-4acc-965b-12814ad0d1bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222619618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2222619618
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.240977833
Short name T292
Test name
Test status
Simulation time 50089566732 ps
CPU time 29.28 seconds
Started Aug 18 05:20:13 PM PDT 24
Finished Aug 18 05:20:42 PM PDT 24
Peak memory 183528 kb
Host smart-19d5f841-df66-492b-b39c-96c59f49ed0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240977833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.240977833
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3647556057
Short name T396
Test name
Test status
Simulation time 487233415836 ps
CPU time 108.71 seconds
Started Aug 18 05:20:16 PM PDT 24
Finished Aug 18 05:22:05 PM PDT 24
Peak memory 183592 kb
Host smart-9a4a8e6b-f6d9-4a4d-bfe7-a6cac082df72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647556057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3647556057
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2614040733
Short name T327
Test name
Test status
Simulation time 153638075340 ps
CPU time 312.09 seconds
Started Aug 18 05:20:16 PM PDT 24
Finished Aug 18 05:25:28 PM PDT 24
Peak memory 191820 kb
Host smart-30b70810-3628-485e-a055-f44bbb1ddcbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614040733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2614040733
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2894056486
Short name T389
Test name
Test status
Simulation time 275536420064 ps
CPU time 121.83 seconds
Started Aug 18 05:20:15 PM PDT 24
Finished Aug 18 05:22:17 PM PDT 24
Peak memory 195236 kb
Host smart-62eeb1f4-c03a-4d3b-8129-0fda7bec5ed0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894056486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2894056486
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.644453110
Short name T313
Test name
Test status
Simulation time 281665118112 ps
CPU time 186.15 seconds
Started Aug 18 05:21:30 PM PDT 24
Finished Aug 18 05:24:36 PM PDT 24
Peak memory 191680 kb
Host smart-7e74529b-ff2b-4bd0-9bc3-127ba7d59003
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644453110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.644453110
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3002363245
Short name T89
Test name
Test status
Simulation time 174176761206 ps
CPU time 500.32 seconds
Started Aug 18 05:21:32 PM PDT 24
Finished Aug 18 05:29:52 PM PDT 24
Peak memory 191784 kb
Host smart-d268c779-4a4f-4563-9340-279e5174c24a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002363245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3002363245
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2140199467
Short name T160
Test name
Test status
Simulation time 1981619035674 ps
CPU time 526.24 seconds
Started Aug 18 05:21:30 PM PDT 24
Finished Aug 18 05:30:17 PM PDT 24
Peak memory 191812 kb
Host smart-b5c88106-d9d6-4856-a6ce-6ecb1a355337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140199467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2140199467
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3808652916
Short name T273
Test name
Test status
Simulation time 175898252270 ps
CPU time 167.43 seconds
Started Aug 18 05:21:31 PM PDT 24
Finished Aug 18 05:24:19 PM PDT 24
Peak memory 191756 kb
Host smart-3d8f0eca-0b60-42be-9f25-c94385034bb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808652916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3808652916
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3780848876
Short name T345
Test name
Test status
Simulation time 68990403824 ps
CPU time 110.76 seconds
Started Aug 18 05:21:31 PM PDT 24
Finished Aug 18 05:23:22 PM PDT 24
Peak memory 191656 kb
Host smart-cf3d2be5-4a7b-4681-9ea7-d3281df4a50e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780848876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3780848876
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3546321836
Short name T365
Test name
Test status
Simulation time 17626362298 ps
CPU time 95.29 seconds
Started Aug 18 05:21:31 PM PDT 24
Finished Aug 18 05:23:07 PM PDT 24
Peak memory 183572 kb
Host smart-bfccf0e6-c52e-4b0d-b24d-e6e934709e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546321836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3546321836
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3593079694
Short name T20
Test name
Test status
Simulation time 17388130159 ps
CPU time 19.69 seconds
Started Aug 18 05:20:19 PM PDT 24
Finished Aug 18 05:20:38 PM PDT 24
Peak memory 183572 kb
Host smart-0a29d48f-8641-4c71-beb0-ac5d3753e7f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593079694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3593079694
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.9447856
Short name T385
Test name
Test status
Simulation time 19730999212 ps
CPU time 30.65 seconds
Started Aug 18 05:20:19 PM PDT 24
Finished Aug 18 05:20:50 PM PDT 24
Peak memory 183572 kb
Host smart-36c5fc37-8ced-47ec-81f4-17684e2f45a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9447856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.9447856
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/140.rv_timer_random.1109177235
Short name T303
Test name
Test status
Simulation time 81203307163 ps
CPU time 188.74 seconds
Started Aug 18 05:21:31 PM PDT 24
Finished Aug 18 05:24:40 PM PDT 24
Peak memory 191792 kb
Host smart-c05bce9c-8ce6-4fba-a793-b6bfbdcd35cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109177235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1109177235
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2444134888
Short name T206
Test name
Test status
Simulation time 99505348895 ps
CPU time 332.39 seconds
Started Aug 18 05:21:31 PM PDT 24
Finished Aug 18 05:27:04 PM PDT 24
Peak memory 191720 kb
Host smart-0fe5d31d-c8a6-4305-bee5-3fd7d473d45d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444134888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2444134888
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3636624831
Short name T454
Test name
Test status
Simulation time 14220534998 ps
CPU time 23.13 seconds
Started Aug 18 05:21:30 PM PDT 24
Finished Aug 18 05:21:53 PM PDT 24
Peak memory 183508 kb
Host smart-f7cab006-e15f-43f4-be70-a358947d5e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636624831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3636624831
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3768255799
Short name T146
Test name
Test status
Simulation time 724354302825 ps
CPU time 1793.79 seconds
Started Aug 18 05:21:32 PM PDT 24
Finished Aug 18 05:51:26 PM PDT 24
Peak memory 191732 kb
Host smart-9d91eab5-512f-4d13-a6d5-2571c36fdfc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768255799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3768255799
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1663988631
Short name T224
Test name
Test status
Simulation time 95290596790 ps
CPU time 90.23 seconds
Started Aug 18 05:21:31 PM PDT 24
Finished Aug 18 05:23:01 PM PDT 24
Peak memory 183596 kb
Host smart-62a367ec-e2aa-4abd-a453-6c5fd152ada1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663988631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1663988631
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.778737818
Short name T424
Test name
Test status
Simulation time 202363449632 ps
CPU time 77.97 seconds
Started Aug 18 05:21:33 PM PDT 24
Finished Aug 18 05:22:51 PM PDT 24
Peak memory 183544 kb
Host smart-d8758c74-9f01-4b82-9d7f-f23e1d58187d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778737818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.778737818
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.16311633
Short name T111
Test name
Test status
Simulation time 40224999754 ps
CPU time 276.07 seconds
Started Aug 18 05:21:30 PM PDT 24
Finished Aug 18 05:26:06 PM PDT 24
Peak memory 183496 kb
Host smart-89cd4f7e-a447-4497-8512-446aac25993d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16311633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.16311633
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1993214699
Short name T296
Test name
Test status
Simulation time 509409629897 ps
CPU time 214.59 seconds
Started Aug 18 05:21:31 PM PDT 24
Finished Aug 18 05:25:06 PM PDT 24
Peak memory 191812 kb
Host smart-c0859f9a-18ea-4abc-945e-7b68aa8c3c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993214699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1993214699
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3753118386
Short name T418
Test name
Test status
Simulation time 493225374022 ps
CPU time 93.52 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:21:48 PM PDT 24
Peak memory 183532 kb
Host smart-a1c2a4b8-63aa-4e57-b6cb-ce2b4f2a2026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753118386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3753118386
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3374319771
Short name T188
Test name
Test status
Simulation time 48373126631 ps
CPU time 188.55 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:23:23 PM PDT 24
Peak memory 191760 kb
Host smart-f03f98dc-be82-401e-aa40-447fdcef7a07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374319771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3374319771
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.798223143
Short name T140
Test name
Test status
Simulation time 100630452076 ps
CPU time 45.08 seconds
Started Aug 18 05:21:39 PM PDT 24
Finished Aug 18 05:22:24 PM PDT 24
Peak memory 194136 kb
Host smart-8e7b1d32-d878-4b56-8e36-24b0a8c8e8d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798223143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.798223143
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2765907418
Short name T212
Test name
Test status
Simulation time 41211333324 ps
CPU time 72.31 seconds
Started Aug 18 05:21:40 PM PDT 24
Finished Aug 18 05:22:52 PM PDT 24
Peak memory 191732 kb
Host smart-b77d4e00-831d-4854-b899-489285be8773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765907418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2765907418
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.634692412
Short name T150
Test name
Test status
Simulation time 329412205320 ps
CPU time 1448.18 seconds
Started Aug 18 05:21:40 PM PDT 24
Finished Aug 18 05:45:48 PM PDT 24
Peak memory 191812 kb
Host smart-8259ff0d-6793-443d-ae24-300e58d59fbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634692412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.634692412
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.950579133
Short name T357
Test name
Test status
Simulation time 182952445990 ps
CPU time 160.96 seconds
Started Aug 18 05:21:39 PM PDT 24
Finished Aug 18 05:24:20 PM PDT 24
Peak memory 183484 kb
Host smart-07861ddd-6642-4eda-b7a2-03d5cd977bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950579133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.950579133
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1107626616
Short name T153
Test name
Test status
Simulation time 39630948026 ps
CPU time 36.93 seconds
Started Aug 18 05:21:39 PM PDT 24
Finished Aug 18 05:22:16 PM PDT 24
Peak memory 191700 kb
Host smart-afee44fd-05d1-4362-bb0f-e0c8b832cfd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107626616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1107626616
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2064191723
Short name T123
Test name
Test status
Simulation time 468660491285 ps
CPU time 252.91 seconds
Started Aug 18 05:20:25 PM PDT 24
Finished Aug 18 05:24:38 PM PDT 24
Peak memory 183524 kb
Host smart-37fd137b-29f4-46e9-9919-2cec4aedc5e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064191723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2064191723
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.296553241
Short name T378
Test name
Test status
Simulation time 56968011414 ps
CPU time 91.55 seconds
Started Aug 18 05:20:22 PM PDT 24
Finished Aug 18 05:21:54 PM PDT 24
Peak memory 183488 kb
Host smart-976179e6-f779-486d-93ed-7c1502fcb4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296553241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.296553241
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3800312341
Short name T248
Test name
Test status
Simulation time 92459779792 ps
CPU time 381.03 seconds
Started Aug 18 05:20:22 PM PDT 24
Finished Aug 18 05:26:43 PM PDT 24
Peak memory 191752 kb
Host smart-407de7a8-ce19-4dfa-85d2-1045f1d89ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800312341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3800312341
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.662630509
Short name T132
Test name
Test status
Simulation time 75402707585 ps
CPU time 132.53 seconds
Started Aug 18 05:20:21 PM PDT 24
Finished Aug 18 05:22:34 PM PDT 24
Peak memory 183580 kb
Host smart-d64d4f7b-b7c9-437d-a656-4f84e8034583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662630509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.662630509
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.2941132252
Short name T408
Test name
Test status
Simulation time 16044757360 ps
CPU time 35.25 seconds
Started Aug 18 05:20:28 PM PDT 24
Finished Aug 18 05:21:04 PM PDT 24
Peak memory 198272 kb
Host smart-5bf6e5b7-6c4e-43cb-a212-a4f2c6088124
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941132252 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.2941132252
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3873983058
Short name T340
Test name
Test status
Simulation time 12790850817 ps
CPU time 22.62 seconds
Started Aug 18 05:21:39 PM PDT 24
Finished Aug 18 05:22:01 PM PDT 24
Peak memory 183464 kb
Host smart-c39e8c08-74eb-4a46-89ea-2fbeef26a26a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873983058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3873983058
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.812042814
Short name T413
Test name
Test status
Simulation time 13251087343 ps
CPU time 22.39 seconds
Started Aug 18 05:21:43 PM PDT 24
Finished Aug 18 05:22:06 PM PDT 24
Peak memory 183584 kb
Host smart-96cf4fec-8d0c-4c05-acb0-2984f9edfe56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812042814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.812042814
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.4261296335
Short name T167
Test name
Test status
Simulation time 86390568649 ps
CPU time 178.42 seconds
Started Aug 18 05:21:39 PM PDT 24
Finished Aug 18 05:24:38 PM PDT 24
Peak memory 194092 kb
Host smart-c792d81c-a336-4c36-a851-fd994a1edfb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261296335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.4261296335
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.4076021896
Short name T453
Test name
Test status
Simulation time 771294874870 ps
CPU time 220.55 seconds
Started Aug 18 05:21:41 PM PDT 24
Finished Aug 18 05:25:22 PM PDT 24
Peak memory 191692 kb
Host smart-2beddcd7-1237-4cb7-b086-0d22b482942c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076021896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.4076021896
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3463079073
Short name T198
Test name
Test status
Simulation time 49490833037 ps
CPU time 89.41 seconds
Started Aug 18 05:21:44 PM PDT 24
Finished Aug 18 05:23:13 PM PDT 24
Peak memory 191764 kb
Host smart-6e58c09b-5488-49a2-b7be-57354b3d73ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463079073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3463079073
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.4041950575
Short name T217
Test name
Test status
Simulation time 4263780524 ps
CPU time 6.86 seconds
Started Aug 18 05:20:24 PM PDT 24
Finished Aug 18 05:20:31 PM PDT 24
Peak memory 183544 kb
Host smart-7e6d047d-33e9-444b-b6cf-bfb0a616870e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041950575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.4041950575
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.535488497
Short name T429
Test name
Test status
Simulation time 127059353823 ps
CPU time 49.84 seconds
Started Aug 18 05:20:24 PM PDT 24
Finished Aug 18 05:21:14 PM PDT 24
Peak memory 183572 kb
Host smart-55c4b9d3-0232-4ea0-b5cc-dc85ea5b2185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535488497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.535488497
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.2295369463
Short name T352
Test name
Test status
Simulation time 632141039723 ps
CPU time 336.79 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:26:00 PM PDT 24
Peak memory 191784 kb
Host smart-fe80fcf2-3500-495d-87d2-debb71ff739a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295369463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2295369463
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.277331336
Short name T359
Test name
Test status
Simulation time 41603325579 ps
CPU time 13.18 seconds
Started Aug 18 05:20:24 PM PDT 24
Finished Aug 18 05:20:38 PM PDT 24
Peak memory 191776 kb
Host smart-091ecfb9-72fd-4b13-acd6-b332f3022fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277331336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.277331336
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1073233300
Short name T55
Test name
Test status
Simulation time 156544207070 ps
CPU time 209.55 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:23:53 PM PDT 24
Peak memory 183448 kb
Host smart-588804b5-c6b2-43a7-8562-eceecf531dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073233300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1073233300
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.1822569290
Short name T34
Test name
Test status
Simulation time 936928319 ps
CPU time 8.63 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:20:32 PM PDT 24
Peak memory 198152 kb
Host smart-f31f3c84-d3df-4f81-be20-ef30f6758481
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822569290 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.1822569290
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.978651208
Short name T202
Test name
Test status
Simulation time 64006859339 ps
CPU time 120.4 seconds
Started Aug 18 05:21:44 PM PDT 24
Finished Aug 18 05:23:45 PM PDT 24
Peak memory 183572 kb
Host smart-4dd70c0e-6e04-4ddb-b460-8289e103c000
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978651208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.978651208
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2000236226
Short name T162
Test name
Test status
Simulation time 135651231813 ps
CPU time 334.5 seconds
Started Aug 18 05:21:39 PM PDT 24
Finished Aug 18 05:27:14 PM PDT 24
Peak memory 191764 kb
Host smart-8223adbe-621b-41f2-865f-7a93bd55770c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000236226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2000236226
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.186380972
Short name T216
Test name
Test status
Simulation time 351324041474 ps
CPU time 190.9 seconds
Started Aug 18 05:21:42 PM PDT 24
Finished Aug 18 05:24:53 PM PDT 24
Peak memory 191744 kb
Host smart-39142cb4-496b-40d7-bbbe-67b288c968be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186380972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.186380972
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2011934154
Short name T289
Test name
Test status
Simulation time 678954558403 ps
CPU time 809.65 seconds
Started Aug 18 05:21:37 PM PDT 24
Finished Aug 18 05:35:07 PM PDT 24
Peak memory 191660 kb
Host smart-7ce64960-e5a8-47c1-88a3-c481c1f94d5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011934154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2011934154
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3410367579
Short name T229
Test name
Test status
Simulation time 961836892076 ps
CPU time 280.75 seconds
Started Aug 18 05:21:43 PM PDT 24
Finished Aug 18 05:26:24 PM PDT 24
Peak memory 191652 kb
Host smart-25c29af5-9d48-491d-a4d3-7214397573bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410367579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3410367579
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1336111086
Short name T133
Test name
Test status
Simulation time 512153326543 ps
CPU time 1062.16 seconds
Started Aug 18 05:21:39 PM PDT 24
Finished Aug 18 05:39:21 PM PDT 24
Peak memory 191808 kb
Host smart-2911d240-a06e-4b0a-96e8-20e66fe7cf58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336111086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1336111086
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3773232984
Short name T374
Test name
Test status
Simulation time 175405155663 ps
CPU time 90.47 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:21:54 PM PDT 24
Peak memory 183524 kb
Host smart-3825d6af-3f04-4f89-87a9-5642035568db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773232984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3773232984
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1503435945
Short name T207
Test name
Test status
Simulation time 75567990111 ps
CPU time 445.61 seconds
Started Aug 18 05:20:24 PM PDT 24
Finished Aug 18 05:27:50 PM PDT 24
Peak memory 191816 kb
Host smart-a69f678e-d36e-44e2-86b4-a87d4d0d3e00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503435945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1503435945
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1848633272
Short name T175
Test name
Test status
Simulation time 158568943555 ps
CPU time 131.79 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:22:35 PM PDT 24
Peak memory 191768 kb
Host smart-e399e35c-2c14-4ed4-9225-2325641a0833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848633272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1848633272
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1292610356
Short name T230
Test name
Test status
Simulation time 20260224165 ps
CPU time 216.65 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:23:59 PM PDT 24
Peak memory 195420 kb
Host smart-f5c1db7e-1e77-4d8f-bd09-ff20b897fb00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292610356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1292610356
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.1449882219
Short name T15
Test name
Test status
Simulation time 3094679898 ps
CPU time 30.86 seconds
Started Aug 18 05:20:25 PM PDT 24
Finished Aug 18 05:20:56 PM PDT 24
Peak memory 194264 kb
Host smart-b1d23e5e-7776-4784-9d3c-5ec2634c544f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449882219 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.1449882219
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1457139078
Short name T128
Test name
Test status
Simulation time 43503270956 ps
CPU time 148.85 seconds
Started Aug 18 05:21:40 PM PDT 24
Finished Aug 18 05:24:09 PM PDT 24
Peak memory 191776 kb
Host smart-aaae14a8-fc8a-40fa-bc05-ac07925b1245
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457139078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1457139078
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.113684003
Short name T343
Test name
Test status
Simulation time 69866598200 ps
CPU time 113.89 seconds
Started Aug 18 05:21:40 PM PDT 24
Finished Aug 18 05:23:34 PM PDT 24
Peak memory 191776 kb
Host smart-52bf263d-318f-4188-9665-bc4cae289421
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113684003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.113684003
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.2801068166
Short name T347
Test name
Test status
Simulation time 603425458304 ps
CPU time 589.83 seconds
Started Aug 18 05:21:50 PM PDT 24
Finished Aug 18 05:31:40 PM PDT 24
Peak memory 191764 kb
Host smart-7dc1b811-7151-4b6c-9eb6-2c1990914275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801068166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2801068166
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3603518318
Short name T118
Test name
Test status
Simulation time 185554069904 ps
CPU time 822.47 seconds
Started Aug 18 05:21:51 PM PDT 24
Finished Aug 18 05:35:34 PM PDT 24
Peak memory 191676 kb
Host smart-0b69c533-b32f-4b5a-8e07-fd3d95ebc897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603518318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3603518318
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3042473073
Short name T349
Test name
Test status
Simulation time 143476731894 ps
CPU time 2496.91 seconds
Started Aug 18 05:21:56 PM PDT 24
Finished Aug 18 06:03:33 PM PDT 24
Peak memory 191772 kb
Host smart-7b1af9a5-8066-4933-b6a1-5d3e7301fe6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042473073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3042473073
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.371161205
Short name T242
Test name
Test status
Simulation time 389673482776 ps
CPU time 204.1 seconds
Started Aug 18 05:21:50 PM PDT 24
Finished Aug 18 05:25:15 PM PDT 24
Peak memory 191760 kb
Host smart-f50f8916-67be-4d5a-9f01-8c5ffada3175
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371161205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.371161205
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.4049856279
Short name T95
Test name
Test status
Simulation time 84558742250 ps
CPU time 153.85 seconds
Started Aug 18 05:20:28 PM PDT 24
Finished Aug 18 05:23:02 PM PDT 24
Peak memory 183540 kb
Host smart-1f53589a-1995-422a-8ff8-60d84fc9d39e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049856279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.4049856279
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1573359591
Short name T8
Test name
Test status
Simulation time 65061795654 ps
CPU time 43.69 seconds
Started Aug 18 05:20:28 PM PDT 24
Finished Aug 18 05:21:12 PM PDT 24
Peak memory 183552 kb
Host smart-652f5cfa-02b7-4078-bf00-777a5d9c201b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573359591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1573359591
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.2951489913
Short name T450
Test name
Test status
Simulation time 55679035763 ps
CPU time 95.12 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:21:58 PM PDT 24
Peak memory 191800 kb
Host smart-7a7bb836-e3d8-4dc8-b84a-1a3d4d91f8f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951489913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2951489913
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2538129966
Short name T49
Test name
Test status
Simulation time 48906631666 ps
CPU time 12.13 seconds
Started Aug 18 05:20:22 PM PDT 24
Finished Aug 18 05:20:34 PM PDT 24
Peak memory 192696 kb
Host smart-0f41152f-d7cc-4521-8aba-a836e5ae6c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538129966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2538129966
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1553057646
Short name T281
Test name
Test status
Simulation time 736937622950 ps
CPU time 2024.34 seconds
Started Aug 18 05:20:24 PM PDT 24
Finished Aug 18 05:54:09 PM PDT 24
Peak memory 196544 kb
Host smart-3cead477-0746-498f-a67a-544e4c8526ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553057646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1553057646
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.1746676152
Short name T247
Test name
Test status
Simulation time 387019720397 ps
CPU time 515.19 seconds
Started Aug 18 05:21:50 PM PDT 24
Finished Aug 18 05:30:26 PM PDT 24
Peak memory 191756 kb
Host smart-8dc03d0f-b7ac-4e24-a1fe-402bced484b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746676152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1746676152
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.261130241
Short name T412
Test name
Test status
Simulation time 36724099803 ps
CPU time 58.8 seconds
Started Aug 18 05:21:51 PM PDT 24
Finished Aug 18 05:22:50 PM PDT 24
Peak memory 183592 kb
Host smart-38fcd13f-fd54-4ecf-b0ca-ea3125dfdbac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261130241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.261130241
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.408097900
Short name T127
Test name
Test status
Simulation time 21301554601 ps
CPU time 34.14 seconds
Started Aug 18 05:21:56 PM PDT 24
Finished Aug 18 05:22:30 PM PDT 24
Peak memory 183576 kb
Host smart-afc45c77-2ce0-4f72-88b2-fade6304e564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408097900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.408097900
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1588396093
Short name T332
Test name
Test status
Simulation time 75253434742 ps
CPU time 447.52 seconds
Started Aug 18 05:21:56 PM PDT 24
Finished Aug 18 05:29:24 PM PDT 24
Peak memory 191748 kb
Host smart-d8e8815e-230d-471b-ae5f-98b9afe504c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588396093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1588396093
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.390094753
Short name T122
Test name
Test status
Simulation time 81904260129 ps
CPU time 127.36 seconds
Started Aug 18 05:21:49 PM PDT 24
Finished Aug 18 05:23:56 PM PDT 24
Peak memory 191724 kb
Host smart-266723f1-7a52-4bad-b1e2-9450ec221897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390094753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.390094753
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3545532361
Short name T356
Test name
Test status
Simulation time 59115697873 ps
CPU time 122.19 seconds
Started Aug 18 05:21:51 PM PDT 24
Finished Aug 18 05:23:54 PM PDT 24
Peak memory 183500 kb
Host smart-07f03786-6791-4d11-b618-4c9f04c3ceeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545532361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3545532361
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3233511127
Short name T211
Test name
Test status
Simulation time 121790244824 ps
CPU time 229.2 seconds
Started Aug 18 05:21:50 PM PDT 24
Finished Aug 18 05:25:39 PM PDT 24
Peak memory 191796 kb
Host smart-5f95feb5-1eb4-446a-87ef-cd9b9012cd13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233511127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3233511127
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2190215609
Short name T261
Test name
Test status
Simulation time 513723820097 ps
CPU time 324.14 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:25:38 PM PDT 24
Peak memory 183728 kb
Host smart-dcec60d3-52cb-4790-a673-a201f62ddafc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190215609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2190215609
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1519540590
Short name T391
Test name
Test status
Simulation time 47363688181 ps
CPU time 65.1 seconds
Started Aug 18 05:20:12 PM PDT 24
Finished Aug 18 05:21:17 PM PDT 24
Peak memory 183540 kb
Host smart-435339a0-b5b2-46ae-8b9d-8bde2f2bcecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519540590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1519540590
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1225484360
Short name T298
Test name
Test status
Simulation time 19755027935 ps
CPU time 98.37 seconds
Started Aug 18 05:20:13 PM PDT 24
Finished Aug 18 05:21:51 PM PDT 24
Peak memory 191780 kb
Host smart-28dea79e-73dd-4a09-8239-cd73e2ac13a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225484360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1225484360
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.263705718
Short name T326
Test name
Test status
Simulation time 419766706 ps
CPU time 0.85 seconds
Started Aug 18 05:20:10 PM PDT 24
Finished Aug 18 05:20:11 PM PDT 24
Peak memory 183100 kb
Host smart-13dbf428-c371-4ed8-bea8-e679e799d320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263705718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.263705718
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1895761975
Short name T6
Test name
Test status
Simulation time 172295842 ps
CPU time 0.83 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:20:15 PM PDT 24
Peak memory 214160 kb
Host smart-4f2fcfa8-a326-4033-a511-503850939a66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895761975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1895761975
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3451128013
Short name T415
Test name
Test status
Simulation time 69875283160 ps
CPU time 89.53 seconds
Started Aug 18 05:20:13 PM PDT 24
Finished Aug 18 05:21:43 PM PDT 24
Peak memory 183468 kb
Host smart-bdaa84eb-9685-4896-80be-eb6e2f06caff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451128013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3451128013
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.13289134
Short name T407
Test name
Test status
Simulation time 176274354956 ps
CPU time 68.82 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:21:32 PM PDT 24
Peak memory 183564 kb
Host smart-00dfbb0e-08e8-4fcd-8810-085da72c2cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13289134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.13289134
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2612017332
Short name T105
Test name
Test status
Simulation time 136315112087 ps
CPU time 1154.73 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:39:38 PM PDT 24
Peak memory 191780 kb
Host smart-2a2c5f61-88d1-464e-9eff-5a38da7bfcfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612017332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2612017332
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.864568931
Short name T436
Test name
Test status
Simulation time 679142454 ps
CPU time 1.4 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:20:25 PM PDT 24
Peak memory 183220 kb
Host smart-af8935f0-62e9-4ead-8631-ff86f4a30836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864568931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.864568931
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.1729044333
Short name T32
Test name
Test status
Simulation time 5696607613 ps
CPU time 11.95 seconds
Started Aug 18 05:20:28 PM PDT 24
Finished Aug 18 05:20:40 PM PDT 24
Peak memory 198292 kb
Host smart-30b7d328-3d1a-4457-895c-2f0e8410cfd5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729044333 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.1729044333
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2258869156
Short name T286
Test name
Test status
Simulation time 622524122995 ps
CPU time 395.88 seconds
Started Aug 18 05:20:29 PM PDT 24
Finished Aug 18 05:27:05 PM PDT 24
Peak memory 183480 kb
Host smart-1ecd5568-313b-4eb6-8b30-f08900255699
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258869156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2258869156
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.474984203
Short name T397
Test name
Test status
Simulation time 470445447639 ps
CPU time 179.15 seconds
Started Aug 18 05:20:25 PM PDT 24
Finished Aug 18 05:23:24 PM PDT 24
Peak memory 183488 kb
Host smart-82ed168e-278e-4628-b68c-7d407827c82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474984203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.474984203
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2313257942
Short name T93
Test name
Test status
Simulation time 286240018136 ps
CPU time 707.17 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:32:10 PM PDT 24
Peak memory 191720 kb
Host smart-fd4ecb9e-8ff7-4613-84fb-b17c42d73c1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313257942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2313257942
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2506547901
Short name T192
Test name
Test status
Simulation time 865865253425 ps
CPU time 234.37 seconds
Started Aug 18 05:20:21 PM PDT 24
Finished Aug 18 05:24:16 PM PDT 24
Peak memory 194436 kb
Host smart-9290780c-c356-4550-be92-7147b0385859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506547901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2506547901
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1262136871
Short name T131
Test name
Test status
Simulation time 350074089858 ps
CPU time 80.76 seconds
Started Aug 18 05:20:31 PM PDT 24
Finished Aug 18 05:21:52 PM PDT 24
Peak memory 183568 kb
Host smart-aeadd483-c821-4bbf-a0e2-b529e35f1659
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262136871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1262136871
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.798061259
Short name T376
Test name
Test status
Simulation time 78230792508 ps
CPU time 42.09 seconds
Started Aug 18 05:20:24 PM PDT 24
Finished Aug 18 05:21:06 PM PDT 24
Peak memory 183588 kb
Host smart-b0881acd-3ef2-420c-b2b7-17279592024e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798061259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.798061259
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1441859534
Short name T139
Test name
Test status
Simulation time 1102576482280 ps
CPU time 344.13 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:26:08 PM PDT 24
Peak memory 191664 kb
Host smart-5cb11210-046f-4339-b5ac-1493eeb88049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441859534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1441859534
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3747387320
Short name T335
Test name
Test status
Simulation time 83570709173 ps
CPU time 67.23 seconds
Started Aug 18 05:20:23 PM PDT 24
Finished Aug 18 05:21:30 PM PDT 24
Peak memory 191792 kb
Host smart-24b01f41-8146-40b1-9972-10283c04612b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747387320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3747387320
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.896465380
Short name T2
Test name
Test status
Simulation time 141093948932 ps
CPU time 135.37 seconds
Started Aug 18 05:20:33 PM PDT 24
Finished Aug 18 05:22:49 PM PDT 24
Peak memory 183464 kb
Host smart-71191e92-0b39-4b06-b69c-2da26c3ff907
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896465380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.896465380
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1019699744
Short name T442
Test name
Test status
Simulation time 270465851983 ps
CPU time 72.53 seconds
Started Aug 18 05:20:31 PM PDT 24
Finished Aug 18 05:21:44 PM PDT 24
Peak memory 183572 kb
Host smart-5fde47f9-b230-499b-ad3a-92addd2fd3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019699744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1019699744
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2465366999
Short name T41
Test name
Test status
Simulation time 44451948884 ps
CPU time 244.9 seconds
Started Aug 18 05:20:32 PM PDT 24
Finished Aug 18 05:24:37 PM PDT 24
Peak memory 191756 kb
Host smart-b83c9945-8ad7-4a3f-8f69-1011268866fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465366999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2465366999
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.299063306
Short name T137
Test name
Test status
Simulation time 380508831928 ps
CPU time 179.84 seconds
Started Aug 18 05:20:32 PM PDT 24
Finished Aug 18 05:23:32 PM PDT 24
Peak memory 183448 kb
Host smart-fa01c89b-3dfb-4cb9-a440-8fdaf57653e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299063306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.299063306
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2240000294
Short name T455
Test name
Test status
Simulation time 20129296758 ps
CPU time 30.14 seconds
Started Aug 18 05:20:42 PM PDT 24
Finished Aug 18 05:21:12 PM PDT 24
Peak memory 183492 kb
Host smart-a9afcd3e-9322-4942-bf24-20db7db248fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240000294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2240000294
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2529057136
Short name T239
Test name
Test status
Simulation time 297324862502 ps
CPU time 240.95 seconds
Started Aug 18 05:20:37 PM PDT 24
Finished Aug 18 05:24:39 PM PDT 24
Peak memory 191720 kb
Host smart-a3c9c93e-47e9-43f9-b545-a37aa9b466a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529057136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2529057136
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.861407017
Short name T112
Test name
Test status
Simulation time 118146177067 ps
CPU time 384.62 seconds
Started Aug 18 05:20:33 PM PDT 24
Finished Aug 18 05:26:58 PM PDT 24
Peak memory 191776 kb
Host smart-162e0571-cd56-4d7f-8f6b-f9934f1315c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861407017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.861407017
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.615897357
Short name T264
Test name
Test status
Simulation time 194954752952 ps
CPU time 161.2 seconds
Started Aug 18 05:20:30 PM PDT 24
Finished Aug 18 05:23:12 PM PDT 24
Peak memory 183576 kb
Host smart-1dd2cb32-426a-438e-bcf5-2a1cbe59b6b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615897357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.615897357
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.4005529847
Short name T448
Test name
Test status
Simulation time 152973788322 ps
CPU time 203.39 seconds
Started Aug 18 05:20:37 PM PDT 24
Finished Aug 18 05:24:00 PM PDT 24
Peak memory 183480 kb
Host smart-95b334d1-56df-4376-acba-4363809a3899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005529847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.4005529847
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1906180529
Short name T370
Test name
Test status
Simulation time 43041859781 ps
CPU time 14.98 seconds
Started Aug 18 05:20:40 PM PDT 24
Finished Aug 18 05:20:55 PM PDT 24
Peak memory 191720 kb
Host smart-94bc921a-a4ec-4251-9fd5-7532ffaef679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906180529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1906180529
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1644044402
Short name T226
Test name
Test status
Simulation time 486262085568 ps
CPU time 1858.45 seconds
Started Aug 18 05:20:33 PM PDT 24
Finished Aug 18 05:51:32 PM PDT 24
Peak memory 195484 kb
Host smart-cbf7f1be-e40f-4553-ad96-4d7a9f230cb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644044402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1644044402
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.4187327792
Short name T92
Test name
Test status
Simulation time 104387947877 ps
CPU time 147.37 seconds
Started Aug 18 05:20:36 PM PDT 24
Finished Aug 18 05:23:04 PM PDT 24
Peak memory 183452 kb
Host smart-62e3af45-1c4e-40a0-88fc-442ee17517b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187327792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.4187327792
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3918419727
Short name T402
Test name
Test status
Simulation time 164919671790 ps
CPU time 79.89 seconds
Started Aug 18 05:20:31 PM PDT 24
Finished Aug 18 05:21:51 PM PDT 24
Peak memory 183476 kb
Host smart-003f3bf9-bc73-4ea0-a29a-394484077c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918419727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3918419727
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.299771274
Short name T323
Test name
Test status
Simulation time 452278300763 ps
CPU time 480.99 seconds
Started Aug 18 05:20:30 PM PDT 24
Finished Aug 18 05:28:31 PM PDT 24
Peak memory 191684 kb
Host smart-dacf9290-f5d7-43d6-bd23-250bf1c90538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299771274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.299771274
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1910344247
Short name T369
Test name
Test status
Simulation time 852494502 ps
CPU time 4.45 seconds
Started Aug 18 05:20:36 PM PDT 24
Finished Aug 18 05:20:40 PM PDT 24
Peak memory 183420 kb
Host smart-fb355b05-3ae3-405a-96d7-a67fe2b8c72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910344247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1910344247
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3037589
Short name T54
Test name
Test status
Simulation time 3263208327100 ps
CPU time 1693.1 seconds
Started Aug 18 05:20:39 PM PDT 24
Finished Aug 18 05:48:53 PM PDT 24
Peak memory 196468 kb
Host smart-3ec807e7-3f5d-48d8-a3ab-f599a45930fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.3037589
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.2321850547
Short name T44
Test name
Test status
Simulation time 1907179687 ps
CPU time 14.95 seconds
Started Aug 18 05:20:36 PM PDT 24
Finished Aug 18 05:20:51 PM PDT 24
Peak memory 193748 kb
Host smart-c035621f-fcf8-42c8-b0a1-e7cebf5b0da2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321850547 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.2321850547
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1110167650
Short name T409
Test name
Test status
Simulation time 336131086881 ps
CPU time 602.15 seconds
Started Aug 18 05:20:33 PM PDT 24
Finished Aug 18 05:30:36 PM PDT 24
Peak memory 183448 kb
Host smart-69608e34-5f94-4dc8-8cc9-54ef1bd691c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110167650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1110167650
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1972577627
Short name T38
Test name
Test status
Simulation time 113339886435 ps
CPU time 44.47 seconds
Started Aug 18 05:20:32 PM PDT 24
Finished Aug 18 05:21:16 PM PDT 24
Peak memory 183500 kb
Host smart-c3d65c1e-c0e5-475a-9d6f-b25ebf8e99d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972577627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1972577627
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.41907065
Short name T355
Test name
Test status
Simulation time 90235168822 ps
CPU time 378.63 seconds
Started Aug 18 05:20:33 PM PDT 24
Finished Aug 18 05:26:52 PM PDT 24
Peak memory 191668 kb
Host smart-bd471ee9-ce38-40e3-a42c-02b90d2b9c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41907065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.41907065
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.702182015
Short name T33
Test name
Test status
Simulation time 2028731655 ps
CPU time 24.54 seconds
Started Aug 18 05:20:40 PM PDT 24
Finished Aug 18 05:21:05 PM PDT 24
Peak memory 198100 kb
Host smart-397f9a84-dd42-4270-9153-ceda7eb6189a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702182015 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.702182015
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3079859819
Short name T272
Test name
Test status
Simulation time 305189939476 ps
CPU time 273.94 seconds
Started Aug 18 05:20:38 PM PDT 24
Finished Aug 18 05:25:12 PM PDT 24
Peak memory 183412 kb
Host smart-133f1ae9-ed51-4ac9-9167-66096f3c5ffb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079859819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3079859819
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1736115689
Short name T405
Test name
Test status
Simulation time 116522223447 ps
CPU time 140.01 seconds
Started Aug 18 05:20:38 PM PDT 24
Finished Aug 18 05:22:58 PM PDT 24
Peak memory 183536 kb
Host smart-fd4c0dd0-dd8c-4ae5-9a7d-8724516a576e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736115689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1736115689
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.372057246
Short name T301
Test name
Test status
Simulation time 7838057796 ps
CPU time 67.95 seconds
Started Aug 18 05:20:31 PM PDT 24
Finished Aug 18 05:21:39 PM PDT 24
Peak memory 183480 kb
Host smart-ad72c064-ba81-4e30-89dd-de7dc03c2350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372057246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.372057246
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.723599605
Short name T381
Test name
Test status
Simulation time 171994822 ps
CPU time 0.55 seconds
Started Aug 18 05:20:39 PM PDT 24
Finished Aug 18 05:20:40 PM PDT 24
Peak memory 183176 kb
Host smart-bbd4cb39-b41a-4af1-85ff-89958a7da29a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723599605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
723599605
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.405669563
Short name T373
Test name
Test status
Simulation time 349705573406 ps
CPU time 190.08 seconds
Started Aug 18 05:20:42 PM PDT 24
Finished Aug 18 05:23:52 PM PDT 24
Peak memory 183576 kb
Host smart-f46c3f15-e189-4ff9-9ce0-05eb8c00372b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405669563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.405669563
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3250615487
Short name T421
Test name
Test status
Simulation time 81814593219 ps
CPU time 519.76 seconds
Started Aug 18 05:20:37 PM PDT 24
Finished Aug 18 05:29:17 PM PDT 24
Peak memory 191680 kb
Host smart-e1c41f15-88fb-41f7-b4a0-d21ef5faff69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250615487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3250615487
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3386969762
Short name T336
Test name
Test status
Simulation time 80422220846 ps
CPU time 458.72 seconds
Started Aug 18 05:20:44 PM PDT 24
Finished Aug 18 05:28:23 PM PDT 24
Peak memory 183448 kb
Host smart-ff461b81-b732-46e1-983a-40a77ca04c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386969762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3386969762
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3592892670
Short name T56
Test name
Test status
Simulation time 292489819030 ps
CPU time 228.09 seconds
Started Aug 18 05:20:40 PM PDT 24
Finished Aug 18 05:24:28 PM PDT 24
Peak memory 195212 kb
Host smart-ae0c6f5e-64d3-4ec8-8b71-da02924754e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592892670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3592892670
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.948389457
Short name T13
Test name
Test status
Simulation time 4910544426 ps
CPU time 58 seconds
Started Aug 18 05:20:41 PM PDT 24
Finished Aug 18 05:21:39 PM PDT 24
Peak memory 198288 kb
Host smart-a9c5cd63-8207-461f-9ef2-c784882872e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948389457 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.948389457
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2896051983
Short name T334
Test name
Test status
Simulation time 242677340878 ps
CPU time 345.49 seconds
Started Aug 18 05:20:10 PM PDT 24
Finished Aug 18 05:25:56 PM PDT 24
Peak memory 183456 kb
Host smart-7340c288-a09d-42f2-a8f4-425a0634cd4e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896051983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2896051983
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3015999444
Short name T392
Test name
Test status
Simulation time 321329361851 ps
CPU time 51.27 seconds
Started Aug 18 05:20:06 PM PDT 24
Finished Aug 18 05:20:58 PM PDT 24
Peak memory 183596 kb
Host smart-d9478dc3-a398-4224-b3e5-c98675101b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015999444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3015999444
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.1630450711
Short name T280
Test name
Test status
Simulation time 66765117646 ps
CPU time 109.98 seconds
Started Aug 18 05:20:10 PM PDT 24
Finished Aug 18 05:22:00 PM PDT 24
Peak memory 191720 kb
Host smart-24292273-ef3b-434c-8be3-6a1bcd816400
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630450711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1630450711
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3654049144
Short name T322
Test name
Test status
Simulation time 94186210690 ps
CPU time 43.19 seconds
Started Aug 18 05:20:06 PM PDT 24
Finished Aug 18 05:20:49 PM PDT 24
Peak memory 183596 kb
Host smart-312d4420-6a1e-43c2-9516-098e5d7acefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654049144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3654049144
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3605166278
Short name T19
Test name
Test status
Simulation time 322545889 ps
CPU time 0.96 seconds
Started Aug 18 05:20:07 PM PDT 24
Finished Aug 18 05:20:08 PM PDT 24
Peak memory 214948 kb
Host smart-977644b1-5d88-47d9-8dc8-1f401972ae56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605166278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3605166278
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1560310753
Short name T444
Test name
Test status
Simulation time 1251138565466 ps
CPU time 870.92 seconds
Started Aug 18 05:20:05 PM PDT 24
Finished Aug 18 05:34:36 PM PDT 24
Peak memory 191752 kb
Host smart-c1d2ebf5-ae02-4119-81e8-de315a55fbb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560310753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1560310753
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1523691045
Short name T252
Test name
Test status
Simulation time 488251623852 ps
CPU time 279.93 seconds
Started Aug 18 05:20:44 PM PDT 24
Finished Aug 18 05:25:24 PM PDT 24
Peak memory 183456 kb
Host smart-a64fe676-1bbb-4cc6-9e16-436110557aec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523691045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1523691045
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1598724771
Short name T386
Test name
Test status
Simulation time 316363437987 ps
CPU time 241.88 seconds
Started Aug 18 05:20:41 PM PDT 24
Finished Aug 18 05:24:43 PM PDT 24
Peak memory 183452 kb
Host smart-15110896-b30e-4c38-932a-22ffc70392a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598724771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1598724771
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3999557550
Short name T348
Test name
Test status
Simulation time 136539182391 ps
CPU time 135.86 seconds
Started Aug 18 05:20:40 PM PDT 24
Finished Aug 18 05:22:56 PM PDT 24
Peak memory 191656 kb
Host smart-bac65b77-a8b3-40e3-a082-8168c94b330d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999557550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3999557550
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3877964884
Short name T445
Test name
Test status
Simulation time 15104634458 ps
CPU time 12.37 seconds
Started Aug 18 05:20:41 PM PDT 24
Finished Aug 18 05:20:53 PM PDT 24
Peak memory 183520 kb
Host smart-1767650b-9e18-4b7a-b1d7-74cd0f19abf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877964884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3877964884
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3496010495
Short name T275
Test name
Test status
Simulation time 615300881430 ps
CPU time 1040.75 seconds
Started Aug 18 05:20:42 PM PDT 24
Finished Aug 18 05:38:03 PM PDT 24
Peak memory 191728 kb
Host smart-e4c45e94-a48c-49fa-8517-37e717eb061a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496010495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3496010495
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2686390282
Short name T144
Test name
Test status
Simulation time 515783658098 ps
CPU time 774.72 seconds
Started Aug 18 05:20:39 PM PDT 24
Finished Aug 18 05:33:34 PM PDT 24
Peak memory 183572 kb
Host smart-e6605435-52c5-4ce8-913c-a9ae55e34fba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686390282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2686390282
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.500009047
Short name T383
Test name
Test status
Simulation time 97159544580 ps
CPU time 157.55 seconds
Started Aug 18 05:20:39 PM PDT 24
Finished Aug 18 05:23:17 PM PDT 24
Peak memory 183564 kb
Host smart-234908ad-c2e1-4ae5-8220-a6cbf118f2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500009047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.500009047
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1714312897
Short name T126
Test name
Test status
Simulation time 153141611642 ps
CPU time 687.73 seconds
Started Aug 18 05:20:39 PM PDT 24
Finished Aug 18 05:32:07 PM PDT 24
Peak memory 191700 kb
Host smart-9b0d25d2-4536-420a-b0c8-55661b7577a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714312897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1714312897
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2998843319
Short name T328
Test name
Test status
Simulation time 209108279434 ps
CPU time 53.58 seconds
Started Aug 18 05:20:40 PM PDT 24
Finished Aug 18 05:21:34 PM PDT 24
Peak memory 191784 kb
Host smart-57f2a976-bb93-4553-b3f3-3074c7c11916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998843319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2998843319
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.4166837226
Short name T287
Test name
Test status
Simulation time 626101636381 ps
CPU time 716.96 seconds
Started Aug 18 05:20:41 PM PDT 24
Finished Aug 18 05:32:39 PM PDT 24
Peak memory 191760 kb
Host smart-52adaa41-4bac-4083-bd50-d61e1fff11fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166837226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.4166837226
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.671630956
Short name T201
Test name
Test status
Simulation time 395545431923 ps
CPU time 688.34 seconds
Started Aug 18 05:20:44 PM PDT 24
Finished Aug 18 05:32:12 PM PDT 24
Peak memory 183504 kb
Host smart-d8349631-5247-4525-8603-f78f01b4ce7c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671630956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.671630956
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3952797418
Short name T434
Test name
Test status
Simulation time 413738387853 ps
CPU time 174.96 seconds
Started Aug 18 05:20:41 PM PDT 24
Finished Aug 18 05:23:36 PM PDT 24
Peak memory 183576 kb
Host smart-171bd199-a8ac-4b43-9e46-779b101988a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952797418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3952797418
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1934538638
Short name T169
Test name
Test status
Simulation time 93097102550 ps
CPU time 48.07 seconds
Started Aug 18 05:20:41 PM PDT 24
Finished Aug 18 05:21:29 PM PDT 24
Peak memory 183532 kb
Host smart-871ab5b0-428d-49ce-a80b-cc15bcf2826d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934538638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1934538638
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3160146953
Short name T297
Test name
Test status
Simulation time 18420120942 ps
CPU time 170.19 seconds
Started Aug 18 05:20:47 PM PDT 24
Finished Aug 18 05:23:37 PM PDT 24
Peak memory 195120 kb
Host smart-4ecaf0a2-a923-40f4-a990-ae21da4bca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160146953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3160146953
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2227100021
Short name T367
Test name
Test status
Simulation time 213919541041 ps
CPU time 366.26 seconds
Started Aug 18 05:20:41 PM PDT 24
Finished Aug 18 05:26:47 PM PDT 24
Peak memory 191736 kb
Host smart-2ebbcb97-7493-4dbc-9b47-acfc9012be54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227100021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2227100021
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.479207120
Short name T337
Test name
Test status
Simulation time 43129635307 ps
CPU time 24.74 seconds
Started Aug 18 05:20:42 PM PDT 24
Finished Aug 18 05:21:07 PM PDT 24
Peak memory 183600 kb
Host smart-99fb19ec-8856-4315-ac8e-dd66da9a5697
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479207120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.479207120
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1705908290
Short name T440
Test name
Test status
Simulation time 197968402421 ps
CPU time 80.5 seconds
Started Aug 18 05:20:43 PM PDT 24
Finished Aug 18 05:22:04 PM PDT 24
Peak memory 183328 kb
Host smart-f25deedb-bb30-4427-9751-7a196ad9bed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705908290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1705908290
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3695577093
Short name T141
Test name
Test status
Simulation time 388909738565 ps
CPU time 405.56 seconds
Started Aug 18 05:20:40 PM PDT 24
Finished Aug 18 05:27:25 PM PDT 24
Peak memory 191744 kb
Host smart-cebd8ccd-0de9-4303-92dc-49f2db255226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695577093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3695577093
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1247602485
Short name T36
Test name
Test status
Simulation time 923173125661 ps
CPU time 283.91 seconds
Started Aug 18 05:20:43 PM PDT 24
Finished Aug 18 05:25:27 PM PDT 24
Peak memory 195400 kb
Host smart-6a8b214d-48b0-408d-8416-3aed53111760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247602485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1247602485
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.541164975
Short name T142
Test name
Test status
Simulation time 313778087762 ps
CPU time 65.27 seconds
Started Aug 18 05:20:43 PM PDT 24
Finished Aug 18 05:21:48 PM PDT 24
Peak memory 195680 kb
Host smart-5fb73479-71ee-4bfe-9f42-1ac6e0af78eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541164975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
541164975
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.157081788
Short name T320
Test name
Test status
Simulation time 28284436885 ps
CPU time 44.88 seconds
Started Aug 18 05:20:45 PM PDT 24
Finished Aug 18 05:21:30 PM PDT 24
Peak memory 183492 kb
Host smart-ee68473b-0632-45fd-91ad-1835f5440d66
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157081788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.157081788
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2353442387
Short name T387
Test name
Test status
Simulation time 186164126686 ps
CPU time 75.81 seconds
Started Aug 18 05:20:41 PM PDT 24
Finished Aug 18 05:21:57 PM PDT 24
Peak memory 183468 kb
Host smart-07b021d8-ce67-4690-96b6-f61ae5a8c27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353442387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2353442387
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.83367863
Short name T115
Test name
Test status
Simulation time 203416996194 ps
CPU time 196.89 seconds
Started Aug 18 05:20:43 PM PDT 24
Finished Aug 18 05:24:00 PM PDT 24
Peak memory 183296 kb
Host smart-74a3105f-3664-47f5-8676-53cd5a929bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83367863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.83367863
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3856872674
Short name T346
Test name
Test status
Simulation time 823485852790 ps
CPU time 402.7 seconds
Started Aug 18 05:20:41 PM PDT 24
Finished Aug 18 05:27:24 PM PDT 24
Peak memory 183584 kb
Host smart-0e14b717-f3ef-4704-bf51-ed9ab80eae72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856872674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3856872674
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2302399862
Short name T447
Test name
Test status
Simulation time 70567857629 ps
CPU time 27.53 seconds
Started Aug 18 05:20:42 PM PDT 24
Finished Aug 18 05:21:09 PM PDT 24
Peak memory 183476 kb
Host smart-c4de1ff3-7efa-46f1-94fd-7e1e48b10be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302399862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2302399862
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.566017245
Short name T321
Test name
Test status
Simulation time 93404186116 ps
CPU time 77.3 seconds
Started Aug 18 05:20:45 PM PDT 24
Finished Aug 18 05:22:03 PM PDT 24
Peak memory 183520 kb
Host smart-a404e5fd-5cc4-4a36-b39a-caa6a6c85cf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566017245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.566017245
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1848453075
Short name T108
Test name
Test status
Simulation time 37505803126 ps
CPU time 64.08 seconds
Started Aug 18 05:20:40 PM PDT 24
Finished Aug 18 05:21:44 PM PDT 24
Peak memory 191700 kb
Host smart-3804ae7b-214c-4bb1-b249-020d0490f81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848453075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1848453075
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1227341509
Short name T400
Test name
Test status
Simulation time 255675503321 ps
CPU time 171.94 seconds
Started Aug 18 05:20:43 PM PDT 24
Finished Aug 18 05:23:35 PM PDT 24
Peak memory 183576 kb
Host smart-0af16733-154c-428a-acfc-76286f600e6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227341509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1227341509
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2586158017
Short name T256
Test name
Test status
Simulation time 191463925483 ps
CPU time 323.62 seconds
Started Aug 18 05:20:52 PM PDT 24
Finished Aug 18 05:26:16 PM PDT 24
Peak memory 183560 kb
Host smart-dab8c796-bb51-4916-867c-cef9d5cb9162
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586158017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2586158017
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1049454714
Short name T398
Test name
Test status
Simulation time 565124019513 ps
CPU time 135.85 seconds
Started Aug 18 05:20:54 PM PDT 24
Finished Aug 18 05:23:10 PM PDT 24
Peak memory 183484 kb
Host smart-3ad4efc3-274b-4a4d-8b07-d1027b216a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049454714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1049454714
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3863237325
Short name T342
Test name
Test status
Simulation time 152617243730 ps
CPU time 348.75 seconds
Started Aug 18 05:20:52 PM PDT 24
Finished Aug 18 05:26:41 PM PDT 24
Peak memory 191764 kb
Host smart-06c819d3-5920-47d5-9d16-4c90c6692b10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863237325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3863237325
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2841421620
Short name T310
Test name
Test status
Simulation time 999405271 ps
CPU time 8.82 seconds
Started Aug 18 05:20:52 PM PDT 24
Finished Aug 18 05:21:01 PM PDT 24
Peak memory 183424 kb
Host smart-4bdaa42f-cdd7-4f76-a623-c0a1140d498b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841421620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2841421620
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.14955010
Short name T416
Test name
Test status
Simulation time 118355393034 ps
CPU time 170.6 seconds
Started Aug 18 05:20:54 PM PDT 24
Finished Aug 18 05:23:45 PM PDT 24
Peak memory 183484 kb
Host smart-7aa46a49-bbd3-467b-a63d-3664d68bd5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14955010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.14955010
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.722897674
Short name T189
Test name
Test status
Simulation time 112685660760 ps
CPU time 79.31 seconds
Started Aug 18 05:20:54 PM PDT 24
Finished Aug 18 05:22:13 PM PDT 24
Peak memory 191672 kb
Host smart-30643bbc-10ef-4246-91b6-b4f3261bb930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722897674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.722897674
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.854930708
Short name T366
Test name
Test status
Simulation time 49690569229 ps
CPU time 76.41 seconds
Started Aug 18 05:20:52 PM PDT 24
Finished Aug 18 05:22:09 PM PDT 24
Peak memory 183572 kb
Host smart-6ee38651-7593-42e3-bf36-56e72e35ad7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854930708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.854930708
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.519125912
Short name T183
Test name
Test status
Simulation time 29744233415 ps
CPU time 49.17 seconds
Started Aug 18 05:20:52 PM PDT 24
Finished Aug 18 05:21:42 PM PDT 24
Peak memory 183452 kb
Host smart-ce4ac098-c7c3-49b5-a721-fa5a5f40daf3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519125912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.519125912
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.535101698
Short name T423
Test name
Test status
Simulation time 237332049706 ps
CPU time 95.47 seconds
Started Aug 18 05:20:52 PM PDT 24
Finished Aug 18 05:22:27 PM PDT 24
Peak memory 183536 kb
Host smart-cb15be78-42da-434a-ba09-5447f6718a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535101698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.535101698
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1931060933
Short name T333
Test name
Test status
Simulation time 28617785535 ps
CPU time 12.55 seconds
Started Aug 18 05:20:57 PM PDT 24
Finished Aug 18 05:21:10 PM PDT 24
Peak memory 191676 kb
Host smart-1c7eac69-1ada-423b-9dc8-8d805069bc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931060933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1931060933
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2398783376
Short name T384
Test name
Test status
Simulation time 191076950704 ps
CPU time 140.54 seconds
Started Aug 18 05:20:55 PM PDT 24
Finished Aug 18 05:23:15 PM PDT 24
Peak memory 183584 kb
Host smart-6a822184-5c11-4146-8a2d-9f91b6ab2043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398783376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2398783376
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.911902881
Short name T50
Test name
Test status
Simulation time 309123698640 ps
CPU time 217.59 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:24:31 PM PDT 24
Peak memory 183476 kb
Host smart-f50f57fc-4c58-40a4-80dc-4e672ecc4341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911902881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
911902881
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1854657594
Short name T430
Test name
Test status
Simulation time 366801735626 ps
CPU time 138.7 seconds
Started Aug 18 05:20:10 PM PDT 24
Finished Aug 18 05:22:29 PM PDT 24
Peak memory 183372 kb
Host smart-ef984fd5-a5da-4d78-a3d6-94f2b3c62f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854657594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1854657594
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3736923484
Short name T452
Test name
Test status
Simulation time 612851767750 ps
CPU time 374.23 seconds
Started Aug 18 05:20:06 PM PDT 24
Finished Aug 18 05:26:21 PM PDT 24
Peak memory 191812 kb
Host smart-287d249c-5fff-40e9-adbf-bf98f050f48c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736923484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3736923484
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3928894296
Short name T403
Test name
Test status
Simulation time 771633304 ps
CPU time 1.85 seconds
Started Aug 18 05:20:13 PM PDT 24
Finished Aug 18 05:20:15 PM PDT 24
Peak memory 192024 kb
Host smart-45b51f11-7236-41e4-a84a-c32d5757a8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928894296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3928894296
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.4192506354
Short name T18
Test name
Test status
Simulation time 132258317 ps
CPU time 0.84 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:20:15 PM PDT 24
Peak memory 213920 kb
Host smart-94a2ceaa-7309-424d-8fa0-98a7599f8f44
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192506354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.4192506354
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2955589751
Short name T277
Test name
Test status
Simulation time 9304243133 ps
CPU time 15.83 seconds
Started Aug 18 05:20:54 PM PDT 24
Finished Aug 18 05:21:10 PM PDT 24
Peak memory 183516 kb
Host smart-5c24fa40-2d37-468e-be91-680c00271f13
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955589751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2955589751
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1328357633
Short name T399
Test name
Test status
Simulation time 71365781556 ps
CPU time 104.14 seconds
Started Aug 18 05:20:52 PM PDT 24
Finished Aug 18 05:22:37 PM PDT 24
Peak memory 183500 kb
Host smart-959333f2-f05c-4e68-a027-a29557b6082c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328357633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1328357633
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2432431642
Short name T339
Test name
Test status
Simulation time 115550903321 ps
CPU time 89.12 seconds
Started Aug 18 05:20:52 PM PDT 24
Finished Aug 18 05:22:22 PM PDT 24
Peak memory 183564 kb
Host smart-8fc7c3e2-ebd8-4700-8d96-56dcb4b656cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432431642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2432431642
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2122620026
Short name T136
Test name
Test status
Simulation time 743913793935 ps
CPU time 346.73 seconds
Started Aug 18 05:20:52 PM PDT 24
Finished Aug 18 05:26:39 PM PDT 24
Peak memory 183564 kb
Host smart-406ab2fb-e2fe-4ed2-a60c-9583fa3593ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122620026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2122620026
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1645977368
Short name T406
Test name
Test status
Simulation time 98350947788 ps
CPU time 76.48 seconds
Started Aug 18 05:21:00 PM PDT 24
Finished Aug 18 05:22:17 PM PDT 24
Peak memory 183592 kb
Host smart-0e283926-1522-49b8-b9c5-ab2da340bde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645977368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1645977368
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3730887341
Short name T270
Test name
Test status
Simulation time 142543521516 ps
CPU time 185.11 seconds
Started Aug 18 05:20:56 PM PDT 24
Finished Aug 18 05:24:01 PM PDT 24
Peak memory 191808 kb
Host smart-1746d387-c375-476a-bc1e-2d9d4da6ea2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730887341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3730887341
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3368788883
Short name T393
Test name
Test status
Simulation time 357728839 ps
CPU time 0.71 seconds
Started Aug 18 05:20:56 PM PDT 24
Finished Aug 18 05:20:57 PM PDT 24
Peak memory 183420 kb
Host smart-deca8130-c683-4509-93e0-08bb839c98d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368788883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3368788883
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2033179451
Short name T58
Test name
Test status
Simulation time 93571319 ps
CPU time 0.69 seconds
Started Aug 18 05:20:58 PM PDT 24
Finished Aug 18 05:20:59 PM PDT 24
Peak memory 183168 kb
Host smart-f4de3b02-3662-412e-9545-446a8ee9a54d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033179451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2033179451
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.1040881815
Short name T439
Test name
Test status
Simulation time 5508845771 ps
CPU time 58.53 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:21:52 PM PDT 24
Peak memory 198256 kb
Host smart-d199f32e-4e9c-4862-bbd8-b1f236210425
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040881815 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.1040881815
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2072193376
Short name T120
Test name
Test status
Simulation time 1006629048856 ps
CPU time 537.16 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:29:51 PM PDT 24
Peak memory 183528 kb
Host smart-26f63c5d-2787-4ed7-94ec-c2b0c7cfbe69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072193376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2072193376
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.340445196
Short name T377
Test name
Test status
Simulation time 58329660403 ps
CPU time 90.33 seconds
Started Aug 18 05:20:54 PM PDT 24
Finished Aug 18 05:22:24 PM PDT 24
Peak memory 183564 kb
Host smart-9fc39aa7-7f83-41dd-ade2-98adb8355963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340445196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.340445196
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2773885548
Short name T316
Test name
Test status
Simulation time 152655529393 ps
CPU time 109.36 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:22:43 PM PDT 24
Peak memory 191680 kb
Host smart-2a5a2882-629e-4fda-8d25-859dfba04b3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773885548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2773885548
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.819102163
Short name T446
Test name
Test status
Simulation time 83980501781 ps
CPU time 48.81 seconds
Started Aug 18 05:20:54 PM PDT 24
Finished Aug 18 05:21:43 PM PDT 24
Peak memory 194980 kb
Host smart-ce4dbaea-4b10-4a8c-931a-0fc456bab823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819102163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.819102163
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2983882964
Short name T191
Test name
Test status
Simulation time 1051262061972 ps
CPU time 679.31 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:32:13 PM PDT 24
Peak memory 191700 kb
Host smart-9093befc-3a67-4750-978a-f0d79b4a1700
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983882964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2983882964
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3291001226
Short name T278
Test name
Test status
Simulation time 7515592180 ps
CPU time 12.44 seconds
Started Aug 18 05:20:55 PM PDT 24
Finished Aug 18 05:21:08 PM PDT 24
Peak memory 183544 kb
Host smart-fd33d8a0-4a3c-4769-aa8b-25886fca4889
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291001226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3291001226
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.364688013
Short name T380
Test name
Test status
Simulation time 186825915778 ps
CPU time 147.66 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:23:21 PM PDT 24
Peak memory 183544 kb
Host smart-03da48a8-cac8-44f0-9eab-a4c7304c4680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364688013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.364688013
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.804467791
Short name T117
Test name
Test status
Simulation time 175470142172 ps
CPU time 443.23 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:28:17 PM PDT 24
Peak memory 191752 kb
Host smart-fe1ab949-aaed-493c-81f7-6c21411fdcbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804467791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.804467791
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2516090799
Short name T159
Test name
Test status
Simulation time 151628336464 ps
CPU time 88.69 seconds
Started Aug 18 05:20:56 PM PDT 24
Finished Aug 18 05:22:25 PM PDT 24
Peak memory 183572 kb
Host smart-3f6c24c9-3395-4926-a348-c449ac57bdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516090799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2516090799
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2084276920
Short name T39
Test name
Test status
Simulation time 7360480456 ps
CPU time 13.57 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:21:07 PM PDT 24
Peak memory 183556 kb
Host smart-92ee007a-c285-4732-8f05-77097efa7648
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084276920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2084276920
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1271778716
Short name T437
Test name
Test status
Simulation time 407020295822 ps
CPU time 144.02 seconds
Started Aug 18 05:20:55 PM PDT 24
Finished Aug 18 05:23:19 PM PDT 24
Peak memory 183592 kb
Host smart-95a83b95-7f68-472d-b474-d2bed0db4a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271778716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1271778716
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.815925746
Short name T213
Test name
Test status
Simulation time 21357867302 ps
CPU time 42.76 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:21:35 PM PDT 24
Peak memory 191764 kb
Host smart-bb9f9a45-2c74-421e-a2d5-e7e74b15f727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815925746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.815925746
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.420103120
Short name T274
Test name
Test status
Simulation time 354058886117 ps
CPU time 252.99 seconds
Started Aug 18 05:20:54 PM PDT 24
Finished Aug 18 05:25:07 PM PDT 24
Peak memory 191652 kb
Host smart-ccd856a9-4a64-47d5-800c-79167a84eb41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420103120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.420103120
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.218572205
Short name T205
Test name
Test status
Simulation time 5102123026958 ps
CPU time 1111.64 seconds
Started Aug 18 05:20:59 PM PDT 24
Finished Aug 18 05:39:31 PM PDT 24
Peak memory 183596 kb
Host smart-33461aab-de80-4a5e-afd2-789f741b89c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218572205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.218572205
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.612297922
Short name T443
Test name
Test status
Simulation time 324865744522 ps
CPU time 154.32 seconds
Started Aug 18 05:20:55 PM PDT 24
Finished Aug 18 05:23:29 PM PDT 24
Peak memory 183552 kb
Host smart-389e03fd-9f94-4e04-8907-718902e658ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612297922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.612297922
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.4181314044
Short name T426
Test name
Test status
Simulation time 130162824447 ps
CPU time 501.3 seconds
Started Aug 18 05:20:55 PM PDT 24
Finished Aug 18 05:29:16 PM PDT 24
Peak memory 183572 kb
Host smart-6e04de6a-e86d-4375-9987-05b8fee7bf40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181314044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.4181314044
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2671475106
Short name T431
Test name
Test status
Simulation time 209567664 ps
CPU time 1.53 seconds
Started Aug 18 05:20:56 PM PDT 24
Finished Aug 18 05:20:57 PM PDT 24
Peak memory 183612 kb
Host smart-8c946d2d-2206-4541-ae61-5292ea8a928c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671475106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2671475106
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3005781326
Short name T7
Test name
Test status
Simulation time 826903256904 ps
CPU time 493.46 seconds
Started Aug 18 05:20:54 PM PDT 24
Finished Aug 18 05:29:07 PM PDT 24
Peak memory 183564 kb
Host smart-7192a70a-2371-4cd1-a7a5-da0fce9e6a7a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005781326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3005781326
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2890771538
Short name T404
Test name
Test status
Simulation time 44288348107 ps
CPU time 36.43 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:21:30 PM PDT 24
Peak memory 183484 kb
Host smart-f16ee902-4dfc-4307-bc8c-8c7099170ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890771538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2890771538
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.832393696
Short name T319
Test name
Test status
Simulation time 16827310386 ps
CPU time 26.93 seconds
Started Aug 18 05:21:00 PM PDT 24
Finished Aug 18 05:21:27 PM PDT 24
Peak memory 183620 kb
Host smart-b33a292b-ab69-4ec6-84b6-3864ca2ed47a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832393696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.832393696
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1440967996
Short name T364
Test name
Test status
Simulation time 134613637073 ps
CPU time 86.86 seconds
Started Aug 18 05:20:54 PM PDT 24
Finished Aug 18 05:22:21 PM PDT 24
Peak memory 183452 kb
Host smart-551dab34-891f-4345-a7f1-ea87d182103f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440967996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1440967996
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2978386298
Short name T147
Test name
Test status
Simulation time 1767511028800 ps
CPU time 1942.83 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:53:17 PM PDT 24
Peak memory 191728 kb
Host smart-fb9a75db-6870-40e6-af67-778728d4caab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978386298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2978386298
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1876961519
Short name T155
Test name
Test status
Simulation time 535124730276 ps
CPU time 294.34 seconds
Started Aug 18 05:20:56 PM PDT 24
Finished Aug 18 05:25:51 PM PDT 24
Peak memory 183720 kb
Host smart-c8242943-0b96-49a8-83b9-a14e5fc1be56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876961519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1876961519
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.330188380
Short name T382
Test name
Test status
Simulation time 371510656234 ps
CPU time 144.91 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:23:19 PM PDT 24
Peak memory 183608 kb
Host smart-6c843cc4-b673-4d00-90d4-f96ea6f2e15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330188380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.330188380
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.798941510
Short name T151
Test name
Test status
Simulation time 75862174430 ps
CPU time 133.11 seconds
Started Aug 18 05:20:55 PM PDT 24
Finished Aug 18 05:23:08 PM PDT 24
Peak memory 191800 kb
Host smart-30721398-d035-480a-8eab-28f6193d354f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798941510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.798941510
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3041584209
Short name T417
Test name
Test status
Simulation time 1230955433 ps
CPU time 2.38 seconds
Started Aug 18 05:20:54 PM PDT 24
Finished Aug 18 05:20:57 PM PDT 24
Peak memory 183248 kb
Host smart-9cacdf4e-808c-4e53-a6f5-d95b47838274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041584209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3041584209
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1391471811
Short name T308
Test name
Test status
Simulation time 206696071185 ps
CPU time 161.47 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:23:35 PM PDT 24
Peak memory 183592 kb
Host smart-6ebc924b-48ea-4708-ab60-a04aa0728404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391471811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1391471811
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3151275138
Short name T401
Test name
Test status
Simulation time 73148585870 ps
CPU time 112.69 seconds
Started Aug 18 05:21:00 PM PDT 24
Finished Aug 18 05:22:52 PM PDT 24
Peak memory 183480 kb
Host smart-4547094a-46f7-4192-8b2a-4b710db22104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151275138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3151275138
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2977678586
Short name T124
Test name
Test status
Simulation time 39200212841 ps
CPU time 61.32 seconds
Started Aug 18 05:20:53 PM PDT 24
Finished Aug 18 05:21:55 PM PDT 24
Peak memory 183480 kb
Host smart-b04f7373-ba1a-4d71-b417-b742b4e9b4cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977678586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2977678586
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.4080107980
Short name T456
Test name
Test status
Simulation time 219654333225 ps
CPU time 143.46 seconds
Started Aug 18 05:21:03 PM PDT 24
Finished Aug 18 05:23:26 PM PDT 24
Peak memory 191664 kb
Host smart-1eb3b0d5-dc71-4353-aa0d-f1e8abdeb0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080107980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.4080107980
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all_with_rand_reset.2976186074
Short name T29
Test name
Test status
Simulation time 5184174084 ps
CPU time 34.82 seconds
Started Aug 18 05:21:08 PM PDT 24
Finished Aug 18 05:21:43 PM PDT 24
Peak memory 195120 kb
Host smart-185654af-cc38-4d42-b1f9-890fa8b33388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976186074 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all_with_rand_reset.2976186074
Directory /workspace/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2860165255
Short name T358
Test name
Test status
Simulation time 2520864528843 ps
CPU time 896.99 seconds
Started Aug 18 05:21:02 PM PDT 24
Finished Aug 18 05:35:59 PM PDT 24
Peak memory 183572 kb
Host smart-bb8f511e-10b9-4d54-be14-b47d87c43516
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860165255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2860165255
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3232756037
Short name T425
Test name
Test status
Simulation time 37939031984 ps
CPU time 53.09 seconds
Started Aug 18 05:21:02 PM PDT 24
Finished Aug 18 05:21:55 PM PDT 24
Peak memory 183576 kb
Host smart-7523c230-674a-4325-b4d1-f90e4d09dfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232756037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3232756037
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1402632727
Short name T271
Test name
Test status
Simulation time 461558556155 ps
CPU time 191.39 seconds
Started Aug 18 05:21:01 PM PDT 24
Finished Aug 18 05:24:12 PM PDT 24
Peak memory 191732 kb
Host smart-fa5023d7-0bae-4867-bf97-fd7d15656ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402632727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1402632727
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2875709352
Short name T411
Test name
Test status
Simulation time 48487365017 ps
CPU time 85.58 seconds
Started Aug 18 05:21:01 PM PDT 24
Finished Aug 18 05:22:27 PM PDT 24
Peak memory 193892 kb
Host smart-6f827d77-016f-40e0-a099-d98428e150b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875709352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2875709352
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2291279813
Short name T269
Test name
Test status
Simulation time 1311233070712 ps
CPU time 589.8 seconds
Started Aug 18 05:20:59 PM PDT 24
Finished Aug 18 05:30:49 PM PDT 24
Peak memory 191712 kb
Host smart-6b15d7e1-61eb-4b45-af89-9b02412472c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291279813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2291279813
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1023089776
Short name T178
Test name
Test status
Simulation time 107354389477 ps
CPU time 188.25 seconds
Started Aug 18 05:20:15 PM PDT 24
Finished Aug 18 05:23:23 PM PDT 24
Peak memory 183488 kb
Host smart-9dcd791f-1198-45f7-8dda-15a6d991a622
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023089776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1023089776
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1145912835
Short name T379
Test name
Test status
Simulation time 40887660682 ps
CPU time 59.69 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:21:14 PM PDT 24
Peak memory 183500 kb
Host smart-ba9cc117-bb38-4862-bad7-13e6a71e2f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145912835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1145912835
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3844525744
Short name T90
Test name
Test status
Simulation time 36966641800 ps
CPU time 242.19 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:24:17 PM PDT 24
Peak memory 191808 kb
Host smart-13bf4fb6-6240-465b-9d2b-084e3cbb6203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844525744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3844525744
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3727825272
Short name T225
Test name
Test status
Simulation time 599051405890 ps
CPU time 624.07 seconds
Started Aug 18 05:20:12 PM PDT 24
Finished Aug 18 05:30:36 PM PDT 24
Peak memory 183500 kb
Host smart-c3308a4d-c17a-4ffc-847c-fda92a5dabce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727825272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3727825272
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.656537529
Short name T30
Test name
Test status
Simulation time 19326175133 ps
CPU time 42.18 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:20:57 PM PDT 24
Peak memory 198272 kb
Host smart-964e5105-92a1-4b9c-8542-463ad342732d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656537529 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.656537529
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.2906631688
Short name T304
Test name
Test status
Simulation time 13401378270 ps
CPU time 23.32 seconds
Started Aug 18 05:21:07 PM PDT 24
Finished Aug 18 05:21:30 PM PDT 24
Peak memory 182420 kb
Host smart-dc73e66e-513e-4146-af97-9981fcc3b5b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906631688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2906631688
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.840990208
Short name T130
Test name
Test status
Simulation time 94259528279 ps
CPU time 188.44 seconds
Started Aug 18 05:21:05 PM PDT 24
Finished Aug 18 05:24:14 PM PDT 24
Peak memory 191680 kb
Host smart-bbdee1f2-d5a0-4a6d-bd64-4c1db0d697d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840990208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.840990208
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2129137563
Short name T172
Test name
Test status
Simulation time 80323929483 ps
CPU time 170.54 seconds
Started Aug 18 05:21:06 PM PDT 24
Finished Aug 18 05:23:57 PM PDT 24
Peak memory 191780 kb
Host smart-03a8ee00-5158-46f6-ab33-30097f191f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129137563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2129137563
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.561999969
Short name T427
Test name
Test status
Simulation time 234485489032 ps
CPU time 195.75 seconds
Started Aug 18 05:21:02 PM PDT 24
Finished Aug 18 05:24:17 PM PDT 24
Peak memory 191724 kb
Host smart-f1a1c5a1-dd7e-48bf-ba83-534054894ede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561999969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.561999969
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2063680246
Short name T441
Test name
Test status
Simulation time 178408943309 ps
CPU time 218.94 seconds
Started Aug 18 05:21:08 PM PDT 24
Finished Aug 18 05:24:47 PM PDT 24
Peak memory 183580 kb
Host smart-82ace4d4-a446-4d91-8c0f-602aede07f32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063680246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2063680246
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.911118406
Short name T353
Test name
Test status
Simulation time 49393147132 ps
CPU time 160.62 seconds
Started Aug 18 05:21:01 PM PDT 24
Finished Aug 18 05:23:42 PM PDT 24
Peak memory 191652 kb
Host smart-59d207fe-6342-4b4d-8d57-cbf3346ecfef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911118406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.911118406
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1917713696
Short name T255
Test name
Test status
Simulation time 50196133105 ps
CPU time 66.97 seconds
Started Aug 18 05:21:04 PM PDT 24
Finished Aug 18 05:22:11 PM PDT 24
Peak memory 183544 kb
Host smart-edc4021c-9bc6-45e5-8122-ad7b277ba8a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917713696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1917713696
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2487820023
Short name T258
Test name
Test status
Simulation time 115349403519 ps
CPU time 94.84 seconds
Started Aug 18 05:20:17 PM PDT 24
Finished Aug 18 05:21:52 PM PDT 24
Peak memory 183548 kb
Host smart-6130499f-a335-4057-a774-5caeb9c9c174
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487820023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2487820023
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_random.2395082089
Short name T21
Test name
Test status
Simulation time 121098532290 ps
CPU time 309.7 seconds
Started Aug 18 05:20:15 PM PDT 24
Finished Aug 18 05:25:25 PM PDT 24
Peak memory 183496 kb
Host smart-6faca4ac-00df-4908-9d84-593e90191386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395082089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2395082089
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1249108896
Short name T433
Test name
Test status
Simulation time 654366815 ps
CPU time 0.66 seconds
Started Aug 18 05:20:16 PM PDT 24
Finished Aug 18 05:20:17 PM PDT 24
Peak memory 183264 kb
Host smart-ffc6cc04-3525-4c2f-962b-eb992585b3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249108896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1249108896
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3192454025
Short name T414
Test name
Test status
Simulation time 157350900784 ps
CPU time 130.76 seconds
Started Aug 18 05:20:18 PM PDT 24
Finished Aug 18 05:22:29 PM PDT 24
Peak memory 191768 kb
Host smart-98b76b9f-04af-4d0d-b893-ad2bc3088560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192454025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3192454025
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/61.rv_timer_random.3035910307
Short name T222
Test name
Test status
Simulation time 621624223919 ps
CPU time 316.93 seconds
Started Aug 18 05:21:06 PM PDT 24
Finished Aug 18 05:26:23 PM PDT 24
Peak memory 191668 kb
Host smart-ef5c8991-7d03-461e-87c5-2fbf91793719
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035910307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3035910307
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1404160649
Short name T200
Test name
Test status
Simulation time 215617495262 ps
CPU time 122.91 seconds
Started Aug 18 05:21:02 PM PDT 24
Finished Aug 18 05:23:05 PM PDT 24
Peak memory 191720 kb
Host smart-97652bb8-7016-4867-b338-42eb5c551be3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404160649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1404160649
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2739772825
Short name T451
Test name
Test status
Simulation time 106324859466 ps
CPU time 211.1 seconds
Started Aug 18 05:21:06 PM PDT 24
Finished Aug 18 05:24:38 PM PDT 24
Peak memory 189704 kb
Host smart-e2094d1f-e4f0-448a-aae5-5f73a17ddd95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739772825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2739772825
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1802422109
Short name T220
Test name
Test status
Simulation time 84294839206 ps
CPU time 55.58 seconds
Started Aug 18 05:21:02 PM PDT 24
Finished Aug 18 05:21:58 PM PDT 24
Peak memory 183472 kb
Host smart-420c609c-bac3-4a33-bd84-6d0990e1a3f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802422109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1802422109
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.4058444800
Short name T179
Test name
Test status
Simulation time 105211089305 ps
CPU time 98.29 seconds
Started Aug 18 05:21:03 PM PDT 24
Finished Aug 18 05:22:41 PM PDT 24
Peak memory 191672 kb
Host smart-38e497f3-e7fe-41bc-babb-3fa3079c9737
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058444800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.4058444800
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3369978256
Short name T114
Test name
Test status
Simulation time 156088310509 ps
CPU time 324.51 seconds
Started Aug 18 05:21:06 PM PDT 24
Finished Aug 18 05:26:30 PM PDT 24
Peak memory 191680 kb
Host smart-82f0e326-456f-4c55-b171-46b4ebd3bbb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369978256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3369978256
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.739257652
Short name T244
Test name
Test status
Simulation time 109070783443 ps
CPU time 340.17 seconds
Started Aug 18 05:21:02 PM PDT 24
Finished Aug 18 05:26:43 PM PDT 24
Peak memory 191800 kb
Host smart-2c80b01a-67fc-4454-a87a-8eaf0ef7147a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739257652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.739257652
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3457931103
Short name T113
Test name
Test status
Simulation time 581564360148 ps
CPU time 241.22 seconds
Started Aug 18 05:21:01 PM PDT 24
Finished Aug 18 05:25:02 PM PDT 24
Peak memory 191808 kb
Host smart-5f5718c8-274b-4f8e-81e5-591c369ea502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457931103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3457931103
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1842554522
Short name T394
Test name
Test status
Simulation time 256434237163 ps
CPU time 146.8 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:22:41 PM PDT 24
Peak memory 183496 kb
Host smart-7595eba6-a548-4e4b-9233-c656867886d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842554522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1842554522
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.980045180
Short name T371
Test name
Test status
Simulation time 302825883339 ps
CPU time 222.37 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:24:01 PM PDT 24
Peak memory 183460 kb
Host smart-be914112-5a10-41ad-aaa6-8952314a3015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980045180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.980045180
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2616086857
Short name T231
Test name
Test status
Simulation time 236161594108 ps
CPU time 593.55 seconds
Started Aug 18 05:20:19 PM PDT 24
Finished Aug 18 05:30:12 PM PDT 24
Peak memory 191772 kb
Host smart-3c6ea150-173b-4480-b686-4b00e1c35060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616086857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2616086857
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1393659610
Short name T129
Test name
Test status
Simulation time 251981648330 ps
CPU time 115.56 seconds
Started Aug 18 05:20:15 PM PDT 24
Finished Aug 18 05:22:11 PM PDT 24
Peak memory 195320 kb
Host smart-74e1c5ed-3d07-471e-a0ab-17c15a593210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393659610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1393659610
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1513849193
Short name T180
Test name
Test status
Simulation time 2717579476744 ps
CPU time 910.72 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:35:25 PM PDT 24
Peak memory 191672 kb
Host smart-18e5cd3a-b363-44af-8538-0ec7a607413c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513849193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1513849193
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1890210376
Short name T35
Test name
Test status
Simulation time 1532400063 ps
CPU time 19.71 seconds
Started Aug 18 05:20:13 PM PDT 24
Finished Aug 18 05:20:33 PM PDT 24
Peak memory 193968 kb
Host smart-3f579e44-660e-48f0-8502-3907a3f6e475
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890210376 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1890210376
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.2477930160
Short name T109
Test name
Test status
Simulation time 252901649724 ps
CPU time 511.55 seconds
Started Aug 18 05:21:06 PM PDT 24
Finished Aug 18 05:29:38 PM PDT 24
Peak memory 191768 kb
Host smart-e4360039-04c9-42ef-9db6-82a7696f399f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477930160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2477930160
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1213926809
Short name T104
Test name
Test status
Simulation time 193032051850 ps
CPU time 195.7 seconds
Started Aug 18 05:21:03 PM PDT 24
Finished Aug 18 05:24:19 PM PDT 24
Peak memory 191736 kb
Host smart-5024925b-aed1-4176-a241-1121ea8cba34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213926809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1213926809
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.4109409117
Short name T267
Test name
Test status
Simulation time 103268026989 ps
CPU time 225.28 seconds
Started Aug 18 05:21:02 PM PDT 24
Finished Aug 18 05:24:48 PM PDT 24
Peak memory 191696 kb
Host smart-f990a3f3-84da-44b8-be88-5243a94c7522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109409117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.4109409117
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2135990919
Short name T174
Test name
Test status
Simulation time 534619906544 ps
CPU time 541.84 seconds
Started Aug 18 05:21:02 PM PDT 24
Finished Aug 18 05:30:04 PM PDT 24
Peak memory 191672 kb
Host smart-44c89ceb-c566-429f-9c6e-db4c9529e9ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135990919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2135990919
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1459816483
Short name T324
Test name
Test status
Simulation time 271601883 ps
CPU time 2.66 seconds
Started Aug 18 05:21:02 PM PDT 24
Finished Aug 18 05:21:05 PM PDT 24
Peak memory 183496 kb
Host smart-83cbc682-d5a2-4430-bf70-82dffd86bcf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459816483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1459816483
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2216370947
Short name T290
Test name
Test status
Simulation time 80408584463 ps
CPU time 18.6 seconds
Started Aug 18 05:21:03 PM PDT 24
Finished Aug 18 05:21:21 PM PDT 24
Peak memory 183568 kb
Host smart-4c3baa59-8e3f-40ed-b36b-74fd224e23b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216370947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2216370947
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.8068508
Short name T176
Test name
Test status
Simulation time 52789285207 ps
CPU time 86.47 seconds
Started Aug 18 05:21:01 PM PDT 24
Finished Aug 18 05:22:28 PM PDT 24
Peak memory 191744 kb
Host smart-d86e46a4-b3ac-4e93-bde9-9d478e227a30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8068508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.8068508
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2556650542
Short name T268
Test name
Test status
Simulation time 415086813783 ps
CPU time 593.18 seconds
Started Aug 18 05:20:14 PM PDT 24
Finished Aug 18 05:30:07 PM PDT 24
Peak memory 183496 kb
Host smart-e871363a-fa8c-4984-8d86-349c769f4b26
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556650542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2556650542
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2496584615
Short name T372
Test name
Test status
Simulation time 388569712666 ps
CPU time 294.66 seconds
Started Aug 18 05:20:17 PM PDT 24
Finished Aug 18 05:25:12 PM PDT 24
Peak memory 183608 kb
Host smart-2316b21c-29ef-4e1d-9740-7267d1f7113f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496584615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2496584615
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1720039813
Short name T199
Test name
Test status
Simulation time 234153544404 ps
CPU time 441 seconds
Started Aug 18 05:20:17 PM PDT 24
Finished Aug 18 05:27:38 PM PDT 24
Peak memory 191764 kb
Host smart-8b6a364e-3a24-4c5c-99b9-247b7e7a312f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720039813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1720039813
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.770191338
Short name T91
Test name
Test status
Simulation time 152429601658 ps
CPU time 751.75 seconds
Started Aug 18 05:20:15 PM PDT 24
Finished Aug 18 05:32:47 PM PDT 24
Peak memory 191768 kb
Host smart-a117fb2f-19fa-4f71-8825-771809a1a77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770191338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.770191338
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1038050058
Short name T249
Test name
Test status
Simulation time 2398203890622 ps
CPU time 1993.55 seconds
Started Aug 18 05:20:16 PM PDT 24
Finished Aug 18 05:53:30 PM PDT 24
Peak memory 196096 kb
Host smart-4fc515a8-029d-4977-bdba-585e5af69911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038050058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1038050058
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/81.rv_timer_random.896471262
Short name T98
Test name
Test status
Simulation time 81109906905 ps
CPU time 172.96 seconds
Started Aug 18 05:21:06 PM PDT 24
Finished Aug 18 05:24:00 PM PDT 24
Peak memory 189736 kb
Host smart-5ca820b2-c3f9-4468-aa6b-26683dbf4b1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896471262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.896471262
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.4287811406
Short name T245
Test name
Test status
Simulation time 43919181744 ps
CPU time 71.87 seconds
Started Aug 18 05:21:06 PM PDT 24
Finished Aug 18 05:22:18 PM PDT 24
Peak memory 191768 kb
Host smart-f5f29088-d02a-4723-a4bd-63a0afc5c3cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287811406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.4287811406
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2525948740
Short name T219
Test name
Test status
Simulation time 165366922426 ps
CPU time 472.89 seconds
Started Aug 18 05:21:06 PM PDT 24
Finished Aug 18 05:28:59 PM PDT 24
Peak memory 191668 kb
Host smart-012f2c34-590f-479c-9b89-b9403ec3797e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525948740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2525948740
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2024450888
Short name T299
Test name
Test status
Simulation time 118704327145 ps
CPU time 48.2 seconds
Started Aug 18 05:21:07 PM PDT 24
Finished Aug 18 05:21:56 PM PDT 24
Peak memory 183580 kb
Host smart-0a5224d6-ac48-4a23-8521-3000247832af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024450888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2024450888
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4000249741
Short name T101
Test name
Test status
Simulation time 132408201497 ps
CPU time 399.68 seconds
Started Aug 18 05:21:11 PM PDT 24
Finished Aug 18 05:27:51 PM PDT 24
Peak memory 191700 kb
Host smart-1364908b-10cc-4cd6-8b59-f34e99f9ce7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000249741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4000249741
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.4267090054
Short name T94
Test name
Test status
Simulation time 41731160991 ps
CPU time 92.07 seconds
Started Aug 18 05:21:10 PM PDT 24
Finished Aug 18 05:22:43 PM PDT 24
Peak memory 191788 kb
Host smart-65ed7e29-07df-44e8-999a-f9fd6c097223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267090054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.4267090054
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2116358686
Short name T119
Test name
Test status
Simulation time 28642201582 ps
CPU time 14.62 seconds
Started Aug 18 05:20:13 PM PDT 24
Finished Aug 18 05:20:27 PM PDT 24
Peak memory 183576 kb
Host smart-d35942c7-0390-4c51-a180-534c08a1a5f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116358686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2116358686
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.168229151
Short name T390
Test name
Test status
Simulation time 815007647 ps
CPU time 1.77 seconds
Started Aug 18 05:20:15 PM PDT 24
Finished Aug 18 05:20:17 PM PDT 24
Peak memory 192112 kb
Host smart-4f624403-d086-4869-8abd-5b4f0e6dcfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168229151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.168229151
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/91.rv_timer_random.3496176228
Short name T158
Test name
Test status
Simulation time 742552946096 ps
CPU time 580.05 seconds
Started Aug 18 05:21:10 PM PDT 24
Finished Aug 18 05:30:51 PM PDT 24
Peak memory 191820 kb
Host smart-906d1c44-0b01-4805-859e-1e62ec19222d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496176228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3496176228
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1184998286
Short name T331
Test name
Test status
Simulation time 40426478116 ps
CPU time 52.92 seconds
Started Aug 18 05:21:12 PM PDT 24
Finished Aug 18 05:22:05 PM PDT 24
Peak memory 183412 kb
Host smart-fa2c1382-8bd9-450c-90b3-ddfe527c2cc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184998286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1184998286
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3332614064
Short name T163
Test name
Test status
Simulation time 240904966250 ps
CPU time 109.83 seconds
Started Aug 18 05:21:12 PM PDT 24
Finished Aug 18 05:23:02 PM PDT 24
Peak memory 183600 kb
Host smart-2a08defa-f0dd-456a-9521-6c486af34eb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332614064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3332614064
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1121861002
Short name T260
Test name
Test status
Simulation time 368766995821 ps
CPU time 214.37 seconds
Started Aug 18 05:21:10 PM PDT 24
Finished Aug 18 05:24:45 PM PDT 24
Peak memory 191936 kb
Host smart-704463f7-eed6-4f46-ad4e-99a910a88ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121861002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1121861002
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.176190579
Short name T279
Test name
Test status
Simulation time 120095090385 ps
CPU time 224.17 seconds
Started Aug 18 05:21:11 PM PDT 24
Finished Aug 18 05:24:55 PM PDT 24
Peak memory 191732 kb
Host smart-db10125b-361a-40fc-9396-acc740b9a0bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176190579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.176190579
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1514677850
Short name T168
Test name
Test status
Simulation time 345101673066 ps
CPU time 1669.64 seconds
Started Aug 18 05:21:15 PM PDT 24
Finished Aug 18 05:49:05 PM PDT 24
Peak memory 191808 kb
Host smart-2b98a629-88d5-41a5-b73c-6bcae054ea53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514677850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1514677850
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.519310819
Short name T251
Test name
Test status
Simulation time 584604585402 ps
CPU time 464.5 seconds
Started Aug 18 05:21:11 PM PDT 24
Finished Aug 18 05:28:56 PM PDT 24
Peak memory 191680 kb
Host smart-6f293801-b9b9-4b8b-8db9-650646f4a2b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519310819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.519310819
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2860392691
Short name T173
Test name
Test status
Simulation time 111329190127 ps
CPU time 43.65 seconds
Started Aug 18 05:21:10 PM PDT 24
Finished Aug 18 05:21:53 PM PDT 24
Peak memory 194324 kb
Host smart-960dd7d4-2a1c-4be4-b096-841239193df8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860392691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2860392691
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2466125476
Short name T422
Test name
Test status
Simulation time 34389182730 ps
CPU time 229.2 seconds
Started Aug 18 05:21:11 PM PDT 24
Finished Aug 18 05:25:01 PM PDT 24
Peak memory 183544 kb
Host smart-6e370a5f-0bf5-40d1-8235-a54fb4a951ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466125476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2466125476
Directory /workspace/99.rv_timer_random/latest
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