Unified Coverage Report :: Group : rv_timer_env_pkg::rv_timer_cfg_cov_obj::timer_cfg_cg

Summary for Variable cp_mtime

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	50	0	50	100.00

Automatically Generated Bins for cp_mtime

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0000000000000000:051eb851eb851eb7]	25	1			T86	1		T87	1		T88	1
auto[051eb851eb851eb8:0a3d70a3d70a3d6f]	29	1			T2	1		T3	1		T86	2
auto[0a3d70a3d70a3d70:0f5c28f5c28f5c27]	22	1			T89	1		T90	1		T91	1
auto[0f5c28f5c28f5c28:147ae147ae147adf]	27	1			T1	1		T92	1		T90	1
auto[147ae147ae147ae0:1999999999999997]	20	1			T93	1		T90	2		T23	1
auto[1999999999999998:1eb851eb851eb84f]	33	1			T90	1		T94	1		T95	1
auto[1eb851eb851eb850:23d70a3d70a3d707]	17	1			T32	1		T96	1		T97	2
auto[23d70a3d70a3d708:28f5c28f5c28f5bf]	19	1			T95	1		T98	1		T99	1
auto[28f5c28f5c28f5c0:2e147ae147ae1477]	23	1			T41	1		T95	1		T18	1
auto[2e147ae147ae1478:333333333333332f]	19	1			T100	1		T95	1		T26	1
auto[3333333333333330:3851eb851eb851e7]	22	1			T101	1		T102	1		T103	1
auto[3851eb851eb851e8:3d70a3d70a3d709f]	16	1			T86	1		T104	1		T95	1
auto[3d70a3d70a3d70a0:428f5c28f5c28f57]	32	1			T6	1		T7	1		T9	2
auto[428f5c28f5c28f58:47ae147ae147ae0f]	16	1			T90	1		T18	1		T105	1
auto[47ae147ae147ae10:4cccccccccccccc7]	32	1			T2	1		T106	1		T107	2
auto[4cccccccccccccc8:51eb851eb851eb7f]	22	1			T7	1		T108	1		T95	2
auto[51eb851eb851eb80:570a3d70a3d70a37]	26	1			T9	1		T41	1		T109	1
auto[570a3d70a3d70a38:5c28f5c28f5c28ef]	31	1			T7	1		T10	1		T110	1
auto[5c28f5c28f5c28f0:6147ae147ae147a7]	29	1			T2	1		T7	1		T111	1
auto[6147ae147ae147a8:666666666666665f]	17	1			T8	1		T112	1		T54	1
auto[6666666666666660:6b851eb851eb8517]	28	1			T2	1		T40	1		T113	1
auto[6b851eb851eb8518:70a3d70a3d70a3cf]	19	1			T32	1		T111	1		T95	1
auto[70a3d70a3d70a3d0:75c28f5c28f5c287]	27	1			T113	1		T93	1		T23	1
auto[75c28f5c28f5c288:7ae147ae147ae13f]	25	1			T6	1		T32	2		T106	1
auto[7ae147ae147ae140:7ffffffffffffff7]	33	1			T86	1		T32	1		T114	1
auto[7ffffffffffffff8:851eb851eb851eaf]	26	1			T3	1		T9	1		T90	1
auto[851eb851eb851eb0:8a3d70a3d70a3d67]	24	1			T32	1		T115	1		T116	1
auto[8a3d70a3d70a3d68:8f5c28f5c28f5c1f]	21	1			T8	1		T104	1		T95	1
auto[8f5c28f5c28f5c20:947ae147ae147ad7]	28	1			T10	1		T108	1		T95	1
auto[947ae147ae147ad8:999999999999998f]	29	1			T32	1		T106	1		T95	1
auto[9999999999999990:9eb851eb851eb847]	24	1			T41	1		T23	1		T117	1
auto[9eb851eb851eb848:a3d70a3d70a3d6ff]	19	1			T93	1		T95	1		T88	1
auto[a3d70a3d70a3d700:a8f5c28f5c28f5b7]	17	1			T41	1		T32	1		T109	1
auto[a8f5c28f5c28f5b8:ae147ae147ae146f]	27	1			T10	1		T32	1		T104	2
auto[ae147ae147ae1470:b333333333333327]	18	1			T10	1		T42	1		T100	1
auto[b333333333333328:b851eb851eb851df]	20	1			T7	1		T109	1		T95	1
auto[b851eb851eb851e0:bd70a3d70a3d7097]	24	1			T118	1		T53	1		T54	1
auto[bd70a3d70a3d7098:c28f5c28f5c28f4f]	19	1			T119	1		T120	1		T121	1
auto[c28f5c28f5c28f50:c7ae147ae147ae07]	16	1			T92	1		T102	1		T122	1
auto[c7ae147ae147ae08:ccccccccccccccbf]	28	1			T6	1		T41	2		T110	1
auto[ccccccccccccccc0:d1eb851eb851eb77]	24	1			T92	1		T108	1		T107	1
auto[d1eb851eb851eb78:d70a3d70a3d70a2f]	19	1			T123	1		T124	1		T125	1
auto[d70a3d70a3d70a30:dc28f5c28f5c28e7]	23	1			T113	1		T32	1		T107	1
auto[dc28f5c28f5c28e8:e147ae147ae1479f]	15	1			T89	1		T95	2		T88	1
auto[e147ae147ae147a0:e666666666666657]	23	1			T9	1		T95	1		T126	1
auto[e666666666666658:eb851eb851eb850f]	31	1			T42	1		T113	1		T89	1
auto[eb851eb851eb8510:f0a3d70a3d70a3c7]	23	1			T20	1		T127	1		T128	1
auto[f0a3d70a3d70a3c8:f5c28f5c28f5c27f]	31	1			T129	1		T118	1		T94	1
auto[f5c28f5c28f5c280:fae147ae147ae137]	19	1			T110	1		T54	1		T128	1
auto[fae147ae147ae138:ffffffffffffffff]	24	1			T96	1		T53	1		T87	1

---

Summary for Variable cp_mtime_cmp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	50	0	50	100.00

Automatically Generated Bins for cp_mtime_cmp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0000000000000000:051eb851eb851eb7]	25	1			T86	1		T87	1		T88	1
auto[051eb851eb851eb8:0a3d70a3d70a3d6f]	29	1			T2	1		T3	1		T86	2
auto[0a3d70a3d70a3d70:0f5c28f5c28f5c27]	22	1			T89	1		T90	1		T91	1
auto[0f5c28f5c28f5c28:147ae147ae147adf]	27	1			T1	1		T92	1		T90	1
auto[147ae147ae147ae0:1999999999999997]	20	1			T93	1		T90	2		T23	1
auto[1999999999999998:1eb851eb851eb84f]	33	1			T90	1		T94	1		T95	1
auto[1eb851eb851eb850:23d70a3d70a3d707]	17	1			T32	1		T96	1		T97	2
auto[23d70a3d70a3d708:28f5c28f5c28f5bf]	19	1			T95	1		T98	1		T99	1
auto[28f5c28f5c28f5c0:2e147ae147ae1477]	23	1			T41	1		T95	1		T18	1
auto[2e147ae147ae1478:333333333333332f]	19	1			T100	1		T95	1		T26	1
auto[3333333333333330:3851eb851eb851e7]	22	1			T101	1		T102	1		T103	1
auto[3851eb851eb851e8:3d70a3d70a3d709f]	16	1			T86	1		T104	1		T95	1
auto[3d70a3d70a3d70a0:428f5c28f5c28f57]	32	1			T6	1		T7	1		T9	2
auto[428f5c28f5c28f58:47ae147ae147ae0f]	16	1			T90	1		T18	1		T105	1
auto[47ae147ae147ae10:4cccccccccccccc7]	32	1			T2	1		T106	1		T107	2
auto[4cccccccccccccc8:51eb851eb851eb7f]	22	1			T7	1		T108	1		T95	2
auto[51eb851eb851eb80:570a3d70a3d70a37]	26	1			T9	1		T41	1		T109	1
auto[570a3d70a3d70a38:5c28f5c28f5c28ef]	31	1			T7	1		T10	1		T110	1
auto[5c28f5c28f5c28f0:6147ae147ae147a7]	29	1			T2	1		T7	1		T111	1
auto[6147ae147ae147a8:666666666666665f]	17	1			T8	1		T112	1		T54	1
auto[6666666666666660:6b851eb851eb8517]	28	1			T2	1		T40	1		T113	1
auto[6b851eb851eb8518:70a3d70a3d70a3cf]	19	1			T32	1		T111	1		T95	1
auto[70a3d70a3d70a3d0:75c28f5c28f5c287]	27	1			T113	1		T93	1		T23	1
auto[75c28f5c28f5c288:7ae147ae147ae13f]	25	1			T6	1		T32	2		T106	1
auto[7ae147ae147ae140:7ffffffffffffff7]	33	1			T86	1		T32	1		T114	1
auto[7ffffffffffffff8:851eb851eb851eaf]	26	1			T3	1		T9	1		T90	1
auto[851eb851eb851eb0:8a3d70a3d70a3d67]	24	1			T32	1		T115	1		T116	1
auto[8a3d70a3d70a3d68:8f5c28f5c28f5c1f]	21	1			T8	1		T104	1		T95	1
auto[8f5c28f5c28f5c20:947ae147ae147ad7]	28	1			T10	1		T108	1		T95	1
auto[947ae147ae147ad8:999999999999998f]	29	1			T32	1		T106	1		T95	1
auto[9999999999999990:9eb851eb851eb847]	24	1			T41	1		T23	1		T117	1
auto[9eb851eb851eb848:a3d70a3d70a3d6ff]	19	1			T93	1		T95	1		T88	1
auto[a3d70a3d70a3d700:a8f5c28f5c28f5b7]	17	1			T41	1		T32	1		T109	1
auto[a8f5c28f5c28f5b8:ae147ae147ae146f]	27	1			T10	1		T32	1		T104	2
auto[ae147ae147ae1470:b333333333333327]	18	1			T10	1		T42	1		T100	1
auto[b333333333333328:b851eb851eb851df]	20	1			T7	1		T109	1		T95	1
auto[b851eb851eb851e0:bd70a3d70a3d7097]	24	1			T118	1		T53	1		T54	1
auto[bd70a3d70a3d7098:c28f5c28f5c28f4f]	19	1			T119	1		T120	1		T121	1
auto[c28f5c28f5c28f50:c7ae147ae147ae07]	16	1			T92	1		T102	1		T122	1
auto[c7ae147ae147ae08:ccccccccccccccbf]	28	1			T6	1		T41	2		T110	1
auto[ccccccccccccccc0:d1eb851eb851eb77]	24	1			T92	1		T108	1		T107	1
auto[d1eb851eb851eb78:d70a3d70a3d70a2f]	19	1			T123	1		T124	1		T125	1
auto[d70a3d70a3d70a30:dc28f5c28f5c28e7]	23	1			T113	1		T32	1		T107	1
auto[dc28f5c28f5c28e8:e147ae147ae1479f]	15	1			T89	1		T95	2		T88	1
auto[e147ae147ae147a0:e666666666666657]	23	1			T9	1		T95	1		T126	1
auto[e666666666666658:eb851eb851eb850f]	31	1			T42	1		T113	1		T89	1
auto[eb851eb851eb8510:f0a3d70a3d70a3c7]	23	1			T20	1		T127	1		T128	1
auto[f0a3d70a3d70a3c8:f5c28f5c28f5c27f]	31	1			T129	1		T118	1		T94	1
auto[f5c28f5c28f5c280:fae147ae147ae137]	19	1			T110	1		T54	1		T128	1
auto[fae147ae147ae138:ffffffffffffffff]	24	1			T96	1		T53	1		T87	1

---

Summary for Variable cp_prescale

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	256	2	254	99.22

Automatically Generated Bins for cp_prescale

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[448:463]]	0	1	1
[auto[3840:3855]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:15]	4	1			T108	1		T130	1		T57	1
auto[16:31]	9	1			T106	1		T95	1		T126	1
auto[32:47]	5	1			T2	1		T55	1		T131	1
auto[48:63]	7	1			T109	1		T132	1		T133	1
auto[64:79]	4	1			T1	1		T102	1		T134	1
auto[80:95]	7	1			T126	1		T135	1		T136	1
auto[96:111]	6	1			T137	1		T57	2		T138	1
auto[112:127]	6	1			T128	1		T139	1		T140	1
auto[128:143]	6	1			T118	1		T56	1		T141	1
auto[144:159]	4	1			T104	1		T57	1		T131	1
auto[160:175]	6	1			T54	1		T116	1		T142	1
auto[176:191]	2	1			T94	1		T143	1		-	-
auto[192:207]	1	1			T144	1		-	-		-	-
auto[208:223]	6	1			T41	1		T145	1		T54	1
auto[224:239]	6	1			T95	1		T88	1		T146	1
auto[240:255]	5	1			T147	1		T148	1		T149	1
auto[256:271]	7	1			T108	1		T95	1		T98	1
auto[272:287]	4	1			T53	1		T128	1		T150	1
auto[288:303]	7	1			T53	1		T151	1		T117	1
auto[304:319]	5	1			T54	1		T152	1		T153	1
auto[320:335]	6	1			T154	1		T146	1		T155	1
auto[336:351]	2	1			T156	1		T157	1		-	-
auto[352:367]	5	1			T129	1		T104	1		T158	1
auto[368:383]	6	1			T32	1		T54	1		T125	1
auto[384:399]	3	1			T159	1		T160	1		T161	1
auto[400:415]	3	1			T162	1		T163	1		T164	1
auto[416:431]	7	1			T32	1		T165	1		T166	1
auto[432:447]	6	1			T95	1		T167	1		T168	1
auto[464:479]	1	1			T169	1		-	-		-	-
auto[480:495]	2	1			T170	1		T171	1		-	-
auto[496:511]	4	1			T26	1		T172	1		T173	1
auto[512:527]	6	1			T7	1		T124	1		T165	1
auto[528:543]	5	1			T95	1		T174	1		T135	1
auto[544:559]	2	1			T175	1		T176	1		-	-
auto[560:575]	1	1			T32	1		-	-		-	-
auto[576:591]	2	1			T177	1		T178	1		-	-
auto[592:607]	7	1			T126	1		T139	1		T179	1
auto[608:623]	7	1			T7	1		T94	1		T23	1
auto[624:639]	4	1			T180	1		T181	1		T157	1
auto[640:655]	5	1			T182	1		T174	1		T183	1
auto[656:671]	2	1			T180	1		T184	1		-	-
auto[672:687]	5	1			T112	1		T20	1		T185	1
auto[688:703]	3	1			T147	1		T186	1		T187	1
auto[704:719]	4	1			T188	1		T166	1		T189	1
auto[720:735]	3	1			T95	1		T190	1		T170	1
auto[736:751]	7	1			T191	1		T192	1		T149	1
auto[752:767]	5	1			T117	1		T169	1		T193	1
auto[768:783]	6	1			T95	1		T53	1		T194	1
auto[784:799]	6	1			T101	1		T195	1		T186	1
auto[800:815]	4	1			T125	1		T196	1		T197	1
auto[816:831]	5	1			T198	1		T199	1		T200	1
auto[832:847]	6	1			T159	1		T54	2		T150	1
auto[848:863]	2	1			T159	1		T201	1		-	-
auto[864:879]	3	1			T202	1		T203	1		T204	1
auto[880:895]	5	1			T98	1		T205	1		T203	1
auto[896:911]	5	1			T8	1		T54	1		T165	1
auto[912:927]	5	1			T111	1		T87	1		T206	1
auto[928:943]	6	1			T102	1		T207	1		T208	1
auto[944:959]	7	1			T209	1		T165	1		T210	1
auto[960:975]	4	1			T42	1		T111	1		T103	1
auto[976:991]	1	1			T181	1		-	-		-	-
auto[992:1007]	7	1			T86	1		T211	1		T212	1
auto[1008:1023]	6	1			T2	1		T56	1		T121	1
auto[1024:1039]	3	1			T213	1		T214	1		T215	1
auto[1040:1055]	2	1			T216	1		T178	1		-	-
auto[1056:1071]	8	1			T53	1		T97	1		T217	1
auto[1072:1087]	4	1			T6	1		T217	1		T218	1
auto[1088:1103]	4	1			T132	1		T176	1		T219	1
auto[1104:1119]	2	1			T120	1		T220	1		-	-
auto[1120:1135]	3	1			T86	1		T206	1		T221	1
auto[1136:1151]	7	1			T6	1		T94	1		T116	1
auto[1152:1167]	6	1			T130	1		T217	1		T222	1
auto[1168:1183]	6	1			T170	1		T140	1		T57	1
auto[1184:1199]	4	1			T223	1		T224	1		T225	1
auto[1200:1215]	4	1			T130	1		T168	1		T176	1
auto[1216:1231]	3	1			T99	1		T226	1		T227	1
auto[1232:1247]	4	1			T228	1		T229	1		T230	1
auto[1248:1263]	8	1			T110	1		T190	1		T158	1
auto[1264:1279]	2	1			T165	1		T149	1		-	-
auto[1280:1295]	3	1			T18	1		T174	1		T220	1
auto[1296:1311]	7	1			T92	1		T89	1		T231	1
auto[1312:1327]	1	1			T95	1		-	-		-	-
auto[1328:1343]	4	1			T223	1		T122	1		T177	1
auto[1344:1359]	6	1			T95	1		T135	1		T232	1
auto[1360:1375]	6	1			T41	1		T95	1		T233	1
auto[1376:1391]	3	1			T214	1		T234	1		T235	1
auto[1392:1407]	6	1			T111	1		T223	1		T180	1
auto[1408:1423]	3	1			T190	1		T156	1		T236	1
auto[1424:1439]	3	1			T190	1		T237	1		T238	1
auto[1440:1455]	4	1			T144	1		T239	1		T162	1
auto[1456:1471]	6	1			T130	1		T206	1		T240	1
auto[1472:1487]	4	1			T95	1		T151	1		T132	1
auto[1488:1503]	1	1			T241	1		-	-		-	-
auto[1504:1519]	7	1			T32	1		T56	1		T165	1
auto[1520:1535]	7	1			T113	1		T93	1		T110	1
auto[1536:1551]	5	1			T95	1		T242	1		T168	1
auto[1552:1567]	3	1			T95	2		T243	1		-	-
auto[1568:1583]	6	1			T40	1		T98	1		T244	1
auto[1584:1599]	4	1			T183	1		T169	1		T239	1
auto[1600:1615]	3	1			T94	1		T103	1		T245	1
auto[1616:1631]	9	1			T95	1		T175	1		T156	1
auto[1632:1647]	3	1			T57	1		T163	1		T246	1
auto[1648:1663]	5	1			T87	1		T196	1		T57	1
auto[1664:1679]	9	1			T2	1		T95	1		T23	1
auto[1680:1695]	8	1			T20	1		T127	1		T151	1
auto[1696:1711]	5	1			T10	1		T142	1		T221	1
auto[1712:1727]	3	1			T56	1		T247	1		T248	1
auto[1728:1743]	2	1			T3	1		T249	1		-	-
auto[1744:1759]	1	1			T215	1		-	-		-	-
auto[1760:1775]	5	1			T218	1		T137	1		T250	1
auto[1776:1791]	2	1			T127	1		T230	1		-	-
auto[1792:1807]	6	1			T10	1		T92	1		T242	1
auto[1808:1823]	2	1			T117	1		T251	1		-	-
auto[1824:1839]	3	1			T111	1		T141	1		T252	1
auto[1840:1855]	3	1			T242	1		T206	1		T253	1
auto[1856:1871]	4	1			T254	1		T255	1		T165	1
auto[1872:1887]	4	1			T113	1		T107	1		T256	1
auto[1888:1903]	4	1			T151	1		T167	1		T183	1
auto[1904:1919]	11	1			T118	1		T95	1		T257	1
auto[1920:1935]	7	1			T93	1		T53	1		T182	1
auto[1936:1951]	3	1			T106	1		T258	1		T259	1
auto[1952:1967]	3	1			T96	1		T260	1		T261	1
auto[1968:1983]	4	1			T6	1		T262	1		T263	1
auto[1984:1999]	1	1			T192	1		-	-		-	-
auto[2000:2015]	5	1			T264	1		T144	1		T214	1
auto[2016:2031]	3	1			T218	1		T186	1		T265	1
auto[2032:2047]	3	1			T197	1		T173	1		T215	1
auto[2048:2063]	2	1			T54	1		T266	1		-	-
auto[2064:2079]	4	1			T125	1		T194	1		T192	1
auto[2080:2095]	8	1			T109	1		T151	1		T119	1
auto[2096:2111]	4	1			T113	1		T116	1		T117	1
auto[2112:2127]	8	1			T42	1		T20	1		T182	1
auto[2128:2143]	2	1			T145	1		T132	1		-	-
auto[2144:2159]	6	1			T232	1		T134	1		T267	1
auto[2160:2175]	7	1			T151	1		T268	1		T56	1
auto[2176:2191]	3	1			T87	1		T203	1		T220	1
auto[2192:2207]	4	1			T269	1		T270	1		T271	1
auto[2208:2223]	2	1			T90	1		T272	1		-	-
auto[2224:2239]	7	1			T89	1		T53	1		T167	1
auto[2240:2255]	3	1			T255	1		T154	1		T245	1
auto[2256:2271]	6	1			T223	1		T117	1		T273	1
auto[2272:2287]	10	1			T274	1		T231	1		T229	1
auto[2288:2303]	5	1			T100	1		T264	1		T203	1
auto[2304:2319]	5	1			T92	1		T147	1		T57	1
auto[2320:2335]	4	1			T122	1		T170	1		T201	1
auto[2336:2351]	4	1			T275	1		T276	1		T277	1
auto[2352:2367]	6	1			T110	1		T196	1		T177	1
auto[2368:2383]	6	1			T53	1		T116	1		T130	1
auto[2384:2399]	4	1			T3	1		T241	1		T278	1
auto[2400:2415]	6	1			T107	1		T109	1		T279	1
auto[2416:2431]	3	1			T54	1		T280	1		T281	1
auto[2432:2447]	5	1			T93	1		T118	1		T282	1
auto[2448:2463]	3	1			T260	1		T229	1		T234	1
auto[2464:2479]	6	1			T108	1		T32	1		T154	1
auto[2480:2495]	4	1			T283	1		T262	1		T284	1
auto[2496:2511]	2	1			T7	1		T285	1		-	-
auto[2512:2527]	8	1			T23	1		T286	1		T191	1
auto[2528:2543]	7	1			T255	1		T210	1		T287	1
auto[2544:2559]	6	1			T41	1		T54	1		T288	1
auto[2560:2575]	4	1			T122	1		T156	1		T253	1
auto[2576:2591]	1	1			T289	1		-	-		-	-
auto[2592:2607]	3	1			T123	1		T228	1		T173	1
auto[2608:2623]	3	1			T238	1		T290	1		T291	1
auto[2624:2639]	4	1			T108	1		T166	1		T292	1
auto[2640:2655]	4	1			T190	1		T268	1		T293	1
auto[2656:2671]	9	1			T86	1		T107	1		T154	1
auto[2672:2687]	7	1			T94	1		T105	1		T174	1
auto[2688:2703]	2	1			T268	1		T294	1		-	-
auto[2704:2719]	5	1			T295	1		T169	1		T180	1
auto[2720:2735]	5	1			T10	1		T41	1		T296	1
auto[2736:2751]	4	1			T144	1		T222	1		T297	1
auto[2752:2767]	4	1			T86	1		T91	1		T95	1
auto[2768:2783]	2	1			T90	1		T163	1		-	-
auto[2784:2799]	5	1			T32	1		T118	1		T123	1
auto[2800:2815]	1	1			T212	1		-	-		-	-
auto[2816:2831]	5	1			T217	1		T152	1		T277	1
auto[2832:2847]	11	1			T111	1		T18	1		T125	1
auto[2848:2863]	7	1			T8	1		T117	1		T217	1
auto[2864:2879]	6	1			T32	1		T22	1		T88	1
auto[2880:2895]	5	1			T113	1		T144	1		T298	1
auto[2896:2911]	5	1			T9	1		T144	1		T134	2
auto[2912:2927]	8	1			T90	1		T99	1		T156	1
auto[2928:2943]	6	1			T18	1		T194	1		T167	1
auto[2944:2959]	4	1			T95	1		T174	1		T231	1
auto[2960:2975]	2	1			T167	1		T265	1		-	-
auto[2976:2991]	3	1			T106	1		T211	1		T299	1
auto[2992:3007]	8	1			T90	1		T95	1		T182	1
auto[3008:3023]	7	1			T95	1		T126	1		T54	1
auto[3024:3039]	1	1			T192	1		-	-		-	-
auto[3040:3055]	5	1			T2	1		T56	1		T205	1
auto[3056:3071]	4	1			T93	1		T132	1		T244	1
auto[3072:3087]	2	1			T9	1		T265	1		-	-
auto[3088:3103]	6	1			T95	1		T53	1		T192	1
auto[3104:3119]	1	1			T89	1		-	-		-	-
auto[3120:3135]	3	1			T250	1		T300	1		T301	1
auto[3136:3151]	6	1			T32	1		T97	1		T295	1
auto[3152:3167]	3	1			T214	1		T284	1		T302	1
auto[3168:3183]	3	1			T223	1		T276	1		T236	1
auto[3184:3199]	4	1			T126	1		T88	1		T303	1
auto[3200:3215]	4	1			T86	1		T147	1		T120	1
auto[3216:3231]	5	1			T88	1		T146	1		T304	1
auto[3232:3247]	8	1			T20	1		T54	1		T122	1
auto[3248:3263]	4	1			T305	1		T201	1		T304	1
auto[3264:3279]	5	1			T103	2		T162	1		T306	1
auto[3280:3295]	6	1			T107	1		T117	1		T150	1
auto[3296:3311]	5	1			T136	1		T307	1		T308	1
auto[3312:3327]	7	1			T104	1		T88	1		T117	1
auto[3328:3343]	5	1			T22	1		T53	1		T87	1
auto[3344:3359]	4	1			T41	1		T23	1		T131	1
auto[3360:3375]	4	1			T32	1		T165	1		T309	1
auto[3376:3391]	4	1			T144	1		T157	1		T310	1
auto[3392:3407]	10	1			T104	1		T217	1		T277	1
auto[3408:3423]	3	1			T113	1		T279	1		T302	1
auto[3424:3439]	4	1			T117	1		T311	1		T269	1
auto[3440:3455]	3	1			T23	1		T137	1		T312	1
auto[3456:3471]	3	1			T7	1		T273	1		T200	1
auto[3472:3487]	5	1			T313	1		T206	1		T253	1
auto[3488:3503]	1	1			T314	1		-	-		-	-
auto[3504:3519]	3	1			T315	1		T172	1		T316	1
auto[3520:3535]	9	1			T107	1		T25	1		T103	1
auto[3536:3551]	2	1			T144	1		T193	1		-	-
auto[3552:3567]	3	1			T32	1		T181	1		T200	1
auto[3568:3583]	2	1			T211	1		T184	1		-	-
auto[3584:3599]	4	1			T260	1		T270	1		T290	1
auto[3600:3615]	9	1			T95	1		T54	1		T150	1
auto[3616:3631]	5	1			T90	1		T20	1		T182	1
auto[3632:3647]	2	1			T152	1		T317	1		-	-
auto[3648:3663]	3	1			T306	1		T316	1		T247	1
auto[3664:3679]	7	1			T100	1		T121	1		T195	1
auto[3680:3695]	8	1			T9	1		T192	1		T214	1
auto[3696:3711]	1	1			T97	1		-	-		-	-
auto[3712:3727]	4	1			T22	1		T115	1		T150	1
auto[3728:3743]	6	1			T95	1		T257	1		T141	1
auto[3744:3759]	5	1			T113	1		T116	1		T264	1
auto[3760:3775]	8	1			T41	1		T106	1		T114	1
auto[3776:3791]	3	1			T182	1		T60	1		T171	1
auto[3792:3807]	6	1			T318	1		T288	1		T308	1
auto[3808:3823]	2	1			T145	1		T191	1		-	-
auto[3824:3839]	5	1			T7	1		T9	1		T54	1
auto[3856:3871]	3	1			T90	1		T164	1		T267	1
auto[3872:3887]	6	1			T25	1		T97	1		T319	1
auto[3888:3903]	6	1			T111	1		T53	2		T144	1
auto[3904:3919]	1	1			T246	1		-	-		-	-
auto[3920:3935]	8	1			T10	1		T105	1		T223	1
auto[3936:3951]	2	1			T206	1		T265	1		-	-
auto[3952:3967]	7	1			T90	1		T130	1		T202	1
auto[3968:3983]	4	1			T320	1		T185	1		T321	1
auto[3984:3999]	8	1			T211	1		T242	1		T120	1
auto[4000:4015]	3	1			T87	1		T188	1		T248	1
auto[4016:4031]	6	1			T55	1		T56	1		T188	1
auto[4032:4047]	5	1			T9	1		T10	1		T196	1
auto[4048:4063]	3	1			T264	1		T133	1		T172	1
auto[4064:4079]	7	1			T217	1		T322	1		T153	1
auto[4080:4095]	9	1			T96	1		T175	1		T56	1

---

Summary for Variable cp_step

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	255	5	250	98.04

User Defined Bins for cp_step

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
step_all_val[16]	0	1	1
step_all_val[142]	0	1	1
step_all_val[165]	0	1	1
step_all_val[202]	0	1	1
step_all_val[232]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
step_all_val[1]	2	1			T90	1		T323	1		-	-
step_all_val[2]	3	1			T113	1		T264	1		T163	1
step_all_val[3]	1	1			T177	1		-	-		-	-
step_all_val[4]	5	1			T182	1		T214	1		T200	1
step_all_val[5]	8	1			T108	1		T110	1		T121	1
step_all_val[6]	6	1			T114	1		T199	1		T269	1
step_all_val[7]	5	1			T93	1		T116	1		T142	1
step_all_val[8]	5	1			T159	1		T97	1		T103	1
step_all_val[9]	6	1			T198	1		T132	1		T324	1
step_all_val[10]	4	1			T145	1		T53	1		T194	1
step_all_val[11]	4	1			T111	1		T95	1		T132	1
step_all_val[12]	4	1			T129	1		T191	1		T220	1
step_all_val[13]	5	1			T268	1		T205	1		T298	1
step_all_val[14]	4	1			T150	1		T157	1		T316	1
step_all_val[15]	3	1			T20	1		T117	1		T325	1
step_all_val[17]	3	1			T326	1		T185	1		T173	1
step_all_val[18]	5	1			T109	1		T195	1		T321	1
step_all_val[19]	4	1			T175	1		T173	1		T327	1
step_all_val[20]	6	1			T20	1		T56	1		T195	2
step_all_val[21]	3	1			T207	1		T131	1		T324	1
step_all_val[22]	5	1			T3	1		T95	1		T142	1
step_all_val[23]	5	1			T10	1		T113	1		T276	1
step_all_val[24]	6	1			T53	1		T167	2		T181	1
step_all_val[25]	7	1			T100	1		T196	1		T56	1
step_all_val[26]	2	1			T257	1		T311	1		-	-
step_all_val[27]	5	1			T97	1		T223	1		T139	1
step_all_val[28]	4	1			T18	1		T243	1		T274	1
step_all_val[29]	4	1			T89	1		T217	1		T305	1
step_all_val[30]	5	1			T96	1		T95	1		T144	1
step_all_val[31]	7	1			T159	1		T206	1		T165	1
step_all_val[32]	2	1			T124	1		T272	1		-	-
step_all_val[33]	4	1			T268	1		T167	1		T328	1
step_all_val[34]	7	1			T32	1		T54	1		T147	1
step_all_val[35]	7	1			T101	1		T196	1		T218	1
step_all_val[36]	9	1			T53	1		T88	1		T122	1
step_all_val[37]	4	1			T127	1		T150	1		T144	1
step_all_val[38]	5	1			T41	1		T95	1		T329	1
step_all_val[39]	5	1			T106	1		T159	1		T130	1
step_all_val[40]	5	1			T87	1		T298	1		T304	1
step_all_val[41]	2	1			T330	1		T331	1		-	-
step_all_val[42]	4	1			T54	1		T314	1		T246	1
step_all_val[43]	9	1			T104	1		T95	1		T255	1
step_all_val[44]	6	1			T112	1		T95	1		T53	1
step_all_val[45]	5	1			T118	1		T116	1		T139	1
step_all_val[46]	9	1			T25	1		T274	1		T137	1
step_all_val[47]	7	1			T117	1		T243	2		T332	1
step_all_val[48]	2	1			T130	1		T184	1		-	-
step_all_val[49]	5	1			T95	1		T188	1		T153	1
step_all_val[50]	6	1			T93	1		T95	1		T23	1
step_all_val[51]	3	1			T102	1		T125	1		T174	1
step_all_val[52]	5	1			T232	1		T220	1		T189	1
step_all_val[53]	2	1			T92	1		T106	1		-	-
step_all_val[54]	4	1			T277	1		T132	1		T333	1
step_all_val[55]	6	1			T113	1		T32	1		T126	1
step_all_val[56]	5	1			T312	1		T60	1		T334	1
step_all_val[57]	6	1			T93	1		T239	1		T240	1
step_all_val[58]	9	1			T87	1		T54	1		T174	1
step_all_val[59]	6	1			T90	1		T95	1		T191	1
step_all_val[60]	2	1			T10	1		T125	1		-	-
step_all_val[61]	3	1			T118	1		T255	1		T222	1
step_all_val[62]	3	1			T87	1		T56	1		T298	1
step_all_val[63]	10	1			T113	1		T151	1		T54	1
step_all_val[64]	5	1			T106	1		T90	1		T167	1
step_all_val[65]	4	1			T107	1		T245	1		T299	1
step_all_val[66]	4	1			T136	1		T170	1		T143	1
step_all_val[67]	6	1			T151	1		T117	1		T152	1
step_all_val[68]	5	1			T99	1		T198	1		T216	1
step_all_val[69]	6	1			T42	1		T209	1		T206	1
step_all_val[70]	5	1			T9	1		T286	1		T116	1
step_all_val[71]	2	1			T278	1		T273	1		-	-
step_all_val[72]	5	1			T86	1		T140	1		T143	1
step_all_val[73]	4	1			T54	1		T174	1		T192	1
step_all_val[74]	5	1			T54	1		T165	1		T234	1
step_all_val[75]	1	1			T95	1		-	-		-	-
step_all_val[76]	4	1			T198	1		T157	1		T244	1
step_all_val[77]	2	1			T57	1		T269	1		-	-
step_all_val[78]	4	1			T262	1		T335	1		T336	1
step_all_val[79]	4	1			T188	1		T337	1		T280	1
step_all_val[80]	3	1			T117	1		T147	1		T295	1
step_all_val[81]	9	1			T23	2		T286	1		T211	1
step_all_val[82]	4	1			T231	1		T205	1		T284	1
step_all_val[83]	10	1			T94	1		T53	1		T54	1
step_all_val[84]	3	1			T275	1		T312	1		T338	1
step_all_val[85]	4	1			T54	1		T339	1		T172	1
step_all_val[86]	1	1			T231	1		-	-		-	-
step_all_val[87]	4	1			T111	1		T188	1		T316	1
step_all_val[88]	4	1			T88	1		T56	1		T299	1
step_all_val[89]	5	1			T2	1		T40	1		T23	1
step_all_val[90]	3	1			T26	1		T317	1		T171	1
step_all_val[91]	3	1			T32	1		T175	1		T143	1
step_all_val[92]	6	1			T91	1		T318	1		T288	1
step_all_val[93]	1	1			T308	1		-	-		-	-
step_all_val[94]	2	1			T92	1		T232	1		-	-
step_all_val[95]	10	1			T95	1		T175	1		T165	2
step_all_val[96]	2	1			T6	1		T331	1		-	-
step_all_val[97]	7	1			T2	1		T126	1		T57	1
step_all_val[98]	4	1			T18	1		T154	1		T140	1
step_all_val[99]	3	1			T7	1		T97	1		T282	1
step_all_val[100]	5	1			T32	1		T123	1		T98	1
step_all_val[101]	6	1			T9	1		T107	1		T260	1
step_all_val[102]	9	1			T95	2		T283	1		T183	1
step_all_val[103]	5	1			T104	1		T53	1		T191	1
step_all_val[104]	5	1			T57	1		T161	1		T204	1
step_all_val[105]	4	1			T54	1		T276	1		T327	1
step_all_val[106]	5	1			T53	1		T168	1		T314	1
step_all_val[107]	3	1			T87	1		T203	1		T215	1
step_all_val[108]	6	1			T111	1		T126	1		T279	1
step_all_val[109]	2	1			T229	1		T340	1		-	-
step_all_val[110]	1	1			T131	1		-	-		-	-
step_all_val[111]	6	1			T22	1		T105	1		T102	1
step_all_val[112]	5	1			T6	1		T90	1		T95	1
step_all_val[113]	3	1			T217	1		T213	1		T201	1
step_all_val[114]	3	1			T117	1		T317	1		T341	1
step_all_val[115]	5	1			T60	1		T334	1		T263	1
step_all_val[116]	2	1			T136	1		T290	1		-	-
step_all_val[117]	7	1			T268	1		T153	1		T342	1
step_all_val[118]	4	1			T117	1		T121	1		T336	1
step_all_val[119]	1	1			T134	1		-	-		-	-
step_all_val[120]	4	1			T107	1		T257	1		T175	1
step_all_val[121]	5	1			T10	1		T160	1		T229	1
step_all_val[122]	5	1			T94	1		T126	1		T158	1
step_all_val[123]	4	1			T147	1		T314	1		T172	1
step_all_val[124]	4	1			T95	1		T145	1		T275	1
step_all_val[125]	3	1			T192	1		T240	1		T215	1
step_all_val[126]	3	1			T217	1		T194	1		T343	1
step_all_val[127]	6	1			T120	1		T56	1		T260	1
step_all_val[128]	2	1			T258	1		T344	1		-	-
step_all_val[129]	3	1			T345	1		T346	1		T248	1
step_all_val[130]	3	1			T94	1		T219	1		T269	1
step_all_val[131]	1	1			T135	1		-	-		-	-
step_all_val[132]	4	1			T8	1		T115	1		T239	1
step_all_val[133]	8	1			T32	1		T95	1		T190	1
step_all_val[134]	9	1			T95	1		T217	2		T214	1
step_all_val[135]	5	1			T7	1		T98	1		T206	1
step_all_val[136]	6	1			T182	1		T217	1		T56	1
step_all_val[137]	9	1			T145	1		T182	1		T223	1
step_all_val[138]	6	1			T183	1		T347	1		T348	1
step_all_val[139]	5	1			T135	1		T153	1		T325	1
step_all_val[140]	6	1			T25	1		T223	1		T190	1
step_all_val[141]	7	1			T104	1		T95	1		T116	1
step_all_val[143]	1	1			T259	1		-	-		-	-
step_all_val[144]	5	1			T88	1		T54	1		T349	1
step_all_val[145]	8	1			T86	1		T90	1		T252	1
step_all_val[146]	3	1			T168	1		T237	1		T200	1
step_all_val[147]	4	1			T165	1		T162	1		T161	1
step_all_val[148]	7	1			T41	2		T151	1		T156	1
step_all_val[149]	7	1			T177	1		T120	1		T186	1
step_all_val[150]	3	1			T167	1		T350	1		T248	1
step_all_val[151]	6	1			T95	1		T165	1		T236	1
step_all_val[152]	3	1			T221	1		T266	1		T265	1
step_all_val[153]	6	1			T242	1		T139	1		T150	1
step_all_val[154]	4	1			T6	1		T110	1		T103	1
step_all_val[155]	8	1			T117	1		T154	1		T192	1
step_all_val[156]	4	1			T53	1		T130	1		T176	1
step_all_val[157]	3	1			T117	1		T188	1		T180	1
step_all_val[158]	7	1			T351	1		T308	1		T168	1
step_all_val[159]	3	1			T22	1		T206	1		T168	1
step_all_val[160]	2	1			T229	1		T306	1		-	-
step_all_val[161]	3	1			T56	1		T142	1		T169	1
step_all_val[162]	2	1			T174	1		T142	1		-	-
step_all_val[163]	2	1			T166	1		T337	1		-	-
step_all_val[164]	7	1			T150	1		T307	1		T349	1
step_all_val[166]	5	1			T23	1		T97	1		T210	1
step_all_val[167]	7	1			T242	1		T308	1		T192	1
step_all_val[168]	1	1			T111	1		-	-		-	-
step_all_val[169]	8	1			T262	1		T212	1		T195	1
step_all_val[170]	7	1			T127	1		T55	1		T132	1
step_all_val[171]	6	1			T92	1		T113	1		T306	1
step_all_val[172]	7	1			T54	1		T279	1		T233	1
step_all_val[173]	2	1			T108	1		T95	1		-	-
step_all_val[174]	2	1			T211	1		T215	1		-	-
step_all_val[175]	6	1			T32	1		T99	1		T146	1
step_all_val[176]	4	1			T3	1		T86	1		T103	1
step_all_val[177]	7	1			T182	1		T98	1		T130	1
step_all_val[178]	3	1			T308	1		T149	1		T352	1
step_all_val[179]	8	1			T135	1		T194	1		T56	1
step_all_val[180]	5	1			T211	1		T242	1		T198	1
step_all_val[181]	3	1			T313	1		T137	1		T310	1
step_all_val[182]	5	1			T110	1		T130	1		T164	1
step_all_val[183]	2	1			T214	1		T267	1		-	-
step_all_val[184]	1	1			T323	1		-	-		-	-
step_all_val[185]	2	1			T128	1		T202	1		-	-
step_all_val[186]	8	1			T190	1		T120	1		T305	1
step_all_val[187]	6	1			T103	1		T231	1		T146	1
step_all_val[188]	3	1			T128	1		T276	1		T347	1
step_all_val[189]	8	1			T108	1		T107	1		T319	1
step_all_val[190]	6	1			T1	1		T94	1		T88	1
step_all_val[191]	4	1			T123	1		T239	1		T309	1
step_all_val[192]	5	1			T2	1		T106	1		T20	1
step_all_val[193]	3	1			T18	1		T341	1		T331	1
step_all_val[194]	2	1			T7	1		T163	1		-	-
step_all_val[195]	5	1			T10	1		T196	1		T169	1
step_all_val[196]	8	1			T10	1		T53	1		T156	2
step_all_val[197]	7	1			T20	1		T117	1		T137	1
step_all_val[198]	5	1			T108	1		T32	1		T330	1
step_all_val[199]	12	1			T93	1		T109	1		T95	1
step_all_val[200]	11	1			T9	1		T86	1		T22	1
step_all_val[201]	8	1			T7	1		T32	1		T217	1
step_all_val[203]	1	1			T273	1		-	-		-	-
step_all_val[204]	3	1			T122	1		T210	1		T353	1
step_all_val[205]	2	1			T53	1		T241	1		-	-
step_all_val[206]	6	1			T42	1		T128	1		T141	1
step_all_val[207]	3	1			T57	1		T354	1		T355	1
step_all_val[208]	4	1			T41	1		T104	1		T356	1
step_all_val[209]	4	1			T276	1		T193	1		T134	1
step_all_val[210]	8	1			T130	1		T55	1		T322	1
step_all_val[211]	6	1			T20	1		T151	1		T119	1
step_all_val[212]	2	1			T2	1		T107	1		-	-
step_all_val[213]	11	1			T9	1		T109	1		T264	1
step_all_val[214]	3	1			T102	1		T143	1		T285	1
step_all_val[215]	5	1			T103	1		T274	1		T170	1
step_all_val[216]	2	1			T32	1		T95	1		-	-
step_all_val[217]	4	1			T135	1		T147	1		T208	1
step_all_val[218]	3	1			T86	1		T141	1		T188	1
step_all_val[219]	3	1			T192	1		T250	1		T253	1
step_all_val[220]	1	1			T96	1		-	-		-	-
step_all_val[221]	5	1			T196	1		T120	1		T260	1
step_all_val[222]	6	1			T90	1		T122	1		T264	1
step_all_val[223]	5	1			T223	2		T134	1		T157	1
step_all_val[224]	2	1			T276	1		T341	1		-	-
step_all_val[225]	8	1			T113	1		T20	1		T174	1
step_all_val[226]	5	1			T41	1		T111	2		T177	1
step_all_val[227]	3	1			T9	1		T151	1		T179	1
step_all_val[228]	7	1			T7	1		T41	1		T152	1
step_all_val[229]	1	1			T292	1		-	-		-	-
step_all_val[230]	5	1			T118	1		T144	1		T57	1
step_all_val[231]	7	1			T90	1		T87	1		T211	1
step_all_val[233]	3	1			T144	1		T201	1		T189	1
step_all_val[234]	5	1			T89	1		T298	1		T333	1
step_all_val[235]	2	1			T158	1		T316	1		-	-
step_all_val[236]	5	1			T53	1		T151	1		T182	1
step_all_val[237]	8	1			T94	1		T255	1		T217	1
step_all_val[238]	4	1			T8	1		T181	1		T357	1
step_all_val[239]	4	1			T100	1		T244	1		T263	1
step_all_val[240]	4	1			T125	1		T277	1		T314	1
step_all_val[241]	6	1			T32	1		T156	1		T326	1
step_all_val[242]	4	1			T300	1		T278	1		T358	1
step_all_val[243]	5	1			T105	1		T54	1		T167	1
step_all_val[244]	4	1			T144	1		T178	1		T220	1
step_all_val[245]	8	1			T126	1		T125	1		T190	1
step_all_val[246]	5	1			T182	1		T128	1		T264	1
step_all_val[247]	6	1			T89	1		T95	1		T209	1
step_all_val[248]	4	1			T174	1		T206	1		T220	1
step_all_val[249]	4	1			T95	1		T144	1		T165	1
step_all_val[250]	7	1			T254	1		T54	1		T196	1
step_all_val[251]	3	1			T264	1		T252	1		T199	1
step_all_val[252]	2	1			T186	1		T258	1		-	-
step_all_val[253]	3	1			T311	1		T359	1		T233	1
step_all_val[254]	12	1			T88	1		T54	1		T97	1
step_all_val[255]	6	1			T118	1		T122	1		T136	1