Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.60 99.36 99.04 100.00 100.00 100.00 99.21


Total test records in report: 582
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T508 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2400761427 Aug 19 05:03:56 PM PDT 24 Aug 19 05:03:57 PM PDT 24 115049999 ps
T509 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1809734308 Aug 19 05:03:38 PM PDT 24 Aug 19 05:03:39 PM PDT 24 29211817 ps
T510 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.992520387 Aug 19 05:03:37 PM PDT 24 Aug 19 05:03:38 PM PDT 24 63299399 ps
T511 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3122922213 Aug 19 05:03:32 PM PDT 24 Aug 19 05:03:33 PM PDT 24 55344476 ps
T512 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3090736777 Aug 19 05:03:57 PM PDT 24 Aug 19 05:03:57 PM PDT 24 85920985 ps
T513 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2273205569 Aug 19 05:04:05 PM PDT 24 Aug 19 05:04:06 PM PDT 24 36126045 ps
T514 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3949317460 Aug 19 05:04:05 PM PDT 24 Aug 19 05:04:06 PM PDT 24 92693600 ps
T515 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2324809799 Aug 19 05:04:06 PM PDT 24 Aug 19 05:04:07 PM PDT 24 20633879 ps
T516 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1099181320 Aug 19 05:03:33 PM PDT 24 Aug 19 05:03:35 PM PDT 24 723746392 ps
T517 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3430649786 Aug 19 05:03:35 PM PDT 24 Aug 19 05:03:36 PM PDT 24 19523139 ps
T518 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4283246657 Aug 19 05:04:03 PM PDT 24 Aug 19 05:04:05 PM PDT 24 111661484 ps
T519 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3618893788 Aug 19 05:03:57 PM PDT 24 Aug 19 05:03:59 PM PDT 24 175592624 ps
T520 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2017889652 Aug 19 05:03:52 PM PDT 24 Aug 19 05:03:53 PM PDT 24 50120016 ps
T521 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.4258216304 Aug 19 05:04:00 PM PDT 24 Aug 19 05:04:01 PM PDT 24 21166081 ps
T522 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.82001121 Aug 19 05:03:35 PM PDT 24 Aug 19 05:03:36 PM PDT 24 29223875 ps
T83 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3673060638 Aug 19 05:03:54 PM PDT 24 Aug 19 05:03:55 PM PDT 24 133368444 ps
T523 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3556787572 Aug 19 05:04:07 PM PDT 24 Aug 19 05:04:08 PM PDT 24 50868210 ps
T524 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2330532565 Aug 19 05:03:38 PM PDT 24 Aug 19 05:03:39 PM PDT 24 39951561 ps
T525 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.672660104 Aug 19 05:04:06 PM PDT 24 Aug 19 05:04:06 PM PDT 24 47381622 ps
T526 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.4259364871 Aug 19 05:04:05 PM PDT 24 Aug 19 05:04:06 PM PDT 24 37405749 ps
T527 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1721732927 Aug 19 05:03:56 PM PDT 24 Aug 19 05:03:57 PM PDT 24 40553842 ps
T72 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1092788227 Aug 19 05:03:39 PM PDT 24 Aug 19 05:03:40 PM PDT 24 125387222 ps
T73 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.789015999 Aug 19 05:03:50 PM PDT 24 Aug 19 05:03:50 PM PDT 24 35177201 ps
T528 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.691063733 Aug 19 05:03:50 PM PDT 24 Aug 19 05:03:51 PM PDT 24 59063316 ps
T529 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.108437920 Aug 19 05:03:57 PM PDT 24 Aug 19 05:03:57 PM PDT 24 55156579 ps
T530 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3143609439 Aug 19 05:03:55 PM PDT 24 Aug 19 05:03:56 PM PDT 24 71461312 ps
T74 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1493463180 Aug 19 05:04:03 PM PDT 24 Aug 19 05:04:03 PM PDT 24 47845374 ps
T531 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3185924156 Aug 19 05:04:01 PM PDT 24 Aug 19 05:04:02 PM PDT 24 13791218 ps
T532 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1974954502 Aug 19 05:04:06 PM PDT 24 Aug 19 05:04:06 PM PDT 24 18638033 ps
T533 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1550995143 Aug 19 05:03:56 PM PDT 24 Aug 19 05:03:56 PM PDT 24 54927616 ps
T534 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1568289220 Aug 19 05:04:05 PM PDT 24 Aug 19 05:04:06 PM PDT 24 35266171 ps
T535 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2241412572 Aug 19 05:04:00 PM PDT 24 Aug 19 05:04:01 PM PDT 24 22132874 ps
T536 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1129993109 Aug 19 05:03:39 PM PDT 24 Aug 19 05:03:40 PM PDT 24 38338372 ps
T537 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3218196505 Aug 19 05:04:00 PM PDT 24 Aug 19 05:04:01 PM PDT 24 11427582 ps
T538 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.293340893 Aug 19 05:03:50 PM PDT 24 Aug 19 05:03:51 PM PDT 24 67728110 ps
T539 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1982921624 Aug 19 05:04:07 PM PDT 24 Aug 19 05:04:08 PM PDT 24 32310668 ps
T540 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.382247601 Aug 19 05:03:49 PM PDT 24 Aug 19 05:03:50 PM PDT 24 157449626 ps
T541 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3064954614 Aug 19 05:03:33 PM PDT 24 Aug 19 05:03:34 PM PDT 24 37327579 ps
T542 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4080629046 Aug 19 05:03:53 PM PDT 24 Aug 19 05:03:54 PM PDT 24 17658896 ps
T543 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2211540303 Aug 19 05:03:56 PM PDT 24 Aug 19 05:03:58 PM PDT 24 353879085 ps
T84 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.361455928 Aug 19 05:03:39 PM PDT 24 Aug 19 05:03:40 PM PDT 24 101251574 ps
T544 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1951523708 Aug 19 05:04:11 PM PDT 24 Aug 19 05:04:12 PM PDT 24 83199889 ps
T545 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1840378819 Aug 19 05:04:06 PM PDT 24 Aug 19 05:04:07 PM PDT 24 14225568 ps
T546 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.4052928175 Aug 19 05:03:35 PM PDT 24 Aug 19 05:03:36 PM PDT 24 18681403 ps
T547 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.161410655 Aug 19 05:03:55 PM PDT 24 Aug 19 05:03:56 PM PDT 24 31110525 ps
T548 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3110839276 Aug 19 05:04:00 PM PDT 24 Aug 19 05:04:02 PM PDT 24 224437644 ps
T549 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.929230176 Aug 19 05:03:53 PM PDT 24 Aug 19 05:03:54 PM PDT 24 43475814 ps
T550 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.591942679 Aug 19 05:04:05 PM PDT 24 Aug 19 05:04:07 PM PDT 24 324896291 ps
T551 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1034387263 Aug 19 05:04:02 PM PDT 24 Aug 19 05:04:04 PM PDT 24 122586177 ps
T552 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.4028006650 Aug 19 05:03:53 PM PDT 24 Aug 19 05:03:54 PM PDT 24 31580598 ps
T553 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2639257045 Aug 19 05:03:39 PM PDT 24 Aug 19 05:03:39 PM PDT 24 22488905 ps
T554 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.413101065 Aug 19 05:04:11 PM PDT 24 Aug 19 05:04:12 PM PDT 24 28159766 ps
T555 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.711999266 Aug 19 05:03:58 PM PDT 24 Aug 19 05:04:01 PM PDT 24 733485993 ps
T556 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4030935289 Aug 19 05:04:11 PM PDT 24 Aug 19 05:04:12 PM PDT 24 62212467 ps
T557 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.128099430 Aug 19 05:03:50 PM PDT 24 Aug 19 05:03:50 PM PDT 24 12499195 ps
T558 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.37276477 Aug 19 05:03:53 PM PDT 24 Aug 19 05:03:54 PM PDT 24 134747368 ps
T559 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1537534533 Aug 19 05:04:07 PM PDT 24 Aug 19 05:04:07 PM PDT 24 24351846 ps
T560 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3337122262 Aug 19 05:03:59 PM PDT 24 Aug 19 05:04:00 PM PDT 24 18117540 ps
T561 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.4057427713 Aug 19 05:03:35 PM PDT 24 Aug 19 05:03:36 PM PDT 24 54598844 ps
T562 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2415954181 Aug 19 05:04:08 PM PDT 24 Aug 19 05:04:09 PM PDT 24 89554964 ps
T563 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2938493452 Aug 19 05:04:10 PM PDT 24 Aug 19 05:04:11 PM PDT 24 18414811 ps
T564 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3745737497 Aug 19 05:03:35 PM PDT 24 Aug 19 05:03:36 PM PDT 24 12914874 ps
T85 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1213896563 Aug 19 05:03:52 PM PDT 24 Aug 19 05:03:53 PM PDT 24 148237104 ps
T565 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3188428322 Aug 19 05:04:02 PM PDT 24 Aug 19 05:04:04 PM PDT 24 97596104 ps
T566 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1664746874 Aug 19 05:03:51 PM PDT 24 Aug 19 05:03:53 PM PDT 24 220568614 ps
T567 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3988953793 Aug 19 05:04:06 PM PDT 24 Aug 19 05:04:07 PM PDT 24 29812903 ps
T568 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.366497968 Aug 19 05:03:56 PM PDT 24 Aug 19 05:03:56 PM PDT 24 15925789 ps
T569 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.483234620 Aug 19 05:03:49 PM PDT 24 Aug 19 05:03:53 PM PDT 24 326477106 ps
T570 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2144629157 Aug 19 05:03:35 PM PDT 24 Aug 19 05:03:36 PM PDT 24 32173161 ps
T571 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.101641361 Aug 19 05:04:01 PM PDT 24 Aug 19 05:04:02 PM PDT 24 16506794 ps
T572 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1883331633 Aug 19 05:04:06 PM PDT 24 Aug 19 05:04:07 PM PDT 24 14667615 ps
T573 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3897852090 Aug 19 05:03:35 PM PDT 24 Aug 19 05:03:36 PM PDT 24 50941871 ps
T574 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.81103612 Aug 19 05:04:02 PM PDT 24 Aug 19 05:04:03 PM PDT 24 287277061 ps
T575 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.702524152 Aug 19 05:03:37 PM PDT 24 Aug 19 05:03:39 PM PDT 24 97691725 ps
T576 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.4097637655 Aug 19 05:03:59 PM PDT 24 Aug 19 05:04:00 PM PDT 24 17175966 ps
T577 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.705210293 Aug 19 05:03:38 PM PDT 24 Aug 19 05:03:39 PM PDT 24 67877149 ps
T578 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3162788512 Aug 19 05:04:11 PM PDT 24 Aug 19 05:04:12 PM PDT 24 14361127 ps
T579 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4256270195 Aug 19 05:04:05 PM PDT 24 Aug 19 05:04:06 PM PDT 24 21306311 ps
T580 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.406335774 Aug 19 05:04:02 PM PDT 24 Aug 19 05:04:03 PM PDT 24 36529691 ps
T581 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3392885112 Aug 19 05:04:01 PM PDT 24 Aug 19 05:04:02 PM PDT 24 13609046 ps
T75 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2079906261 Aug 19 05:04:02 PM PDT 24 Aug 19 05:04:03 PM PDT 24 11778654 ps
T582 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2863240585 Aug 19 05:04:05 PM PDT 24 Aug 19 05:04:06 PM PDT 24 84976785 ps

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.2602225540
Short name T4
Test name
Test status
Simulation time 5601294550 ps
CPU time 41.42 seconds
Started Aug 19 04:37:32 PM PDT 24
Finished Aug 19 04:38:13 PM PDT 24
Peak memory 198248 kb
Host smart-0f036cff-8b1f-45c5-b5bf-22f880100e9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602225540 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.2602225540
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1558650173
Short name T3
Test name
Test status
Simulation time 421351581675 ps
CPU time 183.47 seconds
Started Aug 19 04:37:19 PM PDT 24
Finished Aug 19 04:40:23 PM PDT 24
Peak memory 183588 kb
Host smart-05005e7e-9465-437e-bf5c-0261a45e7913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558650173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1558650173
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1280793925
Short name T95
Test name
Test status
Simulation time 710325644993 ps
CPU time 6583.79 seconds
Started Aug 19 04:37:14 PM PDT 24
Finished Aug 19 06:26:59 PM PDT 24
Peak memory 191808 kb
Host smart-9da24d1d-a867-4c4b-9dae-7578956bd731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280793925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1280793925
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1401978876
Short name T27
Test name
Test status
Simulation time 394417391 ps
CPU time 1.39 seconds
Started Aug 19 05:04:10 PM PDT 24
Finished Aug 19 05:04:12 PM PDT 24
Peak memory 196132 kb
Host smart-66bf7b33-8066-43ee-aced-565780acd680
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401978876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1401978876
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.397023596
Short name T54
Test name
Test status
Simulation time 6915394726601 ps
CPU time 1543.53 seconds
Started Aug 19 04:37:49 PM PDT 24
Finished Aug 19 05:03:33 PM PDT 24
Peak memory 197136 kb
Host smart-821bc99f-7614-402d-ae8c-6fad2b619474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397023596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
397023596
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1754224339
Short name T32
Test name
Test status
Simulation time 7886178376287 ps
CPU time 3468.8 seconds
Started Aug 19 04:37:45 PM PDT 24
Finished Aug 19 05:35:34 PM PDT 24
Peak memory 196584 kb
Host smart-aab84f30-bda7-417f-af7b-55c570c504df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754224339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1754224339
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.591257882
Short name T117
Test name
Test status
Simulation time 694796636820 ps
CPU time 2385.26 seconds
Started Aug 19 04:37:52 PM PDT 24
Finished Aug 19 05:17:38 PM PDT 24
Peak memory 197376 kb
Host smart-9524b925-0c04-4377-b0b7-397aa81446b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591257882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
591257882
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3219116212
Short name T53
Test name
Test status
Simulation time 2921538365956 ps
CPU time 1214.47 seconds
Started Aug 19 04:37:10 PM PDT 24
Finished Aug 19 04:57:25 PM PDT 24
Peak memory 196216 kb
Host smart-aca8a6bd-9dc5-4836-82fd-afbb956e5a76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219116212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3219116212
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/144.rv_timer_random.3884848702
Short name T9
Test name
Test status
Simulation time 681081169365 ps
CPU time 663.33 seconds
Started Aug 19 04:38:08 PM PDT 24
Finished Aug 19 04:49:11 PM PDT 24
Peak memory 191780 kb
Host smart-e46f92ac-3438-4240-83fd-870072610a11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884848702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3884848702
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1236179061
Short name T56
Test name
Test status
Simulation time 1144492687901 ps
CPU time 1131.17 seconds
Started Aug 19 04:37:43 PM PDT 24
Finished Aug 19 04:56:35 PM PDT 24
Peak memory 191784 kb
Host smart-fa3fcb56-1f42-4ff0-aa39-e97d1a6e0067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236179061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1236179061
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3145217122
Short name T47
Test name
Test status
Simulation time 15041015 ps
CPU time 0.55 seconds
Started Aug 19 05:03:35 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 183280 kb
Host smart-9466288e-6885-4d86-a83f-1ace351a7b27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145217122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3145217122
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2291143866
Short name T215
Test name
Test status
Simulation time 646682831664 ps
CPU time 2403.31 seconds
Started Aug 19 04:37:48 PM PDT 24
Finished Aug 19 05:17:53 PM PDT 24
Peak memory 191784 kb
Host smart-1d32eeba-7aa0-4bad-b170-0bf7d2b6a8f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291143866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2291143866
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.76878139
Short name T13
Test name
Test status
Simulation time 59912707 ps
CPU time 0.79 seconds
Started Aug 19 04:37:11 PM PDT 24
Finished Aug 19 04:37:12 PM PDT 24
Peak memory 214656 kb
Host smart-e8e60205-52c5-4dea-bb41-4a508349e39b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76878139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.76878139
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2217991714
Short name T57
Test name
Test status
Simulation time 365625794694 ps
CPU time 682.7 seconds
Started Aug 19 04:37:15 PM PDT 24
Finished Aug 19 04:48:38 PM PDT 24
Peak memory 196320 kb
Host smart-89eedb5b-2ef9-4eb7-ac11-29368e5c7cd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217991714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2217991714
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3475232511
Short name T316
Test name
Test status
Simulation time 911581899103 ps
CPU time 1032.97 seconds
Started Aug 19 04:37:47 PM PDT 24
Finished Aug 19 04:55:00 PM PDT 24
Peak memory 196544 kb
Host smart-123d7b61-7be6-468b-9562-3bc7f0d20c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475232511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3475232511
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/107.rv_timer_random.1615649923
Short name T206
Test name
Test status
Simulation time 610901338334 ps
CPU time 310.37 seconds
Started Aug 19 04:38:04 PM PDT 24
Finished Aug 19 04:43:15 PM PDT 24
Peak memory 192864 kb
Host smart-9f741214-67e9-447b-96f0-f1b74aeb488f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615649923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1615649923
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2977039876
Short name T248
Test name
Test status
Simulation time 767393972651 ps
CPU time 2215.09 seconds
Started Aug 19 04:37:30 PM PDT 24
Finished Aug 19 05:14:25 PM PDT 24
Peak memory 191784 kb
Host smart-cb304fe9-f000-427a-975c-954f02353ecb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977039876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2977039876
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.779585706
Short name T132
Test name
Test status
Simulation time 500511071611 ps
CPU time 904.34 seconds
Started Aug 19 04:37:33 PM PDT 24
Finished Aug 19 04:52:38 PM PDT 24
Peak memory 195356 kb
Host smart-57cb56bb-12dc-4119-917e-af0b0b6669e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779585706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
779585706
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2691028354
Short name T144
Test name
Test status
Simulation time 453712159581 ps
CPU time 406.05 seconds
Started Aug 19 04:37:39 PM PDT 24
Finished Aug 19 04:44:25 PM PDT 24
Peak memory 191784 kb
Host smart-9b7ac831-145b-4e92-b290-4e0d8990caa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691028354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2691028354
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.225882821
Short name T60
Test name
Test status
Simulation time 364141386790 ps
CPU time 782.27 seconds
Started Aug 19 04:37:16 PM PDT 24
Finished Aug 19 04:50:18 PM PDT 24
Peak memory 191772 kb
Host smart-5fc1023f-3023-479b-a020-1c517625b97e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225882821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
225882821
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/135.rv_timer_random.1744198009
Short name T246
Test name
Test status
Simulation time 102851080599 ps
CPU time 496.01 seconds
Started Aug 19 04:38:12 PM PDT 24
Finished Aug 19 04:46:28 PM PDT 24
Peak memory 191812 kb
Host smart-cc7e7442-d5ca-45cd-853a-d56cc7f72e6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744198009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1744198009
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2271851212
Short name T234
Test name
Test status
Simulation time 4786333088227 ps
CPU time 1080.27 seconds
Started Aug 19 04:37:37 PM PDT 24
Finished Aug 19 04:55:37 PM PDT 24
Peak memory 191700 kb
Host smart-272a3e20-31fa-435e-9d7f-5b8fbf5373c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271851212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2271851212
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.4160426301
Short name T173
Test name
Test status
Simulation time 571411587027 ps
CPU time 507.03 seconds
Started Aug 19 04:36:57 PM PDT 24
Finished Aug 19 04:45:24 PM PDT 24
Peak memory 196564 kb
Host smart-75f8f5a5-ef70-45d1-83ce-33cc80ca17ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160426301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
4160426301
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/149.rv_timer_random.185864615
Short name T267
Test name
Test status
Simulation time 213463741330 ps
CPU time 403.61 seconds
Started Aug 19 04:38:05 PM PDT 24
Finished Aug 19 04:44:49 PM PDT 24
Peak memory 191812 kb
Host smart-f467e89f-5736-40af-b81d-f76df862a995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185864615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.185864615
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2430612053
Short name T10
Test name
Test status
Simulation time 335072391019 ps
CPU time 510.09 seconds
Started Aug 19 04:37:59 PM PDT 24
Finished Aug 19 04:46:29 PM PDT 24
Peak memory 191812 kb
Host smart-2f1e1303-ddb0-4dfa-a3c3-3ef2af1cc298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430612053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2430612053
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1044071608
Short name T317
Test name
Test status
Simulation time 113376529973 ps
CPU time 625.78 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:48:28 PM PDT 24
Peak memory 191792 kb
Host smart-36d9efca-3051-46ae-8506-8d280eb2f564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044071608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1044071608
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.858676827
Short name T220
Test name
Test status
Simulation time 2276475222247 ps
CPU time 2018.1 seconds
Started Aug 19 04:37:59 PM PDT 24
Finished Aug 19 05:11:38 PM PDT 24
Peak memory 191808 kb
Host smart-2888016d-2310-41da-a582-334821dbc7d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858676827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.858676827
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.473729627
Short name T106
Test name
Test status
Simulation time 93523613871 ps
CPU time 138.9 seconds
Started Aug 19 04:38:17 PM PDT 24
Finished Aug 19 04:40:36 PM PDT 24
Peak memory 191788 kb
Host smart-960f68f6-dba2-4fbc-a293-95d9c6e2a633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473729627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.473729627
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1433344652
Short name T200
Test name
Test status
Simulation time 572951728323 ps
CPU time 474.84 seconds
Started Aug 19 04:37:59 PM PDT 24
Finished Aug 19 04:45:54 PM PDT 24
Peak memory 191824 kb
Host smart-31c3042f-b682-42b4-a803-8aa6f1771b29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433344652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1433344652
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3139504225
Short name T141
Test name
Test status
Simulation time 111696645424 ps
CPU time 298.14 seconds
Started Aug 19 04:37:57 PM PDT 24
Finished Aug 19 04:42:56 PM PDT 24
Peak memory 191336 kb
Host smart-abcdc214-dfe0-42e9-887e-24c94adf33f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139504225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3139504225
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.886900605
Short name T306
Test name
Test status
Simulation time 307160141447 ps
CPU time 1019.22 seconds
Started Aug 19 04:37:56 PM PDT 24
Finished Aug 19 04:54:56 PM PDT 24
Peak memory 191812 kb
Host smart-2d20fb4e-b8e6-4280-bedc-3a95e209d9b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886900605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.886900605
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2669961447
Short name T184
Test name
Test status
Simulation time 84088655090 ps
CPU time 361.99 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:44:05 PM PDT 24
Peak memory 191800 kb
Host smart-e429a44b-e895-4bd2-9df8-c2b0960790a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669961447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2669961447
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.763630711
Short name T308
Test name
Test status
Simulation time 1203359169736 ps
CPU time 512.22 seconds
Started Aug 19 04:37:45 PM PDT 24
Finished Aug 19 04:46:18 PM PDT 24
Peak memory 196256 kb
Host smart-fbc83426-a110-40b4-872e-ac94cff3c133
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763630711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
763630711
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1661271663
Short name T90
Test name
Test status
Simulation time 396508055006 ps
CPU time 1046.96 seconds
Started Aug 19 04:37:44 PM PDT 24
Finished Aug 19 04:55:11 PM PDT 24
Peak memory 191776 kb
Host smart-eb88da6b-de0f-4953-ba04-e5441d669272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661271663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1661271663
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1918718277
Short name T217
Test name
Test status
Simulation time 699249336206 ps
CPU time 874.01 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 04:52:25 PM PDT 24
Peak memory 191716 kb
Host smart-3af04868-5f07-43f3-9c43-41972ef8cef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918718277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1918718277
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.1903742194
Short name T278
Test name
Test status
Simulation time 402641719982 ps
CPU time 877.99 seconds
Started Aug 19 04:38:09 PM PDT 24
Finished Aug 19 04:52:47 PM PDT 24
Peak memory 191780 kb
Host smart-b4154688-4071-4973-b0e3-b76f37c8c4df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903742194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1903742194
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.4236116351
Short name T250
Test name
Test status
Simulation time 50736948854 ps
CPU time 23.63 seconds
Started Aug 19 04:37:21 PM PDT 24
Finished Aug 19 04:37:44 PM PDT 24
Peak memory 183620 kb
Host smart-632821bf-3b96-41c5-b2c8-f2746ec9dff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236116351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4236116351
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.4140391257
Short name T284
Test name
Test status
Simulation time 208071983001 ps
CPU time 236.69 seconds
Started Aug 19 04:38:04 PM PDT 24
Finished Aug 19 04:42:01 PM PDT 24
Peak memory 191812 kb
Host smart-18aaf9f7-9639-4f02-95e5-f8d45998c187
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140391257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.4140391257
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.4007094134
Short name T170
Test name
Test status
Simulation time 587007726204 ps
CPU time 1060.27 seconds
Started Aug 19 04:37:40 PM PDT 24
Finished Aug 19 04:55:20 PM PDT 24
Peak memory 191812 kb
Host smart-237d914b-c498-479d-b0f9-565a6ef84b27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007094134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.4007094134
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1899541572
Short name T331
Test name
Test status
Simulation time 318696817891 ps
CPU time 717.84 seconds
Started Aug 19 04:38:10 PM PDT 24
Finished Aug 19 04:50:08 PM PDT 24
Peak memory 191808 kb
Host smart-2985ab00-1ab1-4549-bb98-43e56306f413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899541572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1899541572
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1925358078
Short name T178
Test name
Test status
Simulation time 418755223315 ps
CPU time 474.09 seconds
Started Aug 19 04:37:58 PM PDT 24
Finished Aug 19 04:45:53 PM PDT 24
Peak memory 191788 kb
Host smart-6748287d-ea5d-4963-8d30-0e6313f9a919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925358078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1925358078
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3980867477
Short name T264
Test name
Test status
Simulation time 230485490573 ps
CPU time 329.14 seconds
Started Aug 19 04:37:56 PM PDT 24
Finished Aug 19 04:43:26 PM PDT 24
Peak memory 191784 kb
Host smart-ed360902-292a-461a-a112-f223f589e21e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980867477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3980867477
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.298866919
Short name T290
Test name
Test status
Simulation time 498992748982 ps
CPU time 269.2 seconds
Started Aug 19 04:37:18 PM PDT 24
Finished Aug 19 04:41:47 PM PDT 24
Peak memory 191796 kb
Host smart-d2fb9dfe-b787-4590-b356-9387dde012b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298866919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
298866919
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/147.rv_timer_random.2175920392
Short name T276
Test name
Test status
Simulation time 696585519722 ps
CPU time 864.19 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:52:28 PM PDT 24
Peak memory 194080 kb
Host smart-ad7993b2-92b2-40e3-a8e3-02a88482f616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175920392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2175920392
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.636513098
Short name T125
Test name
Test status
Simulation time 104011950897 ps
CPU time 158.44 seconds
Started Aug 19 04:38:01 PM PDT 24
Finished Aug 19 04:40:39 PM PDT 24
Peak memory 191788 kb
Host smart-4045f0bd-2685-4c9b-8a65-8e4e21a32a8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636513098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.636513098
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2720412426
Short name T167
Test name
Test status
Simulation time 356748049784 ps
CPU time 973.88 seconds
Started Aug 19 04:38:17 PM PDT 24
Finished Aug 19 04:54:31 PM PDT 24
Peak memory 191812 kb
Host smart-e4c285af-6a64-4dd7-852b-710fc3776f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720412426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2720412426
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3777757315
Short name T422
Test name
Test status
Simulation time 441752600364 ps
CPU time 250.83 seconds
Started Aug 19 04:37:46 PM PDT 24
Finished Aug 19 04:41:56 PM PDT 24
Peak memory 183588 kb
Host smart-b0befd31-1134-46d8-84ba-24629b444e92
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777757315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3777757315
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/72.rv_timer_random.610438887
Short name T310
Test name
Test status
Simulation time 228742003438 ps
CPU time 824.43 seconds
Started Aug 19 04:37:58 PM PDT 24
Finished Aug 19 04:51:43 PM PDT 24
Peak memory 191772 kb
Host smart-566e4a3a-ec57-421b-8bd5-d4fa7ee5e0c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610438887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.610438887
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2788300653
Short name T186
Test name
Test status
Simulation time 286080216722 ps
CPU time 291.05 seconds
Started Aug 19 04:37:49 PM PDT 24
Finished Aug 19 04:42:41 PM PDT 24
Peak memory 191684 kb
Host smart-308eb9f8-dbc6-4920-b253-bd631bb85f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788300653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2788300653
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2358137795
Short name T263
Test name
Test status
Simulation time 619687159732 ps
CPU time 642.31 seconds
Started Aug 19 04:37:55 PM PDT 24
Finished Aug 19 04:48:38 PM PDT 24
Peak memory 191780 kb
Host smart-b6755829-489c-4da8-8c65-fc8078fd2507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358137795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2358137795
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2664964330
Short name T156
Test name
Test status
Simulation time 133337680913 ps
CPU time 634.1 seconds
Started Aug 19 04:38:04 PM PDT 24
Finished Aug 19 04:48:38 PM PDT 24
Peak memory 191708 kb
Host smart-8e06f0b8-ec0a-4aab-a69e-f5af6753863a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664964330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2664964330
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1590126209
Short name T7
Test name
Test status
Simulation time 154726913439 ps
CPU time 273.12 seconds
Started Aug 19 04:38:08 PM PDT 24
Finished Aug 19 04:42:42 PM PDT 24
Peak memory 191768 kb
Host smart-1a0ec4e5-2aac-44be-b397-f8df5ef72dfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590126209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1590126209
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1933239586
Short name T134
Test name
Test status
Simulation time 1546210598718 ps
CPU time 892.24 seconds
Started Aug 19 04:38:26 PM PDT 24
Finished Aug 19 04:53:18 PM PDT 24
Peak memory 191808 kb
Host smart-64bc03f3-28b4-4ca9-ac95-308a006d263e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933239586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1933239586
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.798674285
Short name T166
Test name
Test status
Simulation time 215006511873 ps
CPU time 159.6 seconds
Started Aug 19 04:38:19 PM PDT 24
Finished Aug 19 04:40:59 PM PDT 24
Peak memory 191692 kb
Host smart-1e67ae39-f537-4490-97d1-f39da8282dd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798674285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.798674285
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2120519645
Short name T255
Test name
Test status
Simulation time 710749672823 ps
CPU time 623.13 seconds
Started Aug 19 04:37:38 PM PDT 24
Finished Aug 19 04:48:01 PM PDT 24
Peak memory 183548 kb
Host smart-a22f2d47-745f-4982-b6c3-7f37d0c65fd4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120519645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2120519645
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random.2548125495
Short name T113
Test name
Test status
Simulation time 156251533186 ps
CPU time 382.33 seconds
Started Aug 19 04:37:43 PM PDT 24
Finished Aug 19 04:44:05 PM PDT 24
Peak memory 191808 kb
Host smart-d13e0959-e471-4280-9cf8-26c3c91ddba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548125495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2548125495
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.526978115
Short name T270
Test name
Test status
Simulation time 888057120834 ps
CPU time 480.91 seconds
Started Aug 19 04:37:44 PM PDT 24
Finished Aug 19 04:45:45 PM PDT 24
Peak memory 191816 kb
Host smart-d8d90f71-0842-4421-830b-c195f36083dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526978115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.526978115
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random.3591054675
Short name T143
Test name
Test status
Simulation time 232547347291 ps
CPU time 196.4 seconds
Started Aug 19 04:37:47 PM PDT 24
Finished Aug 19 04:41:03 PM PDT 24
Peak memory 191756 kb
Host smart-5166d08b-15e1-413c-8f2b-feebb86bab37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591054675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3591054675
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.906739453
Short name T135
Test name
Test status
Simulation time 330856473830 ps
CPU time 1474 seconds
Started Aug 19 04:38:01 PM PDT 24
Finished Aug 19 05:02:35 PM PDT 24
Peak memory 191732 kb
Host smart-26b4e531-ede2-4d5a-8464-c43a04c056c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906739453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.906739453
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2795080759
Short name T78
Test name
Test status
Simulation time 27647052 ps
CPU time 0.69 seconds
Started Aug 19 05:03:34 PM PDT 24
Finished Aug 19 05:03:34 PM PDT 24
Peak memory 192556 kb
Host smart-ce24904e-0163-4b66-b1eb-ee1a328214fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795080759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2795080759
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1493463180
Short name T74
Test name
Test status
Simulation time 47845374 ps
CPU time 0.64 seconds
Started Aug 19 05:04:03 PM PDT 24
Finished Aug 19 05:04:03 PM PDT 24
Peak memory 183404 kb
Host smart-8c052552-1a3e-47c3-a28b-e6f882da9c70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493463180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1493463180
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1416026659
Short name T177
Test name
Test status
Simulation time 543265310203 ps
CPU time 942.81 seconds
Started Aug 19 04:37:15 PM PDT 24
Finished Aug 19 04:52:58 PM PDT 24
Peak memory 183592 kb
Host smart-763ef17b-f5b0-4fe5-ad3c-64be524807b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416026659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1416026659
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/109.rv_timer_random.2821808701
Short name T229
Test name
Test status
Simulation time 85038508544 ps
CPU time 587.04 seconds
Started Aug 19 04:37:57 PM PDT 24
Finished Aug 19 04:47:44 PM PDT 24
Peak memory 191808 kb
Host smart-3e736afd-7bcf-4067-9111-2cbd80a02d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821808701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2821808701
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2715801449
Short name T159
Test name
Test status
Simulation time 104947060108 ps
CPU time 155.16 seconds
Started Aug 19 04:37:23 PM PDT 24
Finished Aug 19 04:39:59 PM PDT 24
Peak memory 191768 kb
Host smart-617e3310-6083-47c6-9e2e-dcf5c5e7311d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715801449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2715801449
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_random.744742076
Short name T335
Test name
Test status
Simulation time 523786933659 ps
CPU time 1889.42 seconds
Started Aug 19 04:37:22 PM PDT 24
Finished Aug 19 05:08:52 PM PDT 24
Peak memory 191792 kb
Host smart-bcc92173-7700-45e5-937a-b95abde4ba78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744742076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.744742076
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random.981035406
Short name T312
Test name
Test status
Simulation time 89588430547 ps
CPU time 153.94 seconds
Started Aug 19 04:37:41 PM PDT 24
Finished Aug 19 04:40:15 PM PDT 24
Peak memory 191820 kb
Host smart-1cde389a-7f84-406e-b3c2-3f303dc6fadb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981035406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.981035406
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2735796062
Short name T314
Test name
Test status
Simulation time 559417592991 ps
CPU time 930.85 seconds
Started Aug 19 04:37:20 PM PDT 24
Finished Aug 19 04:52:51 PM PDT 24
Peak memory 183564 kb
Host smart-ace4edd3-bfbd-4cf2-805a-88136d1728f8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735796062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2735796062
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_random.515628889
Short name T96
Test name
Test status
Simulation time 8462037782 ps
CPU time 9.97 seconds
Started Aug 19 04:37:33 PM PDT 24
Finished Aug 19 04:37:43 PM PDT 24
Peak memory 191808 kb
Host smart-86581687-62d5-4ab4-bec5-0bd8a3473e26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515628889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.515628889
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.624539865
Short name T210
Test name
Test status
Simulation time 329402801715 ps
CPU time 1192.21 seconds
Started Aug 19 04:37:49 PM PDT 24
Finished Aug 19 04:57:41 PM PDT 24
Peak memory 191800 kb
Host smart-e388ca56-5ee8-42ef-9edc-59b14fd1b70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624539865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.624539865
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_random.3929386273
Short name T341
Test name
Test status
Simulation time 463974365265 ps
CPU time 840.69 seconds
Started Aug 19 04:37:48 PM PDT 24
Finished Aug 19 04:51:50 PM PDT 24
Peak memory 191820 kb
Host smart-680150c9-8716-492d-a7fa-74c712743326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929386273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3929386273
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.670331543
Short name T202
Test name
Test status
Simulation time 406024144071 ps
CPU time 611.51 seconds
Started Aug 19 04:37:54 PM PDT 24
Finished Aug 19 04:48:05 PM PDT 24
Peak memory 183568 kb
Host smart-d5e5beff-82ee-4ab7-a03b-55639a71f650
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670331543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.670331543
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_random.1191458131
Short name T94
Test name
Test status
Simulation time 137509470304 ps
CPU time 1688.77 seconds
Started Aug 19 04:37:13 PM PDT 24
Finished Aug 19 05:05:22 PM PDT 24
Peak memory 191336 kb
Host smart-9283120d-1fe1-4478-8560-311effbfebf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191458131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1191458131
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.50346060
Short name T192
Test name
Test status
Simulation time 1090432125919 ps
CPU time 1922.89 seconds
Started Aug 19 04:37:20 PM PDT 24
Finished Aug 19 05:09:23 PM PDT 24
Peak memory 191772 kb
Host smart-4e164cbb-b772-4d4e-8844-e00e98d26e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50346060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.50346060
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/54.rv_timer_random.34116055
Short name T176
Test name
Test status
Simulation time 626056778512 ps
CPU time 422.65 seconds
Started Aug 19 04:37:49 PM PDT 24
Finished Aug 19 04:44:52 PM PDT 24
Peak memory 191804 kb
Host smart-28035e4e-64af-4d9c-860f-f466e3627981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34116055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.34116055
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1961172614
Short name T131
Test name
Test status
Simulation time 206512576448 ps
CPU time 1009.03 seconds
Started Aug 19 04:37:55 PM PDT 24
Finished Aug 19 04:54:44 PM PDT 24
Peak memory 191820 kb
Host smart-80d56f10-48f5-43b2-910b-48fb3124da14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961172614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1961172614
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.469048928
Short name T311
Test name
Test status
Simulation time 200303212231 ps
CPU time 366.87 seconds
Started Aug 19 04:37:26 PM PDT 24
Finished Aug 19 04:43:33 PM PDT 24
Peak memory 183572 kb
Host smart-742d0690-29f0-4621-b18b-d29c46233542
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469048928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.469048928
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3989954133
Short name T50
Test name
Test status
Simulation time 229400808 ps
CPU time 1.14 seconds
Started Aug 19 05:03:59 PM PDT 24
Finished Aug 19 05:04:00 PM PDT 24
Peak memory 184112 kb
Host smart-0045a6d7-394a-4677-8d67-35f2d169552c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989954133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3989954133
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1864807525
Short name T409
Test name
Test status
Simulation time 110798421326 ps
CPU time 189.32 seconds
Started Aug 19 04:37:26 PM PDT 24
Finished Aug 19 04:40:40 PM PDT 24
Peak memory 183608 kb
Host smart-0a3c3b7c-c1d9-4b78-98a6-38cdcb42c3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864807525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1864807525
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2653322390
Short name T241
Test name
Test status
Simulation time 7185585339110 ps
CPU time 1655.54 seconds
Started Aug 19 04:37:35 PM PDT 24
Finished Aug 19 05:05:11 PM PDT 24
Peak memory 183548 kb
Host smart-6a44a868-d48b-47e2-a7f7-d38fb3527498
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653322390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2653322390
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/100.rv_timer_random.2408680975
Short name T232
Test name
Test status
Simulation time 464863265623 ps
CPU time 159.03 seconds
Started Aug 19 04:37:58 PM PDT 24
Finished Aug 19 04:40:37 PM PDT 24
Peak memory 191784 kb
Host smart-b324d8c4-f7e7-4728-8cd7-e44e7ff939d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408680975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2408680975
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1554013035
Short name T169
Test name
Test status
Simulation time 182283059060 ps
CPU time 1692.57 seconds
Started Aug 19 04:38:06 PM PDT 24
Finished Aug 19 05:06:19 PM PDT 24
Peak memory 191824 kb
Host smart-e9d75493-8053-466a-93db-4157270886f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554013035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1554013035
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.4182400506
Short name T97
Test name
Test status
Simulation time 543209659143 ps
CPU time 255.3 seconds
Started Aug 19 04:38:06 PM PDT 24
Finished Aug 19 04:42:22 PM PDT 24
Peak memory 191832 kb
Host smart-be7d4604-5f93-4319-aff0-0e5c98629dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182400506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.4182400506
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3485209985
Short name T455
Test name
Test status
Simulation time 1980788812554 ps
CPU time 1990.11 seconds
Started Aug 19 04:37:59 PM PDT 24
Finished Aug 19 05:11:09 PM PDT 24
Peak memory 191796 kb
Host smart-ffccf480-c41e-4606-bf1e-453f3df740ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485209985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3485209985
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.464729537
Short name T266
Test name
Test status
Simulation time 16563764522 ps
CPU time 35.43 seconds
Started Aug 19 04:37:15 PM PDT 24
Finished Aug 19 04:37:51 PM PDT 24
Peak memory 183544 kb
Host smart-68d1f9fd-94f9-41cf-9d72-c4a5e962fb74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464729537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.464729537
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2058384945
Short name T226
Test name
Test status
Simulation time 29412722491 ps
CPU time 43.56 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:38:47 PM PDT 24
Peak memory 183616 kb
Host smart-ba0e0dbf-ad7a-46ce-a382-9c8fcb4f565d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058384945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2058384945
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2449680904
Short name T142
Test name
Test status
Simulation time 731781390953 ps
CPU time 822.97 seconds
Started Aug 19 04:38:01 PM PDT 24
Finished Aug 19 04:51:44 PM PDT 24
Peak memory 191820 kb
Host smart-ebe1af0e-2a81-45c5-9ef9-43f7f68500e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449680904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2449680904
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1633108784
Short name T163
Test name
Test status
Simulation time 323115046055 ps
CPU time 641.79 seconds
Started Aug 19 04:38:05 PM PDT 24
Finished Aug 19 04:48:47 PM PDT 24
Peak memory 191800 kb
Host smart-763ecc6c-3717-49f8-8bcb-d48d55cf938c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633108784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1633108784
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.439951191
Short name T292
Test name
Test status
Simulation time 182373601050 ps
CPU time 153.77 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:40:36 PM PDT 24
Peak memory 191692 kb
Host smart-77e83830-b939-4bab-af78-048444726cc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439951191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.439951191
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.1997904261
Short name T351
Test name
Test status
Simulation time 67014273877 ps
CPU time 109.5 seconds
Started Aug 19 04:37:14 PM PDT 24
Finished Aug 19 04:39:04 PM PDT 24
Peak memory 183588 kb
Host smart-8cebc441-d6bd-437e-8969-2c80108ba6a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997904261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.1997904261
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/141.rv_timer_random.3580114572
Short name T258
Test name
Test status
Simulation time 77643899073 ps
CPU time 634.32 seconds
Started Aug 19 04:38:04 PM PDT 24
Finished Aug 19 04:48:38 PM PDT 24
Peak memory 191836 kb
Host smart-5759038f-3807-4469-a4ae-0747c4f71732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580114572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3580114572
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1694129976
Short name T2
Test name
Test status
Simulation time 674582369262 ps
CPU time 1021.83 seconds
Started Aug 19 04:37:26 PM PDT 24
Finished Aug 19 04:54:28 PM PDT 24
Peak memory 196064 kb
Host smart-760d60a6-dce4-46cd-ac03-b9f26db30843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694129976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1694129976
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/182.rv_timer_random.2625818515
Short name T149
Test name
Test status
Simulation time 91283052702 ps
CPU time 346.85 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:44:00 PM PDT 24
Peak memory 191752 kb
Host smart-1574c1e4-c44b-419d-be37-303a09c06aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625818515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2625818515
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1354960882
Short name T237
Test name
Test status
Simulation time 18963902678 ps
CPU time 24.1 seconds
Started Aug 19 04:38:00 PM PDT 24
Finished Aug 19 04:38:24 PM PDT 24
Peak memory 183608 kb
Host smart-f09b1664-612e-4382-96bb-ae75c55ddade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354960882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1354960882
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.328736398
Short name T111
Test name
Test status
Simulation time 138448332650 ps
CPU time 616.62 seconds
Started Aug 19 04:37:16 PM PDT 24
Finished Aug 19 04:47:33 PM PDT 24
Peak memory 191820 kb
Host smart-453321d5-390d-4cc0-828a-89d1c408aca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328736398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.328736398
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.881179715
Short name T89
Test name
Test status
Simulation time 322577627885 ps
CPU time 527.29 seconds
Started Aug 19 04:37:42 PM PDT 24
Finished Aug 19 04:46:30 PM PDT 24
Peak memory 183596 kb
Host smart-e883665e-5c8c-4ca6-bcd7-f659518b0aa0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881179715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.881179715
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_random.3320613153
Short name T124
Test name
Test status
Simulation time 152027740336 ps
CPU time 63.07 seconds
Started Aug 19 04:37:32 PM PDT 24
Finished Aug 19 04:38:36 PM PDT 24
Peak memory 183612 kb
Host smart-6197506b-9c94-4a73-b77d-fc1872f8e574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320613153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3320613153
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2882277163
Short name T212
Test name
Test status
Simulation time 244838962586 ps
CPU time 116.09 seconds
Started Aug 19 04:37:26 PM PDT 24
Finished Aug 19 04:39:22 PM PDT 24
Peak memory 183588 kb
Host smart-43fc1044-e5cf-417f-8a83-1420a1093b87
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882277163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2882277163
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_random.2017848655
Short name T230
Test name
Test status
Simulation time 284086434844 ps
CPU time 262.68 seconds
Started Aug 19 04:37:46 PM PDT 24
Finished Aug 19 04:42:09 PM PDT 24
Peak memory 191776 kb
Host smart-d977e1ee-d763-46d0-a2fc-5d1c1a682326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017848655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2017848655
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2008739489
Short name T289
Test name
Test status
Simulation time 24059710238 ps
CPU time 31.85 seconds
Started Aug 19 04:37:42 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 183372 kb
Host smart-6fa02d34-b2f0-4a6c-9637-c5f7c6188868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008739489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2008739489
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_random.2759048856
Short name T145
Test name
Test status
Simulation time 519720561999 ps
CPU time 362.88 seconds
Started Aug 19 04:37:46 PM PDT 24
Finished Aug 19 04:43:49 PM PDT 24
Peak memory 191764 kb
Host smart-3a87eecc-fc39-498f-9e74-5b6475c8a727
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759048856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2759048856
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2125352365
Short name T259
Test name
Test status
Simulation time 42509731452 ps
CPU time 67.86 seconds
Started Aug 19 04:37:43 PM PDT 24
Finished Aug 19 04:38:51 PM PDT 24
Peak memory 183540 kb
Host smart-929f1422-aba0-45f5-8929-42fdd7c8a626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125352365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2125352365
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_random.3528862698
Short name T280
Test name
Test status
Simulation time 345964993709 ps
CPU time 252.93 seconds
Started Aug 19 04:37:39 PM PDT 24
Finished Aug 19 04:41:52 PM PDT 24
Peak memory 191672 kb
Host smart-107ef8a3-dde3-4305-8b05-35b08c59d284
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528862698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3528862698
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.608232128
Short name T273
Test name
Test status
Simulation time 198863237987 ps
CPU time 2043.67 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 05:11:55 PM PDT 24
Peak memory 191784 kb
Host smart-d053f8a5-eb55-4936-833e-e62b79ffcc5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608232128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
608232128
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3234764977
Short name T323
Test name
Test status
Simulation time 58056639772 ps
CPU time 1027.15 seconds
Started Aug 19 04:37:56 PM PDT 24
Finished Aug 19 04:55:03 PM PDT 24
Peak memory 191796 kb
Host smart-8689dabb-e625-4a61-95d8-30f0754764fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234764977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3234764977
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_random.1288377892
Short name T181
Test name
Test status
Simulation time 334499250280 ps
CPU time 304.6 seconds
Started Aug 19 04:37:56 PM PDT 24
Finished Aug 19 04:43:01 PM PDT 24
Peak memory 191796 kb
Host smart-76fe891c-69b4-4641-8d1a-5d350d4dc229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288377892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1288377892
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2262206224
Short name T294
Test name
Test status
Simulation time 2479152637613 ps
CPU time 785.95 seconds
Started Aug 19 04:37:09 PM PDT 24
Finished Aug 19 04:50:15 PM PDT 24
Peak memory 191760 kb
Host smart-212d750d-cf36-46ee-a9a3-1649b0358e5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262206224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2262206224
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/88.rv_timer_random.1184064236
Short name T231
Test name
Test status
Simulation time 436802597391 ps
CPU time 950.88 seconds
Started Aug 19 04:37:57 PM PDT 24
Finished Aug 19 04:53:48 PM PDT 24
Peak memory 191792 kb
Host smart-8dd7e9cb-948b-4b27-a7bc-43af94e628ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184064236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1184064236
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3430649786
Short name T517
Test name
Test status
Simulation time 19523139 ps
CPU time 0.64 seconds
Started Aug 19 05:03:35 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 183332 kb
Host smart-ed25edcb-0fdf-4cfa-a3cf-94f8f8f4e037
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430649786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3430649786
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1099181320
Short name T516
Test name
Test status
Simulation time 723746392 ps
CPU time 2.3 seconds
Started Aug 19 05:03:33 PM PDT 24
Finished Aug 19 05:03:35 PM PDT 24
Peak memory 183576 kb
Host smart-945535a6-aac2-4a69-a704-b0c1fcdb8500
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099181320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1099181320
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3745737497
Short name T564
Test name
Test status
Simulation time 12914874 ps
CPU time 0.58 seconds
Started Aug 19 05:03:35 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 183400 kb
Host smart-a4ef07cb-f4e6-4d1d-8e58-1dc894a5f282
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745737497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3745737497
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.82001121
Short name T522
Test name
Test status
Simulation time 29223875 ps
CPU time 1.33 seconds
Started Aug 19 05:03:35 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 198192 kb
Host smart-fb9fc9a7-7fb3-4e6e-ad1e-fa00087bbc7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82001121 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.82001121
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.264507849
Short name T466
Test name
Test status
Simulation time 12059142 ps
CPU time 0.53 seconds
Started Aug 19 05:03:37 PM PDT 24
Finished Aug 19 05:03:38 PM PDT 24
Peak memory 183024 kb
Host smart-b3ff6cd3-4f2b-4644-8e20-5bc68733a52a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264507849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.264507849
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.4052928175
Short name T546
Test name
Test status
Simulation time 18681403 ps
CPU time 0.58 seconds
Started Aug 19 05:03:35 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 183244 kb
Host smart-61f89d44-bbdb-4536-bd02-c33c84dbb330
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052928175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.4052928175
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2150961142
Short name T52
Test name
Test status
Simulation time 76527226 ps
CPU time 1.67 seconds
Started Aug 19 05:03:36 PM PDT 24
Finished Aug 19 05:03:38 PM PDT 24
Peak memory 198132 kb
Host smart-2b21de69-d634-479d-b73b-7d660552a319
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150961142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2150961142
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.702524152
Short name T575
Test name
Test status
Simulation time 97691725 ps
CPU time 1.4 seconds
Started Aug 19 05:03:37 PM PDT 24
Finished Aug 19 05:03:39 PM PDT 24
Peak memory 184100 kb
Host smart-007afc5e-c657-40e3-8489-456231042dec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702524152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.702524152
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2797622543
Short name T71
Test name
Test status
Simulation time 24641128 ps
CPU time 0.72 seconds
Started Aug 19 05:03:39 PM PDT 24
Finished Aug 19 05:03:40 PM PDT 24
Peak memory 193252 kb
Host smart-5ae1a05e-60a3-42d5-b934-cac47ad1d9f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797622543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2797622543
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.217548745
Short name T480
Test name
Test status
Simulation time 192680076 ps
CPU time 1.41 seconds
Started Aug 19 05:03:37 PM PDT 24
Finished Aug 19 05:03:39 PM PDT 24
Peak memory 183724 kb
Host smart-32901bfb-9cc4-41e0-9817-1f4fb7aa2f5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217548745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.217548745
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.860182254
Short name T69
Test name
Test status
Simulation time 48979641 ps
CPU time 0.6 seconds
Started Aug 19 05:03:39 PM PDT 24
Finished Aug 19 05:03:40 PM PDT 24
Peak memory 183412 kb
Host smart-abf7c562-0eba-4e47-b281-4c0bde425822
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860182254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.860182254
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1809734308
Short name T509
Test name
Test status
Simulation time 29211817 ps
CPU time 0.82 seconds
Started Aug 19 05:03:38 PM PDT 24
Finished Aug 19 05:03:39 PM PDT 24
Peak memory 196528 kb
Host smart-600f3612-f403-4d13-aaa0-6731f44bf4a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809734308 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1809734308
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1092788227
Short name T72
Test name
Test status
Simulation time 125387222 ps
CPU time 0.58 seconds
Started Aug 19 05:03:39 PM PDT 24
Finished Aug 19 05:03:40 PM PDT 24
Peak memory 183408 kb
Host smart-3a7077ea-64cf-448f-bb47-c1049e48a339
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092788227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1092788227
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4196820441
Short name T494
Test name
Test status
Simulation time 22151395 ps
CPU time 0.55 seconds
Started Aug 19 05:03:38 PM PDT 24
Finished Aug 19 05:03:38 PM PDT 24
Peak memory 182660 kb
Host smart-4761baab-bfe2-4842-a3ca-8129a7857a4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196820441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.4196820441
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1129993109
Short name T536
Test name
Test status
Simulation time 38338372 ps
CPU time 0.61 seconds
Started Aug 19 05:03:39 PM PDT 24
Finished Aug 19 05:03:40 PM PDT 24
Peak memory 192276 kb
Host smart-e32f11db-0180-481a-8965-e62acbd6aa52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129993109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1129993109
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2948083758
Short name T474
Test name
Test status
Simulation time 256802386 ps
CPU time 1.83 seconds
Started Aug 19 05:03:37 PM PDT 24
Finished Aug 19 05:03:39 PM PDT 24
Peak memory 198112 kb
Host smart-cb56d1d0-40e8-4c78-beeb-7874e13bb7aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948083758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2948083758
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3753660441
Short name T51
Test name
Test status
Simulation time 405767327 ps
CPU time 1.09 seconds
Started Aug 19 05:03:36 PM PDT 24
Finished Aug 19 05:03:37 PM PDT 24
Peak memory 195940 kb
Host smart-530cb106-6ea8-4416-bf17-393561df579c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753660441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3753660441
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.37276477
Short name T558
Test name
Test status
Simulation time 134747368 ps
CPU time 0.82 seconds
Started Aug 19 05:03:53 PM PDT 24
Finished Aug 19 05:03:54 PM PDT 24
Peak memory 197440 kb
Host smart-f85e6ef5-ecf4-429e-beb2-22c6c9500ea5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37276477 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.37276477
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1490905782
Short name T80
Test name
Test status
Simulation time 13167345 ps
CPU time 0.55 seconds
Started Aug 19 05:03:53 PM PDT 24
Finished Aug 19 05:03:54 PM PDT 24
Peak memory 183348 kb
Host smart-81ace469-449c-4b51-89e1-4ec1ecb2a945
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490905782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1490905782
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3412171611
Short name T498
Test name
Test status
Simulation time 20366525 ps
CPU time 0.55 seconds
Started Aug 19 05:03:58 PM PDT 24
Finished Aug 19 05:03:59 PM PDT 24
Peak memory 183288 kb
Host smart-0a12c9e2-b2ee-443b-b8a4-09dacdbad2e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412171611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3412171611
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3179230991
Short name T49
Test name
Test status
Simulation time 19662227 ps
CPU time 0.61 seconds
Started Aug 19 05:03:51 PM PDT 24
Finished Aug 19 05:03:52 PM PDT 24
Peak memory 192048 kb
Host smart-24e79821-f1ba-4c9e-b1cb-0ec9d83c4c87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179230991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3179230991
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.4091569912
Short name T483
Test name
Test status
Simulation time 93674255 ps
CPU time 1.99 seconds
Started Aug 19 05:03:56 PM PDT 24
Finished Aug 19 05:03:58 PM PDT 24
Peak memory 198152 kb
Host smart-586dce89-a826-404a-9e78-8904cbc85b50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091569912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.4091569912
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1607516754
Short name T29
Test name
Test status
Simulation time 637994048 ps
CPU time 0.84 seconds
Started Aug 19 05:03:52 PM PDT 24
Finished Aug 19 05:03:53 PM PDT 24
Peak memory 193972 kb
Host smart-5ed39254-ef08-4ce5-a219-dbc8250b6867
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607516754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1607516754
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2400761427
Short name T508
Test name
Test status
Simulation time 115049999 ps
CPU time 1.43 seconds
Started Aug 19 05:03:56 PM PDT 24
Finished Aug 19 05:03:57 PM PDT 24
Peak memory 198116 kb
Host smart-e36fd423-44a0-4ab7-93fa-65ab63ce6c62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400761427 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2400761427
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.896690207
Short name T471
Test name
Test status
Simulation time 23828571 ps
CPU time 0.57 seconds
Started Aug 19 05:03:59 PM PDT 24
Finished Aug 19 05:04:00 PM PDT 24
Peak memory 183120 kb
Host smart-e7ce5731-83c5-4117-9b9c-1fa3fbfe2fc0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896690207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.896690207
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4080629046
Short name T542
Test name
Test status
Simulation time 17658896 ps
CPU time 0.53 seconds
Started Aug 19 05:03:53 PM PDT 24
Finished Aug 19 05:03:54 PM PDT 24
Peak memory 182696 kb
Host smart-fef2df53-3ec5-4432-908c-f005ef25c96e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080629046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4080629046
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.4028006650
Short name T552
Test name
Test status
Simulation time 31580598 ps
CPU time 0.88 seconds
Started Aug 19 05:03:53 PM PDT 24
Finished Aug 19 05:03:54 PM PDT 24
Peak memory 191420 kb
Host smart-3c1ae25d-be1a-4cb9-925e-8aee12d580f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028006650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.4028006650
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3618893788
Short name T519
Test name
Test status
Simulation time 175592624 ps
CPU time 1.78 seconds
Started Aug 19 05:03:57 PM PDT 24
Finished Aug 19 05:03:59 PM PDT 24
Peak memory 198060 kb
Host smart-ebcaecd7-35d4-4537-9ac9-93dc8a509d49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618893788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3618893788
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.447611605
Short name T499
Test name
Test status
Simulation time 55370548 ps
CPU time 0.84 seconds
Started Aug 19 05:04:00 PM PDT 24
Finished Aug 19 05:04:01 PM PDT 24
Peak memory 194384 kb
Host smart-cfb28298-0fd5-4fb7-a76f-347e6fac7825
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447611605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.447611605
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2017889652
Short name T520
Test name
Test status
Simulation time 50120016 ps
CPU time 0.86 seconds
Started Aug 19 05:03:52 PM PDT 24
Finished Aug 19 05:03:53 PM PDT 24
Peak memory 197472 kb
Host smart-9ed321fe-1530-4d86-8e82-d922c443cb2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017889652 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2017889652
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2160345821
Short name T68
Test name
Test status
Simulation time 18035435 ps
CPU time 0.59 seconds
Started Aug 19 05:03:53 PM PDT 24
Finished Aug 19 05:03:53 PM PDT 24
Peak memory 183332 kb
Host smart-53e32734-f81f-4194-a5c5-328e7af1a383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160345821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2160345821
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.353902618
Short name T504
Test name
Test status
Simulation time 14141009 ps
CPU time 0.53 seconds
Started Aug 19 05:03:58 PM PDT 24
Finished Aug 19 05:03:59 PM PDT 24
Peak memory 182736 kb
Host smart-4c0047db-e98b-409a-81b3-409a8f6e6028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353902618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.353902618
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.293340893
Short name T538
Test name
Test status
Simulation time 67728110 ps
CPU time 0.66 seconds
Started Aug 19 05:03:50 PM PDT 24
Finished Aug 19 05:03:51 PM PDT 24
Peak memory 192364 kb
Host smart-e85d8ebd-e941-482d-b251-82bd4adb01b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293340893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.293340893
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1552990638
Short name T478
Test name
Test status
Simulation time 126083887 ps
CPU time 1.89 seconds
Started Aug 19 05:03:53 PM PDT 24
Finished Aug 19 05:03:55 PM PDT 24
Peak memory 197956 kb
Host smart-70f58f1a-761b-4e1f-b093-f9172f9e6212
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552990638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1552990638
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2241412572
Short name T535
Test name
Test status
Simulation time 22132874 ps
CPU time 0.82 seconds
Started Aug 19 05:04:00 PM PDT 24
Finished Aug 19 05:04:01 PM PDT 24
Peak memory 197184 kb
Host smart-711ab7c6-3e65-4ea2-8a3a-d15fa02b1219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241412572 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2241412572
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3840179264
Short name T492
Test name
Test status
Simulation time 73622420 ps
CPU time 0.59 seconds
Started Aug 19 05:04:03 PM PDT 24
Finished Aug 19 05:04:04 PM PDT 24
Peak memory 183336 kb
Host smart-b9cc8877-5611-482f-a45c-9ee3c42c2d79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840179264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3840179264
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3218196505
Short name T537
Test name
Test status
Simulation time 11427582 ps
CPU time 0.52 seconds
Started Aug 19 05:04:00 PM PDT 24
Finished Aug 19 05:04:01 PM PDT 24
Peak memory 182728 kb
Host smart-c57ada97-0eb8-4bcd-82dc-e4037b953a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218196505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3218196505
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1982921624
Short name T539
Test name
Test status
Simulation time 32310668 ps
CPU time 0.78 seconds
Started Aug 19 05:04:07 PM PDT 24
Finished Aug 19 05:04:08 PM PDT 24
Peak memory 194012 kb
Host smart-167f45af-9cdb-4f7d-8460-2d2928bb7366
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982921624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1982921624
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3110839276
Short name T548
Test name
Test status
Simulation time 224437644 ps
CPU time 2.14 seconds
Started Aug 19 05:04:00 PM PDT 24
Finished Aug 19 05:04:02 PM PDT 24
Peak memory 198144 kb
Host smart-d88523e3-c897-4a14-b88e-3cd2c8411d56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110839276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3110839276
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1213896563
Short name T85
Test name
Test status
Simulation time 148237104 ps
CPU time 0.75 seconds
Started Aug 19 05:03:52 PM PDT 24
Finished Aug 19 05:03:53 PM PDT 24
Peak memory 183576 kb
Host smart-421a6b96-4bdc-46b0-92c0-18252b1a3dee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213896563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1213896563
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2273205569
Short name T513
Test name
Test status
Simulation time 36126045 ps
CPU time 0.7 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 194944 kb
Host smart-458cbdf8-54d5-4c67-afeb-60e862d600bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273205569 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2273205569
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3392885112
Short name T581
Test name
Test status
Simulation time 13609046 ps
CPU time 0.53 seconds
Started Aug 19 05:04:01 PM PDT 24
Finished Aug 19 05:04:02 PM PDT 24
Peak memory 183136 kb
Host smart-9d7e0091-0f5e-402b-a9c3-8347f4dd038b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392885112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3392885112
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3081619067
Short name T473
Test name
Test status
Simulation time 22405035 ps
CPU time 0.55 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 182700 kb
Host smart-1e964ea6-ce0f-44cb-b3cf-166880f89803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081619067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3081619067
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2496097999
Short name T45
Test name
Test status
Simulation time 32608104 ps
CPU time 0.79 seconds
Started Aug 19 05:04:10 PM PDT 24
Finished Aug 19 05:04:12 PM PDT 24
Peak memory 194016 kb
Host smart-b3ccbcac-ed69-4a61-8f45-79a6aa94232d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496097999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2496097999
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3188428322
Short name T565
Test name
Test status
Simulation time 97596104 ps
CPU time 1.77 seconds
Started Aug 19 05:04:02 PM PDT 24
Finished Aug 19 05:04:04 PM PDT 24
Peak memory 198104 kb
Host smart-647ba172-929d-4bf0-8017-2fd5614ba5f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188428322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3188428322
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.81103612
Short name T574
Test name
Test status
Simulation time 287277061 ps
CPU time 1.13 seconds
Started Aug 19 05:04:02 PM PDT 24
Finished Aug 19 05:04:03 PM PDT 24
Peak memory 184028 kb
Host smart-0d7fceb1-1858-404a-8f73-a63e9369d6fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81103612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_int
g_err.81103612
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.656352468
Short name T481
Test name
Test status
Simulation time 36087189 ps
CPU time 0.94 seconds
Started Aug 19 05:04:06 PM PDT 24
Finished Aug 19 05:04:07 PM PDT 24
Peak memory 197576 kb
Host smart-57ccb9c3-f958-4397-ad10-395e886fa24b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656352468 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.656352468
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.485349194
Short name T31
Test name
Test status
Simulation time 25588491 ps
CPU time 0.58 seconds
Started Aug 19 05:04:11 PM PDT 24
Finished Aug 19 05:04:12 PM PDT 24
Peak memory 183404 kb
Host smart-5277a1b3-5d15-4eb7-b4d7-3508876b56a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485349194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.485349194
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.4258216304
Short name T521
Test name
Test status
Simulation time 21166081 ps
CPU time 0.52 seconds
Started Aug 19 05:04:00 PM PDT 24
Finished Aug 19 05:04:01 PM PDT 24
Peak memory 182720 kb
Host smart-995c5fc6-ff3a-4a7b-8aad-2a5f95d59fbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258216304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.4258216304
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2184754258
Short name T44
Test name
Test status
Simulation time 123616545 ps
CPU time 0.73 seconds
Started Aug 19 05:04:02 PM PDT 24
Finished Aug 19 05:04:02 PM PDT 24
Peak memory 192308 kb
Host smart-82f95333-bc15-49cb-bebc-ad8536f6c4a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184754258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2184754258
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4283246657
Short name T518
Test name
Test status
Simulation time 111661484 ps
CPU time 2.41 seconds
Started Aug 19 05:04:03 PM PDT 24
Finished Aug 19 05:04:05 PM PDT 24
Peak memory 198092 kb
Host smart-d1e0e68e-c48c-407c-bd56-f8f08460f7f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283246657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.4283246657
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1025344734
Short name T28
Test name
Test status
Simulation time 158383850 ps
CPU time 0.81 seconds
Started Aug 19 05:04:02 PM PDT 24
Finished Aug 19 05:04:03 PM PDT 24
Peak memory 194516 kb
Host smart-73db0bbb-e43f-4aa3-a061-86b4964b7d33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025344734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1025344734
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.672660104
Short name T525
Test name
Test status
Simulation time 47381622 ps
CPU time 0.61 seconds
Started Aug 19 05:04:06 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 193904 kb
Host smart-03015375-0821-49f9-8e1d-7f2c7a7ef82c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672660104 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.672660104
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2446387148
Short name T470
Test name
Test status
Simulation time 27048468 ps
CPU time 0.55 seconds
Started Aug 19 05:04:03 PM PDT 24
Finished Aug 19 05:04:04 PM PDT 24
Peak memory 183320 kb
Host smart-64d49954-17a8-45bf-9612-aa57dff56ccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446387148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2446387148
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2841706689
Short name T65
Test name
Test status
Simulation time 32741024 ps
CPU time 0.74 seconds
Started Aug 19 05:04:10 PM PDT 24
Finished Aug 19 05:04:11 PM PDT 24
Peak memory 192340 kb
Host smart-8e24d3ca-661b-4c77-a8c3-512fe99c584a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841706689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2841706689
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1666788688
Short name T495
Test name
Test status
Simulation time 73910723 ps
CPU time 2.49 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:08 PM PDT 24
Peak memory 198100 kb
Host smart-6f895044-2866-49e8-a838-79590d0dea6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666788688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1666788688
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.591942679
Short name T550
Test name
Test status
Simulation time 324896291 ps
CPU time 1.35 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:07 PM PDT 24
Peak memory 195860 kb
Host smart-80bf8cc5-cd29-48e1-9bc4-b012fd64d22c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591942679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.591942679
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3262654048
Short name T61
Test name
Test status
Simulation time 127692983 ps
CPU time 1.69 seconds
Started Aug 19 05:04:07 PM PDT 24
Finished Aug 19 05:04:09 PM PDT 24
Peak memory 198264 kb
Host smart-dbde3735-d971-4578-96c9-2ea2f9d1ddce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262654048 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3262654048
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1537534533
Short name T559
Test name
Test status
Simulation time 24351846 ps
CPU time 0.59 seconds
Started Aug 19 05:04:07 PM PDT 24
Finished Aug 19 05:04:07 PM PDT 24
Peak memory 183384 kb
Host smart-3c3f2bc2-459d-4fca-b42a-df85eb963489
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537534533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1537534533
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.4097637655
Short name T576
Test name
Test status
Simulation time 17175966 ps
CPU time 0.56 seconds
Started Aug 19 05:03:59 PM PDT 24
Finished Aug 19 05:04:00 PM PDT 24
Peak memory 183260 kb
Host smart-d9fe331e-c2b0-4dd3-8463-bf4ec0732256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097637655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.4097637655
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.4157362661
Short name T76
Test name
Test status
Simulation time 25018374 ps
CPU time 0.79 seconds
Started Aug 19 05:04:07 PM PDT 24
Finished Aug 19 05:04:08 PM PDT 24
Peak memory 193616 kb
Host smart-eb52a1da-f330-459c-97f7-ed66253922cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157362661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.4157362661
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3655892692
Short name T472
Test name
Test status
Simulation time 174674228 ps
CPU time 1.12 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 197932 kb
Host smart-ce6ec325-67fb-4a26-b224-bcafede37ed6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655892692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3655892692
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1034387263
Short name T551
Test name
Test status
Simulation time 122586177 ps
CPU time 1.44 seconds
Started Aug 19 05:04:02 PM PDT 24
Finished Aug 19 05:04:04 PM PDT 24
Peak memory 196044 kb
Host smart-94788aad-afcd-453a-ab3b-f76f7be31186
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034387263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1034387263
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1655771248
Short name T479
Test name
Test status
Simulation time 92306635 ps
CPU time 0.68 seconds
Started Aug 19 05:03:59 PM PDT 24
Finished Aug 19 05:04:00 PM PDT 24
Peak memory 194720 kb
Host smart-b66bf32c-9679-442c-b7d6-ad1980a6cb55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655771248 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1655771248
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.101641361
Short name T571
Test name
Test status
Simulation time 16506794 ps
CPU time 0.56 seconds
Started Aug 19 05:04:01 PM PDT 24
Finished Aug 19 05:04:02 PM PDT 24
Peak memory 183388 kb
Host smart-616c3a0a-52ec-4224-8877-93bbac9542f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101641361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.101641361
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3637595041
Short name T462
Test name
Test status
Simulation time 47559857 ps
CPU time 0.55 seconds
Started Aug 19 05:04:10 PM PDT 24
Finished Aug 19 05:04:11 PM PDT 24
Peak memory 183324 kb
Host smart-d50dd679-ca59-4e11-a53f-847089b54403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637595041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3637595041
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3478756156
Short name T487
Test name
Test status
Simulation time 108743459 ps
CPU time 0.71 seconds
Started Aug 19 05:04:04 PM PDT 24
Finished Aug 19 05:04:04 PM PDT 24
Peak memory 193684 kb
Host smart-e68ed950-ce71-4941-8d47-1ed9977159a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478756156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3478756156
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1951523708
Short name T544
Test name
Test status
Simulation time 83199889 ps
CPU time 1.04 seconds
Started Aug 19 05:04:11 PM PDT 24
Finished Aug 19 05:04:12 PM PDT 24
Peak memory 197844 kb
Host smart-70f67743-d15f-477a-86d4-1f6ea7280e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951523708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1951523708
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3949317460
Short name T514
Test name
Test status
Simulation time 92693600 ps
CPU time 0.82 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 193316 kb
Host smart-d4bb9026-2983-4ec3-b0f4-2b87f510f82a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949317460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3949317460
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2323676436
Short name T46
Test name
Test status
Simulation time 37259062 ps
CPU time 0.74 seconds
Started Aug 19 05:04:04 PM PDT 24
Finished Aug 19 05:04:05 PM PDT 24
Peak memory 195536 kb
Host smart-6b536706-368b-4dae-9cac-17e082c788c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323676436 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2323676436
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2079906261
Short name T75
Test name
Test status
Simulation time 11778654 ps
CPU time 0.55 seconds
Started Aug 19 05:04:02 PM PDT 24
Finished Aug 19 05:04:03 PM PDT 24
Peak memory 183356 kb
Host smart-02adfc4f-14da-4d65-bada-d00d5bc545e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079906261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2079906261
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4256270195
Short name T579
Test name
Test status
Simulation time 21306311 ps
CPU time 0.56 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 182700 kb
Host smart-96314d82-8e3c-46ca-971b-e11015163842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256270195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4256270195
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3219540442
Short name T490
Test name
Test status
Simulation time 42864904 ps
CPU time 0.81 seconds
Started Aug 19 05:04:06 PM PDT 24
Finished Aug 19 05:04:07 PM PDT 24
Peak memory 192344 kb
Host smart-94b0dec0-255d-47f3-ad8b-edab457316c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219540442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3219540442
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2415954181
Short name T562
Test name
Test status
Simulation time 89554964 ps
CPU time 0.88 seconds
Started Aug 19 05:04:08 PM PDT 24
Finished Aug 19 05:04:09 PM PDT 24
Peak memory 197052 kb
Host smart-7298976d-503e-4f81-be42-9baa338c2806
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415954181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2415954181
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.4057427713
Short name T561
Test name
Test status
Simulation time 54598844 ps
CPU time 0.83 seconds
Started Aug 19 05:03:35 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 183296 kb
Host smart-10ee8444-533d-4ee1-afa4-b5b1faf16fbf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057427713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.4057427713
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.705210293
Short name T577
Test name
Test status
Simulation time 67877149 ps
CPU time 1.45 seconds
Started Aug 19 05:03:38 PM PDT 24
Finished Aug 19 05:03:39 PM PDT 24
Peak memory 183488 kb
Host smart-a3ace3cb-2e21-4c67-8195-a09a03fa7de6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705210293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.705210293
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2639257045
Short name T553
Test name
Test status
Simulation time 22488905 ps
CPU time 0.54 seconds
Started Aug 19 05:03:39 PM PDT 24
Finished Aug 19 05:03:39 PM PDT 24
Peak memory 182824 kb
Host smart-5f59cdc5-b91d-4ec8-a72e-6609100cb831
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639257045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2639257045
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3897852090
Short name T573
Test name
Test status
Simulation time 50941871 ps
CPU time 0.67 seconds
Started Aug 19 05:03:35 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 194116 kb
Host smart-0d16aabc-7b84-465c-93c7-74f72859f603
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897852090 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3897852090
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3122922213
Short name T511
Test name
Test status
Simulation time 55344476 ps
CPU time 0.59 seconds
Started Aug 19 05:03:32 PM PDT 24
Finished Aug 19 05:03:33 PM PDT 24
Peak memory 183184 kb
Host smart-4d3b116b-2693-4f16-90e2-41f2fc771737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122922213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3122922213
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3551771937
Short name T62
Test name
Test status
Simulation time 35670109 ps
CPU time 0.82 seconds
Started Aug 19 05:03:38 PM PDT 24
Finished Aug 19 05:03:39 PM PDT 24
Peak memory 194136 kb
Host smart-e9de1120-bcff-4cc7-8da4-855577156119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551771937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3551771937
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.992520387
Short name T510
Test name
Test status
Simulation time 63299399 ps
CPU time 1.02 seconds
Started Aug 19 05:03:37 PM PDT 24
Finished Aug 19 05:03:38 PM PDT 24
Peak memory 197028 kb
Host smart-54d047f2-2743-468f-813c-135e2d80b906
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992520387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.992520387
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.361455928
Short name T84
Test name
Test status
Simulation time 101251574 ps
CPU time 1.38 seconds
Started Aug 19 05:03:39 PM PDT 24
Finished Aug 19 05:03:40 PM PDT 24
Peak memory 196240 kb
Host smart-b3a1f331-8826-42ad-b2ed-8ffc3a05da54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361455928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.361455928
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4202184111
Short name T497
Test name
Test status
Simulation time 18696703 ps
CPU time 0.57 seconds
Started Aug 19 05:04:01 PM PDT 24
Finished Aug 19 05:04:02 PM PDT 24
Peak memory 183276 kb
Host smart-2006cb68-55cb-45f9-a59d-1e264104cf88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202184111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4202184111
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1485628919
Short name T475
Test name
Test status
Simulation time 13698169 ps
CPU time 0.55 seconds
Started Aug 19 05:04:11 PM PDT 24
Finished Aug 19 05:04:12 PM PDT 24
Peak memory 182748 kb
Host smart-81f491f1-cd53-428f-973f-b69057e63551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485628919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1485628919
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2307935443
Short name T506
Test name
Test status
Simulation time 12677034 ps
CPU time 0.57 seconds
Started Aug 19 05:04:07 PM PDT 24
Finished Aug 19 05:04:07 PM PDT 24
Peak memory 183316 kb
Host smart-5e9aa905-e1c9-48ef-a879-63f27a4e26f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307935443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2307935443
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1478843701
Short name T463
Test name
Test status
Simulation time 11337241 ps
CPU time 0.52 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:05 PM PDT 24
Peak memory 182940 kb
Host smart-9f003942-ec5e-4f13-9036-8f8b33127ee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478843701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1478843701
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.488108672
Short name T457
Test name
Test status
Simulation time 19228645 ps
CPU time 0.56 seconds
Started Aug 19 05:04:01 PM PDT 24
Finished Aug 19 05:04:02 PM PDT 24
Peak memory 183248 kb
Host smart-20a88e01-2ff7-4155-a074-5ddcec06130e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488108672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.488108672
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.406335774
Short name T580
Test name
Test status
Simulation time 36529691 ps
CPU time 0.54 seconds
Started Aug 19 05:04:02 PM PDT 24
Finished Aug 19 05:04:03 PM PDT 24
Peak memory 183152 kb
Host smart-89ab6626-5448-48cb-a7f4-4b5a0a325e68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406335774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.406335774
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1840378819
Short name T545
Test name
Test status
Simulation time 14225568 ps
CPU time 0.57 seconds
Started Aug 19 05:04:06 PM PDT 24
Finished Aug 19 05:04:07 PM PDT 24
Peak memory 183216 kb
Host smart-981b8e2d-f4b7-404c-9294-c258924de6a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840378819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1840378819
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.4005955107
Short name T491
Test name
Test status
Simulation time 15750864 ps
CPU time 0.6 seconds
Started Aug 19 05:04:07 PM PDT 24
Finished Aug 19 05:04:07 PM PDT 24
Peak memory 182728 kb
Host smart-2038676a-461b-4dab-b898-cc93d0ac4e14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005955107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.4005955107
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1002467867
Short name T459
Test name
Test status
Simulation time 13239278 ps
CPU time 0.51 seconds
Started Aug 19 05:04:06 PM PDT 24
Finished Aug 19 05:04:07 PM PDT 24
Peak memory 182744 kb
Host smart-d8ad402d-7846-4cfa-b2f6-ce432efb828c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002467867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1002467867
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3556787572
Short name T523
Test name
Test status
Simulation time 50868210 ps
CPU time 0.55 seconds
Started Aug 19 05:04:07 PM PDT 24
Finished Aug 19 05:04:08 PM PDT 24
Peak memory 182344 kb
Host smart-0f814087-7515-4c7f-97e1-e5f926ddce13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556787572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3556787572
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.415587322
Short name T64
Test name
Test status
Simulation time 224696500 ps
CPU time 0.8 seconds
Started Aug 19 05:03:38 PM PDT 24
Finished Aug 19 05:03:39 PM PDT 24
Peak memory 183392 kb
Host smart-f57af506-6068-46c3-a07b-f65772dad719
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415587322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.415587322
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2330532565
Short name T524
Test name
Test status
Simulation time 39951561 ps
CPU time 1.49 seconds
Started Aug 19 05:03:38 PM PDT 24
Finished Aug 19 05:03:39 PM PDT 24
Peak memory 193600 kb
Host smart-c693769c-9099-4791-9685-b9c0d1cecfb9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330532565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2330532565
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4193387568
Short name T66
Test name
Test status
Simulation time 36109192 ps
CPU time 0.53 seconds
Started Aug 19 05:03:36 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 183388 kb
Host smart-a7a10d70-7594-4ef7-a5d5-e5f4742b9403
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193387568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4193387568
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.929230176
Short name T549
Test name
Test status
Simulation time 43475814 ps
CPU time 0.77 seconds
Started Aug 19 05:03:53 PM PDT 24
Finished Aug 19 05:03:54 PM PDT 24
Peak memory 196156 kb
Host smart-190f919f-601c-4a8d-be16-cc91f432d083
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929230176 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.929230176
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.875200801
Short name T79
Test name
Test status
Simulation time 45789537 ps
CPU time 0.54 seconds
Started Aug 19 05:03:38 PM PDT 24
Finished Aug 19 05:03:39 PM PDT 24
Peak memory 182984 kb
Host smart-1ca8e072-a18e-4d90-b449-169a16890d5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875200801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.875200801
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.618036802
Short name T507
Test name
Test status
Simulation time 19700293 ps
CPU time 0.6 seconds
Started Aug 19 05:03:37 PM PDT 24
Finished Aug 19 05:03:37 PM PDT 24
Peak memory 183156 kb
Host smart-f50ce923-3f3b-491c-a979-70086f7d988d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618036802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.618036802
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.959896352
Short name T63
Test name
Test status
Simulation time 46751648 ps
CPU time 0.6 seconds
Started Aug 19 05:03:55 PM PDT 24
Finished Aug 19 05:03:56 PM PDT 24
Peak memory 192116 kb
Host smart-091ef0c4-45b9-4fb3-a2f0-a7536273d63a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959896352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.959896352
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2144629157
Short name T570
Test name
Test status
Simulation time 32173161 ps
CPU time 0.98 seconds
Started Aug 19 05:03:35 PM PDT 24
Finished Aug 19 05:03:36 PM PDT 24
Peak memory 196740 kb
Host smart-56694c53-7ee1-4745-bc6c-b9791f7084c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144629157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2144629157
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3064954614
Short name T541
Test name
Test status
Simulation time 37327579 ps
CPU time 0.86 seconds
Started Aug 19 05:03:33 PM PDT 24
Finished Aug 19 05:03:34 PM PDT 24
Peak memory 194476 kb
Host smart-2a6a38bf-0f6f-4866-9721-3ced3a126d85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064954614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3064954614
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3162788512
Short name T578
Test name
Test status
Simulation time 14361127 ps
CPU time 0.56 seconds
Started Aug 19 05:04:11 PM PDT 24
Finished Aug 19 05:04:12 PM PDT 24
Peak memory 183264 kb
Host smart-2c4048cd-aecb-4f61-ba92-d4a7c462fd07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162788512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3162788512
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.413101065
Short name T554
Test name
Test status
Simulation time 28159766 ps
CPU time 0.59 seconds
Started Aug 19 05:04:11 PM PDT 24
Finished Aug 19 05:04:12 PM PDT 24
Peak memory 183208 kb
Host smart-f63c524c-dd44-471b-89dc-8c9c46bb3923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413101065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.413101065
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.292512887
Short name T461
Test name
Test status
Simulation time 35331412 ps
CPU time 0.55 seconds
Started Aug 19 05:04:01 PM PDT 24
Finished Aug 19 05:04:02 PM PDT 24
Peak memory 182924 kb
Host smart-8b68f153-4d5c-4c5b-ad51-782d14edb79b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292512887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.292512887
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3513238298
Short name T482
Test name
Test status
Simulation time 15155555 ps
CPU time 0.53 seconds
Started Aug 19 05:04:10 PM PDT 24
Finished Aug 19 05:04:11 PM PDT 24
Peak memory 182940 kb
Host smart-47cd4c11-a7c7-494c-8386-ccfc8ab53289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513238298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3513238298
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4030935289
Short name T556
Test name
Test status
Simulation time 62212467 ps
CPU time 0.58 seconds
Started Aug 19 05:04:11 PM PDT 24
Finished Aug 19 05:04:12 PM PDT 24
Peak memory 182964 kb
Host smart-3ad891cc-0904-48dc-a49c-9698ca1c953e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030935289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.4030935289
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1204897067
Short name T503
Test name
Test status
Simulation time 15397770 ps
CPU time 0.58 seconds
Started Aug 19 05:04:07 PM PDT 24
Finished Aug 19 05:04:07 PM PDT 24
Peak memory 183264 kb
Host smart-3f1a459d-b654-4862-978e-e335197caaed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204897067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1204897067
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2938493452
Short name T563
Test name
Test status
Simulation time 18414811 ps
CPU time 0.58 seconds
Started Aug 19 05:04:10 PM PDT 24
Finished Aug 19 05:04:11 PM PDT 24
Peak memory 182712 kb
Host smart-77b6f09a-f91f-42dc-9bd5-17d842b13219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938493452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2938493452
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.662926601
Short name T477
Test name
Test status
Simulation time 18640153 ps
CPU time 0.61 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 183220 kb
Host smart-e05052c9-6dd6-4097-aeb5-c9403a1185f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662926601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.662926601
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3385169465
Short name T505
Test name
Test status
Simulation time 39228641 ps
CPU time 0.53 seconds
Started Aug 19 05:04:06 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 182936 kb
Host smart-90d3c74a-f34d-4fb3-86ca-340c5b7ffca9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385169465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3385169465
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2324809799
Short name T515
Test name
Test status
Simulation time 20633879 ps
CPU time 0.56 seconds
Started Aug 19 05:04:06 PM PDT 24
Finished Aug 19 05:04:07 PM PDT 24
Peak memory 182804 kb
Host smart-87347139-55e2-49d4-ab7e-3638491d05f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324809799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2324809799
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2403894297
Short name T70
Test name
Test status
Simulation time 36909646 ps
CPU time 0.85 seconds
Started Aug 19 05:03:48 PM PDT 24
Finished Aug 19 05:03:49 PM PDT 24
Peak memory 193408 kb
Host smart-c4be79f7-be08-4584-9762-5607346d22c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403894297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2403894297
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2977357666
Short name T81
Test name
Test status
Simulation time 89667931 ps
CPU time 3.15 seconds
Started Aug 19 05:03:48 PM PDT 24
Finished Aug 19 05:03:52 PM PDT 24
Peak memory 191772 kb
Host smart-747b9949-31d6-4d77-aed7-0a664a2fef8d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977357666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2977357666
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1088040916
Short name T48
Test name
Test status
Simulation time 37040428 ps
CPU time 0.6 seconds
Started Aug 19 05:03:49 PM PDT 24
Finished Aug 19 05:03:50 PM PDT 24
Peak memory 183392 kb
Host smart-9d5d9962-ab5d-4c7e-85ff-7cfb598dd25d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088040916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1088040916
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1322952995
Short name T469
Test name
Test status
Simulation time 15274221 ps
CPU time 0.63 seconds
Started Aug 19 05:03:50 PM PDT 24
Finished Aug 19 05:03:50 PM PDT 24
Peak memory 193608 kb
Host smart-14608484-74e7-4843-a7c8-2db074dee94a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322952995 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1322952995
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.789015999
Short name T73
Test name
Test status
Simulation time 35177201 ps
CPU time 0.57 seconds
Started Aug 19 05:03:50 PM PDT 24
Finished Aug 19 05:03:50 PM PDT 24
Peak memory 183372 kb
Host smart-71d1f8f6-d7f8-4ee8-968c-482584ded5b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789015999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.789015999
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2690538117
Short name T458
Test name
Test status
Simulation time 52918158 ps
CPU time 0.57 seconds
Started Aug 19 05:03:48 PM PDT 24
Finished Aug 19 05:03:48 PM PDT 24
Peak memory 183036 kb
Host smart-235f4b1b-35f6-46bd-84c2-eb01dfd27271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690538117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2690538117
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.152956397
Short name T502
Test name
Test status
Simulation time 16213076 ps
CPU time 0.67 seconds
Started Aug 19 05:03:53 PM PDT 24
Finished Aug 19 05:03:54 PM PDT 24
Peak memory 192768 kb
Host smart-52f5d7b9-41c6-438a-b6c2-f5c64e57c320
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152956397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.152956397
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2211540303
Short name T543
Test name
Test status
Simulation time 353879085 ps
CPU time 1.7 seconds
Started Aug 19 05:03:56 PM PDT 24
Finished Aug 19 05:03:58 PM PDT 24
Peak memory 198060 kb
Host smart-3b470c1f-1f1e-49bc-8b03-da9875607cb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211540303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2211540303
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.607460924
Short name T467
Test name
Test status
Simulation time 126993977 ps
CPU time 1.18 seconds
Started Aug 19 05:03:49 PM PDT 24
Finished Aug 19 05:03:51 PM PDT 24
Peak memory 183852 kb
Host smart-0c9662b8-18f1-43f7-a901-80e3f4fba205
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607460924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int
g_err.607460924
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2322390206
Short name T465
Test name
Test status
Simulation time 21310830 ps
CPU time 0.59 seconds
Started Aug 19 05:04:11 PM PDT 24
Finished Aug 19 05:04:12 PM PDT 24
Peak memory 182740 kb
Host smart-402a87a0-4216-442d-b8ba-670a85f57d92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322390206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2322390206
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1568289220
Short name T534
Test name
Test status
Simulation time 35266171 ps
CPU time 0.55 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 183288 kb
Host smart-351e206c-1357-4b60-80e2-3cf195eae557
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568289220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1568289220
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.4259364871
Short name T526
Test name
Test status
Simulation time 37405749 ps
CPU time 0.58 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 182752 kb
Host smart-a8edbbdb-3de3-488a-a77b-c2dc911c4660
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259364871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.4259364871
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1974954502
Short name T532
Test name
Test status
Simulation time 18638033 ps
CPU time 0.55 seconds
Started Aug 19 05:04:06 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 182948 kb
Host smart-2d282621-7031-4c95-a58a-77f5c83532c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974954502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1974954502
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.988827393
Short name T460
Test name
Test status
Simulation time 30748590 ps
CPU time 0.55 seconds
Started Aug 19 05:04:11 PM PDT 24
Finished Aug 19 05:04:12 PM PDT 24
Peak memory 183264 kb
Host smart-86ff06fc-b04a-460e-8a36-830dcbeebd61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988827393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.988827393
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3988953793
Short name T567
Test name
Test status
Simulation time 29812903 ps
CPU time 0.57 seconds
Started Aug 19 05:04:06 PM PDT 24
Finished Aug 19 05:04:07 PM PDT 24
Peak memory 182800 kb
Host smart-1e524f8f-a08a-4613-91b5-b96d7cf5329c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988953793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3988953793
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1883331633
Short name T572
Test name
Test status
Simulation time 14667615 ps
CPU time 0.56 seconds
Started Aug 19 05:04:06 PM PDT 24
Finished Aug 19 05:04:07 PM PDT 24
Peak memory 183216 kb
Host smart-ead21b3a-497f-457f-b02e-7b10929fabc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883331633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1883331633
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2863240585
Short name T582
Test name
Test status
Simulation time 84976785 ps
CPU time 0.53 seconds
Started Aug 19 05:04:05 PM PDT 24
Finished Aug 19 05:04:06 PM PDT 24
Peak memory 182900 kb
Host smart-5460c852-0ebd-415e-b3bc-8fbaeb5645ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863240585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2863240585
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.595361048
Short name T489
Test name
Test status
Simulation time 16512976 ps
CPU time 0.64 seconds
Started Aug 19 05:04:04 PM PDT 24
Finished Aug 19 05:04:04 PM PDT 24
Peak memory 183196 kb
Host smart-d1594b6f-7cfe-42a7-a9bb-4f90eac03c17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595361048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.595361048
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3185924156
Short name T531
Test name
Test status
Simulation time 13791218 ps
CPU time 0.59 seconds
Started Aug 19 05:04:01 PM PDT 24
Finished Aug 19 05:04:02 PM PDT 24
Peak memory 183280 kb
Host smart-531b7504-4edd-40eb-b082-55cf85090cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185924156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3185924156
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3143609439
Short name T530
Test name
Test status
Simulation time 71461312 ps
CPU time 0.69 seconds
Started Aug 19 05:03:55 PM PDT 24
Finished Aug 19 05:03:56 PM PDT 24
Peak memory 194644 kb
Host smart-0905cdff-cbbb-4fcc-88b8-7ce6923ad900
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143609439 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3143609439
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.366497968
Short name T568
Test name
Test status
Simulation time 15925789 ps
CPU time 0.6 seconds
Started Aug 19 05:03:56 PM PDT 24
Finished Aug 19 05:03:56 PM PDT 24
Peak memory 183360 kb
Host smart-18f7c0d9-a33a-41e8-b6f5-30ef97a52297
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366497968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.366497968
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4030776982
Short name T476
Test name
Test status
Simulation time 45279660 ps
CPU time 0.55 seconds
Started Aug 19 05:03:58 PM PDT 24
Finished Aug 19 05:03:58 PM PDT 24
Peak memory 183188 kb
Host smart-f4661a74-6f4c-40ed-881a-b2d934d9d3e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030776982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.4030776982
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.4210941091
Short name T77
Test name
Test status
Simulation time 29923150 ps
CPU time 0.76 seconds
Started Aug 19 05:03:49 PM PDT 24
Finished Aug 19 05:03:50 PM PDT 24
Peak memory 193908 kb
Host smart-ced63b77-b234-4a37-8051-e92e823e5194
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210941091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.4210941091
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1664746874
Short name T566
Test name
Test status
Simulation time 220568614 ps
CPU time 1.99 seconds
Started Aug 19 05:03:51 PM PDT 24
Finished Aug 19 05:03:53 PM PDT 24
Peak memory 198024 kb
Host smart-6d1f4e69-e424-448e-92ca-9c6f3e3dc8a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664746874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1664746874
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2777642916
Short name T488
Test name
Test status
Simulation time 189031828 ps
CPU time 0.84 seconds
Started Aug 19 05:03:58 PM PDT 24
Finished Aug 19 05:03:59 PM PDT 24
Peak memory 193356 kb
Host smart-0b017e76-ad0f-46c4-bfdb-de1e1d45c384
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777642916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2777642916
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2734187774
Short name T501
Test name
Test status
Simulation time 34169087 ps
CPU time 0.82 seconds
Started Aug 19 05:03:55 PM PDT 24
Finished Aug 19 05:03:56 PM PDT 24
Peak memory 196148 kb
Host smart-3a401178-dbcb-4f4f-959f-9a7c10edfb2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734187774 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2734187774
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1550995143
Short name T533
Test name
Test status
Simulation time 54927616 ps
CPU time 0.55 seconds
Started Aug 19 05:03:56 PM PDT 24
Finished Aug 19 05:03:56 PM PDT 24
Peak memory 183356 kb
Host smart-17ac90bf-7cfc-47b5-a268-3d47782cd4e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550995143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1550995143
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.691063733
Short name T528
Test name
Test status
Simulation time 59063316 ps
CPU time 0.56 seconds
Started Aug 19 05:03:50 PM PDT 24
Finished Aug 19 05:03:51 PM PDT 24
Peak memory 183196 kb
Host smart-5383af68-7acf-4318-a378-0b5e2ee9a1a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691063733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.691063733
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.383234229
Short name T485
Test name
Test status
Simulation time 19604063 ps
CPU time 0.6 seconds
Started Aug 19 05:03:49 PM PDT 24
Finished Aug 19 05:03:50 PM PDT 24
Peak memory 192596 kb
Host smart-353c8a70-4d5c-4847-aa73-1262e1e1f7cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383234229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.383234229
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3090627576
Short name T493
Test name
Test status
Simulation time 288959700 ps
CPU time 2.4 seconds
Started Aug 19 05:03:55 PM PDT 24
Finished Aug 19 05:03:58 PM PDT 24
Peak memory 198128 kb
Host smart-14c7e416-a12e-4052-8134-74d3a4c049dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090627576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3090627576
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3673060638
Short name T83
Test name
Test status
Simulation time 133368444 ps
CPU time 1.31 seconds
Started Aug 19 05:03:54 PM PDT 24
Finished Aug 19 05:03:55 PM PDT 24
Peak memory 184012 kb
Host smart-17a7bf84-2756-4790-8091-d15f54442f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673060638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3673060638
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3337122262
Short name T560
Test name
Test status
Simulation time 18117540 ps
CPU time 0.92 seconds
Started Aug 19 05:03:59 PM PDT 24
Finished Aug 19 05:04:00 PM PDT 24
Peak memory 197488 kb
Host smart-5b985598-ad1f-4815-bbda-aa4b9399f909
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337122262 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3337122262
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2059453741
Short name T464
Test name
Test status
Simulation time 30602510 ps
CPU time 0.57 seconds
Started Aug 19 05:03:52 PM PDT 24
Finished Aug 19 05:03:53 PM PDT 24
Peak memory 183388 kb
Host smart-ba1f968e-9415-4241-bce4-f18613670702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059453741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2059453741
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.121112699
Short name T484
Test name
Test status
Simulation time 11428140 ps
CPU time 0.59 seconds
Started Aug 19 05:03:59 PM PDT 24
Finished Aug 19 05:04:00 PM PDT 24
Peak memory 182724 kb
Host smart-425eca98-77bd-4810-8f47-9b87b1a345e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121112699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.121112699
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2876095040
Short name T67
Test name
Test status
Simulation time 91176371 ps
CPU time 0.71 seconds
Started Aug 19 05:03:56 PM PDT 24
Finished Aug 19 05:03:57 PM PDT 24
Peak memory 192856 kb
Host smart-d59f4d09-933f-4cd0-8d44-76b69cdfd6f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876095040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2876095040
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3190543116
Short name T468
Test name
Test status
Simulation time 46421178 ps
CPU time 1.01 seconds
Started Aug 19 05:03:51 PM PDT 24
Finished Aug 19 05:03:52 PM PDT 24
Peak memory 197852 kb
Host smart-938efbbb-21f6-4e99-b6ed-b789dbdad3d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190543116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3190543116
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.382247601
Short name T540
Test name
Test status
Simulation time 157449626 ps
CPU time 0.83 seconds
Started Aug 19 05:03:49 PM PDT 24
Finished Aug 19 05:03:50 PM PDT 24
Peak memory 194436 kb
Host smart-dc66a842-8707-4618-abd3-03bc9818e8a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382247601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.382247601
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.290761365
Short name T30
Test name
Test status
Simulation time 87625262 ps
CPU time 1.18 seconds
Started Aug 19 05:03:50 PM PDT 24
Finished Aug 19 05:03:51 PM PDT 24
Peak memory 198132 kb
Host smart-bbe83057-b10d-4c53-a920-a74a5e3188bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290761365 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.290761365
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.128099430
Short name T557
Test name
Test status
Simulation time 12499195 ps
CPU time 0.56 seconds
Started Aug 19 05:03:50 PM PDT 24
Finished Aug 19 05:03:50 PM PDT 24
Peak memory 183392 kb
Host smart-f85c9301-c69f-4f67-b483-6c7a3ef49716
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128099430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.128099430
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4123416112
Short name T500
Test name
Test status
Simulation time 127128835 ps
CPU time 0.57 seconds
Started Aug 19 05:03:48 PM PDT 24
Finished Aug 19 05:03:49 PM PDT 24
Peak memory 183232 kb
Host smart-713d5401-e093-447d-aa41-17fcca91e8a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123416112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.4123416112
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4019357762
Short name T486
Test name
Test status
Simulation time 185509798 ps
CPU time 0.69 seconds
Started Aug 19 05:03:54 PM PDT 24
Finished Aug 19 05:03:55 PM PDT 24
Peak memory 192908 kb
Host smart-5e5e3367-6aa5-428a-becb-43d1d10f2910
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019357762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.4019357762
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.711999266
Short name T555
Test name
Test status
Simulation time 733485993 ps
CPU time 2.97 seconds
Started Aug 19 05:03:58 PM PDT 24
Finished Aug 19 05:04:01 PM PDT 24
Peak memory 198184 kb
Host smart-b0244372-1164-4263-90e5-6585f8b0f976
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711999266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.711999266
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1721732927
Short name T527
Test name
Test status
Simulation time 40553842 ps
CPU time 0.82 seconds
Started Aug 19 05:03:56 PM PDT 24
Finished Aug 19 05:03:57 PM PDT 24
Peak memory 194208 kb
Host smart-886bae45-8e60-4959-92fe-6677c2b84833
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721732927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1721732927
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.108437920
Short name T529
Test name
Test status
Simulation time 55156579 ps
CPU time 0.72 seconds
Started Aug 19 05:03:57 PM PDT 24
Finished Aug 19 05:03:57 PM PDT 24
Peak memory 196108 kb
Host smart-99c063a0-c269-471f-bd08-60d09c45dade
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108437920 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.108437920
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1581370649
Short name T496
Test name
Test status
Simulation time 15425614 ps
CPU time 0.59 seconds
Started Aug 19 05:03:57 PM PDT 24
Finished Aug 19 05:03:58 PM PDT 24
Peak memory 183320 kb
Host smart-17e7e1d0-54b9-4735-9aa9-999c21965ced
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581370649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1581370649
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3090736777
Short name T512
Test name
Test status
Simulation time 85920985 ps
CPU time 0.54 seconds
Started Aug 19 05:03:57 PM PDT 24
Finished Aug 19 05:03:57 PM PDT 24
Peak memory 183304 kb
Host smart-d7290723-e2b0-4080-bd39-effaa8d4b963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090736777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3090736777
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.161410655
Short name T547
Test name
Test status
Simulation time 31110525 ps
CPU time 0.76 seconds
Started Aug 19 05:03:55 PM PDT 24
Finished Aug 19 05:03:56 PM PDT 24
Peak memory 193916 kb
Host smart-0b34ff84-5eda-48de-ba90-ede33d91b2b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161410655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.161410655
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.483234620
Short name T569
Test name
Test status
Simulation time 326477106 ps
CPU time 3.24 seconds
Started Aug 19 05:03:49 PM PDT 24
Finished Aug 19 05:03:53 PM PDT 24
Peak memory 198108 kb
Host smart-c5b00824-5e17-426c-9999-95ad33983ab1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483234620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.483234620
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.488967189
Short name T82
Test name
Test status
Simulation time 517866527 ps
CPU time 1.4 seconds
Started Aug 19 05:03:49 PM PDT 24
Finished Aug 19 05:03:51 PM PDT 24
Peak memory 195456 kb
Host smart-1b08ded4-7cff-4282-8864-70f508ff92d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488967189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.488967189
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.421672397
Short name T236
Test name
Test status
Simulation time 285445794355 ps
CPU time 491.26 seconds
Started Aug 19 04:37:19 PM PDT 24
Finished Aug 19 04:45:30 PM PDT 24
Peak memory 183592 kb
Host smart-72b1983c-af61-4f8a-87d5-5e571a00f8de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421672397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.421672397
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.322331914
Short name T365
Test name
Test status
Simulation time 18285419303 ps
CPU time 26.29 seconds
Started Aug 19 04:37:07 PM PDT 24
Finished Aug 19 04:37:33 PM PDT 24
Peak memory 183604 kb
Host smart-0a1caa78-b6ef-41df-9a4c-b3ca85b32fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322331914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.322331914
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.801743578
Short name T298
Test name
Test status
Simulation time 728942582628 ps
CPU time 371.73 seconds
Started Aug 19 04:37:16 PM PDT 24
Finished Aug 19 04:43:28 PM PDT 24
Peak memory 191728 kb
Host smart-5e8b955c-79a2-40d1-a5e8-e823c6fd1ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801743578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.801743578
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3768913756
Short name T26
Test name
Test status
Simulation time 6474256496 ps
CPU time 10.94 seconds
Started Aug 19 04:37:22 PM PDT 24
Finished Aug 19 04:37:33 PM PDT 24
Peak memory 183592 kb
Host smart-c10ea072-c5eb-4a52-b58f-c54899943e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768913756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3768913756
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2581278310
Short name T343
Test name
Test status
Simulation time 574383527950 ps
CPU time 1002.41 seconds
Started Aug 19 04:37:24 PM PDT 24
Finished Aug 19 04:54:06 PM PDT 24
Peak memory 195452 kb
Host smart-b0d107b6-8d09-4bdc-8eb5-2790d9db4083
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581278310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2581278310
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3780750241
Short name T372
Test name
Test status
Simulation time 220129782646 ps
CPU time 322.54 seconds
Started Aug 19 04:37:10 PM PDT 24
Finished Aug 19 04:42:33 PM PDT 24
Peak memory 183624 kb
Host smart-bac67d4b-9065-4ab5-9ec3-3e1c5aff1689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780750241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3780750241
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1936328084
Short name T350
Test name
Test status
Simulation time 222506983711 ps
CPU time 682.6 seconds
Started Aug 19 04:37:21 PM PDT 24
Finished Aug 19 04:48:43 PM PDT 24
Peak memory 191820 kb
Host smart-5937f3e0-c0c6-41a8-8552-befcf615366f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936328084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1936328084
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1436525052
Short name T15
Test name
Test status
Simulation time 467584625 ps
CPU time 0.85 seconds
Started Aug 19 04:37:10 PM PDT 24
Finished Aug 19 04:37:11 PM PDT 24
Peak memory 214072 kb
Host smart-8290c3a8-d5d4-44f6-972f-98264b35b205
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436525052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1436525052
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1812123277
Short name T406
Test name
Test status
Simulation time 97710948744 ps
CPU time 154.52 seconds
Started Aug 19 04:37:11 PM PDT 24
Finished Aug 19 04:39:46 PM PDT 24
Peak memory 183616 kb
Host smart-d57c9f4d-5c67-4539-ae5f-009609440bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812123277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1812123277
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1855351974
Short name T225
Test name
Test status
Simulation time 71711384134 ps
CPU time 136.85 seconds
Started Aug 19 04:37:18 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 191804 kb
Host smart-6665fca2-d481-4c88-8d3d-333a786d0997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855351974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1855351974
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1463856013
Short name T414
Test name
Test status
Simulation time 105970367 ps
CPU time 0.74 seconds
Started Aug 19 04:37:14 PM PDT 24
Finished Aug 19 04:37:15 PM PDT 24
Peak memory 183316 kb
Host smart-bb0f197d-d620-4aaa-a301-9d2d7723484d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463856013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1463856013
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.34515613
Short name T36
Test name
Test status
Simulation time 1507299043 ps
CPU time 10.79 seconds
Started Aug 19 04:37:10 PM PDT 24
Finished Aug 19 04:37:21 PM PDT 24
Peak memory 198080 kb
Host smart-77f4752e-9328-4f7e-b18f-79529857631e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34515613 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.34515613
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.3853573860
Short name T8
Test name
Test status
Simulation time 70793123022 ps
CPU time 117.84 seconds
Started Aug 19 04:37:57 PM PDT 24
Finished Aug 19 04:39:55 PM PDT 24
Peak memory 191780 kb
Host smart-8e18870f-d016-49e3-bdfa-57b992eb0979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853573860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3853573860
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2426671698
Short name T303
Test name
Test status
Simulation time 92806186018 ps
CPU time 128.99 seconds
Started Aug 19 04:37:34 PM PDT 24
Finished Aug 19 04:39:44 PM PDT 24
Peak memory 183412 kb
Host smart-43c5ed64-2359-425b-82e2-d7ce53f2f226
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426671698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2426671698
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.4006517856
Short name T441
Test name
Test status
Simulation time 7297877998 ps
CPU time 7.22 seconds
Started Aug 19 04:37:31 PM PDT 24
Finished Aug 19 04:37:39 PM PDT 24
Peak memory 195316 kb
Host smart-e590f7bc-99a7-40e6-b80c-67e9fbe7fb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006517856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.4006517856
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.712179632
Short name T435
Test name
Test status
Simulation time 50331193232 ps
CPU time 329.34 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:43:32 PM PDT 24
Peak memory 183600 kb
Host smart-1df873ae-cc3a-47e9-8787-2c02b452577e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712179632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.712179632
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1254727450
Short name T92
Test name
Test status
Simulation time 80536598078 ps
CPU time 281.51 seconds
Started Aug 19 04:38:00 PM PDT 24
Finished Aug 19 04:42:42 PM PDT 24
Peak memory 191780 kb
Host smart-3d94ba24-1af8-4a86-a674-9be8269c8545
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254727450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1254727450
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3072695880
Short name T214
Test name
Test status
Simulation time 174446121574 ps
CPU time 3537.87 seconds
Started Aug 19 04:37:57 PM PDT 24
Finished Aug 19 05:36:55 PM PDT 24
Peak memory 191788 kb
Host smart-9bed2807-959e-4f6e-a3d1-ad6ce2c9232a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072695880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3072695880
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2949594854
Short name T115
Test name
Test status
Simulation time 5042468656 ps
CPU time 14.8 seconds
Started Aug 19 04:38:05 PM PDT 24
Finished Aug 19 04:38:20 PM PDT 24
Peak memory 183588 kb
Host smart-44d443d7-1c9b-4795-bf56-2844d095fe92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949594854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2949594854
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2302890508
Short name T359
Test name
Test status
Simulation time 8481436525 ps
CPU time 14.74 seconds
Started Aug 19 04:38:09 PM PDT 24
Finished Aug 19 04:38:24 PM PDT 24
Peak memory 183620 kb
Host smart-41c8b9d0-22f6-4e22-b046-4b8306f89295
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302890508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2302890508
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3904792276
Short name T420
Test name
Test status
Simulation time 31296668398 ps
CPU time 30.18 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:38:33 PM PDT 24
Peak memory 191744 kb
Host smart-caaf0c31-9b04-4b0f-a543-0af382f096f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904792276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3904792276
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.691756396
Short name T353
Test name
Test status
Simulation time 300816043146 ps
CPU time 61.69 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:39:03 PM PDT 24
Peak memory 183360 kb
Host smart-955737ce-944a-4972-bf2b-021bfd83b90d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691756396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.691756396
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3704402722
Short name T110
Test name
Test status
Simulation time 352612043264 ps
CPU time 442.74 seconds
Started Aug 19 04:37:24 PM PDT 24
Finished Aug 19 04:44:46 PM PDT 24
Peak memory 183568 kb
Host smart-9a9edddc-f846-40a7-b68a-4f68bcf6dd73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704402722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3704402722
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3794664391
Short name T387
Test name
Test status
Simulation time 59137487400 ps
CPU time 92.68 seconds
Started Aug 19 04:37:19 PM PDT 24
Finished Aug 19 04:38:52 PM PDT 24
Peak memory 183580 kb
Host smart-80c1d657-9a19-4f43-8c7e-a477eaa96ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794664391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3794664391
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1715888807
Short name T412
Test name
Test status
Simulation time 692724438 ps
CPU time 1.41 seconds
Started Aug 19 04:37:14 PM PDT 24
Finished Aug 19 04:37:15 PM PDT 24
Peak memory 191692 kb
Host smart-8dc0bac0-518d-4cb1-af6c-55e33ca5ca5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715888807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1715888807
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.4009232739
Short name T221
Test name
Test status
Simulation time 746523210106 ps
CPU time 2036.45 seconds
Started Aug 19 04:37:15 PM PDT 24
Finished Aug 19 05:11:12 PM PDT 24
Peak memory 191796 kb
Host smart-ea488d7c-520b-49ec-b7d4-b15fd30086d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009232739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.4009232739
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.538602842
Short name T407
Test name
Test status
Simulation time 1774127610 ps
CPU time 16.24 seconds
Started Aug 19 04:37:14 PM PDT 24
Finished Aug 19 04:37:30 PM PDT 24
Peak memory 198156 kb
Host smart-1c2e1a55-98f7-4127-9c42-c4d8615347a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538602842 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.538602842
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.3587945776
Short name T201
Test name
Test status
Simulation time 43936887020 ps
CPU time 68.43 seconds
Started Aug 19 04:37:53 PM PDT 24
Finished Aug 19 04:39:01 PM PDT 24
Peak memory 191796 kb
Host smart-42381ceb-bb4e-4734-9f66-ce8a847658b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587945776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3587945776
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1031138073
Short name T330
Test name
Test status
Simulation time 46408892418 ps
CPU time 118.33 seconds
Started Aug 19 04:37:57 PM PDT 24
Finished Aug 19 04:39:55 PM PDT 24
Peak memory 191720 kb
Host smart-dcd42b06-7084-4ddf-8b24-6ebd48bd87d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031138073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1031138073
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3324696022
Short name T198
Test name
Test status
Simulation time 156508358101 ps
CPU time 1329.64 seconds
Started Aug 19 04:37:56 PM PDT 24
Finished Aug 19 05:00:06 PM PDT 24
Peak memory 191780 kb
Host smart-61a86c23-8ca2-4e44-9d49-b4902af611fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324696022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3324696022
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3860950635
Short name T158
Test name
Test status
Simulation time 81664347886 ps
CPU time 131.85 seconds
Started Aug 19 04:38:01 PM PDT 24
Finished Aug 19 04:40:13 PM PDT 24
Peak memory 191780 kb
Host smart-50ca2b0a-afde-4dd8-b112-8486c4f7dd98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860950635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3860950635
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3069516214
Short name T260
Test name
Test status
Simulation time 1388975675682 ps
CPU time 796.96 seconds
Started Aug 19 04:37:55 PM PDT 24
Finished Aug 19 04:51:12 PM PDT 24
Peak memory 191812 kb
Host smart-5cf5cd4b-d9c9-492e-b3ca-10c869cf91bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069516214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3069516214
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.600634853
Short name T319
Test name
Test status
Simulation time 1409202158604 ps
CPU time 647.75 seconds
Started Aug 19 04:38:17 PM PDT 24
Finished Aug 19 04:49:05 PM PDT 24
Peak memory 191804 kb
Host smart-ea112580-86d2-40a2-a4c8-7c1e2b018144
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600634853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.600634853
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1614891055
Short name T199
Test name
Test status
Simulation time 60181786194 ps
CPU time 102.76 seconds
Started Aug 19 04:38:06 PM PDT 24
Finished Aug 19 04:39:49 PM PDT 24
Peak memory 191680 kb
Host smart-237e13f6-ee37-4e64-b097-5d1f69468e9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614891055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1614891055
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.120149433
Short name T1
Test name
Test status
Simulation time 15582452657 ps
CPU time 24.47 seconds
Started Aug 19 04:37:55 PM PDT 24
Finished Aug 19 04:38:19 PM PDT 24
Peak memory 183600 kb
Host smart-e96fc601-92be-4f0c-87e6-531a0bffd6bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120149433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.120149433
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3316030427
Short name T235
Test name
Test status
Simulation time 110543530802 ps
CPU time 169.83 seconds
Started Aug 19 04:37:15 PM PDT 24
Finished Aug 19 04:40:05 PM PDT 24
Peak memory 183596 kb
Host smart-8f94e193-3758-4408-b6f8-d2b90943c68e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316030427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3316030427
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1655361056
Short name T367
Test name
Test status
Simulation time 107219469024 ps
CPU time 76.06 seconds
Started Aug 19 04:37:35 PM PDT 24
Finished Aug 19 04:38:51 PM PDT 24
Peak memory 183564 kb
Host smart-ed02b758-6d24-4be1-9083-ba5cccc97eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655361056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1655361056
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.1840940397
Short name T321
Test name
Test status
Simulation time 70556337254 ps
CPU time 1382.92 seconds
Started Aug 19 04:37:53 PM PDT 24
Finished Aug 19 05:00:56 PM PDT 24
Peak memory 191704 kb
Host smart-4fffa57a-48ee-4f4e-bf38-2fbcfc44a9a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840940397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1840940397
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2346247742
Short name T40
Test name
Test status
Simulation time 33212982753 ps
CPU time 50.54 seconds
Started Aug 19 04:37:35 PM PDT 24
Finished Aug 19 04:38:26 PM PDT 24
Peak memory 193920 kb
Host smart-a4e4b7bd-33df-4cf8-8ebd-d3fdcce9e9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346247742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2346247742
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3553343683
Short name T59
Test name
Test status
Simulation time 2597508910440 ps
CPU time 1074.31 seconds
Started Aug 19 04:37:23 PM PDT 24
Finished Aug 19 04:55:18 PM PDT 24
Peak memory 191760 kb
Host smart-1ebcec20-bbe6-424e-a797-207701ff06f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553343683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3553343683
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.1165165295
Short name T434
Test name
Test status
Simulation time 10802134230 ps
CPU time 23.55 seconds
Started Aug 19 04:37:14 PM PDT 24
Finished Aug 19 04:37:38 PM PDT 24
Peak memory 198264 kb
Host smart-72586cca-ca0b-4126-9d95-78acfb18f212
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165165295 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.1165165295
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.4137312702
Short name T99
Test name
Test status
Simulation time 93784220392 ps
CPU time 431.63 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:45:15 PM PDT 24
Peak memory 191804 kb
Host smart-654c98e4-916d-46f9-ae36-6341024469a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137312702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.4137312702
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.4144727044
Short name T88
Test name
Test status
Simulation time 432904164919 ps
CPU time 335.19 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:43:37 PM PDT 24
Peak memory 191800 kb
Host smart-6432be65-b5c7-4f00-9061-bcb7ddbf39d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144727044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.4144727044
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.947947659
Short name T261
Test name
Test status
Simulation time 125436069154 ps
CPU time 204.67 seconds
Started Aug 19 04:37:57 PM PDT 24
Finished Aug 19 04:41:22 PM PDT 24
Peak memory 191772 kb
Host smart-38ac7e23-f40e-41c3-be8f-0d24b11a0e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947947659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.947947659
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3782324185
Short name T112
Test name
Test status
Simulation time 29018183479 ps
CPU time 36.82 seconds
Started Aug 19 04:38:01 PM PDT 24
Finished Aug 19 04:38:38 PM PDT 24
Peak memory 183612 kb
Host smart-ac62db03-980c-4b3e-9cf4-ce1c52b31ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782324185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3782324185
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2576386090
Short name T355
Test name
Test status
Simulation time 17430908364 ps
CPU time 27.74 seconds
Started Aug 19 04:38:07 PM PDT 24
Finished Aug 19 04:38:36 PM PDT 24
Peak memory 183324 kb
Host smart-41c006a2-cdd1-49f0-bb29-a120e8530a8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576386090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2576386090
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2643376072
Short name T339
Test name
Test status
Simulation time 118063761911 ps
CPU time 239.45 seconds
Started Aug 19 04:37:56 PM PDT 24
Finished Aug 19 04:41:55 PM PDT 24
Peak memory 191800 kb
Host smart-d48bacef-f939-444a-b1cc-65a51304dc48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643376072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2643376072
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2027575020
Short name T394
Test name
Test status
Simulation time 32451030742 ps
CPU time 47.93 seconds
Started Aug 19 04:37:15 PM PDT 24
Finished Aug 19 04:38:03 PM PDT 24
Peak memory 183564 kb
Host smart-074cd7ea-0c33-48b1-9ddb-fca6befb144e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027575020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2027575020
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3763125699
Short name T193
Test name
Test status
Simulation time 301078572631 ps
CPU time 159.43 seconds
Started Aug 19 04:37:11 PM PDT 24
Finished Aug 19 04:39:51 PM PDT 24
Peak memory 191792 kb
Host smart-538fb70f-8c90-47a4-b8d6-cd6cba2e93c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763125699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3763125699
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.772984181
Short name T300
Test name
Test status
Simulation time 110646935076 ps
CPU time 71.76 seconds
Started Aug 19 04:37:17 PM PDT 24
Finished Aug 19 04:38:29 PM PDT 24
Peak memory 191780 kb
Host smart-f8fdb8d3-219c-4cab-adc2-ca73958e1796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772984181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.772984181
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.4128081003
Short name T43
Test name
Test status
Simulation time 13582499457 ps
CPU time 26.09 seconds
Started Aug 19 04:37:37 PM PDT 24
Finished Aug 19 04:38:04 PM PDT 24
Peak memory 198276 kb
Host smart-4c059658-364d-4c9d-9888-fd78ba022e2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128081003 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.4128081003
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.4163136249
Short name T242
Test name
Test status
Simulation time 97157356763 ps
CPU time 156.15 seconds
Started Aug 19 04:37:59 PM PDT 24
Finished Aug 19 04:40:35 PM PDT 24
Peak memory 191776 kb
Host smart-afa65437-5e9a-46f8-923c-0fd9e2e6f29d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163136249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.4163136249
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1303767252
Short name T326
Test name
Test status
Simulation time 72448705216 ps
CPU time 120.58 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:40:04 PM PDT 24
Peak memory 191780 kb
Host smart-ed0d17f9-287c-4416-9d94-1aadb2620489
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303767252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1303767252
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.84465914
Short name T102
Test name
Test status
Simulation time 147334805010 ps
CPU time 157.75 seconds
Started Aug 19 04:38:24 PM PDT 24
Finished Aug 19 04:41:02 PM PDT 24
Peak memory 191816 kb
Host smart-76cd6350-df2f-4d8e-ba0c-aced46ba92e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84465914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.84465914
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1024066370
Short name T454
Test name
Test status
Simulation time 82546279045 ps
CPU time 210.02 seconds
Started Aug 19 04:38:12 PM PDT 24
Finished Aug 19 04:41:43 PM PDT 24
Peak memory 183608 kb
Host smart-00539fd3-da6b-4ae2-a6e8-c4c187f5b1d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024066370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1024066370
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2984681774
Short name T233
Test name
Test status
Simulation time 249833896258 ps
CPU time 161.09 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:40:44 PM PDT 24
Peak memory 191800 kb
Host smart-eb8488ef-a545-4df4-878d-fe122b633ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984681774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2984681774
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.622063179
Short name T150
Test name
Test status
Simulation time 135274828615 ps
CPU time 231.38 seconds
Started Aug 19 04:38:28 PM PDT 24
Finished Aug 19 04:42:20 PM PDT 24
Peak memory 194156 kb
Host smart-2c9dc281-a392-4424-942d-3026f4db3217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622063179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.622063179
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1861297302
Short name T281
Test name
Test status
Simulation time 101336120157 ps
CPU time 170.91 seconds
Started Aug 19 04:37:33 PM PDT 24
Finished Aug 19 04:40:24 PM PDT 24
Peak memory 183572 kb
Host smart-3e5b712e-cf97-4eab-8a1c-130a5f8ce48b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861297302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1861297302
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2348528463
Short name T404
Test name
Test status
Simulation time 215005234370 ps
CPU time 62.09 seconds
Started Aug 19 04:37:22 PM PDT 24
Finished Aug 19 04:38:25 PM PDT 24
Peak memory 183572 kb
Host smart-75d87813-46fd-472f-a9d4-fba360429f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348528463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2348528463
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.829807386
Short name T426
Test name
Test status
Simulation time 50487660546 ps
CPU time 75.43 seconds
Started Aug 19 04:37:24 PM PDT 24
Finished Aug 19 04:38:40 PM PDT 24
Peak memory 183640 kb
Host smart-be99713d-bd57-46bd-9f70-661246936a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829807386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.829807386
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1613218856
Short name T356
Test name
Test status
Simulation time 177388968451 ps
CPU time 403.58 seconds
Started Aug 19 04:37:23 PM PDT 24
Finished Aug 19 04:44:07 PM PDT 24
Peak memory 191796 kb
Host smart-94254c01-9822-45d2-b2b3-0535ac1d4923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613218856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1613218856
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.2167373223
Short name T34
Test name
Test status
Simulation time 10360274235 ps
CPU time 36.52 seconds
Started Aug 19 04:37:13 PM PDT 24
Finished Aug 19 04:37:49 PM PDT 24
Peak memory 198300 kb
Host smart-086f1c84-d662-4809-bd0f-18ea12d0e198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167373223 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.2167373223
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.1752111368
Short name T162
Test name
Test status
Simulation time 237904609923 ps
CPU time 254.2 seconds
Started Aug 19 04:38:15 PM PDT 24
Finished Aug 19 04:42:29 PM PDT 24
Peak memory 191812 kb
Host smart-34d273dd-8233-42cb-80b9-d269e783a5ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752111368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1752111368
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3220722107
Short name T324
Test name
Test status
Simulation time 204435135571 ps
CPU time 208.31 seconds
Started Aug 19 04:38:19 PM PDT 24
Finished Aug 19 04:41:47 PM PDT 24
Peak memory 191808 kb
Host smart-9918e4d5-ba82-4b09-b98d-bce0d7fad613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220722107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3220722107
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2883037918
Short name T265
Test name
Test status
Simulation time 428655513742 ps
CPU time 248.12 seconds
Started Aug 19 04:38:23 PM PDT 24
Finished Aug 19 04:42:32 PM PDT 24
Peak memory 191808 kb
Host smart-ae42c640-10c8-483a-89b8-4bd13a5726e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883037918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2883037918
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1646226768
Short name T116
Test name
Test status
Simulation time 1020729776980 ps
CPU time 983.15 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:54:27 PM PDT 24
Peak memory 191804 kb
Host smart-154cc344-3943-420f-984b-2ef680cd32bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646226768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1646226768
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.863865372
Short name T320
Test name
Test status
Simulation time 162642872307 ps
CPU time 94.89 seconds
Started Aug 19 04:38:11 PM PDT 24
Finished Aug 19 04:39:46 PM PDT 24
Peak memory 183588 kb
Host smart-18ee08f0-fbb3-4657-b57a-3863e6639e9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863865372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.863865372
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1202944648
Short name T100
Test name
Test status
Simulation time 99878330736 ps
CPU time 397.89 seconds
Started Aug 19 04:38:20 PM PDT 24
Finished Aug 19 04:44:58 PM PDT 24
Peak memory 191780 kb
Host smart-8e7810fc-ad69-45e9-bb61-6583e3d60750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202944648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1202944648
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.909991698
Short name T185
Test name
Test status
Simulation time 116072375696 ps
CPU time 216.5 seconds
Started Aug 19 04:38:04 PM PDT 24
Finished Aug 19 04:41:41 PM PDT 24
Peak memory 191824 kb
Host smart-3371eaf5-15bc-47af-8392-1848686096c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909991698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.909991698
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2956927794
Short name T358
Test name
Test status
Simulation time 377307973905 ps
CPU time 359.29 seconds
Started Aug 19 04:37:28 PM PDT 24
Finished Aug 19 04:43:28 PM PDT 24
Peak memory 183568 kb
Host smart-685302f7-aadc-4065-bc07-1d62dd17188c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956927794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2956927794
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.880315906
Short name T392
Test name
Test status
Simulation time 114051042371 ps
CPU time 157.82 seconds
Started Aug 19 04:37:31 PM PDT 24
Finished Aug 19 04:40:09 PM PDT 24
Peak memory 183572 kb
Host smart-499eb4fe-4a86-40e8-85bc-c0f8855801f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880315906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.880315906
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.4077671222
Short name T445
Test name
Test status
Simulation time 36789163 ps
CPU time 0.56 seconds
Started Aug 19 04:37:38 PM PDT 24
Finished Aug 19 04:37:39 PM PDT 24
Peak memory 183240 kb
Host smart-05ab4aa0-d57f-4424-ae6c-711d0940c2c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077671222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.4077671222
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2205326873
Short name T393
Test name
Test status
Simulation time 51353455450 ps
CPU time 81.95 seconds
Started Aug 19 04:37:16 PM PDT 24
Finished Aug 19 04:38:43 PM PDT 24
Peak memory 183580 kb
Host smart-97fb2192-b318-4a7f-a815-7cc8fcd78578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205326873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2205326873
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.20673424
Short name T119
Test name
Test status
Simulation time 320787624762 ps
CPU time 116.33 seconds
Started Aug 19 04:38:23 PM PDT 24
Finished Aug 19 04:40:19 PM PDT 24
Peak memory 183600 kb
Host smart-a4e6989f-481f-4bd1-b3b0-fcaaacb3b913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20673424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.20673424
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2940822370
Short name T154
Test name
Test status
Simulation time 422265062970 ps
CPU time 406.31 seconds
Started Aug 19 04:38:17 PM PDT 24
Finished Aug 19 04:45:03 PM PDT 24
Peak memory 191812 kb
Host smart-b443cc81-e5dc-4307-a1d3-74e9cf8134e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940822370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2940822370
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1935186026
Short name T295
Test name
Test status
Simulation time 33422558167 ps
CPU time 180.47 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:41:03 PM PDT 24
Peak memory 191796 kb
Host smart-a62ffc8a-4b8c-48c5-ae2a-8aaa379caaf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935186026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1935186026
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3704767611
Short name T86
Test name
Test status
Simulation time 148891770351 ps
CPU time 531.28 seconds
Started Aug 19 04:38:20 PM PDT 24
Finished Aug 19 04:47:11 PM PDT 24
Peak memory 195252 kb
Host smart-84610633-8e66-471e-ba01-e8e6d98a3f60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704767611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3704767611
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3811575768
Short name T449
Test name
Test status
Simulation time 71918248648 ps
CPU time 344.06 seconds
Started Aug 19 04:38:19 PM PDT 24
Finished Aug 19 04:44:03 PM PDT 24
Peak memory 191828 kb
Host smart-7cbd11e2-f078-4d19-8860-71fbeddea485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811575768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3811575768
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2825494056
Short name T305
Test name
Test status
Simulation time 123263601145 ps
CPU time 181.3 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:41:04 PM PDT 24
Peak memory 191832 kb
Host smart-17823629-3b63-4142-9016-68afc74b0f01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825494056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2825494056
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2860492563
Short name T129
Test name
Test status
Simulation time 12252994657 ps
CPU time 18.47 seconds
Started Aug 19 04:38:08 PM PDT 24
Finished Aug 19 04:38:27 PM PDT 24
Peak memory 183520 kb
Host smart-6dcc07bb-21a1-463b-8b17-566592839072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860492563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2860492563
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.817164102
Short name T175
Test name
Test status
Simulation time 489327428142 ps
CPU time 547.33 seconds
Started Aug 19 04:38:19 PM PDT 24
Finished Aug 19 04:47:27 PM PDT 24
Peak memory 191812 kb
Host smart-0f7474a4-89ef-4cfd-a747-b4155128a114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817164102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.817164102
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.155833475
Short name T277
Test name
Test status
Simulation time 557520402550 ps
CPU time 321.37 seconds
Started Aug 19 04:37:57 PM PDT 24
Finished Aug 19 04:43:19 PM PDT 24
Peak memory 191784 kb
Host smart-7720a0b8-2f0f-4787-aa76-5a69d29d5447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155833475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.155833475
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2223248132
Short name T157
Test name
Test status
Simulation time 301223328932 ps
CPU time 626.92 seconds
Started Aug 19 04:38:25 PM PDT 24
Finished Aug 19 04:48:52 PM PDT 24
Peak memory 191788 kb
Host smart-5d141f35-c07d-46a1-8039-94db51071191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223248132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2223248132
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.221962713
Short name T286
Test name
Test status
Simulation time 65882808236 ps
CPU time 108.45 seconds
Started Aug 19 04:37:27 PM PDT 24
Finished Aug 19 04:39:15 PM PDT 24
Peak memory 183612 kb
Host smart-60d79525-7ecf-40e9-8e8c-da11d8f8025b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221962713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.221962713
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1166287586
Short name T403
Test name
Test status
Simulation time 46421891167 ps
CPU time 69.82 seconds
Started Aug 19 04:37:16 PM PDT 24
Finished Aug 19 04:38:26 PM PDT 24
Peak memory 183600 kb
Host smart-c07d96a1-350f-4770-9ccf-729616282507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166287586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1166287586
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3546494131
Short name T254
Test name
Test status
Simulation time 144369456049 ps
CPU time 85.82 seconds
Started Aug 19 04:37:31 PM PDT 24
Finished Aug 19 04:38:57 PM PDT 24
Peak memory 191788 kb
Host smart-26f50e12-3bfa-429f-9b9e-d4e9dc2c14ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546494131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3546494131
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2270506354
Short name T451
Test name
Test status
Simulation time 31279355056 ps
CPU time 88.28 seconds
Started Aug 19 04:38:06 PM PDT 24
Finished Aug 19 04:39:35 PM PDT 24
Peak memory 191828 kb
Host smart-1a36a79a-8571-4866-9343-21a85f86edbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270506354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2270506354
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2698826992
Short name T109
Test name
Test status
Simulation time 1789096099385 ps
CPU time 830.3 seconds
Started Aug 19 04:38:13 PM PDT 24
Finished Aug 19 04:52:03 PM PDT 24
Peak memory 191820 kb
Host smart-a82a1176-6550-4a07-b5ea-6528876becf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698826992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2698826992
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3292151814
Short name T130
Test name
Test status
Simulation time 186507297398 ps
CPU time 298.77 seconds
Started Aug 19 04:38:00 PM PDT 24
Finished Aug 19 04:42:59 PM PDT 24
Peak memory 191784 kb
Host smart-e40c656a-3453-45d8-bd06-be30cd148450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292151814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3292151814
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1884851023
Short name T240
Test name
Test status
Simulation time 293243691090 ps
CPU time 196.09 seconds
Started Aug 19 04:38:04 PM PDT 24
Finished Aug 19 04:41:21 PM PDT 24
Peak memory 191772 kb
Host smart-9a06468b-9ea4-470f-8bb4-273f46c5efb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884851023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1884851023
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2091077355
Short name T338
Test name
Test status
Simulation time 322629271251 ps
CPU time 463.22 seconds
Started Aug 19 04:38:01 PM PDT 24
Finished Aug 19 04:45:44 PM PDT 24
Peak memory 191760 kb
Host smart-09526e0d-3259-4d4a-b35b-ecc8c4d4ebb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091077355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2091077355
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2692414299
Short name T208
Test name
Test status
Simulation time 136625332842 ps
CPU time 819.37 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:51:42 PM PDT 24
Peak memory 191796 kb
Host smart-3ece48de-c1bf-470c-8041-e1b1fb35a138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692414299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2692414299
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2378982200
Short name T168
Test name
Test status
Simulation time 499161358814 ps
CPU time 1556.92 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 05:04:01 PM PDT 24
Peak memory 191796 kb
Host smart-e596b6b4-f956-4d89-95a9-2f4870176a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378982200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2378982200
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1264461280
Short name T18
Test name
Test status
Simulation time 106358709621 ps
CPU time 168.63 seconds
Started Aug 19 04:38:21 PM PDT 24
Finished Aug 19 04:41:10 PM PDT 24
Peak memory 191760 kb
Host smart-2190f866-cbe8-4961-811e-57a238bc126c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264461280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1264461280
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1182028036
Short name T123
Test name
Test status
Simulation time 683005124509 ps
CPU time 688.23 seconds
Started Aug 19 04:37:39 PM PDT 24
Finished Aug 19 04:49:07 PM PDT 24
Peak memory 183568 kb
Host smart-e948f5d5-c0ab-44b0-a583-547196784cba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182028036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1182028036
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1501607899
Short name T447
Test name
Test status
Simulation time 255143553989 ps
CPU time 169.75 seconds
Started Aug 19 04:37:34 PM PDT 24
Finished Aug 19 04:40:24 PM PDT 24
Peak memory 183588 kb
Host smart-04c16a3b-07ed-4212-bc2f-356e9d67de8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501607899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1501607899
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2654306844
Short name T107
Test name
Test status
Simulation time 752119777155 ps
CPU time 972.43 seconds
Started Aug 19 04:37:12 PM PDT 24
Finished Aug 19 04:53:25 PM PDT 24
Peak memory 191764 kb
Host smart-b72503e8-7756-421f-96e3-b61ccdf5ad22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654306844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2654306844
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1485115171
Short name T148
Test name
Test status
Simulation time 26600277379 ps
CPU time 38.02 seconds
Started Aug 19 04:37:38 PM PDT 24
Finished Aug 19 04:38:16 PM PDT 24
Peak memory 194108 kb
Host smart-6a5e00e0-73a1-4ad7-97e3-b680153fb25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485115171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1485115171
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.577134819
Short name T151
Test name
Test status
Simulation time 746038138622 ps
CPU time 624.9 seconds
Started Aug 19 04:38:04 PM PDT 24
Finished Aug 19 04:48:29 PM PDT 24
Peak memory 191800 kb
Host smart-930bc7b8-2d40-4220-9132-8fb3ca84fcba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577134819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.577134819
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2391679307
Short name T118
Test name
Test status
Simulation time 86049315023 ps
CPU time 1215.65 seconds
Started Aug 19 04:38:04 PM PDT 24
Finished Aug 19 04:58:20 PM PDT 24
Peak memory 191796 kb
Host smart-c65e70fa-b83b-4530-9e8b-df9e91efe03e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391679307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2391679307
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2899707631
Short name T122
Test name
Test status
Simulation time 462175652173 ps
CPU time 302.72 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:43:06 PM PDT 24
Peak memory 191808 kb
Host smart-32b78796-184a-4ff1-9741-be9da81f9b4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899707631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2899707631
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3848051972
Short name T161
Test name
Test status
Simulation time 360439934910 ps
CPU time 197.56 seconds
Started Aug 19 04:38:25 PM PDT 24
Finished Aug 19 04:41:43 PM PDT 24
Peak memory 191828 kb
Host smart-1aa09729-c665-4cba-a39b-1f07b9143bc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848051972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3848051972
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3044201556
Short name T411
Test name
Test status
Simulation time 18354091413 ps
CPU time 30.97 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:38:34 PM PDT 24
Peak memory 183576 kb
Host smart-bf75ca47-49d2-4dfb-a295-24d6ed41f539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044201556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3044201556
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2581390186
Short name T257
Test name
Test status
Simulation time 42861976928 ps
CPU time 72.51 seconds
Started Aug 19 04:38:17 PM PDT 24
Finished Aug 19 04:39:30 PM PDT 24
Peak memory 191808 kb
Host smart-f83ac48d-7fb3-408a-bdae-4585251bc1b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581390186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2581390186
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3862226624
Short name T344
Test name
Test status
Simulation time 96600265806 ps
CPU time 251.7 seconds
Started Aug 19 04:38:10 PM PDT 24
Finished Aug 19 04:42:22 PM PDT 24
Peak memory 191772 kb
Host smart-46d4e807-d35d-447c-995f-dd992a9163b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862226624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3862226624
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2679716081
Short name T139
Test name
Test status
Simulation time 79292572484 ps
CPU time 41.97 seconds
Started Aug 19 04:37:29 PM PDT 24
Finished Aug 19 04:38:11 PM PDT 24
Peak memory 183564 kb
Host smart-55503afe-2287-4d70-9bee-ff4c084d065a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679716081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2679716081
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.735865694
Short name T379
Test name
Test status
Simulation time 387739682589 ps
CPU time 137.17 seconds
Started Aug 19 04:37:16 PM PDT 24
Finished Aug 19 04:39:34 PM PDT 24
Peak memory 183608 kb
Host smart-8b931c30-1e28-4635-9882-a8b1f63a6c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735865694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.735865694
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1982277309
Short name T216
Test name
Test status
Simulation time 43014241712 ps
CPU time 354.31 seconds
Started Aug 19 04:37:43 PM PDT 24
Finished Aug 19 04:43:37 PM PDT 24
Peak memory 183564 kb
Host smart-073e9443-32d9-435d-9e8a-3699af3f719e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982277309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1982277309
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.2890855078
Short name T87
Test name
Test status
Simulation time 506371225595 ps
CPU time 618.13 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:48:21 PM PDT 24
Peak memory 191796 kb
Host smart-32e8d1d4-5920-4de1-be54-fbf9fa16015c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890855078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2890855078
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.312233358
Short name T327
Test name
Test status
Simulation time 489297558935 ps
CPU time 905.14 seconds
Started Aug 19 04:38:06 PM PDT 24
Finished Aug 19 04:53:12 PM PDT 24
Peak memory 191812 kb
Host smart-c498c98d-5d6b-448e-adad-882d5b8da725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312233358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.312233358
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2106695488
Short name T262
Test name
Test status
Simulation time 311290793475 ps
CPU time 990.47 seconds
Started Aug 19 04:38:22 PM PDT 24
Finished Aug 19 04:54:53 PM PDT 24
Peak memory 191828 kb
Host smart-c2cc5090-0db0-424e-99a4-518723cb1f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106695488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2106695488
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3359570985
Short name T251
Test name
Test status
Simulation time 98589325469 ps
CPU time 364.95 seconds
Started Aug 19 04:38:09 PM PDT 24
Finished Aug 19 04:44:14 PM PDT 24
Peak memory 191768 kb
Host smart-5ef8c33a-7f2f-4cab-b0e2-ab408bf614cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359570985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3359570985
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3509220402
Short name T302
Test name
Test status
Simulation time 159739080536 ps
CPU time 720.68 seconds
Started Aug 19 04:38:12 PM PDT 24
Finished Aug 19 04:50:13 PM PDT 24
Peak memory 191792 kb
Host smart-1719dde8-3d68-49e7-9849-f2a5b9284792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509220402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3509220402
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1693635603
Short name T23
Test name
Test status
Simulation time 106838606381 ps
CPU time 196.58 seconds
Started Aug 19 04:38:04 PM PDT 24
Finished Aug 19 04:41:21 PM PDT 24
Peak memory 191816 kb
Host smart-d87cbc6e-d56d-45f1-8a52-5bb26cc59998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693635603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1693635603
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.565881098
Short name T41
Test name
Test status
Simulation time 894019713622 ps
CPU time 1721.03 seconds
Started Aug 19 04:38:14 PM PDT 24
Finished Aug 19 05:06:56 PM PDT 24
Peak memory 191776 kb
Host smart-b98ff0c5-3552-4bc7-8375-e8a499628e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565881098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.565881098
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1979859253
Short name T336
Test name
Test status
Simulation time 321301973159 ps
CPU time 446.54 seconds
Started Aug 19 04:38:11 PM PDT 24
Finished Aug 19 04:45:38 PM PDT 24
Peak memory 191804 kb
Host smart-c13dae5c-471a-4a5f-b526-f2b870cbac93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979859253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1979859253
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3311883584
Short name T315
Test name
Test status
Simulation time 929548922544 ps
CPU time 886.13 seconds
Started Aug 19 04:37:14 PM PDT 24
Finished Aug 19 04:52:00 PM PDT 24
Peak memory 183604 kb
Host smart-e9c84f35-b29c-44ab-955d-eb0a958c6840
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311883584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3311883584
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.576430408
Short name T362
Test name
Test status
Simulation time 295526344978 ps
CPU time 128.06 seconds
Started Aug 19 04:37:19 PM PDT 24
Finished Aug 19 04:39:27 PM PDT 24
Peak memory 183572 kb
Host smart-2ec3a391-81b9-451e-8c77-90855ccd8d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576430408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.576430408
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1812596207
Short name T104
Test name
Test status
Simulation time 69467985610 ps
CPU time 929.18 seconds
Started Aug 19 04:37:19 PM PDT 24
Finished Aug 19 04:52:48 PM PDT 24
Peak memory 195760 kb
Host smart-2610aec6-56aa-421f-b5d3-eeb0119ac50f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812596207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1812596207
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2275811306
Short name T283
Test name
Test status
Simulation time 100594230306 ps
CPU time 44.19 seconds
Started Aug 19 04:37:19 PM PDT 24
Finished Aug 19 04:38:03 PM PDT 24
Peak memory 183604 kb
Host smart-3c525f24-8e05-41ef-ac83-0cbf98093bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275811306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2275811306
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.111036651
Short name T16
Test name
Test status
Simulation time 88921466 ps
CPU time 0.92 seconds
Started Aug 19 04:37:07 PM PDT 24
Finished Aug 19 04:37:08 PM PDT 24
Peak memory 215088 kb
Host smart-59fd216b-48b9-473a-85d4-f71a9a0826af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111036651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.111036651
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1473530037
Short name T275
Test name
Test status
Simulation time 378116296356 ps
CPU time 242.91 seconds
Started Aug 19 04:37:25 PM PDT 24
Finished Aug 19 04:41:28 PM PDT 24
Peak memory 183540 kb
Host smart-1ce64a02-a2d7-47a5-8e62-4acc94f98fd1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473530037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1473530037
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3293335862
Short name T384
Test name
Test status
Simulation time 470504016223 ps
CPU time 288.8 seconds
Started Aug 19 04:37:26 PM PDT 24
Finished Aug 19 04:42:15 PM PDT 24
Peak memory 183592 kb
Host smart-38db2c73-ee1b-4a59-90a9-d8beb934bead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293335862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3293335862
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2438776765
Short name T133
Test name
Test status
Simulation time 217542955419 ps
CPU time 575.59 seconds
Started Aug 19 04:37:27 PM PDT 24
Finished Aug 19 04:47:02 PM PDT 24
Peak memory 191828 kb
Host smart-b37f7d7b-a15a-4f2a-9dfe-0d941608a1ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438776765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2438776765
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3883412286
Short name T450
Test name
Test status
Simulation time 14631555809 ps
CPU time 6.94 seconds
Started Aug 19 04:37:26 PM PDT 24
Finished Aug 19 04:37:33 PM PDT 24
Peak memory 194092 kb
Host smart-6f8c0396-bf39-4418-a061-58a15b879ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883412286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3883412286
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3344959083
Short name T146
Test name
Test status
Simulation time 2734511242851 ps
CPU time 612.25 seconds
Started Aug 19 04:37:21 PM PDT 24
Finished Aug 19 04:47:34 PM PDT 24
Peak memory 191788 kb
Host smart-f887bdc0-8684-4426-863c-64f1e356b034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344959083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3344959083
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.2400133746
Short name T400
Test name
Test status
Simulation time 5887441211 ps
CPU time 67.92 seconds
Started Aug 19 04:37:16 PM PDT 24
Finished Aug 19 04:38:24 PM PDT 24
Peak memory 198324 kb
Host smart-3ff6aca6-e828-484e-a8c2-016da54ca0ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400133746 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.2400133746
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3819077270
Short name T433
Test name
Test status
Simulation time 423213079197 ps
CPU time 148.82 seconds
Started Aug 19 04:37:15 PM PDT 24
Finished Aug 19 04:39:44 PM PDT 24
Peak memory 183632 kb
Host smart-aedc40b1-3ba1-45eb-b27d-ea428fef385a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819077270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3819077270
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.4004396287
Short name T219
Test name
Test status
Simulation time 33561721838 ps
CPU time 47.45 seconds
Started Aug 19 04:37:43 PM PDT 24
Finished Aug 19 04:38:31 PM PDT 24
Peak memory 195388 kb
Host smart-b3e7c8da-bb76-448d-98d6-0bf89e9cbe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004396287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.4004396287
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2241227963
Short name T429
Test name
Test status
Simulation time 60954928722 ps
CPU time 99.91 seconds
Started Aug 19 04:37:15 PM PDT 24
Finished Aug 19 04:38:55 PM PDT 24
Peak memory 183564 kb
Host smart-aad638db-3243-4d81-9f02-d9a9c9285cf6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241227963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2241227963
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2747094281
Short name T376
Test name
Test status
Simulation time 130696607141 ps
CPU time 49.36 seconds
Started Aug 19 04:37:25 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 183568 kb
Host smart-cf99e463-0fb1-442c-a4ba-7bc5c75780a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747094281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2747094281
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2783682250
Short name T244
Test name
Test status
Simulation time 81546637826 ps
CPU time 523.42 seconds
Started Aug 19 04:37:21 PM PDT 24
Finished Aug 19 04:46:04 PM PDT 24
Peak memory 191776 kb
Host smart-41e2926f-878c-47c3-a9b4-3d5f713e4f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783682250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2783682250
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1658541427
Short name T373
Test name
Test status
Simulation time 85587967 ps
CPU time 0.57 seconds
Started Aug 19 04:37:22 PM PDT 24
Finished Aug 19 04:37:22 PM PDT 24
Peak memory 183236 kb
Host smart-0d6b7614-2b50-49bc-b461-09dde7d742c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658541427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1658541427
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.4035298058
Short name T309
Test name
Test status
Simulation time 636399179128 ps
CPU time 318.33 seconds
Started Aug 19 04:37:34 PM PDT 24
Finished Aug 19 04:42:53 PM PDT 24
Peak memory 183524 kb
Host smart-33673027-4e5d-4490-8228-08b39f0b05be
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035298058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.4035298058
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2335310682
Short name T19
Test name
Test status
Simulation time 409352937353 ps
CPU time 79.79 seconds
Started Aug 19 04:37:43 PM PDT 24
Finished Aug 19 04:39:03 PM PDT 24
Peak memory 183624 kb
Host smart-b948b2be-ecb4-4c61-997d-9802c1c3b3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335310682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2335310682
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.876204951
Short name T114
Test name
Test status
Simulation time 32561962916 ps
CPU time 38.31 seconds
Started Aug 19 04:37:13 PM PDT 24
Finished Aug 19 04:37:51 PM PDT 24
Peak memory 191776 kb
Host smart-320db0cf-226a-43da-9ac8-e9322f1c1978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876204951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.876204951
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2887566496
Short name T332
Test name
Test status
Simulation time 830064452610 ps
CPU time 2006.38 seconds
Started Aug 19 04:37:48 PM PDT 24
Finished Aug 19 05:11:15 PM PDT 24
Peak memory 195876 kb
Host smart-9bab8e09-aa9a-4b6b-8eee-036cac6da8a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887566496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2887566496
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.3027308278
Short name T38
Test name
Test status
Simulation time 1504061981 ps
CPU time 16.9 seconds
Started Aug 19 04:37:28 PM PDT 24
Finished Aug 19 04:37:47 PM PDT 24
Peak memory 198148 kb
Host smart-7ff2c2bf-3389-4bf2-b6e0-e4ce2a4bf20a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027308278 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.3027308278
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1619917151
Short name T456
Test name
Test status
Simulation time 345208288660 ps
CPU time 543.66 seconds
Started Aug 19 04:37:26 PM PDT 24
Finished Aug 19 04:46:30 PM PDT 24
Peak memory 183532 kb
Host smart-bfe553f4-124c-427b-9a16-dcf8ef3e08ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619917151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1619917151
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.711905229
Short name T446
Test name
Test status
Simulation time 128627086501 ps
CPU time 51.96 seconds
Started Aug 19 04:37:46 PM PDT 24
Finished Aug 19 04:38:38 PM PDT 24
Peak memory 183612 kb
Host smart-50d3e1b4-622d-4a82-a448-0160a9033c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711905229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.711905229
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.786913005
Short name T301
Test name
Test status
Simulation time 438466673851 ps
CPU time 273.17 seconds
Started Aug 19 04:37:38 PM PDT 24
Finished Aug 19 04:42:11 PM PDT 24
Peak memory 191760 kb
Host smart-618af04e-b322-4197-aaa7-0229da0f9ec7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786913005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.786913005
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.386248302
Short name T328
Test name
Test status
Simulation time 88480597524 ps
CPU time 1546.68 seconds
Started Aug 19 04:37:26 PM PDT 24
Finished Aug 19 05:03:13 PM PDT 24
Peak memory 191800 kb
Host smart-c2d74e78-0523-4e34-9ddd-83c6baaeee51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386248302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.386248302
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3056225550
Short name T431
Test name
Test status
Simulation time 520222062855 ps
CPU time 221.62 seconds
Started Aug 19 04:37:13 PM PDT 24
Finished Aug 19 04:40:55 PM PDT 24
Peak memory 196388 kb
Host smart-13736ca8-0a2a-485e-8271-9e179030a5f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056225550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3056225550
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3784375634
Short name T360
Test name
Test status
Simulation time 921134620326 ps
CPU time 287.85 seconds
Started Aug 19 04:37:34 PM PDT 24
Finished Aug 19 04:42:22 PM PDT 24
Peak memory 183624 kb
Host smart-f29513a3-5bcf-4f9f-a3a5-51d5a479fc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784375634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3784375634
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.689306387
Short name T182
Test name
Test status
Simulation time 143807490793 ps
CPU time 1657.93 seconds
Started Aug 19 04:37:28 PM PDT 24
Finished Aug 19 05:05:06 PM PDT 24
Peak memory 191800 kb
Host smart-f305aa37-2081-4675-b07c-48689e4b4684
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689306387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.689306387
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2141016187
Short name T340
Test name
Test status
Simulation time 808789114583 ps
CPU time 948.9 seconds
Started Aug 19 04:37:45 PM PDT 24
Finished Aug 19 04:53:34 PM PDT 24
Peak memory 191736 kb
Host smart-8370ec5a-bc53-4eca-b32b-0ca7e7b0beeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141016187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2141016187
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2882731537
Short name T252
Test name
Test status
Simulation time 25940898434 ps
CPU time 43.89 seconds
Started Aug 19 04:37:31 PM PDT 24
Finished Aug 19 04:38:15 PM PDT 24
Peak memory 183568 kb
Host smart-d33a7b36-d148-41b4-9787-210b397148e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882731537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2882731537
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3065860903
Short name T383
Test name
Test status
Simulation time 67585549736 ps
CPU time 55.51 seconds
Started Aug 19 04:37:43 PM PDT 24
Finished Aug 19 04:38:39 PM PDT 24
Peak memory 183560 kb
Host smart-96f1a814-d6c5-491f-b7a1-ef502076030f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065860903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3065860903
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3259692255
Short name T249
Test name
Test status
Simulation time 183656314214 ps
CPU time 442.66 seconds
Started Aug 19 04:37:29 PM PDT 24
Finished Aug 19 04:44:52 PM PDT 24
Peak memory 191816 kb
Host smart-343ba663-ba76-43cb-b975-c2891b12bc6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259692255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3259692255
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1630185946
Short name T425
Test name
Test status
Simulation time 20151976 ps
CPU time 0.53 seconds
Started Aug 19 04:37:27 PM PDT 24
Finished Aug 19 04:37:27 PM PDT 24
Peak memory 183276 kb
Host smart-74e6f494-a5ba-4c29-81a9-679ef95c02ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630185946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1630185946
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.119744254
Short name T334
Test name
Test status
Simulation time 135109915773 ps
CPU time 600.57 seconds
Started Aug 19 04:37:16 PM PDT 24
Finished Aug 19 04:47:16 PM PDT 24
Peak memory 191740 kb
Host smart-9bfb8625-934a-4ee2-94dd-b1829a8550d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119744254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
119744254
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1404683794
Short name T279
Test name
Test status
Simulation time 297000233219 ps
CPU time 456.44 seconds
Started Aug 19 04:37:33 PM PDT 24
Finished Aug 19 04:45:09 PM PDT 24
Peak memory 183548 kb
Host smart-0b370229-f3eb-4e42-a97f-f038619b2ed7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404683794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1404683794
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3232064279
Short name T408
Test name
Test status
Simulation time 96258843074 ps
CPU time 124.95 seconds
Started Aug 19 04:37:34 PM PDT 24
Finished Aug 19 04:39:39 PM PDT 24
Peak memory 183592 kb
Host smart-3689b5d4-8e7a-4218-acc4-08b70a51c452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232064279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3232064279
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2902508171
Short name T121
Test name
Test status
Simulation time 786236397604 ps
CPU time 539.62 seconds
Started Aug 19 04:37:45 PM PDT 24
Finished Aug 19 04:46:45 PM PDT 24
Peak memory 191752 kb
Host smart-1f555e7a-5c58-4ae0-9062-8fd61e936f7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902508171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2902508171
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.960802593
Short name T342
Test name
Test status
Simulation time 26757785561 ps
CPU time 38.17 seconds
Started Aug 19 04:37:41 PM PDT 24
Finished Aug 19 04:38:19 PM PDT 24
Peak memory 191788 kb
Host smart-5aa969fc-4f21-42e4-9293-74a0e1f62653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960802593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.960802593
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.19226866
Short name T438
Test name
Test status
Simulation time 19736486542 ps
CPU time 24.88 seconds
Started Aug 19 04:37:34 PM PDT 24
Finished Aug 19 04:37:59 PM PDT 24
Peak memory 183592 kb
Host smart-a332646f-3132-4164-9d08-3954ad8e245c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19226866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.19226866
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.999705331
Short name T444
Test name
Test status
Simulation time 5701549154 ps
CPU time 49.6 seconds
Started Aug 19 04:37:33 PM PDT 24
Finished Aug 19 04:38:22 PM PDT 24
Peak memory 191748 kb
Host smart-152422ef-ab55-476a-888b-27174a5b512c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999705331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.999705331
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.739370629
Short name T194
Test name
Test status
Simulation time 971426820855 ps
CPU time 515.65 seconds
Started Aug 19 04:37:49 PM PDT 24
Finished Aug 19 04:46:25 PM PDT 24
Peak memory 183584 kb
Host smart-861571d2-e719-483e-9f69-d6651a427876
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739370629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.739370629
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.422367842
Short name T364
Test name
Test status
Simulation time 508938428853 ps
CPU time 202.59 seconds
Started Aug 19 04:37:48 PM PDT 24
Finished Aug 19 04:41:11 PM PDT 24
Peak memory 183568 kb
Host smart-6c546a6a-1646-4a76-89a4-609e4a657379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422367842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.422367842
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.317809868
Short name T6
Test name
Test status
Simulation time 262468158511 ps
CPU time 789.88 seconds
Started Aug 19 04:37:43 PM PDT 24
Finished Aug 19 04:50:53 PM PDT 24
Peak memory 191792 kb
Host smart-9937cdce-5dbe-43ee-9647-0bb55f5b08f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317809868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.317809868
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.50808945
Short name T5
Test name
Test status
Simulation time 12570565815 ps
CPU time 18.88 seconds
Started Aug 19 04:37:23 PM PDT 24
Finished Aug 19 04:37:42 PM PDT 24
Peak memory 183548 kb
Host smart-9d7c234f-1aef-4da1-be45-e6e7c99b2e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50808945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.50808945
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2225909675
Short name T443
Test name
Test status
Simulation time 829069617 ps
CPU time 0.75 seconds
Started Aug 19 04:37:34 PM PDT 24
Finished Aug 19 04:37:35 PM PDT 24
Peak memory 192328 kb
Host smart-c1eb4021-c32f-4850-b117-3ebe4905b294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225909675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2225909675
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3819956084
Short name T17
Test name
Test status
Simulation time 35628855 ps
CPU time 0.72 seconds
Started Aug 19 04:37:18 PM PDT 24
Finished Aug 19 04:37:18 PM PDT 24
Peak memory 213936 kb
Host smart-0a4e632d-6d92-4343-97ee-71fc4dfdf60f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819956084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3819956084
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3683306062
Short name T416
Test name
Test status
Simulation time 110824123447 ps
CPU time 176.93 seconds
Started Aug 19 04:37:15 PM PDT 24
Finished Aug 19 04:40:12 PM PDT 24
Peak memory 183536 kb
Host smart-6b581c50-72da-4118-a589-832ae0fb962f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683306062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3683306062
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1827101219
Short name T42
Test name
Test status
Simulation time 80497590257 ps
CPU time 42.42 seconds
Started Aug 19 04:37:32 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 183556 kb
Host smart-71811fc6-2d7e-425c-b049-0a310d6c3018
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827101219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1827101219
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3281714778
Short name T415
Test name
Test status
Simulation time 250958997228 ps
CPU time 180.56 seconds
Started Aug 19 04:37:48 PM PDT 24
Finished Aug 19 04:40:49 PM PDT 24
Peak memory 183552 kb
Host smart-717e4703-98fd-48ee-9d11-5b7ac81db5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281714778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3281714778
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3026819883
Short name T187
Test name
Test status
Simulation time 102649154452 ps
CPU time 81.78 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 04:39:13 PM PDT 24
Peak memory 183612 kb
Host smart-0ec01717-f487-4537-979c-6297a2ff938e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026819883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3026819883
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.889769770
Short name T179
Test name
Test status
Simulation time 124424705598 ps
CPU time 68.17 seconds
Started Aug 19 04:37:37 PM PDT 24
Finished Aug 19 04:38:45 PM PDT 24
Peak memory 191780 kb
Host smart-82b43151-bb43-46e7-85f0-c590daf360a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889769770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.889769770
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.544691455
Short name T333
Test name
Test status
Simulation time 4986036214654 ps
CPU time 1479.53 seconds
Started Aug 19 04:37:40 PM PDT 24
Finished Aug 19 05:02:20 PM PDT 24
Peak memory 183596 kb
Host smart-72ace10d-a6e3-449c-a5c6-d608a15e94d0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544691455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.544691455
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1944460512
Short name T399
Test name
Test status
Simulation time 5538128182 ps
CPU time 8.55 seconds
Started Aug 19 04:37:33 PM PDT 24
Finished Aug 19 04:37:42 PM PDT 24
Peak memory 183392 kb
Host smart-96b56109-fce2-40d9-8177-c9541077ba91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944460512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1944460512
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.749349743
Short name T126
Test name
Test status
Simulation time 121339753351 ps
CPU time 463.58 seconds
Started Aug 19 04:37:34 PM PDT 24
Finished Aug 19 04:45:18 PM PDT 24
Peak memory 191800 kb
Host smart-c1e914dd-077c-4812-900d-cf64fa42f8c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749349743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.749349743
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1920581910
Short name T256
Test name
Test status
Simulation time 75236329691 ps
CPU time 127.91 seconds
Started Aug 19 04:37:46 PM PDT 24
Finished Aug 19 04:39:54 PM PDT 24
Peak memory 191652 kb
Host smart-ed3ecdee-91d1-487f-8d50-c368962f335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920581910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1920581910
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1992608885
Short name T296
Test name
Test status
Simulation time 67502328073 ps
CPU time 120.28 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 04:39:52 PM PDT 24
Peak memory 191768 kb
Host smart-7cd153c9-1d2d-4a92-86cf-add2a4ed6ca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992608885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1992608885
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2248938797
Short name T140
Test name
Test status
Simulation time 144237589251 ps
CPU time 222.7 seconds
Started Aug 19 04:37:37 PM PDT 24
Finished Aug 19 04:41:20 PM PDT 24
Peak memory 183548 kb
Host smart-f6403ea8-ae7d-4141-8898-f2886c2a67ca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248938797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2248938797
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.4292467243
Short name T410
Test name
Test status
Simulation time 74526634515 ps
CPU time 50.25 seconds
Started Aug 19 04:37:45 PM PDT 24
Finished Aug 19 04:38:35 PM PDT 24
Peak memory 183616 kb
Host smart-97acec5d-6cb4-480b-8a08-d253addcd058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292467243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.4292467243
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3000017028
Short name T196
Test name
Test status
Simulation time 233811484327 ps
CPU time 340.66 seconds
Started Aug 19 04:37:22 PM PDT 24
Finished Aug 19 04:43:03 PM PDT 24
Peak memory 191800 kb
Host smart-94162af5-6cd1-4087-aefd-4ab1adf22085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000017028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3000017028
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.1624392371
Short name T11
Test name
Test status
Simulation time 1849858287 ps
CPU time 13.71 seconds
Started Aug 19 04:37:37 PM PDT 24
Finished Aug 19 04:37:50 PM PDT 24
Peak memory 198128 kb
Host smart-8e697ee6-535c-4f3d-ad60-8c6861442d40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624392371 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.1624392371
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2575802978
Short name T352
Test name
Test status
Simulation time 21935150291 ps
CPU time 16.6 seconds
Started Aug 19 04:37:38 PM PDT 24
Finished Aug 19 04:37:55 PM PDT 24
Peak memory 183564 kb
Host smart-cc862624-7a21-4cda-8413-56b639944a44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575802978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2575802978
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.937818788
Short name T375
Test name
Test status
Simulation time 262677311415 ps
CPU time 205.44 seconds
Started Aug 19 04:37:38 PM PDT 24
Finished Aug 19 04:41:04 PM PDT 24
Peak memory 183560 kb
Host smart-be14bce5-3808-44a3-a004-5be686919fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937818788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.937818788
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2170519677
Short name T101
Test name
Test status
Simulation time 21919808137 ps
CPU time 33.82 seconds
Started Aug 19 04:37:49 PM PDT 24
Finished Aug 19 04:38:23 PM PDT 24
Peak memory 191804 kb
Host smart-b04f0bcc-0916-45c1-8d72-d0f8a0bb2c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170519677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2170519677
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1559406437
Short name T189
Test name
Test status
Simulation time 208929527342 ps
CPU time 97.16 seconds
Started Aug 19 04:37:56 PM PDT 24
Finished Aug 19 04:39:33 PM PDT 24
Peak memory 183548 kb
Host smart-214d49a6-40ed-4a20-85cd-486d2c0a8c17
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559406437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1559406437
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.888641329
Short name T398
Test name
Test status
Simulation time 88443311628 ps
CPU time 68.35 seconds
Started Aug 19 04:37:25 PM PDT 24
Finished Aug 19 04:38:33 PM PDT 24
Peak memory 183616 kb
Host smart-91d1d3b9-860a-4470-88ac-c8b8cc38c3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888641329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.888641329
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1555012492
Short name T58
Test name
Test status
Simulation time 242147590 ps
CPU time 0.53 seconds
Started Aug 19 04:37:36 PM PDT 24
Finished Aug 19 04:37:37 PM PDT 24
Peak memory 182956 kb
Host smart-0b726bc8-4bf5-4db2-9585-2a96237da04e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555012492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1555012492
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1787802089
Short name T349
Test name
Test status
Simulation time 94644971249 ps
CPU time 84.6 seconds
Started Aug 19 04:37:44 PM PDT 24
Finished Aug 19 04:39:08 PM PDT 24
Peak memory 183584 kb
Host smart-d6de42ec-11cc-433b-8313-a84d48a7f8c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787802089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1787802089
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3791214635
Short name T381
Test name
Test status
Simulation time 526905923620 ps
CPU time 215.7 seconds
Started Aug 19 04:37:35 PM PDT 24
Finished Aug 19 04:41:10 PM PDT 24
Peak memory 183592 kb
Host smart-168b2203-4052-4086-9101-48baeac3d19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791214635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3791214635
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3056090599
Short name T247
Test name
Test status
Simulation time 710963940495 ps
CPU time 276.06 seconds
Started Aug 19 04:37:42 PM PDT 24
Finished Aug 19 04:42:19 PM PDT 24
Peak memory 195300 kb
Host smart-db42f7a9-e43c-4c54-be51-6756ff7de263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056090599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3056090599
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2201666995
Short name T313
Test name
Test status
Simulation time 13147115247 ps
CPU time 15.8 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 04:38:06 PM PDT 24
Peak memory 183556 kb
Host smart-41f48e05-d6b4-4b1b-b931-1d60a58d80b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201666995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2201666995
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.761688273
Short name T325
Test name
Test status
Simulation time 739237536129 ps
CPU time 378.99 seconds
Started Aug 19 04:37:49 PM PDT 24
Finished Aug 19 04:44:08 PM PDT 24
Peak memory 183624 kb
Host smart-99610748-23e9-48c0-a211-16c24062e0d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761688273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.761688273
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2901106403
Short name T363
Test name
Test status
Simulation time 127825070440 ps
CPU time 197.34 seconds
Started Aug 19 04:37:45 PM PDT 24
Finished Aug 19 04:41:02 PM PDT 24
Peak memory 183596 kb
Host smart-f2639f8b-b38f-4bf1-8273-72869f3100a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901106403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2901106403
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3580702467
Short name T282
Test name
Test status
Simulation time 66650257550 ps
CPU time 34.27 seconds
Started Aug 19 04:37:43 PM PDT 24
Finished Aug 19 04:38:17 PM PDT 24
Peak memory 183604 kb
Host smart-95498934-10b7-43e5-aca4-1d19e44055ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580702467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3580702467
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.3180569567
Short name T37
Test name
Test status
Simulation time 6533662669 ps
CPU time 38.68 seconds
Started Aug 19 04:37:35 PM PDT 24
Finished Aug 19 04:38:14 PM PDT 24
Peak memory 198268 kb
Host smart-7e34e229-89d3-45cb-8d6b-c47654f6fd64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180569567 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.3180569567
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2645827078
Short name T211
Test name
Test status
Simulation time 1065919512975 ps
CPU time 589.23 seconds
Started Aug 19 04:37:19 PM PDT 24
Finished Aug 19 04:47:08 PM PDT 24
Peak memory 183576 kb
Host smart-05dfaef6-ee07-4893-bd9d-5b03d6cfd0fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645827078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2645827078
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.977539089
Short name T395
Test name
Test status
Simulation time 52397408601 ps
CPU time 12.61 seconds
Started Aug 19 04:37:56 PM PDT 24
Finished Aug 19 04:38:08 PM PDT 24
Peak memory 183572 kb
Host smart-ed60204e-fc58-4aa4-9fd5-9b29734c42fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977539089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.977539089
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.278295046
Short name T440
Test name
Test status
Simulation time 196044792 ps
CPU time 0.73 seconds
Started Aug 19 04:37:48 PM PDT 24
Finished Aug 19 04:37:49 PM PDT 24
Peak memory 183212 kb
Host smart-83ebd03a-2545-463b-b6d4-406d3abfb48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278295046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.278295046
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1648762897
Short name T377
Test name
Test status
Simulation time 107770038012 ps
CPU time 164.3 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 04:40:35 PM PDT 24
Peak memory 183584 kb
Host smart-8bd9f93a-6ed7-49a5-8b6b-7ed71245d13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648762897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1648762897
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1039217398
Short name T152
Test name
Test status
Simulation time 193699699895 ps
CPU time 175.18 seconds
Started Aug 19 04:37:43 PM PDT 24
Finished Aug 19 04:40:38 PM PDT 24
Peak memory 191776 kb
Host smart-95c4aed0-da23-414e-93f4-a592c63571a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039217398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1039217398
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3803708774
Short name T274
Test name
Test status
Simulation time 128836868875 ps
CPU time 391.46 seconds
Started Aug 19 04:37:34 PM PDT 24
Finished Aug 19 04:44:05 PM PDT 24
Peak memory 191816 kb
Host smart-3876f42c-f997-4b1e-894a-b0d7fe5bf6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803708774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3803708774
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.785332210
Short name T423
Test name
Test status
Simulation time 1024369375030 ps
CPU time 1045.72 seconds
Started Aug 19 04:37:50 PM PDT 24
Finished Aug 19 04:55:16 PM PDT 24
Peak memory 191788 kb
Host smart-1e6dc0b1-ada6-433d-aa86-24d238c1dbb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785332210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
785332210
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3279573826
Short name T307
Test name
Test status
Simulation time 19556656554 ps
CPU time 10.42 seconds
Started Aug 19 04:37:58 PM PDT 24
Finished Aug 19 04:38:08 PM PDT 24
Peak memory 183560 kb
Host smart-0c87f705-8919-418f-81c7-032df16dd26e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279573826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3279573826
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2453075308
Short name T402
Test name
Test status
Simulation time 19472146120 ps
CPU time 31.75 seconds
Started Aug 19 04:37:46 PM PDT 24
Finished Aug 19 04:38:18 PM PDT 24
Peak memory 183572 kb
Host smart-c29fbc45-da12-46ba-bd41-d09ae7aee489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453075308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2453075308
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.251549922
Short name T24
Test name
Test status
Simulation time 197051794 ps
CPU time 1.12 seconds
Started Aug 19 04:37:49 PM PDT 24
Finished Aug 19 04:37:51 PM PDT 24
Peak memory 183504 kb
Host smart-1aa30806-7a55-4a8e-b4af-e2c4348feba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251549922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.251549922
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.137663544
Short name T98
Test name
Test status
Simulation time 480898803387 ps
CPU time 275.05 seconds
Started Aug 19 04:37:13 PM PDT 24
Finished Aug 19 04:41:48 PM PDT 24
Peak memory 183568 kb
Host smart-3fb4c81b-aaca-474b-9777-a857c8b23191
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137663544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.137663544
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3700929313
Short name T21
Test name
Test status
Simulation time 346911420834 ps
CPU time 146.14 seconds
Started Aug 19 04:37:32 PM PDT 24
Finished Aug 19 04:39:58 PM PDT 24
Peak memory 183580 kb
Host smart-8c866c3b-d507-4334-a7c4-ecc435231409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700929313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3700929313
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2301825407
Short name T171
Test name
Test status
Simulation time 56471356553 ps
CPU time 216.47 seconds
Started Aug 19 04:37:37 PM PDT 24
Finished Aug 19 04:41:13 PM PDT 24
Peak memory 192000 kb
Host smart-8ee0cbc8-e3d1-4fac-9ac8-981d15f0ee7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301825407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2301825407
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.135861256
Short name T207
Test name
Test status
Simulation time 63056718577 ps
CPU time 63.06 seconds
Started Aug 19 04:37:12 PM PDT 24
Finished Aug 19 04:38:16 PM PDT 24
Peak memory 183608 kb
Host smart-d3710e17-9b63-4d6d-8d37-5400fb2a0ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135861256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.135861256
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1737409108
Short name T14
Test name
Test status
Simulation time 64054400 ps
CPU time 0.81 seconds
Started Aug 19 04:37:21 PM PDT 24
Finished Aug 19 04:37:22 PM PDT 24
Peak memory 214624 kb
Host smart-a2245bca-84a0-401d-b71d-80a4d8fe2c15
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737409108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1737409108
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2310001156
Short name T361
Test name
Test status
Simulation time 229518104681 ps
CPU time 186.36 seconds
Started Aug 19 04:37:12 PM PDT 24
Finished Aug 19 04:40:19 PM PDT 24
Peak memory 183556 kb
Host smart-280c3fad-3533-4208-837d-c6d3798fbfc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310001156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2310001156
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1455353324
Short name T347
Test name
Test status
Simulation time 193292630143 ps
CPU time 261.45 seconds
Started Aug 19 04:37:42 PM PDT 24
Finished Aug 19 04:42:03 PM PDT 24
Peak memory 183524 kb
Host smart-4e8d9a7c-c144-4c7d-b51a-f023bd176c8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455353324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1455353324
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.4256336878
Short name T374
Test name
Test status
Simulation time 381313652096 ps
CPU time 138.67 seconds
Started Aug 19 04:37:45 PM PDT 24
Finished Aug 19 04:40:03 PM PDT 24
Peak memory 183536 kb
Host smart-cc1341b4-6188-4f36-821a-eac3fee7773e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256336878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.4256336878
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3453404406
Short name T272
Test name
Test status
Simulation time 89969279475 ps
CPU time 31.22 seconds
Started Aug 19 04:37:54 PM PDT 24
Finished Aug 19 04:38:25 PM PDT 24
Peak memory 183576 kb
Host smart-eb0a8525-99d5-46ea-bf84-21fd405daa9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453404406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3453404406
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3432778523
Short name T147
Test name
Test status
Simulation time 1725358434304 ps
CPU time 932.99 seconds
Started Aug 19 04:37:40 PM PDT 24
Finished Aug 19 04:53:14 PM PDT 24
Peak memory 183528 kb
Host smart-8cf3e4e7-9ee0-49cb-8fa0-6176a54d5290
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432778523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3432778523
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2016099867
Short name T366
Test name
Test status
Simulation time 600998686703 ps
CPU time 173.75 seconds
Started Aug 19 04:37:43 PM PDT 24
Finished Aug 19 04:40:37 PM PDT 24
Peak memory 183620 kb
Host smart-72987bc5-14cf-4c0e-9c29-4fbb95a3eab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016099867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2016099867
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.285847148
Short name T293
Test name
Test status
Simulation time 30766409927 ps
CPU time 49.42 seconds
Started Aug 19 04:37:44 PM PDT 24
Finished Aug 19 04:38:34 PM PDT 24
Peak memory 183616 kb
Host smart-ee0473ad-5d54-4081-b3c9-3b48c1ca1a9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285847148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.285847148
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3182144091
Short name T448
Test name
Test status
Simulation time 124561683613 ps
CPU time 45.99 seconds
Started Aug 19 04:37:52 PM PDT 24
Finished Aug 19 04:38:38 PM PDT 24
Peak memory 191772 kb
Host smart-5a2513b0-3b70-4d57-8140-5d98d33ba435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182144091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3182144091
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.635266267
Short name T253
Test name
Test status
Simulation time 213911815012 ps
CPU time 310.34 seconds
Started Aug 19 04:37:44 PM PDT 24
Finished Aug 19 04:42:54 PM PDT 24
Peak memory 195200 kb
Host smart-c71d29c1-80b2-4053-9f62-f718cb465b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635266267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
635266267
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.800302486
Short name T218
Test name
Test status
Simulation time 574101414564 ps
CPU time 253.63 seconds
Started Aug 19 04:37:53 PM PDT 24
Finished Aug 19 04:42:07 PM PDT 24
Peak memory 183600 kb
Host smart-2fbbf0eb-2e97-43c8-b2e9-a3203cfcca43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800302486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.800302486
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1613948646
Short name T427
Test name
Test status
Simulation time 198757454270 ps
CPU time 83.56 seconds
Started Aug 19 04:37:50 PM PDT 24
Finished Aug 19 04:39:14 PM PDT 24
Peak memory 183608 kb
Host smart-c300247b-4ffd-4f10-ac5d-add6d3f85aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613948646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1613948646
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2478924581
Short name T285
Test name
Test status
Simulation time 281497593413 ps
CPU time 366.12 seconds
Started Aug 19 04:37:52 PM PDT 24
Finished Aug 19 04:43:59 PM PDT 24
Peak memory 191808 kb
Host smart-64f7354e-df5b-4952-a260-2ad03888d83c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478924581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2478924581
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1542251599
Short name T370
Test name
Test status
Simulation time 1163106865 ps
CPU time 2.89 seconds
Started Aug 19 04:37:47 PM PDT 24
Finished Aug 19 04:37:50 PM PDT 24
Peak memory 191636 kb
Host smart-2d76a61b-fccb-4e78-9979-bd2dc4fda476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542251599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1542251599
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3093507553
Short name T417
Test name
Test status
Simulation time 134203092781 ps
CPU time 208.65 seconds
Started Aug 19 04:37:54 PM PDT 24
Finished Aug 19 04:41:28 PM PDT 24
Peak memory 183604 kb
Host smart-9b38ab78-9a6b-4f7f-abe5-3cc78f48f5e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093507553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3093507553
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.3292662107
Short name T12
Test name
Test status
Simulation time 4807301941 ps
CPU time 28.33 seconds
Started Aug 19 04:37:53 PM PDT 24
Finished Aug 19 04:38:21 PM PDT 24
Peak memory 198284 kb
Host smart-a22cf6e9-e811-43c2-af7f-7a419238a8ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292662107 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.3292662107
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3286163537
Short name T191
Test name
Test status
Simulation time 467871562959 ps
CPU time 829.45 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 04:51:41 PM PDT 24
Peak memory 183512 kb
Host smart-09d2342e-a083-40d7-97a2-d8ab145755d8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286163537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3286163537
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3961969295
Short name T430
Test name
Test status
Simulation time 45927400529 ps
CPU time 76.81 seconds
Started Aug 19 04:37:50 PM PDT 24
Finished Aug 19 04:39:07 PM PDT 24
Peak memory 183608 kb
Host smart-7d3e5663-a344-42ac-b4dd-c1a0f98dec4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961969295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3961969295
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2465221586
Short name T239
Test name
Test status
Simulation time 2025839054727 ps
CPU time 625.86 seconds
Started Aug 19 04:37:41 PM PDT 24
Finished Aug 19 04:48:07 PM PDT 24
Peak memory 191820 kb
Host smart-06181709-6fa9-4c4b-b6dc-8cc521db6e4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465221586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2465221586
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.211819249
Short name T405
Test name
Test status
Simulation time 348410713971 ps
CPU time 284.15 seconds
Started Aug 19 04:37:58 PM PDT 24
Finished Aug 19 04:42:42 PM PDT 24
Peak memory 191776 kb
Host smart-e0bb495f-7d25-4351-b2c9-260d0aec6743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211819249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.211819249
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2182230931
Short name T385
Test name
Test status
Simulation time 332055930226 ps
CPU time 468.89 seconds
Started Aug 19 04:37:55 PM PDT 24
Finished Aug 19 04:45:44 PM PDT 24
Peak memory 195248 kb
Host smart-9134af42-5c0f-4e7b-b848-ba14ab421c2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182230931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2182230931
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1217213949
Short name T22
Test name
Test status
Simulation time 230157559308 ps
CPU time 368.21 seconds
Started Aug 19 04:37:47 PM PDT 24
Finished Aug 19 04:43:55 PM PDT 24
Peak memory 183584 kb
Host smart-cc8497a2-18b4-4ff1-9a45-d78cc18e08f2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217213949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1217213949
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2536061467
Short name T368
Test name
Test status
Simulation time 716422613757 ps
CPU time 283.81 seconds
Started Aug 19 04:37:54 PM PDT 24
Finished Aug 19 04:42:38 PM PDT 24
Peak memory 183584 kb
Host smart-725ed585-0e02-4b57-b43a-8fb93501f520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536061467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2536061467
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.967836594
Short name T205
Test name
Test status
Simulation time 302031367082 ps
CPU time 1252.31 seconds
Started Aug 19 04:37:53 PM PDT 24
Finished Aug 19 04:58:46 PM PDT 24
Peak memory 191708 kb
Host smart-83eae792-2b01-492e-a31e-d6f9cc7c161b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967836594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.967836594
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2661163651
Short name T391
Test name
Test status
Simulation time 1405063265 ps
CPU time 12.62 seconds
Started Aug 19 04:37:44 PM PDT 24
Finished Aug 19 04:37:56 PM PDT 24
Peak memory 183468 kb
Host smart-428c894e-7e7b-42ab-b7d5-d67b32338abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661163651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2661163651
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.2782389991
Short name T35
Test name
Test status
Simulation time 1603734195 ps
CPU time 14.37 seconds
Started Aug 19 04:37:46 PM PDT 24
Finished Aug 19 04:38:00 PM PDT 24
Peak memory 198168 kb
Host smart-3afbc403-3b9a-4bc5-8d0f-6e04e6db59b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782389991 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.2782389991
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3684598961
Short name T439
Test name
Test status
Simulation time 30956002609 ps
CPU time 25.03 seconds
Started Aug 19 04:37:40 PM PDT 24
Finished Aug 19 04:38:05 PM PDT 24
Peak memory 183548 kb
Host smart-6bccb35c-6dec-413e-a1b5-8cca426a0baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684598961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3684598961
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.953140089
Short name T348
Test name
Test status
Simulation time 7747384515 ps
CPU time 7.4 seconds
Started Aug 19 04:37:31 PM PDT 24
Finished Aug 19 04:37:39 PM PDT 24
Peak memory 183588 kb
Host smart-ccecb80f-ec74-40dc-a0e7-63b79694dc72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953140089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.953140089
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3322397724
Short name T164
Test name
Test status
Simulation time 637330674589 ps
CPU time 796.47 seconds
Started Aug 19 04:37:46 PM PDT 24
Finished Aug 19 04:51:03 PM PDT 24
Peak memory 191764 kb
Host smart-2ba82659-8e34-4cea-be6e-f64298260014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322397724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3322397724
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.269088007
Short name T453
Test name
Test status
Simulation time 3057970549 ps
CPU time 21.17 seconds
Started Aug 19 04:37:44 PM PDT 24
Finished Aug 19 04:38:06 PM PDT 24
Peak memory 198324 kb
Host smart-ed927d81-da5a-4541-bcdc-824fc90d3ee3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269088007 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.269088007
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2453498443
Short name T318
Test name
Test status
Simulation time 417064149102 ps
CPU time 348.78 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 04:43:40 PM PDT 24
Peak memory 183552 kb
Host smart-d2635212-94f8-4e7a-834d-df247447c095
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453498443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2453498443
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1853006303
Short name T436
Test name
Test status
Simulation time 28532671680 ps
CPU time 45.7 seconds
Started Aug 19 04:37:47 PM PDT 24
Finished Aug 19 04:38:33 PM PDT 24
Peak memory 183592 kb
Host smart-ac68003b-79af-4b60-8328-de1f99c362fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853006303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1853006303
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1394237615
Short name T120
Test name
Test status
Simulation time 229525311152 ps
CPU time 379.46 seconds
Started Aug 19 04:37:36 PM PDT 24
Finished Aug 19 04:43:56 PM PDT 24
Peak memory 194688 kb
Host smart-000dea5f-52d1-46ed-a446-9aa994d3acbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394237615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1394237615
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.782773286
Short name T371
Test name
Test status
Simulation time 934092957 ps
CPU time 0.93 seconds
Started Aug 19 04:37:47 PM PDT 24
Finished Aug 19 04:37:48 PM PDT 24
Peak memory 183256 kb
Host smart-97fad045-41aa-439f-87aa-9193ae872722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782773286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.782773286
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2810948742
Short name T386
Test name
Test status
Simulation time 6999082283792 ps
CPU time 916.82 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 04:53:08 PM PDT 24
Peak memory 191760 kb
Host smart-dfce8f0e-961f-42de-a60e-203381f12e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810948742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2810948742
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.1191728311
Short name T33
Test name
Test status
Simulation time 12313971783 ps
CPU time 17.7 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 04:38:09 PM PDT 24
Peak memory 198276 kb
Host smart-baa3fc76-a839-4c90-a3e6-4d0ce860b122
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191728311 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.1191728311
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1528824117
Short name T138
Test name
Test status
Simulation time 1559216420132 ps
CPU time 905.62 seconds
Started Aug 19 04:37:46 PM PDT 24
Finished Aug 19 04:52:52 PM PDT 24
Peak memory 183576 kb
Host smart-b613b934-0644-4c8e-bf28-585b6efa54b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528824117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1528824117
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.951722651
Short name T421
Test name
Test status
Simulation time 523109439611 ps
CPU time 188.15 seconds
Started Aug 19 04:37:57 PM PDT 24
Finished Aug 19 04:41:05 PM PDT 24
Peak memory 183568 kb
Host smart-0f36dcb3-8fc1-4d89-840d-64535109e457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951722651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.951722651
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.345770687
Short name T224
Test name
Test status
Simulation time 156075095068 ps
CPU time 128.54 seconds
Started Aug 19 04:37:55 PM PDT 24
Finished Aug 19 04:40:04 PM PDT 24
Peak memory 183612 kb
Host smart-31f1468a-2fda-4166-96a5-1ae6626b2dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345770687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.345770687
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3324534778
Short name T269
Test name
Test status
Simulation time 391462227697 ps
CPU time 1025.45 seconds
Started Aug 19 04:37:52 PM PDT 24
Finished Aug 19 04:54:58 PM PDT 24
Peak memory 195356 kb
Host smart-57366b59-e102-4238-b568-12963f783ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324534778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3324534778
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.160281312
Short name T93
Test name
Test status
Simulation time 1847104495395 ps
CPU time 673.69 seconds
Started Aug 19 04:37:59 PM PDT 24
Finished Aug 19 04:49:13 PM PDT 24
Peak memory 183560 kb
Host smart-4621beb0-06d8-47a3-aca2-5350016bb62e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160281312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.160281312
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2106544385
Short name T389
Test name
Test status
Simulation time 101713569639 ps
CPU time 70.48 seconds
Started Aug 19 04:37:45 PM PDT 24
Finished Aug 19 04:38:56 PM PDT 24
Peak memory 183612 kb
Host smart-0fab38e7-b67d-4881-a25f-778b1494d498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106544385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2106544385
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1456694820
Short name T271
Test name
Test status
Simulation time 314905397863 ps
CPU time 219.29 seconds
Started Aug 19 04:37:54 PM PDT 24
Finished Aug 19 04:41:33 PM PDT 24
Peak memory 191800 kb
Host smart-a8fbc02f-3859-42f9-91d6-01c451d0aaf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456694820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1456694820
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.896101021
Short name T419
Test name
Test status
Simulation time 162960743678 ps
CPU time 75.55 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:39:18 PM PDT 24
Peak memory 183612 kb
Host smart-868eac79-cb43-4dab-89f3-dc593c4c1527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896101021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.896101021
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.928473478
Short name T413
Test name
Test status
Simulation time 31620846 ps
CPU time 0.59 seconds
Started Aug 19 04:37:53 PM PDT 24
Finished Aug 19 04:37:54 PM PDT 24
Peak memory 183284 kb
Host smart-613414a0-1aec-4d00-8c6c-3c62cd8ca3fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928473478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.
928473478
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3346861786
Short name T390
Test name
Test status
Simulation time 370034850128 ps
CPU time 188.03 seconds
Started Aug 19 04:37:46 PM PDT 24
Finished Aug 19 04:40:54 PM PDT 24
Peak memory 183552 kb
Host smart-24e0700c-e432-42a4-9cc5-4b834ee6fa44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346861786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3346861786
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1362496452
Short name T424
Test name
Test status
Simulation time 162773981138 ps
CPU time 69.18 seconds
Started Aug 19 04:37:47 PM PDT 24
Finished Aug 19 04:38:56 PM PDT 24
Peak memory 183564 kb
Host smart-4e1228b9-6f2c-4c8f-a030-e78f5c905777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362496452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1362496452
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.771435231
Short name T25
Test name
Test status
Simulation time 177385294768 ps
CPU time 99.82 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 04:39:31 PM PDT 24
Peak memory 191812 kb
Host smart-5fb46c43-72b5-4af8-aa6a-30a71e71eebb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771435231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.771435231
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.4291732186
Short name T204
Test name
Test status
Simulation time 231042480263 ps
CPU time 93.47 seconds
Started Aug 19 04:37:53 PM PDT 24
Finished Aug 19 04:39:27 PM PDT 24
Peak memory 195308 kb
Host smart-063d4184-8d55-4d70-b060-17d79ac2bebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291732186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.4291732186
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2357869535
Short name T437
Test name
Test status
Simulation time 1429235373484 ps
CPU time 607.21 seconds
Started Aug 19 04:37:52 PM PDT 24
Finished Aug 19 04:48:00 PM PDT 24
Peak memory 191780 kb
Host smart-3266a866-8978-4d4b-8e1d-c3777bf4f419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357869535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2357869535
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1239916397
Short name T108
Test name
Test status
Simulation time 222688309876 ps
CPU time 337.74 seconds
Started Aug 19 04:37:28 PM PDT 24
Finished Aug 19 04:43:06 PM PDT 24
Peak memory 183584 kb
Host smart-d92d2e4e-231a-4888-95e2-b8ef879c1c15
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239916397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1239916397
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.183153573
Short name T396
Test name
Test status
Simulation time 511600450570 ps
CPU time 204.24 seconds
Started Aug 19 04:37:13 PM PDT 24
Finished Aug 19 04:40:37 PM PDT 24
Peak memory 182996 kb
Host smart-159c8153-52fd-419c-8b12-c69831feb087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183153573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.183153573
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3128850174
Short name T442
Test name
Test status
Simulation time 517910494899 ps
CPU time 341.94 seconds
Started Aug 19 04:37:30 PM PDT 24
Finished Aug 19 04:43:12 PM PDT 24
Peak memory 195184 kb
Host smart-e526257e-3f2b-4d92-973f-4a81bc6f52f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128850174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3128850174
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.2048394245
Short name T203
Test name
Test status
Simulation time 372665246050 ps
CPU time 831.61 seconds
Started Aug 19 04:38:01 PM PDT 24
Finished Aug 19 04:51:52 PM PDT 24
Peak memory 191796 kb
Host smart-332e4cee-d4b9-475e-a59a-f394de628a2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048394245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2048394245
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.414764774
Short name T357
Test name
Test status
Simulation time 44151236203 ps
CPU time 145.15 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 04:40:17 PM PDT 24
Peak memory 183628 kb
Host smart-dd1e1df5-2f79-49cf-b1f0-5b59b054ccca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414764774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.414764774
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.4044374024
Short name T299
Test name
Test status
Simulation time 464373485269 ps
CPU time 414.08 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:44:56 PM PDT 24
Peak memory 192844 kb
Host smart-117b5797-5005-44df-9873-28cc50487844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044374024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.4044374024
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1899821652
Short name T174
Test name
Test status
Simulation time 286727918890 ps
CPU time 274.65 seconds
Started Aug 19 04:37:56 PM PDT 24
Finished Aug 19 04:42:30 PM PDT 24
Peak memory 191804 kb
Host smart-0129e84c-6ffa-4f8a-a8cf-4ecab313bf1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899821652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1899821652
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.827126766
Short name T180
Test name
Test status
Simulation time 520766368985 ps
CPU time 501.12 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 04:46:12 PM PDT 24
Peak memory 191808 kb
Host smart-5f55beac-2411-40f2-ac9d-e0ee08b9efa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827126766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.827126766
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.4200802594
Short name T452
Test name
Test status
Simulation time 178507068509 ps
CPU time 830.91 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:51:54 PM PDT 24
Peak memory 191744 kb
Host smart-44b510c6-224a-467d-a359-93d71a7a0c3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200802594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.4200802594
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1167363715
Short name T337
Test name
Test status
Simulation time 1702825602432 ps
CPU time 969.9 seconds
Started Aug 19 04:37:44 PM PDT 24
Finished Aug 19 04:53:54 PM PDT 24
Peak memory 183632 kb
Host smart-565289b3-a1de-4b58-97f9-3ca740efaa08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167363715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1167363715
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.139479397
Short name T380
Test name
Test status
Simulation time 105371207011 ps
CPU time 160.83 seconds
Started Aug 19 04:37:16 PM PDT 24
Finished Aug 19 04:39:57 PM PDT 24
Peak memory 183584 kb
Host smart-d81c0c56-4e1e-4bdc-87b3-d5a9cd649d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139479397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.139479397
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2354621435
Short name T345
Test name
Test status
Simulation time 79923437804 ps
CPU time 377.47 seconds
Started Aug 19 04:37:08 PM PDT 24
Finished Aug 19 04:43:25 PM PDT 24
Peak memory 191800 kb
Host smart-fffdf799-d2f7-470e-954b-7eba92f6ec5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354621435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2354621435
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.4223023045
Short name T432
Test name
Test status
Simulation time 18658013 ps
CPU time 0.54 seconds
Started Aug 19 04:37:22 PM PDT 24
Finished Aug 19 04:37:22 PM PDT 24
Peak memory 183288 kb
Host smart-bd706ceb-4012-45fb-84d7-e7dfdf3f1f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223023045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4223023045
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.853602977
Short name T213
Test name
Test status
Simulation time 2304029347 ps
CPU time 2.46 seconds
Started Aug 19 04:37:53 PM PDT 24
Finished Aug 19 04:37:56 PM PDT 24
Peak memory 183612 kb
Host smart-f7e37723-2ffc-4f84-a9a2-a661250b3dc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853602977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.853602977
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2233592250
Short name T322
Test name
Test status
Simulation time 119740990962 ps
CPU time 367.86 seconds
Started Aug 19 04:37:59 PM PDT 24
Finished Aug 19 04:44:07 PM PDT 24
Peak memory 183600 kb
Host smart-bbc130bd-2038-47dc-8790-582871732769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233592250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2233592250
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.4196160954
Short name T20
Test name
Test status
Simulation time 163139466354 ps
CPU time 296.69 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:42:59 PM PDT 24
Peak memory 191816 kb
Host smart-d30a312a-a5b3-4cbc-810b-2b74943372a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196160954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.4196160954
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.106283323
Short name T160
Test name
Test status
Simulation time 148719220751 ps
CPU time 79.52 seconds
Started Aug 19 04:38:06 PM PDT 24
Finished Aug 19 04:39:25 PM PDT 24
Peak memory 183580 kb
Host smart-3f2b3d44-3183-4c08-8666-9f75e7d5d5b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106283323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.106283323
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3986649124
Short name T288
Test name
Test status
Simulation time 40424437376 ps
CPU time 122.58 seconds
Started Aug 19 04:37:51 PM PDT 24
Finished Aug 19 04:39:54 PM PDT 24
Peak memory 191808 kb
Host smart-00ec45bb-d942-4a3f-bd14-4ff36a7956a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986649124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3986649124
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2169571256
Short name T136
Test name
Test status
Simulation time 75432485586 ps
CPU time 159.9 seconds
Started Aug 19 04:37:57 PM PDT 24
Finished Aug 19 04:40:38 PM PDT 24
Peak memory 191384 kb
Host smart-c2ba94f2-49f4-4e96-b757-3c59496b61ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169571256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2169571256
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.617799082
Short name T137
Test name
Test status
Simulation time 543311307290 ps
CPU time 385.3 seconds
Started Aug 19 04:37:57 PM PDT 24
Finished Aug 19 04:44:23 PM PDT 24
Peak memory 191820 kb
Host smart-4ac08b84-937f-48d7-814a-4d4721645034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617799082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.617799082
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.413510074
Short name T346
Test name
Test status
Simulation time 205488413153 ps
CPU time 521.39 seconds
Started Aug 19 04:38:25 PM PDT 24
Finished Aug 19 04:47:06 PM PDT 24
Peak memory 191828 kb
Host smart-f20312ea-94ee-4237-8a65-ff5d6b5daf22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413510074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.413510074
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1191784180
Short name T243
Test name
Test status
Simulation time 1473863319160 ps
CPU time 445.84 seconds
Started Aug 19 04:37:50 PM PDT 24
Finished Aug 19 04:45:16 PM PDT 24
Peak memory 191828 kb
Host smart-c1fe77d3-050d-48df-9d4b-9046f8ae38e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191784180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1191784180
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3713156214
Short name T287
Test name
Test status
Simulation time 437740531862 ps
CPU time 232.44 seconds
Started Aug 19 04:37:24 PM PDT 24
Finished Aug 19 04:41:16 PM PDT 24
Peak memory 183604 kb
Host smart-68ccbccd-b20a-4adf-809d-6390492056af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713156214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3713156214
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2844342170
Short name T369
Test name
Test status
Simulation time 161346292661 ps
CPU time 118.81 seconds
Started Aug 19 04:37:10 PM PDT 24
Finished Aug 19 04:39:09 PM PDT 24
Peak memory 183576 kb
Host smart-86cdad06-c950-4d4c-9209-62bbc5b1c17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844342170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2844342170
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.308779582
Short name T195
Test name
Test status
Simulation time 257604023857 ps
CPU time 746.88 seconds
Started Aug 19 04:37:10 PM PDT 24
Finished Aug 19 04:49:37 PM PDT 24
Peak memory 195600 kb
Host smart-0552e50a-7cbc-4e5f-8e82-643ecc0c430e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308779582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.308779582
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1598644521
Short name T291
Test name
Test status
Simulation time 73048547984 ps
CPU time 59.19 seconds
Started Aug 19 04:37:11 PM PDT 24
Finished Aug 19 04:38:11 PM PDT 24
Peak memory 183404 kb
Host smart-a528d446-c24a-4593-a5a5-49c6f98233ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598644521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1598644521
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/71.rv_timer_random.1581487365
Short name T354
Test name
Test status
Simulation time 65165048127 ps
CPU time 33.27 seconds
Started Aug 19 04:37:50 PM PDT 24
Finished Aug 19 04:38:23 PM PDT 24
Peak memory 183544 kb
Host smart-232bd3de-d91c-4f2b-9a1d-cf1e3c8ff8cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581487365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1581487365
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3836340487
Short name T227
Test name
Test status
Simulation time 44889353389 ps
CPU time 77.73 seconds
Started Aug 19 04:38:00 PM PDT 24
Finished Aug 19 04:39:18 PM PDT 24
Peak memory 183604 kb
Host smart-423eae48-fa6d-42c2-bc1c-0f9b15ab8a12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836340487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3836340487
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3929387426
Short name T228
Test name
Test status
Simulation time 104958545869 ps
CPU time 164.19 seconds
Started Aug 19 04:38:03 PM PDT 24
Finished Aug 19 04:40:47 PM PDT 24
Peak memory 191820 kb
Host smart-a272f17e-f07a-4646-b923-4932ff0967df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929387426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3929387426
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2288028719
Short name T172
Test name
Test status
Simulation time 263762276136 ps
CPU time 289.38 seconds
Started Aug 19 04:37:56 PM PDT 24
Finished Aug 19 04:42:45 PM PDT 24
Peak memory 191840 kb
Host smart-7a3aec0b-8423-40c2-9654-01c5e726e34f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288028719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2288028719
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2629065178
Short name T238
Test name
Test status
Simulation time 126357807471 ps
CPU time 270.34 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:42:32 PM PDT 24
Peak memory 191832 kb
Host smart-d7d58a1c-d70e-4b13-8fa4-ef0a4f625e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629065178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2629065178
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1535919379
Short name T155
Test name
Test status
Simulation time 56313227398 ps
CPU time 80.8 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:39:23 PM PDT 24
Peak memory 192788 kb
Host smart-cb6d6b59-d2c7-46ee-a2d5-7cb37422b9bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535919379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1535919379
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2045410505
Short name T268
Test name
Test status
Simulation time 204022773274 ps
CPU time 501.08 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:46:23 PM PDT 24
Peak memory 191792 kb
Host smart-eaafe9b7-4309-4d0a-b94c-f0c400e2e996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045410505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2045410505
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1444302579
Short name T382
Test name
Test status
Simulation time 318951941966 ps
CPU time 262.89 seconds
Started Aug 19 04:37:17 PM PDT 24
Finished Aug 19 04:41:40 PM PDT 24
Peak memory 183604 kb
Host smart-abf822f5-981d-447f-9259-649561ce1171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444302579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1444302579
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3506066007
Short name T188
Test name
Test status
Simulation time 545203789009 ps
CPU time 1244.42 seconds
Started Aug 19 04:37:13 PM PDT 24
Finished Aug 19 04:57:57 PM PDT 24
Peak memory 191792 kb
Host smart-6e67c2f2-8067-4bfc-8bd2-6af95580c286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506066007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3506066007
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1191799504
Short name T388
Test name
Test status
Simulation time 108939775 ps
CPU time 0.59 seconds
Started Aug 19 04:37:38 PM PDT 24
Finished Aug 19 04:37:38 PM PDT 24
Peak memory 183252 kb
Host smart-4ae65c4e-81c3-4ca3-92d4-4077ba3eaaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191799504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1191799504
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2256007400
Short name T165
Test name
Test status
Simulation time 2067254279926 ps
CPU time 1964.61 seconds
Started Aug 19 04:37:12 PM PDT 24
Finished Aug 19 05:09:57 PM PDT 24
Peak memory 197072 kb
Host smart-cd68f05d-e398-4f46-951b-8804c8d0c87d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256007400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2256007400
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.3340849736
Short name T222
Test name
Test status
Simulation time 169573080015 ps
CPU time 311.49 seconds
Started Aug 19 04:38:00 PM PDT 24
Finished Aug 19 04:43:12 PM PDT 24
Peak memory 191800 kb
Host smart-b7cfbe28-c07d-44f0-acc0-e323024209f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340849736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3340849736
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.288760730
Short name T128
Test name
Test status
Simulation time 361385197587 ps
CPU time 172.37 seconds
Started Aug 19 04:38:12 PM PDT 24
Finished Aug 19 04:41:05 PM PDT 24
Peak memory 191824 kb
Host smart-2ccc5d5d-acbc-4858-b0fb-14f6cf0024f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288760730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.288760730
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2888179260
Short name T418
Test name
Test status
Simulation time 70538837166 ps
CPU time 60.53 seconds
Started Aug 19 04:38:06 PM PDT 24
Finished Aug 19 04:39:12 PM PDT 24
Peak memory 183492 kb
Host smart-d4477394-3a42-46d3-85cd-34c20c0962bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888179260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2888179260
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3860623364
Short name T190
Test name
Test status
Simulation time 150277405099 ps
CPU time 660.39 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:49:02 PM PDT 24
Peak memory 191792 kb
Host smart-c919afc0-a0de-4d68-a648-09b9d6754cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860623364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3860623364
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3131012805
Short name T428
Test name
Test status
Simulation time 179924556012 ps
CPU time 1345.96 seconds
Started Aug 19 04:37:54 PM PDT 24
Finished Aug 19 05:00:20 PM PDT 24
Peak memory 191788 kb
Host smart-6c9d87ce-ac10-4b7a-b47c-e9daf302ed48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131012805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3131012805
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1557386270
Short name T91
Test name
Test status
Simulation time 18612459489 ps
CPU time 47.42 seconds
Started Aug 19 04:37:53 PM PDT 24
Finished Aug 19 04:38:41 PM PDT 24
Peak memory 183576 kb
Host smart-6f808dfc-ffb6-46e4-ad77-6289a30658ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557386270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1557386270
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2526498441
Short name T209
Test name
Test status
Simulation time 40971567680 ps
CPU time 81.99 seconds
Started Aug 19 04:38:00 PM PDT 24
Finished Aug 19 04:39:22 PM PDT 24
Peak memory 191776 kb
Host smart-de1e91f5-becb-48fa-91eb-5b9e0ec2f9e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526498441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2526498441
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2152277198
Short name T304
Test name
Test status
Simulation time 5821687991 ps
CPU time 9.92 seconds
Started Aug 19 04:37:18 PM PDT 24
Finished Aug 19 04:37:28 PM PDT 24
Peak memory 183544 kb
Host smart-6dfd6ddb-7baf-4625-a4aa-59a4c26ac481
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152277198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2152277198
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1071874413
Short name T397
Test name
Test status
Simulation time 729671942745 ps
CPU time 275.86 seconds
Started Aug 19 04:37:24 PM PDT 24
Finished Aug 19 04:41:59 PM PDT 24
Peak memory 183600 kb
Host smart-52f5da08-f70a-4eaa-806d-adb090aef639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071874413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1071874413
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.81673136
Short name T329
Test name
Test status
Simulation time 303162662956 ps
CPU time 130.34 seconds
Started Aug 19 04:37:13 PM PDT 24
Finished Aug 19 04:39:23 PM PDT 24
Peak memory 191768 kb
Host smart-3496b88e-46de-4f3b-b4f9-e0619acb3e6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81673136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.81673136
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3845048840
Short name T378
Test name
Test status
Simulation time 84930788 ps
CPU time 1.08 seconds
Started Aug 19 04:37:12 PM PDT 24
Finished Aug 19 04:37:13 PM PDT 24
Peak memory 183480 kb
Host smart-86293ecb-4558-4ddd-a598-ff9d6c26f602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845048840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3845048840
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1221125567
Short name T55
Test name
Test status
Simulation time 457637122651 ps
CPU time 327.66 seconds
Started Aug 19 04:37:12 PM PDT 24
Finished Aug 19 04:42:40 PM PDT 24
Peak memory 195544 kb
Host smart-500089df-3132-49e6-b344-72dea44f4bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221125567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1221125567
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.309662101
Short name T39
Test name
Test status
Simulation time 1532684207 ps
CPU time 17.45 seconds
Started Aug 19 04:37:25 PM PDT 24
Finished Aug 19 04:37:43 PM PDT 24
Peak memory 198136 kb
Host smart-2e445304-9f87-448b-8c4f-60314e7d5d32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309662101 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.309662101
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.1285233526
Short name T401
Test name
Test status
Simulation time 161977305087 ps
CPU time 90.72 seconds
Started Aug 19 04:37:57 PM PDT 24
Finished Aug 19 04:39:28 PM PDT 24
Peak memory 183628 kb
Host smart-f412a604-c05b-45b9-884a-e017935868b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285233526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1285233526
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.650829722
Short name T197
Test name
Test status
Simulation time 92946931872 ps
CPU time 301.15 seconds
Started Aug 19 04:38:05 PM PDT 24
Finished Aug 19 04:43:06 PM PDT 24
Peak memory 191788 kb
Host smart-3ec0da2b-bbbb-41b0-99d8-384ff0c56bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650829722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.650829722
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3247095177
Short name T183
Test name
Test status
Simulation time 321431085368 ps
CPU time 329.24 seconds
Started Aug 19 04:38:05 PM PDT 24
Finished Aug 19 04:43:34 PM PDT 24
Peak memory 191816 kb
Host smart-f2cbecf1-717f-49b5-a8bc-33303ddccfc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247095177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3247095177
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1034566029
Short name T297
Test name
Test status
Simulation time 31942915381 ps
CPU time 44.73 seconds
Started Aug 19 04:38:02 PM PDT 24
Finished Aug 19 04:38:47 PM PDT 24
Peak memory 183588 kb
Host smart-6a444004-0d71-49e5-b028-1103684f7d4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034566029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1034566029
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.4100040241
Short name T223
Test name
Test status
Simulation time 119237391085 ps
CPU time 423.96 seconds
Started Aug 19 04:37:53 PM PDT 24
Finished Aug 19 04:44:57 PM PDT 24
Peak memory 191820 kb
Host smart-a0f498c3-534e-45af-a525-6b690c8b9f16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100040241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.4100040241
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.189194548
Short name T127
Test name
Test status
Simulation time 996061430144 ps
CPU time 255.8 seconds
Started Aug 19 04:37:57 PM PDT 24
Finished Aug 19 04:42:13 PM PDT 24
Peak memory 191692 kb
Host smart-79b28b50-fb20-466e-8137-7af35afdad65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189194548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.189194548
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2641659730
Short name T245
Test name
Test status
Simulation time 370026529800 ps
CPU time 515.77 seconds
Started Aug 19 04:37:55 PM PDT 24
Finished Aug 19 04:46:31 PM PDT 24
Peak memory 195020 kb
Host smart-04f9d193-7c87-4a5a-9c9d-c02da487ba69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641659730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2641659730
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.120015428
Short name T105
Test name
Test status
Simulation time 193712652382 ps
CPU time 1220.12 seconds
Started Aug 19 04:38:07 PM PDT 24
Finished Aug 19 04:58:27 PM PDT 24
Peak memory 191760 kb
Host smart-122836c7-8bbf-49d9-9e50-6f58996b3b02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120015428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.120015428
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2247156886
Short name T153
Test name
Test status
Simulation time 106656130123 ps
CPU time 195.88 seconds
Started Aug 19 04:38:01 PM PDT 24
Finished Aug 19 04:41:17 PM PDT 24
Peak memory 191780 kb
Host smart-f8f97821-fdcb-4f6e-97cf-a518b671164c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247156886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2247156886
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3939508263
Short name T103
Test name
Test status
Simulation time 188948145590 ps
CPU time 1051.39 seconds
Started Aug 19 04:37:55 PM PDT 24
Finished Aug 19 04:55:26 PM PDT 24
Peak memory 191808 kb
Host smart-b8d84852-6ae3-439e-bec8-8a81bcd4351e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939508263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3939508263
Directory /workspace/99.rv_timer_random/latest
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