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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.36 99.04 100.00 100.00 100.00 99.43


Total test records in report: 580
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T505 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2282669987 Aug 23 02:38:09 AM UTC 24 Aug 23 02:38:11 AM UTC 24 36020224 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.2699934339 Aug 23 02:38:10 AM UTC 24 Aug 23 02:38:12 AM UTC 24 13909492 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.652162703 Aug 23 02:38:10 AM UTC 24 Aug 23 02:38:12 AM UTC 24 17127960 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2240309000 Aug 23 02:38:10 AM UTC 24 Aug 23 02:38:12 AM UTC 24 48970444 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.928842188 Aug 23 02:38:10 AM UTC 24 Aug 23 02:38:13 AM UTC 24 181923578 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.3467905939 Aug 23 02:38:11 AM UTC 24 Aug 23 02:38:13 AM UTC 24 37809961 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3415889144 Aug 23 02:38:13 AM UTC 24 Aug 23 02:38:14 AM UTC 24 40694188 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.3913407071 Aug 23 02:38:13 AM UTC 24 Aug 23 02:38:15 AM UTC 24 185358980 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1749762347 Aug 23 02:38:13 AM UTC 24 Aug 23 02:38:15 AM UTC 24 108206853 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.3753567959 Aug 23 02:38:14 AM UTC 24 Aug 23 02:38:16 AM UTC 24 11619765 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2138574231 Aug 23 02:38:14 AM UTC 24 Aug 23 02:38:17 AM UTC 24 735092662 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.2962533166 Aug 23 02:38:15 AM UTC 24 Aug 23 02:38:17 AM UTC 24 13684185 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2785273738 Aug 23 02:38:16 AM UTC 24 Aug 23 02:38:18 AM UTC 24 49163813 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.912128140 Aug 23 02:38:16 AM UTC 24 Aug 23 02:38:18 AM UTC 24 82947575 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.3181018903 Aug 23 02:38:18 AM UTC 24 Aug 23 02:38:20 AM UTC 24 18829887 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4124717523 Aug 23 02:38:18 AM UTC 24 Aug 23 02:38:20 AM UTC 24 72198382 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.539390938 Aug 23 02:38:18 AM UTC 24 Aug 23 02:38:21 AM UTC 24 36828074 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.411921532 Aug 23 02:38:19 AM UTC 24 Aug 23 02:38:21 AM UTC 24 90598374 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.550586032 Aug 23 02:38:19 AM UTC 24 Aug 23 02:38:21 AM UTC 24 31793294 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1047568396 Aug 23 02:38:20 AM UTC 24 Aug 23 02:38:23 AM UTC 24 134526981 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.303802264 Aug 23 02:38:20 AM UTC 24 Aug 23 02:38:23 AM UTC 24 82675072 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.1162391943 Aug 23 02:38:22 AM UTC 24 Aug 23 02:38:23 AM UTC 24 51381419 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.367857741 Aug 23 02:38:22 AM UTC 24 Aug 23 02:38:23 AM UTC 24 30053676 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.513473564 Aug 23 02:38:22 AM UTC 24 Aug 23 02:38:24 AM UTC 24 20212657 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3241323158 Aug 23 02:38:22 AM UTC 24 Aug 23 02:38:24 AM UTC 24 71575089 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.2591422201 Aug 23 02:38:24 AM UTC 24 Aug 23 02:38:26 AM UTC 24 61673169 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.808493234 Aug 23 02:38:24 AM UTC 24 Aug 23 02:38:26 AM UTC 24 223449753 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.332148033 Aug 23 02:38:24 AM UTC 24 Aug 23 02:38:26 AM UTC 24 22594152 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2606914743 Aug 23 02:38:24 AM UTC 24 Aug 23 02:38:27 AM UTC 24 36409860 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2153000415 Aug 23 02:38:26 AM UTC 24 Aug 23 02:38:27 AM UTC 24 51403711 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.4228663136 Aug 23 02:38:24 AM UTC 24 Aug 23 02:38:29 AM UTC 24 191369172 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.525819311 Aug 23 02:38:27 AM UTC 24 Aug 23 02:38:29 AM UTC 24 412690171 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3209837789 Aug 23 02:38:27 AM UTC 24 Aug 23 02:38:30 AM UTC 24 99092062 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.205573265 Aug 23 02:38:28 AM UTC 24 Aug 23 02:38:30 AM UTC 24 12086525 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.2048613432 Aug 23 02:38:28 AM UTC 24 Aug 23 02:38:30 AM UTC 24 33189537 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.3026483995 Aug 23 02:38:27 AM UTC 24 Aug 23 02:38:30 AM UTC 24 177155029 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1190259844 Aug 23 02:38:29 AM UTC 24 Aug 23 02:38:31 AM UTC 24 96609088 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.3092834903 Aug 23 02:38:31 AM UTC 24 Aug 23 02:38:33 AM UTC 24 52705481 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2766775000 Aug 23 02:38:31 AM UTC 24 Aug 23 02:38:33 AM UTC 24 109337345 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2394669709 Aug 23 02:38:31 AM UTC 24 Aug 23 02:38:33 AM UTC 24 126026818 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.1513648571 Aug 23 02:38:31 AM UTC 24 Aug 23 02:38:33 AM UTC 24 50427402 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3915452766 Aug 23 02:38:32 AM UTC 24 Aug 23 02:38:34 AM UTC 24 23420408 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.3950051891 Aug 23 02:38:32 AM UTC 24 Aug 23 02:38:34 AM UTC 24 23544135 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.827261783 Aug 23 02:38:34 AM UTC 24 Aug 23 02:38:36 AM UTC 24 153099380 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3671288409 Aug 23 02:38:34 AM UTC 24 Aug 23 02:38:36 AM UTC 24 105698025 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.4051743988 Aug 23 02:38:34 AM UTC 24 Aug 23 02:38:36 AM UTC 24 48989019 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.1232744438 Aug 23 02:38:35 AM UTC 24 Aug 23 02:38:37 AM UTC 24 50163053 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.3924997456 Aug 23 02:38:35 AM UTC 24 Aug 23 02:38:37 AM UTC 24 140827001 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.605098743 Aug 23 02:38:35 AM UTC 24 Aug 23 02:38:37 AM UTC 24 17475367 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.1403885083 Aug 23 02:38:47 AM UTC 24 Aug 23 02:38:49 AM UTC 24 50764757 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.779139014 Aug 23 02:38:51 AM UTC 24 Aug 23 02:38:52 AM UTC 24 16515569 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.1939795767 Aug 23 02:38:38 AM UTC 24 Aug 23 02:38:40 AM UTC 24 12304898 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.1778950079 Aug 23 02:38:38 AM UTC 24 Aug 23 02:38:40 AM UTC 24 12295670 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1811930976 Aug 23 02:38:38 AM UTC 24 Aug 23 02:38:40 AM UTC 24 21208231 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1562339771 Aug 23 02:38:38 AM UTC 24 Aug 23 02:38:40 AM UTC 24 26595467 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.2159393334 Aug 23 02:38:38 AM UTC 24 Aug 23 02:38:40 AM UTC 24 41421641 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.105086209 Aug 23 02:38:38 AM UTC 24 Aug 23 02:38:40 AM UTC 24 69207278 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.1972750011 Aug 23 02:38:41 AM UTC 24 Aug 23 02:38:43 AM UTC 24 15247202 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1696913471 Aug 23 02:38:41 AM UTC 24 Aug 23 02:38:43 AM UTC 24 41443747 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.342221780 Aug 23 02:38:41 AM UTC 24 Aug 23 02:38:43 AM UTC 24 69746445 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.134946310 Aug 23 02:38:41 AM UTC 24 Aug 23 02:38:43 AM UTC 24 58452856 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.280201290 Aug 23 02:38:41 AM UTC 24 Aug 23 02:38:43 AM UTC 24 15199759 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.786041616 Aug 23 02:38:42 AM UTC 24 Aug 23 02:38:44 AM UTC 24 10499657 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.37990835 Aug 23 02:38:44 AM UTC 24 Aug 23 02:38:46 AM UTC 24 43148700 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.1738749646 Aug 23 02:38:44 AM UTC 24 Aug 23 02:38:46 AM UTC 24 39848051 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.3301845438 Aug 23 02:38:44 AM UTC 24 Aug 23 02:38:46 AM UTC 24 11778883 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.3686944380 Aug 23 02:38:44 AM UTC 24 Aug 23 02:38:46 AM UTC 24 19137075 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.2422803484 Aug 23 02:38:44 AM UTC 24 Aug 23 02:38:46 AM UTC 24 51879235 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.2777478276 Aug 23 02:38:45 AM UTC 24 Aug 23 02:38:47 AM UTC 24 14112534 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.4060892852 Aug 23 02:38:49 AM UTC 24 Aug 23 02:38:50 AM UTC 24 49593480 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.815474152 Aug 23 02:38:47 AM UTC 24 Aug 23 02:38:49 AM UTC 24 31343322 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.3985818957 Aug 23 02:38:47 AM UTC 24 Aug 23 02:38:49 AM UTC 24 28578490 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.1865083010 Aug 23 02:38:47 AM UTC 24 Aug 23 02:38:49 AM UTC 24 20286038 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.3934189247 Aug 23 02:38:47 AM UTC 24 Aug 23 02:38:49 AM UTC 24 31846353 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1262467326 Aug 23 02:38:51 AM UTC 24 Aug 23 02:38:52 AM UTC 24 19412591 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.1812766476 Aug 23 02:38:51 AM UTC 24 Aug 23 02:38:52 AM UTC 24 33210660 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.2481763510 Aug 23 02:38:51 AM UTC 24 Aug 23 02:38:53 AM UTC 24 28183576 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.3625281473 Aug 23 02:38:51 AM UTC 24 Aug 23 02:38:53 AM UTC 24 16732447 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.2852262210 Aug 23 02:38:52 AM UTC 24 Aug 23 02:38:54 AM UTC 24 14117256 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.117699506 Aug 23 02:38:54 AM UTC 24 Aug 23 02:38:56 AM UTC 24 43258533 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all_with_rand_reset.3240794833
Short name T1
Test name
Test status
Simulation time 1055171588 ps
CPU time 7.92 seconds
Started Aug 23 01:23:16 AM UTC 24
Finished Aug 23 01:23:25 AM UTC 24
Peak memory 203892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3240794833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.rv_timer_stress_all_with_rand_reset.3240794833
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.2091759294
Short name T15
Test name
Test status
Simulation time 193737463147 ps
CPU time 90.37 seconds
Started Aug 23 01:23:28 AM UTC 24
Finished Aug 23 01:25:00 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091759294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2091759294
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.2559499315
Short name T91
Test name
Test status
Simulation time 2191407544720 ps
CPU time 1528.59 seconds
Started Aug 23 01:24:15 AM UTC 24
Finished Aug 23 01:49:59 AM UTC 24
Peak memory 202448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559499315 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.2559499315
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3803020915
Short name T18
Test name
Test status
Simulation time 250880846 ps
CPU time 0.94 seconds
Started Aug 23 02:37:02 AM UTC 24
Finished Aug 23 02:37:04 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803020915 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.3803020915
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.1084148056
Short name T40
Test name
Test status
Simulation time 577134806067 ps
CPU time 1120.18 seconds
Started Aug 23 01:31:43 AM UTC 24
Finished Aug 23 01:50:36 AM UTC 24
Peak memory 202344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084148056 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.1084148056
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/15.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.3324522397
Short name T170
Test name
Test status
Simulation time 2816818346124 ps
CPU time 2066 seconds
Started Aug 23 01:48:26 AM UTC 24
Finished Aug 23 02:23:13 AM UTC 24
Peak memory 202452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324522397 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.3324522397
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/35.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.1944364146
Short name T9
Test name
Test status
Simulation time 733010951441 ps
CPU time 253.22 seconds
Started Aug 23 01:30:17 AM UTC 24
Finished Aug 23 01:34:34 AM UTC 24
Peak memory 199844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944364146 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.1944364146
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.2507033523
Short name T103
Test name
Test status
Simulation time 581017425234 ps
CPU time 1374.82 seconds
Started Aug 23 01:29:57 AM UTC 24
Finished Aug 23 01:53:06 AM UTC 24
Peak memory 202580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507033523 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.2507033523
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/12.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.1487263447
Short name T105
Test name
Test status
Simulation time 749664797022 ps
CPU time 1247.29 seconds
Started Aug 23 01:31:25 AM UTC 24
Finished Aug 23 01:52:24 AM UTC 24
Peak memory 202404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487263447 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.1487263447
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/14.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.494422332
Short name T173
Test name
Test status
Simulation time 5642683333908 ps
CPU time 1953.83 seconds
Started Aug 23 01:29:32 AM UTC 24
Finished Aug 23 02:02:25 AM UTC 24
Peak memory 202520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494422332 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.494422332
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/11.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.4155846324
Short name T83
Test name
Test status
Simulation time 390161740989 ps
CPU time 491.12 seconds
Started Aug 23 01:25:36 AM UTC 24
Finished Aug 23 01:33:52 AM UTC 24
Peak memory 199844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155846324 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.4155846324
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/7.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.1560552025
Short name T45
Test name
Test status
Simulation time 24820518 ps
CPU time 0.51 seconds
Started Aug 23 02:37:26 AM UTC 24
Finished Aug 23 02:37:27 AM UTC 24
Peak memory 198908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560552025 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1560552025
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.513891678
Short name T39
Test name
Test status
Simulation time 515222187375 ps
CPU time 1008.04 seconds
Started Aug 23 01:28:08 AM UTC 24
Finished Aug 23 01:45:07 AM UTC 24
Peak memory 202348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513891678 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.513891678
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/10.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.2822183520
Short name T3
Test name
Test status
Simulation time 229828568 ps
CPU time 0.73 seconds
Started Aug 23 01:23:24 AM UTC 24
Finished Aug 23 01:23:26 AM UTC 24
Peak memory 230928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822183520 -assert nopostproc +UVM_TESTNAME=rv
_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2822183520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.2611714331
Short name T147
Test name
Test status
Simulation time 447589779600 ps
CPU time 1090.89 seconds
Started Aug 23 01:56:20 AM UTC 24
Finished Aug 23 02:14:42 AM UTC 24
Peak memory 202404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611714331 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.2611714331
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/44.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.1204201534
Short name T38
Test name
Test status
Simulation time 313505423464 ps
CPU time 863.79 seconds
Started Aug 23 01:23:23 AM UTC 24
Finished Aug 23 01:37:56 AM UTC 24
Peak memory 202488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204201534 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.1204201534
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.452577668
Short name T172
Test name
Test status
Simulation time 362141151313 ps
CPU time 1743.19 seconds
Started Aug 23 01:47:31 AM UTC 24
Finished Aug 23 02:16:52 AM UTC 24
Peak memory 202348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452577668 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.452577668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/34.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.1363589032
Short name T148
Test name
Test status
Simulation time 1156420733070 ps
CPU time 1841.17 seconds
Started Aug 23 01:59:34 AM UTC 24
Finished Aug 23 02:30:34 AM UTC 24
Peak memory 200968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363589032 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.1363589032
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/47.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.3629593855
Short name T116
Test name
Test status
Simulation time 2419682106857 ps
CPU time 1287.34 seconds
Started Aug 23 01:26:46 AM UTC 24
Finished Aug 23 01:48:27 AM UTC 24
Peak memory 202348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629593855 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.3629593855
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/9.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.956094818
Short name T85
Test name
Test status
Simulation time 62926061836 ps
CPU time 93.82 seconds
Started Aug 23 01:36:49 AM UTC 24
Finished Aug 23 01:38:25 AM UTC 24
Peak memory 199724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956094818 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.956094818
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.3216303496
Short name T346
Test name
Test status
Simulation time 414469492741 ps
CPU time 1888.81 seconds
Started Aug 23 02:26:36 AM UTC 24
Finished Aug 23 02:58:25 AM UTC 24
Peak memory 202480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216303496 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3216303496
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/154.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.3033688368
Short name T188
Test name
Test status
Simulation time 1485912177908 ps
CPU time 751.98 seconds
Started Aug 23 01:42:29 AM UTC 24
Finished Aug 23 01:55:09 AM UTC 24
Peak memory 202440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033688368 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.3033688368
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/29.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.1413702256
Short name T248
Test name
Test status
Simulation time 2062707581814 ps
CPU time 1277.71 seconds
Started Aug 23 01:59:10 AM UTC 24
Finished Aug 23 02:20:40 AM UTC 24
Peak memory 202404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413702256 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.1413702256
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/46.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.3797910153
Short name T176
Test name
Test status
Simulation time 463159267950 ps
CPU time 1323.63 seconds
Started Aug 23 01:43:18 AM UTC 24
Finished Aug 23 02:05:35 AM UTC 24
Peak memory 202420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797910153 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.3797910153
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/30.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.4199335766
Short name T269
Test name
Test status
Simulation time 194958356702 ps
CPU time 1684.25 seconds
Started Aug 23 02:01:25 AM UTC 24
Finished Aug 23 02:29:46 AM UTC 24
Peak memory 202484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199335766 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.4199335766
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/48.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.2980369958
Short name T96
Test name
Test status
Simulation time 272775650744 ps
CPU time 379.1 seconds
Started Aug 23 01:26:10 AM UTC 24
Finished Aug 23 01:32:33 AM UTC 24
Peak memory 199612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980369958 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2980369958
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/9.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.1008181193
Short name T92
Test name
Test status
Simulation time 670957553407 ps
CPU time 613.59 seconds
Started Aug 23 01:29:41 AM UTC 24
Finished Aug 23 01:40:01 AM UTC 24
Peak memory 202548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008181193 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1008181193
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/12.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.1506632747
Short name T139
Test name
Test status
Simulation time 320922698884 ps
CPU time 222.51 seconds
Started Aug 23 01:41:41 AM UTC 24
Finished Aug 23 01:45:26 AM UTC 24
Peak memory 199668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506632747 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.1506632747
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/28.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.2984596168
Short name T273
Test name
Test status
Simulation time 1687832042571 ps
CPU time 2138.7 seconds
Started Aug 23 02:04:48 AM UTC 24
Finished Aug 23 02:40:48 AM UTC 24
Peak memory 202484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984596168 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2984596168
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/65.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.2222269223
Short name T159
Test name
Test status
Simulation time 530104249129 ps
CPU time 785.73 seconds
Started Aug 23 02:24:11 AM UTC 24
Finished Aug 23 02:37:25 AM UTC 24
Peak memory 202352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2222269223 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2222269223
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/145.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.1132599491
Short name T223
Test name
Test status
Simulation time 806613825850 ps
CPU time 1067.51 seconds
Started Aug 23 01:45:27 AM UTC 24
Finished Aug 23 02:03:25 AM UTC 24
Peak memory 202480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132599491 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.1132599491
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/32.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.3149663297
Short name T196
Test name
Test status
Simulation time 184771506026 ps
CPU time 257.98 seconds
Started Aug 23 02:07:03 AM UTC 24
Finished Aug 23 02:11:24 AM UTC 24
Peak memory 199668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149663297 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3149663297
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/79.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.3934473693
Short name T243
Test name
Test status
Simulation time 169294135026 ps
CPU time 89.91 seconds
Started Aug 23 02:16:53 AM UTC 24
Finished Aug 23 02:18:25 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934473693 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3934473693
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/113.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.2293869691
Short name T155
Test name
Test status
Simulation time 453327620999 ps
CPU time 1675.98 seconds
Started Aug 23 02:16:56 AM UTC 24
Finished Aug 23 02:45:09 AM UTC 24
Peak memory 202520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293869691 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2293869691
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/115.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.344997912
Short name T277
Test name
Test status
Simulation time 144538594648 ps
CPU time 248.32 seconds
Started Aug 23 02:19:40 AM UTC 24
Finished Aug 23 02:23:51 AM UTC 24
Peak memory 199668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344997912 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.344997912
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/128.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.3725921577
Short name T263
Test name
Test status
Simulation time 120645040004 ps
CPU time 1561.49 seconds
Started Aug 23 02:25:07 AM UTC 24
Finished Aug 23 02:51:25 AM UTC 24
Peak memory 202408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725921577 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3725921577
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/150.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.843781691
Short name T41
Test name
Test status
Simulation time 1616480924869 ps
CPU time 801.82 seconds
Started Aug 23 01:39:25 AM UTC 24
Finished Aug 23 01:52:56 AM UTC 24
Peak memory 202444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843781691 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.843781691
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/24.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.3628410866
Short name T294
Test name
Test status
Simulation time 698980852515 ps
CPU time 723.15 seconds
Started Aug 23 02:10:01 AM UTC 24
Finished Aug 23 02:22:12 AM UTC 24
Peak memory 202456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628410866 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3628410866
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/90.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.3752249014
Short name T343
Test name
Test status
Simulation time 235700732078 ps
CPU time 193.02 seconds
Started Aug 23 02:13:50 AM UTC 24
Finished Aug 23 02:17:06 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752249014 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3752249014
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/102.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.2057196358
Short name T202
Test name
Test status
Simulation time 239027725966 ps
CPU time 114.05 seconds
Started Aug 23 02:22:14 AM UTC 24
Finished Aug 23 02:24:11 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057196358 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2057196358
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/138.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.117359957
Short name T356
Test name
Test status
Simulation time 162289071879 ps
CPU time 667.72 seconds
Started Aug 23 02:27:04 AM UTC 24
Finished Aug 23 02:38:19 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117359957 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.117359957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/157.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.3052827568
Short name T336
Test name
Test status
Simulation time 123480436940 ps
CPU time 416.59 seconds
Started Aug 23 02:29:12 AM UTC 24
Finished Aug 23 02:36:14 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052827568 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3052827568
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/165.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.3014734774
Short name T345
Test name
Test status
Simulation time 770665238480 ps
CPU time 434.81 seconds
Started Aug 23 02:36:51 AM UTC 24
Finished Aug 23 02:44:11 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014734774 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3014734774
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/198.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.2609365347
Short name T157
Test name
Test status
Simulation time 339560299330 ps
CPU time 675.87 seconds
Started Aug 23 01:46:10 AM UTC 24
Finished Aug 23 01:57:34 AM UTC 24
Peak memory 202448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609365347 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2609365347
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/34.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.1151834027
Short name T199
Test name
Test status
Simulation time 137114804174 ps
CPU time 615.63 seconds
Started Aug 23 02:02:06 AM UTC 24
Finished Aug 23 02:12:29 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151834027 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1151834027
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/52.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.3687274617
Short name T276
Test name
Test status
Simulation time 308395044662 ps
CPU time 2185.27 seconds
Started Aug 23 01:24:38 AM UTC 24
Finished Aug 23 02:01:25 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687274617 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3687274617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/6.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.4250491925
Short name T275
Test name
Test status
Simulation time 124835084346 ps
CPU time 59.69 seconds
Started Aug 23 02:12:58 AM UTC 24
Finished Aug 23 02:13:59 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250491925 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.4250491925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/100.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.381269565
Short name T154
Test name
Test status
Simulation time 340710456304 ps
CPU time 195.55 seconds
Started Aug 23 02:14:42 AM UTC 24
Finished Aug 23 02:18:01 AM UTC 24
Peak memory 199676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381269565 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.381269565
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/107.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.3416116513
Short name T279
Test name
Test status
Simulation time 553633758192 ps
CPU time 699.99 seconds
Started Aug 23 02:17:17 AM UTC 24
Finished Aug 23 02:29:05 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416116513 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3416116513
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/117.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.3516807886
Short name T108
Test name
Test status
Simulation time 37646606677 ps
CPU time 20.29 seconds
Started Aug 23 01:31:16 AM UTC 24
Finished Aug 23 01:31:37 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516807886 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.3516807886
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.3996081442
Short name T193
Test name
Test status
Simulation time 622730542658 ps
CPU time 418.17 seconds
Started Aug 23 02:30:24 AM UTC 24
Finished Aug 23 02:37:27 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996081442 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3996081442
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/177.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.211585262
Short name T123
Test name
Test status
Simulation time 13800882019 ps
CPU time 18.64 seconds
Started Aug 23 01:38:19 AM UTC 24
Finished Aug 23 01:38:38 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211585262 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.211585262
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.1447936051
Short name T226
Test name
Test status
Simulation time 260908397953 ps
CPU time 353.88 seconds
Started Aug 23 01:43:59 AM UTC 24
Finished Aug 23 01:49:57 AM UTC 24
Peak memory 199724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447936051 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.1447936051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.3892713049
Short name T342
Test name
Test status
Simulation time 1263198453198 ps
CPU time 1484.61 seconds
Started Aug 23 01:49:13 AM UTC 24
Finished Aug 23 02:14:12 AM UTC 24
Peak memory 202484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892713049 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.3892713049
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/36.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.531310810
Short name T252
Test name
Test status
Simulation time 118333597649 ps
CPU time 191.89 seconds
Started Aug 23 02:01:26 AM UTC 24
Finished Aug 23 02:04:41 AM UTC 24
Peak memory 199840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531310810 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.531310810
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/49.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.2544026783
Short name T341
Test name
Test status
Simulation time 113806213393 ps
CPU time 366.37 seconds
Started Aug 23 02:12:40 AM UTC 24
Finished Aug 23 02:18:50 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544026783 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2544026783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/98.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.3050374496
Short name T23
Test name
Test status
Simulation time 25016675 ps
CPU time 0.45 seconds
Started Aug 23 02:37:09 AM UTC 24
Finished Aug 23 02:37:11 AM UTC 24
Peak memory 199044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050374496 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3050374496
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.979943742
Short name T51
Test name
Test status
Simulation time 17526415 ps
CPU time 0.71 seconds
Started Aug 23 02:37:41 AM UTC 24
Finished Aug 23 02:37:43 AM UTC 24
Peak memory 198908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979943742 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.979943742
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.3634501913
Short name T224
Test name
Test status
Simulation time 151596796990 ps
CPU time 260.79 seconds
Started Aug 23 02:17:07 AM UTC 24
Finished Aug 23 02:21:31 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634501913 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3634501913
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/116.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.451895269
Short name T328
Test name
Test status
Simulation time 252049279162 ps
CPU time 460.95 seconds
Started Aug 23 02:22:12 AM UTC 24
Finished Aug 23 02:29:59 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451895269 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.451895269
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/137.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.448665168
Short name T367
Test name
Test status
Simulation time 232629327262 ps
CPU time 2031.68 seconds
Started Aug 23 02:28:22 AM UTC 24
Finished Aug 23 03:02:36 AM UTC 24
Peak memory 202352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448665168 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.448665168
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/162.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.1423331436
Short name T206
Test name
Test status
Simulation time 256941342438 ps
CPU time 785.8 seconds
Started Aug 23 02:30:20 AM UTC 24
Finished Aug 23 02:43:34 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423331436 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1423331436
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/176.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.723212622
Short name T265
Test name
Test status
Simulation time 51334749647 ps
CPU time 1111.23 seconds
Started Aug 23 02:30:34 AM UTC 24
Finished Aug 23 02:49:18 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723212622 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.723212622
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/179.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.3696237193
Short name T145
Test name
Test status
Simulation time 1141422632243 ps
CPU time 556.04 seconds
Started Aug 23 02:32:19 AM UTC 24
Finished Aug 23 02:41:42 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696237193 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3696237193
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/182.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.1413297177
Short name T160
Test name
Test status
Simulation time 5196566312362 ps
CPU time 926.17 seconds
Started Aug 23 01:47:22 AM UTC 24
Finished Aug 23 02:02:58 AM UTC 24
Peak memory 202328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413297177 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.1413297177
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.3351969213
Short name T180
Test name
Test status
Simulation time 95790629585 ps
CPU time 162.07 seconds
Started Aug 23 01:47:39 AM UTC 24
Finished Aug 23 01:50:24 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351969213 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3351969213
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/35.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.3084373121
Short name T72
Test name
Test status
Simulation time 661787215796 ps
CPU time 348.77 seconds
Started Aug 23 01:24:03 AM UTC 24
Finished Aug 23 01:29:56 AM UTC 24
Peak memory 199676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084373121 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3084373121
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.4078239206
Short name T236
Test name
Test status
Simulation time 2672500582 ps
CPU time 6.59 seconds
Started Aug 23 01:53:06 AM UTC 24
Finished Aug 23 01:53:14 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078239206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.4078239206
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/40.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.1641493177
Short name T287
Test name
Test status
Simulation time 138623864173 ps
CPU time 1155.7 seconds
Started Aug 23 02:03:36 AM UTC 24
Finished Aug 23 02:23:03 AM UTC 24
Peak memory 202408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641493177 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1641493177
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/58.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.1286863748
Short name T183
Test name
Test status
Simulation time 186758981100 ps
CPU time 419.16 seconds
Started Aug 23 02:07:05 AM UTC 24
Finished Aug 23 02:14:09 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286863748 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1286863748
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/80.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.3623896011
Short name T307
Test name
Test status
Simulation time 632830987787 ps
CPU time 813.83 seconds
Started Aug 23 02:11:24 AM UTC 24
Finished Aug 23 02:25:07 AM UTC 24
Peak memory 202520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623896011 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3623896011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/95.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3241323158
Short name T66
Test name
Test status
Simulation time 71575089 ps
CPU time 1.48 seconds
Started Aug 23 02:38:22 AM UTC 24
Finished Aug 23 02:38:24 AM UTC 24
Peak memory 199104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241323158 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.3241323158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.271026736
Short name T323
Test name
Test status
Simulation time 241487380803 ps
CPU time 379.23 seconds
Started Aug 23 01:27:42 AM UTC 24
Finished Aug 23 01:34:05 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271026736 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.271026736
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.3995840288
Short name T302
Test name
Test status
Simulation time 2735344199090 ps
CPU time 832.43 seconds
Started Aug 23 02:13:44 AM UTC 24
Finished Aug 23 02:27:45 AM UTC 24
Peak memory 202448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995840288 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3995840288
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/101.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.2010527374
Short name T164
Test name
Test status
Simulation time 82314756025 ps
CPU time 50.21 seconds
Started Aug 23 02:15:14 AM UTC 24
Finished Aug 23 02:16:06 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010527374 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2010527374
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/108.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.1622481725
Short name T315
Test name
Test status
Simulation time 125778640148 ps
CPU time 723.33 seconds
Started Aug 23 01:29:22 AM UTC 24
Finished Aug 23 01:41:33 AM UTC 24
Peak memory 202416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622481725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1622481725
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/11.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.1957081202
Short name T99
Test name
Test status
Simulation time 677554451906 ps
CPU time 574.72 seconds
Started Aug 23 01:29:44 AM UTC 24
Finished Aug 23 01:39:25 AM UTC 24
Peak memory 199832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957081202 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.1957081202
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all_with_rand_reset.3130785287
Short name T12
Test name
Test status
Simulation time 15441172909 ps
CPU time 20.63 seconds
Started Aug 23 01:29:55 AM UTC 24
Finished Aug 23 01:30:17 AM UTC 24
Peak memory 206048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3130785287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.rv_timer_stress_all_with_rand_reset.3130785287
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.1214605758
Short name T231
Test name
Test status
Simulation time 142430848091 ps
CPU time 557.16 seconds
Started Aug 23 02:20:06 AM UTC 24
Finished Aug 23 02:29:29 AM UTC 24
Peak memory 202520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214605758 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1214605758
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/129.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.3351110380
Short name T74
Test name
Test status
Simulation time 65462879968 ps
CPU time 102 seconds
Started Aug 23 01:29:58 AM UTC 24
Finished Aug 23 01:31:42 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351110380 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3351110380
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/13.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.659166155
Short name T303
Test name
Test status
Simulation time 54217612593 ps
CPU time 107.52 seconds
Started Aug 23 02:21:27 AM UTC 24
Finished Aug 23 02:23:17 AM UTC 24
Peak memory 199812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659166155 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.659166155
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/133.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.1349810981
Short name T266
Test name
Test status
Simulation time 165435628782 ps
CPU time 280.77 seconds
Started Aug 23 02:21:32 AM UTC 24
Finished Aug 23 02:26:16 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349810981 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1349810981
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/134.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.3217789164
Short name T271
Test name
Test status
Simulation time 779552823905 ps
CPU time 901.91 seconds
Started Aug 23 02:21:41 AM UTC 24
Finished Aug 23 02:36:54 AM UTC 24
Peak memory 202448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217789164 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3217789164
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/135.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.3899045601
Short name T348
Test name
Test status
Simulation time 104252708934 ps
CPU time 306.14 seconds
Started Aug 23 02:24:35 AM UTC 24
Finished Aug 23 02:29:45 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899045601 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3899045601
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/147.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.3230910484
Short name T240
Test name
Test status
Simulation time 83568700674 ps
CPU time 168 seconds
Started Aug 23 02:24:52 AM UTC 24
Finished Aug 23 02:27:43 AM UTC 24
Peak memory 199844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230910484 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3230910484
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/148.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.1209059303
Short name T120
Test name
Test status
Simulation time 480637378935 ps
CPU time 110.43 seconds
Started Aug 23 01:31:30 AM UTC 24
Finished Aug 23 01:33:22 AM UTC 24
Peak memory 199804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209059303 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1209059303
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/15.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.3010202181
Short name T234
Test name
Test status
Simulation time 286245516653 ps
CPU time 497.41 seconds
Started Aug 23 02:26:18 AM UTC 24
Finished Aug 23 02:34:41 AM UTC 24
Peak memory 202184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010202181 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3010202181
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/152.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.1260790409
Short name T217
Test name
Test status
Simulation time 183515657182 ps
CPU time 115.92 seconds
Started Aug 23 02:27:44 AM UTC 24
Finished Aug 23 02:29:42 AM UTC 24
Peak memory 199612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260790409 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1260790409
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/159.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.3855851101
Short name T150
Test name
Test status
Simulation time 83385661869 ps
CPU time 73.89 seconds
Started Aug 23 02:29:43 AM UTC 24
Finished Aug 23 02:30:58 AM UTC 24
Peak memory 199868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855851101 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3855851101
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/171.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.4083367029
Short name T220
Test name
Test status
Simulation time 334507205719 ps
CPU time 1741.32 seconds
Started Aug 23 01:34:04 AM UTC 24
Finished Aug 23 02:03:24 AM UTC 24
Peak memory 202484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083367029 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.4083367029
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/18.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.1146020483
Short name T185
Test name
Test status
Simulation time 103636666617 ps
CPU time 43.68 seconds
Started Aug 23 02:32:29 AM UTC 24
Finished Aug 23 02:33:14 AM UTC 24
Peak memory 199612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146020483 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1146020483
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/183.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.4114430979
Short name T128
Test name
Test status
Simulation time 384730697823 ps
CPU time 201.27 seconds
Started Aug 23 01:34:54 AM UTC 24
Finished Aug 23 01:38:18 AM UTC 24
Peak memory 199844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114430979 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.4114430979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.121801667
Short name T319
Test name
Test status
Simulation time 392515877291 ps
CPU time 744.93 seconds
Started Aug 23 02:34:41 AM UTC 24
Finished Aug 23 02:47:15 AM UTC 24
Peak memory 202448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121801667 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.121801667
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/191.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.944360982
Short name T337
Test name
Test status
Simulation time 527612306440 ps
CPU time 256.03 seconds
Started Aug 23 02:36:15 AM UTC 24
Finished Aug 23 02:40:34 AM UTC 24
Peak memory 199844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944360982 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.944360982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/197.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.3949798960
Short name T102
Test name
Test status
Simulation time 177567206942 ps
CPU time 256.88 seconds
Started Aug 23 01:35:38 AM UTC 24
Finished Aug 23 01:39:58 AM UTC 24
Peak memory 199716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949798960 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.3949798960
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.360224598
Short name T146
Test name
Test status
Simulation time 152839706031 ps
CPU time 315.57 seconds
Started Aug 23 01:38:39 AM UTC 24
Finished Aug 23 01:43:59 AM UTC 24
Peak memory 199740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360224598 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.360224598
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/24.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.2610058051
Short name T308
Test name
Test status
Simulation time 2155050652420 ps
CPU time 756.39 seconds
Started Aug 23 01:49:01 AM UTC 24
Finished Aug 23 02:01:45 AM UTC 24
Peak memory 202520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610058051 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.2610058051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.3871484051
Short name T322
Test name
Test status
Simulation time 16885377095 ps
CPU time 6.34 seconds
Started Aug 23 01:49:58 AM UTC 24
Finished Aug 23 01:50:05 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871484051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3871484051
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/37.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.2654066073
Short name T211
Test name
Test status
Simulation time 220045787353 ps
CPU time 758.44 seconds
Started Aug 23 01:50:48 AM UTC 24
Finished Aug 23 02:03:35 AM UTC 24
Peak memory 202420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654066073 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.2654066073
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/38.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.1699477380
Short name T366
Test name
Test status
Simulation time 51644700835 ps
CPU time 49.88 seconds
Started Aug 23 01:54:58 AM UTC 24
Finished Aug 23 01:55:49 AM UTC 24
Peak memory 199676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699477380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1699477380
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/42.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.3902751081
Short name T321
Test name
Test status
Simulation time 5360341534 ps
CPU time 2.88 seconds
Started Aug 23 01:55:54 AM UTC 24
Finished Aug 23 01:55:58 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902751081 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.3902751081
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.1437082001
Short name T107
Test name
Test status
Simulation time 236720944856 ps
CPU time 94.5 seconds
Started Aug 23 01:26:03 AM UTC 24
Finished Aug 23 01:27:40 AM UTC 24
Peak memory 199784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437082001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1437082001
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/8.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2860267271
Short name T43
Test name
Test status
Simulation time 64699086 ps
CPU time 0.55 seconds
Started Aug 23 02:37:14 AM UTC 24
Finished Aug 23 02:37:16 AM UTC 24
Peak memory 198908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860267271 -assert nopostproc +UVM_TESTNA
ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.2860267271
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2472761328
Short name T42
Test name
Test status
Simulation time 104627535 ps
CPU time 1.17 seconds
Started Aug 23 02:37:11 AM UTC 24
Finished Aug 23 02:37:14 AM UTC 24
Peak memory 199040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472761328 -assert nopostproc +UVM_TESTNA
ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.2472761328
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1407869614
Short name T22
Test name
Test status
Simulation time 46461679 ps
CPU time 0.49 seconds
Started Aug 23 02:37:07 AM UTC 24
Finished Aug 23 02:37:09 AM UTC 24
Peak memory 198908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407869614 -assert nopostproc +UVM_TESTNA
ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.1407869614
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3118685681
Short name T33
Test name
Test status
Simulation time 32345543 ps
CPU time 0.68 seconds
Started Aug 23 02:37:19 AM UTC 24
Finished Aug 23 02:37:20 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3118685681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_cs
r_mem_rw_with_rand_reset.3118685681
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.1540144158
Short name T451
Test name
Test status
Simulation time 24651076 ps
CPU time 0.47 seconds
Started Aug 23 02:37:05 AM UTC 24
Finished Aug 23 02:37:07 AM UTC 24
Peak memory 198904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540144158 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1540144158
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.468955661
Short name T44
Test name
Test status
Simulation time 60133170 ps
CPU time 0.71 seconds
Started Aug 23 02:37:17 AM UTC 24
Finished Aug 23 02:37:18 AM UTC 24
Peak memory 198908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468955661 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.468955661
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.598903493
Short name T450
Test name
Test status
Simulation time 190538383 ps
CPU time 2.01 seconds
Started Aug 23 02:36:58 AM UTC 24
Finished Aug 23 02:37:01 AM UTC 24
Peak memory 200740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598903493 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.598903493
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2156749535
Short name T64
Test name
Test status
Simulation time 41088973 ps
CPU time 0.53 seconds
Started Aug 23 02:37:28 AM UTC 24
Finished Aug 23 02:37:30 AM UTC 24
Peak memory 199040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156749535 -assert nopostproc +UVM_TESTNA
ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.2156749535
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.26678565
Short name T34
Test name
Test status
Simulation time 551285264 ps
CPU time 1.34 seconds
Started Aug 23 02:37:27 AM UTC 24
Finished Aug 23 02:37:30 AM UTC 24
Peak memory 199040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26678565 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.26678565
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1795386327
Short name T36
Test name
Test status
Simulation time 68654239 ps
CPU time 0.51 seconds
Started Aug 23 02:37:26 AM UTC 24
Finished Aug 23 02:37:27 AM UTC 24
Peak memory 199040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795386327 -assert nopostproc +UVM_TESTNA
ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.1795386327
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2978493120
Short name T454
Test name
Test status
Simulation time 80113586 ps
CPU time 0.57 seconds
Started Aug 23 02:37:28 AM UTC 24
Finished Aug 23 02:37:30 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2978493120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_cs
r_mem_rw_with_rand_reset.2978493120
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.2471552434
Short name T453
Test name
Test status
Simulation time 42513583 ps
CPU time 0.49 seconds
Started Aug 23 02:37:24 AM UTC 24
Finished Aug 23 02:37:25 AM UTC 24
Peak memory 198904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471552434 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2471552434
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1533794313
Short name T57
Test name
Test status
Simulation time 17367382 ps
CPU time 0.64 seconds
Started Aug 23 02:37:28 AM UTC 24
Finished Aug 23 02:37:30 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533794313 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.1533794313
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.769034737
Short name T452
Test name
Test status
Simulation time 347687384 ps
CPU time 1.4 seconds
Started Aug 23 02:37:21 AM UTC 24
Finished Aug 23 02:37:23 AM UTC 24
Peak memory 199100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769034737 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.769034737
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1976305668
Short name T19
Test name
Test status
Simulation time 862766327 ps
CPU time 0.94 seconds
Started Aug 23 02:37:24 AM UTC 24
Finished Aug 23 02:37:26 AM UTC 24
Peak memory 198912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976305668 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.1976305668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2076061382
Short name T501
Test name
Test status
Simulation time 78129559 ps
CPU time 0.78 seconds
Started Aug 23 02:38:07 AM UTC 24
Finished Aug 23 02:38:09 AM UTC 24
Peak memory 198976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2076061382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_c
sr_mem_rw_with_rand_reset.2076061382
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.1392827199
Short name T497
Test name
Test status
Simulation time 31043283 ps
CPU time 0.51 seconds
Started Aug 23 02:38:05 AM UTC 24
Finished Aug 23 02:38:06 AM UTC 24
Peak memory 199036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392827199 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1392827199
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.2710816038
Short name T496
Test name
Test status
Simulation time 20343391 ps
CPU time 0.45 seconds
Started Aug 23 02:38:05 AM UTC 24
Finished Aug 23 02:38:06 AM UTC 24
Peak memory 198764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710816038 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2710816038
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/10.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1423882260
Short name T500
Test name
Test status
Simulation time 16862243 ps
CPU time 0.58 seconds
Started Aug 23 02:38:06 AM UTC 24
Finished Aug 23 02:38:07 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423882260 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.1423882260
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.4262467649
Short name T498
Test name
Test status
Simulation time 104200184 ps
CPU time 1.96 seconds
Started Aug 23 02:38:03 AM UTC 24
Finished Aug 23 02:38:06 AM UTC 24
Peak memory 200948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262467649 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.4262467649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1852542797
Short name T499
Test name
Test status
Simulation time 344488582 ps
CPU time 0.93 seconds
Started Aug 23 02:38:05 AM UTC 24
Finished Aug 23 02:38:06 AM UTC 24
Peak memory 199104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852542797 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.1852542797
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.652162703
Short name T507
Test name
Test status
Simulation time 17127960 ps
CPU time 0.58 seconds
Started Aug 23 02:38:10 AM UTC 24
Finished Aug 23 02:38:12 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=652162703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_cs
r_mem_rw_with_rand_reset.652162703
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.3492574221
Short name T504
Test name
Test status
Simulation time 16355257 ps
CPU time 0.51 seconds
Started Aug 23 02:38:08 AM UTC 24
Finished Aug 23 02:38:10 AM UTC 24
Peak memory 198896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492574221 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3492574221
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.2299940785
Short name T503
Test name
Test status
Simulation time 12920604 ps
CPU time 0.47 seconds
Started Aug 23 02:38:08 AM UTC 24
Finished Aug 23 02:38:09 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299940785 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2299940785
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/11.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2282669987
Short name T505
Test name
Test status
Simulation time 36020224 ps
CPU time 0.53 seconds
Started Aug 23 02:38:09 AM UTC 24
Finished Aug 23 02:38:11 AM UTC 24
Peak memory 198912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282669987 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.2282669987
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.190697276
Short name T502
Test name
Test status
Simulation time 98933564 ps
CPU time 1.48 seconds
Started Aug 23 02:38:07 AM UTC 24
Finished Aug 23 02:38:09 AM UTC 24
Peak memory 199100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190697276 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.190697276
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2954668385
Short name T67
Test name
Test status
Simulation time 121696150 ps
CPU time 1.14 seconds
Started Aug 23 02:38:07 AM UTC 24
Finished Aug 23 02:38:09 AM UTC 24
Peak memory 199104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954668385 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.2954668385
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1749762347
Short name T513
Test name
Test status
Simulation time 108206853 ps
CPU time 1.2 seconds
Started Aug 23 02:38:13 AM UTC 24
Finished Aug 23 02:38:15 AM UTC 24
Peak memory 198976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1749762347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_c
sr_mem_rw_with_rand_reset.1749762347
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.3467905939
Short name T510
Test name
Test status
Simulation time 37809961 ps
CPU time 0.47 seconds
Started Aug 23 02:38:11 AM UTC 24
Finished Aug 23 02:38:13 AM UTC 24
Peak memory 199036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467905939 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3467905939
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.2699934339
Short name T506
Test name
Test status
Simulation time 13909492 ps
CPU time 0.46 seconds
Started Aug 23 02:38:10 AM UTC 24
Finished Aug 23 02:38:12 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699934339 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2699934339
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/12.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3415889144
Short name T511
Test name
Test status
Simulation time 40694188 ps
CPU time 0.61 seconds
Started Aug 23 02:38:13 AM UTC 24
Finished Aug 23 02:38:14 AM UTC 24
Peak memory 198912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415889144 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.3415889144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.928842188
Short name T509
Test name
Test status
Simulation time 181923578 ps
CPU time 1.19 seconds
Started Aug 23 02:38:10 AM UTC 24
Finished Aug 23 02:38:13 AM UTC 24
Peak memory 198904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928842188 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.928842188
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2240309000
Short name T508
Test name
Test status
Simulation time 48970444 ps
CPU time 0.72 seconds
Started Aug 23 02:38:10 AM UTC 24
Finished Aug 23 02:38:12 AM UTC 24
Peak memory 199104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240309000 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.2240309000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2785273738
Short name T517
Test name
Test status
Simulation time 49163813 ps
CPU time 0.86 seconds
Started Aug 23 02:38:16 AM UTC 24
Finished Aug 23 02:38:18 AM UTC 24
Peak memory 198976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2785273738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_c
sr_mem_rw_with_rand_reset.2785273738
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.2962533166
Short name T516
Test name
Test status
Simulation time 13684185 ps
CPU time 0.66 seconds
Started Aug 23 02:38:15 AM UTC 24
Finished Aug 23 02:38:17 AM UTC 24
Peak memory 198908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962533166 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2962533166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.3753567959
Short name T514
Test name
Test status
Simulation time 11619765 ps
CPU time 0.68 seconds
Started Aug 23 02:38:14 AM UTC 24
Finished Aug 23 02:38:16 AM UTC 24
Peak memory 198900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753567959 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3753567959
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/13.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.912128140
Short name T518
Test name
Test status
Simulation time 82947575 ps
CPU time 0.95 seconds
Started Aug 23 02:38:16 AM UTC 24
Finished Aug 23 02:38:18 AM UTC 24
Peak memory 198916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912128140 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.912128140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.3913407071
Short name T512
Test name
Test status
Simulation time 185358980 ps
CPU time 1.09 seconds
Started Aug 23 02:38:13 AM UTC 24
Finished Aug 23 02:38:15 AM UTC 24
Peak memory 199096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913407071 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3913407071
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2138574231
Short name T515
Test name
Test status
Simulation time 735092662 ps
CPU time 1.47 seconds
Started Aug 23 02:38:14 AM UTC 24
Finished Aug 23 02:38:17 AM UTC 24
Peak memory 198908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138574231 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.2138574231
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1047568396
Short name T524
Test name
Test status
Simulation time 134526981 ps
CPU time 1.3 seconds
Started Aug 23 02:38:20 AM UTC 24
Finished Aug 23 02:38:23 AM UTC 24
Peak memory 198976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1047568396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_c
sr_mem_rw_with_rand_reset.1047568396
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.411921532
Short name T522
Test name
Test status
Simulation time 90598374 ps
CPU time 0.8 seconds
Started Aug 23 02:38:19 AM UTC 24
Finished Aug 23 02:38:21 AM UTC 24
Peak memory 199044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411921532 -assert nopostproc +UVM_TESTNAME=rv_t
imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.411921532
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.3181018903
Short name T519
Test name
Test status
Simulation time 18829887 ps
CPU time 0.83 seconds
Started Aug 23 02:38:18 AM UTC 24
Finished Aug 23 02:38:20 AM UTC 24
Peak memory 198840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181018903 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3181018903
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/14.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.550586032
Short name T523
Test name
Test status
Simulation time 31793294 ps
CPU time 0.92 seconds
Started Aug 23 02:38:19 AM UTC 24
Finished Aug 23 02:38:21 AM UTC 24
Peak memory 199112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550586032 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.550586032
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.539390938
Short name T521
Test name
Test status
Simulation time 36828074 ps
CPU time 2.04 seconds
Started Aug 23 02:38:18 AM UTC 24
Finished Aug 23 02:38:21 AM UTC 24
Peak memory 200876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539390938 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.539390938
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4124717523
Short name T520
Test name
Test status
Simulation time 72198382 ps
CPU time 1.24 seconds
Started Aug 23 02:38:18 AM UTC 24
Finished Aug 23 02:38:20 AM UTC 24
Peak memory 199104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124717523 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.4124717523
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2606914743
Short name T530
Test name
Test status
Simulation time 36409860 ps
CPU time 1.39 seconds
Started Aug 23 02:38:24 AM UTC 24
Finished Aug 23 02:38:27 AM UTC 24
Peak memory 198976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2606914743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_c
sr_mem_rw_with_rand_reset.2606914743
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.513473564
Short name T54
Test name
Test status
Simulation time 20212657 ps
CPU time 0.83 seconds
Started Aug 23 02:38:22 AM UTC 24
Finished Aug 23 02:38:24 AM UTC 24
Peak memory 199044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513473564 -assert nopostproc +UVM_TESTNAME=rv_t
imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.513473564
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.1162391943
Short name T526
Test name
Test status
Simulation time 51381419 ps
CPU time 0.64 seconds
Started Aug 23 02:38:22 AM UTC 24
Finished Aug 23 02:38:23 AM UTC 24
Peak memory 198940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162391943 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1162391943
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/15.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.367857741
Short name T527
Test name
Test status
Simulation time 30053676 ps
CPU time 0.71 seconds
Started Aug 23 02:38:22 AM UTC 24
Finished Aug 23 02:38:23 AM UTC 24
Peak memory 199092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367857741 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.367857741
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.303802264
Short name T525
Test name
Test status
Simulation time 82675072 ps
CPU time 1.63 seconds
Started Aug 23 02:38:20 AM UTC 24
Finished Aug 23 02:38:23 AM UTC 24
Peak memory 199100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303802264 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.303802264
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3209837789
Short name T534
Test name
Test status
Simulation time 99092062 ps
CPU time 1.78 seconds
Started Aug 23 02:38:27 AM UTC 24
Finished Aug 23 02:38:30 AM UTC 24
Peak memory 201024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3209837789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_c
sr_mem_rw_with_rand_reset.3209837789
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.332148033
Short name T55
Test name
Test status
Simulation time 22594152 ps
CPU time 0.82 seconds
Started Aug 23 02:38:24 AM UTC 24
Finished Aug 23 02:38:26 AM UTC 24
Peak memory 199044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332148033 -assert nopostproc +UVM_TESTNAME=rv_t
imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.332148033
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.2591422201
Short name T528
Test name
Test status
Simulation time 61673169 ps
CPU time 0.78 seconds
Started Aug 23 02:38:24 AM UTC 24
Finished Aug 23 02:38:26 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591422201 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2591422201
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/16.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2153000415
Short name T531
Test name
Test status
Simulation time 51403711 ps
CPU time 0.89 seconds
Started Aug 23 02:38:26 AM UTC 24
Finished Aug 23 02:38:27 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153000415 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.2153000415
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.4228663136
Short name T532
Test name
Test status
Simulation time 191369172 ps
CPU time 3.35 seconds
Started Aug 23 02:38:24 AM UTC 24
Finished Aug 23 02:38:29 AM UTC 24
Peak memory 200684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228663136 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.4228663136
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.808493234
Short name T529
Test name
Test status
Simulation time 223449753 ps
CPU time 0.93 seconds
Started Aug 23 02:38:24 AM UTC 24
Finished Aug 23 02:38:26 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808493234 -assert nopostproc +UVM_TEST
NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.808493234
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2766775000
Short name T539
Test name
Test status
Simulation time 109337345 ps
CPU time 0.94 seconds
Started Aug 23 02:38:31 AM UTC 24
Finished Aug 23 02:38:33 AM UTC 24
Peak memory 198976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=2766775000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_c
sr_mem_rw_with_rand_reset.2766775000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.2048613432
Short name T56
Test name
Test status
Simulation time 33189537 ps
CPU time 0.71 seconds
Started Aug 23 02:38:28 AM UTC 24
Finished Aug 23 02:38:30 AM UTC 24
Peak memory 199036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048613432 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2048613432
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.205573265
Short name T535
Test name
Test status
Simulation time 12086525 ps
CPU time 0.71 seconds
Started Aug 23 02:38:28 AM UTC 24
Finished Aug 23 02:38:30 AM UTC 24
Peak memory 198904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205573265 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.205573265
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/17.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1190259844
Short name T537
Test name
Test status
Simulation time 96609088 ps
CPU time 0.86 seconds
Started Aug 23 02:38:29 AM UTC 24
Finished Aug 23 02:38:31 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190259844 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.1190259844
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.3026483995
Short name T536
Test name
Test status
Simulation time 177155029 ps
CPU time 2.43 seconds
Started Aug 23 02:38:27 AM UTC 24
Finished Aug 23 02:38:30 AM UTC 24
Peak memory 202724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026483995 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3026483995
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.525819311
Short name T533
Test name
Test status
Simulation time 412690171 ps
CPU time 1.4 seconds
Started Aug 23 02:38:27 AM UTC 24
Finished Aug 23 02:38:29 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525819311 -assert nopostproc +UVM_TEST
NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.525819311
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3671288409
Short name T545
Test name
Test status
Simulation time 105698025 ps
CPU time 1.19 seconds
Started Aug 23 02:38:34 AM UTC 24
Finished Aug 23 02:38:36 AM UTC 24
Peak memory 198964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3671288409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_c
sr_mem_rw_with_rand_reset.3671288409
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.3950051891
Short name T543
Test name
Test status
Simulation time 23544135 ps
CPU time 0.78 seconds
Started Aug 23 02:38:32 AM UTC 24
Finished Aug 23 02:38:34 AM UTC 24
Peak memory 198908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950051891 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3950051891
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.3092834903
Short name T538
Test name
Test status
Simulation time 52705481 ps
CPU time 0.67 seconds
Started Aug 23 02:38:31 AM UTC 24
Finished Aug 23 02:38:33 AM UTC 24
Peak memory 198792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092834903 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3092834903
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/18.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3915452766
Short name T542
Test name
Test status
Simulation time 23420408 ps
CPU time 0.75 seconds
Started Aug 23 02:38:32 AM UTC 24
Finished Aug 23 02:38:34 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915452766 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.3915452766
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.1513648571
Short name T541
Test name
Test status
Simulation time 50427402 ps
CPU time 1.58 seconds
Started Aug 23 02:38:31 AM UTC 24
Finished Aug 23 02:38:33 AM UTC 24
Peak memory 199032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513648571 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1513648571
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2394669709
Short name T540
Test name
Test status
Simulation time 126026818 ps
CPU time 1.07 seconds
Started Aug 23 02:38:31 AM UTC 24
Finished Aug 23 02:38:33 AM UTC 24
Peak memory 199104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394669709 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.2394669709
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1562339771
Short name T555
Test name
Test status
Simulation time 26595467 ps
CPU time 1 seconds
Started Aug 23 02:38:38 AM UTC 24
Finished Aug 23 02:38:40 AM UTC 24
Peak memory 198908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1562339771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_c
sr_mem_rw_with_rand_reset.1562339771
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.3924997456
Short name T548
Test name
Test status
Simulation time 140827001 ps
CPU time 0.81 seconds
Started Aug 23 02:38:35 AM UTC 24
Finished Aug 23 02:38:37 AM UTC 24
Peak memory 199036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924997456 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3924997456
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.1232744438
Short name T547
Test name
Test status
Simulation time 50163053 ps
CPU time 0.8 seconds
Started Aug 23 02:38:35 AM UTC 24
Finished Aug 23 02:38:37 AM UTC 24
Peak memory 198840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232744438 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1232744438
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/19.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.605098743
Short name T549
Test name
Test status
Simulation time 17475367 ps
CPU time 0.85 seconds
Started Aug 23 02:38:35 AM UTC 24
Finished Aug 23 02:38:37 AM UTC 24
Peak memory 199112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605098743 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.605098743
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.4051743988
Short name T546
Test name
Test status
Simulation time 48989019 ps
CPU time 1.55 seconds
Started Aug 23 02:38:34 AM UTC 24
Finished Aug 23 02:38:36 AM UTC 24
Peak memory 199096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051743988 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.4051743988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.827261783
Short name T544
Test name
Test status
Simulation time 153099380 ps
CPU time 1.07 seconds
Started Aug 23 02:38:34 AM UTC 24
Finished Aug 23 02:38:36 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827261783 -assert nopostproc +UVM_TEST
NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.827261783
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3573467107
Short name T46
Test name
Test status
Simulation time 168424067 ps
CPU time 0.63 seconds
Started Aug 23 02:37:33 AM UTC 24
Finished Aug 23 02:37:35 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573467107 -assert nopostproc +UVM_TESTNA
ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.3573467107
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2566250560
Short name T48
Test name
Test status
Simulation time 195542155 ps
CPU time 2.32 seconds
Started Aug 23 02:37:33 AM UTC 24
Finished Aug 23 02:37:37 AM UTC 24
Peak memory 200944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566250560 -assert nopostproc +UVM_TESTNA
ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.2566250560
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.88921860
Short name T456
Test name
Test status
Simulation time 44721570 ps
CPU time 0.52 seconds
Started Aug 23 02:37:31 AM UTC 24
Finished Aug 23 02:37:33 AM UTC 24
Peak memory 198908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88921860 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.88921860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1677269664
Short name T458
Test name
Test status
Simulation time 80568998 ps
CPU time 1.14 seconds
Started Aug 23 02:37:36 AM UTC 24
Finished Aug 23 02:37:39 AM UTC 24
Peak memory 201020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1677269664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_cs
r_mem_rw_with_rand_reset.1677269664
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.1816121175
Short name T35
Test name
Test status
Simulation time 25879783 ps
CPU time 0.52 seconds
Started Aug 23 02:37:33 AM UTC 24
Finished Aug 23 02:37:35 AM UTC 24
Peak memory 199044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816121175 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1816121175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.2036086870
Short name T455
Test name
Test status
Simulation time 18415956 ps
CPU time 0.5 seconds
Started Aug 23 02:37:31 AM UTC 24
Finished Aug 23 02:37:33 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036086870 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2036086870
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.842681318
Short name T47
Test name
Test status
Simulation time 33574967 ps
CPU time 0.69 seconds
Started Aug 23 02:37:34 AM UTC 24
Finished Aug 23 02:37:37 AM UTC 24
Peak memory 199104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842681318 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.842681318
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.3552439860
Short name T457
Test name
Test status
Simulation time 668126922 ps
CPU time 2.15 seconds
Started Aug 23 02:37:30 AM UTC 24
Finished Aug 23 02:37:34 AM UTC 24
Peak memory 200748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552439860 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3552439860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.583799424
Short name T20
Test name
Test status
Simulation time 295160013 ps
CPU time 0.95 seconds
Started Aug 23 02:37:30 AM UTC 24
Finished Aug 23 02:37:33 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583799424 -assert nopostproc +UVM_TEST
NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.583799424
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.1939795767
Short name T552
Test name
Test status
Simulation time 12304898 ps
CPU time 0.82 seconds
Started Aug 23 02:38:38 AM UTC 24
Finished Aug 23 02:38:40 AM UTC 24
Peak memory 198900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939795767 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1939795767
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/20.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1811930976
Short name T554
Test name
Test status
Simulation time 21208231 ps
CPU time 0.83 seconds
Started Aug 23 02:38:38 AM UTC 24
Finished Aug 23 02:38:40 AM UTC 24
Peak memory 198900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811930976 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1811930976
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/21.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.105086209
Short name T557
Test name
Test status
Simulation time 69207278 ps
CPU time 0.77 seconds
Started Aug 23 02:38:38 AM UTC 24
Finished Aug 23 02:38:40 AM UTC 24
Peak memory 198904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105086209 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.105086209
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/22.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.1778950079
Short name T553
Test name
Test status
Simulation time 12295670 ps
CPU time 0.81 seconds
Started Aug 23 02:38:38 AM UTC 24
Finished Aug 23 02:38:40 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778950079 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1778950079
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/23.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.2159393334
Short name T556
Test name
Test status
Simulation time 41421641 ps
CPU time 0.79 seconds
Started Aug 23 02:38:38 AM UTC 24
Finished Aug 23 02:38:40 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159393334 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2159393334
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/24.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1696913471
Short name T559
Test name
Test status
Simulation time 41443747 ps
CPU time 0.81 seconds
Started Aug 23 02:38:41 AM UTC 24
Finished Aug 23 02:38:43 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696913471 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1696913471
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/25.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.342221780
Short name T560
Test name
Test status
Simulation time 69746445 ps
CPU time 0.82 seconds
Started Aug 23 02:38:41 AM UTC 24
Finished Aug 23 02:38:43 AM UTC 24
Peak memory 198916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342221780 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.342221780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/26.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.134946310
Short name T561
Test name
Test status
Simulation time 58452856 ps
CPU time 0.84 seconds
Started Aug 23 02:38:41 AM UTC 24
Finished Aug 23 02:38:43 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134946310 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.134946310
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/27.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.1972750011
Short name T558
Test name
Test status
Simulation time 15247202 ps
CPU time 0.67 seconds
Started Aug 23 02:38:41 AM UTC 24
Finished Aug 23 02:38:43 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972750011 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1972750011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/28.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.280201290
Short name T562
Test name
Test status
Simulation time 15199759 ps
CPU time 0.85 seconds
Started Aug 23 02:38:41 AM UTC 24
Finished Aug 23 02:38:43 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280201290 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.280201290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/29.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2330146130
Short name T462
Test name
Test status
Simulation time 73145293 ps
CPU time 1.29 seconds
Started Aug 23 02:37:41 AM UTC 24
Finished Aug 23 02:37:43 AM UTC 24
Peak memory 198908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330146130 -assert nopostproc +UVM_TESTNA
ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.2330146130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2706298500
Short name T50
Test name
Test status
Simulation time 47641381 ps
CPU time 0.49 seconds
Started Aug 23 02:37:40 AM UTC 24
Finished Aug 23 02:37:41 AM UTC 24
Peak memory 199040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706298500 -assert nopostproc +UVM_TESTNA
ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.2706298500
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.40628097
Short name T463
Test name
Test status
Simulation time 71409349 ps
CPU time 0.59 seconds
Started Aug 23 02:37:42 AM UTC 24
Finished Aug 23 02:37:43 AM UTC 24
Peak memory 198700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=40628097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_
mem_rw_with_rand_reset.40628097
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.3088481093
Short name T49
Test name
Test status
Simulation time 11122397 ps
CPU time 0.48 seconds
Started Aug 23 02:37:40 AM UTC 24
Finished Aug 23 02:37:41 AM UTC 24
Peak memory 199044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088481093 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3088481093
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.3582163865
Short name T459
Test name
Test status
Simulation time 29239071 ps
CPU time 0.49 seconds
Started Aug 23 02:37:38 AM UTC 24
Finished Aug 23 02:37:39 AM UTC 24
Peak memory 198904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582163865 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3582163865
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.662498237
Short name T58
Test name
Test status
Simulation time 236480569 ps
CPU time 0.7 seconds
Started Aug 23 02:37:41 AM UTC 24
Finished Aug 23 02:37:43 AM UTC 24
Peak memory 199104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662498237 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.662498237
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.4168556567
Short name T460
Test name
Test status
Simulation time 2173516248 ps
CPU time 1.79 seconds
Started Aug 23 02:37:36 AM UTC 24
Finished Aug 23 02:37:40 AM UTC 24
Peak memory 199100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168556567 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.4168556567
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2077748995
Short name T461
Test name
Test status
Simulation time 161352291 ps
CPU time 0.94 seconds
Started Aug 23 02:37:38 AM UTC 24
Finished Aug 23 02:37:40 AM UTC 24
Peak memory 198912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077748995 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.2077748995
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.786041616
Short name T563
Test name
Test status
Simulation time 10499657 ps
CPU time 0.82 seconds
Started Aug 23 02:38:42 AM UTC 24
Finished Aug 23 02:38:44 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786041616 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.786041616
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/30.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.37990835
Short name T564
Test name
Test status
Simulation time 43148700 ps
CPU time 0.76 seconds
Started Aug 23 02:38:44 AM UTC 24
Finished Aug 23 02:38:46 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37990835 -assert nopostproc +UVM_TESTNAME=rv_timer
_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.37990835
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/31.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.1738749646
Short name T565
Test name
Test status
Simulation time 39848051 ps
CPU time 0.87 seconds
Started Aug 23 02:38:44 AM UTC 24
Finished Aug 23 02:38:46 AM UTC 24
Peak memory 198900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738749646 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1738749646
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/32.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.3301845438
Short name T566
Test name
Test status
Simulation time 11778883 ps
CPU time 0.83 seconds
Started Aug 23 02:38:44 AM UTC 24
Finished Aug 23 02:38:46 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301845438 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3301845438
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/33.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.3686944380
Short name T567
Test name
Test status
Simulation time 19137075 ps
CPU time 0.79 seconds
Started Aug 23 02:38:44 AM UTC 24
Finished Aug 23 02:38:46 AM UTC 24
Peak memory 198900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686944380 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3686944380
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/34.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.2422803484
Short name T568
Test name
Test status
Simulation time 51879235 ps
CPU time 0.81 seconds
Started Aug 23 02:38:44 AM UTC 24
Finished Aug 23 02:38:46 AM UTC 24
Peak memory 198840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422803484 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2422803484
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/35.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.2777478276
Short name T569
Test name
Test status
Simulation time 14112534 ps
CPU time 0.83 seconds
Started Aug 23 02:38:45 AM UTC 24
Finished Aug 23 02:38:47 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777478276 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2777478276
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/36.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.815474152
Short name T571
Test name
Test status
Simulation time 31343322 ps
CPU time 0.84 seconds
Started Aug 23 02:38:47 AM UTC 24
Finished Aug 23 02:38:49 AM UTC 24
Peak memory 198596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815474152 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.815474152
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/37.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.1865083010
Short name T573
Test name
Test status
Simulation time 20286038 ps
CPU time 0.83 seconds
Started Aug 23 02:38:47 AM UTC 24
Finished Aug 23 02:38:49 AM UTC 24
Peak memory 198840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865083010 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1865083010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/38.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.3985818957
Short name T572
Test name
Test status
Simulation time 28578490 ps
CPU time 0.79 seconds
Started Aug 23 02:38:47 AM UTC 24
Finished Aug 23 02:38:49 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985818957 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3985818957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/39.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.556261867
Short name T467
Test name
Test status
Simulation time 19242361 ps
CPU time 0.59 seconds
Started Aug 23 02:37:45 AM UTC 24
Finished Aug 23 02:37:47 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556261867 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.556261867
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.254588101
Short name T469
Test name
Test status
Simulation time 1241497331 ps
CPU time 2.32 seconds
Started Aug 23 02:37:45 AM UTC 24
Finished Aug 23 02:37:49 AM UTC 24
Peak memory 200904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254588101 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.254588101
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.851881947
Short name T52
Test name
Test status
Simulation time 15682553 ps
CPU time 0.51 seconds
Started Aug 23 02:37:44 AM UTC 24
Finished Aug 23 02:37:46 AM UTC 24
Peak memory 198504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851881947 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.851881947
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1269968905
Short name T468
Test name
Test status
Simulation time 27825062 ps
CPU time 0.57 seconds
Started Aug 23 02:37:46 AM UTC 24
Finished Aug 23 02:37:48 AM UTC 24
Peak memory 198908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=1269968905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_cs
r_mem_rw_with_rand_reset.1269968905
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.3845304484
Short name T53
Test name
Test status
Simulation time 46870242 ps
CPU time 0.5 seconds
Started Aug 23 02:37:44 AM UTC 24
Finished Aug 23 02:37:46 AM UTC 24
Peak memory 198584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845304484 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3845304484
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.2344883443
Short name T465
Test name
Test status
Simulation time 45468933 ps
CPU time 0.45 seconds
Started Aug 23 02:37:43 AM UTC 24
Finished Aug 23 02:37:45 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344883443 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2344883443
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.747448152
Short name T59
Test name
Test status
Simulation time 21048919 ps
CPU time 0.71 seconds
Started Aug 23 02:37:45 AM UTC 24
Finished Aug 23 02:37:47 AM UTC 24
Peak memory 199104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747448152 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.747448152
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.2217071541
Short name T464
Test name
Test status
Simulation time 485623805 ps
CPU time 1.4 seconds
Started Aug 23 02:37:42 AM UTC 24
Finished Aug 23 02:37:44 AM UTC 24
Peak memory 198712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217071541 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2217071541
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3224380632
Short name T466
Test name
Test status
Simulation time 81759595 ps
CPU time 0.95 seconds
Started Aug 23 02:37:43 AM UTC 24
Finished Aug 23 02:37:45 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224380632 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.3224380632
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.1403885083
Short name T550
Test name
Test status
Simulation time 50764757 ps
CPU time 0.78 seconds
Started Aug 23 02:38:47 AM UTC 24
Finished Aug 23 02:38:49 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403885083 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1403885083
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/40.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.3934189247
Short name T574
Test name
Test status
Simulation time 31846353 ps
CPU time 0.81 seconds
Started Aug 23 02:38:47 AM UTC 24
Finished Aug 23 02:38:49 AM UTC 24
Peak memory 198900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934189247 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3934189247
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/41.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.4060892852
Short name T570
Test name
Test status
Simulation time 49593480 ps
CPU time 0.82 seconds
Started Aug 23 02:38:49 AM UTC 24
Finished Aug 23 02:38:50 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060892852 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.4060892852
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/42.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.779139014
Short name T551
Test name
Test status
Simulation time 16515569 ps
CPU time 0.8 seconds
Started Aug 23 02:38:51 AM UTC 24
Finished Aug 23 02:38:52 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779139014 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.779139014
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/43.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.1812766476
Short name T576
Test name
Test status
Simulation time 33210660 ps
CPU time 0.79 seconds
Started Aug 23 02:38:51 AM UTC 24
Finished Aug 23 02:38:52 AM UTC 24
Peak memory 198900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812766476 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1812766476
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/44.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1262467326
Short name T575
Test name
Test status
Simulation time 19412591 ps
CPU time 0.72 seconds
Started Aug 23 02:38:51 AM UTC 24
Finished Aug 23 02:38:52 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262467326 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1262467326
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/45.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.2481763510
Short name T577
Test name
Test status
Simulation time 28183576 ps
CPU time 0.81 seconds
Started Aug 23 02:38:51 AM UTC 24
Finished Aug 23 02:38:53 AM UTC 24
Peak memory 198900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481763510 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2481763510
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/46.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.3625281473
Short name T578
Test name
Test status
Simulation time 16732447 ps
CPU time 0.83 seconds
Started Aug 23 02:38:51 AM UTC 24
Finished Aug 23 02:38:53 AM UTC 24
Peak memory 198900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625281473 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3625281473
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/47.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.2852262210
Short name T579
Test name
Test status
Simulation time 14117256 ps
CPU time 0.77 seconds
Started Aug 23 02:38:52 AM UTC 24
Finished Aug 23 02:38:54 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852262210 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2852262210
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/48.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.117699506
Short name T580
Test name
Test status
Simulation time 43258533 ps
CPU time 0.72 seconds
Started Aug 23 02:38:54 AM UTC 24
Finished Aug 23 02:38:56 AM UTC 24
Peak memory 198932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117699506 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.117699506
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/49.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3390949603
Short name T474
Test name
Test status
Simulation time 50510463 ps
CPU time 0.63 seconds
Started Aug 23 02:37:50 AM UTC 24
Finished Aug 23 02:37:52 AM UTC 24
Peak memory 198604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3390949603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_cs
r_mem_rw_with_rand_reset.3390949603
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.3962044830
Short name T473
Test name
Test status
Simulation time 93296389 ps
CPU time 0.45 seconds
Started Aug 23 02:37:49 AM UTC 24
Finished Aug 23 02:37:50 AM UTC 24
Peak memory 199044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962044830 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3962044830
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.2783229494
Short name T471
Test name
Test status
Simulation time 46943455 ps
CPU time 0.47 seconds
Started Aug 23 02:37:48 AM UTC 24
Finished Aug 23 02:37:49 AM UTC 24
Peak memory 198904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783229494 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2783229494
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/5.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2237888042
Short name T60
Test name
Test status
Simulation time 25298265 ps
CPU time 0.62 seconds
Started Aug 23 02:37:50 AM UTC 24
Finished Aug 23 02:37:51 AM UTC 24
Peak memory 198952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237888042 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.2237888042
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.697245283
Short name T470
Test name
Test status
Simulation time 366053780 ps
CPU time 1.5 seconds
Started Aug 23 02:37:46 AM UTC 24
Finished Aug 23 02:37:49 AM UTC 24
Peak memory 201148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697245283 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.697245283
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1022306676
Short name T472
Test name
Test status
Simulation time 83320928 ps
CPU time 0.95 seconds
Started Aug 23 02:37:48 AM UTC 24
Finished Aug 23 02:37:49 AM UTC 24
Peak memory 198912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022306676 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.1022306676
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3206781345
Short name T479
Test name
Test status
Simulation time 180544912 ps
CPU time 0.73 seconds
Started Aug 23 02:37:53 AM UTC 24
Finished Aug 23 02:37:55 AM UTC 24
Peak memory 198900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3206781345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_cs
r_mem_rw_with_rand_reset.3206781345
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.714104069
Short name T477
Test name
Test status
Simulation time 16000880 ps
CPU time 0.51 seconds
Started Aug 23 02:37:52 AM UTC 24
Finished Aug 23 02:37:54 AM UTC 24
Peak memory 198848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714104069 -assert nopostproc +UVM_TESTNAME=rv_t
imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.714104069
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.1000420050
Short name T476
Test name
Test status
Simulation time 40168865 ps
CPU time 0.44 seconds
Started Aug 23 02:37:51 AM UTC 24
Finished Aug 23 02:37:53 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000420050 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1000420050
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/6.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1595905239
Short name T61
Test name
Test status
Simulation time 29997505 ps
CPU time 0.66 seconds
Started Aug 23 02:37:52 AM UTC 24
Finished Aug 23 02:37:54 AM UTC 24
Peak memory 199048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595905239 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.1595905239
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.467375759
Short name T478
Test name
Test status
Simulation time 206467524 ps
CPU time 2.87 seconds
Started Aug 23 02:37:50 AM UTC 24
Finished Aug 23 02:37:54 AM UTC 24
Peak memory 200680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467375759 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.467375759
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3942957902
Short name T475
Test name
Test status
Simulation time 168276061 ps
CPU time 0.68 seconds
Started Aug 23 02:37:50 AM UTC 24
Finished Aug 23 02:37:52 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942957902 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.3942957902
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.348648181
Short name T484
Test name
Test status
Simulation time 51292828 ps
CPU time 0.9 seconds
Started Aug 23 02:37:56 AM UTC 24
Finished Aug 23 02:37:58 AM UTC 24
Peak memory 201016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=348648181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr
_mem_rw_with_rand_reset.348648181
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.1578396344
Short name T483
Test name
Test status
Simulation time 21209875 ps
CPU time 0.5 seconds
Started Aug 23 02:37:55 AM UTC 24
Finished Aug 23 02:37:57 AM UTC 24
Peak memory 199044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578396344 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1578396344
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.2130226648
Short name T482
Test name
Test status
Simulation time 40078600 ps
CPU time 0.47 seconds
Started Aug 23 02:37:55 AM UTC 24
Finished Aug 23 02:37:57 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130226648 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2130226648
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/7.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.943021561
Short name T62
Test name
Test status
Simulation time 41823392 ps
CPU time 0.53 seconds
Started Aug 23 02:37:56 AM UTC 24
Finished Aug 23 02:37:58 AM UTC 24
Peak memory 198908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943021561 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.943021561
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.3562290532
Short name T480
Test name
Test status
Simulation time 53868870 ps
CPU time 1.06 seconds
Started Aug 23 02:37:53 AM UTC 24
Finished Aug 23 02:37:56 AM UTC 24
Peak memory 198904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562290532 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3562290532
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1047793218
Short name T481
Test name
Test status
Simulation time 119356612 ps
CPU time 1.13 seconds
Started Aug 23 02:37:54 AM UTC 24
Finished Aug 23 02:37:57 AM UTC 24
Peak memory 198912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047793218 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.1047793218
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3389055302
Short name T489
Test name
Test status
Simulation time 73879191 ps
CPU time 0.55 seconds
Started Aug 23 02:38:00 AM UTC 24
Finished Aug 23 02:38:01 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3389055302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_cs
r_mem_rw_with_rand_reset.3389055302
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.271834645
Short name T487
Test name
Test status
Simulation time 247534471 ps
CPU time 0.48 seconds
Started Aug 23 02:37:59 AM UTC 24
Finished Aug 23 02:38:00 AM UTC 24
Peak memory 199044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271834645 -assert nopostproc +UVM_TESTNAME=rv_t
imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.271834645
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.297082649
Short name T485
Test name
Test status
Simulation time 15921559 ps
CPU time 0.48 seconds
Started Aug 23 02:37:58 AM UTC 24
Finished Aug 23 02:37:59 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297082649 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.297082649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/8.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2716968857
Short name T63
Test name
Test status
Simulation time 61689411 ps
CPU time 0.67 seconds
Started Aug 23 02:37:59 AM UTC 24
Finished Aug 23 02:38:00 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716968857 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.2716968857
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.1262180813
Short name T488
Test name
Test status
Simulation time 476234996 ps
CPU time 2.58 seconds
Started Aug 23 02:37:58 AM UTC 24
Finished Aug 23 02:38:01 AM UTC 24
Peak memory 200592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262180813 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1262180813
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1019921172
Short name T486
Test name
Test status
Simulation time 125930798 ps
CPU time 0.93 seconds
Started Aug 23 02:37:58 AM UTC 24
Finished Aug 23 02:38:00 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019921172 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.1019921172
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3978075286
Short name T495
Test name
Test status
Simulation time 22804997 ps
CPU time 0.84 seconds
Started Aug 23 02:38:03 AM UTC 24
Finished Aug 23 02:38:05 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en
_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random
_seed=3978075286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_cs
r_mem_rw_with_rand_reset.3978075286
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.3511648198
Short name T493
Test name
Test status
Simulation time 23111454 ps
CPU time 0.5 seconds
Started Aug 23 02:38:02 AM UTC 24
Finished Aug 23 02:38:04 AM UTC 24
Peak memory 199044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511648198 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3511648198
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.1305323324
Short name T491
Test name
Test status
Simulation time 22994175 ps
CPU time 0.47 seconds
Started Aug 23 02:38:01 AM UTC 24
Finished Aug 23 02:38:03 AM UTC 24
Peak memory 198972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305323324 -assert nopostproc +UVM_TESTNAME=rv_tim
er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1305323324
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/9.rv_timer_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.4203727587
Short name T494
Test name
Test status
Simulation time 91282301 ps
CPU time 0.51 seconds
Started Aug 23 02:38:02 AM UTC 24
Finished Aug 23 02:38:04 AM UTC 24
Peak memory 199108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203727587 -assert nopostproc
+UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.4203727587
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.820178529
Short name T490
Test name
Test status
Simulation time 41055177 ps
CPU time 1 seconds
Started Aug 23 02:38:00 AM UTC 24
Finished Aug 23 02:38:02 AM UTC 24
Peak memory 198904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820178529 -assert nopostproc +UVM_TESTNAME=rv_time
r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.820178529
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3252855314
Short name T492
Test name
Test status
Simulation time 651255868 ps
CPU time 1.16 seconds
Started Aug 23 02:38:01 AM UTC 24
Finished Aug 23 02:38:03 AM UTC 24
Peak memory 198912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252855314 -assert nopostproc +UVM_TES
TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.3252855314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.2221467054
Short name T7
Test name
Test status
Simulation time 50115450404 ps
CPU time 41.85 seconds
Started Aug 23 01:23:14 AM UTC 24
Finished Aug 23 01:23:58 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221467054 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.2221467054
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.4243943934
Short name T17
Test name
Test status
Simulation time 45755003617 ps
CPU time 60 seconds
Started Aug 23 01:23:14 AM UTC 24
Finished Aug 23 01:24:16 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243943934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.4243943934
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.2127871568
Short name T109
Test name
Test status
Simulation time 754466221804 ps
CPU time 531.24 seconds
Started Aug 23 01:23:11 AM UTC 24
Finished Aug 23 01:32:08 AM UTC 24
Peak memory 202448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127871568 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2127871568
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.3843986144
Short name T2
Test name
Test status
Simulation time 9104924192 ps
CPU time 8.88 seconds
Started Aug 23 01:23:16 AM UTC 24
Finished Aug 23 01:23:26 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843986144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3843986144
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/0.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.634381004
Short name T115
Test name
Test status
Simulation time 647448208466 ps
CPU time 911.41 seconds
Started Aug 23 01:23:28 AM UTC 24
Finished Aug 23 01:38:48 AM UTC 24
Peak memory 202256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634381004 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.634381004
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.544759515
Short name T5
Test name
Test status
Simulation time 57300822634 ps
CPU time 21.89 seconds
Started Aug 23 01:23:26 AM UTC 24
Finished Aug 23 01:23:50 AM UTC 24
Peak memory 199676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544759515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.544759515
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.1586674312
Short name T201
Test name
Test status
Simulation time 113327661492 ps
CPU time 1261.04 seconds
Started Aug 23 01:23:26 AM UTC 24
Finished Aug 23 01:44:41 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586674312 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1586674312
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.3816428708
Short name T4
Test name
Test status
Simulation time 76452324 ps
CPU time 0.8 seconds
Started Aug 23 01:23:41 AM UTC 24
Finished Aug 23 01:23:43 AM UTC 24
Peak memory 228936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816428708 -assert nopostproc +UVM_TESTNAME=rv
_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3816428708
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.2364549563
Short name T119
Test name
Test status
Simulation time 557831150133 ps
CPU time 477.18 seconds
Started Aug 23 01:23:37 AM UTC 24
Finished Aug 23 01:31:40 AM UTC 24
Peak memory 202444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364549563 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.2364549563
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/1.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.1233221244
Short name T375
Test name
Test status
Simulation time 156264223844 ps
CPU time 51.57 seconds
Started Aug 23 01:27:24 AM UTC 24
Finished Aug 23 01:28:17 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233221244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1233221244
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/10.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.42575505
Short name T100
Test name
Test status
Simulation time 259408892668 ps
CPU time 140.2 seconds
Started Aug 23 01:26:50 AM UTC 24
Finished Aug 23 01:29:13 AM UTC 24
Peak memory 199872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42575505 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.42575505
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/10.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.2738700572
Short name T131
Test name
Test status
Simulation time 80693770859 ps
CPU time 162.67 seconds
Started Aug 23 01:27:55 AM UTC 24
Finished Aug 23 01:30:40 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738700572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2738700572
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/10.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.2628390016
Short name T208
Test name
Test status
Simulation time 139020756157 ps
CPU time 455.12 seconds
Started Aug 23 02:14:00 AM UTC 24
Finished Aug 23 02:21:41 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628390016 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2628390016
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/103.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.3329263172
Short name T280
Test name
Test status
Simulation time 45586749499 ps
CPU time 69.53 seconds
Started Aug 23 02:14:07 AM UTC 24
Finished Aug 23 02:15:18 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329263172 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3329263172
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/104.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.2693491123
Short name T313
Test name
Test status
Simulation time 104140546332 ps
CPU time 795.15 seconds
Started Aug 23 02:14:09 AM UTC 24
Finished Aug 23 02:27:33 AM UTC 24
Peak memory 202484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693491123 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2693491123
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/105.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.3385318924
Short name T368
Test name
Test status
Simulation time 649160432587 ps
CPU time 1350.28 seconds
Started Aug 23 02:14:13 AM UTC 24
Finished Aug 23 02:36:57 AM UTC 24
Peak memory 202484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385318924 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3385318924
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/106.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.2553382017
Short name T268
Test name
Test status
Simulation time 157692227043 ps
CPU time 524.79 seconds
Started Aug 23 02:15:19 AM UTC 24
Finished Aug 23 02:24:10 AM UTC 24
Peak memory 202448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553382017 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2553382017
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/109.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.114534451
Short name T77
Test name
Test status
Simulation time 51463311957 ps
CPU time 24.99 seconds
Started Aug 23 01:29:13 AM UTC 24
Finished Aug 23 01:29:40 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114534451 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.114534451
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.4166872517
Short name T376
Test name
Test status
Simulation time 127049201703 ps
CPU time 83.46 seconds
Started Aug 23 01:28:17 AM UTC 24
Finished Aug 23 01:29:42 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166872517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.4166872517
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/11.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.4050572455
Short name T87
Test name
Test status
Simulation time 47774672522 ps
CPU time 96.66 seconds
Started Aug 23 01:28:10 AM UTC 24
Finished Aug 23 01:29:49 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050572455 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.4050572455
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/11.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.1709095920
Short name T216
Test name
Test status
Simulation time 4018718694924 ps
CPU time 1134.72 seconds
Started Aug 23 02:15:23 AM UTC 24
Finished Aug 23 02:34:30 AM UTC 24
Peak memory 202444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709095920 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1709095920
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/110.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.2730383743
Short name T353
Test name
Test status
Simulation time 134475347026 ps
CPU time 108.87 seconds
Started Aug 23 02:15:25 AM UTC 24
Finished Aug 23 02:17:16 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730383743 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2730383743
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/111.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.4022553
Short name T436
Test name
Test status
Simulation time 74729201531 ps
CPU time 315.59 seconds
Started Aug 23 02:16:07 AM UTC 24
Finished Aug 23 02:21:26 AM UTC 24
Peak memory 199664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022553 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.4022553
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/112.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.2355108611
Short name T351
Test name
Test status
Simulation time 276074315900 ps
CPU time 204.8 seconds
Started Aug 23 02:16:53 AM UTC 24
Finished Aug 23 02:20:20 AM UTC 24
Peak memory 199780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355108611 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2355108611
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/114.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.41699679
Short name T333
Test name
Test status
Simulation time 16330955166 ps
CPU time 25.13 seconds
Started Aug 23 02:17:44 AM UTC 24
Finished Aug 23 02:18:10 AM UTC 24
Peak memory 199844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41699679 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.41699679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/118.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.1409249606
Short name T360
Test name
Test status
Simulation time 273705128535 ps
CPU time 90.61 seconds
Started Aug 23 02:17:57 AM UTC 24
Finished Aug 23 02:19:30 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409249606 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1409249606
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/119.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.2249977068
Short name T380
Test name
Test status
Simulation time 365649519586 ps
CPU time 150.67 seconds
Started Aug 23 01:29:43 AM UTC 24
Finished Aug 23 01:32:16 AM UTC 24
Peak memory 199676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249977068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2249977068
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/12.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.180552524
Short name T89
Test name
Test status
Simulation time 94973460438 ps
CPU time 82.97 seconds
Started Aug 23 01:29:50 AM UTC 24
Finished Aug 23 01:31:15 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180552524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.180552524
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/12.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.3741216957
Short name T192
Test name
Test status
Simulation time 25075893723 ps
CPU time 32.63 seconds
Started Aug 23 02:18:11 AM UTC 24
Finished Aug 23 02:18:45 AM UTC 24
Peak memory 199844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741216957 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3741216957
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/121.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.3100030955
Short name T434
Test name
Test status
Simulation time 18178442185 ps
CPU time 59.29 seconds
Started Aug 23 02:18:25 AM UTC 24
Finished Aug 23 02:19:26 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100030955 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3100030955
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/122.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.1495189819
Short name T165
Test name
Test status
Simulation time 532042405454 ps
CPU time 293.07 seconds
Started Aug 23 02:18:46 AM UTC 24
Finished Aug 23 02:23:43 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495189819 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1495189819
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/123.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.3227384806
Short name T435
Test name
Test status
Simulation time 92110599493 ps
CPU time 33.96 seconds
Started Aug 23 02:18:51 AM UTC 24
Finished Aug 23 02:19:27 AM UTC 24
Peak memory 199532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227384806 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3227384806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/124.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.1488365101
Short name T349
Test name
Test status
Simulation time 32449365485 ps
CPU time 36.78 seconds
Started Aug 23 02:19:26 AM UTC 24
Finished Aug 23 02:20:05 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488365101 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1488365101
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/125.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.207879921
Short name T359
Test name
Test status
Simulation time 169267398209 ps
CPU time 578.03 seconds
Started Aug 23 02:19:27 AM UTC 24
Finished Aug 23 02:29:12 AM UTC 24
Peak memory 202484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207879921 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.207879921
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/126.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.3901710093
Short name T449
Test name
Test status
Simulation time 317592174044 ps
CPU time 1841.33 seconds
Started Aug 23 02:19:31 AM UTC 24
Finished Aug 23 02:50:31 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901710093 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3901710093
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/127.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.1823508928
Short name T382
Test name
Test status
Simulation time 432848651131 ps
CPU time 168.17 seconds
Started Aug 23 01:30:14 AM UTC 24
Finished Aug 23 01:33:05 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823508928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1823508928
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/13.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.3335265489
Short name T140
Test name
Test status
Simulation time 97727615711 ps
CPU time 49.25 seconds
Started Aug 23 01:30:24 AM UTC 24
Finished Aug 23 01:31:15 AM UTC 24
Peak memory 199784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335265489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3335265489
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/13.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.3673849460
Short name T37
Test name
Test status
Simulation time 212389795430 ps
CPU time 265.01 seconds
Started Aug 23 01:30:32 AM UTC 24
Finished Aug 23 01:35:01 AM UTC 24
Peak memory 199604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673849460 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.3673849460
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/13.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.1257385094
Short name T253
Test name
Test status
Simulation time 206755588903 ps
CPU time 142.78 seconds
Started Aug 23 02:20:21 AM UTC 24
Finished Aug 23 02:22:46 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257385094 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1257385094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/130.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.822427219
Short name T225
Test name
Test status
Simulation time 79356037698 ps
CPU time 97.4 seconds
Started Aug 23 02:20:35 AM UTC 24
Finished Aug 23 02:22:14 AM UTC 24
Peak memory 199748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822427219 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.822427219
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/131.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.296812682
Short name T357
Test name
Test status
Simulation time 74779312423 ps
CPU time 422.33 seconds
Started Aug 23 02:20:41 AM UTC 24
Finished Aug 23 02:27:48 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296812682 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.296812682
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/132.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.3656623660
Short name T293
Test name
Test status
Simulation time 272970478185 ps
CPU time 182.72 seconds
Started Aug 23 02:21:46 AM UTC 24
Finished Aug 23 02:24:52 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656623660 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3656623660
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/136.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.4065764199
Short name T355
Test name
Test status
Simulation time 119281250486 ps
CPU time 395.26 seconds
Started Aug 23 02:22:47 AM UTC 24
Finished Aug 23 02:29:27 AM UTC 24
Peak memory 199844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065764199 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.4065764199
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/139.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.416594727
Short name T378
Test name
Test status
Simulation time 98493908386 ps
CPU time 34.34 seconds
Started Aug 23 01:30:52 AM UTC 24
Finished Aug 23 01:31:29 AM UTC 24
Peak memory 199748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416594727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.416594727
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/14.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.1430995115
Short name T133
Test name
Test status
Simulation time 93390168195 ps
CPU time 131.34 seconds
Started Aug 23 01:30:40 AM UTC 24
Finished Aug 23 01:32:54 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430995115 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1430995115
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/14.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.1707568868
Short name T377
Test name
Test status
Simulation time 427613832 ps
CPU time 0.94 seconds
Started Aug 23 01:31:16 AM UTC 24
Finished Aug 23 01:31:18 AM UTC 24
Peak memory 198992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707568868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1707568868
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/14.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.2795072677
Short name T365
Test name
Test status
Simulation time 1215003271619 ps
CPU time 1820.18 seconds
Started Aug 23 02:23:05 AM UTC 24
Finished Aug 23 02:53:44 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795072677 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2795072677
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/140.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.693687469
Short name T161
Test name
Test status
Simulation time 37916407530 ps
CPU time 97.08 seconds
Started Aug 23 02:23:14 AM UTC 24
Finished Aug 23 02:24:53 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693687469 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.693687469
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/141.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.3194027640
Short name T297
Test name
Test status
Simulation time 196079511366 ps
CPU time 194.29 seconds
Started Aug 23 02:23:18 AM UTC 24
Finished Aug 23 02:26:35 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194027640 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3194027640
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/142.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.2159474722
Short name T344
Test name
Test status
Simulation time 157956884457 ps
CPU time 48.62 seconds
Started Aug 23 02:23:44 AM UTC 24
Finished Aug 23 02:24:34 AM UTC 24
Peak memory 199612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159474722 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2159474722
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/143.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.2090977617
Short name T272
Test name
Test status
Simulation time 195311861515 ps
CPU time 179.27 seconds
Started Aug 23 02:23:52 AM UTC 24
Finished Aug 23 02:26:54 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090977617 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2090977617
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/144.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.2165782704
Short name T257
Test name
Test status
Simulation time 88432283642 ps
CPU time 123.91 seconds
Started Aug 23 02:24:11 AM UTC 24
Finished Aug 23 02:26:17 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165782704 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2165782704
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/146.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.837638332
Short name T203
Test name
Test status
Simulation time 169661400993 ps
CPU time 86.47 seconds
Started Aug 23 02:24:53 AM UTC 24
Finished Aug 23 02:26:22 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837638332 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.837638332
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/149.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.609281250
Short name T136
Test name
Test status
Simulation time 316690443303 ps
CPU time 237.89 seconds
Started Aug 23 01:31:38 AM UTC 24
Finished Aug 23 01:35:39 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609281250 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.609281250
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.4168083993
Short name T383
Test name
Test status
Simulation time 66331387400 ps
CPU time 93.92 seconds
Started Aug 23 01:31:33 AM UTC 24
Finished Aug 23 01:33:09 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168083993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.4168083993
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/15.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.3233993465
Short name T379
Test name
Test status
Simulation time 440848981 ps
CPU time 0.74 seconds
Started Aug 23 01:31:41 AM UTC 24
Finished Aug 23 01:31:43 AM UTC 24
Peak memory 198876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233993465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3233993465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/15.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all_with_rand_reset.1156179687
Short name T14
Test name
Test status
Simulation time 3772090470 ps
CPU time 14.57 seconds
Started Aug 23 01:31:43 AM UTC 24
Finished Aug 23 01:31:59 AM UTC 24
Peak memory 203964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1156179687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.rv_timer_stress_all_with_rand_reset.1156179687
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.2147116884
Short name T439
Test name
Test status
Simulation time 552759392182 ps
CPU time 181.53 seconds
Started Aug 23 02:26:18 AM UTC 24
Finished Aug 23 02:29:22 AM UTC 24
Peak memory 199412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147116884 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2147116884
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/151.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.2711584075
Short name T247
Test name
Test status
Simulation time 1098574852815 ps
CPU time 237.95 seconds
Started Aug 23 02:26:23 AM UTC 24
Finished Aug 23 02:30:24 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711584075 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2711584075
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/153.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.3632134156
Short name T239
Test name
Test status
Simulation time 66676231726 ps
CPU time 103.42 seconds
Started Aug 23 02:26:50 AM UTC 24
Finished Aug 23 02:28:35 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632134156 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3632134156
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/155.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.991020982
Short name T363
Test name
Test status
Simulation time 64988871744 ps
CPU time 84.73 seconds
Started Aug 23 02:26:55 AM UTC 24
Finished Aug 23 02:28:21 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991020982 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.991020982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/156.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.1472087953
Short name T327
Test name
Test status
Simulation time 375092619699 ps
CPU time 111.64 seconds
Started Aug 23 02:27:34 AM UTC 24
Finished Aug 23 02:29:28 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472087953 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1472087953
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/158.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.3129083400
Short name T114
Test name
Test status
Simulation time 175901525249 ps
CPU time 247.6 seconds
Started Aug 23 01:32:17 AM UTC 24
Finished Aug 23 01:36:28 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129083400 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.3129083400
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.3235831341
Short name T387
Test name
Test status
Simulation time 533931726632 ps
CPU time 204.21 seconds
Started Aug 23 01:32:09 AM UTC 24
Finished Aug 23 01:35:37 AM UTC 24
Peak memory 199784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235831341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3235831341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/16.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.2925873624
Short name T101
Test name
Test status
Simulation time 125546911186 ps
CPU time 214.73 seconds
Started Aug 23 01:31:59 AM UTC 24
Finished Aug 23 01:35:37 AM UTC 24
Peak memory 199780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925873624 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2925873624
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/16.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.620144646
Short name T381
Test name
Test status
Simulation time 48794166 ps
CPU time 0.51 seconds
Started Aug 23 01:32:34 AM UTC 24
Finished Aug 23 01:32:36 AM UTC 24
Peak memory 198880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620144646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.620144646
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/16.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.772303808
Short name T385
Test name
Test status
Simulation time 89219719212 ps
CPU time 112.41 seconds
Started Aug 23 01:32:48 AM UTC 24
Finished Aug 23 01:34:43 AM UTC 24
Peak memory 199612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772303808 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.772303808
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/16.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.716177204
Short name T262
Test name
Test status
Simulation time 51541902083 ps
CPU time 94.17 seconds
Started Aug 23 02:27:46 AM UTC 24
Finished Aug 23 02:29:22 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716177204 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.716177204
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/160.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.2116428581
Short name T235
Test name
Test status
Simulation time 1200778487996 ps
CPU time 1644.27 seconds
Started Aug 23 02:27:49 AM UTC 24
Finished Aug 23 02:55:31 AM UTC 24
Peak memory 202352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116428581 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2116428581
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/161.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.3643957022
Short name T325
Test name
Test status
Simulation time 95587095837 ps
CPU time 228.65 seconds
Started Aug 23 02:28:36 AM UTC 24
Finished Aug 23 02:32:28 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643957022 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3643957022
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/163.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.330445613
Short name T441
Test name
Test status
Simulation time 49712286937 ps
CPU time 72.03 seconds
Started Aug 23 02:29:05 AM UTC 24
Finished Aug 23 02:30:19 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330445613 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.330445613
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/164.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.2120854141
Short name T320
Test name
Test status
Simulation time 84413015654 ps
CPU time 68.22 seconds
Started Aug 23 02:29:23 AM UTC 24
Finished Aug 23 02:30:32 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120854141 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2120854141
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/166.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.190582780
Short name T440
Test name
Test status
Simulation time 34312546191 ps
CPU time 47.66 seconds
Started Aug 23 02:29:23 AM UTC 24
Finished Aug 23 02:30:12 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190582780 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.190582780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/167.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.4176758977
Short name T364
Test name
Test status
Simulation time 151784682639 ps
CPU time 577.72 seconds
Started Aug 23 02:29:28 AM UTC 24
Finished Aug 23 02:39:12 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176758977 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4176758977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/168.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.246336826
Short name T324
Test name
Test status
Simulation time 172221014552 ps
CPU time 122.28 seconds
Started Aug 23 02:29:29 AM UTC 24
Finished Aug 23 02:31:33 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246336826 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.246336826
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/169.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.1975397583
Short name T90
Test name
Test status
Simulation time 85609015041 ps
CPU time 122.42 seconds
Started Aug 23 01:33:08 AM UTC 24
Finished Aug 23 01:35:12 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975397583 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.1975397583
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.1736385265
Short name T384
Test name
Test status
Simulation time 229675974305 ps
CPU time 88.05 seconds
Started Aug 23 01:33:06 AM UTC 24
Finished Aug 23 01:34:36 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736385265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1736385265
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/17.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.2312298227
Short name T134
Test name
Test status
Simulation time 26829264112 ps
CPU time 100.45 seconds
Started Aug 23 01:32:54 AM UTC 24
Finished Aug 23 01:34:37 AM UTC 24
Peak memory 199844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312298227 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2312298227
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/17.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.2470767990
Short name T121
Test name
Test status
Simulation time 115488799475 ps
CPU time 111.01 seconds
Started Aug 23 01:33:10 AM UTC 24
Finished Aug 23 01:35:03 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470767990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2470767990
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/17.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.2369736619
Short name T393
Test name
Test status
Simulation time 892169343347 ps
CPU time 335.26 seconds
Started Aug 23 01:33:53 AM UTC 24
Finished Aug 23 01:39:32 AM UTC 24
Peak memory 199608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369736619 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.2369736619
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/17.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all_with_rand_reset.435692881
Short name T25
Test name
Test status
Simulation time 3740280138 ps
CPU time 38.92 seconds
Started Aug 23 01:33:23 AM UTC 24
Finished Aug 23 01:34:03 AM UTC 24
Peak memory 203888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=435692881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_stress_all_with_rand_reset.435692881
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.2325869909
Short name T330
Test name
Test status
Simulation time 475870263453 ps
CPU time 307.46 seconds
Started Aug 23 02:29:30 AM UTC 24
Finished Aug 23 02:34:41 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325869909 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2325869909
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/170.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.782410082
Short name T274
Test name
Test status
Simulation time 3086148888177 ps
CPU time 746.89 seconds
Started Aug 23 02:29:46 AM UTC 24
Finished Aug 23 02:42:21 AM UTC 24
Peak memory 202448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782410082 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.782410082
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/172.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.2605983762
Short name T443
Test name
Test status
Simulation time 165717105694 ps
CPU time 262.49 seconds
Started Aug 23 02:29:47 AM UTC 24
Finished Aug 23 02:34:13 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605983762 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2605983762
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/173.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.2157599690
Short name T358
Test name
Test status
Simulation time 469589637012 ps
CPU time 787.59 seconds
Started Aug 23 02:29:59 AM UTC 24
Finished Aug 23 02:43:15 AM UTC 24
Peak memory 202484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157599690 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2157599690
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/174.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.1965102711
Short name T213
Test name
Test status
Simulation time 916168861646 ps
CPU time 617.46 seconds
Started Aug 23 02:30:12 AM UTC 24
Finished Aug 23 02:40:37 AM UTC 24
Peak memory 202520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965102711 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1965102711
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/175.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.828391649
Short name T260
Test name
Test status
Simulation time 540523027678 ps
CPU time 286.42 seconds
Started Aug 23 02:30:33 AM UTC 24
Finished Aug 23 02:35:23 AM UTC 24
Peak memory 199668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828391649 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.828391649
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/178.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.3218991562
Short name T84
Test name
Test status
Simulation time 3978040115 ps
CPU time 6.34 seconds
Started Aug 23 01:34:35 AM UTC 24
Finished Aug 23 01:34:42 AM UTC 24
Peak memory 199660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218991562 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.3218991562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/18.rv_timer_disabled.3147953823
Short name T386
Test name
Test status
Simulation time 135791828601 ps
CPU time 44.57 seconds
Started Aug 23 01:34:06 AM UTC 24
Finished Aug 23 01:34:53 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147953823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3147953823
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/18.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.1400274851
Short name T76
Test name
Test status
Simulation time 43623001943 ps
CPU time 65.9 seconds
Started Aug 23 01:34:36 AM UTC 24
Finished Aug 23 01:35:44 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400274851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1400274851
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/18.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.3806973082
Short name T152
Test name
Test status
Simulation time 719083230043 ps
CPU time 804.45 seconds
Started Aug 23 01:34:43 AM UTC 24
Finished Aug 23 01:48:16 AM UTC 24
Peak memory 202344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806973082 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.3806973082
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/18.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.3705927669
Short name T255
Test name
Test status
Simulation time 1252502150629 ps
CPU time 905.06 seconds
Started Aug 23 02:30:59 AM UTC 24
Finished Aug 23 02:46:15 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705927669 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3705927669
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/180.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.1460845010
Short name T162
Test name
Test status
Simulation time 294915791027 ps
CPU time 172.79 seconds
Started Aug 23 02:31:34 AM UTC 24
Finished Aug 23 02:34:29 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460845010 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1460845010
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/181.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.1853287626
Short name T197
Test name
Test status
Simulation time 133626663398 ps
CPU time 194.04 seconds
Started Aug 23 02:32:54 AM UTC 24
Finished Aug 23 02:36:10 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853287626 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1853287626
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/184.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.2771394402
Short name T442
Test name
Test status
Simulation time 64317604438 ps
CPU time 39.34 seconds
Started Aug 23 02:33:15 AM UTC 24
Finished Aug 23 02:33:56 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771394402 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2771394402
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/185.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.4195133126
Short name T316
Test name
Test status
Simulation time 1433197779600 ps
CPU time 1833.11 seconds
Started Aug 23 02:33:56 AM UTC 24
Finished Aug 23 03:04:49 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195133126 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.4195133126
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/186.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.1918576361
Short name T298
Test name
Test status
Simulation time 558354402248 ps
CPU time 769.5 seconds
Started Aug 23 02:34:13 AM UTC 24
Finished Aug 23 02:47:12 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918576361 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1918576361
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/187.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.6061486
Short name T362
Test name
Test status
Simulation time 427556665101 ps
CPU time 102.92 seconds
Started Aug 23 02:34:29 AM UTC 24
Finished Aug 23 02:36:14 AM UTC 24
Peak memory 199664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6061486 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.6061486
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/188.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.2478589973
Short name T444
Test name
Test status
Simulation time 237681343 ps
CPU time 0.87 seconds
Started Aug 23 02:34:30 AM UTC 24
Finished Aug 23 02:34:32 AM UTC 24
Peak memory 198876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478589973 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2478589973
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/189.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.1223788428
Short name T389
Test name
Test status
Simulation time 112978965109 ps
CPU time 143.01 seconds
Started Aug 23 01:34:53 AM UTC 24
Finished Aug 23 01:37:26 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223788428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1223788428
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/19.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.2252240538
Short name T122
Test name
Test status
Simulation time 126651946874 ps
CPU time 54.92 seconds
Started Aug 23 01:34:43 AM UTC 24
Finished Aug 23 01:35:40 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252240538 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2252240538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/19.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.2118675538
Short name T110
Test name
Test status
Simulation time 136131250125 ps
CPU time 103.61 seconds
Started Aug 23 01:35:02 AM UTC 24
Finished Aug 23 01:36:48 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118675538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2118675538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/19.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.1626515130
Short name T93
Test name
Test status
Simulation time 1548980991736 ps
CPU time 419.91 seconds
Started Aug 23 01:35:12 AM UTC 24
Finished Aug 23 01:42:17 AM UTC 24
Peak memory 199840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626515130 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.1626515130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/19.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.4243397819
Short name T445
Test name
Test status
Simulation time 41145157239 ps
CPU time 64.2 seconds
Started Aug 23 02:34:33 AM UTC 24
Finished Aug 23 02:35:39 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243397819 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.4243397819
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/190.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.2015137006
Short name T448
Test name
Test status
Simulation time 469266885177 ps
CPU time 338.12 seconds
Started Aug 23 02:34:41 AM UTC 24
Finished Aug 23 02:40:24 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015137006 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2015137006
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/192.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.3502141553
Short name T446
Test name
Test status
Simulation time 24161257670 ps
CPU time 116.05 seconds
Started Aug 23 02:35:25 AM UTC 24
Finished Aug 23 02:37:23 AM UTC 24
Peak memory 199668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502141553 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3502141553
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/193.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.1746911077
Short name T284
Test name
Test status
Simulation time 149971895233 ps
CPU time 810.71 seconds
Started Aug 23 02:35:40 AM UTC 24
Finished Aug 23 02:49:20 AM UTC 24
Peak memory 202548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746911077 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1746911077
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/194.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.4104418747
Short name T447
Test name
Test status
Simulation time 229128023686 ps
CPU time 87.63 seconds
Started Aug 23 02:36:11 AM UTC 24
Finished Aug 23 02:37:40 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104418747 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.4104418747
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/195.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.3342236452
Short name T354
Test name
Test status
Simulation time 35707138274 ps
CPU time 34.12 seconds
Started Aug 23 02:36:15 AM UTC 24
Finished Aug 23 02:36:50 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342236452 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3342236452
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/196.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.452292536
Short name T361
Test name
Test status
Simulation time 244816661692 ps
CPU time 288.37 seconds
Started Aug 23 02:36:54 AM UTC 24
Finished Aug 23 02:41:47 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452292536 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.452292536
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/199.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.2158974881
Short name T69
Test name
Test status
Simulation time 583122515317 ps
CPU time 750.39 seconds
Started Aug 23 01:23:44 AM UTC 24
Finished Aug 23 01:36:23 AM UTC 24
Peak memory 202324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158974881 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.2158974881
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.4074812964
Short name T369
Test name
Test status
Simulation time 133168346423 ps
CPU time 101.32 seconds
Started Aug 23 01:23:41 AM UTC 24
Finished Aug 23 01:25:25 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074812964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.4074812964
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.1209439147
Short name T94
Test name
Test status
Simulation time 1065341076602 ps
CPU time 968.87 seconds
Started Aug 23 01:23:41 AM UTC 24
Finished Aug 23 01:40:01 AM UTC 24
Peak memory 202548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209439147 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1209439147
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.2175172466
Short name T135
Test name
Test status
Simulation time 31273465496 ps
CPU time 327.33 seconds
Started Aug 23 01:23:49 AM UTC 24
Finished Aug 23 01:29:21 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175172466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2175172466
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.1030049012
Short name T6
Test name
Test status
Simulation time 129246603 ps
CPU time 0.63 seconds
Started Aug 23 01:23:51 AM UTC 24
Finished Aug 23 01:23:52 AM UTC 24
Peak memory 230928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030049012 -assert nopostproc +UVM_TESTNAME=rv
_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1030049012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.999130411
Short name T106
Test name
Test status
Simulation time 75950639881 ps
CPU time 136.08 seconds
Started Aug 23 01:23:51 AM UTC 24
Finished Aug 23 01:26:09 AM UTC 24
Peak memory 199712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999130411 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.999130411
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/2.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.698126332
Short name T388
Test name
Test status
Simulation time 18732473373 ps
CPU time 25.67 seconds
Started Aug 23 01:35:33 AM UTC 24
Finished Aug 23 01:35:59 AM UTC 24
Peak memory 199676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698126332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.698126332
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/20.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.3790998723
Short name T117
Test name
Test status
Simulation time 834976629216 ps
CPU time 124.63 seconds
Started Aug 23 01:35:18 AM UTC 24
Finished Aug 23 01:37:24 AM UTC 24
Peak memory 199668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790998723 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3790998723
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/20.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.742394013
Short name T98
Test name
Test status
Simulation time 8664752398 ps
CPU time 12.31 seconds
Started Aug 23 01:35:38 AM UTC 24
Finished Aug 23 01:35:51 AM UTC 24
Peak memory 199600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742394013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.742394013
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/20.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.3542127575
Short name T394
Test name
Test status
Simulation time 176950238906 ps
CPU time 240.87 seconds
Started Aug 23 01:35:41 AM UTC 24
Finished Aug 23 01:39:45 AM UTC 24
Peak memory 199604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542127575 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.3542127575
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/20.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all_with_rand_reset.455963538
Short name T26
Test name
Test status
Simulation time 15986163937 ps
CPU time 30.1 seconds
Started Aug 23 01:35:40 AM UTC 24
Finished Aug 23 01:36:11 AM UTC 24
Peak memory 206044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=455963538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_stress_all_with_rand_reset.455963538
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.1403198841
Short name T79
Test name
Test status
Simulation time 4058920527 ps
CPU time 5.94 seconds
Started Aug 23 01:36:00 AM UTC 24
Finished Aug 23 01:36:07 AM UTC 24
Peak memory 199724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403198841 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.1403198841
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.2608272701
Short name T392
Test name
Test status
Simulation time 115498605840 ps
CPU time 163.98 seconds
Started Aug 23 01:35:52 AM UTC 24
Finished Aug 23 01:38:39 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608272701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2608272701
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/21.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.3306755012
Short name T86
Test name
Test status
Simulation time 17351926463 ps
CPU time 312.39 seconds
Started Aug 23 01:35:44 AM UTC 24
Finished Aug 23 01:41:00 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306755012 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3306755012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/21.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.305893101
Short name T190
Test name
Test status
Simulation time 153277682921 ps
CPU time 726.71 seconds
Started Aug 23 01:36:08 AM UTC 24
Finished Aug 23 01:48:23 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305893101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.305893101
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/21.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.3648314887
Short name T395
Test name
Test status
Simulation time 668436113884 ps
CPU time 243.09 seconds
Started Aug 23 01:36:23 AM UTC 24
Finished Aug 23 01:40:29 AM UTC 24
Peak memory 199700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648314887 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.3648314887
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/21.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all_with_rand_reset.1400935736
Short name T27
Test name
Test status
Simulation time 3570081200 ps
CPU time 13.99 seconds
Started Aug 23 01:36:12 AM UTC 24
Finished Aug 23 01:36:27 AM UTC 24
Peak memory 199792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1400935736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.rv_timer_stress_all_with_rand_reset.1400935736
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.331200290
Short name T390
Test name
Test status
Simulation time 340558416300 ps
CPU time 87.53 seconds
Started Aug 23 01:36:28 AM UTC 24
Finished Aug 23 01:37:58 AM UTC 24
Peak memory 199748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331200290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.331200290
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/22.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.179967433
Short name T81
Test name
Test status
Simulation time 226075295152 ps
CPU time 180.03 seconds
Started Aug 23 01:36:28 AM UTC 24
Finished Aug 23 01:39:31 AM UTC 24
Peak memory 199840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179967433 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.179967433
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/22.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.4109317479
Short name T70
Test name
Test status
Simulation time 43228111148 ps
CPU time 60.52 seconds
Started Aug 23 01:37:25 AM UTC 24
Finished Aug 23 01:38:29 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109317479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.4109317479
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/22.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.876042788
Short name T194
Test name
Test status
Simulation time 2616492255824 ps
CPU time 1004.46 seconds
Started Aug 23 01:37:57 AM UTC 24
Finished Aug 23 01:54:51 AM UTC 24
Peak memory 202424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876042788 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.876042788
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/22.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.1329674850
Short name T391
Test name
Test status
Simulation time 15221382686 ps
CPU time 21.82 seconds
Started Aug 23 01:37:59 AM UTC 24
Finished Aug 23 01:38:22 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329674850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1329674850
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/23.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.3428475556
Short name T97
Test name
Test status
Simulation time 120915833457 ps
CPU time 178.65 seconds
Started Aug 23 01:37:58 AM UTC 24
Finished Aug 23 01:40:59 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428475556 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3428475556
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/23.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.492009207
Short name T124
Test name
Test status
Simulation time 84497268386 ps
CPU time 116.8 seconds
Started Aug 23 01:38:23 AM UTC 24
Finished Aug 23 01:40:22 AM UTC 24
Peak memory 199688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492009207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.492009207
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/23.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.2236190239
Short name T402
Test name
Test status
Simulation time 414657150004 ps
CPU time 284.05 seconds
Started Aug 23 01:38:29 AM UTC 24
Finished Aug 23 01:43:16 AM UTC 24
Peak memory 199700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236190239 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.2236190239
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/23.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all_with_rand_reset.1663657224
Short name T28
Test name
Test status
Simulation time 2500784216 ps
CPU time 13.79 seconds
Started Aug 23 01:38:26 AM UTC 24
Finished Aug 23 01:38:41 AM UTC 24
Peak memory 201916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1663657224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.rv_timer_stress_all_with_rand_reset.1663657224
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.2801102468
Short name T80
Test name
Test status
Simulation time 38018206760 ps
CPU time 34.49 seconds
Started Aug 23 01:38:41 AM UTC 24
Finished Aug 23 01:39:17 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801102468 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.2801102468
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.3461517181
Short name T396
Test name
Test status
Simulation time 344639254589 ps
CPU time 111.18 seconds
Started Aug 23 01:38:40 AM UTC 24
Finished Aug 23 01:40:33 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461517181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3461517181
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/24.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.796864694
Short name T186
Test name
Test status
Simulation time 193161488980 ps
CPU time 91.69 seconds
Started Aug 23 01:38:49 AM UTC 24
Finished Aug 23 01:40:23 AM UTC 24
Peak memory 199712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796864694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.796864694
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/24.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.1627124047
Short name T233
Test name
Test status
Simulation time 87414016536 ps
CPU time 124.7 seconds
Started Aug 23 01:39:43 AM UTC 24
Finished Aug 23 01:41:50 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627124047 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.1627124047
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.615013657
Short name T397
Test name
Test status
Simulation time 272539652013 ps
CPU time 87.19 seconds
Started Aug 23 01:39:32 AM UTC 24
Finished Aug 23 01:41:02 AM UTC 24
Peak memory 199464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615013657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.615013657
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/25.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.2032300630
Short name T334
Test name
Test status
Simulation time 61857676424 ps
CPU time 63.01 seconds
Started Aug 23 01:39:32 AM UTC 24
Finished Aug 23 01:40:37 AM UTC 24
Peak memory 199528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032300630 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2032300630
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/25.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.1217429895
Short name T138
Test name
Test status
Simulation time 90343365729 ps
CPU time 466.95 seconds
Started Aug 23 01:39:45 AM UTC 24
Finished Aug 23 01:47:38 AM UTC 24
Peak memory 202452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217429895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1217429895
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/25.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.3550099215
Short name T198
Test name
Test status
Simulation time 39617472984 ps
CPU time 27.57 seconds
Started Aug 23 01:40:01 AM UTC 24
Finished Aug 23 01:40:30 AM UTC 24
Peak memory 199236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550099215 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.3550099215
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/25.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.1699383807
Short name T290
Test name
Test status
Simulation time 874807048894 ps
CPU time 422.12 seconds
Started Aug 23 01:40:24 AM UTC 24
Finished Aug 23 01:47:31 AM UTC 24
Peak memory 202328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699383807 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.1699383807
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.831292368
Short name T398
Test name
Test status
Simulation time 41231557963 ps
CPU time 56.6 seconds
Started Aug 23 01:40:23 AM UTC 24
Finished Aug 23 01:41:21 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831292368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.831292368
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/26.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.4080623879
Short name T288
Test name
Test status
Simulation time 58947750947 ps
CPU time 288.07 seconds
Started Aug 23 01:40:02 AM UTC 24
Finished Aug 23 01:44:53 AM UTC 24
Peak memory 199464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080623879 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.4080623879
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/26.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.269356668
Short name T129
Test name
Test status
Simulation time 187045054560 ps
CPU time 331.31 seconds
Started Aug 23 01:40:29 AM UTC 24
Finished Aug 23 01:46:04 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269356668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.269356668
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/26.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.768476094
Short name T104
Test name
Test status
Simulation time 327435524893 ps
CPU time 378.32 seconds
Started Aug 23 01:40:31 AM UTC 24
Finished Aug 23 01:46:53 AM UTC 24
Peak memory 199780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768476094 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.768476094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/26.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.2862395325
Short name T229
Test name
Test status
Simulation time 720519119246 ps
CPU time 529.58 seconds
Started Aug 23 01:40:49 AM UTC 24
Finished Aug 23 01:49:44 AM UTC 24
Peak memory 202648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862395325 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.2862395325
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.281246562
Short name T404
Test name
Test status
Simulation time 176731300329 ps
CPU time 259.84 seconds
Started Aug 23 01:40:38 AM UTC 24
Finished Aug 23 01:45:01 AM UTC 24
Peak memory 199784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281246562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.281246562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/27.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.391366411
Short name T244
Test name
Test status
Simulation time 41602233767 ps
CPU time 12.87 seconds
Started Aug 23 01:40:34 AM UTC 24
Finished Aug 23 01:40:48 AM UTC 24
Peak memory 199700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391366411 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.391366411
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/27.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.1864997197
Short name T314
Test name
Test status
Simulation time 45817167243 ps
CPU time 86.2 seconds
Started Aug 23 01:40:59 AM UTC 24
Finished Aug 23 01:42:27 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864997197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1864997197
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/27.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.355663334
Short name T137
Test name
Test status
Simulation time 143648644314 ps
CPU time 187.88 seconds
Started Aug 23 01:41:02 AM UTC 24
Finished Aug 23 01:44:13 AM UTC 24
Peak memory 199908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355663334 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.355663334
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/27.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.2401457991
Short name T112
Test name
Test status
Simulation time 38898579923 ps
CPU time 17.46 seconds
Started Aug 23 01:41:21 AM UTC 24
Finished Aug 23 01:41:40 AM UTC 24
Peak memory 199660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401457991 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.2401457991
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.1693358909
Short name T403
Test name
Test status
Simulation time 210795290196 ps
CPU time 154.78 seconds
Started Aug 23 01:41:18 AM UTC 24
Finished Aug 23 01:43:56 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693358909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1693358909
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/28.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.2381697544
Short name T111
Test name
Test status
Simulation time 148503969598 ps
CPU time 421.28 seconds
Started Aug 23 01:41:08 AM UTC 24
Finished Aug 23 01:48:14 AM UTC 24
Peak memory 199776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381697544 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2381697544
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/28.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.3676887441
Short name T399
Test name
Test status
Simulation time 480156888 ps
CPU time 0.62 seconds
Started Aug 23 01:41:33 AM UTC 24
Finished Aug 23 01:41:35 AM UTC 24
Peak memory 198876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676887441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3676887441
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/28.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all_with_rand_reset.3599196587
Short name T29
Test name
Test status
Simulation time 3370719689 ps
CPU time 22.91 seconds
Started Aug 23 01:41:36 AM UTC 24
Finished Aug 23 01:42:01 AM UTC 24
Peak memory 203888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=3599196587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 28.rv_timer_stress_all_with_rand_reset.3599196587
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.926130702
Short name T200
Test name
Test status
Simulation time 289570764378 ps
CPU time 398.6 seconds
Started Aug 23 01:42:18 AM UTC 24
Finished Aug 23 01:49:01 AM UTC 24
Peak memory 202464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926130702 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.926130702
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.2634373520
Short name T400
Test name
Test status
Simulation time 15490938955 ps
CPU time 20.36 seconds
Started Aug 23 01:42:02 AM UTC 24
Finished Aug 23 01:42:23 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634373520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2634373520
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/29.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.3156768034
Short name T300
Test name
Test status
Simulation time 149803790570 ps
CPU time 51.82 seconds
Started Aug 23 01:41:51 AM UTC 24
Finished Aug 23 01:42:44 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156768034 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3156768034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/29.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.1028553889
Short name T286
Test name
Test status
Simulation time 1894281891 ps
CPU time 3.21 seconds
Started Aug 23 01:42:24 AM UTC 24
Finished Aug 23 01:42:28 AM UTC 24
Peak memory 199684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028553889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1028553889
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/29.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all_with_rand_reset.1394380016
Short name T30
Test name
Test status
Simulation time 661205875 ps
CPU time 8.17 seconds
Started Aug 23 01:42:28 AM UTC 24
Finished Aug 23 01:42:37 AM UTC 24
Peak memory 201776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1394380016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.rv_timer_stress_all_with_rand_reset.1394380016
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.2416698425
Short name T95
Test name
Test status
Simulation time 144394409024 ps
CPU time 69.92 seconds
Started Aug 23 01:23:53 AM UTC 24
Finished Aug 23 01:25:05 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416698425 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.2416698425
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.3969440861
Short name T10
Test name
Test status
Simulation time 18097248222 ps
CPU time 11.53 seconds
Started Aug 23 01:23:53 AM UTC 24
Finished Aug 23 01:24:06 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969440861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3969440861
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.832346037
Short name T113
Test name
Test status
Simulation time 48858341954 ps
CPU time 357.5 seconds
Started Aug 23 01:23:52 AM UTC 24
Finished Aug 23 01:29:54 AM UTC 24
Peak memory 199668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832346037 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.832346037
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.159764007
Short name T8
Test name
Test status
Simulation time 89038406 ps
CPU time 0.68 seconds
Started Aug 23 01:24:01 AM UTC 24
Finished Aug 23 01:24:03 AM UTC 24
Peak memory 230888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159764007 -assert nopostproc +UVM_TESTNAME=rv_
timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.159764007
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.1179928917
Short name T88
Test name
Test status
Simulation time 13040188440 ps
CPU time 353.84 seconds
Started Aug 23 01:23:59 AM UTC 24
Finished Aug 23 01:29:57 AM UTC 24
Peak memory 199704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179928917 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.1179928917
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/3.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.3206787166
Short name T149
Test name
Test status
Simulation time 294813435620 ps
CPU time 447.88 seconds
Started Aug 23 01:42:56 AM UTC 24
Finished Aug 23 01:50:29 AM UTC 24
Peak memory 202352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206787166 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.3206787166
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.176562015
Short name T401
Test name
Test status
Simulation time 6990052064 ps
CPU time 9.04 seconds
Started Aug 23 01:42:45 AM UTC 24
Finished Aug 23 01:42:55 AM UTC 24
Peak memory 199676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176562015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.176562015
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/30.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.3182053695
Short name T222
Test name
Test status
Simulation time 24044985481 ps
CPU time 32.93 seconds
Started Aug 23 01:42:38 AM UTC 24
Finished Aug 23 01:43:12 AM UTC 24
Peak memory 199668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182053695 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3182053695
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/30.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.609456029
Short name T285
Test name
Test status
Simulation time 9070051003 ps
CPU time 3.78 seconds
Started Aug 23 01:43:13 AM UTC 24
Finished Aug 23 01:43:18 AM UTC 24
Peak memory 199780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609456029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.609456029
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/30.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.2530909850
Short name T406
Test name
Test status
Simulation time 282603540589 ps
CPU time 201.68 seconds
Started Aug 23 01:43:56 AM UTC 24
Finished Aug 23 01:47:21 AM UTC 24
Peak memory 199592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530909850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2530909850
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/31.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.1497896966
Short name T167
Test name
Test status
Simulation time 122549746237 ps
CPU time 758.44 seconds
Started Aug 23 01:43:32 AM UTC 24
Finished Aug 23 01:56:19 AM UTC 24
Peak memory 202584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497896966 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1497896966
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/31.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.835328843
Short name T340
Test name
Test status
Simulation time 95577879893 ps
CPU time 78.88 seconds
Started Aug 23 01:44:14 AM UTC 24
Finished Aug 23 01:45:34 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835328843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.835328843
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/31.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.1690321583
Short name T295
Test name
Test status
Simulation time 1225498708938 ps
CPU time 537.46 seconds
Started Aug 23 01:44:42 AM UTC 24
Finished Aug 23 01:53:45 AM UTC 24
Peak memory 202480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690321583 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.1690321583
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/31.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.313760774
Short name T215
Test name
Test status
Simulation time 97881715221 ps
CPU time 141.83 seconds
Started Aug 23 01:45:02 AM UTC 24
Finished Aug 23 01:47:26 AM UTC 24
Peak memory 199584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313760774 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.313760774
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.267345214
Short name T409
Test name
Test status
Simulation time 750885793340 ps
CPU time 241.6 seconds
Started Aug 23 01:44:54 AM UTC 24
Finished Aug 23 01:48:59 AM UTC 24
Peak memory 199812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267345214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.267345214
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/32.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.1023795575
Short name T166
Test name
Test status
Simulation time 36312085273 ps
CPU time 54.11 seconds
Started Aug 23 01:44:43 AM UTC 24
Finished Aug 23 01:45:38 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023795575 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1023795575
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/32.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.180895384
Short name T352
Test name
Test status
Simulation time 12009661820 ps
CPU time 5.79 seconds
Started Aug 23 01:45:08 AM UTC 24
Finished Aug 23 01:45:15 AM UTC 24
Peak memory 199784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180895384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.180895384
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/32.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.3705660019
Short name T309
Test name
Test status
Simulation time 10509960879 ps
CPU time 13.88 seconds
Started Aug 23 01:45:39 AM UTC 24
Finished Aug 23 01:45:54 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705660019 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.3705660019
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.3402981032
Short name T153
Test name
Test status
Simulation time 328226594246 ps
CPU time 301.41 seconds
Started Aug 23 01:45:34 AM UTC 24
Finished Aug 23 01:50:40 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402981032 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3402981032
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/33.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.527692775
Short name T405
Test name
Test status
Simulation time 271446027 ps
CPU time 0.58 seconds
Started Aug 23 01:45:55 AM UTC 24
Finished Aug 23 01:45:57 AM UTC 24
Peak memory 198876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527692775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.527692775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/33.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.3034772103
Short name T227
Test name
Test status
Simulation time 646294312309 ps
CPU time 798.58 seconds
Started Aug 23 01:46:05 AM UTC 24
Finished Aug 23 01:59:33 AM UTC 24
Peak memory 202404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034772103 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.3034772103
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/33.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.852764815
Short name T412
Test name
Test status
Simulation time 438412782392 ps
CPU time 139.01 seconds
Started Aug 23 01:46:55 AM UTC 24
Finished Aug 23 01:49:16 AM UTC 24
Peak memory 199676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852764815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.852764815
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/34.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.696758175
Short name T407
Test name
Test status
Simulation time 1049236770 ps
CPU time 1.14 seconds
Started Aug 23 01:47:27 AM UTC 24
Finished Aug 23 01:47:29 AM UTC 24
Peak memory 199024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696758175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.696758175
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/34.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all_with_rand_reset.435325590
Short name T31
Test name
Test status
Simulation time 1181535536 ps
CPU time 10.54 seconds
Started Aug 23 01:47:30 AM UTC 24
Finished Aug 23 01:47:42 AM UTC 24
Peak memory 201848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=435325590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_stress_all_with_rand_reset.435325590
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.3447590066
Short name T331
Test name
Test status
Simulation time 864339741597 ps
CPU time 369.95 seconds
Started Aug 23 01:48:15 AM UTC 24
Finished Aug 23 01:54:30 AM UTC 24
Peak memory 199660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447590066 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.3447590066
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.4100254084
Short name T413
Test name
Test status
Simulation time 584708879416 ps
CPU time 182.19 seconds
Started Aug 23 01:47:42 AM UTC 24
Finished Aug 23 01:50:47 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100254084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.4100254084
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/35.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.3096891822
Short name T408
Test name
Test status
Simulation time 8442940986 ps
CPU time 6.57 seconds
Started Aug 23 01:48:17 AM UTC 24
Finished Aug 23 01:48:25 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096891822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3096891822
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/35.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all_with_rand_reset.4264981860
Short name T410
Test name
Test status
Simulation time 13798371570 ps
CPU time 35.5 seconds
Started Aug 23 01:48:23 AM UTC 24
Finished Aug 23 01:49:00 AM UTC 24
Peak memory 206176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=4264981860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.rv_timer_stress_all_with_rand_reset.4264981860
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.2041472988
Short name T418
Test name
Test status
Simulation time 304915319018 ps
CPU time 186.38 seconds
Started Aug 23 01:48:59 AM UTC 24
Finished Aug 23 01:52:08 AM UTC 24
Peak memory 199728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041472988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2041472988
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/36.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.4223709347
Short name T175
Test name
Test status
Simulation time 114075495978 ps
CPU time 687.61 seconds
Started Aug 23 01:48:27 AM UTC 24
Finished Aug 23 02:00:03 AM UTC 24
Peak memory 202548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223709347 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.4223709347
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/36.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.153769926
Short name T411
Test name
Test status
Simulation time 23388599372 ps
CPU time 9.15 seconds
Started Aug 23 01:49:02 AM UTC 24
Finished Aug 23 01:49:12 AM UTC 24
Peak memory 199676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153769926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.153769926
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/36.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.247999192
Short name T187
Test name
Test status
Simulation time 84981157096 ps
CPU time 65.22 seconds
Started Aug 23 01:49:45 AM UTC 24
Finished Aug 23 01:50:52 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247999192 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.247999192
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.2338430875
Short name T415
Test name
Test status
Simulation time 502570519841 ps
CPU time 101.86 seconds
Started Aug 23 01:49:17 AM UTC 24
Finished Aug 23 01:51:01 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338430875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2338430875
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/37.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.2636943362
Short name T142
Test name
Test status
Simulation time 222109912055 ps
CPU time 366.08 seconds
Started Aug 23 01:49:15 AM UTC 24
Finished Aug 23 01:55:25 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636943362 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2636943362
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/37.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.2504732977
Short name T174
Test name
Test status
Simulation time 4167691780532 ps
CPU time 1504.01 seconds
Started Aug 23 01:50:06 AM UTC 24
Finished Aug 23 02:15:24 AM UTC 24
Peak memory 202440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504732977 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.2504732977
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/37.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all_with_rand_reset.1793228629
Short name T414
Test name
Test status
Simulation time 18467006582 ps
CPU time 45.72 seconds
Started Aug 23 01:50:00 AM UTC 24
Finished Aug 23 01:50:47 AM UTC 24
Peak memory 206112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=1793228629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.rv_timer_stress_all_with_rand_reset.1793228629
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.2919420414
Short name T329
Test name
Test status
Simulation time 741909071480 ps
CPU time 531.12 seconds
Started Aug 23 01:50:36 AM UTC 24
Finished Aug 23 01:59:33 AM UTC 24
Peak memory 199612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919420414 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.2919420414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.1699893952
Short name T416
Test name
Test status
Simulation time 58620456669 ps
CPU time 79.47 seconds
Started Aug 23 01:50:29 AM UTC 24
Finished Aug 23 01:51:51 AM UTC 24
Peak memory 199664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699893952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1699893952
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/38.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.19253593
Short name T189
Test name
Test status
Simulation time 165346719996 ps
CPU time 437.61 seconds
Started Aug 23 01:50:24 AM UTC 24
Finished Aug 23 01:57:47 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19253593 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.19253593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/38.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.263344985
Short name T238
Test name
Test status
Simulation time 111459656616 ps
CPU time 190.1 seconds
Started Aug 23 01:50:40 AM UTC 24
Finished Aug 23 01:53:53 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263344985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.263344985
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/38.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.338507775
Short name T141
Test name
Test status
Simulation time 493805957639 ps
CPU time 216.19 seconds
Started Aug 23 01:51:17 AM UTC 24
Finished Aug 23 01:54:56 AM UTC 24
Peak memory 199584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338507775 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.338507775
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.1730936562
Short name T422
Test name
Test status
Simulation time 350457206593 ps
CPU time 249.79 seconds
Started Aug 23 01:51:02 AM UTC 24
Finished Aug 23 01:55:14 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730936562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1730936562
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/39.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.3524197342
Short name T156
Test name
Test status
Simulation time 129292560771 ps
CPU time 389.82 seconds
Started Aug 23 01:50:52 AM UTC 24
Finished Aug 23 01:57:27 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524197342 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3524197342
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/39.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.4046149532
Short name T417
Test name
Test status
Simulation time 220101053 ps
CPU time 0.71 seconds
Started Aug 23 01:51:52 AM UTC 24
Finished Aug 23 01:51:54 AM UTC 24
Peak memory 198876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046149532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.4046149532
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/39.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.3218866076
Short name T419
Test name
Test status
Simulation time 437840433490 ps
CPU time 160.99 seconds
Started Aug 23 01:52:02 AM UTC 24
Finished Aug 23 01:54:45 AM UTC 24
Peak memory 199700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218866076 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.3218866076
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/39.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.1710051034
Short name T13
Test name
Test status
Simulation time 1382853412 ps
CPU time 2.6 seconds
Started Aug 23 01:24:07 AM UTC 24
Finished Aug 23 01:24:11 AM UTC 24
Peak memory 199396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710051034 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.1710051034
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.2867016863
Short name T24
Test name
Test status
Simulation time 210212079699 ps
CPU time 29 seconds
Started Aug 23 01:24:07 AM UTC 24
Finished Aug 23 01:24:37 AM UTC 24
Peak memory 199780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867016863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2867016863
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.3003811754
Short name T127
Test name
Test status
Simulation time 373505940517 ps
CPU time 313.8 seconds
Started Aug 23 01:24:11 AM UTC 24
Finished Aug 23 01:29:29 AM UTC 24
Peak memory 199720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003811754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3003811754
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.4302972
Short name T16
Test name
Test status
Simulation time 89830590 ps
CPU time 0.79 seconds
Started Aug 23 01:24:15 AM UTC 24
Finished Aug 23 01:24:17 AM UTC 24
Peak memory 230888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4302972 -assert nopostproc +UVM_TESTNAME=rv_ti
mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.4302972
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.3530833973
Short name T237
Test name
Test status
Simulation time 24829609531 ps
CPU time 35.26 seconds
Started Aug 23 01:52:56 AM UTC 24
Finished Aug 23 01:53:33 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530833973 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.3530833973
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.1483784359
Short name T423
Test name
Test status
Simulation time 140913751182 ps
CPU time 170.75 seconds
Started Aug 23 01:52:25 AM UTC 24
Finished Aug 23 01:55:19 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483784359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1483784359
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/40.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.2252649169
Short name T181
Test name
Test status
Simulation time 94551792218 ps
CPU time 138.16 seconds
Started Aug 23 01:52:09 AM UTC 24
Finished Aug 23 01:54:30 AM UTC 24
Peak memory 199740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252649169 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2252649169
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/40.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.1907472258
Short name T278
Test name
Test status
Simulation time 303690987825 ps
CPU time 533.95 seconds
Started Aug 23 01:53:27 AM UTC 24
Finished Aug 23 02:02:28 AM UTC 24
Peak memory 202440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907472258 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.1907472258
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/40.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.3218639518
Short name T195
Test name
Test status
Simulation time 71867056157 ps
CPU time 100.23 seconds
Started Aug 23 01:53:54 AM UTC 24
Finished Aug 23 01:55:36 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218639518 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.3218639518
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.3722224094
Short name T421
Test name
Test status
Simulation time 52471113297 ps
CPU time 74.52 seconds
Started Aug 23 01:53:46 AM UTC 24
Finished Aug 23 01:55:02 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722224094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3722224094
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/41.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.3533944981
Short name T326
Test name
Test status
Simulation time 175943291634 ps
CPU time 159.15 seconds
Started Aug 23 01:53:34 AM UTC 24
Finished Aug 23 01:56:15 AM UTC 24
Peak memory 199868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533944981 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3533944981
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/41.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.575037011
Short name T246
Test name
Test status
Simulation time 40503870366 ps
CPU time 65 seconds
Started Aug 23 01:54:31 AM UTC 24
Finished Aug 23 01:55:37 AM UTC 24
Peak memory 199748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575037011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.575037011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/41.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.2018149925
Short name T168
Test name
Test status
Simulation time 491848845600 ps
CPU time 232.47 seconds
Started Aug 23 01:54:34 AM UTC 24
Finished Aug 23 01:58:30 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018149925 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.2018149925
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/41.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.2356731379
Short name T282
Test name
Test status
Simulation time 1173198977109 ps
CPU time 520.29 seconds
Started Aug 23 01:54:56 AM UTC 24
Finished Aug 23 02:03:42 AM UTC 24
Peak memory 202448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356731379 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.2356731379
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.2141830143
Short name T420
Test name
Test status
Simulation time 3057598862 ps
CPU time 4.24 seconds
Started Aug 23 01:54:52 AM UTC 24
Finished Aug 23 01:54:57 AM UTC 24
Peak memory 199460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141830143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2141830143
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/42.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.652023038
Short name T207
Test name
Test status
Simulation time 141521611413 ps
CPU time 393.35 seconds
Started Aug 23 01:54:46 AM UTC 24
Finished Aug 23 02:01:24 AM UTC 24
Peak memory 199804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652023038 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.652023038
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/42.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.3370788130
Short name T151
Test name
Test status
Simulation time 209896591637 ps
CPU time 583.52 seconds
Started Aug 23 01:55:09 AM UTC 24
Finished Aug 23 02:04:59 AM UTC 24
Peak memory 202440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370788130 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.3370788130
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/42.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.126342622
Short name T292
Test name
Test status
Simulation time 487568856611 ps
CPU time 235.52 seconds
Started Aug 23 01:55:19 AM UTC 24
Finished Aug 23 01:59:18 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126342622 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.126342622
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.2831601123
Short name T427
Test name
Test status
Simulation time 218133657309 ps
CPU time 254.91 seconds
Started Aug 23 01:55:15 AM UTC 24
Finished Aug 23 01:59:33 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831601123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2831601123
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/43.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.937822108
Short name T212
Test name
Test status
Simulation time 411603893471 ps
CPU time 253.84 seconds
Started Aug 23 01:55:12 AM UTC 24
Finished Aug 23 01:59:30 AM UTC 24
Peak memory 199904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937822108 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.937822108
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/43.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.3789816316
Short name T241
Test name
Test status
Simulation time 52074184713 ps
CPU time 18.44 seconds
Started Aug 23 01:55:26 AM UTC 24
Finished Aug 23 01:55:46 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789816316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3789816316
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/43.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.3930767593
Short name T143
Test name
Test status
Simulation time 6201303473324 ps
CPU time 958.09 seconds
Started Aug 23 01:55:39 AM UTC 24
Finished Aug 23 02:11:46 AM UTC 24
Peak memory 202440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930767593 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.3930767593
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/43.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.3272999000
Short name T424
Test name
Test status
Simulation time 52505952534 ps
CPU time 70.14 seconds
Started Aug 23 01:55:51 AM UTC 24
Finished Aug 23 01:57:03 AM UTC 24
Peak memory 199676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272999000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3272999000
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/44.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.4010148421
Short name T158
Test name
Test status
Simulation time 237373392995 ps
CPU time 510.93 seconds
Started Aug 23 01:55:47 AM UTC 24
Finished Aug 23 02:04:24 AM UTC 24
Peak memory 199780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010148421 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.4010148421
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/44.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.777651253
Short name T304
Test name
Test status
Simulation time 30399901116 ps
CPU time 55.33 seconds
Started Aug 23 01:55:59 AM UTC 24
Finished Aug 23 01:56:56 AM UTC 24
Peak memory 199688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777651253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.777651253
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/44.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.2118791389
Short name T310
Test name
Test status
Simulation time 23677403516 ps
CPU time 30.23 seconds
Started Aug 23 01:57:03 AM UTC 24
Finished Aug 23 01:57:35 AM UTC 24
Peak memory 199660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118791389 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.2118791389
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.1085479012
Short name T426
Test name
Test status
Simulation time 99030175571 ps
CPU time 142.66 seconds
Started Aug 23 01:56:56 AM UTC 24
Finished Aug 23 01:59:21 AM UTC 24
Peak memory 199712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085479012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1085479012
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/45.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.859432801
Short name T317
Test name
Test status
Simulation time 139025412382 ps
CPU time 658.44 seconds
Started Aug 23 01:56:25 AM UTC 24
Finished Aug 23 02:07:31 AM UTC 24
Peak memory 202404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859432801 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.859432801
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/45.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.3662940414
Short name T232
Test name
Test status
Simulation time 183323274713 ps
CPU time 77.47 seconds
Started Aug 23 01:57:28 AM UTC 24
Finished Aug 23 01:58:48 AM UTC 24
Peak memory 199912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662940414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3662940414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/45.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.1524126465
Short name T219
Test name
Test status
Simulation time 3056500101141 ps
CPU time 1750.15 seconds
Started Aug 23 01:57:35 AM UTC 24
Finished Aug 23 02:27:03 AM UTC 24
Peak memory 202516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524126465 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.1524126465
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/45.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.3505363728
Short name T228
Test name
Test status
Simulation time 380514117384 ps
CPU time 174.84 seconds
Started Aug 23 01:58:31 AM UTC 24
Finished Aug 23 02:01:28 AM UTC 24
Peak memory 199788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505363728 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.3505363728
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.1027514323
Short name T425
Test name
Test status
Simulation time 37448504664 ps
CPU time 53.81 seconds
Started Aug 23 01:58:07 AM UTC 24
Finished Aug 23 01:59:02 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027514323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1027514323
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/46.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.1486667734
Short name T291
Test name
Test status
Simulation time 136572833180 ps
CPU time 187.41 seconds
Started Aug 23 01:57:47 AM UTC 24
Finished Aug 23 02:00:58 AM UTC 24
Peak memory 199776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486667734 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1486667734
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/46.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.4079787706
Short name T437
Test name
Test status
Simulation time 169305263184 ps
CPU time 1362.9 seconds
Started Aug 23 01:58:49 AM UTC 24
Finished Aug 23 02:21:45 AM UTC 24
Peak memory 202488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079787706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.4079787706
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/46.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.2725637417
Short name T184
Test name
Test status
Simulation time 627419863239 ps
CPU time 136.23 seconds
Started Aug 23 01:59:30 AM UTC 24
Finished Aug 23 02:01:49 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725637417 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.2725637417
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.301465676
Short name T428
Test name
Test status
Simulation time 72367137805 ps
CPU time 101.38 seconds
Started Aug 23 01:59:22 AM UTC 24
Finished Aug 23 02:01:05 AM UTC 24
Peak memory 199664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301465676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.301465676
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/47.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.3262445787
Short name T178
Test name
Test status
Simulation time 213782010047 ps
CPU time 407.51 seconds
Started Aug 23 01:59:19 AM UTC 24
Finished Aug 23 02:06:12 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262445787 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3262445787
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/47.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.2924362889
Short name T245
Test name
Test status
Simulation time 63995713856 ps
CPU time 32.02 seconds
Started Aug 23 01:59:34 AM UTC 24
Finished Aug 23 02:00:08 AM UTC 24
Peak memory 199536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924362889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2924362889
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/47.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.1373848146
Short name T191
Test name
Test status
Simulation time 107556993268 ps
CPU time 167.4 seconds
Started Aug 23 02:00:44 AM UTC 24
Finished Aug 23 02:03:34 AM UTC 24
Peak memory 199716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373848146 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.1373848146
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.1756228541
Short name T430
Test name
Test status
Simulation time 597567324073 ps
CPU time 233.64 seconds
Started Aug 23 02:00:08 AM UTC 24
Finished Aug 23 02:04:05 AM UTC 24
Peak memory 199848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756228541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1756228541
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/48.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.2873629484
Short name T281
Test name
Test status
Simulation time 55321472212 ps
CPU time 77.9 seconds
Started Aug 23 02:00:07 AM UTC 24
Finished Aug 23 02:01:27 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873629484 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2873629484
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/48.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.2954445251
Short name T242
Test name
Test status
Simulation time 35426301796 ps
CPU time 65.2 seconds
Started Aug 23 02:00:58 AM UTC 24
Finished Aug 23 02:02:05 AM UTC 24
Peak memory 199620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954445251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2954445251
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/48.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all_with_rand_reset.362659975
Short name T32
Test name
Test status
Simulation time 5083179979 ps
CPU time 16.94 seconds
Started Aug 23 02:01:06 AM UTC 24
Finished Aug 23 02:01:25 AM UTC 24
Peak memory 201752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s
eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool
s/sim.tcl +ntb_random_seed=362659975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_stress_all_with_rand_reset.362659975
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/48.rv_timer_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.4221696266
Short name T335
Test name
Test status
Simulation time 134072293248 ps
CPU time 221.18 seconds
Started Aug 23 02:01:28 AM UTC 24
Finished Aug 23 02:05:12 AM UTC 24
Peak memory 199660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221696266 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.4221696266
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.3850760541
Short name T429
Test name
Test status
Simulation time 16522509265 ps
CPU time 6.35 seconds
Started Aug 23 02:01:26 AM UTC 24
Finished Aug 23 02:01:33 AM UTC 24
Peak memory 199748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850760541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3850760541
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/49.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.4224704798
Short name T338
Test name
Test status
Simulation time 353374590150 ps
CPU time 329.17 seconds
Started Aug 23 02:01:29 AM UTC 24
Finished Aug 23 02:07:03 AM UTC 24
Peak memory 199712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224704798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.4224704798
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/49.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.2017057889
Short name T311
Test name
Test status
Simulation time 534386392737 ps
CPU time 902.66 seconds
Started Aug 23 02:01:43 AM UTC 24
Finished Aug 23 02:16:55 AM UTC 24
Peak memory 202516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017057889 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.2017057889
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/49.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.2794296872
Short name T71
Test name
Test status
Simulation time 160917763226 ps
CPU time 138.48 seconds
Started Aug 23 01:24:17 AM UTC 24
Finished Aug 23 01:26:38 AM UTC 24
Peak memory 199780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794296872 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.2794296872
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.34819291
Short name T65
Test name
Test status
Simulation time 91193057790 ps
CPU time 24.18 seconds
Started Aug 23 01:24:16 AM UTC 24
Finished Aug 23 01:24:42 AM UTC 24
Peak memory 199676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34819291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_
SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.34819291
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/5.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.3615011055
Short name T132
Test name
Test status
Simulation time 1347554516775 ps
CPU time 424.16 seconds
Started Aug 23 01:24:15 AM UTC 24
Finished Aug 23 01:31:24 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615011055 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3615011055
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/5.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.4097499449
Short name T21
Test name
Test status
Simulation time 26430328 ps
CPU time 0.48 seconds
Started Aug 23 01:24:20 AM UTC 24
Finished Aug 23 01:24:21 AM UTC 24
Peak memory 198876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097499449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.4097499449
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/5.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.3836486641
Short name T68
Test name
Test status
Simulation time 353728052492 ps
CPU time 496.34 seconds
Started Aug 23 01:24:26 AM UTC 24
Finished Aug 23 01:32:48 AM UTC 24
Peak memory 199612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836486641 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.3836486641
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/5.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.51329806
Short name T301
Test name
Test status
Simulation time 295781606693 ps
CPU time 178.42 seconds
Started Aug 23 02:01:46 AM UTC 24
Finished Aug 23 02:04:47 AM UTC 24
Peak memory 199780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51329806 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.51329806
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/50.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.4214400573
Short name T177
Test name
Test status
Simulation time 99416956252 ps
CPU time 289.85 seconds
Started Aug 23 02:01:50 AM UTC 24
Finished Aug 23 02:06:44 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214400573 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.4214400573
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/51.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.398503060
Short name T182
Test name
Test status
Simulation time 241758844372 ps
CPU time 449.44 seconds
Started Aug 23 02:02:25 AM UTC 24
Finished Aug 23 02:10:00 AM UTC 24
Peak memory 199868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398503060 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.398503060
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/53.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.3944912665
Short name T144
Test name
Test status
Simulation time 128011720643 ps
CPU time 146.28 seconds
Started Aug 23 02:02:28 AM UTC 24
Finished Aug 23 02:04:57 AM UTC 24
Peak memory 199844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944912665 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3944912665
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/54.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.1082531298
Short name T339
Test name
Test status
Simulation time 98192890580 ps
CPU time 2588.12 seconds
Started Aug 23 02:02:58 AM UTC 24
Finished Aug 23 02:46:33 AM UTC 24
Peak memory 202548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082531298 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1082531298
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/55.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.2480767414
Short name T256
Test name
Test status
Simulation time 21519277288 ps
CPU time 173.56 seconds
Started Aug 23 02:03:24 AM UTC 24
Finished Aug 23 02:06:21 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480767414 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2480767414
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/56.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.2553046014
Short name T305
Test name
Test status
Simulation time 86215174513 ps
CPU time 83.21 seconds
Started Aug 23 02:03:26 AM UTC 24
Finished Aug 23 02:04:51 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553046014 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2553046014
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/57.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.3248654444
Short name T169
Test name
Test status
Simulation time 233769695723 ps
CPU time 1006.56 seconds
Started Aug 23 02:03:36 AM UTC 24
Finished Aug 23 02:20:34 AM UTC 24
Peak memory 202612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248654444 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3248654444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/59.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.1798063444
Short name T82
Test name
Test status
Simulation time 787989971202 ps
CPU time 297.33 seconds
Started Aug 23 01:24:42 AM UTC 24
Finished Aug 23 01:29:43 AM UTC 24
Peak memory 199844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798063444 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.1798063444
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.3332932948
Short name T374
Test name
Test status
Simulation time 285255698372 ps
CPU time 196.44 seconds
Started Aug 23 01:24:38 AM UTC 24
Finished Aug 23 01:27:57 AM UTC 24
Peak memory 199780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332932948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3332932948
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/6.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.3750496265
Short name T118
Test name
Test status
Simulation time 42242902718 ps
CPU time 52.07 seconds
Started Aug 23 01:24:59 AM UTC 24
Finished Aug 23 01:25:52 AM UTC 24
Peak memory 199464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750496265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3750496265
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/6.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.75329296
Short name T130
Test name
Test status
Simulation time 719464602397 ps
CPU time 313.75 seconds
Started Aug 23 01:25:06 AM UTC 24
Finished Aug 23 01:30:24 AM UTC 24
Peak memory 199704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75329296 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.75329296
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/6.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.3596156982
Short name T296
Test name
Test status
Simulation time 31446995293 ps
CPU time 49.22 seconds
Started Aug 23 02:03:43 AM UTC 24
Finished Aug 23 02:04:33 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596156982 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3596156982
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/60.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.2115081347
Short name T438
Test name
Test status
Simulation time 42776261105 ps
CPU time 1349.38 seconds
Started Aug 23 02:04:06 AM UTC 24
Finished Aug 23 02:26:49 AM UTC 24
Peak memory 202484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115081347 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2115081347
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/61.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.2017365207
Short name T163
Test name
Test status
Simulation time 136556749397 ps
CPU time 488.55 seconds
Started Aug 23 02:04:25 AM UTC 24
Finished Aug 23 02:12:39 AM UTC 24
Peak memory 199844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017365207 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2017365207
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/62.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.1125857173
Short name T171
Test name
Test status
Simulation time 177807191580 ps
CPU time 92.22 seconds
Started Aug 23 02:04:34 AM UTC 24
Finished Aug 23 02:06:08 AM UTC 24
Peak memory 199668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125857173 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1125857173
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/63.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.29265140
Short name T218
Test name
Test status
Simulation time 138122787966 ps
CPU time 111.71 seconds
Started Aug 23 02:04:41 AM UTC 24
Finished Aug 23 02:06:35 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29265140 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.29265140
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/64.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.338914443
Short name T289
Test name
Test status
Simulation time 179978008971 ps
CPU time 177.83 seconds
Started Aug 23 02:04:52 AM UTC 24
Finished Aug 23 02:07:53 AM UTC 24
Peak memory 199804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338914443 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.338914443
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/66.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.138552597
Short name T270
Test name
Test status
Simulation time 154452540467 ps
CPU time 264.04 seconds
Started Aug 23 02:04:58 AM UTC 24
Finished Aug 23 02:09:26 AM UTC 24
Peak memory 199804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138552597 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.138552597
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/67.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.3804054060
Short name T254
Test name
Test status
Simulation time 443481894849 ps
CPU time 337.18 seconds
Started Aug 23 02:05:00 AM UTC 24
Finished Aug 23 02:10:42 AM UTC 24
Peak memory 199668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804054060 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3804054060
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/68.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.2411406421
Short name T204
Test name
Test status
Simulation time 225836488017 ps
CPU time 690.97 seconds
Started Aug 23 02:05:13 AM UTC 24
Finished Aug 23 02:16:52 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411406421 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2411406421
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/69.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.2335168184
Short name T125
Test name
Test status
Simulation time 95965281813 ps
CPU time 144.82 seconds
Started Aug 23 01:25:26 AM UTC 24
Finished Aug 23 01:27:53 AM UTC 24
Peak memory 199724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335168184 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.2335168184
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.872897577
Short name T373
Test name
Test status
Simulation time 94333943038 ps
CPU time 123.33 seconds
Started Aug 23 01:25:18 AM UTC 24
Finished Aug 23 01:27:23 AM UTC 24
Peak memory 199676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872897577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.872897577
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/7.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.3631497878
Short name T210
Test name
Test status
Simulation time 128915791965 ps
CPU time 1154.03 seconds
Started Aug 23 01:25:11 AM UTC 24
Finished Aug 23 01:44:37 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631497878 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3631497878
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/7.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.361980780
Short name T126
Test name
Test status
Simulation time 80478753592 ps
CPU time 31.32 seconds
Started Aug 23 01:25:29 AM UTC 24
Finished Aug 23 01:26:02 AM UTC 24
Peak memory 199688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361980780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST
_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.361980780
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/7.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.4028446399
Short name T431
Test name
Test status
Simulation time 64817822360 ps
CPU time 50.38 seconds
Started Aug 23 02:05:36 AM UTC 24
Finished Aug 23 02:06:28 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028446399 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4028446399
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/70.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.524509842
Short name T432
Test name
Test status
Simulation time 144218485147 ps
CPU time 60.55 seconds
Started Aug 23 02:06:08 AM UTC 24
Finished Aug 23 02:07:11 AM UTC 24
Peak memory 199740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524509842 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.524509842
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/71.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.2594231858
Short name T179
Test name
Test status
Simulation time 38830129896 ps
CPU time 128.05 seconds
Started Aug 23 02:06:13 AM UTC 24
Finished Aug 23 02:08:23 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594231858 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2594231858
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/72.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.3638050371
Short name T350
Test name
Test status
Simulation time 51025053064 ps
CPU time 70.27 seconds
Started Aug 23 02:06:22 AM UTC 24
Finished Aug 23 02:07:33 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638050371 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3638050371
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/73.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.1219170260
Short name T299
Test name
Test status
Simulation time 7848420775 ps
CPU time 10.71 seconds
Started Aug 23 02:06:29 AM UTC 24
Finished Aug 23 02:06:41 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219170260 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1219170260
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/74.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.3513774790
Short name T221
Test name
Test status
Simulation time 795770713282 ps
CPU time 365.14 seconds
Started Aug 23 02:06:36 AM UTC 24
Finished Aug 23 02:12:45 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513774790 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3513774790
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/75.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.1747668728
Short name T332
Test name
Test status
Simulation time 501287259017 ps
CPU time 416.08 seconds
Started Aug 23 02:06:42 AM UTC 24
Finished Aug 23 02:13:43 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747668728 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1747668728
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/76.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.968328983
Short name T312
Test name
Test status
Simulation time 11991215050 ps
CPU time 10.7 seconds
Started Aug 23 02:06:45 AM UTC 24
Finished Aug 23 02:06:57 AM UTC 24
Peak memory 199804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968328983 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.968328983
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/77.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.2590094075
Short name T264
Test name
Test status
Simulation time 16025179589 ps
CPU time 5 seconds
Started Aug 23 02:06:58 AM UTC 24
Finished Aug 23 02:07:04 AM UTC 24
Peak memory 199460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590094075 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2590094075
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/78.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.1998706497
Short name T75
Test name
Test status
Simulation time 597200537278 ps
CPU time 275.32 seconds
Started Aug 23 01:25:53 AM UTC 24
Finished Aug 23 01:30:32 AM UTC 24
Peak memory 199684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998706497 -assert nopostpr
oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.1998706497
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.3813346776
Short name T370
Test name
Test status
Simulation time 25546632310 ps
CPU time 22.08 seconds
Started Aug 23 01:25:47 AM UTC 24
Finished Aug 23 01:26:10 AM UTC 24
Peak memory 199872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813346776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3813346776
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/8.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.1820488970
Short name T78
Test name
Test status
Simulation time 846086584965 ps
CPU time 584.71 seconds
Started Aug 23 01:25:40 AM UTC 24
Finished Aug 23 01:35:31 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820488970 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1820488970
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/8.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.15364464
Short name T11
Test name
Test status
Simulation time 72598042102 ps
CPU time 198.59 seconds
Started Aug 23 01:26:10 AM UTC 24
Finished Aug 23 01:29:31 AM UTC 24
Peak memory 199668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15364464 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.15364464
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/8.rv_timer_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.2327910308
Short name T250
Test name
Test status
Simulation time 106153780353 ps
CPU time 171.15 seconds
Started Aug 23 02:07:11 AM UTC 24
Finished Aug 23 02:10:05 AM UTC 24
Peak memory 199704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327910308 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2327910308
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/81.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.1171845469
Short name T433
Test name
Test status
Simulation time 46831114712 ps
CPU time 69.79 seconds
Started Aug 23 02:07:31 AM UTC 24
Finished Aug 23 02:08:43 AM UTC 24
Peak memory 199804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171845469 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1171845469
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/82.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.1072220341
Short name T261
Test name
Test status
Simulation time 203066543581 ps
CPU time 1469.36 seconds
Started Aug 23 02:07:34 AM UTC 24
Finished Aug 23 02:32:18 AM UTC 24
Peak memory 202408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072220341 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1072220341
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/83.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.3744462760
Short name T283
Test name
Test status
Simulation time 986944733 ps
CPU time 1.6 seconds
Started Aug 23 02:07:53 AM UTC 24
Finished Aug 23 02:07:56 AM UTC 24
Peak memory 198872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744462760 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3744462760
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/84.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.1862238103
Short name T318
Test name
Test status
Simulation time 1450569424 ps
CPU time 1.63 seconds
Started Aug 23 02:07:56 AM UTC 24
Finished Aug 23 02:07:59 AM UTC 24
Peak memory 198872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862238103 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1862238103
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/85.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.1110842248
Short name T209
Test name
Test status
Simulation time 371705380454 ps
CPU time 183.36 seconds
Started Aug 23 02:07:59 AM UTC 24
Finished Aug 23 02:11:05 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110842248 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1110842248
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/86.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.3619962360
Short name T267
Test name
Test status
Simulation time 70498308245 ps
CPU time 566.82 seconds
Started Aug 23 02:08:23 AM UTC 24
Finished Aug 23 02:17:57 AM UTC 24
Peak memory 202412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619962360 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3619962360
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/87.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.1342375679
Short name T230
Test name
Test status
Simulation time 580997663282 ps
CPU time 393.04 seconds
Started Aug 23 02:08:43 AM UTC 24
Finished Aug 23 02:15:22 AM UTC 24
Peak memory 199808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342375679 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1342375679
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/88.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.910126643
Short name T214
Test name
Test status
Simulation time 87156134613 ps
CPU time 78.36 seconds
Started Aug 23 02:09:27 AM UTC 24
Finished Aug 23 02:10:47 AM UTC 24
Peak memory 199664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910126643 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.910126643
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/89.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.363375979
Short name T73
Test name
Test status
Simulation time 470759384335 ps
CPU time 229.93 seconds
Started Aug 23 01:26:32 AM UTC 24
Finished Aug 23 01:30:25 AM UTC 24
Peak memory 199588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363375979 -assert nopostpro
c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.363375979
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.2214072489
Short name T372
Test name
Test status
Simulation time 27042594167 ps
CPU time 33.8 seconds
Started Aug 23 01:26:11 AM UTC 24
Finished Aug 23 01:26:46 AM UTC 24
Peak memory 199844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214072489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES
T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2214072489
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/9.rv_timer_disabled/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.2357987
Short name T371
Test name
Test status
Simulation time 384455222 ps
CPU time 0.79 seconds
Started Aug 23 01:26:39 AM UTC 24
Finished Aug 23 01:26:41 AM UTC 24
Peak memory 198876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_S
EQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2357987
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/9.rv_timer_random_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.2661309314
Short name T258
Test name
Test status
Simulation time 385238184842 ps
CPU time 304.09 seconds
Started Aug 23 02:10:06 AM UTC 24
Finished Aug 23 02:15:14 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661309314 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2661309314
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/91.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.1208096424
Short name T347
Test name
Test status
Simulation time 91236712311 ps
CPU time 133.13 seconds
Started Aug 23 02:10:42 AM UTC 24
Finished Aug 23 02:12:57 AM UTC 24
Peak memory 199708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208096424 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1208096424
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/92.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.191314447
Short name T205
Test name
Test status
Simulation time 200208839820 ps
CPU time 1312.28 seconds
Started Aug 23 02:10:47 AM UTC 24
Finished Aug 23 02:32:53 AM UTC 24
Peak memory 202404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191314447 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.191314447
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/93.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.2030514930
Short name T306
Test name
Test status
Simulation time 419259043059 ps
CPU time 506.34 seconds
Started Aug 23 02:11:06 AM UTC 24
Finished Aug 23 02:19:39 AM UTC 24
Peak memory 199852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030514930 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2030514930
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/94.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.3719346011
Short name T251
Test name
Test status
Simulation time 83838820719 ps
CPU time 119.95 seconds
Started Aug 23 02:11:47 AM UTC 24
Finished Aug 23 02:13:49 AM UTC 24
Peak memory 199668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719346011 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3719346011
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/96.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.1747278765
Short name T249
Test name
Test status
Simulation time 66311725832 ps
CPU time 94.61 seconds
Started Aug 23 02:12:30 AM UTC 24
Finished Aug 23 02:14:06 AM UTC 24
Peak memory 199672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747278765 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1747278765
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/97.rv_timer_random/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.3427026183
Short name T259
Test name
Test status
Simulation time 350519283071 ps
CPU time 294.08 seconds
Started Aug 23 02:12:46 AM UTC 24
Finished Aug 23 02:17:43 AM UTC 24
Peak memory 199744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427026183 -assert nopostproc +UVM_TESTNAM
E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_22/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3427026183
Directory /workspaces/repo/scratch/os_regression_2024_08_22/rv_timer-sim-vcs/99.rv_timer_random/latest
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