Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.53	99.36	99.04	100.00		100.00	100.00	98.75

Total test records in report: 576

T55	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.712401558	Aug 25 01:41:17 AM UTC 24	Aug 25 01:41:19 AM UTC 24	12657370 ps
T505	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.1510709486	Aug 25 01:41:17 AM UTC 24	Aug 25 01:41:19 AM UTC 24	22394450 ps
T506	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3221711549	Aug 25 01:41:17 AM UTC 24	Aug 25 01:41:19 AM UTC 24	15219023 ps
T507	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2234722659	Aug 25 01:41:17 AM UTC 24	Aug 25 01:41:19 AM UTC 24	54924925 ps
T508	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.809684569	Aug 25 01:41:16 AM UTC 24	Aug 25 01:41:19 AM UTC 24	38441874 ps
T509	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.103141958	Aug 25 01:41:18 AM UTC 24	Aug 25 01:41:21 AM UTC 24	52234070 ps
T510	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.837358577	Aug 25 01:41:19 AM UTC 24	Aug 25 01:41:21 AM UTC 24	20949328 ps
T56	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.2871725009	Aug 25 01:41:19 AM UTC 24	Aug 25 01:41:21 AM UTC 24	50999131 ps
T511	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2282085483	Aug 25 01:41:18 AM UTC 24	Aug 25 01:41:21 AM UTC 24	383538899 ps
T512	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1566957871	Aug 25 01:41:19 AM UTC 24	Aug 25 01:41:21 AM UTC 24	32128061 ps
T513	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.612528548	Aug 25 01:41:19 AM UTC 24	Aug 25 01:41:21 AM UTC 24	32282657 ps
T514	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.305031612	Aug 25 01:41:19 AM UTC 24	Aug 25 01:41:22 AM UTC 24	39119085 ps
T515	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.2479624130	Aug 25 01:41:22 AM UTC 24	Aug 25 01:41:23 AM UTC 24	17601445 ps
T516	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1493632963	Aug 25 01:41:20 AM UTC 24	Aug 25 01:41:23 AM UTC 24	108877974 ps
T517	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.315206600	Aug 25 01:41:22 AM UTC 24	Aug 25 01:41:23 AM UTC 24	14585637 ps
T518	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2854721869	Aug 25 01:41:22 AM UTC 24	Aug 25 01:41:24 AM UTC 24	20775255 ps
T519	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2208446668	Aug 25 01:41:22 AM UTC 24	Aug 25 01:41:24 AM UTC 24	102514328 ps
T520	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3642286791	Aug 25 01:41:22 AM UTC 24	Aug 25 01:41:24 AM UTC 24	255933432 ps
T521	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.4127368220	Aug 25 01:41:23 AM UTC 24	Aug 25 01:41:25 AM UTC 24	71295984 ps
T522	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.2977092420	Aug 25 01:41:23 AM UTC 24	Aug 25 01:41:25 AM UTC 24	14649564 ps
T523	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.777522422	Aug 25 01:41:22 AM UTC 24	Aug 25 01:41:26 AM UTC 24	110746388 ps
T524	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1982202511	Aug 25 01:41:24 AM UTC 24	Aug 25 01:41:26 AM UTC 24	101833349 ps
T525	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.239965540	Aug 25 01:41:25 AM UTC 24	Aug 25 01:41:27 AM UTC 24	22014405 ps
T526	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.802006789	Aug 25 01:41:24 AM UTC 24	Aug 25 01:41:27 AM UTC 24	853477529 ps
T527	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.4010552254	Aug 25 01:41:25 AM UTC 24	Aug 25 01:41:27 AM UTC 24	12727532 ps
T528	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.132723747	Aug 25 01:41:24 AM UTC 24	Aug 25 01:41:27 AM UTC 24	42653510 ps
T529	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3945044584	Aug 25 01:41:26 AM UTC 24	Aug 25 01:41:27 AM UTC 24	16974239 ps
T530	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1536219165	Aug 25 01:41:25 AM UTC 24	Aug 25 01:41:28 AM UTC 24	116438142 ps
T531	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.2711991476	Aug 25 01:41:24 AM UTC 24	Aug 25 01:41:29 AM UTC 24	438696199 ps
T532	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.1174000260	Aug 25 01:41:27 AM UTC 24	Aug 25 01:41:29 AM UTC 24	25324025 ps
T533	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3978982725	Aug 25 01:41:27 AM UTC 24	Aug 25 01:41:30 AM UTC 24	878560470 ps
T534	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.1840837211	Aug 25 01:41:28 AM UTC 24	Aug 25 01:41:30 AM UTC 24	27495914 ps
T535	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.4153077069	Aug 25 01:41:28 AM UTC 24	Aug 25 01:41:30 AM UTC 24	16555794 ps
T58	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.439336720	Aug 25 01:41:28 AM UTC 24	Aug 25 01:41:30 AM UTC 24	147367313 ps
T536	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2138603913	Aug 25 01:41:28 AM UTC 24	Aug 25 01:41:30 AM UTC 24	54408791 ps
T537	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.2652853563	Aug 25 01:41:26 AM UTC 24	Aug 25 01:41:30 AM UTC 24	193521485 ps
T538	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.46808763	Aug 25 01:41:28 AM UTC 24	Aug 25 01:41:30 AM UTC 24	63848647 ps
T539	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3020140182	Aug 25 01:41:28 AM UTC 24	Aug 25 01:41:31 AM UTC 24	356857404 ps
T540	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3578016586	Aug 25 01:41:29 AM UTC 24	Aug 25 01:41:32 AM UTC 24	38457929 ps
T541	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.2385327156	Aug 25 01:41:28 AM UTC 24	Aug 25 01:41:32 AM UTC 24	186081606 ps
T542	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2516837298	Aug 25 01:41:29 AM UTC 24	Aug 25 01:41:32 AM UTC 24	90752370 ps
T543	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.890842105	Aug 25 01:41:31 AM UTC 24	Aug 25 01:41:33 AM UTC 24	17470168 ps
T544	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.1041142070	Aug 25 01:41:38 AM UTC 24	Aug 25 01:41:39 AM UTC 24	44022264 ps
T57	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.2386736476	Aug 25 01:41:31 AM UTC 24	Aug 25 01:41:33 AM UTC 24	20775274 ps
T545	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.4039272047	Aug 25 01:41:31 AM UTC 24	Aug 25 01:41:33 AM UTC 24	34452961 ps
T546	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2874552369	Aug 25 01:41:31 AM UTC 24	Aug 25 01:41:33 AM UTC 24	13623064 ps
T547	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1980639567	Aug 25 01:41:31 AM UTC 24	Aug 25 01:41:33 AM UTC 24	13771110 ps
T548	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3865884215	Aug 25 01:41:31 AM UTC 24	Aug 25 01:41:33 AM UTC 24	81128727 ps
T549	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.329161777	Aug 25 01:41:31 AM UTC 24	Aug 25 01:41:33 AM UTC 24	83757670 ps
T550	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.304155497	Aug 25 01:41:32 AM UTC 24	Aug 25 01:41:34 AM UTC 24	13812117 ps
T551	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.2336321733	Aug 25 01:41:32 AM UTC 24	Aug 25 01:41:34 AM UTC 24	17570849 ps
T552	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.2292607759	Aug 25 01:41:33 AM UTC 24	Aug 25 01:41:35 AM UTC 24	12357153 ps
T553	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.1058119253	Aug 25 01:41:33 AM UTC 24	Aug 25 01:41:35 AM UTC 24	45058143 ps
T554	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.2184873671	Aug 25 01:41:33 AM UTC 24	Aug 25 01:41:35 AM UTC 24	15379664 ps
T555	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.3740525306	Aug 25 01:41:29 AM UTC 24	Aug 25 01:41:35 AM UTC 24	283185181 ps
T556	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.2026076929	Aug 25 01:41:33 AM UTC 24	Aug 25 01:41:35 AM UTC 24	56570546 ps
T557	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.1141848450	Aug 25 01:41:33 AM UTC 24	Aug 25 01:41:35 AM UTC 24	47594597 ps
T558	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.2317377354	Aug 25 01:41:34 AM UTC 24	Aug 25 01:41:35 AM UTC 24	30660862 ps
T559	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.4007573354	Aug 25 01:41:34 AM UTC 24	Aug 25 01:41:35 AM UTC 24	39469709 ps
T560	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.903789733	Aug 25 01:41:35 AM UTC 24	Aug 25 01:41:37 AM UTC 24	15649324 ps
T561	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.25216467	Aug 25 01:41:35 AM UTC 24	Aug 25 01:41:37 AM UTC 24	14136733 ps
T562	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.3279009657	Aug 25 01:41:35 AM UTC 24	Aug 25 01:41:37 AM UTC 24	12978884 ps
T563	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.311204221	Aug 25 01:41:35 AM UTC 24	Aug 25 01:41:37 AM UTC 24	53582494 ps
T564	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.454768075	Aug 25 01:41:36 AM UTC 24	Aug 25 01:41:38 AM UTC 24	47360780 ps
T565	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.3486547318	Aug 25 01:41:36 AM UTC 24	Aug 25 01:41:38 AM UTC 24	22312332 ps
T566	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.3608646888	Aug 25 01:41:36 AM UTC 24	Aug 25 01:41:38 AM UTC 24	37385393 ps
T567	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.1423407326	Aug 25 01:41:36 AM UTC 24	Aug 25 01:41:38 AM UTC 24	33103652 ps
T568	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.3815368926	Aug 25 01:41:36 AM UTC 24	Aug 25 01:41:38 AM UTC 24	20790960 ps
T569	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.800453259	Aug 25 01:41:36 AM UTC 24	Aug 25 01:41:38 AM UTC 24	48892488 ps
T570	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.1505427977	Aug 25 01:41:36 AM UTC 24	Aug 25 01:41:38 AM UTC 24	18903223 ps
T571	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.3887397825	Aug 25 01:41:38 AM UTC 24	Aug 25 01:41:39 AM UTC 24	66453821 ps
T572	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.1597811219	Aug 25 01:41:38 AM UTC 24	Aug 25 01:41:39 AM UTC 24	28892278 ps
T573	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1909900990	Aug 25 01:41:38 AM UTC 24	Aug 25 01:41:39 AM UTC 24	61624888 ps
T574	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.4242907325	Aug 25 01:41:39 AM UTC 24	Aug 25 01:41:41 AM UTC 24	55121423 ps
T575	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.4180206203	Aug 25 01:41:39 AM UTC 24	Aug 25 01:41:41 AM UTC 24	12612670 ps
T576	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.3258106115	Aug 25 01:41:39 AM UTC 24	Aug 25 01:41:41 AM UTC 24	20227441 ps

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all_with_rand_reset.4176086511
Short name	T8
Test name
Test status
Simulation time	4466956586 ps
CPU time	10.01 seconds
Started	Aug 25 01:07:35 AM UTC 24
Finished	Aug 25 01:07:46 AM UTC 24
Peak memory	201980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4176086511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.rv_timer_stress_all_with_rand_reset.4176086511
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/28.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.260317538
Short name	T143
Test name
Test status
Simulation time	207455729018 ps
CPU time	151.38 seconds
Started	Aug 25 01:00:25 AM UTC 24
Finished	Aug 25 01:02:59 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260317538 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.260317538
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.194607180
Short name	T1
Test name
Test status
Simulation time	116564753 ps
CPU time	1.09 seconds
Started	Aug 25 01:00:23 AM UTC 24
Finished	Aug 25 01:00:26 AM UTC 24
Peak memory	231348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194607180 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.194607180
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.598488083
Short name	T122
Test name
Test status
Simulation time	144479340070 ps
CPU time	510.84 seconds
Started	Aug 25 01:00:33 AM UTC 24
Finished	Aug 25 01:09:10 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598488083 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.598488083
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.3245205199
Short name	T76
Test name
Test status
Simulation time	298060900045 ps
CPU time	1129.64 seconds
Started	Aug 25 01:01:54 AM UTC 24
Finished	Aug 25 01:20:57 AM UTC 24
Peak memory	202356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245205199 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.3245205199
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/10.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.85079516
Short name	T282
Test name
Test status
Simulation time	912342514801 ps
CPU time	3574.18 seconds
Started	Aug 25 01:12:51 AM UTC 24
Finished	Aug 25 02:13:09 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85079516 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.85079516
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/37.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.2535553815
Short name	T14
Test name
Test status
Simulation time	4800740017 ps
CPU time	21.48 seconds
Started	Aug 25 01:01:25 AM UTC 24
Finished	Aug 25 01:01:48 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535553815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2535553815
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/8.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.3459213809
Short name	T172
Test name
Test status
Simulation time	658404302716 ps
CPU time	7199.18 seconds
Started	Aug 25 01:17:34 AM UTC 24
Finished	Aug 25 03:18:57 AM UTC 24
Peak memory	202432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459213809 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.3459213809
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/45.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1036932732
Short name	T33
Test name
Test status
Simulation time	30922692 ps
CPU time	1.09 seconds
Started	Aug 25 01:40:35 AM UTC 24
Finished	Aug 25 01:40:37 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036932732 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.1036932732
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.833710203
Short name	T124
Test name
Test status
Simulation time	1655233686098 ps
CPU time	1004.11 seconds
Started	Aug 25 01:01:40 AM UTC 24
Finished	Aug 25 01:18:37 AM UTC 24
Peak memory	199848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833710203 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.833710203
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/9.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.2281322508
Short name	T261
Test name
Test status
Simulation time	513837517392 ps
CPU time	3419.46 seconds
Started	Aug 25 01:07:28 AM UTC 24
Finished	Aug 25 02:05:11 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281322508 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.2281322508
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/27.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.433127389
Short name	T331
Test name
Test status
Simulation time	521357796149 ps
CPU time	3061.59 seconds
Started	Aug 25 01:16:12 AM UTC 24
Finished	Aug 25 02:07:50 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433127389 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.433127389
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/43.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.846890052
Short name	T163
Test name
Test status
Simulation time	1048430927518 ps
CPU time	3677.62 seconds
Started	Aug 25 01:03:46 AM UTC 24
Finished	Aug 25 02:05:50 AM UTC 24
Peak memory	202584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846890052 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.846890052
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/17.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.3573393485
Short name	T263
Test name
Test status
Simulation time	220180318867 ps
CPU time	1156.41 seconds
Started	Aug 25 01:02:25 AM UTC 24
Finished	Aug 25 01:21:58 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573393485 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.3573393485
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/13.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.3364465615
Short name	T207
Test name
Test status
Simulation time	2121400131263 ps
CPU time	1751.49 seconds
Started	Aug 25 01:06:27 AM UTC 24
Finished	Aug 25 01:36:00 AM UTC 24
Peak memory	202416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364465615 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.3364465615
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/25.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1105977265
Short name	T69
Test name
Test status
Simulation time	463863073 ps
CPU time	2 seconds
Started	Aug 25 01:40:48 AM UTC 24
Finished	Aug 25 01:40:51 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105977265 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.1105977265
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.2245488424
Short name	T179
Test name
Test status
Simulation time	2855165953259 ps
CPU time	3061.14 seconds
Started	Aug 25 01:18:19 AM UTC 24
Finished	Aug 25 02:09:57 AM UTC 24
Peak memory	202452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245488424 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.2245488424
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/47.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.197416669
Short name	T348
Test name
Test status
Simulation time	1395447279617 ps
CPU time	3164.85 seconds
Started	Aug 25 01:05:43 AM UTC 24
Finished	Aug 25 01:59:09 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197416669 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.197416669
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/23.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.2427584743
Short name	T101
Test name
Test status
Simulation time	564370009636 ps
CPU time	609.43 seconds
Started	Aug 25 01:01:06 AM UTC 24
Finished	Aug 25 01:11:24 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427584743 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2427584743
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/7.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.2168543807
Short name	T260
Test name
Test status
Simulation time	663636340872 ps
CPU time	2519.68 seconds
Started	Aug 25 01:08:46 AM UTC 24
Finished	Aug 25 01:51:17 AM UTC 24
Peak memory	202416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168543807 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.2168543807
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/31.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.1685163818
Short name	T82
Test name
Test status
Simulation time	195338833548 ps
CPU time	306.85 seconds
Started	Aug 25 01:10:59 AM UTC 24
Finished	Aug 25 01:16:11 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685163818 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1685163818
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/36.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.1237047293
Short name	T90
Test name
Test status
Simulation time	107380297023 ps
CPU time	465.14 seconds
Started	Aug 25 01:09:19 AM UTC 24
Finished	Aug 25 01:17:10 AM UTC 24
Peak memory	199828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237047293 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1237047293
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/33.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.3095502698
Short name	T96
Test name
Test status
Simulation time	513339596414 ps
CPU time	503.22 seconds
Started	Aug 25 01:00:22 AM UTC 24
Finished	Aug 25 01:08:52 AM UTC 24
Peak memory	199684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095502698 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.3095502698
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.2874177686
Short name	T257
Test name
Test status
Simulation time	439245685434 ps
CPU time	833.06 seconds
Started	Aug 25 01:36:01 AM UTC 24
Finished	Aug 25 01:50:06 AM UTC 24
Peak memory	199868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874177686 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2874177686
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/167.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.987966042
Short name	T300
Test name
Test status
Simulation time	344819311661 ps
CPU time	1497.09 seconds
Started	Aug 25 01:38:41 AM UTC 24
Finished	Aug 25 02:03:59 AM UTC 24
Peak memory	202548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987966042 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.987966042
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/186.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.1662256259
Short name	T235
Test name
Test status
Simulation time	954456463030 ps
CPU time	899.92 seconds
Started	Aug 25 01:00:38 AM UTC 24
Finished	Aug 25 01:15:50 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662256259 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.1662256259
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.2418316009
Short name	T178
Test name
Test status
Simulation time	338176648395 ps
CPU time	2370.03 seconds
Started	Aug 25 01:14:36 AM UTC 24
Finished	Aug 25 01:54:35 AM UTC 24
Peak memory	202452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2418316009 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.2418316009
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/39.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.3963034510
Short name	T296
Test name
Test status
Simulation time	239376603483 ps
CPU time	390.14 seconds
Started	Aug 25 01:16:26 AM UTC 24
Finished	Aug 25 01:23:03 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963034510 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.3963034510
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.2164985361
Short name	T229
Test name
Test status
Simulation time	329492499181 ps
CPU time	335.63 seconds
Started	Aug 25 01:16:21 AM UTC 24
Finished	Aug 25 01:22:02 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164985361 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2164985361
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/44.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.1856305460
Short name	T108
Test name
Test status
Simulation time	67327405678 ps
CPU time	203.22 seconds
Started	Aug 25 01:00:23 AM UTC 24
Finished	Aug 25 01:03:50 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856305460 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1856305460
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.1838087828
Short name	T247
Test name
Test status
Simulation time	788260545489 ps
CPU time	2784.12 seconds
Started	Aug 25 01:02:11 AM UTC 24
Finished	Aug 25 01:49:06 AM UTC 24
Peak memory	202472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838087828 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.1838087828
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/12.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.3094360800
Short name	T164
Test name
Test status
Simulation time	467055724365 ps
CPU time	430.44 seconds
Started	Aug 25 01:36:49 AM UTC 24
Finished	Aug 25 01:44:05 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094360800 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3094360800
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/171.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.824305353
Short name	T318
Test name
Test status
Simulation time	536240364441 ps
CPU time	4107.91 seconds
Started	Aug 25 01:00:39 AM UTC 24
Finished	Aug 25 02:10:04 AM UTC 24
Peak memory	202356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824305353 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.824305353
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.2701571366
Short name	T194
Test name
Test status
Simulation time	129474129968 ps
CPU time	727.02 seconds
Started	Aug 25 01:21:54 AM UTC 24
Finished	Aug 25 01:34:11 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701571366 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2701571366
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/68.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.368579230
Short name	T214
Test name
Test status
Simulation time	238023146432 ps
CPU time	404.62 seconds
Started	Aug 25 01:23:38 AM UTC 24
Finished	Aug 25 01:30:29 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368579230 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.368579230
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/89.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.3192451432
Short name	T196
Test name
Test status
Simulation time	2063071082848 ps
CPU time	1947.57 seconds
Started	Aug 25 01:05:29 AM UTC 24
Finished	Aug 25 01:38:20 AM UTC 24
Peak memory	202360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192451432 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.3192451432
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/22.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.2794236203
Short name	T220
Test name
Test status
Simulation time	210928751408 ps
CPU time	895.37 seconds
Started	Aug 25 01:19:52 AM UTC 24
Finished	Aug 25 01:34:59 AM UTC 24
Peak memory	199872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794236203 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2794236203
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/53.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.4166821272
Short name	T347
Test name
Test status
Simulation time	733053612634 ps
CPU time	806.59 seconds
Started	Aug 25 01:28:34 AM UTC 24
Finished	Aug 25 01:42:11 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166821272 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.4166821272
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/116.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.748927844
Short name	T184
Test name
Test status
Simulation time	156586947157 ps
CPU time	676.41 seconds
Started	Aug 25 01:30:22 AM UTC 24
Finished	Aug 25 01:41:48 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748927844 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.748927844
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/122.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.115184769
Short name	T192
Test name
Test status
Simulation time	1012811877183 ps
CPU time	592.51 seconds
Started	Aug 25 01:30:31 AM UTC 24
Finished	Aug 25 01:40:31 AM UTC 24
Peak memory	199324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115184769 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.115184769
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/126.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.2776987796
Short name	T219
Test name
Test status
Simulation time	777730628979 ps
CPU time	1135.71 seconds
Started	Aug 25 01:31:39 AM UTC 24
Finished	Aug 25 01:50:50 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776987796 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2776987796
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/132.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.3891350892
Short name	T312
Test name
Test status
Simulation time	1129743868486 ps
CPU time	1140.1 seconds
Started	Aug 25 01:02:53 AM UTC 24
Finished	Aug 25 01:22:08 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891350892 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.3891350892
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.104173472
Short name	T355
Test name
Test status
Simulation time	218978194984 ps
CPU time	3345.66 seconds
Started	Aug 25 01:02:49 AM UTC 24
Finished	Aug 25 01:59:19 AM UTC 24
Peak memory	202548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104173472 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.104173472
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/15.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.1806646641
Short name	T239
Test name
Test status
Simulation time	346752519839 ps
CPU time	680.38 seconds
Started	Aug 25 01:09:49 AM UTC 24
Finished	Aug 25 01:21:20 AM UTC 24
Peak memory	199716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806646641 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1806646641
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/34.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.1262945948
Short name	T283
Test name
Test status
Simulation time	1387623342069 ps
CPU time	2035.35 seconds
Started	Aug 25 01:10:55 AM UTC 24
Finished	Aug 25 01:45:15 AM UTC 24
Peak memory	202356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262945948 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.1262945948
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/35.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.2953982531
Short name	T190
Test name
Test status
Simulation time	161584163062 ps
CPU time	506.46 seconds
Started	Aug 25 01:30:17 AM UTC 24
Finished	Aug 25 01:38:51 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953982531 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2953982531
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/120.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.2651045606
Short name	T317
Test name
Test status
Simulation time	685726997981 ps
CPU time	1503.26 seconds
Started	Aug 25 01:31:47 AM UTC 24
Finished	Aug 25 01:57:12 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651045606 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2651045606
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/134.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.525856442
Short name	T281
Test name
Test status
Simulation time	522161907502 ps
CPU time	491.11 seconds
Started	Aug 25 01:33:46 AM UTC 24
Finished	Aug 25 01:42:04 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525856442 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.525856442
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/148.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.2086255424
Short name	T181
Test name
Test status
Simulation time	128622810986 ps
CPU time	685.11 seconds
Started	Aug 25 01:34:01 AM UTC 24
Finished	Aug 25 01:45:35 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086255424 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2086255424
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/149.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.3010722706
Short name	T186
Test name
Test status
Simulation time	238937410589 ps
CPU time	212.96 seconds
Started	Aug 25 01:35:55 AM UTC 24
Finished	Aug 25 01:39:31 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010722706 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3010722706
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/165.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.2765700928
Short name	T249
Test name
Test status
Simulation time	194586620598 ps
CPU time	345.16 seconds
Started	Aug 25 01:38:21 AM UTC 24
Finished	Aug 25 01:44:11 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765700928 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2765700928
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/185.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.1402300083
Short name	T38
Test name
Test status
Simulation time	71011225633 ps
CPU time	204.54 seconds
Started	Aug 25 01:11:30 AM UTC 24
Finished	Aug 25 01:14:58 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402300083 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.1402300083
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/36.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.362980342
Short name	T273
Test name
Test status
Simulation time	100417035187 ps
CPU time	450.58 seconds
Started	Aug 25 01:23:08 AM UTC 24
Finished	Aug 25 01:30:45 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362980342 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.362980342
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/83.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.2495178760
Short name	T183
Test name
Test status
Simulation time	130773316228 ps
CPU time	436.35 seconds
Started	Aug 25 01:27:58 AM UTC 24
Finished	Aug 25 01:35:21 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495178760 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2495178760
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/113.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.58462516
Short name	T374
Test name
Test status
Simulation time	2227381794078 ps
CPU time	2714.21 seconds
Started	Aug 25 01:29:54 AM UTC 24
Finished	Aug 25 02:15:43 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58462516 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.58462516
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/118.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.797270385
Short name	T230
Test name
Test status
Simulation time	378167965355 ps
CPU time	2218.86 seconds
Started	Aug 25 01:02:13 AM UTC 24
Finished	Aug 25 01:39:39 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797270385 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.797270385
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/13.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.1761042684
Short name	T165
Test name
Test status
Simulation time	288421503113 ps
CPU time	883.12 seconds
Started	Aug 25 01:32:25 AM UTC 24
Finished	Aug 25 01:47:20 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761042684 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1761042684
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/138.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.1739331093
Short name	T339
Test name
Test status
Simulation time	104759686205 ps
CPU time	602.9 seconds
Started	Aug 25 01:34:12 AM UTC 24
Finished	Aug 25 01:44:24 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739331093 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1739331093
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/151.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.4237332722
Short name	T155
Test name
Test status
Simulation time	3161265657345 ps
CPU time	2266.56 seconds
Started	Aug 25 01:04:34 AM UTC 24
Finished	Aug 25 01:42:49 AM UTC 24
Peak memory	202484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237332722 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.4237332722
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/19.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.1047191889
Short name	T86
Test name
Test status
Simulation time	692046903176 ps
CPU time	324.73 seconds
Started	Aug 25 01:00:33 AM UTC 24
Finished	Aug 25 01:06:03 AM UTC 24
Peak memory	199732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047191889 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.1047191889
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.820960259
Short name	T245
Test name
Test status
Simulation time	520497283466 ps
CPU time	2081.42 seconds
Started	Aug 25 01:04:44 AM UTC 24
Finished	Aug 25 01:39:50 AM UTC 24
Peak memory	202584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820960259 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.820960259
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/20.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.1988550448
Short name	T252
Test name
Test status
Simulation time	233890375178 ps
CPU time	1297.96 seconds
Started	Aug 25 01:01:13 AM UTC 24
Finished	Aug 25 01:23:08 AM UTC 24
Peak memory	202348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988550448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1988550448
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/7.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.2863247146
Short name	T277
Test name
Test status
Simulation time	90714799943 ps
CPU time	476.37 seconds
Started	Aug 25 01:24:06 AM UTC 24
Finished	Aug 25 01:32:10 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863247146 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2863247146
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/93.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.1237709390
Short name	T237
Test name
Test status
Simulation time	115103378725 ps
CPU time	565.8 seconds
Started	Aug 25 01:24:59 AM UTC 24
Finished	Aug 25 01:34:33 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237709390 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1237709390
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/99.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.264113107
Short name	T44
Test name
Test status
Simulation time	76742269 ps
CPU time	1.13 seconds
Started	Aug 25 01:40:35 AM UTC 24
Finished	Aug 25 01:40:37 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264113107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.264113107
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.4240294889
Short name	T310
Test name
Test status
Simulation time	116127704383 ps
CPU time	325.7 seconds
Started	Aug 25 01:25:46 AM UTC 24
Finished	Aug 25 01:31:16 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240294889 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.4240294889
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/103.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.2933410921
Short name	T79
Test name
Test status
Simulation time	405867909361 ps
CPU time	709.32 seconds
Started	Aug 25 01:02:43 AM UTC 24
Finished	Aug 25 01:14:42 AM UTC 24
Peak memory	199576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933410921 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.2933410921
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.726931189
Short name	T304
Test name
Test status
Simulation time	90822175754 ps
CPU time	750.6 seconds
Started	Aug 25 01:33:32 AM UTC 24
Finished	Aug 25 01:46:14 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726931189 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.726931189
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/146.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.2021004275
Short name	T89
Test name
Test status
Simulation time	226264627227 ps
CPU time	725.93 seconds
Started	Aug 25 01:02:59 AM UTC 24
Finished	Aug 25 01:15:15 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021004275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2021004275
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/15.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.1601424341
Short name	T334
Test name
Test status
Simulation time	160592262866 ps
CPU time	814.85 seconds
Started	Aug 25 01:34:20 AM UTC 24
Finished	Aug 25 01:48:05 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601424341 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1601424341
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/152.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.4138362366
Short name	T180
Test name
Test status
Simulation time	497954173088 ps
CPU time	536.94 seconds
Started	Aug 25 01:34:34 AM UTC 24
Finished	Aug 25 01:43:39 AM UTC 24
Peak memory	199776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138362366 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.4138362366
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/154.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.3276737500
Short name	T191
Test name
Test status
Simulation time	123486520425 ps
CPU time	2200.5 seconds
Started	Aug 25 01:03:03 AM UTC 24
Finished	Aug 25 01:40:10 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276737500 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3276737500
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/16.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.3099983641
Short name	T271
Test name
Test status
Simulation time	664734459723 ps
CPU time	501.3 seconds
Started	Aug 25 01:37:52 AM UTC 24
Finished	Aug 25 01:46:21 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099983641 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3099983641
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/180.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.671294143
Short name	T213
Test name
Test status
Simulation time	644939223996 ps
CPU time	540.33 seconds
Started	Aug 25 01:08:49 AM UTC 24
Finished	Aug 25 01:17:56 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671294143 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.671294143
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/32.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.1069423759
Short name	T91
Test name
Test status
Simulation time	501882659593 ps
CPU time	461.87 seconds
Started	Aug 25 01:00:48 AM UTC 24
Finished	Aug 25 01:08:36 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069423759 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.1069423759
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.3726562582
Short name	T127
Test name
Test status
Simulation time	1218130987186 ps
CPU time	859.95 seconds
Started	Aug 25 01:00:55 AM UTC 24
Finished	Aug 25 01:15:25 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726562582 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.3726562582
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/5.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.3120101446
Short name	T268
Test name
Test status
Simulation time	141314089486 ps
CPU time	1045.32 seconds
Started	Aug 25 01:19:20 AM UTC 24
Finished	Aug 25 01:37:00 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120101446 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3120101446
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/52.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.2537814679
Short name	T189
Test name
Test status
Simulation time	129592954045 ps
CPU time	1075.26 seconds
Started	Aug 25 01:23:15 AM UTC 24
Finished	Aug 25 01:41:23 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537814679 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2537814679
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/85.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.305085718
Short name	T171
Test name
Test status
Simulation time	254851049600 ps
CPU time	834.86 seconds
Started	Aug 25 01:24:13 AM UTC 24
Finished	Aug 25 01:38:18 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305085718 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.305085718
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/95.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.91937668
Short name	T16
Test name
Test status
Simulation time	280624540 ps
CPU time	2.02 seconds
Started	Aug 25 01:40:29 AM UTC 24
Finished	Aug 25 01:40:32 AM UTC 24
Peak memory	200820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91937668 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.91937668
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.1503454842
Short name	T174
Test name
Test status
Simulation time	313991441148 ps
CPU time	534.14 seconds
Started	Aug 25 01:24:59 AM UTC 24
Finished	Aug 25 01:34:00 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503454842 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1503454842
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/100.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.202275710
Short name	T344
Test name
Test status
Simulation time	65969719571 ps
CPU time	1409.57 seconds
Started	Aug 25 01:26:52 AM UTC 24
Finished	Aug 25 01:50:40 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202275710 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.202275710
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/106.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.588850739
Short name	T73
Test name
Test status
Simulation time	100370886028 ps
CPU time	298.26 seconds
Started	Aug 25 01:01:55 AM UTC 24
Finished	Aug 25 01:06:58 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588850739 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.588850739
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/11.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.3176827668
Short name	T106
Test name
Test status
Simulation time	274585457299 ps
CPU time	333.19 seconds
Started	Aug 25 01:01:58 AM UTC 24
Finished	Aug 25 01:07:37 AM UTC 24
Peak memory	199788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176827668 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.3176827668
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/11.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.574679452
Short name	T187
Test name
Test status
Simulation time	119466569752 ps
CPU time	1268.37 seconds
Started	Aug 25 01:33:28 AM UTC 24
Finished	Aug 25 01:54:54 AM UTC 24
Peak memory	202520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574679452 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.574679452
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/145.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.692036973
Short name	T107
Test name
Test status
Simulation time	862376996345 ps
CPU time	631.98 seconds
Started	Aug 25 01:03:03 AM UTC 24
Finished	Aug 25 01:13:43 AM UTC 24
Peak memory	199812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692036973 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.692036973
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/15.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.1994284533
Short name	T341
Test name
Test status
Simulation time	524112122061 ps
CPU time	1697.05 seconds
Started	Aug 25 01:34:03 AM UTC 24
Finished	Aug 25 02:02:42 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994284533 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1994284533
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/150.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.3232368022
Short name	T292
Test name
Test status
Simulation time	395002299806 ps
CPU time	765.33 seconds
Started	Aug 25 01:34:34 AM UTC 24
Finished	Aug 25 01:47:30 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232368022 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3232368022
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/153.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.1938207680
Short name	T359
Test name
Test status
Simulation time	153464958993 ps
CPU time	748.19 seconds
Started	Aug 25 01:34:36 AM UTC 24
Finished	Aug 25 01:47:14 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938207680 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1938207680
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/155.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.2974607945
Short name	T255
Test name
Test status
Simulation time	196991036208 ps
CPU time	249.4 seconds
Started	Aug 25 01:35:22 AM UTC 24
Finished	Aug 25 01:39:35 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974607945 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2974607945
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/163.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.109964986
Short name	T156
Test name
Test status
Simulation time	115709189722 ps
CPU time	2532.78 seconds
Started	Aug 25 01:03:58 AM UTC 24
Finished	Aug 25 01:46:43 AM UTC 24
Peak memory	202548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109964986 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.109964986
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/19.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.2804225711
Short name	T110
Test name
Test status
Simulation time	10000875794 ps
CPU time	30.88 seconds
Started	Aug 25 01:04:50 AM UTC 24
Finished	Aug 25 01:05:23 AM UTC 24
Peak memory	199600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804225711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2804225711
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/21.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.2178731548
Short name	T379
Test name
Test status
Simulation time	78618895 ps
CPU time	1.41 seconds
Started	Aug 25 01:05:40 AM UTC 24
Finished	Aug 25 01:05:42 AM UTC 24
Peak memory	198992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178731548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2178731548
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/23.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.1795426904
Short name	T327
Test name
Test status
Simulation time	38031749437 ps
CPU time	1883.52 seconds
Started	Aug 25 01:08:37 AM UTC 24
Finished	Aug 25 01:40:26 AM UTC 24
Peak memory	202528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795426904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1795426904
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/31.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.3936138843
Short name	T120
Test name
Test status
Simulation time	89818246405 ps
CPU time	260.51 seconds
Started	Aug 25 01:11:18 AM UTC 24
Finished	Aug 25 01:15:43 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936138843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3936138843
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/36.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.2022093561
Short name	T195
Test name
Test status
Simulation time	28366510417 ps
CPU time	98.39 seconds
Started	Aug 25 01:20:41 AM UTC 24
Finished	Aug 25 01:22:22 AM UTC 24
Peak memory	199872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022093561 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2022093561
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/57.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.1537014943
Short name	T201
Test name
Test status
Simulation time	1645938374407 ps
CPU time	1565.54 seconds
Started	Aug 25 01:01:05 AM UTC 24
Finished	Aug 25 01:27:32 AM UTC 24
Peak memory	202444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537014943 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.1537014943
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/6.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.35537879
Short name	T35
Test name
Test status
Simulation time	1096813382 ps
CPU time	3.93 seconds
Started	Aug 25 01:40:33 AM UTC 24
Finished	Aug 25 01:40:38 AM UTC 24
Peak memory	200752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35537879 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.35537879
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.973112108
Short name	T19
Test name
Test status
Simulation time	94713002 ps
CPU time	0.81 seconds
Started	Aug 25 01:40:32 AM UTC 24
Finished	Aug 25 01:40:34 AM UTC 24
Peak memory	198848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973112108 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.973112108
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1728411406
Short name	T34
Test name
Test status
Simulation time	55762010 ps
CPU time	0.94 seconds
Started	Aug 25 01:40:36 AM UTC 24
Finished	Aug 25 01:40:38 AM UTC 24
Peak memory	198980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1728411406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_cs r_mem_rw_with_rand_reset.1728411406
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.2137857018
Short name	T20
Test name
Test status
Simulation time	17744790 ps
CPU time	0.83 seconds
Started	Aug 25 01:40:33 AM UTC 24
Finished	Aug 25 01:40:35 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137857018 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2137857018
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.1459629780
Short name	T452
Test name
Test status
Simulation time	16603781 ps
CPU time	0.84 seconds
Started	Aug 25 01:40:32 AM UTC 24
Finished	Aug 25 01:40:34 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459629780 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1459629780
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.2164280168
Short name	T32
Test name
Test status
Simulation time	596768531 ps
CPU time	4.51 seconds
Started	Aug 25 01:40:26 AM UTC 24
Finished	Aug 25 01:40:32 AM UTC 24
Peak memory	200744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164280168 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2164280168
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3290975955
Short name	T46
Test name
Test status
Simulation time	45966815 ps
CPU time	1.1 seconds
Started	Aug 25 01:40:41 AM UTC 24
Finished	Aug 25 01:40:43 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290975955 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.3290975955
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.229152394
Short name	T454
Test name
Test status
Simulation time	960558698 ps
CPU time	2.22 seconds
Started	Aug 25 01:40:40 AM UTC 24
Finished	Aug 25 01:40:43 AM UTC 24
Peak memory	200696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229152394 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.229152394
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4245821223
Short name	T45
Test name
Test status
Simulation time	34424251 ps
CPU time	0.85 seconds
Started	Aug 25 01:40:39 AM UTC 24
Finished	Aug 25 01:40:41 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245821223 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.4245821223
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1550617206
Short name	T455
Test name
Test status
Simulation time	40580361 ps
CPU time	1.17 seconds
Started	Aug 25 01:40:41 AM UTC 24
Finished	Aug 25 01:40:43 AM UTC 24
Peak memory	198980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1550617206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_cs r_mem_rw_with_rand_reset.1550617206
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.1278974818
Short name	T67
Test name
Test status
Simulation time	13428608 ps
CPU time	0.84 seconds
Started	Aug 25 01:40:39 AM UTC 24
Finished	Aug 25 01:40:41 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278974818 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1278974818
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.14891593
Short name	T453
Test name
Test status
Simulation time	17663411 ps
CPU time	0.86 seconds
Started	Aug 25 01:40:38 AM UTC 24
Finished	Aug 25 01:40:40 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14891593 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.14891593
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1256691824
Short name	T59
Test name
Test status
Simulation time	15439400 ps
CPU time	0.88 seconds
Started	Aug 25 01:40:41 AM UTC 24
Finished	Aug 25 01:40:43 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256691824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.1256691824
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.1712809766
Short name	T37
Test name
Test status
Simulation time	258740333 ps
CPU time	2.03 seconds
Started	Aug 25 01:40:38 AM UTC 24
Finished	Aug 25 01:40:41 AM UTC 24
Peak memory	200756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712809766 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1712809766
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3684755642
Short name	T17
Test name
Test status
Simulation time	162974828 ps
CPU time	2.08 seconds
Started	Aug 25 01:40:38 AM UTC 24
Finished	Aug 25 01:40:41 AM UTC 24
Peak memory	200752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684755642 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.3684755642
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.334120788
Short name	T497
Test name
Test status
Simulation time	30278140 ps
CPU time	1.17 seconds
Started	Aug 25 01:41:13 AM UTC 24
Finished	Aug 25 01:41:15 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=334120788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_cs r_mem_rw_with_rand_reset.334120788
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.232760352
Short name	T494
Test name
Test status
Simulation time	21565841 ps
CPU time	0.88 seconds
Started	Aug 25 01:41:12 AM UTC 24
Finished	Aug 25 01:41:14 AM UTC 24
Peak memory	198540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232760352 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.232760352
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.2134437397
Short name	T492
Test name
Test status
Simulation time	34984277 ps
CPU time	0.84 seconds
Started	Aug 25 01:41:12 AM UTC 24
Finished	Aug 25 01:41:14 AM UTC 24
Peak memory	198552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134437397 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2134437397
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/10.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.964855363
Short name	T496
Test name
Test status
Simulation time	112900031 ps
CPU time	1.01 seconds
Started	Aug 25 01:41:12 AM UTC 24
Finished	Aug 25 01:41:14 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964855363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.964855363
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.838139082
Short name	T493
Test name
Test status
Simulation time	84777247 ps
CPU time	2.76 seconds
Started	Aug 25 01:41:10 AM UTC 24
Finished	Aug 25 01:41:14 AM UTC 24
Peak memory	200688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838139082 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.838139082
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3515476227
Short name	T495
Test name
Test status
Simulation time	1033666782 ps
CPU time	2.1 seconds
Started	Aug 25 01:41:11 AM UTC 24
Finished	Aug 25 01:41:14 AM UTC 24
Peak memory	200948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515476227 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.3515476227
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3007291669
Short name	T503
Test name
Test status
Simulation time	142771802 ps
CPU time	2.27 seconds
Started	Aug 25 01:41:14 AM UTC 24
Finished	Aug 25 01:41:18 AM UTC 24
Peak memory	200820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3007291669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_c sr_mem_rw_with_rand_reset.3007291669
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.3372347022
Short name	T54
Test name
Test status
Simulation time	91470631 ps
CPU time	0.84 seconds
Started	Aug 25 01:41:14 AM UTC 24
Finished	Aug 25 01:41:16 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372347022 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3372347022
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.2388866794
Short name	T500
Test name
Test status
Simulation time	112343868 ps
CPU time	0.8 seconds
Started	Aug 25 01:41:14 AM UTC 24
Finished	Aug 25 01:41:16 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388866794 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2388866794
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/11.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2745016704
Short name	T501
Test name
Test status
Simulation time	80434935 ps
CPU time	0.94 seconds
Started	Aug 25 01:41:14 AM UTC 24
Finished	Aug 25 01:41:16 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745016704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.2745016704
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.837391572
Short name	T499
Test name
Test status
Simulation time	232363232 ps
CPU time	1.79 seconds
Started	Aug 25 01:41:13 AM UTC 24
Finished	Aug 25 01:41:16 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837391572 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.837391572
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1861504743
Short name	T502
Test name
Test status
Simulation time	69973968 ps
CPU time	1.58 seconds
Started	Aug 25 01:41:14 AM UTC 24
Finished	Aug 25 01:41:17 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861504743 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.1861504743
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2234722659
Short name	T507
Test name
Test status
Simulation time	54924925 ps
CPU time	0.93 seconds
Started	Aug 25 01:41:17 AM UTC 24
Finished	Aug 25 01:41:19 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2234722659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_c sr_mem_rw_with_rand_reset.2234722659
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.712401558
Short name	T55
Test name
Test status
Simulation time	12657370 ps
CPU time	0.83 seconds
Started	Aug 25 01:41:17 AM UTC 24
Finished	Aug 25 01:41:19 AM UTC 24
Peak memory	199004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712401558 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.712401558
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.1510709486
Short name	T505
Test name
Test status
Simulation time	22394450 ps
CPU time	0.82 seconds
Started	Aug 25 01:41:17 AM UTC 24
Finished	Aug 25 01:41:19 AM UTC 24
Peak memory	198784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510709486 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1510709486
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/12.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3221711549
Short name	T506
Test name
Test status
Simulation time	15219023 ps
CPU time	0.88 seconds
Started	Aug 25 01:41:17 AM UTC 24
Finished	Aug 25 01:41:19 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221711549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.3221711549
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.809684569
Short name	T508
Test name
Test status
Simulation time	38441874 ps
CPU time	2.42 seconds
Started	Aug 25 01:41:16 AM UTC 24
Finished	Aug 25 01:41:19 AM UTC 24
Peak memory	200680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809684569 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.809684569
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2422677124
Short name	T504
Test name
Test status
Simulation time	212312033 ps
CPU time	1.19 seconds
Started	Aug 25 01:41:16 AM UTC 24
Finished	Aug 25 01:41:18 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422677124 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.2422677124
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.612528548
Short name	T513
Test name
Test status
Simulation time	32282657 ps
CPU time	1.07 seconds
Started	Aug 25 01:41:19 AM UTC 24
Finished	Aug 25 01:41:21 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=612528548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_cs r_mem_rw_with_rand_reset.612528548
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.2871725009
Short name	T56
Test name
Test status
Simulation time	50999131 ps
CPU time	0.87 seconds
Started	Aug 25 01:41:19 AM UTC 24
Finished	Aug 25 01:41:21 AM UTC 24
Peak memory	199020 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871725009 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2871725009
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.837358577
Short name	T510
Test name
Test status
Simulation time	20949328 ps
CPU time	0.82 seconds
Started	Aug 25 01:41:19 AM UTC 24
Finished	Aug 25 01:41:21 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837358577 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.837358577
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/13.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1566957871
Short name	T512
Test name
Test status
Simulation time	32128061 ps
CPU time	1.04 seconds
Started	Aug 25 01:41:19 AM UTC 24
Finished	Aug 25 01:41:21 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566957871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.1566957871
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.103141958
Short name	T509
Test name
Test status
Simulation time	52234070 ps
CPU time	1.66 seconds
Started	Aug 25 01:41:18 AM UTC 24
Finished	Aug 25 01:41:21 AM UTC 24
Peak memory	199100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103141958 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.103141958
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2282085483
Short name	T511
Test name
Test status
Simulation time	383538899 ps
CPU time	2.01 seconds
Started	Aug 25 01:41:18 AM UTC 24
Finished	Aug 25 01:41:21 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282085483 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.2282085483
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2208446668
Short name	T519
Test name
Test status
Simulation time	102514328 ps
CPU time	1.14 seconds
Started	Aug 25 01:41:22 AM UTC 24
Finished	Aug 25 01:41:24 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2208446668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_c sr_mem_rw_with_rand_reset.2208446668
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.315206600
Short name	T517
Test name
Test status
Simulation time	14585637 ps
CPU time	0.84 seconds
Started	Aug 25 01:41:22 AM UTC 24
Finished	Aug 25 01:41:23 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315206600 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.315206600
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.2479624130
Short name	T515
Test name
Test status
Simulation time	17601445 ps
CPU time	0.84 seconds
Started	Aug 25 01:41:22 AM UTC 24
Finished	Aug 25 01:41:23 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479624130 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2479624130
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/14.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2854721869
Short name	T518
Test name
Test status
Simulation time	20775255 ps
CPU time	1.15 seconds
Started	Aug 25 01:41:22 AM UTC 24
Finished	Aug 25 01:41:24 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854721869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.2854721869
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.305031612
Short name	T514
Test name
Test status
Simulation time	39119085 ps
CPU time	1.93 seconds
Started	Aug 25 01:41:19 AM UTC 24
Finished	Aug 25 01:41:22 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305031612 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.305031612
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1493632963
Short name	T516
Test name
Test status
Simulation time	108877974 ps
CPU time	2.02 seconds
Started	Aug 25 01:41:20 AM UTC 24
Finished	Aug 25 01:41:23 AM UTC 24
Peak memory	200888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493632963 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.1493632963
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.132723747
Short name	T528
Test name
Test status
Simulation time	42653510 ps
CPU time	2.26 seconds
Started	Aug 25 01:41:24 AM UTC 24
Finished	Aug 25 01:41:27 AM UTC 24
Peak memory	200808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=132723747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_cs r_mem_rw_with_rand_reset.132723747
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.2977092420
Short name	T522
Test name
Test status
Simulation time	14649564 ps
CPU time	0.87 seconds
Started	Aug 25 01:41:23 AM UTC 24
Finished	Aug 25 01:41:25 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977092420 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2977092420
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.4127368220
Short name	T521
Test name
Test status
Simulation time	71295984 ps
CPU time	0.84 seconds
Started	Aug 25 01:41:23 AM UTC 24
Finished	Aug 25 01:41:25 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127368220 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.4127368220
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/15.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1982202511
Short name	T524
Test name
Test status
Simulation time	101833349 ps
CPU time	1.08 seconds
Started	Aug 25 01:41:24 AM UTC 24
Finished	Aug 25 01:41:26 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982202511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.1982202511
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.777522422
Short name	T523
Test name
Test status
Simulation time	110746388 ps
CPU time	3.21 seconds
Started	Aug 25 01:41:22 AM UTC 24
Finished	Aug 25 01:41:26 AM UTC 24
Peak memory	202728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777522422 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.777522422
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3642286791
Short name	T520
Test name
Test status
Simulation time	255933432 ps
CPU time	1.64 seconds
Started	Aug 25 01:41:22 AM UTC 24
Finished	Aug 25 01:41:24 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642286791 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.3642286791
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3945044584
Short name	T529
Test name
Test status
Simulation time	16974239 ps
CPU time	0.96 seconds
Started	Aug 25 01:41:26 AM UTC 24
Finished	Aug 25 01:41:27 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3945044584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_c sr_mem_rw_with_rand_reset.3945044584
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.4010552254
Short name	T527
Test name
Test status
Simulation time	12727532 ps
CPU time	0.81 seconds
Started	Aug 25 01:41:25 AM UTC 24
Finished	Aug 25 01:41:27 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010552254 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4010552254
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.239965540
Short name	T525
Test name
Test status
Simulation time	22014405 ps
CPU time	0.81 seconds
Started	Aug 25 01:41:25 AM UTC 24
Finished	Aug 25 01:41:27 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239965540 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.239965540
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/16.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1536219165
Short name	T530
Test name
Test status
Simulation time	116438142 ps
CPU time	1.17 seconds
Started	Aug 25 01:41:25 AM UTC 24
Finished	Aug 25 01:41:28 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536219165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.1536219165
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.2711991476
Short name	T531
Test name
Test status
Simulation time	438696199 ps
CPU time	3.37 seconds
Started	Aug 25 01:41:24 AM UTC 24
Finished	Aug 25 01:41:29 AM UTC 24
Peak memory	202724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711991476 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2711991476
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.802006789
Short name	T526
Test name
Test status
Simulation time	853477529 ps
CPU time	1.96 seconds
Started	Aug 25 01:41:24 AM UTC 24
Finished	Aug 25 01:41:27 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802006789 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.802006789
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.46808763
Short name	T538
Test name
Test status
Simulation time	63848647 ps
CPU time	1.19 seconds
Started	Aug 25 01:41:28 AM UTC 24
Finished	Aug 25 01:41:30 AM UTC 24
Peak memory	198980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=46808763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr _mem_rw_with_rand_reset.46808763
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.1840837211
Short name	T534
Test name
Test status
Simulation time	27495914 ps
CPU time	0.85 seconds
Started	Aug 25 01:41:28 AM UTC 24
Finished	Aug 25 01:41:30 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840837211 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1840837211
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.1174000260
Short name	T532
Test name
Test status
Simulation time	25324025 ps
CPU time	0.83 seconds
Started	Aug 25 01:41:27 AM UTC 24
Finished	Aug 25 01:41:29 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174000260 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1174000260
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/17.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2138603913
Short name	T536
Test name
Test status
Simulation time	54408791 ps
CPU time	1.06 seconds
Started	Aug 25 01:41:28 AM UTC 24
Finished	Aug 25 01:41:30 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138603913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.2138603913
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.2652853563
Short name	T537
Test name
Test status
Simulation time	193521485 ps
CPU time	3.58 seconds
Started	Aug 25 01:41:26 AM UTC 24
Finished	Aug 25 01:41:30 AM UTC 24
Peak memory	200676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652853563 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2652853563
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3978982725
Short name	T533
Test name
Test status
Simulation time	878560470 ps
CPU time	1.94 seconds
Started	Aug 25 01:41:27 AM UTC 24
Finished	Aug 25 01:41:30 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978982725 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.3978982725
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2516837298
Short name	T542
Test name
Test status
Simulation time	90752370 ps
CPU time	1.56 seconds
Started	Aug 25 01:41:29 AM UTC 24
Finished	Aug 25 01:41:32 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2516837298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_c sr_mem_rw_with_rand_reset.2516837298
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.439336720
Short name	T58
Test name
Test status
Simulation time	147367313 ps
CPU time	0.86 seconds
Started	Aug 25 01:41:28 AM UTC 24
Finished	Aug 25 01:41:30 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439336720 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.439336720
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.4153077069
Short name	T535
Test name
Test status
Simulation time	16555794 ps
CPU time	0.8 seconds
Started	Aug 25 01:41:28 AM UTC 24
Finished	Aug 25 01:41:30 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153077069 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.4153077069
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/18.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3578016586
Short name	T540
Test name
Test status
Simulation time	38457929 ps
CPU time	1.2 seconds
Started	Aug 25 01:41:29 AM UTC 24
Finished	Aug 25 01:41:32 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578016586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.3578016586
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.2385327156
Short name	T541
Test name
Test status
Simulation time	186081606 ps
CPU time	2.56 seconds
Started	Aug 25 01:41:28 AM UTC 24
Finished	Aug 25 01:41:32 AM UTC 24
Peak memory	202724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385327156 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2385327156
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3020140182
Short name	T539
Test name
Test status
Simulation time	356857404 ps
CPU time	1.98 seconds
Started	Aug 25 01:41:28 AM UTC 24
Finished	Aug 25 01:41:31 AM UTC 24
Peak memory	198848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020140182 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.3020140182
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3865884215
Short name	T548
Test name
Test status
Simulation time	81128727 ps
CPU time	1.51 seconds
Started	Aug 25 01:41:31 AM UTC 24
Finished	Aug 25 01:41:33 AM UTC 24
Peak memory	198868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3865884215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_c sr_mem_rw_with_rand_reset.3865884215
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.2386736476
Short name	T57
Test name
Test status
Simulation time	20775274 ps
CPU time	0.85 seconds
Started	Aug 25 01:41:31 AM UTC 24
Finished	Aug 25 01:41:33 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2386736476 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2386736476
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.890842105
Short name	T543
Test name
Test status
Simulation time	17470168 ps
CPU time	0.87 seconds
Started	Aug 25 01:41:31 AM UTC 24
Finished	Aug 25 01:41:33 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890842105 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.890842105
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/19.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2874552369
Short name	T546
Test name
Test status
Simulation time	13623064 ps
CPU time	0.91 seconds
Started	Aug 25 01:41:31 AM UTC 24
Finished	Aug 25 01:41:33 AM UTC 24
Peak memory	199004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874552369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.2874552369
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.3740525306
Short name	T555
Test name
Test status
Simulation time	283185181 ps
CPU time	4.76 seconds
Started	Aug 25 01:41:29 AM UTC 24
Finished	Aug 25 01:41:35 AM UTC 24
Peak memory	200876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740525306 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3740525306
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.329161777
Short name	T549
Test name
Test status
Simulation time	83757670 ps
CPU time	1.71 seconds
Started	Aug 25 01:41:31 AM UTC 24
Finished	Aug 25 01:41:33 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329161777 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.329161777
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2360124084
Short name	T458
Test name
Test status
Simulation time	28044481 ps
CPU time	1.09 seconds
Started	Aug 25 01:40:47 AM UTC 24
Finished	Aug 25 01:40:49 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360124084 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.2360124084
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1568064647
Short name	T49
Test name
Test status
Simulation time	543232108 ps
CPU time	5.59 seconds
Started	Aug 25 01:40:46 AM UTC 24
Finished	Aug 25 01:40:53 AM UTC 24
Peak memory	200820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568064647 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.1568064647
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4221640546
Short name	T68
Test name
Test status
Simulation time	46494794 ps
CPU time	0.86 seconds
Started	Aug 25 01:40:45 AM UTC 24
Finished	Aug 25 01:40:46 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221640546 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.4221640546
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2112509889
Short name	T459
Test name
Test status
Simulation time	23231812 ps
CPU time	1.06 seconds
Started	Aug 25 01:40:48 AM UTC 24
Finished	Aug 25 01:40:50 AM UTC 24
Peak memory	198980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2112509889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_cs r_mem_rw_with_rand_reset.2112509889
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.1419025322
Short name	T36
Test name
Test status
Simulation time	13740945 ps
CPU time	0.82 seconds
Started	Aug 25 01:40:45 AM UTC 24
Finished	Aug 25 01:40:46 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419025322 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1419025322
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.2046684714
Short name	T456
Test name
Test status
Simulation time	54836746 ps
CPU time	0.84 seconds
Started	Aug 25 01:40:45 AM UTC 24
Finished	Aug 25 01:40:46 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046684714 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2046684714
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2563205307
Short name	T47
Test name
Test status
Simulation time	13766860 ps
CPU time	0.92 seconds
Started	Aug 25 01:40:48 AM UTC 24
Finished	Aug 25 01:40:50 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563205307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.2563205307
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.2965103835
Short name	T457
Test name
Test status
Simulation time	684569244 ps
CPU time	4.54 seconds
Started	Aug 25 01:40:42 AM UTC 24
Finished	Aug 25 01:40:48 AM UTC 24
Peak memory	202720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965103835 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2965103835
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3918471171
Short name	T18
Test name
Test status
Simulation time	215920802 ps
CPU time	2.17 seconds
Started	Aug 25 01:40:43 AM UTC 24
Finished	Aug 25 01:40:47 AM UTC 24
Peak memory	200740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918471171 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.3918471171
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.4039272047
Short name	T545
Test name
Test status
Simulation time	34452961 ps
CPU time	0.79 seconds
Started	Aug 25 01:41:31 AM UTC 24
Finished	Aug 25 01:41:33 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039272047 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4039272047
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/20.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1980639567
Short name	T547
Test name
Test status
Simulation time	13771110 ps
CPU time	0.8 seconds
Started	Aug 25 01:41:31 AM UTC 24
Finished	Aug 25 01:41:33 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980639567 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1980639567
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/21.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.304155497
Short name	T550
Test name
Test status
Simulation time	13812117 ps
CPU time	0.81 seconds
Started	Aug 25 01:41:32 AM UTC 24
Finished	Aug 25 01:41:34 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304155497 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.304155497
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/22.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.2336321733
Short name	T551
Test name
Test status
Simulation time	17570849 ps
CPU time	0.79 seconds
Started	Aug 25 01:41:32 AM UTC 24
Finished	Aug 25 01:41:34 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336321733 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2336321733
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/23.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.1058119253
Short name	T553
Test name
Test status
Simulation time	45058143 ps
CPU time	0.84 seconds
Started	Aug 25 01:41:33 AM UTC 24
Finished	Aug 25 01:41:35 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058119253 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1058119253
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/24.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.2292607759
Short name	T552
Test name
Test status
Simulation time	12357153 ps
CPU time	0.81 seconds
Started	Aug 25 01:41:33 AM UTC 24
Finished	Aug 25 01:41:35 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292607759 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2292607759
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/25.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.2184873671
Short name	T554
Test name
Test status
Simulation time	15379664 ps
CPU time	0.85 seconds
Started	Aug 25 01:41:33 AM UTC 24
Finished	Aug 25 01:41:35 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184873671 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2184873671
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/26.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.2026076929
Short name	T556
Test name
Test status
Simulation time	56570546 ps
CPU time	0.83 seconds
Started	Aug 25 01:41:33 AM UTC 24
Finished	Aug 25 01:41:35 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026076929 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2026076929
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/27.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.1141848450
Short name	T557
Test name
Test status
Simulation time	47594597 ps
CPU time	0.82 seconds
Started	Aug 25 01:41:33 AM UTC 24
Finished	Aug 25 01:41:35 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141848450 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1141848450
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/28.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.2317377354
Short name	T558
Test name
Test status
Simulation time	30660862 ps
CPU time	0.8 seconds
Started	Aug 25 01:41:34 AM UTC 24
Finished	Aug 25 01:41:35 AM UTC 24
Peak memory	198964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317377354 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2317377354
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/29.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.4266867059
Short name	T51
Test name
Test status
Simulation time	14819645 ps
CPU time	0.96 seconds
Started	Aug 25 01:40:51 AM UTC 24
Finished	Aug 25 01:40:54 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266867059 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.4266867059
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3847878711
Short name	T463
Test name
Test status
Simulation time	184161235 ps
CPU time	2.27 seconds
Started	Aug 25 01:40:51 AM UTC 24
Finished	Aug 25 01:40:55 AM UTC 24
Peak memory	200664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847878711 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.3847878711
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3462269572
Short name	T48
Test name
Test status
Simulation time	59494887 ps
CPU time	0.89 seconds
Started	Aug 25 01:40:50 AM UTC 24
Finished	Aug 25 01:40:53 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462269572 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.3462269572
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4061606586
Short name	T462
Test name
Test status
Simulation time	27395644 ps
CPU time	1.73 seconds
Started	Aug 25 01:40:52 AM UTC 24
Finished	Aug 25 01:40:55 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4061606586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_cs r_mem_rw_with_rand_reset.4061606586
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.2911767243
Short name	T50
Test name
Test status
Simulation time	15955134 ps
CPU time	0.88 seconds
Started	Aug 25 01:40:51 AM UTC 24
Finished	Aug 25 01:40:54 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911767243 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2911767243
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.2787996808
Short name	T461
Test name
Test status
Simulation time	29986675 ps
CPU time	0.82 seconds
Started	Aug 25 01:40:49 AM UTC 24
Finished	Aug 25 01:40:51 AM UTC 24
Peak memory	198900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787996808 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2787996808
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2556064691
Short name	T60
Test name
Test status
Simulation time	376745836 ps
CPU time	1.23 seconds
Started	Aug 25 01:40:51 AM UTC 24
Finished	Aug 25 01:40:54 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556064691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.2556064691
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.2436178372
Short name	T460
Test name
Test status
Simulation time	193759616 ps
CPU time	1.84 seconds
Started	Aug 25 01:40:48 AM UTC 24
Finished	Aug 25 01:40:51 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436178372 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2436178372
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.4007573354
Short name	T559
Test name
Test status
Simulation time	39469709 ps
CPU time	0.81 seconds
Started	Aug 25 01:41:34 AM UTC 24
Finished	Aug 25 01:41:35 AM UTC 24
Peak memory	198960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007573354 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.4007573354
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/30.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.25216467
Short name	T561
Test name
Test status
Simulation time	14136733 ps
CPU time	0.84 seconds
Started	Aug 25 01:41:35 AM UTC 24
Finished	Aug 25 01:41:37 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25216467 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.25216467
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/31.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.903789733
Short name	T560
Test name
Test status
Simulation time	15649324 ps
CPU time	0.8 seconds
Started	Aug 25 01:41:35 AM UTC 24
Finished	Aug 25 01:41:37 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903789733 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.903789733
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/32.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.311204221
Short name	T563
Test name
Test status
Simulation time	53582494 ps
CPU time	0.85 seconds
Started	Aug 25 01:41:35 AM UTC 24
Finished	Aug 25 01:41:37 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311204221 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.311204221
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/33.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.3279009657
Short name	T562
Test name
Test status
Simulation time	12978884 ps
CPU time	0.79 seconds
Started	Aug 25 01:41:35 AM UTC 24
Finished	Aug 25 01:41:37 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279009657 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3279009657
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/34.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.454768075
Short name	T564
Test name
Test status
Simulation time	47360780 ps
CPU time	0.83 seconds
Started	Aug 25 01:41:36 AM UTC 24
Finished	Aug 25 01:41:38 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454768075 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.454768075
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/35.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.3486547318
Short name	T565
Test name
Test status
Simulation time	22312332 ps
CPU time	0.82 seconds
Started	Aug 25 01:41:36 AM UTC 24
Finished	Aug 25 01:41:38 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486547318 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3486547318
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/36.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.3608646888
Short name	T566
Test name
Test status
Simulation time	37385393 ps
CPU time	0.86 seconds
Started	Aug 25 01:41:36 AM UTC 24
Finished	Aug 25 01:41:38 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608646888 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3608646888
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/37.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.1423407326
Short name	T567
Test name
Test status
Simulation time	33103652 ps
CPU time	0.83 seconds
Started	Aug 25 01:41:36 AM UTC 24
Finished	Aug 25 01:41:38 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423407326 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1423407326
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/38.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.1505427977
Short name	T570
Test name
Test status
Simulation time	18903223 ps
CPU time	0.83 seconds
Started	Aug 25 01:41:36 AM UTC 24
Finished	Aug 25 01:41:38 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505427977 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1505427977
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/39.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.4105656908
Short name	T469
Test name
Test status
Simulation time	128659623 ps
CPU time	0.9 seconds
Started	Aug 25 01:40:56 AM UTC 24
Finished	Aug 25 01:40:58 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105656908 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.4105656908
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.740892307
Short name	T470
Test name
Test status
Simulation time	70846727 ps
CPU time	1.94 seconds
Started	Aug 25 01:40:55 AM UTC 24
Finished	Aug 25 01:40:58 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740892307 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.740892307
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.701815367
Short name	T466
Test name
Test status
Simulation time	43154115 ps
CPU time	0.86 seconds
Started	Aug 25 01:40:55 AM UTC 24
Finished	Aug 25 01:40:57 AM UTC 24
Peak memory	198856 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701815367 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.701815367
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3309930251
Short name	T472
Test name
Test status
Simulation time	74784515 ps
CPU time	2.78 seconds
Started	Aug 25 01:40:56 AM UTC 24
Finished	Aug 25 01:41:00 AM UTC 24
Peak memory	200948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3309930251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_cs r_mem_rw_with_rand_reset.3309930251
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.1117923176
Short name	T467
Test name
Test status
Simulation time	17600353 ps
CPU time	0.87 seconds
Started	Aug 25 01:40:55 AM UTC 24
Finished	Aug 25 01:40:57 AM UTC 24
Peak memory	198916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117923176 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1117923176
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.1215986137
Short name	T464
Test name
Test status
Simulation time	18204643 ps
CPU time	0.85 seconds
Started	Aug 25 01:40:54 AM UTC 24
Finished	Aug 25 01:40:56 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215986137 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1215986137
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.813519446
Short name	T61
Test name
Test status
Simulation time	28839243 ps
CPU time	1.09 seconds
Started	Aug 25 01:40:56 AM UTC 24
Finished	Aug 25 01:40:58 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813519446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.813519446
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.702498365
Short name	T468
Test name
Test status
Simulation time	458342378 ps
CPU time	3.25 seconds
Started	Aug 25 01:40:53 AM UTC 24
Finished	Aug 25 01:40:57 AM UTC 24
Peak memory	200676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702498365 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.702498365
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3610805105
Short name	T465
Test name
Test status
Simulation time	106347882 ps
CPU time	1.93 seconds
Started	Aug 25 01:40:54 AM UTC 24
Finished	Aug 25 01:40:57 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610805105 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.3610805105
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.3815368926
Short name	T568
Test name
Test status
Simulation time	20790960 ps
CPU time	0.8 seconds
Started	Aug 25 01:41:36 AM UTC 24
Finished	Aug 25 01:41:38 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815368926 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3815368926
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/40.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.800453259
Short name	T569
Test name
Test status
Simulation time	48892488 ps
CPU time	0.82 seconds
Started	Aug 25 01:41:36 AM UTC 24
Finished	Aug 25 01:41:38 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800453259 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.800453259
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/41.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.582032830
Short name	T498
Test name
Test status
Simulation time	51312844 ps
CPU time	0.85 seconds
Started	Aug 25 01:41:36 AM UTC 24
Finished	Aug 25 01:41:38 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582032830 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.582032830
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/42.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.1041142070
Short name	T544
Test name
Test status
Simulation time	44022264 ps
CPU time	0.79 seconds
Started	Aug 25 01:41:38 AM UTC 24
Finished	Aug 25 01:41:39 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041142070 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1041142070
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/43.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.3887397825
Short name	T571
Test name
Test status
Simulation time	66453821 ps
CPU time	0.81 seconds
Started	Aug 25 01:41:38 AM UTC 24
Finished	Aug 25 01:41:39 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887397825 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3887397825
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/44.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1909900990
Short name	T573
Test name
Test status
Simulation time	61624888 ps
CPU time	0.85 seconds
Started	Aug 25 01:41:38 AM UTC 24
Finished	Aug 25 01:41:39 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909900990 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1909900990
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/45.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.1597811219
Short name	T572
Test name
Test status
Simulation time	28892278 ps
CPU time	0.82 seconds
Started	Aug 25 01:41:38 AM UTC 24
Finished	Aug 25 01:41:39 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597811219 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1597811219
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/46.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.4242907325
Short name	T574
Test name
Test status
Simulation time	55121423 ps
CPU time	0.8 seconds
Started	Aug 25 01:41:39 AM UTC 24
Finished	Aug 25 01:41:41 AM UTC 24
Peak memory	198864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242907325 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.4242907325
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/47.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.4180206203
Short name	T575
Test name
Test status
Simulation time	12612670 ps
CPU time	0.83 seconds
Started	Aug 25 01:41:39 AM UTC 24
Finished	Aug 25 01:41:41 AM UTC 24
Peak memory	198872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180206203 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.4180206203
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/48.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.3258106115
Short name	T576
Test name
Test status
Simulation time	20227441 ps
CPU time	0.82 seconds
Started	Aug 25 01:41:39 AM UTC 24
Finished	Aug 25 01:41:41 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258106115 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3258106115
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/49.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2613051460
Short name	T474
Test name
Test status
Simulation time	115963166 ps
CPU time	1.91 seconds
Started	Aug 25 01:40:59 AM UTC 24
Finished	Aug 25 01:41:02 AM UTC 24
Peak memory	198980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2613051460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_cs r_mem_rw_with_rand_reset.2613051460
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.2714007213
Short name	T62
Test name
Test status
Simulation time	48876376 ps
CPU time	0.85 seconds
Started	Aug 25 01:40:59 AM UTC 24
Finished	Aug 25 01:41:01 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714007213 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2714007213
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.432690686
Short name	T471
Test name
Test status
Simulation time	10700316 ps
CPU time	0.79 seconds
Started	Aug 25 01:40:57 AM UTC 24
Finished	Aug 25 01:40:59 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432690686 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.432690686
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/5.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1314055792
Short name	T63
Test name
Test status
Simulation time	194282233 ps
CPU time	1.02 seconds
Started	Aug 25 01:40:59 AM UTC 24
Finished	Aug 25 01:41:01 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314055792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.1314055792
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.3665278835
Short name	T473
Test name
Test status
Simulation time	637643649 ps
CPU time	2.64 seconds
Started	Aug 25 01:40:57 AM UTC 24
Finished	Aug 25 01:41:01 AM UTC 24
Peak memory	200756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665278835 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3665278835
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1339184619
Short name	T70
Test name
Test status
Simulation time	1249362980 ps
CPU time	2.02 seconds
Started	Aug 25 01:40:57 AM UTC 24
Finished	Aug 25 01:41:00 AM UTC 24
Peak memory	200884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339184619 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.1339184619
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2161569869
Short name	T477
Test name
Test status
Simulation time	75805498 ps
CPU time	1.29 seconds
Started	Aug 25 01:41:01 AM UTC 24
Finished	Aug 25 01:41:04 AM UTC 24
Peak memory	198980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2161569869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_cs r_mem_rw_with_rand_reset.2161569869
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.2491679299
Short name	T52
Test name
Test status
Simulation time	36795455 ps
CPU time	0.82 seconds
Started	Aug 25 01:41:01 AM UTC 24
Finished	Aug 25 01:41:03 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491679299 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2491679299
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.2744326083
Short name	T476
Test name
Test status
Simulation time	84328354 ps
CPU time	0.8 seconds
Started	Aug 25 01:41:01 AM UTC 24
Finished	Aug 25 01:41:03 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744326083 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2744326083
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/6.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.46101995
Short name	T64
Test name
Test status
Simulation time	185337315 ps
CPU time	0.89 seconds
Started	Aug 25 01:41:01 AM UTC 24
Finished	Aug 25 01:41:03 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46101995 -assert nopostproc + UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.46101995
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.2699848400
Short name	T475
Test name
Test status
Simulation time	128233751 ps
CPU time	2.55 seconds
Started	Aug 25 01:40:59 AM UTC 24
Finished	Aug 25 01:41:02 AM UTC 24
Peak memory	200680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699848400 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2699848400
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1277580120
Short name	T71
Test name
Test status
Simulation time	93384831 ps
CPU time	1.89 seconds
Started	Aug 25 01:41:00 AM UTC 24
Finished	Aug 25 01:41:03 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277580120 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.1277580120
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.142818427
Short name	T481
Test name
Test status
Simulation time	24069200 ps
CPU time	1.06 seconds
Started	Aug 25 01:41:04 AM UTC 24
Finished	Aug 25 01:41:06 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=142818427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr _mem_rw_with_rand_reset.142818427
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.811624967
Short name	T480
Test name
Test status
Simulation time	38660480 ps
CPU time	0.84 seconds
Started	Aug 25 01:41:04 AM UTC 24
Finished	Aug 25 01:41:06 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811624967 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.811624967
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.3222750437
Short name	T479
Test name
Test status
Simulation time	13414759 ps
CPU time	0.84 seconds
Started	Aug 25 01:41:03 AM UTC 24
Finished	Aug 25 01:41:06 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222750437 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3222750437
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/7.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2982175496
Short name	T65
Test name
Test status
Simulation time	42744175 ps
CPU time	0.95 seconds
Started	Aug 25 01:41:04 AM UTC 24
Finished	Aug 25 01:41:06 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982175496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.2982175496
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.2878641328
Short name	T482
Test name
Test status
Simulation time	46784676 ps
CPU time	3.4 seconds
Started	Aug 25 01:41:02 AM UTC 24
Finished	Aug 25 01:41:07 AM UTC 24
Peak memory	202996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878641328 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2878641328
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2768856574
Short name	T478
Test name
Test status
Simulation time	771469331 ps
CPU time	1.82 seconds
Started	Aug 25 01:41:02 AM UTC 24
Finished	Aug 25 01:41:05 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768856574 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.2768856574
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3652111139
Short name	T486
Test name
Test status
Simulation time	92659088 ps
CPU time	2.17 seconds
Started	Aug 25 01:41:07 AM UTC 24
Finished	Aug 25 01:41:11 AM UTC 24
Peak memory	203124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3652111139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_cs r_mem_rw_with_rand_reset.3652111139
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.1201477292
Short name	T53
Test name
Test status
Simulation time	37313173 ps
CPU time	0.81 seconds
Started	Aug 25 01:41:06 AM UTC 24
Finished	Aug 25 01:41:08 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201477292 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1201477292
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.1214595060
Short name	T484
Test name
Test status
Simulation time	34130351 ps
CPU time	0.82 seconds
Started	Aug 25 01:41:06 AM UTC 24
Finished	Aug 25 01:41:08 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214595060 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1214595060
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/8.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.175876125
Short name	T66
Test name
Test status
Simulation time	46064483 ps
CPU time	1.21 seconds
Started	Aug 25 01:41:06 AM UTC 24
Finished	Aug 25 01:41:09 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175876125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.175876125
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.447456797
Short name	T485
Test name
Test status
Simulation time	120637506 ps
CPU time	3.26 seconds
Started	Aug 25 01:41:04 AM UTC 24
Finished	Aug 25 01:41:08 AM UTC 24
Peak memory	200680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447456797 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.447456797
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.459155880
Short name	T483
Test name
Test status
Simulation time	267100727 ps
CPU time	1.5 seconds
Started	Aug 25 01:41:05 AM UTC 24
Finished	Aug 25 01:41:07 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459155880 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.459155880
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.198448009
Short name	T491
Test name
Test status
Simulation time	31232583 ps
CPU time	1.96 seconds
Started	Aug 25 01:41:10 AM UTC 24
Finished	Aug 25 01:41:13 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=198448009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr _mem_rw_with_rand_reset.198448009
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.1697047547
Short name	T489
Test name
Test status
Simulation time	15164263 ps
CPU time	0.88 seconds
Started	Aug 25 01:41:09 AM UTC 24
Finished	Aug 25 01:41:12 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697047547 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1697047547
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.1717145025
Short name	T487
Test name
Test status
Simulation time	15337908 ps
CPU time	0.82 seconds
Started	Aug 25 01:41:08 AM UTC 24
Finished	Aug 25 01:41:11 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717145025 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1717145025
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/9.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1096085797
Short name	T490
Test name
Test status
Simulation time	120689295 ps
CPU time	1.07 seconds
Started	Aug 25 01:41:10 AM UTC 24
Finished	Aug 25 01:41:12 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096085797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.1096085797
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.3944929405
Short name	T488
Test name
Test status
Simulation time	87806056 ps
CPU time	3.03 seconds
Started	Aug 25 01:41:07 AM UTC 24
Finished	Aug 25 01:41:11 AM UTC 24
Peak memory	202728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944929405 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3944929405
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3003353319
Short name	T72
Test name
Test status
Simulation time	2295939905 ps
CPU time	1.97 seconds
Started	Aug 25 01:41:07 AM UTC 24
Finished	Aug 25 01:41:10 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003353319 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.3003353319
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.3000814699
Short name	T84
Test name
Test status
Simulation time	199053144911 ps
CPU time	639.02 seconds
Started	Aug 25 01:00:21 AM UTC 24
Finished	Aug 25 01:11:08 AM UTC 24
Peak memory	202332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000814699 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.3000814699
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.2815901620
Short name	T382
Test name
Test status
Simulation time	71934787568 ps
CPU time	104.74 seconds
Started	Aug 25 01:00:21 AM UTC 24
Finished	Aug 25 01:02:08 AM UTC 24
Peak memory	199852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815901620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2815901620
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.2899218895
Short name	T92
Test name
Test status
Simulation time	1848786729901 ps
CPU time	952.86 seconds
Started	Aug 25 01:00:20 AM UTC 24
Finished	Aug 25 01:16:25 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899218895 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2899218895
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.1956363378
Short name	T13
Test name
Test status
Simulation time	20856811142 ps
CPU time	66.38 seconds
Started	Aug 25 01:00:21 AM UTC 24
Finished	Aug 25 01:01:29 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956363378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1956363378
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/0.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.4129789267
Short name	T9
Test name
Test status
Simulation time	61988721495 ps
CPU time	45.61 seconds
Started	Aug 25 01:00:25 AM UTC 24
Finished	Aug 25 01:01:12 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129789267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.4129789267
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.1019031994
Short name	T130
Test name
Test status
Simulation time	98245398479 ps
CPU time	168.35 seconds
Started	Aug 25 01:00:25 AM UTC 24
Finished	Aug 25 01:03:16 AM UTC 24
Peak memory	199684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019031994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1019031994
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.4246010560
Short name	T2
Test name
Test status
Simulation time	225003361 ps
CPU time	1.19 seconds
Started	Aug 25 01:00:32 AM UTC 24
Finished	Aug 25 01:00:34 AM UTC 24
Peak memory	230928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246010560 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.4246010560
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.3585334570
Short name	T422
Test name
Test status
Simulation time	276959862265 ps
CPU time	839.34 seconds
Started	Aug 25 01:00:31 AM UTC 24
Finished	Aug 25 01:14:41 AM UTC 24
Peak memory	202348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585334570 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.3585334570
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/1.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.2771352688
Short name	T94
Test name
Test status
Simulation time	208212852222 ps
CPU time	482.98 seconds
Started	Aug 25 01:01:49 AM UTC 24
Finished	Aug 25 01:09:58 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771352688 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.2771352688
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.1537056620
Short name	T410
Test name
Test status
Simulation time	196214289254 ps
CPU time	446.56 seconds
Started	Aug 25 01:01:43 AM UTC 24
Finished	Aug 25 01:09:15 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537056620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1537056620
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/10.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.1098597365
Short name	T87
Test name
Test status
Simulation time	180357587689 ps
CPU time	405.93 seconds
Started	Aug 25 01:01:42 AM UTC 24
Finished	Aug 25 01:08:34 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098597365 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1098597365
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/10.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.3774841262
Short name	T22
Test name
Test status
Simulation time	81074687 ps
CPU time	0.91 seconds
Started	Aug 25 01:01:51 AM UTC 24
Finished	Aug 25 01:01:53 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774841262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3774841262
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/10.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.2897837737
Short name	T377
Test name
Test status
Simulation time	352747097 ps
CPU time	15.9 seconds
Started	Aug 25 01:25:08 AM UTC 24
Finished	Aug 25 01:25:25 AM UTC 24
Peak memory	199604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897837737 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2897837737
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/101.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.847444024
Short name	T323
Test name
Test status
Simulation time	2256318516183 ps
CPU time	898.89 seconds
Started	Aug 25 01:25:26 AM UTC 24
Finished	Aug 25 01:40:37 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847444024 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.847444024
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/102.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.3576828929
Short name	T346
Test name
Test status
Simulation time	512158265387 ps
CPU time	1343.49 seconds
Started	Aug 25 01:25:50 AM UTC 24
Finished	Aug 25 01:48:32 AM UTC 24
Peak memory	202480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576828929 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3576828929
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/104.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.3540837715
Short name	T211
Test name
Test status
Simulation time	118200979618 ps
CPU time	365 seconds
Started	Aug 25 01:26:44 AM UTC 24
Finished	Aug 25 01:32:54 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540837715 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3540837715
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/105.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.204791886
Short name	T248
Test name
Test status
Simulation time	93884928926 ps
CPU time	588.48 seconds
Started	Aug 25 01:27:15 AM UTC 24
Finished	Aug 25 01:37:11 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204791886 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.204791886
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/107.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.1196852114
Short name	T205
Test name
Test status
Simulation time	81601181397 ps
CPU time	262.1 seconds
Started	Aug 25 01:27:21 AM UTC 24
Finished	Aug 25 01:31:47 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196852114 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1196852114
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/108.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.3733262048
Short name	T259
Test name
Test status
Simulation time	516853756181 ps
CPU time	939.91 seconds
Started	Aug 25 01:27:26 AM UTC 24
Finished	Aug 25 01:43:18 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733262048 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3733262048
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/109.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.2049054854
Short name	T349
Test name
Test status
Simulation time	466971505357 ps
CPU time	1149.12 seconds
Started	Aug 25 01:01:57 AM UTC 24
Finished	Aug 25 01:21:19 AM UTC 24
Peak memory	199772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049054854 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.2049054854
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.2082359137
Short name	T383
Test name
Test status
Simulation time	16345849849 ps
CPU time	42.56 seconds
Started	Aug 25 01:01:55 AM UTC 24
Finished	Aug 25 01:02:39 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082359137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2082359137
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/11.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.1722861220
Short name	T381
Test name
Test status
Simulation time	580904004 ps
CPU time	2.68 seconds
Started	Aug 25 01:01:57 AM UTC 24
Finished	Aug 25 01:02:01 AM UTC 24
Peak memory	199600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722861220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1722861220
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/11.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.2634461229
Short name	T299
Test name
Test status
Simulation time	214514722937 ps
CPU time	274.05 seconds
Started	Aug 25 01:27:26 AM UTC 24
Finished	Aug 25 01:32:04 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634461229 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2634461229
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/110.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.343001289
Short name	T202
Test name
Test status
Simulation time	194056723640 ps
CPU time	179.06 seconds
Started	Aug 25 01:27:28 AM UTC 24
Finished	Aug 25 01:30:30 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343001289 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.343001289
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/111.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.371270461
Short name	T376
Test name
Test status
Simulation time	425633172576 ps
CPU time	834.73 seconds
Started	Aug 25 01:27:33 AM UTC 24
Finished	Aug 25 01:41:40 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371270461 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.371270461
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/112.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.2513020244
Short name	T216
Test name
Test status
Simulation time	850462107034 ps
CPU time	2006.27 seconds
Started	Aug 25 01:27:59 AM UTC 24
Finished	Aug 25 02:01:52 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513020244 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2513020244
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/114.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.1989555650
Short name	T362
Test name
Test status
Simulation time	311383580202 ps
CPU time	1003.71 seconds
Started	Aug 25 01:28:18 AM UTC 24
Finished	Aug 25 01:45:14 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989555650 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1989555650
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/115.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.1982980964
Short name	T358
Test name
Test status
Simulation time	57091661878 ps
CPU time	338.63 seconds
Started	Aug 25 01:29:09 AM UTC 24
Finished	Aug 25 01:34:53 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982980964 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1982980964
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/117.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.1048745828
Short name	T250
Test name
Test status
Simulation time	81178890644 ps
CPU time	231.82 seconds
Started	Aug 25 01:30:06 AM UTC 24
Finished	Aug 25 01:34:02 AM UTC 24
Peak memory	199608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048745828 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1048745828
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/119.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.3492503162
Short name	T391
Test name
Test status
Simulation time	317160342486 ps
CPU time	197.49 seconds
Started	Aug 25 01:02:02 AM UTC 24
Finished	Aug 25 01:05:23 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492503162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3492503162
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/12.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.365757586
Short name	T103
Test name
Test status
Simulation time	82589102336 ps
CPU time	435.27 seconds
Started	Aug 25 01:02:01 AM UTC 24
Finished	Aug 25 01:09:23 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365757586 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.365757586
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/12.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.3163238958
Short name	T125
Test name
Test status
Simulation time	23777169113 ps
CPU time	92.07 seconds
Started	Aug 25 01:02:09 AM UTC 24
Finished	Aug 25 01:03:43 AM UTC 24
Peak memory	199816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163238958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3163238958
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/12.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.3510336832
Short name	T280
Test name
Test status
Simulation time	396319199865 ps
CPU time	658.76 seconds
Started	Aug 25 01:30:19 AM UTC 24
Finished	Aug 25 01:41:27 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510336832 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3510336832
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/121.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.2954862952
Short name	T151
Test name
Test status
Simulation time	56473799332 ps
CPU time	181.74 seconds
Started	Aug 25 01:30:27 AM UTC 24
Finished	Aug 25 01:33:31 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954862952 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2954862952
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/123.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.3922732163
Short name	T369
Test name
Test status
Simulation time	1304379825558 ps
CPU time	710.43 seconds
Started	Aug 25 01:30:29 AM UTC 24
Finished	Aug 25 01:42:30 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922732163 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3922732163
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/124.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.3090908111
Short name	T298
Test name
Test status
Simulation time	321387370250 ps
CPU time	606.17 seconds
Started	Aug 25 01:30:30 AM UTC 24
Finished	Aug 25 01:40:44 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090908111 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3090908111
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/125.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.2504108704
Short name	T368
Test name
Test status
Simulation time	108914701057 ps
CPU time	434.67 seconds
Started	Aug 25 01:30:31 AM UTC 24
Finished	Aug 25 01:37:52 AM UTC 24
Peak memory	199364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504108704 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2504108704
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/127.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.579256000
Short name	T324
Test name
Test status
Simulation time	199195563405 ps
CPU time	129.73 seconds
Started	Aug 25 01:30:38 AM UTC 24
Finished	Aug 25 01:32:50 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579256000 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.579256000
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/128.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.4184593302
Short name	T309
Test name
Test status
Simulation time	244131204244 ps
CPU time	288.56 seconds
Started	Aug 25 01:30:46 AM UTC 24
Finished	Aug 25 01:35:39 AM UTC 24
Peak memory	199776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184593302 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4184593302
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/129.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.2367562398
Short name	T119
Test name
Test status
Simulation time	111904398316 ps
CPU time	382.61 seconds
Started	Aug 25 01:02:16 AM UTC 24
Finished	Aug 25 01:08:44 AM UTC 24
Peak memory	199848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367562398 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.2367562398
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.3364811315
Short name	T387
Test name
Test status
Simulation time	33767483730 ps
CPU time	89.47 seconds
Started	Aug 25 01:02:16 AM UTC 24
Finished	Aug 25 01:03:47 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364811315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3364811315
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/13.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.3918769336
Short name	T140
Test name
Test status
Simulation time	462515488752 ps
CPU time	406.49 seconds
Started	Aug 25 01:02:20 AM UTC 24
Finished	Aug 25 01:09:12 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918769336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3918769336
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/13.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.3688584487
Short name	T360
Test name
Test status
Simulation time	22141365972 ps
CPU time	78.03 seconds
Started	Aug 25 01:31:17 AM UTC 24
Finished	Aug 25 01:32:37 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688584487 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3688584487
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/130.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.1215402419
Short name	T170
Test name
Test status
Simulation time	89414758636 ps
CPU time	114.62 seconds
Started	Aug 25 01:31:30 AM UTC 24
Finished	Aug 25 01:33:27 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1215402419 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1215402419
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/131.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.1904839798
Short name	T326
Test name
Test status
Simulation time	145386558641 ps
CPU time	410.71 seconds
Started	Aug 25 01:31:45 AM UTC 24
Finished	Aug 25 01:38:41 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904839798 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1904839798
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/133.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.3191710237
Short name	T287
Test name
Test status
Simulation time	215910988274 ps
CPU time	645.83 seconds
Started	Aug 25 01:32:05 AM UTC 24
Finished	Aug 25 01:43:01 AM UTC 24
Peak memory	199904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191710237 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3191710237
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/135.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.3829478750
Short name	T238
Test name
Test status
Simulation time	82263333891 ps
CPU time	272.15 seconds
Started	Aug 25 01:32:11 AM UTC 24
Finished	Aug 25 01:36:47 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829478750 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3829478750
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/136.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.3411200200
Short name	T325
Test name
Test status
Simulation time	133447247532 ps
CPU time	221.46 seconds
Started	Aug 25 01:32:23 AM UTC 24
Finished	Aug 25 01:36:08 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411200200 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3411200200
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/137.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.4292341174
Short name	T294
Test name
Test status
Simulation time	120344581364 ps
CPU time	606.54 seconds
Started	Aug 25 01:32:32 AM UTC 24
Finished	Aug 25 01:42:47 AM UTC 24
Peak memory	199776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292341174 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.4292341174
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/139.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.968703659
Short name	T401
Test name
Test status
Simulation time	225675763530 ps
CPU time	238.69 seconds
Started	Aug 25 01:02:40 AM UTC 24
Finished	Aug 25 01:06:42 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968703659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.968703659
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/14.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.1122511525
Short name	T137
Test name
Test status
Simulation time	276363933555 ps
CPU time	139.25 seconds
Started	Aug 25 01:02:27 AM UTC 24
Finished	Aug 25 01:04:49 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122511525 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1122511525
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/14.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.2179699480
Short name	T149
Test name
Test status
Simulation time	45885190941 ps
CPU time	82.87 seconds
Started	Aug 25 01:02:43 AM UTC 24
Finished	Aug 25 01:04:08 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179699480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2179699480
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/14.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.1740752432
Short name	T40
Test name
Test status
Simulation time	1643406346501 ps
CPU time	875.38 seconds
Started	Aug 25 01:02:47 AM UTC 24
Finished	Aug 25 01:17:34 AM UTC 24
Peak memory	199616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740752432 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.1740752432
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/14.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.865772334
Short name	T328
Test name
Test status
Simulation time	471819830515 ps
CPU time	428.55 seconds
Started	Aug 25 01:32:38 AM UTC 24
Finished	Aug 25 01:39:53 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865772334 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.865772334
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/140.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.3385171124
Short name	T315
Test name
Test status
Simulation time	73830248520 ps
CPU time	120.55 seconds
Started	Aug 25 01:32:44 AM UTC 24
Finished	Aug 25 01:34:47 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385171124 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3385171124
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/141.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.2960816314
Short name	T199
Test name
Test status
Simulation time	240269343577 ps
CPU time	451.41 seconds
Started	Aug 25 01:32:51 AM UTC 24
Finished	Aug 25 01:40:29 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960816314 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2960816314
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/142.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.2667270693
Short name	T356
Test name
Test status
Simulation time	15329891304 ps
CPU time	11.89 seconds
Started	Aug 25 01:32:55 AM UTC 24
Finished	Aug 25 01:33:08 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667270693 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2667270693
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/143.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.134017405
Short name	T330
Test name
Test status
Simulation time	34895405149 ps
CPU time	33.74 seconds
Started	Aug 25 01:33:09 AM UTC 24
Finished	Aug 25 01:33:45 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134017405 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.134017405
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/144.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.4018264451
Short name	T350
Test name
Test status
Simulation time	62469696216 ps
CPU time	91.8 seconds
Started	Aug 25 01:33:35 AM UTC 24
Finished	Aug 25 01:35:08 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018264451 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.4018264451
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/147.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.2652351338
Short name	T412
Test name
Test status
Simulation time	556671539557 ps
CPU time	403.73 seconds
Started	Aug 25 01:02:52 AM UTC 24
Finished	Aug 25 01:09:42 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652351338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2652351338
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/15.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.145325581
Short name	T233
Test name
Test status
Simulation time	1460855053069 ps
CPU time	1746.01 seconds
Started	Aug 25 01:34:41 AM UTC 24
Finished	Aug 25 02:04:10 AM UTC 24
Peak memory	202548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145325581 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.145325581
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/156.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.2968442658
Short name	T270
Test name
Test status
Simulation time	185664306316 ps
CPU time	358.49 seconds
Started	Aug 25 01:34:47 AM UTC 24
Finished	Aug 25 01:40:50 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968442658 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2968442658
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/157.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.2791046464
Short name	T337
Test name
Test status
Simulation time	128964470203 ps
CPU time	403.22 seconds
Started	Aug 25 01:34:53 AM UTC 24
Finished	Aug 25 01:41:43 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791046464 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2791046464
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/158.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.3202558977
Short name	T371
Test name
Test status
Simulation time	39149561326 ps
CPU time	110.23 seconds
Started	Aug 25 01:34:59 AM UTC 24
Finished	Aug 25 01:36:52 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202558977 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3202558977
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/159.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.3860446979
Short name	T121
Test name
Test status
Simulation time	28373189391 ps
CPU time	36.62 seconds
Started	Aug 25 01:03:17 AM UTC 24
Finished	Aug 25 01:03:55 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860446979 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.3860446979
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.2459594767
Short name	T402
Test name
Test status
Simulation time	102157772904 ps
CPU time	255.62 seconds
Started	Aug 25 01:03:10 AM UTC 24
Finished	Aug 25 01:07:30 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459594767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2459594767
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/16.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.763802125
Short name	T386
Test name
Test status
Simulation time	298824278 ps
CPU time	1.29 seconds
Started	Aug 25 01:03:22 AM UTC 24
Finished	Aug 25 01:03:24 AM UTC 24
Peak memory	198936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763802125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.763802125
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/16.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.2692547499
Short name	T136
Test name
Test status
Simulation time	1100844933338 ps
CPU time	918.06 seconds
Started	Aug 25 01:03:36 AM UTC 24
Finished	Aug 25 01:19:05 AM UTC 24
Peak memory	199596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692547499 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.2692547499
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/16.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all_with_rand_reset.3052111430
Short name	T23
Test name
Test status
Simulation time	2747503621 ps
CPU time	30.6 seconds
Started	Aug 25 01:03:25 AM UTC 24
Finished	Aug 25 01:03:57 AM UTC 24
Peak memory	203964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3052111430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.rv_timer_stress_all_with_rand_reset.3052111430
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/16.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.1474733985
Short name	T365
Test name
Test status
Simulation time	36821404478 ps
CPU time	119.41 seconds
Started	Aug 25 01:35:04 AM UTC 24
Finished	Aug 25 01:37:05 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474733985 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1474733985
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/160.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.3532053758
Short name	T451
Test name
Test status
Simulation time	170052592439 ps
CPU time	2596.35 seconds
Started	Aug 25 01:35:10 AM UTC 24
Finished	Aug 25 02:19:00 AM UTC 24
Peak memory	202544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532053758 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3532053758
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/161.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.2676364164
Short name	T445
Test name
Test status
Simulation time	99787220588 ps
CPU time	162.06 seconds
Started	Aug 25 01:35:15 AM UTC 24
Finished	Aug 25 01:38:00 AM UTC 24
Peak memory	199456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676364164 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2676364164
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/162.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.2659226888
Short name	T159
Test name
Test status
Simulation time	30157461507 ps
CPU time	56.92 seconds
Started	Aug 25 01:35:40 AM UTC 24
Finished	Aug 25 01:36:39 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659226888 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2659226888
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/164.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.1187036712
Short name	T446
Test name
Test status
Simulation time	202722045302 ps
CPU time	203.06 seconds
Started	Aug 25 01:35:57 AM UTC 24
Finished	Aug 25 01:39:24 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187036712 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1187036712
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/166.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.4062730732
Short name	T284
Test name
Test status
Simulation time	64341860655 ps
CPU time	195.93 seconds
Started	Aug 25 01:36:08 AM UTC 24
Finished	Aug 25 01:39:28 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062730732 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4062730732
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/168.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.525855946
Short name	T228
Test name
Test status
Simulation time	335195318442 ps
CPU time	208.1 seconds
Started	Aug 25 01:36:39 AM UTC 24
Finished	Aug 25 01:40:11 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525855946 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.525855946
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/169.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.2154538124
Short name	T112
Test name
Test status
Simulation time	60399712999 ps
CPU time	193.68 seconds
Started	Aug 25 01:03:45 AM UTC 24
Finished	Aug 25 01:07:02 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154538124 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.2154538124
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.4197873981
Short name	T393
Test name
Test status
Simulation time	61079633198 ps
CPU time	120.63 seconds
Started	Aug 25 01:03:40 AM UTC 24
Finished	Aug 25 01:05:43 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197873981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.4197873981
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/17.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.748143581
Short name	T210
Test name
Test status
Simulation time	508009894160 ps
CPU time	2053.49 seconds
Started	Aug 25 01:03:39 AM UTC 24
Finished	Aug 25 01:38:19 AM UTC 24
Peak memory	202548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748143581 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.748143581
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/17.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.2364306658
Short name	T388
Test name
Test status
Simulation time	3629379260 ps
CPU time	6.46 seconds
Started	Aug 25 01:03:45 AM UTC 24
Finished	Aug 25 01:03:52 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364306658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2364306658
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/17.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.3339986780
Short name	T378
Test name
Test status
Simulation time	177127380529 ps
CPU time	441.12 seconds
Started	Aug 25 01:36:47 AM UTC 24
Finished	Aug 25 01:44:15 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339986780 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3339986780
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/170.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.2342100051
Short name	T197
Test name
Test status
Simulation time	362298897002 ps
CPU time	2381.61 seconds
Started	Aug 25 01:36:53 AM UTC 24
Finished	Aug 25 02:17:06 AM UTC 24
Peak memory	202480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342100051 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2342100051
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/172.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.989546633
Short name	T375
Test name
Test status
Simulation time	76274924388 ps
CPU time	356.52 seconds
Started	Aug 25 01:37:01 AM UTC 24
Finished	Aug 25 01:43:03 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989546633 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.989546633
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/173.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.2735217117
Short name	T361
Test name
Test status
Simulation time	91745030880 ps
CPU time	217.7 seconds
Started	Aug 25 01:37:06 AM UTC 24
Finished	Aug 25 01:40:47 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735217117 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2735217117
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/174.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.1651402357
Short name	T152
Test name
Test status
Simulation time	5438970649 ps
CPU time	21.18 seconds
Started	Aug 25 01:37:12 AM UTC 24
Finished	Aug 25 01:37:34 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651402357 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1651402357
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/175.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.542667194
Short name	T353
Test name
Test status
Simulation time	88063969455 ps
CPU time	513.76 seconds
Started	Aug 25 01:37:18 AM UTC 24
Finished	Aug 25 01:45:59 AM UTC 24
Peak memory	199684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542667194 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.542667194
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/176.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.3175164363
Short name	T329
Test name
Test status
Simulation time	125235623903 ps
CPU time	310.79 seconds
Started	Aug 25 01:37:29 AM UTC 24
Finished	Aug 25 01:42:45 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175164363 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3175164363
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/177.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.5208363
Short name	T352
Test name
Test status
Simulation time	235725626163 ps
CPU time	358.26 seconds
Started	Aug 25 01:37:34 AM UTC 24
Finished	Aug 25 01:43:38 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5208363 -assert nopostproc +UVM_TESTNAME=r v_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.5208363
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/178.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.3920988952
Short name	T215
Test name
Test status
Simulation time	1129370399149 ps
CPU time	1129.33 seconds
Started	Aug 25 01:37:35 AM UTC 24
Finished	Aug 25 01:56:40 AM UTC 24
Peak memory	202484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920988952 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3920988952
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/179.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.2408381302
Short name	T209
Test name
Test status
Simulation time	5410854832203 ps
CPU time	1996.24 seconds
Started	Aug 25 01:03:53 AM UTC 24
Finished	Aug 25 01:37:33 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408381302 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.2408381302
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.1617931113
Short name	T363
Test name
Test status
Simulation time	81912003093 ps
CPU time	1903.08 seconds
Started	Aug 25 01:03:48 AM UTC 24
Finished	Aug 25 01:35:54 AM UTC 24
Peak memory	202484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617931113 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1617931113
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/18.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.521805093
Short name	T115
Test name
Test status
Simulation time	46229160238 ps
CPU time	42.61 seconds
Started	Aug 25 01:03:54 AM UTC 24
Finished	Aug 25 01:04:38 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521805093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.521805093
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/18.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.2790971173
Short name	T182
Test name
Test status
Simulation time	307339189809 ps
CPU time	804.03 seconds
Started	Aug 25 01:03:57 AM UTC 24
Finished	Aug 25 01:17:31 AM UTC 24
Peak memory	199616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790971173 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.2790971173
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/18.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.2824742108
Short name	T275
Test name
Test status
Simulation time	76001766523 ps
CPU time	1450.67 seconds
Started	Aug 25 01:38:00 AM UTC 24
Finished	Aug 25 02:02:31 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824742108 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2824742108
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/181.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.3913930862
Short name	T251
Test name
Test status
Simulation time	23659354943 ps
CPU time	35.12 seconds
Started	Aug 25 01:38:04 AM UTC 24
Finished	Aug 25 01:38:40 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913930862 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3913930862
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/182.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.2196723914
Short name	T340
Test name
Test status
Simulation time	1354339102714 ps
CPU time	3175.7 seconds
Started	Aug 25 01:38:20 AM UTC 24
Finished	Aug 25 02:31:58 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196723914 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2196723914
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/183.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.3345258692
Short name	T357
Test name
Test status
Simulation time	132718619315 ps
CPU time	2232.36 seconds
Started	Aug 25 01:38:20 AM UTC 24
Finished	Aug 25 02:16:02 AM UTC 24
Peak memory	202544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345258692 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3345258692
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/184.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.17920793
Short name	T447
Test name
Test status
Simulation time	24658061145 ps
CPU time	91.39 seconds
Started	Aug 25 01:38:42 AM UTC 24
Finished	Aug 25 01:40:15 AM UTC 24
Peak memory	199776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17920793 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.17920793
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/187.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.2546648284
Short name	T224
Test name
Test status
Simulation time	3161840204 ps
CPU time	147.1 seconds
Started	Aug 25 01:38:51 AM UTC 24
Finished	Aug 25 01:41:21 AM UTC 24
Peak memory	199868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546648284 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2546648284
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/188.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.659209686
Short name	T313
Test name
Test status
Simulation time	105878880023 ps
CPU time	195.66 seconds
Started	Aug 25 01:39:24 AM UTC 24
Finished	Aug 25 01:42:43 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659209686 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.659209686
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/189.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.2370086825
Short name	T141
Test name
Test status
Simulation time	647320197811 ps
CPU time	625.26 seconds
Started	Aug 25 01:04:10 AM UTC 24
Finished	Aug 25 01:14:44 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370086825 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.2370086825
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.2733932121
Short name	T392
Test name
Test status
Simulation time	102281209163 ps
CPU time	86.01 seconds
Started	Aug 25 01:03:59 AM UTC 24
Finished	Aug 25 01:05:27 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733932121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2733932121
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/19.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.2200018905
Short name	T77
Test name
Test status
Simulation time	21469898143 ps
CPU time	81.35 seconds
Started	Aug 25 01:04:10 AM UTC 24
Finished	Aug 25 01:05:34 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200018905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2200018905
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/19.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all_with_rand_reset.2075456505
Short name	T24
Test name
Test status
Simulation time	1817689486 ps
CPU time	21.84 seconds
Started	Aug 25 01:04:24 AM UTC 24
Finished	Aug 25 01:04:48 AM UTC 24
Peak memory	203900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2075456505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.rv_timer_stress_all_with_rand_reset.2075456505
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/19.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.3321176316
Short name	T448
Test name
Test status
Simulation time	211792304457 ps
CPU time	173.11 seconds
Started	Aug 25 01:39:28 AM UTC 24
Finished	Aug 25 01:42:25 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321176316 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3321176316
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/190.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.421992335
Short name	T372
Test name
Test status
Simulation time	170566967011 ps
CPU time	286.1 seconds
Started	Aug 25 01:39:32 AM UTC 24
Finished	Aug 25 01:44:24 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421992335 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.421992335
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/191.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.762561910
Short name	T269
Test name
Test status
Simulation time	100426407394 ps
CPU time	313.17 seconds
Started	Aug 25 01:39:36 AM UTC 24
Finished	Aug 25 01:44:55 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762561910 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.762561910
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/192.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.1515737565
Short name	T366
Test name
Test status
Simulation time	65972325400 ps
CPU time	216.97 seconds
Started	Aug 25 01:39:40 AM UTC 24
Finished	Aug 25 01:43:21 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515737565 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1515737565
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/193.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.1490189720
Short name	T218
Test name
Test status
Simulation time	1033728553889 ps
CPU time	578.57 seconds
Started	Aug 25 01:39:51 AM UTC 24
Finished	Aug 25 01:49:37 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490189720 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1490189720
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/194.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.3500507142
Short name	T288
Test name
Test status
Simulation time	504842232944 ps
CPU time	450.03 seconds
Started	Aug 25 01:39:52 AM UTC 24
Finished	Aug 25 01:47:28 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500507142 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3500507142
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/195.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.546828187
Short name	T217
Test name
Test status
Simulation time	965365518495 ps
CPU time	479.89 seconds
Started	Aug 25 01:39:54 AM UTC 24
Finished	Aug 25 01:48:01 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546828187 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.546828187
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/196.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.137981485
Short name	T336
Test name
Test status
Simulation time	141118343135 ps
CPU time	592.25 seconds
Started	Aug 25 01:40:11 AM UTC 24
Finished	Aug 25 01:50:13 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137981485 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.137981485
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/197.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.1765612803
Short name	T162
Test name
Test status
Simulation time	486434462474 ps
CPU time	462.96 seconds
Started	Aug 25 01:40:12 AM UTC 24
Finished	Aug 25 01:48:01 AM UTC 24
Peak memory	199776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765612803 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1765612803
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/198.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.4197565276
Short name	T291
Test name
Test status
Simulation time	65244611230 ps
CPU time	226.76 seconds
Started	Aug 25 01:40:16 AM UTC 24
Finished	Aug 25 01:44:07 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197565276 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.4197565276
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/199.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.2051802242
Short name	T404
Test name
Test status
Simulation time	152301928359 ps
CPU time	432.97 seconds
Started	Aug 25 01:00:33 AM UTC 24
Finished	Aug 25 01:07:53 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051802242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2051802242
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.3321573834
Short name	T3
Test name
Test status
Simulation time	634173639 ps
CPU time	1.25 seconds
Started	Aug 25 01:00:34 AM UTC 24
Finished	Aug 25 01:00:37 AM UTC 24
Peak memory	198872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321573834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3321573834
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.2984767616
Short name	T4
Test name
Test status
Simulation time	64167150 ps
CPU time	1.04 seconds
Started	Aug 25 01:00:38 AM UTC 24
Finished	Aug 25 01:00:40 AM UTC 24
Peak memory	230928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984767616 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2984767616
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.2236909068
Short name	T243
Test name
Test status
Simulation time	1371195620486 ps
CPU time	1340.98 seconds
Started	Aug 25 01:04:36 AM UTC 24
Finished	Aug 25 01:27:14 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236909068 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.2236909068
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.2449354381
Short name	T396
Test name
Test status
Simulation time	126342257882 ps
CPU time	89.32 seconds
Started	Aug 25 01:04:36 AM UTC 24
Finished	Aug 25 01:06:08 AM UTC 24
Peak memory	199912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449354381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2449354381
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/20.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.3838728747
Short name	T118
Test name
Test status
Simulation time	184209292406 ps
CPU time	118.59 seconds
Started	Aug 25 01:04:36 AM UTC 24
Finished	Aug 25 01:06:37 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838728747 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3838728747
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/20.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.4172028437
Short name	T390
Test name
Test status
Simulation time	62603037 ps
CPU time	0.82 seconds
Started	Aug 25 01:04:40 AM UTC 24
Finished	Aug 25 01:04:42 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172028437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.4172028437
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/20.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all_with_rand_reset.3523128810
Short name	T25
Test name
Test status
Simulation time	1690826906 ps
CPU time	16.76 seconds
Started	Aug 25 01:04:40 AM UTC 24
Finished	Aug 25 01:04:58 AM UTC 24
Peak memory	201776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3523128810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.rv_timer_stress_all_with_rand_reset.3523128810
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/20.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.3731544122
Short name	T134
Test name
Test status
Simulation time	510317236036 ps
CPU time	642.4 seconds
Started	Aug 25 01:04:49 AM UTC 24
Finished	Aug 25 01:15:40 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731544122 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.3731544122
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.4049856116
Short name	T409
Test name
Test status
Simulation time	237264886569 ps
CPU time	254.09 seconds
Started	Aug 25 01:04:47 AM UTC 24
Finished	Aug 25 01:09:05 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049856116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.4049856116
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/21.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.3628752
Short name	T244
Test name
Test status
Simulation time	101173525491 ps
CPU time	847.43 seconds
Started	Aug 25 01:04:47 AM UTC 24
Finished	Aug 25 01:19:06 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628752 -assert nopostproc +UVM_TESTNAME=r v_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3628752
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/21.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.1573382953
Short name	T397
Test name
Test status
Simulation time	56482102747 ps
CPU time	75.88 seconds
Started	Aug 25 01:04:59 AM UTC 24
Finished	Aug 25 01:06:17 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573382953 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.1573382953
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/21.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.2616815146
Short name	T105
Test name
Test status
Simulation time	780670177729 ps
CPU time	528.33 seconds
Started	Aug 25 01:05:14 AM UTC 24
Finished	Aug 25 01:14:10 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616815146 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.2616815146
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.132002635
Short name	T413
Test name
Test status
Simulation time	93635490310 ps
CPU time	273.27 seconds
Started	Aug 25 01:05:11 AM UTC 24
Finished	Aug 25 01:09:48 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132002635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.132002635
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/22.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.3916833044
Short name	T154
Test name
Test status
Simulation time	159825157877 ps
CPU time	1328.04 seconds
Started	Aug 25 01:05:00 AM UTC 24
Finished	Aug 25 01:27:25 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916833044 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3916833044
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/22.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.2550352746
Short name	T114
Test name
Test status
Simulation time	230714480926 ps
CPU time	133.98 seconds
Started	Aug 25 01:05:23 AM UTC 24
Finished	Aug 25 01:07:40 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550352746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2550352746
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/22.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.119371278
Short name	T333
Test name
Test status
Simulation time	1574234814704 ps
CPU time	1284.79 seconds
Started	Aug 25 01:05:39 AM UTC 24
Finished	Aug 25 01:27:20 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119371278 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.119371278
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.1740279817
Short name	T415
Test name
Test status
Simulation time	179139157392 ps
CPU time	303.22 seconds
Started	Aug 25 01:05:39 AM UTC 24
Finished	Aug 25 01:10:46 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740279817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1740279817
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/23.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.1637289673
Short name	T74
Test name
Test status
Simulation time	146841813429 ps
CPU time	314.8 seconds
Started	Aug 25 01:05:35 AM UTC 24
Finished	Aug 25 01:10:54 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637289673 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1637289673
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/23.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.941835485
Short name	T146
Test name
Test status
Simulation time	240935907289 ps
CPU time	236.21 seconds
Started	Aug 25 01:05:58 AM UTC 24
Finished	Aug 25 01:09:58 AM UTC 24
Peak memory	199724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941835485 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.941835485
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.826669525
Short name	T400
Test name
Test status
Simulation time	45222125427 ps
CPU time	34.8 seconds
Started	Aug 25 01:05:54 AM UTC 24
Finished	Aug 25 01:06:31 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826669525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.826669525
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/24.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.3093606843
Short name	T126
Test name
Test status
Simulation time	43795451016 ps
CPU time	127.34 seconds
Started	Aug 25 01:05:49 AM UTC 24
Finished	Aug 25 01:07:59 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093606843 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3093606843
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/24.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.1534738315
Short name	T394
Test name
Test status
Simulation time	17654997 ps
CPU time	0.82 seconds
Started	Aug 25 01:06:00 AM UTC 24
Finished	Aug 25 01:06:02 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534738315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1534738315
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/24.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.3412683095
Short name	T395
Test name
Test status
Simulation time	131833291 ps
CPU time	0.78 seconds
Started	Aug 25 01:06:03 AM UTC 24
Finished	Aug 25 01:06:05 AM UTC 24
Peak memory	198880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412683095 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.3412683095
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/24.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.2668713319
Short name	T104
Test name
Test status
Simulation time	102940821475 ps
CPU time	319.96 seconds
Started	Aug 25 01:06:18 AM UTC 24
Finished	Aug 25 01:11:42 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668713319 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.2668713319
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.2930027793
Short name	T406
Test name
Test status
Simulation time	63536194080 ps
CPU time	109.1 seconds
Started	Aug 25 01:06:09 AM UTC 24
Finished	Aug 25 01:08:00 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930027793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2930027793
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/25.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.768848947
Short name	T113
Test name
Test status
Simulation time	84063835641 ps
CPU time	72.3 seconds
Started	Aug 25 01:06:06 AM UTC 24
Finished	Aug 25 01:07:20 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768848947 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.768848947
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/25.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.1928780135
Short name	T399
Test name
Test status
Simulation time	703346228 ps
CPU time	2.93 seconds
Started	Aug 25 01:06:22 AM UTC 24
Finished	Aug 25 01:06:26 AM UTC 24
Peak memory	199620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928780135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1928780135
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/25.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all_with_rand_reset.755490719
Short name	T26
Test name
Test status
Simulation time	5152134390 ps
CPU time	61.74 seconds
Started	Aug 25 01:06:26 AM UTC 24
Finished	Aug 25 01:07:30 AM UTC 24
Peak memory	204068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=755490719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.755490719
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/25.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.1302021742
Short name	T307
Test name
Test status
Simulation time	1534738846496 ps
CPU time	1597.42 seconds
Started	Aug 25 01:06:36 AM UTC 24
Finished	Aug 25 01:33:33 AM UTC 24
Peak memory	202452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302021742 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.1302021742
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.1798685994
Short name	T407
Test name
Test status
Simulation time	40020126428 ps
CPU time	104.42 seconds
Started	Aug 25 01:06:32 AM UTC 24
Finished	Aug 25 01:08:18 AM UTC 24
Peak memory	199848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798685994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1798685994
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/26.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.2234579199
Short name	T78
Test name
Test status
Simulation time	238573744793 ps
CPU time	449.04 seconds
Started	Aug 25 01:06:30 AM UTC 24
Finished	Aug 25 01:14:06 AM UTC 24
Peak memory	199908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234579199 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2234579199
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/26.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.1380521332
Short name	T95
Test name
Test status
Simulation time	125125488231 ps
CPU time	73.09 seconds
Started	Aug 25 01:06:38 AM UTC 24
Finished	Aug 25 01:07:54 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380521332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1380521332
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/26.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.401077884
Short name	T98
Test name
Test status
Simulation time	524573955366 ps
CPU time	865.89 seconds
Started	Aug 25 01:06:43 AM UTC 24
Finished	Aug 25 01:21:19 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401077884 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.401077884
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/26.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.4053116128
Short name	T142
Test name
Test status
Simulation time	86581578950 ps
CPU time	44.86 seconds
Started	Aug 25 01:07:19 AM UTC 24
Finished	Aug 25 01:08:05 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053116128 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.4053116128
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.1396425916
Short name	T420
Test name
Test status
Simulation time	339014794789 ps
CPU time	403.51 seconds
Started	Aug 25 01:07:02 AM UTC 24
Finished	Aug 25 01:13:51 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396425916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1396425916
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/27.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.383613235
Short name	T254
Test name
Test status
Simulation time	346454789105 ps
CPU time	1277.23 seconds
Started	Aug 25 01:06:58 AM UTC 24
Finished	Aug 25 01:28:33 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383613235 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.383613235
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/27.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.2257531837
Short name	T306
Test name
Test status
Simulation time	174980582125 ps
CPU time	2022.01 seconds
Started	Aug 25 01:07:21 AM UTC 24
Finished	Aug 25 01:41:28 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257531837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2257531837
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/27.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.3442580813
Short name	T276
Test name
Test status
Simulation time	649803395936 ps
CPU time	1086.85 seconds
Started	Aug 25 01:07:30 AM UTC 24
Finished	Aug 25 01:25:50 AM UTC 24
Peak memory	199848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442580813 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.3442580813
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.1687516740
Short name	T417
Test name
Test status
Simulation time	83755182504 ps
CPU time	235.19 seconds
Started	Aug 25 01:07:30 AM UTC 24
Finished	Aug 25 01:11:29 AM UTC 24
Peak memory	199716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687516740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1687516740
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/28.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.2876619072
Short name	T145
Test name
Test status
Simulation time	45472976845 ps
CPU time	109.96 seconds
Started	Aug 25 01:07:29 AM UTC 24
Finished	Aug 25 01:09:22 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876619072 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2876619072
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/28.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.2890030179
Short name	T403
Test name
Test status
Simulation time	54101768 ps
CPU time	1 seconds
Started	Aug 25 01:07:32 AM UTC 24
Finished	Aug 25 01:07:34 AM UTC 24
Peak memory	198872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890030179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2890030179
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/28.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.1315711396
Short name	T43
Test name
Test status
Simulation time	395762278976 ps
CPU time	1274.51 seconds
Started	Aug 25 01:07:38 AM UTC 24
Finished	Aug 25 01:29:08 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315711396 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.1315711396
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/28.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.438681733
Short name	T99
Test name
Test status
Simulation time	933322336298 ps
CPU time	869.98 seconds
Started	Aug 25 01:07:47 AM UTC 24
Finished	Aug 25 01:22:29 AM UTC 24
Peak memory	199724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438681733 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.438681733
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.2656024183
Short name	T144
Test name
Test status
Simulation time	6766391667 ps
CPU time	19.75 seconds
Started	Aug 25 01:07:41 AM UTC 24
Finished	Aug 25 01:08:02 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656024183 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2656024183
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/29.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.1862719101
Short name	T405
Test name
Test status
Simulation time	1000518755 ps
CPU time	1.83 seconds
Started	Aug 25 01:07:54 AM UTC 24
Finished	Aug 25 01:07:57 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862719101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1862719101
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/29.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.3680537188
Short name	T41
Test name
Test status
Simulation time	586383917974 ps
CPU time	898.53 seconds
Started	Aug 25 01:07:57 AM UTC 24
Finished	Aug 25 01:23:08 AM UTC 24
Peak memory	199788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680537188 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.3680537188
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/29.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all_with_rand_reset.832996942
Short name	T27
Test name
Test status
Simulation time	3118182950 ps
CPU time	28.85 seconds
Started	Aug 25 01:07:55 AM UTC 24
Finished	Aug 25 01:08:25 AM UTC 24
Peak memory	203928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=832996942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.832996942
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/29.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.3744645298
Short name	T128
Test name
Test status
Simulation time	1196054998744 ps
CPU time	1019.93 seconds
Started	Aug 25 01:00:39 AM UTC 24
Finished	Aug 25 01:17:52 AM UTC 24
Peak memory	202592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744645298 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.3744645298
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.4042409219
Short name	T384
Test name
Test status
Simulation time	433804884234 ps
CPU time	131.63 seconds
Started	Aug 25 01:00:38 AM UTC 24
Finished	Aug 25 01:02:52 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042409219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.4042409219
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.501004274
Short name	T109
Test name
Test status
Simulation time	147217700226 ps
CPU time	234.06 seconds
Started	Aug 25 01:00:38 AM UTC 24
Finished	Aug 25 01:04:36 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501004274 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.501004274
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.336427632
Short name	T15
Test name
Test status
Simulation time	102783280317 ps
CPU time	75.75 seconds
Started	Aug 25 01:00:39 AM UTC 24
Finished	Aug 25 01:01:57 AM UTC 24
Peak memory	199620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336427632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.336427632
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.383018357
Short name	T5
Test name
Test status
Simulation time	170185970 ps
CPU time	1.29 seconds
Started	Aug 25 01:00:40 AM UTC 24
Finished	Aug 25 01:00:43 AM UTC 24
Peak memory	230888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383018357 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.383018357
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.812892338
Short name	T129
Test name
Test status
Simulation time	128479020544 ps
CPU time	368.29 seconds
Started	Aug 25 01:08:03 AM UTC 24
Finished	Aug 25 01:14:17 AM UTC 24
Peak memory	199660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812892338 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.812892338
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.1553945942
Short name	T423
Test name
Test status
Simulation time	336774150503 ps
CPU time	412.7 seconds
Started	Aug 25 01:08:01 AM UTC 24
Finished	Aug 25 01:14:59 AM UTC 24
Peak memory	199812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553945942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1553945942
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/30.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.3767305632
Short name	T289
Test name
Test status
Simulation time	162322005487 ps
CPU time	750.41 seconds
Started	Aug 25 01:08:00 AM UTC 24
Finished	Aug 25 01:20:41 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767305632 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3767305632
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/30.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.759685468
Short name	T88
Test name
Test status
Simulation time	101050524165 ps
CPU time	189.32 seconds
Started	Aug 25 01:08:05 AM UTC 24
Finished	Aug 25 01:11:18 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759685468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.759685468
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/30.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.2975324180
Short name	T222
Test name
Test status
Simulation time	421773348202 ps
CPU time	1181.64 seconds
Started	Aug 25 01:08:22 AM UTC 24
Finished	Aug 25 01:28:17 AM UTC 24
Peak memory	199716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975324180 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.2975324180
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/30.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all_with_rand_reset.2282413076
Short name	T28
Test name
Test status
Simulation time	2035008268 ps
CPU time	24.6 seconds
Started	Aug 25 01:08:20 AM UTC 24
Finished	Aug 25 01:08:45 AM UTC 24
Peak memory	201776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2282413076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 30.rv_timer_stress_all_with_rand_reset.2282413076
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/30.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.1040575419
Short name	T311
Test name
Test status
Simulation time	1083321413492 ps
CPU time	969.22 seconds
Started	Aug 25 01:08:36 AM UTC 24
Finished	Aug 25 01:24:58 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040575419 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.1040575419
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.4122733419
Short name	T432
Test name
Test status
Simulation time	185497019137 ps
CPU time	558.4 seconds
Started	Aug 25 01:08:35 AM UTC 24
Finished	Aug 25 01:18:01 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122733419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.4122733419
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/31.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.3133361304
Short name	T123
Test name
Test status
Simulation time	80776423793 ps
CPU time	220.53 seconds
Started	Aug 25 01:08:26 AM UTC 24
Finished	Aug 25 01:12:10 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133361304 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3133361304
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/31.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.3597119196
Short name	T97
Test name
Test status
Simulation time	483355021157 ps
CPU time	686.61 seconds
Started	Aug 25 01:09:06 AM UTC 24
Finished	Aug 25 01:20:41 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597119196 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.3597119196
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.2200865466
Short name	T418
Test name
Test status
Simulation time	117216299857 ps
CPU time	187.78 seconds
Started	Aug 25 01:08:53 AM UTC 24
Finished	Aug 25 01:12:04 AM UTC 24
Peak memory	199812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200865466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2200865466
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/32.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.2540563943
Short name	T380
Test name
Test status
Simulation time	95963329598 ps
CPU time	79.3 seconds
Started	Aug 25 01:09:11 AM UTC 24
Finished	Aug 25 01:10:33 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540563943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2540563943
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/32.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.238757001
Short name	T411
Test name
Test status
Simulation time	86389139 ps
CPU time	0.82 seconds
Started	Aug 25 01:09:15 AM UTC 24
Finished	Aug 25 01:09:17 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238757001 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.238757001
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/32.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.3105895781
Short name	T75
Test name
Test status
Simulation time	52486420412 ps
CPU time	52.63 seconds
Started	Aug 25 01:09:23 AM UTC 24
Finished	Aug 25 01:10:17 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105895781 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.3105895781
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.4269033726
Short name	T430
Test name
Test status
Simulation time	890550187564 ps
CPU time	445.42 seconds
Started	Aug 25 01:09:19 AM UTC 24
Finished	Aug 25 01:16:50 AM UTC 24
Peak memory	199716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269033726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.4269033726
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/33.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.1159984903
Short name	T295
Test name
Test status
Simulation time	53526127601 ps
CPU time	202.91 seconds
Started	Aug 25 01:09:24 AM UTC 24
Finished	Aug 25 01:12:50 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159984903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1159984903
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/33.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.3825619423
Short name	T158
Test name
Test status
Simulation time	1079198405131 ps
CPU time	1455.59 seconds
Started	Aug 25 01:09:45 AM UTC 24
Finished	Aug 25 01:34:19 AM UTC 24
Peak memory	199916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825619423 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.3825619423
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/33.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.3244518241
Short name	T116
Test name
Test status
Simulation time	16936336293 ps
CPU time	49.39 seconds
Started	Aug 25 01:09:59 AM UTC 24
Finished	Aug 25 01:10:50 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244518241 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.3244518241
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.3168735815
Short name	T419
Test name
Test status
Simulation time	56940857326 ps
CPU time	168.93 seconds
Started	Aug 25 01:09:59 AM UTC 24
Finished	Aug 25 01:12:51 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168735815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3168735815
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/34.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.3568059638
Short name	T414
Test name
Test status
Simulation time	202816803 ps
CPU time	0.94 seconds
Started	Aug 25 01:10:06 AM UTC 24
Finished	Aug 25 01:10:08 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568059638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3568059638
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/34.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.913578638
Short name	T302
Test name
Test status
Simulation time	262639523377 ps
CPU time	1046.58 seconds
Started	Aug 25 01:10:17 AM UTC 24
Finished	Aug 25 01:27:57 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913578638 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.913578638
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/34.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.711803548
Short name	T148
Test name
Test status
Simulation time	4136170738 ps
CPU time	4.33 seconds
Started	Aug 25 01:10:47 AM UTC 24
Finished	Aug 25 01:10:52 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711803548 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.711803548
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.633746745
Short name	T433
Test name
Test status
Simulation time	682430629247 ps
CPU time	447.04 seconds
Started	Aug 25 01:10:34 AM UTC 24
Finished	Aug 25 01:18:07 AM UTC 24
Peak memory	199716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633746745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.633746745
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/35.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.3771701706
Short name	T117
Test name
Test status
Simulation time	818795941576 ps
CPU time	699.83 seconds
Started	Aug 25 01:10:18 AM UTC 24
Finished	Aug 25 01:22:08 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771701706 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3771701706
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/35.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.1597397699
Short name	T351
Test name
Test status
Simulation time	51252332550 ps
CPU time	406.85 seconds
Started	Aug 25 01:10:51 AM UTC 24
Finished	Aug 25 01:17:43 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597397699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1597397699
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/35.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.33365034
Short name	T225
Test name
Test status
Simulation time	1400334220665 ps
CPU time	636.47 seconds
Started	Aug 25 01:11:08 AM UTC 24
Finished	Aug 25 01:21:54 AM UTC 24
Peak memory	199588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33365034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.33365034
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.2035221328
Short name	T425
Test name
Test status
Simulation time	685461000027 ps
CPU time	275.63 seconds
Started	Aug 25 01:11:08 AM UTC 24
Finished	Aug 25 01:15:48 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035221328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2035221328
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/36.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.2094297267
Short name	T102
Test name
Test status
Simulation time	79316310650 ps
CPU time	124.75 seconds
Started	Aug 25 01:12:05 AM UTC 24
Finished	Aug 25 01:14:12 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094297267 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.2094297267
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.3263991347
Short name	T416
Test name
Test status
Simulation time	145537006959 ps
CPU time	368.61 seconds
Started	Aug 25 01:11:49 AM UTC 24
Finished	Aug 25 01:18:02 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263991347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3263991347
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/37.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.3207694774
Short name	T111
Test name
Test status
Simulation time	229530344485 ps
CPU time	160.27 seconds
Started	Aug 25 01:11:43 AM UTC 24
Finished	Aug 25 01:14:26 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207694774 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3207694774
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/37.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.3068571332
Short name	T81
Test name
Test status
Simulation time	61624357952 ps
CPU time	44.87 seconds
Started	Aug 25 01:12:11 AM UTC 24
Finished	Aug 25 01:12:57 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068571332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3068571332
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/37.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.501947369
Short name	T203
Test name
Test status
Simulation time	393284569663 ps
CPU time	1091.64 seconds
Started	Aug 25 01:13:03 AM UTC 24
Finished	Aug 25 01:31:29 AM UTC 24
Peak memory	199724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501947369 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.501947369
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.3816520500
Short name	T426
Test name
Test status
Simulation time	106321682915 ps
CPU time	168.9 seconds
Started	Aug 25 01:12:58 AM UTC 24
Finished	Aug 25 01:15:50 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816520500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3816520500
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/38.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.3777641147
Short name	T166
Test name
Test status
Simulation time	461152051736 ps
CPU time	467.35 seconds
Started	Aug 25 01:12:51 AM UTC 24
Finished	Aug 25 01:20:45 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777641147 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3777641147
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/38.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.3784126954
Short name	T132
Test name
Test status
Simulation time	168569963802 ps
CPU time	130.7 seconds
Started	Aug 25 01:13:44 AM UTC 24
Finished	Aug 25 01:15:57 AM UTC 24
Peak memory	199912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784126954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3784126954
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/38.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.3784504572
Short name	T427
Test name
Test status
Simulation time	127504399464 ps
CPU time	115.98 seconds
Started	Aug 25 01:14:06 AM UTC 24
Finished	Aug 25 01:16:04 AM UTC 24
Peak memory	199788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784504572 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.3784504572
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/38.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.852717962
Short name	T161
Test name
Test status
Simulation time	1137195967351 ps
CPU time	953.03 seconds
Started	Aug 25 01:14:12 AM UTC 24
Finished	Aug 25 01:30:17 AM UTC 24
Peak memory	199660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852717962 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.852717962
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.1423447353
Short name	T437
Test name
Test status
Simulation time	103477061614 ps
CPU time	281.59 seconds
Started	Aug 25 01:14:11 AM UTC 24
Finished	Aug 25 01:18:57 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423447353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1423447353
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/39.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.2697891477
Short name	T93
Test name
Test status
Simulation time	442826837083 ps
CPU time	398.49 seconds
Started	Aug 25 01:14:08 AM UTC 24
Finished	Aug 25 01:20:52 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697891477 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2697891477
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/39.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.2224731192
Short name	T421
Test name
Test status
Simulation time	25123419240 ps
CPU time	17.69 seconds
Started	Aug 25 01:14:17 AM UTC 24
Finished	Aug 25 01:14:36 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224731192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2224731192
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/39.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.25236774
Short name	T139
Test name
Test status
Simulation time	653049572480 ps
CPU time	1036.16 seconds
Started	Aug 25 01:00:43 AM UTC 24
Finished	Aug 25 01:18:13 AM UTC 24
Peak memory	202656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25236774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.25236774
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.2897330564
Short name	T408
Test name
Test status
Simulation time	346983076370 ps
CPU time	465.15 seconds
Started	Aug 25 01:00:43 AM UTC 24
Finished	Aug 25 01:08:35 AM UTC 24
Peak memory	199816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897330564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2897330564
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.3409249123
Short name	T226
Test name
Test status
Simulation time	669711329375 ps
CPU time	1276.31 seconds
Started	Aug 25 01:00:40 AM UTC 24
Finished	Aug 25 01:22:14 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409249123 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3409249123
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.3208825293
Short name	T83
Test name
Test status
Simulation time	17587735964 ps
CPU time	228.63 seconds
Started	Aug 25 01:00:46 AM UTC 24
Finished	Aug 25 01:04:38 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208825293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3208825293
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.2987887878
Short name	T6
Test name
Test status
Simulation time	159132475 ps
CPU time	1.1 seconds
Started	Aug 25 01:00:48 AM UTC 24
Finished	Aug 25 01:00:50 AM UTC 24
Peak memory	228940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987887878 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2987887878
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.279291122
Short name	T370
Test name
Test status
Simulation time	85964459243 ps
CPU time	44.37 seconds
Started	Aug 25 01:14:45 AM UTC 24
Finished	Aug 25 01:15:31 AM UTC 24
Peak memory	199588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279291122 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.279291122
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.659749345
Short name	T431
Test name
Test status
Simulation time	73647620327 ps
CPU time	185.49 seconds
Started	Aug 25 01:14:44 AM UTC 24
Finished	Aug 25 01:17:52 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659749345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.659749345
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/40.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.915583690
Short name	T138
Test name
Test status
Simulation time	228491371940 ps
CPU time	181.59 seconds
Started	Aug 25 01:14:41 AM UTC 24
Finished	Aug 25 01:17:46 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915583690 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.915583690
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/40.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.948894137
Short name	T153
Test name
Test status
Simulation time	28927760599 ps
CPU time	34.7 seconds
Started	Aug 25 01:14:56 AM UTC 24
Finished	Aug 25 01:15:32 AM UTC 24
Peak memory	199616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948894137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.948894137
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/40.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.3979718203
Short name	T135
Test name
Test status
Simulation time	19345049983 ps
CPU time	57.84 seconds
Started	Aug 25 01:15:00 AM UTC 24
Finished	Aug 25 01:15:59 AM UTC 24
Peak memory	199616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979718203 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.3979718203
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/40.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.1919708028
Short name	T321
Test name
Test status
Simulation time	320330377595 ps
CPU time	1003.77 seconds
Started	Aug 25 01:15:25 AM UTC 24
Finished	Aug 25 01:32:21 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919708028 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.1919708028
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.1654745311
Short name	T440
Test name
Test status
Simulation time	141873005051 ps
CPU time	327.11 seconds
Started	Aug 25 01:15:16 AM UTC 24
Finished	Aug 25 01:20:47 AM UTC 24
Peak memory	199792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654745311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1654745311
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/41.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.1749478053
Short name	T176
Test name
Test status
Simulation time	117243761170 ps
CPU time	405.35 seconds
Started	Aug 25 01:15:04 AM UTC 24
Finished	Aug 25 01:21:55 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749478053 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1749478053
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/41.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.4027204750
Short name	T343
Test name
Test status
Simulation time	389513335384 ps
CPU time	205 seconds
Started	Aug 25 01:15:25 AM UTC 24
Finished	Aug 25 01:18:54 AM UTC 24
Peak memory	199848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027204750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.4027204750
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/41.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.1388064157
Short name	T314
Test name
Test status
Simulation time	906826267706 ps
CPU time	3576.14 seconds
Started	Aug 25 01:15:31 AM UTC 24
Finished	Aug 25 02:15:52 AM UTC 24
Peak memory	202356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388064157 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.1388064157
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/41.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all_with_rand_reset.3876701039
Short name	T29
Test name
Test status
Simulation time	1872268840 ps
CPU time	26.51 seconds
Started	Aug 25 01:15:26 AM UTC 24
Finished	Aug 25 01:15:54 AM UTC 24
Peak memory	201852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3876701039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.rv_timer_stress_all_with_rand_reset.3876701039
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/41.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.2354055789
Short name	T223
Test name
Test status
Simulation time	760379040706 ps
CPU time	1288.74 seconds
Started	Aug 25 01:15:43 AM UTC 24
Finished	Aug 25 01:37:28 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354055789 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.2354055789
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.3442407047
Short name	T424
Test name
Test status
Simulation time	220351275383 ps
CPU time	171.47 seconds
Started	Aug 25 01:15:40 AM UTC 24
Finished	Aug 25 01:18:35 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442407047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3442407047
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/42.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.3862425600
Short name	T258
Test name
Test status
Simulation time	630387692769 ps
CPU time	499.03 seconds
Started	Aug 25 01:15:32 AM UTC 24
Finished	Aug 25 01:23:59 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862425600 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3862425600
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/42.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.3309101943
Short name	T188
Test name
Test status
Simulation time	43851480781 ps
CPU time	102.16 seconds
Started	Aug 25 01:15:49 AM UTC 24
Finished	Aug 25 01:17:33 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309101943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3309101943
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/42.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.1129333685
Short name	T42
Test name
Test status
Simulation time	182119158964 ps
CPU time	459.51 seconds
Started	Aug 25 01:15:51 AM UTC 24
Finished	Aug 25 01:23:37 AM UTC 24
Peak memory	199620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129333685 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.1129333685
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/42.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.4258060841
Short name	T285
Test name
Test status
Simulation time	98125316692 ps
CPU time	50.02 seconds
Started	Aug 25 01:16:00 AM UTC 24
Finished	Aug 25 01:16:52 AM UTC 24
Peak memory	199596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258060841 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.4258060841
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.3385268689
Short name	T435
Test name
Test status
Simulation time	120188322332 ps
CPU time	163.38 seconds
Started	Aug 25 01:15:58 AM UTC 24
Finished	Aug 25 01:18:44 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385268689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3385268689
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/43.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.734138581
Short name	T345
Test name
Test status
Simulation time	183161588549 ps
CPU time	161.35 seconds
Started	Aug 25 01:15:55 AM UTC 24
Finished	Aug 25 01:18:39 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734138581 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.734138581
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/43.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.898396081
Short name	T301
Test name
Test status
Simulation time	11991208598 ps
CPU time	38.64 seconds
Started	Aug 25 01:16:01 AM UTC 24
Finished	Aug 25 01:16:41 AM UTC 24
Peak memory	199848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898396081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.898396081
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/43.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all_with_rand_reset.357443622
Short name	T428
Test name
Test status
Simulation time	1294505048 ps
CPU time	17.46 seconds
Started	Aug 25 01:16:05 AM UTC 24
Finished	Aug 25 01:16:24 AM UTC 24
Peak memory	201892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=357443622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.357443622
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/43.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.1688655513
Short name	T438
Test name
Test status
Simulation time	95919794015 ps
CPU time	162.58 seconds
Started	Aug 25 01:16:24 AM UTC 24
Finished	Aug 25 01:19:10 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688655513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1688655513
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/44.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.2754134332
Short name	T429
Test name
Test status
Simulation time	440661889 ps
CPU time	1.25 seconds
Started	Aug 25 01:16:41 AM UTC 24
Finished	Aug 25 01:16:44 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754134332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2754134332
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/44.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.1168644361
Short name	T198
Test name
Test status
Simulation time	372765268328 ps
CPU time	1132.31 seconds
Started	Aug 25 01:16:51 AM UTC 24
Finished	Aug 25 01:35:56 AM UTC 24
Peak memory	199788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168644361 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.1168644361
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/44.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.212017767
Short name	T131
Test name
Test status
Simulation time	148766890672 ps
CPU time	259.26 seconds
Started	Aug 25 01:17:11 AM UTC 24
Finished	Aug 25 01:21:34 AM UTC 24
Peak memory	199724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212017767 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.212017767
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.1011906255
Short name	T439
Test name
Test status
Simulation time	141761552728 ps
CPU time	203.87 seconds
Started	Aug 25 01:17:04 AM UTC 24
Finished	Aug 25 01:20:31 AM UTC 24
Peak memory	199812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011906255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1011906255
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/45.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.3838241861
Short name	T272
Test name
Test status
Simulation time	182760826221 ps
CPU time	175.42 seconds
Started	Aug 25 01:16:53 AM UTC 24
Finished	Aug 25 01:19:51 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838241861 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3838241861
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/45.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.699094658
Short name	T262
Test name
Test status
Simulation time	395131259678 ps
CPU time	390.2 seconds
Started	Aug 25 01:17:32 AM UTC 24
Finished	Aug 25 01:24:07 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699094658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.699094658
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/45.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all_with_rand_reset.1745084225
Short name	T31
Test name
Test status
Simulation time	379213390 ps
CPU time	4.41 seconds
Started	Aug 25 01:17:33 AM UTC 24
Finished	Aug 25 01:17:38 AM UTC 24
Peak memory	201720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1745084225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.rv_timer_stress_all_with_rand_reset.1745084225
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/45.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.2464604585
Short name	T241
Test name
Test status
Simulation time	255978420015 ps
CPU time	351.91 seconds
Started	Aug 25 01:17:47 AM UTC 24
Finished	Aug 25 01:23:44 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464604585 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.2464604585
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.220099803
Short name	T436
Test name
Test status
Simulation time	20823444952 ps
CPU time	64.28 seconds
Started	Aug 25 01:17:44 AM UTC 24
Finished	Aug 25 01:18:50 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220099803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.220099803
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/46.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.4177619443
Short name	T290
Test name
Test status
Simulation time	436773392849 ps
CPU time	880.33 seconds
Started	Aug 25 01:17:39 AM UTC 24
Finished	Aug 25 01:32:31 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177619443 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.4177619443
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/46.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.2010905241
Short name	T444
Test name
Test status
Simulation time	18213341455 ps
CPU time	397.62 seconds
Started	Aug 25 01:17:52 AM UTC 24
Finished	Aug 25 01:24:36 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010905241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2010905241
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/46.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.1410284263
Short name	T354
Test name
Test status
Simulation time	2111104674821 ps
CPU time	1549.8 seconds
Started	Aug 25 01:17:57 AM UTC 24
Finished	Aug 25 01:44:05 AM UTC 24
Peak memory	202456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410284263 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.1410284263
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/46.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.2590953045
Short name	T338
Test name
Test status
Simulation time	31213423426 ps
CPU time	47.86 seconds
Started	Aug 25 01:18:08 AM UTC 24
Finished	Aug 25 01:18:57 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590953045 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.2590953045
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.2783869112
Short name	T434
Test name
Test status
Simulation time	51715907556 ps
CPU time	32.68 seconds
Started	Aug 25 01:18:03 AM UTC 24
Finished	Aug 25 01:18:37 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783869112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2783869112
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/47.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.3906056654
Short name	T234
Test name
Test status
Simulation time	75097546700 ps
CPU time	985.4 seconds
Started	Aug 25 01:18:02 AM UTC 24
Finished	Aug 25 01:34:40 AM UTC 24
Peak memory	199872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906056654 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3906056654
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/47.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.178338131
Short name	T342
Test name
Test status
Simulation time	104555734407 ps
CPU time	291.93 seconds
Started	Aug 25 01:18:14 AM UTC 24
Finished	Aug 25 01:23:10 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178338131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.178338131
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/47.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.691948458
Short name	T303
Test name
Test status
Simulation time	488781907400 ps
CPU time	704.47 seconds
Started	Aug 25 01:18:37 AM UTC 24
Finished	Aug 25 01:30:30 AM UTC 24
Peak memory	199660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691948458 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.691948458
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.4090102279
Short name	T442
Test name
Test status
Simulation time	473449124932 ps
CPU time	240.22 seconds
Started	Aug 25 01:18:37 AM UTC 24
Finished	Aug 25 01:22:41 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090102279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4090102279
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/48.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.3680757678
Short name	T279
Test name
Test status
Simulation time	237524779982 ps
CPU time	348.64 seconds
Started	Aug 25 01:18:35 AM UTC 24
Finished	Aug 25 01:24:29 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680757678 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3680757678
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/48.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.3864346339
Short name	T240
Test name
Test status
Simulation time	32050249165 ps
CPU time	275.61 seconds
Started	Aug 25 01:18:39 AM UTC 24
Finished	Aug 25 01:23:19 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864346339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3864346339
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/48.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.769994654
Short name	T443
Test name
Test status
Simulation time	102254309414 ps
CPU time	309.02 seconds
Started	Aug 25 01:18:51 AM UTC 24
Finished	Aug 25 01:24:05 AM UTC 24
Peak memory	199812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769994654 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.769994654
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/48.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.3089663119
Short name	T278
Test name
Test status
Simulation time	443581267421 ps
CPU time	1278.69 seconds
Started	Aug 25 01:18:59 AM UTC 24
Finished	Aug 25 01:40:33 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089663119 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.3089663119
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.974096014
Short name	T441
Test name
Test status
Simulation time	48225397291 ps
CPU time	146.24 seconds
Started	Aug 25 01:18:57 AM UTC 24
Finished	Aug 25 01:21:26 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974096014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.974096014
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/49.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.139310203
Short name	T449
Test name
Test status
Simulation time	482099382607 ps
CPU time	1702.04 seconds
Started	Aug 25 01:18:54 AM UTC 24
Finished	Aug 25 01:47:38 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139310203 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.139310203
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/49.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.3673260004
Short name	T266
Test name
Test status
Simulation time	2847307504 ps
CPU time	7.2 seconds
Started	Aug 25 01:19:06 AM UTC 24
Finished	Aug 25 01:19:14 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673260004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3673260004
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/49.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.1433610393
Short name	T227
Test name
Test status
Simulation time	491499603244 ps
CPU time	1225.7 seconds
Started	Aug 25 01:19:10 AM UTC 24
Finished	Aug 25 01:39:51 AM UTC 24
Peak memory	199788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433610393 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.1433610393
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/49.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.2696677294
Short name	T85
Test name
Test status
Simulation time	164742760335 ps
CPU time	147.21 seconds
Started	Aug 25 01:00:51 AM UTC 24
Finished	Aug 25 01:03:21 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696677294 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.2696677294
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.1117709649
Short name	T133
Test name
Test status
Simulation time	140783334802 ps
CPU time	109.82 seconds
Started	Aug 25 01:00:50 AM UTC 24
Finished	Aug 25 01:02:42 AM UTC 24
Peak memory	199692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117709649 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1117709649
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/5.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.3559843349
Short name	T10
Test name
Test status
Simulation time	9713849957 ps
CPU time	29.77 seconds
Started	Aug 25 01:00:51 AM UTC 24
Finished	Aug 25 01:01:23 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559843349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3559843349
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/5.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.3962668436
Short name	T308
Test name
Test status
Simulation time	48338495087 ps
CPU time	86.47 seconds
Started	Aug 25 01:19:11 AM UTC 24
Finished	Aug 25 01:20:40 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962668436 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3962668436
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/50.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.1002086562
Short name	T212
Test name
Test status
Simulation time	116409216171 ps
CPU time	1068.71 seconds
Started	Aug 25 01:19:15 AM UTC 24
Finished	Aug 25 01:37:17 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002086562 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1002086562
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/51.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.132664995
Short name	T274
Test name
Test status
Simulation time	68092279483 ps
CPU time	202.44 seconds
Started	Aug 25 01:20:31 AM UTC 24
Finished	Aug 25 01:23:57 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132664995 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.132664995
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/54.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.25948914
Short name	T335
Test name
Test status
Simulation time	390944132046 ps
CPU time	833.26 seconds
Started	Aug 25 01:20:31 AM UTC 24
Finished	Aug 25 01:34:36 AM UTC 24
Peak memory	199680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25948914 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.25948914
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/55.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.3192493230
Short name	T322
Test name
Test status
Simulation time	157761682399 ps
CPU time	955.12 seconds
Started	Aug 25 01:20:40 AM UTC 24
Finished	Aug 25 01:36:47 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192493230 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3192493230
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/56.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.3311192692
Short name	T208
Test name
Test status
Simulation time	48836627890 ps
CPU time	170.37 seconds
Started	Aug 25 01:20:41 AM UTC 24
Finished	Aug 25 01:23:35 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311192692 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3311192692
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/58.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.2519510976
Short name	T221
Test name
Test status
Simulation time	2029555864464 ps
CPU time	844.78 seconds
Started	Aug 25 01:20:47 AM UTC 24
Finished	Aug 25 01:35:02 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519510976 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2519510976
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/59.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.3670647400
Short name	T204
Test name
Test status
Simulation time	2698477934359 ps
CPU time	1755.41 seconds
Started	Aug 25 01:01:01 AM UTC 24
Finished	Aug 25 01:30:37 AM UTC 24
Peak memory	202332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670647400 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.3670647400
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.559644361
Short name	T80
Test name
Test status
Simulation time	352479210633 ps
CPU time	329.03 seconds
Started	Aug 25 01:00:56 AM UTC 24
Finished	Aug 25 01:06:30 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559644361 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.559644361
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/6.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.4099064124
Short name	T7
Test name
Test status
Simulation time	259122195 ps
CPU time	0.97 seconds
Started	Aug 25 01:01:03 AM UTC 24
Finished	Aug 25 01:01:05 AM UTC 24
Peak memory	198872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099064124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4099064124
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/6.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.2976017942
Short name	T305
Test name
Test status
Simulation time	127571987633 ps
CPU time	1635.6 seconds
Started	Aug 25 01:20:49 AM UTC 24
Finished	Aug 25 01:48:24 AM UTC 24
Peak memory	202484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976017942 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2976017942
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/60.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.3738854978
Short name	T264
Test name
Test status
Simulation time	48371679936 ps
CPU time	152.74 seconds
Started	Aug 25 01:20:53 AM UTC 24
Finished	Aug 25 01:23:28 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738854978 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3738854978
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/61.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.3685920504
Short name	T200
Test name
Test status
Simulation time	176670965884 ps
CPU time	562.48 seconds
Started	Aug 25 01:20:58 AM UTC 24
Finished	Aug 25 01:30:28 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685920504 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3685920504
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/62.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.2119956488
Short name	T173
Test name
Test status
Simulation time	112227079863 ps
CPU time	537.34 seconds
Started	Aug 25 01:21:20 AM UTC 24
Finished	Aug 25 01:30:25 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119956488 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2119956488
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/63.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.3699472301
Short name	T367
Test name
Test status
Simulation time	82851118226 ps
CPU time	112.19 seconds
Started	Aug 25 01:21:20 AM UTC 24
Finished	Aug 25 01:23:14 AM UTC 24
Peak memory	199532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699472301 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3699472301
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/64.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.4033423580
Short name	T267
Test name
Test status
Simulation time	45337095540 ps
CPU time	82.46 seconds
Started	Aug 25 01:21:20 AM UTC 24
Finished	Aug 25 01:22:45 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033423580 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.4033423580
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/65.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.1469423839
Short name	T193
Test name
Test status
Simulation time	537644199023 ps
CPU time	510.53 seconds
Started	Aug 25 01:21:27 AM UTC 24
Finished	Aug 25 01:30:05 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469423839 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1469423839
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/66.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.466372922
Short name	T206
Test name
Test status
Simulation time	82196840498 ps
CPU time	640.17 seconds
Started	Aug 25 01:21:35 AM UTC 24
Finished	Aug 25 01:32:24 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466372922 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.466372922
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/67.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.297015125
Short name	T297
Test name
Test status
Simulation time	41920016778 ps
CPU time	954.14 seconds
Started	Aug 25 01:21:55 AM UTC 24
Finished	Aug 25 01:38:03 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297015125 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.297015125
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/69.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.2647068757
Short name	T147
Test name
Test status
Simulation time	307521229556 ps
CPU time	843.27 seconds
Started	Aug 25 01:01:10 AM UTC 24
Finished	Aug 25 01:15:25 AM UTC 24
Peak memory	199732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647068757 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.2647068757
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.3931714755
Short name	T398
Test name
Test status
Simulation time	226456470628 ps
CPU time	308.57 seconds
Started	Aug 25 01:01:08 AM UTC 24
Finished	Aug 25 01:06:21 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931714755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3931714755
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/7.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.3360668218
Short name	T185
Test name
Test status
Simulation time	228153879255 ps
CPU time	2605.37 seconds
Started	Aug 25 01:01:15 AM UTC 24
Finished	Aug 25 01:45:13 AM UTC 24
Peak memory	202488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360668218 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.3360668218
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/7.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.737092293
Short name	T231
Test name
Test status
Simulation time	24947332586 ps
CPU time	32.24 seconds
Started	Aug 25 01:21:57 AM UTC 24
Finished	Aug 25 01:22:31 AM UTC 24
Peak memory	199532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737092293 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.737092293
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/70.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.2516893482
Short name	T236
Test name
Test status
Simulation time	371494032766 ps
CPU time	467.24 seconds
Started	Aug 25 01:21:59 AM UTC 24
Finished	Aug 25 01:29:53 AM UTC 24
Peak memory	199908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516893482 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2516893482
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/71.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.3297649990
Short name	T373
Test name
Test status
Simulation time	134711962862 ps
CPU time	1312.48 seconds
Started	Aug 25 01:22:03 AM UTC 24
Finished	Aug 25 01:44:12 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297649990 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3297649990
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/72.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.2227281200
Short name	T160
Test name
Test status
Simulation time	515458906369 ps
CPU time	774.87 seconds
Started	Aug 25 01:22:09 AM UTC 24
Finished	Aug 25 01:35:14 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227281200 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2227281200
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/73.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.2926461020
Short name	T169
Test name
Test status
Simulation time	191059794386 ps
CPU time	486.28 seconds
Started	Aug 25 01:22:09 AM UTC 24
Finished	Aug 25 01:30:22 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926461020 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2926461020
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/74.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.100705270
Short name	T167
Test name
Test status
Simulation time	91292536300 ps
CPU time	114.36 seconds
Started	Aug 25 01:22:15 AM UTC 24
Finished	Aug 25 01:24:12 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100705270 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.100705270
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/75.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.2938749187
Short name	T320
Test name
Test status
Simulation time	123219188600 ps
CPU time	191.9 seconds
Started	Aug 25 01:22:30 AM UTC 24
Finished	Aug 25 01:25:46 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938749187 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2938749187
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/77.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.3635460909
Short name	T293
Test name
Test status
Simulation time	25274019652 ps
CPU time	288.66 seconds
Started	Aug 25 01:22:32 AM UTC 24
Finished	Aug 25 01:27:26 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635460909 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3635460909
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/78.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.4272590773
Short name	T177
Test name
Test status
Simulation time	175495498645 ps
CPU time	535.77 seconds
Started	Aug 25 01:22:42 AM UTC 24
Finished	Aug 25 01:31:45 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272590773 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.4272590773
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/79.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.2459083298
Short name	T256
Test name
Test status
Simulation time	1907664823570 ps
CPU time	1217.09 seconds
Started	Aug 25 01:01:25 AM UTC 24
Finished	Aug 25 01:21:57 AM UTC 24
Peak memory	202332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459083298 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.2459083298
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.3884685703
Short name	T385
Test name
Test status
Simulation time	334081470400 ps
CPU time	103.98 seconds
Started	Aug 25 01:01:23 AM UTC 24
Finished	Aug 25 01:03:09 AM UTC 24
Peak memory	199724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884685703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3884685703
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/8.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.364134230
Short name	T319
Test name
Test status
Simulation time	92148805533 ps
CPU time	1132.93 seconds
Started	Aug 25 01:01:23 AM UTC 24
Finished	Aug 25 01:20:31 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364134230 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.364134230
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/8.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.495367155
Short name	T39
Test name
Test status
Simulation time	258786374561 ps
CPU time	860.1 seconds
Started	Aug 25 01:01:28 AM UTC 24
Finished	Aug 25 01:16:00 AM UTC 24
Peak memory	199624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495367155 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.495367155
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/8.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all_with_rand_reset.891295313
Short name	T12
Test name
Test status
Simulation time	2994337078 ps
CPU time	32.4 seconds
Started	Aug 25 01:01:27 AM UTC 24
Finished	Aug 25 01:02:02 AM UTC 24
Peak memory	203896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=891295313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.891295313
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/8.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.3702216735
Short name	T316
Test name
Test status
Simulation time	772972405576 ps
CPU time	278.09 seconds
Started	Aug 25 01:22:45 AM UTC 24
Finished	Aug 25 01:27:28 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702216735 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3702216735
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/80.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.373812709
Short name	T364
Test name
Test status
Simulation time	743349512336 ps
CPU time	1255.39 seconds
Started	Aug 25 01:23:03 AM UTC 24
Finished	Aug 25 01:44:14 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373812709 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.373812709
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/81.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.692013688
Short name	T168
Test name
Test status
Simulation time	35751884058 ps
CPU time	106.95 seconds
Started	Aug 25 01:23:08 AM UTC 24
Finished	Aug 25 01:24:58 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692013688 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.692013688
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/82.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.3570455079
Short name	T150
Test name
Test status
Simulation time	205755920717 ps
CPU time	421.45 seconds
Started	Aug 25 01:23:11 AM UTC 24
Finished	Aug 25 01:30:19 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570455079 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3570455079
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/84.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.4179920989
Short name	T242
Test name
Test status
Simulation time	170976781740 ps
CPU time	207.24 seconds
Started	Aug 25 01:23:20 AM UTC 24
Finished	Aug 25 01:26:51 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179920989 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4179920989
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/86.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.1966309186
Short name	T450
Test name
Test status
Simulation time	468758424102 ps
CPU time	2596.69 seconds
Started	Aug 25 01:23:29 AM UTC 24
Finished	Aug 25 02:07:19 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966309186 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1966309186
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/87.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.418432436
Short name	T253
Test name
Test status
Simulation time	194789094484 ps
CPU time	258.74 seconds
Started	Aug 25 01:23:36 AM UTC 24
Finished	Aug 25 01:27:59 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418432436 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.418432436
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/88.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.3443562597
Short name	T30
Test name
Test status
Simulation time	7094606513 ps
CPU time	23.58 seconds
Started	Aug 25 01:01:32 AM UTC 24
Finished	Aug 25 01:01:57 AM UTC 24
Peak memory	199596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443562597 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.3443562597
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.902473187
Short name	T389
Test name
Test status
Simulation time	130714330089 ps
CPU time	181.21 seconds
Started	Aug 25 01:01:31 AM UTC 24
Finished	Aug 25 01:04:35 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902473187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.902473187
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/9.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.111219287
Short name	T100
Test name
Test status
Simulation time	50512469816 ps
CPU time	52.31 seconds
Started	Aug 25 01:01:31 AM UTC 24
Finished	Aug 25 01:02:25 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111219287 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.111219287
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/9.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.3269700021
Short name	T21
Test name
Test status
Simulation time	1070770772 ps
CPU time	1.69 seconds
Started	Aug 25 01:01:34 AM UTC 24
Finished	Aug 25 01:01:37 AM UTC 24
Peak memory	198872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269700021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3269700021
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/9.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all_with_rand_reset.1608167575
Short name	T11
Test name
Test status
Simulation time	1057090402 ps
CPU time	15.35 seconds
Started	Aug 25 01:01:38 AM UTC 24
Finished	Aug 25 01:01:54 AM UTC 24
Peak memory	201852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1608167575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.rv_timer_stress_all_with_rand_reset.1608167575
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/9.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.865919201
Short name	T246
Test name
Test status
Simulation time	7669406045 ps
CPU time	26.88 seconds
Started	Aug 25 01:23:45 AM UTC 24
Finished	Aug 25 01:24:13 AM UTC 24
Peak memory	199872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865919201 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.865919201
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/90.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.3845770710
Short name	T332
Test name
Test status
Simulation time	351415576954 ps
CPU time	2444.12 seconds
Started	Aug 25 01:23:58 AM UTC 24
Finished	Aug 25 02:05:16 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845770710 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3845770710
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/91.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.3311867829
Short name	T286
Test name
Test status
Simulation time	84654848863 ps
CPU time	65.55 seconds
Started	Aug 25 01:24:00 AM UTC 24
Finished	Aug 25 01:25:07 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311867829 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3311867829
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/92.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.2528771956
Short name	T232
Test name
Test status
Simulation time	420972877275 ps
CPU time	507.78 seconds
Started	Aug 25 01:24:08 AM UTC 24
Finished	Aug 25 01:32:43 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2528771956 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2528771956
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/94.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.1733838977
Short name	T175
Test name
Test status
Simulation time	33113076000 ps
CPU time	145.55 seconds
Started	Aug 25 01:24:14 AM UTC 24
Finished	Aug 25 01:26:43 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733838977 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1733838977
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/96.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.3350286775
Short name	T265
Test name
Test status
Simulation time	140762904240 ps
CPU time	594.35 seconds
Started	Aug 25 01:24:31 AM UTC 24
Finished	Aug 25 01:34:33 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350286775 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3350286775
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/97.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.1636004627
Short name	T157
Test name
Test status
Simulation time	93991558173 ps
CPU time	415.99 seconds
Started	Aug 25 01:24:37 AM UTC 24
Finished	Aug 25 01:31:39 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636004627 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_24/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1636004627
Directory	/workspaces/repo/scratch/os_regression_2024_08_24/rv_timer-sim-vcs/98.rv_timer_random/latest