| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.70 | 99.36 | 99.04 | 100.00 | 100.00 | 100.00 | 99.77 |
| T503 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2643082756 | Aug 27 03:24:19 AM UTC 24 | Aug 27 03:24:22 AM UTC 24 | 302385850 ps | ||
| T504 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4002499428 | Aug 27 03:24:20 AM UTC 24 | Aug 27 03:24:22 AM UTC 24 | 183160623 ps | ||
| T505 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.2793610131 | Aug 27 03:24:20 AM UTC 24 | Aug 27 03:24:22 AM UTC 24 | 206235114 ps | ||
| T506 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.2330353381 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 15424354 ps | ||
| T507 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.2997964251 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:43 AM UTC 24 | 19250993 ps | ||
| T508 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.2321240026 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 13220429 ps | ||
| T509 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.4254783806 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 125516301 ps | ||
| T510 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3535934742 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 74782301 ps | ||
| T511 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.3064942791 | Aug 27 03:24:19 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 233022180 ps | ||
| T512 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.2684922550 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:43 AM UTC 24 | 178019951 ps | ||
| T513 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.1092957508 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 14068049 ps | ||
| T514 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.670445739 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 193773122 ps | ||
| T515 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.2217653357 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 20693463 ps | ||
| T516 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3932358441 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 80492758 ps | ||
| T517 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.3182189222 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 12389293 ps | ||
| T518 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4267665372 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 16667711 ps | ||
| T519 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2710860794 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 27956658 ps | ||
| T520 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.131742817 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 58399474 ps | ||
| T521 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.2812404765 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 128359057 ps | ||
| T522 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.3984594914 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:43 AM UTC 24 | 25357944 ps | ||
| T523 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.544888728 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 214654576 ps | ||
| T524 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.3802288373 | Aug 27 03:24:22 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 66514194 ps | ||
| T525 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3945625273 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 28280139 ps | ||
| T526 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.4112111452 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 115194248 ps | ||
| T527 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.4008317531 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 12583411 ps | ||
| T528 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.3231046949 | Aug 27 03:24:22 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 56803025 ps | ||
| T529 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4134734176 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 137474845 ps | ||
| T530 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2414231607 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 27527779 ps | ||
| T531 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3795737497 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 45241075 ps | ||
| T532 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3190477683 | Aug 27 03:24:22 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 78482638 ps | ||
| T533 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.679236743 | Aug 27 03:24:22 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 36270688 ps | ||
| T534 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.4161658861 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:23 AM UTC 24 | 381870754 ps | ||
| T535 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.358202104 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:24 AM UTC 24 | 77660468 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1552288881 | Aug 27 03:24:22 AM UTC 24 | Aug 27 03:24:24 AM UTC 24 | 201879603 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.2445166918 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:24 AM UTC 24 | 140752612 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.2020253641 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:24 AM UTC 24 | 236510382 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.229551207 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:24 AM UTC 24 | 118580890 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.698002304 | Aug 27 03:24:21 AM UTC 24 | Aug 27 03:24:25 AM UTC 24 | 472992890 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.3761679554 | Aug 27 03:24:22 AM UTC 24 | Aug 27 03:24:25 AM UTC 24 | 99605247 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.144986823 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:25 AM UTC 24 | 41023290 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3546104728 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:25 AM UTC 24 | 131964082 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.1161495369 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:30 AM UTC 24 | 14219331 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.2065004804 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:43 AM UTC 24 | 42422444 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.4259729287 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:30 AM UTC 24 | 139627903 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.2545513622 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:30 AM UTC 24 | 24293903 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.1451576781 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:31 AM UTC 24 | 15921391 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.4070335143 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:31 AM UTC 24 | 51088880 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.4271096089 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:31 AM UTC 24 | 13722451 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.2186539724 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:31 AM UTC 24 | 30563529 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.4290981940 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:31 AM UTC 24 | 15769618 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.652014990 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:31 AM UTC 24 | 15830826 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.3837199079 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:31 AM UTC 24 | 18306662 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.473762208 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:31 AM UTC 24 | 38621839 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.337879990 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:31 AM UTC 24 | 43300287 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.3634700530 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:31 AM UTC 24 | 41126274 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1554577142 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:31 AM UTC 24 | 53209215 ps | ||
| T72 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.1912719933 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:35 AM UTC 24 | 36533517 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.294847586 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:35 AM UTC 24 | 23698369 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2035037281 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:36 AM UTC 24 | 37241733 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.612960091 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:36 AM UTC 24 | 36752658 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.3021472274 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:41 AM UTC 24 | 13514453 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.987743724 | Aug 27 03:24:26 AM UTC 24 | Aug 27 03:24:41 AM UTC 24 | 46093551 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.3674811260 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:42 AM UTC 24 | 34266963 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.3251341851 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:42 AM UTC 24 | 33082784 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1660885444 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:42 AM UTC 24 | 15505314 ps | ||
| T73 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.2895494507 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:42 AM UTC 24 | 39227058 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.398339897 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:42 AM UTC 24 | 30452257 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.642294909 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:42 AM UTC 24 | 109493735 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.162953528 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:42 AM UTC 24 | 100220525 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2612229172 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:42 AM UTC 24 | 117647562 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.231029431 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:43 AM UTC 24 | 25774964 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.3070752158 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:43 AM UTC 24 | 24965609 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1187547525 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:43 AM UTC 24 | 19563569 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.2432565162 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:43 AM UTC 24 | 30835495 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.3645324713 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:43 AM UTC 24 | 14643603 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.2510709849 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:43 AM UTC 24 | 22671988 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.1067213399 | Aug 27 03:24:25 AM UTC 24 | Aug 27 03:24:43 AM UTC 24 | 13543396 ps | ||
| T578 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.1286959400 | Aug 27 03:24:25 AM UTC 24 | Aug 27 03:24:43 AM UTC 24 | 50232389 ps | ||
| T579 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.2171045800 | Aug 27 03:24:25 AM UTC 24 | Aug 27 03:24:43 AM UTC 24 | 29327819 ps | ||
| T580 | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.4150678995 | Aug 27 03:24:23 AM UTC 24 | Aug 27 03:24:44 AM UTC 24 | 208075405 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all_with_rand_reset.3383364982 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3151551435 ps |
| CPU time | 48.88 seconds |
| Started | Aug 27 03:46:16 AM UTC 24 |
| Finished | Aug 27 03:47:07 AM UTC 24 |
| Peak memory | 203968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3383364982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.rv_timer_stress_all_with_rand_reset.3383364982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.3440946899 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 384805476714 ps |
| CPU time | 156.75 seconds |
| Started | Aug 27 03:45:59 AM UTC 24 |
| Finished | Aug 27 03:48:38 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440946899 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3440946899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.577844722 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 85538289 ps |
| CPU time | 1.44 seconds |
| Started | Aug 27 03:45:59 AM UTC 24 |
| Finished | Aug 27 03:46:01 AM UTC 24 |
| Peak memory | 230928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577844722 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.577844722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.927851154 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2604546911880 ps |
| CPU time | 1734.7 seconds |
| Started | Aug 27 04:00:19 AM UTC 24 |
| Finished | Aug 27 04:29:32 AM UTC 24 |
| Peak memory | 202516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927851154 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.927851154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/33.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.3126297939 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 2238670311538 ps |
| CPU time | 6116.36 seconds |
| Started | Aug 27 03:47:22 AM UTC 24 |
| Finished | Aug 27 05:30:21 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126297939 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.3126297939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/7.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.1172888082 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1362755228820 ps |
| CPU time | 2266.82 seconds |
| Started | Aug 27 03:45:37 AM UTC 24 |
| Finished | Aug 27 04:23:47 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172888082 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.1172888082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.2410134713 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 1666423045626 ps |
| CPU time | 1004.17 seconds |
| Started | Aug 27 04:01:03 AM UTC 24 |
| Finished | Aug 27 04:17:57 AM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410134713 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.2410134713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/34.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3419880561 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 468994259 ps |
| CPU time | 1.04 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:15 AM UTC 24 |
| Peak memory | 198860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419880561 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.3419880561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.1049505205 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 230394920101 ps |
| CPU time | 289.67 seconds |
| Started | Aug 27 03:47:40 AM UTC 24 |
| Finished | Aug 27 03:52:34 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049505205 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1049505205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/9.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.405367913 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1132398713004 ps |
| CPU time | 1292.9 seconds |
| Started | Aug 27 03:46:18 AM UTC 24 |
| Finished | Aug 27 04:08:06 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405367913 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.405367913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.3846998980 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 155305518 ps |
| CPU time | 0.61 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:17 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846998980 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3846998980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.1475482589 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1489241374740 ps |
| CPU time | 1606.38 seconds |
| Started | Aug 27 03:54:04 AM UTC 24 |
| Finished | Aug 27 04:21:07 AM UTC 24 |
| Peak memory | 202424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475482589 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.1475482589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/24.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.153568973 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 702544082529 ps |
| CPU time | 1945.86 seconds |
| Started | Aug 27 03:49:37 AM UTC 24 |
| Finished | Aug 27 04:22:22 AM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153568973 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.153568973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/14.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.1624828667 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2363828081469 ps |
| CPU time | 1126.07 seconds |
| Started | Aug 27 04:06:02 AM UTC 24 |
| Finished | Aug 27 04:24:59 AM UTC 24 |
| Peak memory | 202584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624828667 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.1624828667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/43.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.3363765073 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 110431836379 ps |
| CPU time | 359.2 seconds |
| Started | Aug 27 03:53:42 AM UTC 24 |
| Finished | Aug 27 03:59:46 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363765073 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3363765073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/23.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.2430374089 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1345501804120 ps |
| CPU time | 1536.63 seconds |
| Started | Aug 27 03:46:09 AM UTC 24 |
| Finished | Aug 27 04:12:03 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430374089 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.2430374089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.2640423305 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 560280454191 ps |
| CPU time | 1437 seconds |
| Started | Aug 27 04:08:34 AM UTC 24 |
| Finished | Aug 27 04:32:45 AM UTC 24 |
| Peak memory | 202352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640423305 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.2640423305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/46.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.420109442 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1103749696683 ps |
| CPU time | 1330.86 seconds |
| Started | Aug 27 04:10:09 AM UTC 24 |
| Finished | Aug 27 04:32:33 AM UTC 24 |
| Peak memory | 202484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420109442 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.420109442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/49.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.2122494325 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 178091120634 ps |
| CPU time | 516.11 seconds |
| Started | Aug 27 03:49:06 AM UTC 24 |
| Finished | Aug 27 03:57:48 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122494325 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.2122494325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/13.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.489842535 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 4618749314608 ps |
| CPU time | 1967.18 seconds |
| Started | Aug 27 03:58:53 AM UTC 24 |
| Finished | Aug 27 04:32:01 AM UTC 24 |
| Peak memory | 202484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489842535 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.489842535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/30.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.1048851784 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 1274550560764 ps |
| CPU time | 1595.49 seconds |
| Started | Aug 27 04:02:23 AM UTC 24 |
| Finished | Aug 27 04:29:16 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048851784 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.1048851784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/37.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.347845790 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 644546873207 ps |
| CPU time | 171.29 seconds |
| Started | Aug 27 03:47:28 AM UTC 24 |
| Finished | Aug 27 03:50:22 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347845790 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.347845790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.123381248 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 649304350933 ps |
| CPU time | 696.23 seconds |
| Started | Aug 27 04:04:39 AM UTC 24 |
| Finished | Aug 27 04:16:23 AM UTC 24 |
| Peak memory | 199608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123381248 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.123381248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/40.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.793931644 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 33272531713 ps |
| CPU time | 76.85 seconds |
| Started | Aug 27 03:46:04 AM UTC 24 |
| Finished | Aug 27 03:47:23 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793931644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.793931644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.3754021514 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 621185673182 ps |
| CPU time | 437.45 seconds |
| Started | Aug 27 03:56:07 AM UTC 24 |
| Finished | Aug 27 04:03:30 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754021514 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3754021514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/28.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.2764590100 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 3391131760742 ps |
| CPU time | 988.66 seconds |
| Started | Aug 27 04:25:25 AM UTC 24 |
| Finished | Aug 27 04:42:06 AM UTC 24 |
| Peak memory | 202440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764590100 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2764590100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/152.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.3912043442 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 406393732803 ps |
| CPU time | 526.42 seconds |
| Started | Aug 27 03:45:28 AM UTC 24 |
| Finished | Aug 27 03:54:21 AM UTC 24 |
| Peak memory | 202324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912043442 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.3912043442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.2513701806 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 94460648608 ps |
| CPU time | 376.54 seconds |
| Started | Aug 27 04:09:06 AM UTC 24 |
| Finished | Aug 27 04:15:27 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513701806 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2513701806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/48.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.2873093260 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 606268248466 ps |
| CPU time | 1681.89 seconds |
| Started | Aug 27 04:12:49 AM UTC 24 |
| Finished | Aug 27 04:41:09 AM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873093260 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2873093260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/64.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.3791722987 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 188273192469 ps |
| CPU time | 477.79 seconds |
| Started | Aug 27 04:14:13 AM UTC 24 |
| Finished | Aug 27 04:22:17 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791722987 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3791722987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/74.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.1850420242 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 406108929785 ps |
| CPU time | 745.48 seconds |
| Started | Aug 27 04:22:23 AM UTC 24 |
| Finished | Aug 27 04:34:57 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850420242 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1850420242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/131.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.2920327636 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 191129330692 ps |
| CPU time | 741.76 seconds |
| Started | Aug 27 04:10:37 AM UTC 24 |
| Finished | Aug 27 04:23:07 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920327636 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2920327636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/53.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.1122861926 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 142184458830 ps |
| CPU time | 291.05 seconds |
| Started | Aug 27 04:20:03 AM UTC 24 |
| Finished | Aug 27 04:24:58 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122861926 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1122861926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/115.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.2895954331 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 120129179410 ps |
| CPU time | 395.78 seconds |
| Started | Aug 27 04:26:06 AM UTC 24 |
| Finished | Aug 27 04:32:47 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895954331 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2895954331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/155.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.4087218809 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 158777245192 ps |
| CPU time | 504.85 seconds |
| Started | Aug 27 03:46:13 AM UTC 24 |
| Finished | Aug 27 03:54:44 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087218809 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.4087218809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.56957855 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 702801179263 ps |
| CPU time | 1364.47 seconds |
| Started | Aug 27 04:10:09 AM UTC 24 |
| Finished | Aug 27 04:33:08 AM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56957855 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.56957855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/50.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.4228051659 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 583377448642 ps |
| CPU time | 942.13 seconds |
| Started | Aug 27 03:48:23 AM UTC 24 |
| Finished | Aug 27 04:04:15 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228051659 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.4228051659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/10.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.2959055926 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 159392427033 ps |
| CPU time | 434.89 seconds |
| Started | Aug 27 04:18:04 AM UTC 24 |
| Finished | Aug 27 04:25:24 AM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959055926 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2959055926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/100.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.2488423428 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 109184314693 ps |
| CPU time | 424.09 seconds |
| Started | Aug 27 04:18:56 AM UTC 24 |
| Finished | Aug 27 04:26:05 AM UTC 24 |
| Peak memory | 199868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488423428 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2488423428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/107.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.330552094 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1000446539197 ps |
| CPU time | 511.91 seconds |
| Started | Aug 27 03:50:22 AM UTC 24 |
| Finished | Aug 27 03:59:00 AM UTC 24 |
| Peak memory | 199748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330552094 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.330552094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/16.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.2553257956 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 517292214958 ps |
| CPU time | 1418.7 seconds |
| Started | Aug 27 04:13:19 AM UTC 24 |
| Finished | Aug 27 04:37:13 AM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553257956 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2553257956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/68.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.393860381 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 2041222108491 ps |
| CPU time | 3434.02 seconds |
| Started | Aug 27 04:18:33 AM UTC 24 |
| Finished | Aug 27 05:16:25 AM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393860381 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.393860381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/104.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.3849095571 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 130960959533 ps |
| CPU time | 392.94 seconds |
| Started | Aug 27 04:20:09 AM UTC 24 |
| Finished | Aug 27 04:26:47 AM UTC 24 |
| Peak memory | 199700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849095571 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3849095571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/116.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.1063026963 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 290611136509 ps |
| CPU time | 469.31 seconds |
| Started | Aug 27 04:26:29 AM UTC 24 |
| Finished | Aug 27 04:34:24 AM UTC 24 |
| Peak memory | 199700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063026963 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1063026963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/158.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.241086044 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1847581558174 ps |
| CPU time | 1266.24 seconds |
| Started | Aug 27 03:51:08 AM UTC 24 |
| Finished | Aug 27 04:12:27 AM UTC 24 |
| Peak memory | 202348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241086044 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.241086044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/17.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.720643525 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 249280473581 ps |
| CPU time | 279.32 seconds |
| Started | Aug 27 03:55:36 AM UTC 24 |
| Finished | Aug 27 04:00:19 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720643525 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.720643525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/27.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.1160456726 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 372723655871 ps |
| CPU time | 477.7 seconds |
| Started | Aug 27 03:57:16 AM UTC 24 |
| Finished | Aug 27 04:05:20 AM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160456726 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.1160456726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.1001603499 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 236232782751 ps |
| CPU time | 218.83 seconds |
| Started | Aug 27 04:00:24 AM UTC 24 |
| Finished | Aug 27 04:04:07 AM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001603499 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1001603499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/34.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.4057930564 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 234371636125 ps |
| CPU time | 249.29 seconds |
| Started | Aug 27 04:02:35 AM UTC 24 |
| Finished | Aug 27 04:06:48 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057930564 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.4057930564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/38.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.2547756162 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 97990788055 ps |
| CPU time | 292.43 seconds |
| Started | Aug 27 04:13:28 AM UTC 24 |
| Finished | Aug 27 04:18:25 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547756162 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2547756162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/69.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.3290153505 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 564718693076 ps |
| CPU time | 218.74 seconds |
| Started | Aug 27 04:14:50 AM UTC 24 |
| Finished | Aug 27 04:18:32 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290153505 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3290153505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/79.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.579344115 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 664864800152 ps |
| CPU time | 392.67 seconds |
| Started | Aug 27 04:17:18 AM UTC 24 |
| Finished | Aug 27 04:23:55 AM UTC 24 |
| Peak memory | 199872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579344115 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.579344115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/94.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.2208149324 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 890315238190 ps |
| CPU time | 812.94 seconds |
| Started | Aug 27 03:45:54 AM UTC 24 |
| Finished | Aug 27 03:59:35 AM UTC 24 |
| Peak memory | 202424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208149324 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.2208149324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.2271291712 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 72340677864 ps |
| CPU time | 293.28 seconds |
| Started | Aug 27 04:19:00 AM UTC 24 |
| Finished | Aug 27 04:23:57 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271291712 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2271291712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/108.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.717382970 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 483059677686 ps |
| CPU time | 231.82 seconds |
| Started | Aug 27 04:25:21 AM UTC 24 |
| Finished | Aug 27 04:29:16 AM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717382970 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.717382970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/151.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.1782749726 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 516981427369 ps |
| CPU time | 1332.99 seconds |
| Started | Aug 27 04:31:47 AM UTC 24 |
| Finished | Aug 27 04:54:14 AM UTC 24 |
| Peak memory | 202484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782749726 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1782749726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/199.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.3183109145 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 563619898601 ps |
| CPU time | 1179.81 seconds |
| Started | Aug 27 03:57:40 AM UTC 24 |
| Finished | Aug 27 04:17:33 AM UTC 24 |
| Peak memory | 202352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183109145 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.3183109145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/29.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4085582531 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 45048964 ps |
| CPU time | 0.73 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:15 AM UTC 24 |
| Peak memory | 196984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085582531 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.4085582531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4073948861 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 1161676036 ps |
| CPU time | 1.37 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:16 AM UTC 24 |
| Peak memory | 198264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073948861 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.4073948861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.2894397568 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 575369518549 ps |
| CPU time | 616.1 seconds |
| Started | Aug 27 03:45:44 AM UTC 24 |
| Finished | Aug 27 03:56:07 AM UTC 24 |
| Peak memory | 202648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894397568 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2894397568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.3773953566 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 87773984501 ps |
| CPU time | 239.05 seconds |
| Started | Aug 27 03:48:10 AM UTC 24 |
| Finished | Aug 27 03:52:13 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773953566 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3773953566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/10.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.3794070968 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 284191099850 ps |
| CPU time | 125.81 seconds |
| Started | Aug 27 04:18:25 AM UTC 24 |
| Finished | Aug 27 04:20:33 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794070968 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3794070968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/103.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.2870739752 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 273028193736 ps |
| CPU time | 184.07 seconds |
| Started | Aug 27 04:22:10 AM UTC 24 |
| Finished | Aug 27 04:25:17 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870739752 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2870739752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/128.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.33133359 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 45485642196 ps |
| CPU time | 52.94 seconds |
| Started | Aug 27 04:22:18 AM UTC 24 |
| Finished | Aug 27 04:23:12 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33133359 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.33133359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/129.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.553375075 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 98978340408 ps |
| CPU time | 194.75 seconds |
| Started | Aug 27 03:48:45 AM UTC 24 |
| Finished | Aug 27 03:52:02 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553375075 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.553375075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/13.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.1691483174 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 2383971877453 ps |
| CPU time | 818.88 seconds |
| Started | Aug 27 04:22:52 AM UTC 24 |
| Finished | Aug 27 04:36:40 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691483174 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1691483174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/134.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.808609529 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 101759988118 ps |
| CPU time | 202.73 seconds |
| Started | Aug 27 04:25:03 AM UTC 24 |
| Finished | Aug 27 04:28:29 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808609529 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.808609529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/146.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.1220193653 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 192135776029 ps |
| CPU time | 629.79 seconds |
| Started | Aug 27 04:26:47 AM UTC 24 |
| Finished | Aug 27 04:37:24 AM UTC 24 |
| Peak memory | 199904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220193653 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1220193653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/161.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.3105756120 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 108134929596 ps |
| CPU time | 848.34 seconds |
| Started | Aug 27 04:26:48 AM UTC 24 |
| Finished | Aug 27 04:41:06 AM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105756120 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3105756120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/162.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.1907245181 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 349454926375 ps |
| CPU time | 417.35 seconds |
| Started | Aug 27 04:26:54 AM UTC 24 |
| Finished | Aug 27 04:33:58 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907245181 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1907245181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/163.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.577569873 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 137827339435 ps |
| CPU time | 234.13 seconds |
| Started | Aug 27 04:26:58 AM UTC 24 |
| Finished | Aug 27 04:30:55 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577569873 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.577569873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/165.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.1822051864 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 581704690655 ps |
| CPU time | 445.59 seconds |
| Started | Aug 27 04:29:32 AM UTC 24 |
| Finished | Aug 27 04:37:04 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822051864 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1822051864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/182.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.1618377602 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 65680145904 ps |
| CPU time | 115.88 seconds |
| Started | Aug 27 03:52:02 AM UTC 24 |
| Finished | Aug 27 03:54:00 AM UTC 24 |
| Peak memory | 199748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618377602 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.1618377602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.23966059 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 55827020406 ps |
| CPU time | 32.37 seconds |
| Started | Aug 27 04:30:56 AM UTC 24 |
| Finished | Aug 27 04:31:30 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23966059 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.23966059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/191.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.3689992859 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 722777872568 ps |
| CPU time | 659.16 seconds |
| Started | Aug 27 03:53:44 AM UTC 24 |
| Finished | Aug 27 04:04:50 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689992859 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.3689992859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.3824813754 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 624434690348 ps |
| CPU time | 1222.41 seconds |
| Started | Aug 27 04:09:38 AM UTC 24 |
| Finished | Aug 27 04:30:13 AM UTC 24 |
| Peak memory | 202488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824813754 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.3824813754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/48.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.1049402481 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 195890223108 ps |
| CPU time | 813.78 seconds |
| Started | Aug 27 04:12:45 AM UTC 24 |
| Finished | Aug 27 04:26:27 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049402481 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1049402481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/63.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.890279603 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 129408234870 ps |
| CPU time | 1380.53 seconds |
| Started | Aug 27 03:45:25 AM UTC 24 |
| Finished | Aug 27 04:08:42 AM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890279603 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.890279603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.3126622410 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 455988382658 ps |
| CPU time | 155.63 seconds |
| Started | Aug 27 03:45:31 AM UTC 24 |
| Finished | Aug 27 03:48:09 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126622410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3126622410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.3477228118 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 339715801373 ps |
| CPU time | 537.5 seconds |
| Started | Aug 27 04:18:16 AM UTC 24 |
| Finished | Aug 27 04:27:20 AM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477228118 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3477228118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/102.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.4176335342 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 123490190532 ps |
| CPU time | 328.04 seconds |
| Started | Aug 27 03:48:23 AM UTC 24 |
| Finished | Aug 27 03:53:55 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176335342 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.4176335342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/11.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.503793461 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 89432430916 ps |
| CPU time | 610.83 seconds |
| Started | Aug 27 04:21:07 AM UTC 24 |
| Finished | Aug 27 04:31:25 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503793461 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.503793461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/121.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.1188823071 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 506519496850 ps |
| CPU time | 2240.25 seconds |
| Started | Aug 27 04:21:15 AM UTC 24 |
| Finished | Aug 27 04:59:00 AM UTC 24 |
| Peak memory | 202544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188823071 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1188823071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/122.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.2789347609 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 260638675564 ps |
| CPU time | 185.56 seconds |
| Started | Aug 27 04:21:54 AM UTC 24 |
| Finished | Aug 27 04:25:02 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789347609 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2789347609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/127.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.3224065512 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 140131066984 ps |
| CPU time | 1959.9 seconds |
| Started | Aug 27 04:22:33 AM UTC 24 |
| Finished | Aug 27 04:55:35 AM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224065512 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3224065512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/132.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.3777464782 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 1862845333830 ps |
| CPU time | 798.99 seconds |
| Started | Aug 27 04:23:08 AM UTC 24 |
| Finished | Aug 27 04:36:37 AM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777464782 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3777464782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/135.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.784785684 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 199739932712 ps |
| CPU time | 655.6 seconds |
| Started | Aug 27 04:25:18 AM UTC 24 |
| Finished | Aug 27 04:36:21 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784785684 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.784785684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/150.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.3943134964 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 382387464568 ps |
| CPU time | 565.99 seconds |
| Started | Aug 27 04:27:41 AM UTC 24 |
| Finished | Aug 27 04:37:14 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943134964 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3943134964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/169.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.929245342 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 316553392438 ps |
| CPU time | 474.8 seconds |
| Started | Aug 27 04:28:34 AM UTC 24 |
| Finished | Aug 27 04:36:35 AM UTC 24 |
| Peak memory | 199608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929245342 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.929245342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/174.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.3461415099 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 462037491616 ps |
| CPU time | 214.07 seconds |
| Started | Aug 27 03:59:44 AM UTC 24 |
| Finished | Aug 27 04:03:21 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461415099 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3461415099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/32.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.2280048029 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1297578617831 ps |
| CPU time | 683.49 seconds |
| Started | Aug 27 04:01:42 AM UTC 24 |
| Finished | Aug 27 04:13:13 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280048029 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.2280048029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.3171003105 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 129976744674 ps |
| CPU time | 1747.85 seconds |
| Started | Aug 27 04:01:29 AM UTC 24 |
| Finished | Aug 27 04:30:57 AM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171003105 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3171003105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/36.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.3614477949 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 93694180910 ps |
| CPU time | 127.55 seconds |
| Started | Aug 27 04:04:13 AM UTC 24 |
| Finished | Aug 27 04:06:22 AM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614477949 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.3614477949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/39.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.63784504 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 81900028192 ps |
| CPU time | 103.35 seconds |
| Started | Aug 27 04:04:13 AM UTC 24 |
| Finished | Aug 27 04:05:58 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63784504 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.63784504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/40.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.412945957 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 394244641096 ps |
| CPU time | 515.75 seconds |
| Started | Aug 27 04:10:40 AM UTC 24 |
| Finished | Aug 27 04:19:22 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412945957 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.412945957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/54.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.430384119 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 28194750390 ps |
| CPU time | 297.26 seconds |
| Started | Aug 27 04:11:14 AM UTC 24 |
| Finished | Aug 27 04:16:15 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430384119 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.430384119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/56.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.180499879 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 286560004 ps |
| CPU time | 3.38 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:18 AM UTC 24 |
| Peak memory | 198736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180499879 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.180499879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.653861937 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 63675006 ps |
| CPU time | 0.61 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:15 AM UTC 24 |
| Peak memory | 197596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653861937 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.653861937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.906185646 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 35294810 ps |
| CPU time | 0.9 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:15 AM UTC 24 |
| Peak memory | 198832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=906185646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr _mem_rw_with_rand_reset.906185646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.4084410487 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 45672008 ps |
| CPU time | 0.54 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:15 AM UTC 24 |
| Peak memory | 196928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084410487 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.4084410487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.3706529475 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 13619628 ps |
| CPU time | 0.59 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:15 AM UTC 24 |
| Peak memory | 197024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706529475 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3706529475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4153774888 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 39260062 ps |
| CPU time | 0.7 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:15 AM UTC 24 |
| Peak memory | 198196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153774888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.4153774888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.2667544310 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 328264273 ps |
| CPU time | 1.49 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:16 AM UTC 24 |
| Peak memory | 197508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667544310 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2667544310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.86745453 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 95161058 ps |
| CPU time | 0.53 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:16 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86745453 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.86745453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.453880281 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 248916264 ps |
| CPU time | 2.09 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:17 AM UTC 24 |
| Peak memory | 200744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453880281 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.453880281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.23950104 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 23848036 ps |
| CPU time | 0.45 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:15 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23950104 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.23950104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.729083693 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 129481244 ps |
| CPU time | 0.7 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:17 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=729083693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr _mem_rw_with_rand_reset.729083693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.3830553263 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 22249613 ps |
| CPU time | 0.51 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:15 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830553263 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3830553263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.1269531866 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 15709476 ps |
| CPU time | 0.46 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:15 AM UTC 24 |
| Peak memory | 198220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269531866 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1269531866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1368327795 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 44579133 ps |
| CPU time | 0.6 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:16 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368327795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.1368327795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.3487232201 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 144172760 ps |
| CPU time | 2.27 seconds |
| Started | Aug 27 03:24:13 AM UTC 24 |
| Finished | Aug 27 03:24:17 AM UTC 24 |
| Peak memory | 202792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487232201 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3487232201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1611414744 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 76464828 ps |
| CPU time | 0.69 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 198940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1611414744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_c sr_mem_rw_with_rand_reset.1611414744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.1608056750 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 39382993 ps |
| CPU time | 0.54 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608056750 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1608056750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.3415475501 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 53436998 ps |
| CPU time | 0.5 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415475501 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3415475501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/10.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.672509180 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 19718177 ps |
| CPU time | 0.75 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672509180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.672509180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.4204671645 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 18700151 ps |
| CPU time | 0.79 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204671645 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.4204671645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2643082756 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 302385850 ps |
| CPU time | 1.24 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:22 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643082756 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.2643082756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2074552066 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 46123974 ps |
| CPU time | 0.7 seconds |
| Started | Aug 27 03:24:20 AM UTC 24 |
| Finished | Aug 27 03:24:22 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2074552066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_c sr_mem_rw_with_rand_reset.2074552066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.1690838082 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 11379537 ps |
| CPU time | 0.53 seconds |
| Started | Aug 27 03:24:20 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690838082 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1690838082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.4127211214 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 36437982 ps |
| CPU time | 0.52 seconds |
| Started | Aug 27 03:24:20 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127211214 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4127211214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/11.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3375883365 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 30418888 ps |
| CPU time | 0.65 seconds |
| Started | Aug 27 03:24:20 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375883365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.3375883365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.2793610131 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 206235114 ps |
| CPU time | 1.18 seconds |
| Started | Aug 27 03:24:20 AM UTC 24 |
| Finished | Aug 27 03:24:22 AM UTC 24 |
| Peak memory | 198844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793610131 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2793610131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4002499428 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 183160623 ps |
| CPU time | 1.16 seconds |
| Started | Aug 27 03:24:20 AM UTC 24 |
| Finished | Aug 27 03:24:22 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002499428 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.4002499428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.4112111452 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 115194248 ps |
| CPU time | 1.19 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4112111452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_c sr_mem_rw_with_rand_reset.4112111452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.690840422 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 16452874 ps |
| CPU time | 0.51 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690840422 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.690840422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.2330353381 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 15424354 ps |
| CPU time | 0.49 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 198736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330353381 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2330353381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/12.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3535934742 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 74782301 ps |
| CPU time | 0.55 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535934742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.3535934742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.131742817 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 58399474 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131742817 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.131742817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.670445739 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 193773122 ps |
| CPU time | 0.94 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 198772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670445739 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.670445739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.358202104 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 77660468 ps |
| CPU time | 1.27 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:24 AM UTC 24 |
| Peak memory | 198960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=358202104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_cs r_mem_rw_with_rand_reset.358202104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.4254783806 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 125516301 ps |
| CPU time | 0.48 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254783806 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.4254783806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.2321240026 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 13220429 ps |
| CPU time | 0.47 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321240026 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2321240026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/13.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3932358441 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 80492758 ps |
| CPU time | 0.68 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932358441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.3932358441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.2020253641 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 236510382 ps |
| CPU time | 2.29 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:24 AM UTC 24 |
| Peak memory | 202728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020253641 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2020253641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.4161658861 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 381870754 ps |
| CPU time | 1.23 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161658861 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.4161658861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2710860794 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 27956658 ps |
| CPU time | 0.63 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2710860794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_c sr_mem_rw_with_rand_reset.2710860794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.3182189222 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 12389293 ps |
| CPU time | 0.53 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182189222 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3182189222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.1092957508 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 14068049 ps |
| CPU time | 0.48 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092957508 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1092957508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/14.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4267665372 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 16667711 ps |
| CPU time | 0.53 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267665372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.4267665372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.2445166918 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 140752612 ps |
| CPU time | 1.59 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:24 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445166918 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2445166918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4134734176 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 137474845 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134734176 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.4134734176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2414231607 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 27527779 ps |
| CPU time | 0.66 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 198920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2414231607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_c sr_mem_rw_with_rand_reset.2414231607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.2812404765 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 128359057 ps |
| CPU time | 0.46 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812404765 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2812404765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.2217653357 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 20693463 ps |
| CPU time | 0.52 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217653357 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2217653357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/15.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3945625273 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 28280139 ps |
| CPU time | 0.63 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 199080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945625273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.3945625273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.698002304 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 472992890 ps |
| CPU time | 2.01 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:25 AM UTC 24 |
| Peak memory | 200884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698002304 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.698002304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.544888728 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 214654576 ps |
| CPU time | 0.71 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544888728 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.544888728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3190477683 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 78482638 ps |
| CPU time | 0.59 seconds |
| Started | Aug 27 03:24:22 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3190477683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_c sr_mem_rw_with_rand_reset.3190477683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.3802288373 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 66514194 ps |
| CPU time | 0.49 seconds |
| Started | Aug 27 03:24:22 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 198956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802288373 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3802288373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.4008317531 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 12583411 ps |
| CPU time | 0.49 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008317531 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.4008317531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/16.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.679236743 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 36270688 ps |
| CPU time | 0.62 seconds |
| Started | Aug 27 03:24:22 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679236743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.679236743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.229551207 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 118580890 ps |
| CPU time | 1.8 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:24 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229551207 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.229551207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3795737497 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 45241075 ps |
| CPU time | 0.78 seconds |
| Started | Aug 27 03:24:21 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795737497 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.3795737497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.294847586 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 23698369 ps |
| CPU time | 0.58 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:35 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=294847586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_cs r_mem_rw_with_rand_reset.294847586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.1912719933 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 36533517 ps |
| CPU time | 0.51 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:35 AM UTC 24 |
| Peak memory | 200636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912719933 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1912719933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.3231046949 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 56803025 ps |
| CPU time | 0.48 seconds |
| Started | Aug 27 03:24:22 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231046949 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3231046949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/17.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2035037281 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 37241733 ps |
| CPU time | 0.68 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:36 AM UTC 24 |
| Peak memory | 198916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035037281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.2035037281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.3761679554 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 99605247 ps |
| CPU time | 1.81 seconds |
| Started | Aug 27 03:24:22 AM UTC 24 |
| Finished | Aug 27 03:24:25 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761679554 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3761679554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1552288881 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 201879603 ps |
| CPU time | 1.19 seconds |
| Started | Aug 27 03:24:22 AM UTC 24 |
| Finished | Aug 27 03:24:24 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552288881 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.1552288881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.231029431 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 25774964 ps |
| CPU time | 1.42 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:43 AM UTC 24 |
| Peak memory | 200952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=231029431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_cs r_mem_rw_with_rand_reset.231029431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.596288510 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 17142966 ps |
| CPU time | 0.7 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:42 AM UTC 24 |
| Peak memory | 198388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596288510 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.596288510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.3674811260 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 34266963 ps |
| CPU time | 0.49 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:42 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674811260 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3674811260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/18.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1660885444 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 15505314 ps |
| CPU time | 0.77 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:42 AM UTC 24 |
| Peak memory | 198744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660885444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.1660885444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.612960091 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 36752658 ps |
| CPU time | 1.27 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:36 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612960091 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.612960091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2612229172 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 117647562 ps |
| CPU time | 1.3 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:42 AM UTC 24 |
| Peak memory | 200704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612229172 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.2612229172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3546104728 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 131964082 ps |
| CPU time | 0.96 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:25 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3546104728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_c sr_mem_rw_with_rand_reset.3546104728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.2895494507 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 39227058 ps |
| CPU time | 0.7 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:42 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895494507 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2895494507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.3251341851 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 33082784 ps |
| CPU time | 0.53 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:42 AM UTC 24 |
| Peak memory | 198884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251341851 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3251341851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/19.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.398339897 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 30452257 ps |
| CPU time | 0.74 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:42 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398339897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.398339897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.4150678995 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 208075405 ps |
| CPU time | 2.67 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:44 AM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150678995 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.4150678995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.642294909 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 109493735 ps |
| CPU time | 0.79 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:42 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642294909 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.642294909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1176045685 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 36465372 ps |
| CPU time | 0.6 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:17 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176045685 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.1176045685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2810038348 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 1013063312 ps |
| CPU time | 2.52 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 200940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810038348 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.2810038348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.507921687 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 58755470 ps |
| CPU time | 0.52 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:16 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507921687 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.507921687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.489492092 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 123787412 ps |
| CPU time | 0.77 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:17 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=489492092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr _mem_rw_with_rand_reset.489492092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.1297426326 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 16872747 ps |
| CPU time | 0.65 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:16 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297426326 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1297426326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.966208012 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 13836470 ps |
| CPU time | 0.61 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:17 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966208012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.966208012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.2841400558 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 435705604 ps |
| CPU time | 1.36 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:17 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841400558 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2841400558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.157886397 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 220114124 ps |
| CPU time | 1.22 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:17 AM UTC 24 |
| Peak memory | 198640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157886397 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.157886397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.144986823 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 41023290 ps |
| CPU time | 0.5 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:25 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144986823 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.144986823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/20.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1187547525 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 19563569 ps |
| CPU time | 0.51 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:43 AM UTC 24 |
| Peak memory | 198960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187547525 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1187547525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/21.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.3070752158 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 24965609 ps |
| CPU time | 0.46 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:43 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070752158 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3070752158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/22.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.2684922550 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 178019951 ps |
| CPU time | 0.53 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:43 AM UTC 24 |
| Peak memory | 198764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684922550 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2684922550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/23.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.2510709849 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 22671988 ps |
| CPU time | 0.63 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:43 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510709849 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2510709849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/24.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.3645324713 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 14643603 ps |
| CPU time | 0.62 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:43 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645324713 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3645324713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/25.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.2065004804 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 42422444 ps |
| CPU time | 0.65 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:43 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065004804 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2065004804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/26.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.2997964251 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 19250993 ps |
| CPU time | 0.54 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:43 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997964251 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2997964251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/27.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.3984594914 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 25357944 ps |
| CPU time | 0.52 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:43 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984594914 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3984594914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/28.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.2432565162 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 30835495 ps |
| CPU time | 0.62 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:43 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432565162 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2432565162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/29.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2581884176 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 38647239 ps |
| CPU time | 0.54 seconds |
| Started | Aug 27 03:24:16 AM UTC 24 |
| Finished | Aug 27 03:24:18 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581884176 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.2581884176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.263081659 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 143402663 ps |
| CPU time | 1.48 seconds |
| Started | Aug 27 03:24:16 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 198964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263081659 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.263081659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4104811291 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 46974412 ps |
| CPU time | 0.56 seconds |
| Started | Aug 27 03:24:16 AM UTC 24 |
| Finished | Aug 27 03:24:18 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104811291 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.4104811291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1355817732 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 57539978 ps |
| CPU time | 0.73 seconds |
| Started | Aug 27 03:24:16 AM UTC 24 |
| Finished | Aug 27 03:24:18 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1355817732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_cs r_mem_rw_with_rand_reset.1355817732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.2209366425 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 17076358 ps |
| CPU time | 0.67 seconds |
| Started | Aug 27 03:24:16 AM UTC 24 |
| Finished | Aug 27 03:24:18 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209366425 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2209366425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.3555893863 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 15887452 ps |
| CPU time | 0.58 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:17 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555893863 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3555893863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.517421664 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 162976814 ps |
| CPU time | 0.54 seconds |
| Started | Aug 27 03:24:16 AM UTC 24 |
| Finished | Aug 27 03:24:18 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517421664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.517421664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.2041948415 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 67246685 ps |
| CPU time | 1.59 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:18 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041948415 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2041948415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2038883374 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 232212483 ps |
| CPU time | 1.29 seconds |
| Started | Aug 27 03:24:15 AM UTC 24 |
| Finished | Aug 27 03:24:17 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038883374 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.2038883374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.162953528 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 100220525 ps |
| CPU time | 0.63 seconds |
| Started | Aug 27 03:24:23 AM UTC 24 |
| Finished | Aug 27 03:24:42 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162953528 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.162953528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/30.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.1286959400 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 50232389 ps |
| CPU time | 0.54 seconds |
| Started | Aug 27 03:24:25 AM UTC 24 |
| Finished | Aug 27 03:24:43 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286959400 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1286959400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/31.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.2171045800 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 29327819 ps |
| CPU time | 0.5 seconds |
| Started | Aug 27 03:24:25 AM UTC 24 |
| Finished | Aug 27 03:24:43 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171045800 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2171045800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/32.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.1067213399 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 13543396 ps |
| CPU time | 0.54 seconds |
| Started | Aug 27 03:24:25 AM UTC 24 |
| Finished | Aug 27 03:24:43 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067213399 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1067213399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/33.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.2545513622 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 24293903 ps |
| CPU time | 0.48 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:30 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545513622 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2545513622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/34.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.4259729287 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 139627903 ps |
| CPU time | 0.47 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:30 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259729287 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.4259729287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/35.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.1161495369 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 14219331 ps |
| CPU time | 0.46 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:30 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161495369 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1161495369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/36.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.4070335143 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 51088880 ps |
| CPU time | 0.47 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:31 AM UTC 24 |
| Peak memory | 198844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070335143 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.4070335143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/37.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.1451576781 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 15921391 ps |
| CPU time | 0.46 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:31 AM UTC 24 |
| Peak memory | 198052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451576781 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1451576781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/38.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.4271096089 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 13722451 ps |
| CPU time | 0.46 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:31 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271096089 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4271096089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/39.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2048874306 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 89391794 ps |
| CPU time | 0.65 seconds |
| Started | Aug 27 03:24:17 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 198000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048874306 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.2048874306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1349182267 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 1572016502 ps |
| CPU time | 3.28 seconds |
| Started | Aug 27 03:24:17 AM UTC 24 |
| Finished | Aug 27 03:24:22 AM UTC 24 |
| Peak memory | 200740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349182267 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.1349182267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1017175482 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 60155794 ps |
| CPU time | 0.57 seconds |
| Started | Aug 27 03:24:16 AM UTC 24 |
| Finished | Aug 27 03:24:18 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017175482 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.1017175482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.689657927 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 33249455 ps |
| CPU time | 0.58 seconds |
| Started | Aug 27 03:24:17 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 198136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=689657927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr _mem_rw_with_rand_reset.689657927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.1810797535 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 12224383 ps |
| CPU time | 0.58 seconds |
| Started | Aug 27 03:24:17 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810797535 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1810797535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.16687072 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 53076470 ps |
| CPU time | 0.49 seconds |
| Started | Aug 27 03:24:16 AM UTC 24 |
| Finished | Aug 27 03:24:18 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16687072 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.16687072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2857059100 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 85403261 ps |
| CPU time | 0.74 seconds |
| Started | Aug 27 03:24:17 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857059100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.2857059100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.1037194208 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 131336640 ps |
| CPU time | 1.86 seconds |
| Started | Aug 27 03:24:16 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037194208 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1037194208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2930200291 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 107959020 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 03:24:16 AM UTC 24 |
| Finished | Aug 27 03:24:18 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930200291 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.2930200291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.2186539724 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 30563529 ps |
| CPU time | 0.5 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:31 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186539724 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2186539724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/40.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.652014990 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 15830826 ps |
| CPU time | 0.48 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:31 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652014990 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.652014990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/41.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.4290981940 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 15769618 ps |
| CPU time | 0.49 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:31 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290981940 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.4290981940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/42.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.3837199079 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 18306662 ps |
| CPU time | 0.49 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:31 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837199079 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3837199079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/43.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.337879990 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 43300287 ps |
| CPU time | 0.47 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:31 AM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337879990 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.337879990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/44.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1554577142 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 53209215 ps |
| CPU time | 0.49 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:31 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554577142 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1554577142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/45.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.3634700530 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 41126274 ps |
| CPU time | 0.46 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:31 AM UTC 24 |
| Peak memory | 198844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634700530 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3634700530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/46.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.473762208 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 38621839 ps |
| CPU time | 0.51 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:31 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473762208 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.473762208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/47.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.3021472274 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 13514453 ps |
| CPU time | 0.48 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:41 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021472274 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3021472274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/48.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.987743724 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 46093551 ps |
| CPU time | 0.47 seconds |
| Started | Aug 27 03:24:26 AM UTC 24 |
| Finished | Aug 27 03:24:41 AM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987743724 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.987743724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/49.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3235583811 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 37107928 ps |
| CPU time | 0.77 seconds |
| Started | Aug 27 03:24:18 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3235583811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_cs r_mem_rw_with_rand_reset.3235583811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.3381083592 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 38971550 ps |
| CPU time | 0.54 seconds |
| Started | Aug 27 03:24:17 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 199024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381083592 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3381083592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.1190237487 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 55726854 ps |
| CPU time | 0.48 seconds |
| Started | Aug 27 03:24:17 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 198948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190237487 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1190237487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/5.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2055217783 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 19262886 ps |
| CPU time | 0.51 seconds |
| Started | Aug 27 03:24:17 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055217783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.2055217783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.3028367599 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 60104196 ps |
| CPU time | 0.87 seconds |
| Started | Aug 27 03:24:17 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028367599 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3028367599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4156284176 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 297038333 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 03:24:17 AM UTC 24 |
| Finished | Aug 27 03:24:20 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156284176 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.4156284176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1674690476 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 38195972 ps |
| CPU time | 1.1 seconds |
| Started | Aug 27 03:24:18 AM UTC 24 |
| Finished | Aug 27 03:24:20 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1674690476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_cs r_mem_rw_with_rand_reset.1674690476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.2629299138 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 53239734 ps |
| CPU time | 0.51 seconds |
| Started | Aug 27 03:24:18 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 198992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629299138 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2629299138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.1260484786 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 44668216 ps |
| CPU time | 0.51 seconds |
| Started | Aug 27 03:24:18 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260484786 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1260484786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/6.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2201227046 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 192725147 ps |
| CPU time | 0.72 seconds |
| Started | Aug 27 03:24:18 AM UTC 24 |
| Finished | Aug 27 03:24:20 AM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201227046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.2201227046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.3348149833 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 196310215 ps |
| CPU time | 2.2 seconds |
| Started | Aug 27 03:24:18 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 200756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348149833 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3348149833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2645935607 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 177159279 ps |
| CPU time | 0.87 seconds |
| Started | Aug 27 03:24:18 AM UTC 24 |
| Finished | Aug 27 03:24:20 AM UTC 24 |
| Peak memory | 199096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645935607 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.2645935607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.4095296796 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 56601553 ps |
| CPU time | 0.87 seconds |
| Started | Aug 27 03:24:18 AM UTC 24 |
| Finished | Aug 27 03:24:20 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4095296796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_cs r_mem_rw_with_rand_reset.4095296796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.1960119681 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 26068913 ps |
| CPU time | 0.54 seconds |
| Started | Aug 27 03:24:18 AM UTC 24 |
| Finished | Aug 27 03:24:20 AM UTC 24 |
| Peak memory | 198808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960119681 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1960119681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.3472522796 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 12378534 ps |
| CPU time | 0.5 seconds |
| Started | Aug 27 03:24:18 AM UTC 24 |
| Finished | Aug 27 03:24:19 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472522796 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3472522796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/7.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1693724440 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 94854751 ps |
| CPU time | 0.64 seconds |
| Started | Aug 27 03:24:18 AM UTC 24 |
| Finished | Aug 27 03:24:20 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693724440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.1693724440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.590969729 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 169769281 ps |
| CPU time | 1.84 seconds |
| Started | Aug 27 03:24:18 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 198704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590969729 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.590969729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1147693212 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 197567635 ps |
| CPU time | 1.27 seconds |
| Started | Aug 27 03:24:18 AM UTC 24 |
| Finished | Aug 27 03:24:20 AM UTC 24 |
| Peak memory | 198928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147693212 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.1147693212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1403850520 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 17942703 ps |
| CPU time | 0.77 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1403850520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_cs r_mem_rw_with_rand_reset.1403850520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.49447484 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 14884365 ps |
| CPU time | 0.5 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49447484 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.49447484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.2931803065 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 55565464 ps |
| CPU time | 0.51 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931803065 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2931803065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/8.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.297220843 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 24768453 ps |
| CPU time | 0.55 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297220843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.297220843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.3859870864 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 363224267 ps |
| CPU time | 1.5 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:22 AM UTC 24 |
| Peak memory | 201148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859870864 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3859870864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2547227254 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 111286286 ps |
| CPU time | 0.89 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547227254 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.2547227254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2916452729 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 50573847 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:22 AM UTC 24 |
| Peak memory | 201024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2916452729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_cs r_mem_rw_with_rand_reset.2916452729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.915962317 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 47462152 ps |
| CPU time | 0.52 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 198592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915962317 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.915962317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.3418944360 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 37686856 ps |
| CPU time | 0.46 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418944360 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3418944360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/9.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3168158990 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 14339029 ps |
| CPU time | 0.55 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 198516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168158990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.3168158990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.3064942791 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 233022180 ps |
| CPU time | 2.46 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:23 AM UTC 24 |
| Peak memory | 200684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064942791 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3064942791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2897921720 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 89128564 ps |
| CPU time | 0.73 seconds |
| Started | Aug 27 03:24:19 AM UTC 24 |
| Finished | Aug 27 03:24:21 AM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897921720 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.2897921720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.3865445034 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 167608979611 ps |
| CPU time | 317.64 seconds |
| Started | Aug 27 03:45:25 AM UTC 24 |
| Finished | Aug 27 03:50:47 AM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865445034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3865445034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.3299195590 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 72839603 ps |
| CPU time | 1.28 seconds |
| Started | Aug 27 03:45:40 AM UTC 24 |
| Finished | Aug 27 03:45:43 AM UTC 24 |
| Peak memory | 229300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299195590 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3299195590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.2023411021 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 167567044092 ps |
| CPU time | 275.75 seconds |
| Started | Aug 27 03:45:50 AM UTC 24 |
| Finished | Aug 27 03:50:29 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023411021 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.2023411021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.514363767 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 208383668619 ps |
| CPU time | 163.3 seconds |
| Started | Aug 27 03:45:44 AM UTC 24 |
| Finished | Aug 27 03:48:29 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514363767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.514363767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.4263992485 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 738235584775 ps |
| CPU time | 807.78 seconds |
| Started | Aug 27 03:45:50 AM UTC 24 |
| Finished | Aug 27 03:59:27 AM UTC 24 |
| Peak memory | 202412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263992485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.4263992485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/1.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.95335615 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 181972134992 ps |
| CPU time | 158.12 seconds |
| Started | Aug 27 03:48:17 AM UTC 24 |
| Finished | Aug 27 03:50:58 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95335615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.95335615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.925449553 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 376703358474 ps |
| CPU time | 234.86 seconds |
| Started | Aug 27 03:48:13 AM UTC 24 |
| Finished | Aug 27 03:52:11 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925449553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.925449553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/10.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.3846958241 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 3254514370 ps |
| CPU time | 1.59 seconds |
| Started | Aug 27 03:48:20 AM UTC 24 |
| Finished | Aug 27 03:48:22 AM UTC 24 |
| Peak memory | 198940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846958241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3846958241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/10.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.1670838998 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 62329739453 ps |
| CPU time | 176.94 seconds |
| Started | Aug 27 04:18:14 AM UTC 24 |
| Finished | Aug 27 04:21:14 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670838998 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1670838998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/101.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.415635649 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 159088486545 ps |
| CPU time | 443.98 seconds |
| Started | Aug 27 04:18:44 AM UTC 24 |
| Finished | Aug 27 04:26:13 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415635649 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.415635649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/105.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.826271346 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 807974981810 ps |
| CPU time | 656.48 seconds |
| Started | Aug 27 04:18:56 AM UTC 24 |
| Finished | Aug 27 04:30:00 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826271346 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.826271346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/106.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.2937316347 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 394963724 ps |
| CPU time | 1.38 seconds |
| Started | Aug 27 04:19:15 AM UTC 24 |
| Finished | Aug 27 04:19:17 AM UTC 24 |
| Peak memory | 198932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937316347 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2937316347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/109.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.3151215391 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 266784958362 ps |
| CPU time | 260.8 seconds |
| Started | Aug 27 03:48:28 AM UTC 24 |
| Finished | Aug 27 03:52:52 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151215391 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.3151215391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.3260213757 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 122263709756 ps |
| CPU time | 163.71 seconds |
| Started | Aug 27 03:48:25 AM UTC 24 |
| Finished | Aug 27 03:51:11 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260213757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3260213757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/11.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.3585942711 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 120307867 ps |
| CPU time | 1.68 seconds |
| Started | Aug 27 03:48:32 AM UTC 24 |
| Finished | Aug 27 03:48:35 AM UTC 24 |
| Peak memory | 198932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585942711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3585942711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/11.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.2321934362 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 1410973981314 ps |
| CPU time | 625.76 seconds |
| Started | Aug 27 03:48:32 AM UTC 24 |
| Finished | Aug 27 03:59:04 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321934362 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.2321934362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/11.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.3386656461 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 19319970131 ps |
| CPU time | 47.98 seconds |
| Started | Aug 27 04:19:18 AM UTC 24 |
| Finished | Aug 27 04:20:08 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386656461 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3386656461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/110.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.2305415270 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 76337855128 ps |
| CPU time | 120.7 seconds |
| Started | Aug 27 04:19:23 AM UTC 24 |
| Finished | Aug 27 04:21:27 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305415270 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2305415270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/111.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.2238283765 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 119612336796 ps |
| CPU time | 724.16 seconds |
| Started | Aug 27 04:19:33 AM UTC 24 |
| Finished | Aug 27 04:31:46 AM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238283765 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2238283765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/112.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.3737450606 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 184782956 ps |
| CPU time | 1.49 seconds |
| Started | Aug 27 04:19:47 AM UTC 24 |
| Finished | Aug 27 04:19:50 AM UTC 24 |
| Peak memory | 198932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737450606 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3737450606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/113.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.1024790737 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 659393675122 ps |
| CPU time | 950.39 seconds |
| Started | Aug 27 04:19:50 AM UTC 24 |
| Finished | Aug 27 04:35:52 AM UTC 24 |
| Peak memory | 202580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024790737 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1024790737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/114.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.3923051167 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 444127899420 ps |
| CPU time | 779.4 seconds |
| Started | Aug 27 04:20:24 AM UTC 24 |
| Finished | Aug 27 04:33:33 AM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923051167 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3923051167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/117.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.1764564586 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 139173015735 ps |
| CPU time | 231.17 seconds |
| Started | Aug 27 04:20:27 AM UTC 24 |
| Finished | Aug 27 04:24:21 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764564586 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1764564586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/118.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.777416676 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 69476195822 ps |
| CPU time | 55.75 seconds |
| Started | Aug 27 04:20:34 AM UTC 24 |
| Finished | Aug 27 04:21:31 AM UTC 24 |
| Peak memory | 199456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777416676 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.777416676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/119.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.1387096414 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 19519301978 ps |
| CPU time | 28.63 seconds |
| Started | Aug 27 03:48:36 AM UTC 24 |
| Finished | Aug 27 03:49:06 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387096414 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.1387096414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.2456092342 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 58556732171 ps |
| CPU time | 49.87 seconds |
| Started | Aug 27 03:48:35 AM UTC 24 |
| Finished | Aug 27 03:49:27 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456092342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2456092342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/12.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.3994764204 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 129699605168 ps |
| CPU time | 744.02 seconds |
| Started | Aug 27 03:48:32 AM UTC 24 |
| Finished | Aug 27 04:01:05 AM UTC 24 |
| Peak memory | 199748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994764204 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3994764204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/12.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.1268197279 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 37929099983 ps |
| CPU time | 24.6 seconds |
| Started | Aug 27 03:48:37 AM UTC 24 |
| Finished | Aug 27 03:49:03 AM UTC 24 |
| Peak memory | 199540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268197279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1268197279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/12.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.647019133 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 405329694435 ps |
| CPU time | 661.26 seconds |
| Started | Aug 27 03:48:39 AM UTC 24 |
| Finished | Aug 27 03:59:47 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647019133 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.647019133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/12.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.1452479333 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 198160496266 ps |
| CPU time | 240.45 seconds |
| Started | Aug 27 04:20:58 AM UTC 24 |
| Finished | Aug 27 04:25:02 AM UTC 24 |
| Peak memory | 199700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452479333 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1452479333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/120.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.3607199735 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 83162493524 ps |
| CPU time | 446.07 seconds |
| Started | Aug 27 04:21:27 AM UTC 24 |
| Finished | Aug 27 04:28:59 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607199735 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3607199735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/123.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.4136407531 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 38591442950 ps |
| CPU time | 64.57 seconds |
| Started | Aug 27 04:21:31 AM UTC 24 |
| Finished | Aug 27 04:22:38 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136407531 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.4136407531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/124.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.935075380 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 158970374890 ps |
| CPU time | 436.23 seconds |
| Started | Aug 27 04:21:49 AM UTC 24 |
| Finished | Aug 27 04:29:10 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935075380 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.935075380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/125.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.194598558 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 249048486900 ps |
| CPU time | 1220.52 seconds |
| Started | Aug 27 04:21:54 AM UTC 24 |
| Finished | Aug 27 04:42:27 AM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194598558 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.194598558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/126.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.470440408 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 279248500724 ps |
| CPU time | 493.35 seconds |
| Started | Aug 27 03:48:57 AM UTC 24 |
| Finished | Aug 27 03:57:15 AM UTC 24 |
| Peak memory | 199584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470440408 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.470440408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.660458277 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 328423444810 ps |
| CPU time | 108.92 seconds |
| Started | Aug 27 03:48:57 AM UTC 24 |
| Finished | Aug 27 03:50:48 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660458277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.660458277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/13.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.2788077103 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 537902141578 ps |
| CPU time | 173.32 seconds |
| Started | Aug 27 03:49:00 AM UTC 24 |
| Finished | Aug 27 03:51:56 AM UTC 24 |
| Peak memory | 199816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788077103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2788077103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/13.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all_with_rand_reset.2670092293 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 297820157 ps |
| CPU time | 2.45 seconds |
| Started | Aug 27 03:49:04 AM UTC 24 |
| Finished | Aug 27 03:49:07 AM UTC 24 |
| Peak memory | 201776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2670092293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.rv_timer_stress_all_with_rand_reset.2670092293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/13.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.1107241404 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 184125780373 ps |
| CPU time | 261.08 seconds |
| Started | Aug 27 04:22:19 AM UTC 24 |
| Finished | Aug 27 04:26:44 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107241404 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1107241404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/130.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.431891251 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 405488844440 ps |
| CPU time | 245.85 seconds |
| Started | Aug 27 04:22:38 AM UTC 24 |
| Finished | Aug 27 04:26:48 AM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431891251 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.431891251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/133.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.3168531794 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 149628315259 ps |
| CPU time | 727.07 seconds |
| Started | Aug 27 04:23:13 AM UTC 24 |
| Finished | Aug 27 04:35:29 AM UTC 24 |
| Peak memory | 199604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168531794 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3168531794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/136.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.2961652130 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 191702728250 ps |
| CPU time | 87.36 seconds |
| Started | Aug 27 04:23:24 AM UTC 24 |
| Finished | Aug 27 04:24:53 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961652130 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2961652130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/137.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.1831990432 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 86088287187 ps |
| CPU time | 298.82 seconds |
| Started | Aug 27 04:23:28 AM UTC 24 |
| Finished | Aug 27 04:28:30 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831990432 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1831990432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/138.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.1882591853 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 167864592889 ps |
| CPU time | 815.91 seconds |
| Started | Aug 27 04:23:48 AM UTC 24 |
| Finished | Aug 27 04:37:33 AM UTC 24 |
| Peak memory | 200012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882591853 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1882591853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/139.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.1615701171 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 727905656756 ps |
| CPU time | 356.53 seconds |
| Started | Aug 27 03:49:09 AM UTC 24 |
| Finished | Aug 27 03:55:10 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615701171 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.1615701171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.4111919758 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 17107555543 ps |
| CPU time | 45.54 seconds |
| Started | Aug 27 03:49:09 AM UTC 24 |
| Finished | Aug 27 03:49:56 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111919758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.4111919758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/14.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.2540165052 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 227706636533 ps |
| CPU time | 270.86 seconds |
| Started | Aug 27 03:49:09 AM UTC 24 |
| Finished | Aug 27 03:53:43 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540165052 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2540165052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/14.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.2015433414 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 48744798201 ps |
| CPU time | 82.79 seconds |
| Started | Aug 27 03:49:21 AM UTC 24 |
| Finished | Aug 27 03:50:45 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015433414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2015433414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/14.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.3346685264 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 170427633326 ps |
| CPU time | 922.7 seconds |
| Started | Aug 27 04:23:56 AM UTC 24 |
| Finished | Aug 27 04:39:29 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346685264 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3346685264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/140.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.2077858118 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 263313735438 ps |
| CPU time | 332.88 seconds |
| Started | Aug 27 04:23:58 AM UTC 24 |
| Finished | Aug 27 04:29:35 AM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077858118 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2077858118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/141.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.3946378369 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 33000553091 ps |
| CPU time | 45.76 seconds |
| Started | Aug 27 04:24:23 AM UTC 24 |
| Finished | Aug 27 04:25:10 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946378369 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3946378369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/142.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.878856424 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 316173838848 ps |
| CPU time | 163.12 seconds |
| Started | Aug 27 04:24:54 AM UTC 24 |
| Finished | Aug 27 04:27:39 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878856424 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.878856424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/143.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.2834186207 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 437455164088 ps |
| CPU time | 2080.48 seconds |
| Started | Aug 27 04:24:59 AM UTC 24 |
| Finished | Aug 27 05:00:03 AM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834186207 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2834186207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/144.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.4072057408 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 44563788212 ps |
| CPU time | 140.94 seconds |
| Started | Aug 27 04:25:00 AM UTC 24 |
| Finished | Aug 27 04:27:23 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072057408 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.4072057408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/145.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.385711280 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 159137876156 ps |
| CPU time | 310.26 seconds |
| Started | Aug 27 04:25:03 AM UTC 24 |
| Finished | Aug 27 04:30:18 AM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385711280 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.385711280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/147.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.762609351 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 128662560240 ps |
| CPU time | 437.03 seconds |
| Started | Aug 27 04:25:11 AM UTC 24 |
| Finished | Aug 27 04:32:33 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762609351 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.762609351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/148.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.1841781884 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 194776743979 ps |
| CPU time | 94.95 seconds |
| Started | Aug 27 04:25:17 AM UTC 24 |
| Finished | Aug 27 04:26:54 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841781884 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1841781884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/149.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.610280078 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 23756731682 ps |
| CPU time | 13.9 seconds |
| Started | Aug 27 03:49:56 AM UTC 24 |
| Finished | Aug 27 03:50:11 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610280078 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.610280078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.3332670105 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 120815691161 ps |
| CPU time | 197.05 seconds |
| Started | Aug 27 03:49:49 AM UTC 24 |
| Finished | Aug 27 03:53:09 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332670105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3332670105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/15.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.3982065027 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 39333620031 ps |
| CPU time | 218.15 seconds |
| Started | Aug 27 03:49:39 AM UTC 24 |
| Finished | Aug 27 03:53:20 AM UTC 24 |
| Peak memory | 199872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982065027 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3982065027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/15.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.1775295314 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 168028396571 ps |
| CPU time | 130.65 seconds |
| Started | Aug 27 03:50:11 AM UTC 24 |
| Finished | Aug 27 03:52:24 AM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775295314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1775295314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/15.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.2239990736 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 261129409235 ps |
| CPU time | 923.38 seconds |
| Started | Aug 27 03:50:22 AM UTC 24 |
| Finished | Aug 27 04:05:56 AM UTC 24 |
| Peak memory | 202424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239990736 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.2239990736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/15.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.2189211367 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 131129133285 ps |
| CPU time | 590.71 seconds |
| Started | Aug 27 04:25:38 AM UTC 24 |
| Finished | Aug 27 04:35:36 AM UTC 24 |
| Peak memory | 199904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189211367 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2189211367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/153.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.626286154 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 156804223799 ps |
| CPU time | 223.71 seconds |
| Started | Aug 27 04:25:44 AM UTC 24 |
| Finished | Aug 27 04:29:31 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626286154 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.626286154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/154.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.558758261 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 539942492200 ps |
| CPU time | 251.53 seconds |
| Started | Aug 27 04:26:08 AM UTC 24 |
| Finished | Aug 27 04:30:23 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558758261 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.558758261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/156.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.3589783777 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 20133321702 ps |
| CPU time | 69.88 seconds |
| Started | Aug 27 04:26:13 AM UTC 24 |
| Finished | Aug 27 04:27:25 AM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589783777 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3589783777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/157.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.3074475873 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 83987773805 ps |
| CPU time | 561.1 seconds |
| Started | Aug 27 04:26:37 AM UTC 24 |
| Finished | Aug 27 04:36:05 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074475873 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3074475873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/159.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.3453744147 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1124678045755 ps |
| CPU time | 1137.97 seconds |
| Started | Aug 27 03:50:40 AM UTC 24 |
| Finished | Aug 27 04:09:49 AM UTC 24 |
| Peak memory | 202328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453744147 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.3453744147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.1955834558 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 183229032359 ps |
| CPU time | 326.77 seconds |
| Started | Aug 27 03:50:31 AM UTC 24 |
| Finished | Aug 27 03:56:02 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955834558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1955834558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/16.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.1717493602 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 210511079 ps |
| CPU time | 1.02 seconds |
| Started | Aug 27 03:50:46 AM UTC 24 |
| Finished | Aug 27 03:50:48 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717493602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1717493602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/16.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.1881817033 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 3738830564485 ps |
| CPU time | 1629.82 seconds |
| Started | Aug 27 03:50:48 AM UTC 24 |
| Finished | Aug 27 04:18:15 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881817033 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.1881817033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/16.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.2481360420 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 63704804244 ps |
| CPU time | 125.44 seconds |
| Started | Aug 27 04:26:45 AM UTC 24 |
| Finished | Aug 27 04:28:53 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481360420 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2481360420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/160.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.2365661201 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 632319564053 ps |
| CPU time | 1150.34 seconds |
| Started | Aug 27 04:26:56 AM UTC 24 |
| Finished | Aug 27 04:46:19 AM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365661201 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2365661201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/164.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.211300602 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 184559791826 ps |
| CPU time | 502.81 seconds |
| Started | Aug 27 04:27:21 AM UTC 24 |
| Finished | Aug 27 04:35:50 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211300602 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.211300602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/166.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.3822336888 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 369299992948 ps |
| CPU time | 530.28 seconds |
| Started | Aug 27 04:27:24 AM UTC 24 |
| Finished | Aug 27 04:36:21 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822336888 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3822336888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/167.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.390501204 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 63958659439 ps |
| CPU time | 74.06 seconds |
| Started | Aug 27 04:27:26 AM UTC 24 |
| Finished | Aug 27 04:28:42 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390501204 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.390501204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/168.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.911925935 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 155249696855 ps |
| CPU time | 96.79 seconds |
| Started | Aug 27 03:50:58 AM UTC 24 |
| Finished | Aug 27 03:52:37 AM UTC 24 |
| Peak memory | 199584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911925935 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.911925935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.3304646543 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 532499511298 ps |
| CPU time | 272.27 seconds |
| Started | Aug 27 03:50:53 AM UTC 24 |
| Finished | Aug 27 03:55:29 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304646543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3304646543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/17.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.2622542947 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 107634514073 ps |
| CPU time | 298.25 seconds |
| Started | Aug 27 03:50:49 AM UTC 24 |
| Finished | Aug 27 03:55:51 AM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622542947 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2622542947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/17.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.962047618 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 112493376523 ps |
| CPU time | 159.67 seconds |
| Started | Aug 27 03:51:01 AM UTC 24 |
| Finished | Aug 27 03:53:43 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962047618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.962047618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/17.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all_with_rand_reset.3104127405 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 7861111390 ps |
| CPU time | 45.62 seconds |
| Started | Aug 27 03:51:04 AM UTC 24 |
| Finished | Aug 27 03:51:51 AM UTC 24 |
| Peak memory | 206044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3104127405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.rv_timer_stress_all_with_rand_reset.3104127405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/17.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.3179156138 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 558595331948 ps |
| CPU time | 1129.5 seconds |
| Started | Aug 27 04:28:05 AM UTC 24 |
| Finished | Aug 27 04:47:07 AM UTC 24 |
| Peak memory | 202440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179156138 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3179156138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/170.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.1711298831 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 96953435206 ps |
| CPU time | 399.18 seconds |
| Started | Aug 27 04:28:20 AM UTC 24 |
| Finished | Aug 27 04:35:04 AM UTC 24 |
| Peak memory | 199868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711298831 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1711298831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/171.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.576632661 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 311566758527 ps |
| CPU time | 1230.67 seconds |
| Started | Aug 27 04:28:30 AM UTC 24 |
| Finished | Aug 27 04:49:16 AM UTC 24 |
| Peak memory | 202412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576632661 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.576632661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/172.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.3981335590 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 403985685122 ps |
| CPU time | 292.56 seconds |
| Started | Aug 27 04:28:31 AM UTC 24 |
| Finished | Aug 27 04:33:28 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981335590 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3981335590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/173.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.4114670313 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 206844845619 ps |
| CPU time | 97.48 seconds |
| Started | Aug 27 04:28:43 AM UTC 24 |
| Finished | Aug 27 04:30:22 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114670313 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.4114670313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/175.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.560715359 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 15274447974 ps |
| CPU time | 32.04 seconds |
| Started | Aug 27 04:28:54 AM UTC 24 |
| Finished | Aug 27 04:29:27 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560715359 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.560715359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/176.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.3171582966 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 487574564028 ps |
| CPU time | 275.3 seconds |
| Started | Aug 27 04:29:00 AM UTC 24 |
| Finished | Aug 27 04:33:40 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171582966 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3171582966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/177.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.2810692826 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 75869222574 ps |
| CPU time | 133.08 seconds |
| Started | Aug 27 04:29:10 AM UTC 24 |
| Finished | Aug 27 04:31:26 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810692826 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2810692826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/178.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.4140115003 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 102237633098 ps |
| CPU time | 447.02 seconds |
| Started | Aug 27 04:29:17 AM UTC 24 |
| Finished | Aug 27 04:36:49 AM UTC 24 |
| Peak memory | 199284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140115003 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.4140115003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/179.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.739511648 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 531232226960 ps |
| CPU time | 296.02 seconds |
| Started | Aug 27 03:51:46 AM UTC 24 |
| Finished | Aug 27 03:56:46 AM UTC 24 |
| Peak memory | 199584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739511648 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.739511648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/18.rv_timer_disabled.2415714732 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 36073643409 ps |
| CPU time | 38.98 seconds |
| Started | Aug 27 03:51:43 AM UTC 24 |
| Finished | Aug 27 03:52:24 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415714732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2415714732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/18.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.3730421194 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 90395711225 ps |
| CPU time | 1571.68 seconds |
| Started | Aug 27 03:51:12 AM UTC 24 |
| Finished | Aug 27 04:17:42 AM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730421194 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3730421194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/18.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.3357149765 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 41784193306 ps |
| CPU time | 108.19 seconds |
| Started | Aug 27 03:51:49 AM UTC 24 |
| Finished | Aug 27 03:53:40 AM UTC 24 |
| Peak memory | 199816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357149765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3357149765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/18.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.553536835 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2077567714972 ps |
| CPU time | 1656.83 seconds |
| Started | Aug 27 03:51:52 AM UTC 24 |
| Finished | Aug 27 04:19:46 AM UTC 24 |
| Peak memory | 202444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553536835 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.553536835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/18.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.889096989 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 594885672285 ps |
| CPU time | 554.29 seconds |
| Started | Aug 27 04:29:17 AM UTC 24 |
| Finished | Aug 27 04:38:38 AM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889096989 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.889096989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/180.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.1381700583 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 588250150956 ps |
| CPU time | 2047.05 seconds |
| Started | Aug 27 04:29:28 AM UTC 24 |
| Finished | Aug 27 05:03:57 AM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381700583 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1381700583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/181.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.130919550 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 574511850653 ps |
| CPU time | 576.19 seconds |
| Started | Aug 27 04:29:33 AM UTC 24 |
| Finished | Aug 27 04:39:17 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130919550 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.130919550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/183.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.1802608283 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 91902503901 ps |
| CPU time | 106.77 seconds |
| Started | Aug 27 04:29:36 AM UTC 24 |
| Finished | Aug 27 04:31:26 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802608283 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1802608283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/184.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.1622295824 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 113415612863 ps |
| CPU time | 406.25 seconds |
| Started | Aug 27 04:29:59 AM UTC 24 |
| Finished | Aug 27 04:36:50 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622295824 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1622295824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/185.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.663259378 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 329739656574 ps |
| CPU time | 1214.18 seconds |
| Started | Aug 27 04:30:01 AM UTC 24 |
| Finished | Aug 27 04:50:28 AM UTC 24 |
| Peak memory | 202584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663259378 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.663259378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/186.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.1288681884 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 487622969741 ps |
| CPU time | 451.99 seconds |
| Started | Aug 27 04:30:14 AM UTC 24 |
| Finished | Aug 27 04:37:52 AM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288681884 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1288681884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/187.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.3110312089 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 116431130667 ps |
| CPU time | 466.71 seconds |
| Started | Aug 27 04:30:19 AM UTC 24 |
| Finished | Aug 27 04:38:12 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110312089 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3110312089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/188.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.1554055147 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 146984076988 ps |
| CPU time | 84.22 seconds |
| Started | Aug 27 04:30:23 AM UTC 24 |
| Finished | Aug 27 04:31:49 AM UTC 24 |
| Peak memory | 199700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554055147 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1554055147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/189.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.1009591350 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 127033398612 ps |
| CPU time | 84.94 seconds |
| Started | Aug 27 03:52:02 AM UTC 24 |
| Finished | Aug 27 03:53:29 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009591350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1009591350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/19.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.1813458347 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 323369071367 ps |
| CPU time | 1088.85 seconds |
| Started | Aug 27 03:51:57 AM UTC 24 |
| Finished | Aug 27 04:10:18 AM UTC 24 |
| Peak memory | 199816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813458347 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1813458347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/19.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.496725258 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 82317388621 ps |
| CPU time | 96.32 seconds |
| Started | Aug 27 03:52:03 AM UTC 24 |
| Finished | Aug 27 03:53:41 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496725258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.496725258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/19.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.692738359 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 4058441643952 ps |
| CPU time | 1271.68 seconds |
| Started | Aug 27 03:52:12 AM UTC 24 |
| Finished | Aug 27 04:13:38 AM UTC 24 |
| Peak memory | 202548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692738359 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.692738359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/19.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.2463210319 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 140370200190 ps |
| CPU time | 757.94 seconds |
| Started | Aug 27 04:30:25 AM UTC 24 |
| Finished | Aug 27 04:43:12 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463210319 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2463210319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/190.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.1209046236 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 196089230196 ps |
| CPU time | 969.26 seconds |
| Started | Aug 27 04:30:56 AM UTC 24 |
| Finished | Aug 27 04:47:16 AM UTC 24 |
| Peak memory | 202484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209046236 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1209046236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/192.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.360538052 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 39155450345 ps |
| CPU time | 71.52 seconds |
| Started | Aug 27 04:30:57 AM UTC 24 |
| Finished | Aug 27 04:32:11 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360538052 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.360538052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/193.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.3454742207 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 452780037579 ps |
| CPU time | 269.85 seconds |
| Started | Aug 27 04:31:17 AM UTC 24 |
| Finished | Aug 27 04:35:51 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454742207 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3454742207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/194.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.1045814449 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 276852360803 ps |
| CPU time | 1466.43 seconds |
| Started | Aug 27 04:31:26 AM UTC 24 |
| Finished | Aug 27 04:56:09 AM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045814449 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1045814449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/195.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.3836499037 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 362090785279 ps |
| CPU time | 378.74 seconds |
| Started | Aug 27 04:31:27 AM UTC 24 |
| Finished | Aug 27 04:37:51 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836499037 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3836499037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/196.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.651344024 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 4531271113 ps |
| CPU time | 74.63 seconds |
| Started | Aug 27 04:31:27 AM UTC 24 |
| Finished | Aug 27 04:32:44 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651344024 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.651344024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/197.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.365568288 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 678177779331 ps |
| CPU time | 864.23 seconds |
| Started | Aug 27 04:31:31 AM UTC 24 |
| Finished | Aug 27 04:46:06 AM UTC 24 |
| Peak memory | 199748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365568288 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.365568288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/198.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.679796303 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 1837413100603 ps |
| CPU time | 981.6 seconds |
| Started | Aug 27 03:46:02 AM UTC 24 |
| Finished | Aug 27 04:02:34 AM UTC 24 |
| Peak memory | 202424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679796303 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.679796303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.3775658502 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 425731691121 ps |
| CPU time | 153.47 seconds |
| Started | Aug 27 03:46:01 AM UTC 24 |
| Finished | Aug 27 03:48:37 AM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775658502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3775658502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.1293627701 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 401948124 ps |
| CPU time | 1.35 seconds |
| Started | Aug 27 03:46:09 AM UTC 24 |
| Finished | Aug 27 03:46:11 AM UTC 24 |
| Peak memory | 230928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293627701 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1293627701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.2601740549 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 291480555509 ps |
| CPU time | 510.85 seconds |
| Started | Aug 27 03:52:26 AM UTC 24 |
| Finished | Aug 27 04:01:02 AM UTC 24 |
| Peak memory | 199660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601740549 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.2601740549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.3675750918 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 276259307578 ps |
| CPU time | 138.13 seconds |
| Started | Aug 27 03:52:24 AM UTC 24 |
| Finished | Aug 27 03:54:45 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675750918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3675750918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/20.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.4200445991 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 68757681736 ps |
| CPU time | 156.44 seconds |
| Started | Aug 27 03:52:13 AM UTC 24 |
| Finished | Aug 27 03:54:52 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200445991 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.4200445991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/20.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.2298449502 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 101925266469 ps |
| CPU time | 475.28 seconds |
| Started | Aug 27 03:52:35 AM UTC 24 |
| Finished | Aug 27 04:00:36 AM UTC 24 |
| Peak memory | 199816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298449502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2298449502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/20.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.3321616732 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 128793668009 ps |
| CPU time | 369.53 seconds |
| Started | Aug 27 03:52:38 AM UTC 24 |
| Finished | Aug 27 03:58:52 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321616732 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.3321616732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/20.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.2121334984 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 25624499772 ps |
| CPU time | 21.18 seconds |
| Started | Aug 27 03:53:04 AM UTC 24 |
| Finished | Aug 27 03:53:27 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121334984 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.2121334984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.135602151 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 371706743242 ps |
| CPU time | 159.83 seconds |
| Started | Aug 27 03:52:53 AM UTC 24 |
| Finished | Aug 27 03:55:35 AM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135602151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.135602151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/21.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.7172835 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 40204181529 ps |
| CPU time | 81.6 seconds |
| Started | Aug 27 03:52:39 AM UTC 24 |
| Finished | Aug 27 03:54:02 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7172835 -assert nopostproc +UVM_TESTNAME=r v_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.7172835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/21.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.3435554600 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 68194175 ps |
| CPU time | 1.03 seconds |
| Started | Aug 27 03:53:09 AM UTC 24 |
| Finished | Aug 27 03:53:12 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435554600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3435554600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/21.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.517098549 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 429969637028 ps |
| CPU time | 782.05 seconds |
| Started | Aug 27 03:53:16 AM UTC 24 |
| Finished | Aug 27 04:06:26 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517098549 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.517098549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/21.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.695712512 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 79955240898 ps |
| CPU time | 130.61 seconds |
| Started | Aug 27 03:53:28 AM UTC 24 |
| Finished | Aug 27 03:55:41 AM UTC 24 |
| Peak memory | 199660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695712512 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.695712512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.2081688041 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 22791668975 ps |
| CPU time | 36.53 seconds |
| Started | Aug 27 03:53:27 AM UTC 24 |
| Finished | Aug 27 03:54:05 AM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081688041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2081688041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/22.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.4050916029 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 829420723568 ps |
| CPU time | 506.57 seconds |
| Started | Aug 27 03:53:21 AM UTC 24 |
| Finished | Aug 27 04:01:53 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050916029 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.4050916029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/22.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.1967288436 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 53475756199 ps |
| CPU time | 186.42 seconds |
| Started | Aug 27 03:53:30 AM UTC 24 |
| Finished | Aug 27 03:56:39 AM UTC 24 |
| Peak memory | 199880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967288436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1967288436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/22.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.2551998317 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 212357559460 ps |
| CPU time | 280.85 seconds |
| Started | Aug 27 03:53:41 AM UTC 24 |
| Finished | Aug 27 03:58:25 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551998317 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.2551998317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/22.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.2146741946 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 87754037617 ps |
| CPU time | 232.36 seconds |
| Started | Aug 27 03:53:44 AM UTC 24 |
| Finished | Aug 27 03:57:40 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146741946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2146741946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/23.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.4190275904 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 102995111 ps |
| CPU time | 0.79 seconds |
| Started | Aug 27 03:53:45 AM UTC 24 |
| Finished | Aug 27 03:53:47 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190275904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.4190275904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/23.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.4164174078 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 454600832268 ps |
| CPU time | 379.42 seconds |
| Started | Aug 27 03:53:48 AM UTC 24 |
| Finished | Aug 27 04:00:12 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164174078 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.4164174078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/23.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.3050615493 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2307705357780 ps |
| CPU time | 1261.27 seconds |
| Started | Aug 27 03:53:56 AM UTC 24 |
| Finished | Aug 27 04:15:10 AM UTC 24 |
| Peak memory | 202520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050615493 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.3050615493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.3123544579 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 84660627898 ps |
| CPU time | 47.03 seconds |
| Started | Aug 27 03:53:54 AM UTC 24 |
| Finished | Aug 27 03:54:42 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123544579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3123544579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/24.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.429812338 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 271899465741 ps |
| CPU time | 162.55 seconds |
| Started | Aug 27 03:53:52 AM UTC 24 |
| Finished | Aug 27 03:56:38 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429812338 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.429812338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/24.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.2585178287 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 44583437 ps |
| CPU time | 0.85 seconds |
| Started | Aug 27 03:54:01 AM UTC 24 |
| Finished | Aug 27 03:54:03 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585178287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2585178287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/24.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.2805964332 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 322344150161 ps |
| CPU time | 499.67 seconds |
| Started | Aug 27 03:54:25 AM UTC 24 |
| Finished | Aug 27 04:02:50 AM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805964332 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.2805964332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.533955402 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 356389603484 ps |
| CPU time | 186.04 seconds |
| Started | Aug 27 03:54:21 AM UTC 24 |
| Finished | Aug 27 03:57:30 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533955402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.533955402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/25.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.503898175 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 29512054462 ps |
| CPU time | 939.68 seconds |
| Started | Aug 27 03:54:05 AM UTC 24 |
| Finished | Aug 27 04:09:55 AM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503898175 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.503898175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/25.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.2234479869 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 229352324 ps |
| CPU time | 1.01 seconds |
| Started | Aug 27 03:54:43 AM UTC 24 |
| Finished | Aug 27 03:54:45 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234479869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2234479869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/25.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.2217823208 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 153896990235 ps |
| CPU time | 241.67 seconds |
| Started | Aug 27 03:54:46 AM UTC 24 |
| Finished | Aug 27 03:58:52 AM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217823208 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.2217823208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/25.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all_with_rand_reset.2541745446 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2300665756 ps |
| CPU time | 16.95 seconds |
| Started | Aug 27 03:54:44 AM UTC 24 |
| Finished | Aug 27 03:55:03 AM UTC 24 |
| Peak memory | 202012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2541745446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.rv_timer_stress_all_with_rand_reset.2541745446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/25.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.1263180816 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 124905692864 ps |
| CPU time | 314.92 seconds |
| Started | Aug 27 03:54:54 AM UTC 24 |
| Finished | Aug 27 04:00:13 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263180816 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.1263180816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.1309979366 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 69091547633 ps |
| CPU time | 148.5 seconds |
| Started | Aug 27 03:54:47 AM UTC 24 |
| Finished | Aug 27 03:57:19 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309979366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1309979366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/26.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.2334868048 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2064201638327 ps |
| CPU time | 1353.12 seconds |
| Started | Aug 27 03:54:46 AM UTC 24 |
| Finished | Aug 27 04:17:34 AM UTC 24 |
| Peak memory | 202548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334868048 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2334868048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/26.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.2968516127 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 92823602661 ps |
| CPU time | 72.02 seconds |
| Started | Aug 27 03:55:04 AM UTC 24 |
| Finished | Aug 27 03:56:18 AM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968516127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2968516127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/26.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.337632502 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 295709881282 ps |
| CPU time | 598.8 seconds |
| Started | Aug 27 03:55:30 AM UTC 24 |
| Finished | Aug 27 04:05:35 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337632502 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.337632502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/26.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all_with_rand_reset.2248691546 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4561753528 ps |
| CPU time | 42.88 seconds |
| Started | Aug 27 03:55:11 AM UTC 24 |
| Finished | Aug 27 03:55:55 AM UTC 24 |
| Peak memory | 204024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2248691546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.rv_timer_stress_all_with_rand_reset.2248691546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/26.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.4271785608 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 3809471786085 ps |
| CPU time | 1008.3 seconds |
| Started | Aug 27 03:55:45 AM UTC 24 |
| Finished | Aug 27 04:12:44 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271785608 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.4271785608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.4112831889 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 172448229103 ps |
| CPU time | 270.7 seconds |
| Started | Aug 27 03:55:41 AM UTC 24 |
| Finished | Aug 27 04:00:15 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112831889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.4112831889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/27.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.419078453 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 107127359083 ps |
| CPU time | 754.06 seconds |
| Started | Aug 27 03:55:52 AM UTC 24 |
| Finished | Aug 27 04:08:35 AM UTC 24 |
| Peak memory | 199748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419078453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.419078453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/27.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.2325152880 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 877678819515 ps |
| CPU time | 1377.19 seconds |
| Started | Aug 27 03:56:02 AM UTC 24 |
| Finished | Aug 27 04:19:14 AM UTC 24 |
| Peak memory | 202352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325152880 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.2325152880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/27.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all_with_rand_reset.4118742592 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2164998958 ps |
| CPU time | 34.96 seconds |
| Started | Aug 27 03:55:56 AM UTC 24 |
| Finished | Aug 27 03:56:32 AM UTC 24 |
| Peak memory | 203888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4118742592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.rv_timer_stress_all_with_rand_reset.4118742592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/27.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.175932324 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 125163317828 ps |
| CPU time | 163.34 seconds |
| Started | Aug 27 03:56:33 AM UTC 24 |
| Finished | Aug 27 03:59:19 AM UTC 24 |
| Peak memory | 199660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175932324 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.175932324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.205850558 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 154579063403 ps |
| CPU time | 312.79 seconds |
| Started | Aug 27 03:56:18 AM UTC 24 |
| Finished | Aug 27 04:01:35 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205850558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.205850558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/28.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.2532043053 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 205862080797 ps |
| CPU time | 2145.03 seconds |
| Started | Aug 27 03:56:39 AM UTC 24 |
| Finished | Aug 27 04:32:47 AM UTC 24 |
| Peak memory | 202424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532043053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2532043053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/28.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.227823601 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 1907515591625 ps |
| CPU time | 1857.64 seconds |
| Started | Aug 27 03:56:47 AM UTC 24 |
| Finished | Aug 27 04:28:04 AM UTC 24 |
| Peak memory | 202484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227823601 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.227823601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/28.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all_with_rand_reset.438363412 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1182023449 ps |
| CPU time | 15.37 seconds |
| Started | Aug 27 03:56:41 AM UTC 24 |
| Finished | Aug 27 03:56:57 AM UTC 24 |
| Peak memory | 201788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=438363412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.438363412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/28.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.771911408 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 343593048179 ps |
| CPU time | 231.99 seconds |
| Started | Aug 27 03:57:07 AM UTC 24 |
| Finished | Aug 27 04:01:03 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771911408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.771911408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/29.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.1033309306 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 156050594711 ps |
| CPU time | 501.16 seconds |
| Started | Aug 27 03:56:58 AM UTC 24 |
| Finished | Aug 27 04:05:25 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033309306 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1033309306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/29.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.2755975106 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 28090857065 ps |
| CPU time | 50.47 seconds |
| Started | Aug 27 03:57:19 AM UTC 24 |
| Finished | Aug 27 03:58:11 AM UTC 24 |
| Peak memory | 199816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755975106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2755975106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/29.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.3689766044 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 562451142871 ps |
| CPU time | 889.99 seconds |
| Started | Aug 27 03:46:13 AM UTC 24 |
| Finished | Aug 27 04:01:12 AM UTC 24 |
| Peak memory | 202400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689766044 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.3689766044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.939321545 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 472522793335 ps |
| CPU time | 141.99 seconds |
| Started | Aug 27 03:46:13 AM UTC 24 |
| Finished | Aug 27 03:48:37 AM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939321545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.939321545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.1920813975 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 44419264394 ps |
| CPU time | 137.22 seconds |
| Started | Aug 27 03:46:16 AM UTC 24 |
| Finished | Aug 27 03:48:36 AM UTC 24 |
| Peak memory | 199660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920813975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1920813975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.150747403 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 486309815 ps |
| CPU time | 1.46 seconds |
| Started | Aug 27 03:46:22 AM UTC 24 |
| Finished | Aug 27 03:46:25 AM UTC 24 |
| Peak memory | 230928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150747403 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.150747403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.3771697484 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 186485342049 ps |
| CPU time | 375 seconds |
| Started | Aug 27 03:58:19 AM UTC 24 |
| Finished | Aug 27 04:04:39 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771697484 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.3771697484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.191255368 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 191321052978 ps |
| CPU time | 247.58 seconds |
| Started | Aug 27 03:58:12 AM UTC 24 |
| Finished | Aug 27 04:02:23 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191255368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.191255368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/30.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.1018377567 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 201520065219 ps |
| CPU time | 136.02 seconds |
| Started | Aug 27 03:57:49 AM UTC 24 |
| Finished | Aug 27 04:00:07 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018377567 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1018377567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/30.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.1902016572 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 71413749171 ps |
| CPU time | 131.81 seconds |
| Started | Aug 27 03:58:26 AM UTC 24 |
| Finished | Aug 27 04:00:40 AM UTC 24 |
| Peak memory | 199852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902016572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1902016572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/30.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.3810137309 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 145016708446 ps |
| CPU time | 329.28 seconds |
| Started | Aug 27 03:59:05 AM UTC 24 |
| Finished | Aug 27 04:04:39 AM UTC 24 |
| Peak memory | 199660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810137309 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.3810137309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.225533480 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 29691669411 ps |
| CPU time | 38.68 seconds |
| Started | Aug 27 03:59:04 AM UTC 24 |
| Finished | Aug 27 03:59:44 AM UTC 24 |
| Peak memory | 199748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225533480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.225533480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/31.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.2757171983 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 403049110467 ps |
| CPU time | 646.8 seconds |
| Started | Aug 27 03:59:01 AM UTC 24 |
| Finished | Aug 27 04:09:56 AM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757171983 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2757171983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/31.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.1689473661 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 20004962639 ps |
| CPU time | 22.89 seconds |
| Started | Aug 27 03:59:20 AM UTC 24 |
| Finished | Aug 27 03:59:45 AM UTC 24 |
| Peak memory | 199880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689473661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1689473661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/31.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.699898497 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 2398820155074 ps |
| CPU time | 1268.12 seconds |
| Started | Aug 27 03:59:36 AM UTC 24 |
| Finished | Aug 27 04:20:57 AM UTC 24 |
| Peak memory | 202444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699898497 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.699898497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/31.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.1695308265 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 103950896157 ps |
| CPU time | 70.55 seconds |
| Started | Aug 27 03:59:46 AM UTC 24 |
| Finished | Aug 27 04:00:58 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695308265 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.1695308265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.3052325827 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 195214288725 ps |
| CPU time | 102.16 seconds |
| Started | Aug 27 03:59:45 AM UTC 24 |
| Finished | Aug 27 04:01:29 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052325827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3052325827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/32.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.2991664049 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 3754711961 ps |
| CPU time | 4.57 seconds |
| Started | Aug 27 03:59:47 AM UTC 24 |
| Finished | Aug 27 03:59:52 AM UTC 24 |
| Peak memory | 199604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991664049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2991664049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/32.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.781319960 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 42063173534 ps |
| CPU time | 120.3 seconds |
| Started | Aug 27 03:59:53 AM UTC 24 |
| Finished | Aug 27 04:01:56 AM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781319960 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.781319960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/32.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.4148005922 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 7942142335 ps |
| CPU time | 8.89 seconds |
| Started | Aug 27 04:00:13 AM UTC 24 |
| Finished | Aug 27 04:00:23 AM UTC 24 |
| Peak memory | 199660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148005922 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.4148005922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.1765860194 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 41540448746 ps |
| CPU time | 78.35 seconds |
| Started | Aug 27 04:00:08 AM UTC 24 |
| Finished | Aug 27 04:01:28 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765860194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1765860194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/33.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.674342344 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 89613764297 ps |
| CPU time | 563.65 seconds |
| Started | Aug 27 03:59:59 AM UTC 24 |
| Finished | Aug 27 04:09:30 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674342344 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.674342344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/33.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.1814436597 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 690315306726 ps |
| CPU time | 291.91 seconds |
| Started | Aug 27 04:00:13 AM UTC 24 |
| Finished | Aug 27 04:05:10 AM UTC 24 |
| Peak memory | 199816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814436597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1814436597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/33.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.3950446088 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 1382451430268 ps |
| CPU time | 1170.2 seconds |
| Started | Aug 27 04:00:41 AM UTC 24 |
| Finished | Aug 27 04:20:23 AM UTC 24 |
| Peak memory | 202464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950446088 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.3950446088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.2376146178 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 937074073337 ps |
| CPU time | 166.67 seconds |
| Started | Aug 27 04:00:37 AM UTC 24 |
| Finished | Aug 27 04:03:26 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376146178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2376146178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/34.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.1294000267 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 284242285647 ps |
| CPU time | 550.88 seconds |
| Started | Aug 27 04:00:50 AM UTC 24 |
| Finished | Aug 27 04:10:08 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294000267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1294000267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/34.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.2542688546 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 571624439599 ps |
| CPU time | 308.66 seconds |
| Started | Aug 27 04:01:06 AM UTC 24 |
| Finished | Aug 27 04:06:19 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542688546 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.2542688546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.1994461339 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 264375229589 ps |
| CPU time | 98.72 seconds |
| Started | Aug 27 04:01:05 AM UTC 24 |
| Finished | Aug 27 04:02:46 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994461339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1994461339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/35.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.1344749546 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 8350098141 ps |
| CPU time | 167.62 seconds |
| Started | Aug 27 04:01:04 AM UTC 24 |
| Finished | Aug 27 04:03:54 AM UTC 24 |
| Peak memory | 199872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344749546 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1344749546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/35.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.2719724209 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 330184875246 ps |
| CPU time | 45.44 seconds |
| Started | Aug 27 04:01:12 AM UTC 24 |
| Finished | Aug 27 04:01:59 AM UTC 24 |
| Peak memory | 199816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719724209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2719724209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/35.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.3691336456 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 208416277487 ps |
| CPU time | 326.52 seconds |
| Started | Aug 27 04:01:29 AM UTC 24 |
| Finished | Aug 27 04:07:00 AM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691336456 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.3691336456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/35.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.119049763 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 313620878605 ps |
| CPU time | 163.4 seconds |
| Started | Aug 27 04:01:37 AM UTC 24 |
| Finished | Aug 27 04:04:22 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119049763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.119049763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/36.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.4183462244 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 38509096403 ps |
| CPU time | 313.42 seconds |
| Started | Aug 27 04:01:49 AM UTC 24 |
| Finished | Aug 27 04:07:07 AM UTC 24 |
| Peak memory | 199816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183462244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.4183462244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/36.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.3829866150 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 1191049431854 ps |
| CPU time | 1568.46 seconds |
| Started | Aug 27 04:01:54 AM UTC 24 |
| Finished | Aug 27 04:28:19 AM UTC 24 |
| Peak memory | 202584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829866150 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.3829866150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/36.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.1446714959 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 5683552283 ps |
| CPU time | 16.01 seconds |
| Started | Aug 27 04:02:00 AM UTC 24 |
| Finished | Aug 27 04:02:17 AM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446714959 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.1446714959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.654672145 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 156763372983 ps |
| CPU time | 290.65 seconds |
| Started | Aug 27 04:02:00 AM UTC 24 |
| Finished | Aug 27 04:06:54 AM UTC 24 |
| Peak memory | 199852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654672145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.654672145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/37.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.974700586 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 990896072413 ps |
| CPU time | 516.74 seconds |
| Started | Aug 27 04:01:56 AM UTC 24 |
| Finished | Aug 27 04:10:39 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974700586 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.974700586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/37.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.258633806 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 66111348102 ps |
| CPU time | 157.66 seconds |
| Started | Aug 27 04:02:13 AM UTC 24 |
| Finished | Aug 27 04:04:53 AM UTC 24 |
| Peak memory | 199812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258633806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.258633806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/37.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all_with_rand_reset.2594823558 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4571210903 ps |
| CPU time | 18.39 seconds |
| Started | Aug 27 04:02:18 AM UTC 24 |
| Finished | Aug 27 04:02:38 AM UTC 24 |
| Peak memory | 202012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2594823558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.rv_timer_stress_all_with_rand_reset.2594823558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/37.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.3156036122 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 13148900358 ps |
| CPU time | 44.5 seconds |
| Started | Aug 27 04:02:46 AM UTC 24 |
| Finished | Aug 27 04:03:33 AM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156036122 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.3156036122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.4016983269 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 87801084519 ps |
| CPU time | 185.3 seconds |
| Started | Aug 27 04:02:38 AM UTC 24 |
| Finished | Aug 27 04:05:46 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016983269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.4016983269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/38.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.2195445607 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 32551263345 ps |
| CPU time | 79.98 seconds |
| Started | Aug 27 04:02:51 AM UTC 24 |
| Finished | Aug 27 04:04:12 AM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195445607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2195445607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/38.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.125821391 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 1003058372542 ps |
| CPU time | 769.62 seconds |
| Started | Aug 27 04:03:27 AM UTC 24 |
| Finished | Aug 27 04:16:25 AM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125821391 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.125821391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/38.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.784478049 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1194037993434 ps |
| CPU time | 1122.74 seconds |
| Started | Aug 27 04:03:57 AM UTC 24 |
| Finished | Aug 27 04:22:52 AM UTC 24 |
| Peak memory | 202424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784478049 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.784478049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.3108419759 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 452240613430 ps |
| CPU time | 357.1 seconds |
| Started | Aug 27 04:03:35 AM UTC 24 |
| Finished | Aug 27 04:09:37 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108419759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3108419759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/39.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.2356168187 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 95540065765 ps |
| CPU time | 580.3 seconds |
| Started | Aug 27 04:03:31 AM UTC 24 |
| Finished | Aug 27 04:13:18 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356168187 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2356168187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/39.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.2594447845 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 94988888133 ps |
| CPU time | 36.28 seconds |
| Started | Aug 27 04:03:57 AM UTC 24 |
| Finished | Aug 27 04:04:34 AM UTC 24 |
| Peak memory | 199604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594447845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2594447845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/39.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.3552946161 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 491634823433 ps |
| CPU time | 922.25 seconds |
| Started | Aug 27 03:46:26 AM UTC 24 |
| Finished | Aug 27 04:01:59 AM UTC 24 |
| Peak memory | 202648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552946161 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.3552946161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.1265801058 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 355719398975 ps |
| CPU time | 170.79 seconds |
| Started | Aug 27 03:46:26 AM UTC 24 |
| Finished | Aug 27 03:49:20 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265801058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1265801058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.1443240102 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 44742505922 ps |
| CPU time | 311.58 seconds |
| Started | Aug 27 03:46:26 AM UTC 24 |
| Finished | Aug 27 03:51:42 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443240102 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1443240102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.2831061964 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 21366288563 ps |
| CPU time | 20.37 seconds |
| Started | Aug 27 03:46:29 AM UTC 24 |
| Finished | Aug 27 03:46:51 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831061964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2831061964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.693595768 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 72736048 ps |
| CPU time | 1.22 seconds |
| Started | Aug 27 03:46:39 AM UTC 24 |
| Finished | Aug 27 03:46:42 AM UTC 24 |
| Peak memory | 228940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693595768 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.693595768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.3710019020 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 233656516468 ps |
| CPU time | 110.33 seconds |
| Started | Aug 27 03:46:37 AM UTC 24 |
| Finished | Aug 27 03:48:29 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710019020 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.3710019020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all_with_rand_reset.2823566855 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 4946268043 ps |
| CPU time | 23.29 seconds |
| Started | Aug 27 03:46:37 AM UTC 24 |
| Finished | Aug 27 03:47:02 AM UTC 24 |
| Peak memory | 201844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2823566855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.rv_timer_stress_all_with_rand_reset.2823566855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.4249880540 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 22816313670 ps |
| CPU time | 76.21 seconds |
| Started | Aug 27 04:04:23 AM UTC 24 |
| Finished | Aug 27 04:05:41 AM UTC 24 |
| Peak memory | 199748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249880540 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.4249880540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.1276852863 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 70292681 ps |
| CPU time | 0.73 seconds |
| Started | Aug 27 04:04:35 AM UTC 24 |
| Finished | Aug 27 04:04:37 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276852863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1276852863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/40.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all_with_rand_reset.2865840350 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 3270711614 ps |
| CPU time | 41.86 seconds |
| Started | Aug 27 04:04:37 AM UTC 24 |
| Finished | Aug 27 04:05:20 AM UTC 24 |
| Peak memory | 204060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2865840350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.rv_timer_stress_all_with_rand_reset.2865840350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/40.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.1844884087 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 81889471465 ps |
| CPU time | 235.82 seconds |
| Started | Aug 27 04:04:54 AM UTC 24 |
| Finished | Aug 27 04:08:54 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844884087 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.1844884087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.1513294428 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 122558211203 ps |
| CPU time | 201.41 seconds |
| Started | Aug 27 04:04:52 AM UTC 24 |
| Finished | Aug 27 04:08:16 AM UTC 24 |
| Peak memory | 199872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513294428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1513294428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/41.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.4242361191 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 195211812229 ps |
| CPU time | 1557.39 seconds |
| Started | Aug 27 04:04:41 AM UTC 24 |
| Finished | Aug 27 04:30:55 AM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242361191 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4242361191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/41.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.3326375582 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 23381467992 ps |
| CPU time | 55.07 seconds |
| Started | Aug 27 04:04:57 AM UTC 24 |
| Finished | Aug 27 04:05:53 AM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326375582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3326375582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/41.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.48829084 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 482491210818 ps |
| CPU time | 643.34 seconds |
| Started | Aug 27 04:05:14 AM UTC 24 |
| Finished | Aug 27 04:16:04 AM UTC 24 |
| Peak memory | 199628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48829084 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.48829084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/41.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all_with_rand_reset.2664089287 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 7586559825 ps |
| CPU time | 48.56 seconds |
| Started | Aug 27 04:05:11 AM UTC 24 |
| Finished | Aug 27 04:06:01 AM UTC 24 |
| Peak memory | 203960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2664089287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.rv_timer_stress_all_with_rand_reset.2664089287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/41.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.1618016066 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 17240345714 ps |
| CPU time | 35.7 seconds |
| Started | Aug 27 04:05:27 AM UTC 24 |
| Finished | Aug 27 04:06:04 AM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618016066 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.1618016066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.3369996941 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 100068703243 ps |
| CPU time | 122.14 seconds |
| Started | Aug 27 04:05:21 AM UTC 24 |
| Finished | Aug 27 04:07:25 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369996941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3369996941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/42.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.2185346241 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 84440938861 ps |
| CPU time | 133.73 seconds |
| Started | Aug 27 04:05:21 AM UTC 24 |
| Finished | Aug 27 04:07:37 AM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185346241 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2185346241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/42.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.1827398156 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 265182151858 ps |
| CPU time | 295.35 seconds |
| Started | Aug 27 04:05:36 AM UTC 24 |
| Finished | Aug 27 04:10:36 AM UTC 24 |
| Peak memory | 199852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827398156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1827398156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/42.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.56810958 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 282419653628 ps |
| CPU time | 394.25 seconds |
| Started | Aug 27 04:05:47 AM UTC 24 |
| Finished | Aug 27 04:12:26 AM UTC 24 |
| Peak memory | 199760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56810958 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.56810958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/42.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.1388736826 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 222930529833 ps |
| CPU time | 510.58 seconds |
| Started | Aug 27 04:05:57 AM UTC 24 |
| Finished | Aug 27 04:14:34 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388736826 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.1388736826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.261300034 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 568709088005 ps |
| CPU time | 192.16 seconds |
| Started | Aug 27 04:05:54 AM UTC 24 |
| Finished | Aug 27 04:09:09 AM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261300034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.261300034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/43.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.638280824 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 73528283743 ps |
| CPU time | 1513.59 seconds |
| Started | Aug 27 04:05:47 AM UTC 24 |
| Finished | Aug 27 04:31:17 AM UTC 24 |
| Peak memory | 202612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638280824 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.638280824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/43.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.3025095692 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 433985714 ps |
| CPU time | 1.13 seconds |
| Started | Aug 27 04:05:58 AM UTC 24 |
| Finished | Aug 27 04:06:01 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025095692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3025095692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/43.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.2884621780 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 456004150765 ps |
| CPU time | 503.81 seconds |
| Started | Aug 27 04:06:23 AM UTC 24 |
| Finished | Aug 27 04:14:53 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884621780 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.2884621780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.2176374005 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 196632163417 ps |
| CPU time | 63.35 seconds |
| Started | Aug 27 04:06:20 AM UTC 24 |
| Finished | Aug 27 04:07:25 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176374005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2176374005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/44.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.1483570240 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 193732789302 ps |
| CPU time | 177.37 seconds |
| Started | Aug 27 04:06:05 AM UTC 24 |
| Finished | Aug 27 04:09:05 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483570240 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1483570240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/44.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.3935568407 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 79936942385 ps |
| CPU time | 152.89 seconds |
| Started | Aug 27 04:06:27 AM UTC 24 |
| Finished | Aug 27 04:09:02 AM UTC 24 |
| Peak memory | 199852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935568407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3935568407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/44.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.3778725267 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1308841747339 ps |
| CPU time | 2304.42 seconds |
| Started | Aug 27 04:06:34 AM UTC 24 |
| Finished | Aug 27 04:45:23 AM UTC 24 |
| Peak memory | 202484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778725267 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.3778725267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/44.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.3098539395 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1529607294026 ps |
| CPU time | 608.67 seconds |
| Started | Aug 27 04:07:01 AM UTC 24 |
| Finished | Aug 27 04:17:17 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098539395 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.3098539395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.2300303787 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 175315455879 ps |
| CPU time | 76.58 seconds |
| Started | Aug 27 04:06:49 AM UTC 24 |
| Finished | Aug 27 04:08:07 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300303787 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2300303787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/45.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.1758409324 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 87960158171 ps |
| CPU time | 536.08 seconds |
| Started | Aug 27 04:07:07 AM UTC 24 |
| Finished | Aug 27 04:16:11 AM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758409324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1758409324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/45.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.674689930 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 593720490783 ps |
| CPU time | 1058.08 seconds |
| Started | Aug 27 04:07:27 AM UTC 24 |
| Finished | Aug 27 04:25:16 AM UTC 24 |
| Peak memory | 199608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674689930 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.674689930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/45.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all_with_rand_reset.2628719422 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 5544585521 ps |
| CPU time | 87.18 seconds |
| Started | Aug 27 04:07:25 AM UTC 24 |
| Finished | Aug 27 04:08:55 AM UTC 24 |
| Peak memory | 203960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2628719422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 45.rv_timer_stress_all_with_rand_reset.2628719422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/45.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.1429628487 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 514115905595 ps |
| CPU time | 315.94 seconds |
| Started | Aug 27 04:08:08 AM UTC 24 |
| Finished | Aug 27 04:13:28 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429628487 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.1429628487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.4094792595 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 16141520021 ps |
| CPU time | 25.47 seconds |
| Started | Aug 27 04:08:07 AM UTC 24 |
| Finished | Aug 27 04:08:33 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094792595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.4094792595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/46.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.2920689082 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 289318922107 ps |
| CPU time | 351.84 seconds |
| Started | Aug 27 04:07:38 AM UTC 24 |
| Finished | Aug 27 04:13:34 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920689082 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2920689082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/46.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.2219974708 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 91481208 ps |
| CPU time | 1.07 seconds |
| Started | Aug 27 04:08:17 AM UTC 24 |
| Finished | Aug 27 04:08:19 AM UTC 24 |
| Peak memory | 198936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219974708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2219974708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/46.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.1594435348 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 409494400305 ps |
| CPU time | 223.75 seconds |
| Started | Aug 27 04:08:42 AM UTC 24 |
| Finished | Aug 27 04:12:29 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594435348 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.1594435348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.3466389150 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 415126834791 ps |
| CPU time | 163.54 seconds |
| Started | Aug 27 04:08:40 AM UTC 24 |
| Finished | Aug 27 04:11:26 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466389150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3466389150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/47.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.2720587087 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 241162794595 ps |
| CPU time | 180.06 seconds |
| Started | Aug 27 04:08:36 AM UTC 24 |
| Finished | Aug 27 04:11:39 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720587087 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2720587087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/47.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.3192609917 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 66377858615 ps |
| CPU time | 47.15 seconds |
| Started | Aug 27 04:08:54 AM UTC 24 |
| Finished | Aug 27 04:09:43 AM UTC 24 |
| Peak memory | 199468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192609917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3192609917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/47.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.992559912 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 3177525748826 ps |
| CPU time | 1158.58 seconds |
| Started | Aug 27 04:09:03 AM UTC 24 |
| Finished | Aug 27 04:28:33 AM UTC 24 |
| Peak memory | 202580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992559912 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.992559912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/47.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.3325207166 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 7838983255580 ps |
| CPU time | 2279.03 seconds |
| Started | Aug 27 04:09:10 AM UTC 24 |
| Finished | Aug 27 04:47:33 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325207166 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.3325207166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.3743174481 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 53731047979 ps |
| CPU time | 123.88 seconds |
| Started | Aug 27 04:09:08 AM UTC 24 |
| Finished | Aug 27 04:11:14 AM UTC 24 |
| Peak memory | 199872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3743174481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3743174481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/48.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.1442942386 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 21149513955 ps |
| CPU time | 67.1 seconds |
| Started | Aug 27 04:09:31 AM UTC 24 |
| Finished | Aug 27 04:10:40 AM UTC 24 |
| Peak memory | 199852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442942386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1442942386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/48.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.115936163 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 2858842668 ps |
| CPU time | 2.09 seconds |
| Started | Aug 27 04:09:56 AM UTC 24 |
| Finished | Aug 27 04:09:59 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115936163 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.115936163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.3726066162 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 438609226427 ps |
| CPU time | 282.84 seconds |
| Started | Aug 27 04:09:49 AM UTC 24 |
| Finished | Aug 27 04:14:36 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726066162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3726066162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/49.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.25947200 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 391530502186 ps |
| CPU time | 338.3 seconds |
| Started | Aug 27 04:09:44 AM UTC 24 |
| Finished | Aug 27 04:15:27 AM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25947200 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.25947200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/49.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.997153405 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 304947573344 ps |
| CPU time | 212.51 seconds |
| Started | Aug 27 04:09:56 AM UTC 24 |
| Finished | Aug 27 04:13:32 AM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997153405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.997153405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/49.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.366931274 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 42679726288 ps |
| CPU time | 76.06 seconds |
| Started | Aug 27 03:46:55 AM UTC 24 |
| Finished | Aug 27 03:48:13 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366931274 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.366931274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.3331533637 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 419901092934 ps |
| CPU time | 425.58 seconds |
| Started | Aug 27 03:46:42 AM UTC 24 |
| Finished | Aug 27 03:53:53 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331533637 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3331533637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/5.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.382432087 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 207832907984 ps |
| CPU time | 878.21 seconds |
| Started | Aug 27 03:46:59 AM UTC 24 |
| Finished | Aug 27 04:01:48 AM UTC 24 |
| Peak memory | 202452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382432087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.382432087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/5.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.626018005 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 224662025282 ps |
| CPU time | 1061.15 seconds |
| Started | Aug 27 03:47:02 AM UTC 24 |
| Finished | Aug 27 04:04:56 AM UTC 24 |
| Peak memory | 202340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626018005 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.626018005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/5.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.755124527 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 62400678739 ps |
| CPU time | 148.54 seconds |
| Started | Aug 27 04:10:19 AM UTC 24 |
| Finished | Aug 27 04:12:50 AM UTC 24 |
| Peak memory | 199872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755124527 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.755124527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/51.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.1146823674 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 437626408788 ps |
| CPU time | 242.88 seconds |
| Started | Aug 27 04:10:30 AM UTC 24 |
| Finished | Aug 27 04:14:36 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146823674 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1146823674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/52.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.3330752031 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 573650697440 ps |
| CPU time | 124.93 seconds |
| Started | Aug 27 04:10:41 AM UTC 24 |
| Finished | Aug 27 04:12:48 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330752031 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3330752031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/55.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.2861037054 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 323998384515 ps |
| CPU time | 183.77 seconds |
| Started | Aug 27 04:11:27 AM UTC 24 |
| Finished | Aug 27 04:14:34 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861037054 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2861037054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/57.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.678030507 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 120170084141 ps |
| CPU time | 204.34 seconds |
| Started | Aug 27 04:11:40 AM UTC 24 |
| Finished | Aug 27 04:15:08 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678030507 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.678030507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/58.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.4244320434 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 692995438391 ps |
| CPU time | 607.29 seconds |
| Started | Aug 27 04:12:04 AM UTC 24 |
| Finished | Aug 27 04:22:18 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244320434 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.4244320434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/59.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.810424697 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 30289224764 ps |
| CPU time | 70.62 seconds |
| Started | Aug 27 03:47:12 AM UTC 24 |
| Finished | Aug 27 03:48:24 AM UTC 24 |
| Peak memory | 199500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810424697 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.810424697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.2172277065 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 582265657458 ps |
| CPU time | 102.46 seconds |
| Started | Aug 27 03:47:12 AM UTC 24 |
| Finished | Aug 27 03:48:56 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172277065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2172277065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/6.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.731659810 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 144746174815 ps |
| CPU time | 370.08 seconds |
| Started | Aug 27 03:47:12 AM UTC 24 |
| Finished | Aug 27 03:53:26 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731659810 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.731659810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/6.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.2144806729 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 97498725101 ps |
| CPU time | 1531.71 seconds |
| Started | Aug 27 03:47:12 AM UTC 24 |
| Finished | Aug 27 04:12:59 AM UTC 24 |
| Peak memory | 202412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144806729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2144806729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/6.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.3833978125 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 767776038581 ps |
| CPU time | 817.86 seconds |
| Started | Aug 27 03:47:16 AM UTC 24 |
| Finished | Aug 27 04:01:04 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833978125 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.3833978125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/6.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.2800177803 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 192878325075 ps |
| CPU time | 1039.56 seconds |
| Started | Aug 27 04:12:27 AM UTC 24 |
| Finished | Aug 27 04:29:58 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800177803 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2800177803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/60.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.4014501327 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 161284406698 ps |
| CPU time | 838.85 seconds |
| Started | Aug 27 04:12:28 AM UTC 24 |
| Finished | Aug 27 04:26:36 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014501327 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.4014501327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/61.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.1048673888 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 249304700776 ps |
| CPU time | 572.32 seconds |
| Started | Aug 27 04:12:30 AM UTC 24 |
| Finished | Aug 27 04:22:09 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048673888 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1048673888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/62.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.3777292099 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 168448155134 ps |
| CPU time | 629.52 seconds |
| Started | Aug 27 04:12:50 AM UTC 24 |
| Finished | Aug 27 04:23:26 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777292099 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3777292099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/65.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.1865681132 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 53426860371 ps |
| CPU time | 70.27 seconds |
| Started | Aug 27 04:13:00 AM UTC 24 |
| Finished | Aug 27 04:14:12 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865681132 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1865681132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/66.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.1920494463 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 117354043702 ps |
| CPU time | 123.16 seconds |
| Started | Aug 27 04:13:13 AM UTC 24 |
| Finished | Aug 27 04:15:19 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920494463 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1920494463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/67.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.348215939 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 531772114904 ps |
| CPU time | 422.54 seconds |
| Started | Aug 27 03:47:16 AM UTC 24 |
| Finished | Aug 27 03:54:24 AM UTC 24 |
| Peak memory | 199584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348215939 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.348215939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.527847638 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 207395584527 ps |
| CPU time | 223.48 seconds |
| Started | Aug 27 03:47:16 AM UTC 24 |
| Finished | Aug 27 03:51:03 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527847638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.527847638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/7.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.1007637143 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 257517546628 ps |
| CPU time | 48.51 seconds |
| Started | Aug 27 03:47:16 AM UTC 24 |
| Finished | Aug 27 03:48:06 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007637143 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1007637143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/7.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.3041864395 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 970544654 ps |
| CPU time | 2.24 seconds |
| Started | Aug 27 03:47:19 AM UTC 24 |
| Finished | Aug 27 03:47:22 AM UTC 24 |
| Peak memory | 199608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041864395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3041864395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/7.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.3177051619 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 94767260858 ps |
| CPU time | 164.2 seconds |
| Started | Aug 27 04:13:33 AM UTC 24 |
| Finished | Aug 27 04:16:20 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177051619 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3177051619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/70.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.2157417155 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 4839716613 ps |
| CPU time | 7.9 seconds |
| Started | Aug 27 04:13:35 AM UTC 24 |
| Finished | Aug 27 04:13:44 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157417155 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2157417155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/71.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.1166195487 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 134122894430 ps |
| CPU time | 576.98 seconds |
| Started | Aug 27 04:13:39 AM UTC 24 |
| Finished | Aug 27 04:23:22 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166195487 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1166195487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/72.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.1792020007 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 114426044055 ps |
| CPU time | 128.99 seconds |
| Started | Aug 27 04:13:45 AM UTC 24 |
| Finished | Aug 27 04:15:56 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792020007 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1792020007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/73.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.790405465 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 65132813688 ps |
| CPU time | 322.93 seconds |
| Started | Aug 27 04:14:35 AM UTC 24 |
| Finished | Aug 27 04:20:02 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=790405465 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.790405465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/75.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.1888091332 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 283489917670 ps |
| CPU time | 653.9 seconds |
| Started | Aug 27 04:14:35 AM UTC 24 |
| Finished | Aug 27 04:25:37 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888091332 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1888091332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/76.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.3884133665 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 347756100184 ps |
| CPU time | 212.95 seconds |
| Started | Aug 27 04:14:37 AM UTC 24 |
| Finished | Aug 27 04:18:13 AM UTC 24 |
| Peak memory | 199580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884133665 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3884133665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/77.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.4236193223 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 82481432009 ps |
| CPU time | 100.05 seconds |
| Started | Aug 27 04:14:37 AM UTC 24 |
| Finished | Aug 27 04:16:19 AM UTC 24 |
| Peak memory | 199584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236193223 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.4236193223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/78.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.565296631 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 156819222183 ps |
| CPU time | 78.66 seconds |
| Started | Aug 27 03:47:23 AM UTC 24 |
| Finished | Aug 27 03:48:44 AM UTC 24 |
| Peak memory | 199752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565296631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.565296631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/8.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.2337944833 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 46406299972 ps |
| CPU time | 377.71 seconds |
| Started | Aug 27 03:47:22 AM UTC 24 |
| Finished | Aug 27 03:53:45 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337944833 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2337944833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/8.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.3374955904 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 30563533757 ps |
| CPU time | 50.85 seconds |
| Started | Aug 27 03:47:28 AM UTC 24 |
| Finished | Aug 27 03:48:20 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374955904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3374955904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/8.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.1369031290 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 62087627 ps |
| CPU time | 0.79 seconds |
| Started | Aug 27 03:47:38 AM UTC 24 |
| Finished | Aug 27 03:47:40 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369031290 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.1369031290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/8.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.1072877338 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 39786442290 ps |
| CPU time | 275.17 seconds |
| Started | Aug 27 04:14:53 AM UTC 24 |
| Finished | Aug 27 04:19:32 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072877338 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1072877338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/80.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.271950977 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 378884277077 ps |
| CPU time | 222.97 seconds |
| Started | Aug 27 04:15:08 AM UTC 24 |
| Finished | Aug 27 04:18:54 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271950977 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.271950977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/81.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.1130291322 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 829956220957 ps |
| CPU time | 225.27 seconds |
| Started | Aug 27 04:15:11 AM UTC 24 |
| Finished | Aug 27 04:18:59 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130291322 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1130291322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/82.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.2921483970 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 804504770405 ps |
| CPU time | 1197.18 seconds |
| Started | Aug 27 04:15:20 AM UTC 24 |
| Finished | Aug 27 04:35:30 AM UTC 24 |
| Peak memory | 202648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921483970 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2921483970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/83.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.75414199 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 154484706897 ps |
| CPU time | 607.75 seconds |
| Started | Aug 27 04:15:28 AM UTC 24 |
| Finished | Aug 27 04:25:43 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75414199 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.75414199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/84.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.1318064799 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 84486488290 ps |
| CPU time | 418.9 seconds |
| Started | Aug 27 04:15:28 AM UTC 24 |
| Finished | Aug 27 04:22:32 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318064799 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1318064799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/85.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.2183809225 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 205196881199 ps |
| CPU time | 556.49 seconds |
| Started | Aug 27 04:15:57 AM UTC 24 |
| Finished | Aug 27 04:25:20 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183809225 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2183809225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/86.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.2157983572 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 39096485924 ps |
| CPU time | 84.62 seconds |
| Started | Aug 27 04:16:05 AM UTC 24 |
| Finished | Aug 27 04:17:32 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157983572 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2157983572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/87.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.2633044238 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 32626489896 ps |
| CPU time | 110.25 seconds |
| Started | Aug 27 04:16:11 AM UTC 24 |
| Finished | Aug 27 04:18:04 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633044238 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2633044238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/88.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.1160265213 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 342210038125 ps |
| CPU time | 631.58 seconds |
| Started | Aug 27 04:16:16 AM UTC 24 |
| Finished | Aug 27 04:26:55 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160265213 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1160265213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/89.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.2821119235 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 191922356571 ps |
| CPU time | 464.08 seconds |
| Started | Aug 27 03:47:55 AM UTC 24 |
| Finished | Aug 27 03:55:44 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821119235 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.2821119235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.498741506 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 131707491101 ps |
| CPU time | 232.84 seconds |
| Started | Aug 27 03:47:53 AM UTC 24 |
| Finished | Aug 27 03:51:49 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498741506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.498741506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/9.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.2920404606 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 705696003 ps |
| CPU time | 2.26 seconds |
| Started | Aug 27 03:48:05 AM UTC 24 |
| Finished | Aug 27 03:48:09 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920404606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2920404606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/9.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.3177838419 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 111065519933 ps |
| CPU time | 801.36 seconds |
| Started | Aug 27 03:48:10 AM UTC 24 |
| Finished | Aug 27 04:01:41 AM UTC 24 |
| Peak memory | 199684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177838419 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.3177838419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/9.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all_with_rand_reset.2013853938 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 4330245890 ps |
| CPU time | 13.81 seconds |
| Started | Aug 27 03:48:07 AM UTC 24 |
| Finished | Aug 27 03:48:22 AM UTC 24 |
| Peak memory | 201920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2013853938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.rv_timer_stress_all_with_rand_reset.2013853938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/9.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.4059319093 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 166563839836 ps |
| CPU time | 1265.82 seconds |
| Started | Aug 27 04:16:20 AM UTC 24 |
| Finished | Aug 27 04:37:40 AM UTC 24 |
| Peak memory | 202548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059319093 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.4059319093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/90.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.3027747667 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 124671999829 ps |
| CPU time | 242.72 seconds |
| Started | Aug 27 04:16:20 AM UTC 24 |
| Finished | Aug 27 04:20:26 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027747667 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3027747667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/91.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.3378438891 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 91272478826 ps |
| CPU time | 135.49 seconds |
| Started | Aug 27 04:16:24 AM UTC 24 |
| Finished | Aug 27 04:18:43 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378438891 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3378438891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/92.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.2098799233 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 586960719398 ps |
| CPU time | 322.04 seconds |
| Started | Aug 27 04:16:27 AM UTC 24 |
| Finished | Aug 27 04:21:53 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098799233 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2098799233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/93.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.3530751864 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 162722371981 ps |
| CPU time | 507.88 seconds |
| Started | Aug 27 04:17:33 AM UTC 24 |
| Finished | Aug 27 04:26:07 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530751864 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3530751864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/95.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.1384527840 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 178258204018 ps |
| CPU time | 556.39 seconds |
| Started | Aug 27 04:17:34 AM UTC 24 |
| Finished | Aug 27 04:26:56 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384527840 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1384527840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/96.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.2970309796 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 113303129036 ps |
| CPU time | 249.1 seconds |
| Started | Aug 27 04:17:35 AM UTC 24 |
| Finished | Aug 27 04:21:48 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970309796 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2970309796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/97.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.4173494552 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 122911205555 ps |
| CPU time | 246.41 seconds |
| Started | Aug 27 04:17:42 AM UTC 24 |
| Finished | Aug 27 04:21:52 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173494552 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.4173494552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/98.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.3296138632 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 70399773717 ps |
| CPU time | 55.69 seconds |
| Started | Aug 27 04:17:58 AM UTC 24 |
| Finished | Aug 27 04:18:55 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296138632 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3296138632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/rv_timer-sim-vcs/99.rv_timer_random/latest |
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