| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.68 | 99.36 | 99.04 | 100.00 | 100.00 | 100.00 | 99.66 |
| T507 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.395857633 | Aug 28 07:05:32 PM UTC 24 | Aug 28 07:05:34 PM UTC 24 | 26068360 ps | ||
| T75 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.1601872086 | Aug 28 07:05:32 PM UTC 24 | Aug 28 07:05:34 PM UTC 24 | 36355432 ps | ||
| T508 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1061266963 | Aug 28 07:05:32 PM UTC 24 | Aug 28 07:05:34 PM UTC 24 | 25828405 ps | ||
| T509 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1685351051 | Aug 28 07:05:32 PM UTC 24 | Aug 28 07:05:35 PM UTC 24 | 373228292 ps | ||
| T510 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.2235236114 | Aug 28 07:05:34 PM UTC 24 | Aug 28 07:05:35 PM UTC 24 | 38805154 ps | ||
| T89 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3703725424 | Aug 28 07:05:34 PM UTC 24 | Aug 28 07:05:36 PM UTC 24 | 213516133 ps | ||
| T511 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1308550390 | Aug 28 07:05:33 PM UTC 24 | Aug 28 07:05:36 PM UTC 24 | 26939558 ps | ||
| T512 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.2118777520 | Aug 28 07:05:35 PM UTC 24 | Aug 28 07:05:37 PM UTC 24 | 24230978 ps | ||
| T513 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.851719232 | Aug 28 07:05:35 PM UTC 24 | Aug 28 07:05:37 PM UTC 24 | 14150033 ps | ||
| T514 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2709061659 | Aug 28 07:05:35 PM UTC 24 | Aug 28 07:05:37 PM UTC 24 | 83656787 ps | ||
| T515 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.452043116 | Aug 28 07:05:31 PM UTC 24 | Aug 28 07:05:37 PM UTC 24 | 990124267 ps | ||
| T516 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.262079618 | Aug 28 07:05:33 PM UTC 24 | Aug 28 07:05:37 PM UTC 24 | 37813820 ps | ||
| T517 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3124499085 | Aug 28 07:05:36 PM UTC 24 | Aug 28 07:05:39 PM UTC 24 | 437636862 ps | ||
| T518 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.2573179526 | Aug 28 07:05:37 PM UTC 24 | Aug 28 07:05:39 PM UTC 24 | 38628552 ps | ||
| T74 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.3799231848 | Aug 28 07:05:37 PM UTC 24 | Aug 28 07:05:39 PM UTC 24 | 24272098 ps | ||
| T519 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1904020545 | Aug 28 07:05:37 PM UTC 24 | Aug 28 07:05:39 PM UTC 24 | 12905129 ps | ||
| T520 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.870110719 | Aug 28 07:05:37 PM UTC 24 | Aug 28 07:05:39 PM UTC 24 | 22982055 ps | ||
| T521 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.4284743786 | Aug 28 07:05:38 PM UTC 24 | Aug 28 07:05:40 PM UTC 24 | 24795792 ps | ||
| T522 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.2446986832 | Aug 28 07:05:38 PM UTC 24 | Aug 28 07:05:40 PM UTC 24 | 237122491 ps | ||
| T523 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.2014721132 | Aug 28 07:05:36 PM UTC 24 | Aug 28 07:05:41 PM UTC 24 | 197421903 ps | ||
| T524 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3757489602 | Aug 28 07:05:39 PM UTC 24 | Aug 28 07:05:41 PM UTC 24 | 81347802 ps | ||
| T90 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.904004260 | Aug 28 07:05:38 PM UTC 24 | Aug 28 07:05:41 PM UTC 24 | 230760360 ps | ||
| T525 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3688834433 | Aug 28 07:05:39 PM UTC 24 | Aug 28 07:05:42 PM UTC 24 | 132445473 ps | ||
| T526 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.3421120684 | Aug 28 07:05:41 PM UTC 24 | Aug 28 07:05:42 PM UTC 24 | 57698918 ps | ||
| T76 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.1254108685 | Aug 28 07:05:41 PM UTC 24 | Aug 28 07:05:43 PM UTC 24 | 32022865 ps | ||
| T527 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1094360164 | Aug 28 07:05:41 PM UTC 24 | Aug 28 07:05:43 PM UTC 24 | 51232900 ps | ||
| T528 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.811962108 | Aug 28 07:05:40 PM UTC 24 | Aug 28 07:05:43 PM UTC 24 | 132991687 ps | ||
| T529 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.4130235092 | Aug 28 07:05:41 PM UTC 24 | Aug 28 07:05:43 PM UTC 24 | 69274750 ps | ||
| T530 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.2571971832 | Aug 28 07:05:38 PM UTC 24 | Aug 28 07:05:43 PM UTC 24 | 113198373 ps | ||
| T531 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.509519896 | Aug 28 07:05:42 PM UTC 24 | Aug 28 07:05:44 PM UTC 24 | 12984471 ps | ||
| T532 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.1719788566 | Aug 28 07:05:39 PM UTC 24 | Aug 28 07:05:44 PM UTC 24 | 200273059 ps | ||
| T533 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1363892876 | Aug 28 07:05:42 PM UTC 24 | Aug 28 07:05:44 PM UTC 24 | 148524310 ps | ||
| T534 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.3359880498 | Aug 28 07:05:52 PM UTC 24 | Aug 28 07:05:54 PM UTC 24 | 18906046 ps | ||
| T535 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.2012703331 | Aug 28 07:05:42 PM UTC 24 | Aug 28 07:05:45 PM UTC 24 | 94580184 ps | ||
| T77 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.1808430035 | Aug 28 07:05:43 PM UTC 24 | Aug 28 07:05:45 PM UTC 24 | 37396429 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2832559149 | Aug 28 07:05:43 PM UTC 24 | Aug 28 07:05:45 PM UTC 24 | 103844077 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.2616287228 | Aug 28 07:05:44 PM UTC 24 | Aug 28 07:05:46 PM UTC 24 | 23380914 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.1878815477 | Aug 28 07:05:44 PM UTC 24 | Aug 28 07:05:46 PM UTC 24 | 21760382 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1336222218 | Aug 28 07:05:44 PM UTC 24 | Aug 28 07:05:46 PM UTC 24 | 33249321 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.555414872 | Aug 28 07:05:43 PM UTC 24 | Aug 28 07:05:47 PM UTC 24 | 38816229 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.187596504 | Aug 28 07:05:43 PM UTC 24 | Aug 28 07:05:47 PM UTC 24 | 199635796 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.227022181 | Aug 28 07:05:46 PM UTC 24 | Aug 28 07:05:47 PM UTC 24 | 17636046 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3770328926 | Aug 28 07:05:44 PM UTC 24 | Aug 28 07:05:47 PM UTC 24 | 233699728 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.2192220277 | Aug 28 07:05:46 PM UTC 24 | Aug 28 07:05:47 PM UTC 24 | 13535729 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.4244819880 | Aug 28 07:05:46 PM UTC 24 | Aug 28 07:05:48 PM UTC 24 | 118383995 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2127492438 | Aug 28 07:05:45 PM UTC 24 | Aug 28 07:05:48 PM UTC 24 | 96717070 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.36791055 | Aug 28 07:05:47 PM UTC 24 | Aug 28 07:05:49 PM UTC 24 | 20054673 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.2323227183 | Aug 28 07:05:47 PM UTC 24 | Aug 28 07:05:49 PM UTC 24 | 40922533 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2702745568 | Aug 28 07:05:47 PM UTC 24 | Aug 28 07:05:49 PM UTC 24 | 21228262 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.222190227 | Aug 28 07:05:52 PM UTC 24 | Aug 28 07:05:54 PM UTC 24 | 112166929 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.1288919389 | Aug 28 07:05:45 PM UTC 24 | Aug 28 07:05:50 PM UTC 24 | 134313754 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.620323833 | Aug 28 07:05:48 PM UTC 24 | Aug 28 07:05:50 PM UTC 24 | 37405569 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.3559902867 | Aug 28 07:05:48 PM UTC 24 | Aug 28 07:05:50 PM UTC 24 | 14612171 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.138271006 | Aug 28 07:05:48 PM UTC 24 | Aug 28 07:05:50 PM UTC 24 | 31024078 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.3979882125 | Aug 28 07:05:48 PM UTC 24 | Aug 28 07:05:50 PM UTC 24 | 11756057 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.2402637338 | Aug 28 07:05:48 PM UTC 24 | Aug 28 07:05:50 PM UTC 24 | 29443589 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4083769452 | Aug 28 07:05:47 PM UTC 24 | Aug 28 07:05:50 PM UTC 24 | 37884603 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.954819201 | Aug 28 07:05:49 PM UTC 24 | Aug 28 07:05:51 PM UTC 24 | 25367523 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.631033048 | Aug 28 07:05:49 PM UTC 24 | Aug 28 07:05:51 PM UTC 24 | 47087951 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.1411881932 | Aug 28 07:05:49 PM UTC 24 | Aug 28 07:05:51 PM UTC 24 | 26151267 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.906629558 | Aug 28 07:05:49 PM UTC 24 | Aug 28 07:05:51 PM UTC 24 | 14891614 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.561622144 | Aug 28 07:05:49 PM UTC 24 | Aug 28 07:05:51 PM UTC 24 | 45223250 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.2632815265 | Aug 28 07:05:52 PM UTC 24 | Aug 28 07:05:54 PM UTC 24 | 34760940 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.1457463750 | Aug 28 07:05:50 PM UTC 24 | Aug 28 07:05:52 PM UTC 24 | 42640727 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.890473988 | Aug 28 07:05:51 PM UTC 24 | Aug 28 07:05:52 PM UTC 24 | 29438178 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.893473373 | Aug 28 07:05:50 PM UTC 24 | Aug 28 07:05:52 PM UTC 24 | 58457856 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.3954532323 | Aug 28 07:05:51 PM UTC 24 | Aug 28 07:05:52 PM UTC 24 | 50129534 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.2481529062 | Aug 28 07:05:51 PM UTC 24 | Aug 28 07:05:52 PM UTC 24 | 24129051 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.1111697644 | Aug 28 07:05:51 PM UTC 24 | Aug 28 07:05:52 PM UTC 24 | 26667141 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.4217080978 | Aug 28 07:05:51 PM UTC 24 | Aug 28 07:05:52 PM UTC 24 | 17244526 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.3443016793 | Aug 28 07:05:52 PM UTC 24 | Aug 28 07:05:54 PM UTC 24 | 49269764 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.3801904999 | Aug 28 07:05:52 PM UTC 24 | Aug 28 07:05:54 PM UTC 24 | 22989608 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.1661579052 | Aug 28 07:05:53 PM UTC 24 | Aug 28 07:05:55 PM UTC 24 | 12346689 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.2046418216 | Aug 28 07:05:53 PM UTC 24 | Aug 28 07:05:55 PM UTC 24 | 14707604 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.4252936571 | Aug 28 07:05:53 PM UTC 24 | Aug 28 07:05:55 PM UTC 24 | 14743386 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.3856769999 | Aug 28 07:05:53 PM UTC 24 | Aug 28 07:05:55 PM UTC 24 | 124425063 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.2696353595 | Aug 28 07:05:53 PM UTC 24 | Aug 28 07:05:55 PM UTC 24 | 48677388 ps | ||
| T578 | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.1393314100 | Aug 28 07:05:53 PM UTC 24 | Aug 28 07:05:55 PM UTC 24 | 15205044 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.1567615113 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 7025643692 ps |
| CPU time | 23.77 seconds |
| Started | Aug 28 06:26:33 PM UTC 24 |
| Finished | Aug 28 06:26:58 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567615113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1567615113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/23.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all_with_rand_reset.659096756 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 4559672574 ps |
| CPU time | 21.9 seconds |
| Started | Aug 28 06:26:09 PM UTC 24 |
| Finished | Aug 28 06:26:32 PM UTC 24 |
| Peak memory | 201844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=659096756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.659096756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/22.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.511285154 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 390475242752 ps |
| CPU time | 103.07 seconds |
| Started | Aug 28 06:26:48 PM UTC 24 |
| Finished | Aug 28 06:28:33 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511285154 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.511285154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/24.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2876709084 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 40753110 ps |
| CPU time | 1.2 seconds |
| Started | Aug 28 07:04:43 PM UTC 24 |
| Finished | Aug 28 07:04:45 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876709084 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.2876709084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.4206915205 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 518631755043 ps |
| CPU time | 1228.88 seconds |
| Started | Aug 28 06:26:59 PM UTC 24 |
| Finished | Aug 28 06:47:44 PM UTC 24 |
| Peak memory | 202452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206915205 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.4206915205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/24.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.2066773134 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1173648641055 ps |
| CPU time | 1359.16 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:44:07 PM UTC 24 |
| Peak memory | 202412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066773134 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.2066773134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.1184304383 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 488315525567 ps |
| CPU time | 4907.5 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 07:44:03 PM UTC 24 |
| Peak memory | 202588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184304383 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.1184304383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/6.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1255755320 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 63251159 ps |
| CPU time | 1.1 seconds |
| Started | Aug 28 07:04:48 PM UTC 24 |
| Finished | Aug 28 07:04:50 PM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255755320 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.1255755320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.1840539445 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 161098161251 ps |
| CPU time | 193.01 seconds |
| Started | Aug 28 06:23:17 PM UTC 24 |
| Finished | Aug 28 06:26:33 PM UTC 24 |
| Peak memory | 199916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840539445 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.1840539445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/17.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.3191813163 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 407094843983 ps |
| CPU time | 822.95 seconds |
| Started | Aug 28 06:29:11 PM UTC 24 |
| Finished | Aug 28 06:43:07 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191813163 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.3191813163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/27.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.3781335595 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 2607387814955 ps |
| CPU time | 2586.53 seconds |
| Started | Aug 28 06:28:12 PM UTC 24 |
| Finished | Aug 28 07:11:52 PM UTC 24 |
| Peak memory | 202356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781335595 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.3781335595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/26.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.1023175930 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 583263084270 ps |
| CPU time | 2264.69 seconds |
| Started | Aug 28 06:40:52 PM UTC 24 |
| Finished | Aug 28 07:19:07 PM UTC 24 |
| Peak memory | 199620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023175930 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.1023175930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/43.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.1355957097 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 502760854405 ps |
| CPU time | 2443.82 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 07:02:30 PM UTC 24 |
| Peak memory | 202356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355957097 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.1355957097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/7.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.2020310290 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1593064136632 ps |
| CPU time | 1017.53 seconds |
| Started | Aug 28 06:21:16 PM UTC 24 |
| Finished | Aug 28 06:38:29 PM UTC 24 |
| Peak memory | 202592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020310290 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.2020310290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/10.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.3098244068 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 752640334493 ps |
| CPU time | 1384.15 seconds |
| Started | Aug 28 06:31:37 PM UTC 24 |
| Finished | Aug 28 06:55:00 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098244068 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.3098244068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/31.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.3157317982 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 766452456214 ps |
| CPU time | 784.4 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:34:28 PM UTC 24 |
| Peak memory | 199812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157317982 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3157317982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/8.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.1929847502 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 172509728 ps |
| CPU time | 1.03 seconds |
| Started | Aug 28 06:21:06 PM UTC 24 |
| Finished | Aug 28 06:21:08 PM UTC 24 |
| Peak memory | 230928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929847502 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1929847502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.1467012052 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 190634478489 ps |
| CPU time | 643.92 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:32:03 PM UTC 24 |
| Peak memory | 202400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467012052 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1467012052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/5.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.2781374364 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 933854544879 ps |
| CPU time | 1425.49 seconds |
| Started | Aug 28 06:21:08 PM UTC 24 |
| Finished | Aug 28 06:45:12 PM UTC 24 |
| Peak memory | 202428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781374364 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.2781374364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.1315143237 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 136382402527 ps |
| CPU time | 474.13 seconds |
| Started | Aug 28 06:32:53 PM UTC 24 |
| Finished | Aug 28 06:40:55 PM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315143237 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1315143237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/34.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.3735731594 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 521038180356 ps |
| CPU time | 869.13 seconds |
| Started | Aug 28 06:49:16 PM UTC 24 |
| Finished | Aug 28 07:03:59 PM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735731594 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3735731594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/95.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.2527461354 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 701950115465 ps |
| CPU time | 815.17 seconds |
| Started | Aug 28 06:29:24 PM UTC 24 |
| Finished | Aug 28 06:43:12 PM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527461354 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2527461354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/28.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.332736722 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 313251466159 ps |
| CPU time | 297.52 seconds |
| Started | Aug 28 06:21:24 PM UTC 24 |
| Finished | Aug 28 06:26:25 PM UTC 24 |
| Peak memory | 199756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332736722 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.332736722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/12.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.2038458695 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 737860662886 ps |
| CPU time | 2906.72 seconds |
| Started | Aug 28 06:22:07 PM UTC 24 |
| Finished | Aug 28 07:11:13 PM UTC 24 |
| Peak memory | 202452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038458695 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.2038458695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/15.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.1015000196 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 238913994075 ps |
| CPU time | 608.59 seconds |
| Started | Aug 28 06:38:23 PM UTC 24 |
| Finished | Aug 28 06:48:40 PM UTC 24 |
| Peak memory | 199616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015000196 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.1015000196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/40.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.3436323627 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 154679452273 ps |
| CPU time | 311.68 seconds |
| Started | Aug 28 06:46:57 PM UTC 24 |
| Finished | Aug 28 06:52:15 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436323627 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3436323627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/70.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.4264465044 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 592107459329 ps |
| CPU time | 3237.72 seconds |
| Started | Aug 28 06:53:32 PM UTC 24 |
| Finished | Aug 28 07:48:13 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264465044 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.4264465044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/118.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.2337467327 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 115017045919 ps |
| CPU time | 297.18 seconds |
| Started | Aug 28 06:53:38 PM UTC 24 |
| Finished | Aug 28 06:58:41 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337467327 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2337467327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/120.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.1280300342 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 531472380016 ps |
| CPU time | 1054.79 seconds |
| Started | Aug 28 06:57:48 PM UTC 24 |
| Finished | Aug 28 07:15:38 PM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280300342 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1280300342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/145.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.1613487630 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 115274857322 ps |
| CPU time | 640.31 seconds |
| Started | Aug 28 06:59:25 PM UTC 24 |
| Finished | Aug 28 07:10:16 PM UTC 24 |
| Peak memory | 199904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613487630 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1613487630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/158.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.3605253341 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 131819687039 ps |
| CPU time | 1118.76 seconds |
| Started | Aug 28 06:52:37 PM UTC 24 |
| Finished | Aug 28 07:11:33 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605253341 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3605253341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/116.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.225567011 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 825962541885 ps |
| CPU time | 2176.43 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:57:56 PM UTC 24 |
| Peak memory | 202328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225567011 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.225567011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.2028132436 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 172205633987 ps |
| CPU time | 739.13 seconds |
| Started | Aug 28 06:47:05 PM UTC 24 |
| Finished | Aug 28 06:59:35 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028132436 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2028132436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/73.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.867894507 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 3316385949159 ps |
| CPU time | 1612.62 seconds |
| Started | Aug 28 06:21:06 PM UTC 24 |
| Finished | Aug 28 06:48:21 PM UTC 24 |
| Peak memory | 202352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867894507 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.867894507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.3203570172 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 289578143681 ps |
| CPU time | 222.27 seconds |
| Started | Aug 28 06:21:15 PM UTC 24 |
| Finished | Aug 28 06:25:01 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203570172 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.3203570172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.3258049707 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 619481462258 ps |
| CPU time | 3422.45 seconds |
| Started | Aug 28 06:21:15 PM UTC 24 |
| Finished | Aug 28 07:19:02 PM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258049707 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3258049707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/10.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.2364677924 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 162346566181 ps |
| CPU time | 561.21 seconds |
| Started | Aug 28 06:54:53 PM UTC 24 |
| Finished | Aug 28 07:04:23 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364677924 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2364677924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/128.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.2784922367 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 234796816844 ps |
| CPU time | 563.58 seconds |
| Started | Aug 28 06:30:10 PM UTC 24 |
| Finished | Aug 28 06:39:43 PM UTC 24 |
| Peak memory | 199616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784922367 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.2784922367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/29.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.4266467112 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 499725695173 ps |
| CPU time | 643.87 seconds |
| Started | Aug 28 06:50:17 PM UTC 24 |
| Finished | Aug 28 07:01:12 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266467112 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.4266467112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/102.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.1918899966 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 232130760666 ps |
| CPU time | 352.62 seconds |
| Started | Aug 28 06:50:42 PM UTC 24 |
| Finished | Aug 28 06:56:41 PM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918899966 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1918899966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/105.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.425457315 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1644129113840 ps |
| CPU time | 632.04 seconds |
| Started | Aug 28 06:53:10 PM UTC 24 |
| Finished | Aug 28 07:03:52 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425457315 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.425457315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/117.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.3907722647 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 245469758528 ps |
| CPU time | 677.33 seconds |
| Started | Aug 28 06:56:42 PM UTC 24 |
| Finished | Aug 28 07:08:10 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907722647 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3907722647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/139.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.1739380928 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 3370777946743 ps |
| CPU time | 1626.61 seconds |
| Started | Aug 28 06:59:10 PM UTC 24 |
| Finished | Aug 28 07:26:40 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739380928 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1739380928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/157.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.37734400 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 882595218121 ps |
| CPU time | 1139.81 seconds |
| Started | Aug 28 06:25:01 PM UTC 24 |
| Finished | Aug 28 06:44:18 PM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37734400 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.37734400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/20.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.3265613427 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 856049946027 ps |
| CPU time | 546.55 seconds |
| Started | Aug 28 06:31:02 PM UTC 24 |
| Finished | Aug 28 06:40:17 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265613427 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3265613427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/31.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.3435740084 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 139516003333 ps |
| CPU time | 1360.64 seconds |
| Started | Aug 28 06:43:02 PM UTC 24 |
| Finished | Aug 28 07:06:04 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435740084 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3435740084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/48.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.3592585619 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 150555801121 ps |
| CPU time | 717.77 seconds |
| Started | Aug 28 06:52:15 PM UTC 24 |
| Finished | Aug 28 07:04:24 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592585619 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3592585619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/113.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.3603829630 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 140321581445 ps |
| CPU time | 334.87 seconds |
| Started | Aug 28 06:58:38 PM UTC 24 |
| Finished | Aug 28 07:04:18 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603829630 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3603829630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/150.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.2295152722 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 101038772060 ps |
| CPU time | 1699.72 seconds |
| Started | Aug 28 06:59:40 PM UTC 24 |
| Finished | Aug 28 07:28:23 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295152722 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2295152722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/164.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.2243542429 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 689541013701 ps |
| CPU time | 1957.45 seconds |
| Started | Aug 28 07:03:07 PM UTC 24 |
| Finished | Aug 28 07:36:11 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243542429 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2243542429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/185.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.1841780456 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 34227810497 ps |
| CPU time | 14.88 seconds |
| Started | Aug 28 06:21:07 PM UTC 24 |
| Finished | Aug 28 06:21:23 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841780456 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1841780456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.1683313267 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 44822382773 ps |
| CPU time | 681.8 seconds |
| Started | Aug 28 06:37:16 PM UTC 24 |
| Finished | Aug 28 06:48:48 PM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683313267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1683313267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/38.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.1800394683 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 867628042334 ps |
| CPU time | 1983.68 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:54:41 PM UTC 24 |
| Peak memory | 202444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800394683 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1800394683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/7.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.3680757629 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 109211771290 ps |
| CPU time | 2000.15 seconds |
| Started | Aug 28 06:21:06 PM UTC 24 |
| Finished | Aug 28 06:54:55 PM UTC 24 |
| Peak memory | 202300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680757629 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3680757629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.3448482213 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1070196907162 ps |
| CPU time | 1264.84 seconds |
| Started | Aug 28 06:21:07 PM UTC 24 |
| Finished | Aug 28 06:42:29 PM UTC 24 |
| Peak memory | 202524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448482213 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.3448482213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.1491309659 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 350346673071 ps |
| CPU time | 1113.82 seconds |
| Started | Aug 28 06:21:17 PM UTC 24 |
| Finished | Aug 28 06:40:05 PM UTC 24 |
| Peak memory | 202332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491309659 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.1491309659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.3256412865 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 107463378807 ps |
| CPU time | 382.28 seconds |
| Started | Aug 28 06:54:14 PM UTC 24 |
| Finished | Aug 28 07:00:44 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256412865 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3256412865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/124.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.1318516085 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 127137003606 ps |
| CPU time | 362.29 seconds |
| Started | Aug 28 06:56:58 PM UTC 24 |
| Finished | Aug 28 07:03:05 PM UTC 24 |
| Peak memory | 199608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318516085 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1318516085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/140.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.4239738287 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 92188052569 ps |
| CPU time | 242.43 seconds |
| Started | Aug 28 07:03:09 PM UTC 24 |
| Finished | Aug 28 07:07:17 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239738287 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.4239738287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/186.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.2691822728 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 144727218160 ps |
| CPU time | 164.6 seconds |
| Started | Aug 28 06:24:50 PM UTC 24 |
| Finished | Aug 28 06:27:37 PM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691822728 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.2691822728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.3026788732 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 51635681578 ps |
| CPU time | 114.86 seconds |
| Started | Aug 28 06:26:15 PM UTC 24 |
| Finished | Aug 28 06:28:12 PM UTC 24 |
| Peak memory | 199904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026788732 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3026788732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/23.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.1274088082 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1444549096625 ps |
| CPU time | 1065.18 seconds |
| Started | Aug 28 06:41:36 PM UTC 24 |
| Finished | Aug 28 06:59:35 PM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274088082 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.1274088082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/44.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.2106790742 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 99308577142 ps |
| CPU time | 279 seconds |
| Started | Aug 28 06:49:12 PM UTC 24 |
| Finished | Aug 28 06:53:57 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106790742 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2106790742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/94.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1910073933 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 19611875 ps |
| CPU time | 1.1 seconds |
| Started | Aug 28 07:04:49 PM UTC 24 |
| Finished | Aug 28 07:04:51 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910073933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.1910073933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3008370117 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 344390112 ps |
| CPU time | 3.84 seconds |
| Started | Aug 28 07:04:54 PM UTC 24 |
| Finished | Aug 28 07:04:59 PM UTC 24 |
| Peak memory | 200816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008370117 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.3008370117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.811962108 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 132991687 ps |
| CPU time | 2.18 seconds |
| Started | Aug 28 07:05:40 PM UTC 24 |
| Finished | Aug 28 07:05:43 PM UTC 24 |
| Peak memory | 200888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811962108 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.811962108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.2913524951 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 46018769798 ps |
| CPU time | 117.25 seconds |
| Started | Aug 28 06:50:36 PM UTC 24 |
| Finished | Aug 28 06:52:36 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913524951 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2913524951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/103.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.3789042775 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 107837558740 ps |
| CPU time | 317.41 seconds |
| Started | Aug 28 06:50:58 PM UTC 24 |
| Finished | Aug 28 06:56:21 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789042775 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3789042775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/108.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.1908840843 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 737043624910 ps |
| CPU time | 525.5 seconds |
| Started | Aug 28 06:21:19 PM UTC 24 |
| Finished | Aug 28 06:30:12 PM UTC 24 |
| Peak memory | 199620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908840843 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.1908840843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/11.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.9352415 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 495853645435 ps |
| CPU time | 607.27 seconds |
| Started | Aug 28 06:51:58 PM UTC 24 |
| Finished | Aug 28 07:02:15 PM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9352415 -assert nopostproc +UVM_TESTNAME=r v_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.9352415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/111.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.211753831 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 567845265862 ps |
| CPU time | 421.14 seconds |
| Started | Aug 28 06:52:30 PM UTC 24 |
| Finished | Aug 28 06:59:37 PM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211753831 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.211753831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/115.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.56372919 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 110602476741 ps |
| CPU time | 245.44 seconds |
| Started | Aug 28 07:01:01 PM UTC 24 |
| Finished | Aug 28 07:05:11 PM UTC 24 |
| Peak memory | 199752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56372919 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.56372919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/167.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.2451719255 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 317808422531 ps |
| CPU time | 278.98 seconds |
| Started | Aug 28 06:23:00 PM UTC 24 |
| Finished | Aug 28 06:27:43 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451719255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2451719255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/17.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.1062619780 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 276188366674 ps |
| CPU time | 169.52 seconds |
| Started | Aug 28 07:01:45 PM UTC 24 |
| Finished | Aug 28 07:04:39 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062619780 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1062619780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/173.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.565470519 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 614353970259 ps |
| CPU time | 983.7 seconds |
| Started | Aug 28 07:04:18 PM UTC 24 |
| Finished | Aug 28 07:20:56 PM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565470519 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.565470519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/196.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.347489976 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 97412001886 ps |
| CPU time | 260.48 seconds |
| Started | Aug 28 06:27:38 PM UTC 24 |
| Finished | Aug 28 06:32:02 PM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347489976 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.347489976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/26.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.324901828 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 92065085449 ps |
| CPU time | 170.09 seconds |
| Started | Aug 28 06:46:16 PM UTC 24 |
| Finished | Aug 28 06:49:09 PM UTC 24 |
| Peak memory | 199868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324901828 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.324901828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/61.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.3612071950 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 15385169165 ps |
| CPU time | 14.17 seconds |
| Started | Aug 28 06:47:17 PM UTC 24 |
| Finished | Aug 28 06:47:32 PM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612071950 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3612071950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/75.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.4261944081 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 584058897521 ps |
| CPU time | 347.62 seconds |
| Started | Aug 28 06:21:06 PM UTC 24 |
| Finished | Aug 28 06:26:59 PM UTC 24 |
| Peak memory | 202320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261944081 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.4261944081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.2032581098 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 77507406287 ps |
| CPU time | 211.47 seconds |
| Started | Aug 28 06:50:17 PM UTC 24 |
| Finished | Aug 28 06:53:53 PM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032581098 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2032581098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/101.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.207345495 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 42481244134 ps |
| CPU time | 617.84 seconds |
| Started | Aug 28 06:50:44 PM UTC 24 |
| Finished | Aug 28 07:01:13 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207345495 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.207345495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/107.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.1024712359 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 115262014947 ps |
| CPU time | 433 seconds |
| Started | Aug 28 06:51:25 PM UTC 24 |
| Finished | Aug 28 06:58:45 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024712359 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1024712359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/109.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.2972833114 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 192047319243 ps |
| CPU time | 2756.56 seconds |
| Started | Aug 28 06:21:16 PM UTC 24 |
| Finished | Aug 28 07:07:47 PM UTC 24 |
| Peak memory | 202608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972833114 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2972833114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/11.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.916685854 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 214312760205 ps |
| CPU time | 264.41 seconds |
| Started | Aug 28 06:21:18 PM UTC 24 |
| Finished | Aug 28 06:25:46 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916685854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.916685854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/11.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.3584882583 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 75013426858 ps |
| CPU time | 217.03 seconds |
| Started | Aug 28 06:52:15 PM UTC 24 |
| Finished | Aug 28 06:55:57 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584882583 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3584882583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/112.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.755594353 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 304720366782 ps |
| CPU time | 149.44 seconds |
| Started | Aug 28 06:54:56 PM UTC 24 |
| Finished | Aug 28 06:57:28 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755594353 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.755594353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/129.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.3183521911 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 223309499788 ps |
| CPU time | 479.94 seconds |
| Started | Aug 28 06:21:24 PM UTC 24 |
| Finished | Aug 28 06:29:30 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183521911 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3183521911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/13.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.2128594076 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 1444547638870 ps |
| CPU time | 1877.1 seconds |
| Started | Aug 28 06:21:30 PM UTC 24 |
| Finished | Aug 28 06:53:09 PM UTC 24 |
| Peak memory | 202432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128594076 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.2128594076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/13.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.2889292624 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 457354190114 ps |
| CPU time | 674.97 seconds |
| Started | Aug 28 06:56:38 PM UTC 24 |
| Finished | Aug 28 07:08:02 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889292624 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2889292624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/138.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.469483086 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 53119582544 ps |
| CPU time | 76.54 seconds |
| Started | Aug 28 06:21:33 PM UTC 24 |
| Finished | Aug 28 06:22:52 PM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469483086 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.469483086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.3435995012 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 374532825207 ps |
| CPU time | 255.88 seconds |
| Started | Aug 28 06:56:59 PM UTC 24 |
| Finished | Aug 28 07:01:19 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435995012 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3435995012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/141.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.1344582739 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 266550492226 ps |
| CPU time | 229.13 seconds |
| Started | Aug 28 06:58:42 PM UTC 24 |
| Finished | Aug 28 07:02:35 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344582739 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1344582739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/152.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.1064888145 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 403403977143 ps |
| CPU time | 414.24 seconds |
| Started | Aug 28 06:59:26 PM UTC 24 |
| Finished | Aug 28 07:06:27 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064888145 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1064888145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/159.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.1393418518 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 83710982433 ps |
| CPU time | 203.15 seconds |
| Started | Aug 28 06:59:36 PM UTC 24 |
| Finished | Aug 28 07:03:03 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393418518 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1393418518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/160.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.1735779548 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 567551259071 ps |
| CPU time | 485 seconds |
| Started | Aug 28 06:59:40 PM UTC 24 |
| Finished | Aug 28 07:07:51 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735779548 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1735779548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/163.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.3186953873 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 547427109085 ps |
| CPU time | 361.5 seconds |
| Started | Aug 28 07:00:29 PM UTC 24 |
| Finished | Aug 28 07:06:36 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186953873 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3186953873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/165.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.864406174 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 588340391685 ps |
| CPU time | 1057.91 seconds |
| Started | Aug 28 07:01:47 PM UTC 24 |
| Finished | Aug 28 07:19:41 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864406174 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.864406174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/174.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.3022783936 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1253804079654 ps |
| CPU time | 696.21 seconds |
| Started | Aug 28 07:02:02 PM UTC 24 |
| Finished | Aug 28 07:13:48 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022783936 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3022783936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/176.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.3353877545 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 584602113824 ps |
| CPU time | 311.77 seconds |
| Started | Aug 28 07:02:11 PM UTC 24 |
| Finished | Aug 28 07:07:28 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353877545 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3353877545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/177.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.75983740 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 119527284116 ps |
| CPU time | 596.39 seconds |
| Started | Aug 28 07:02:31 PM UTC 24 |
| Finished | Aug 28 07:12:36 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75983740 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.75983740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/179.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.3368958437 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 164418656215 ps |
| CPU time | 388.5 seconds |
| Started | Aug 28 07:02:35 PM UTC 24 |
| Finished | Aug 28 07:09:11 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368958437 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3368958437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/180.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.252706977 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 172827256311 ps |
| CPU time | 376.9 seconds |
| Started | Aug 28 07:03:03 PM UTC 24 |
| Finished | Aug 28 07:09:26 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252706977 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.252706977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/182.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.4167448588 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 266423985699 ps |
| CPU time | 606.39 seconds |
| Started | Aug 28 07:03:11 PM UTC 24 |
| Finished | Aug 28 07:13:27 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167448588 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.4167448588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/187.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.1526142620 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 118467277295 ps |
| CPU time | 313.3 seconds |
| Started | Aug 28 06:27:07 PM UTC 24 |
| Finished | Aug 28 06:32:24 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526142620 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1526142620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/25.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.196350709 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 419805691178 ps |
| CPU time | 975.92 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:37:38 PM UTC 24 |
| Peak memory | 202520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196350709 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.196350709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.1784271874 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 778883608396 ps |
| CPU time | 285.46 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:25:59 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784271874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1784271874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.83730446 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 669610640254 ps |
| CPU time | 444.92 seconds |
| Started | Aug 28 06:39:44 PM UTC 24 |
| Finished | Aug 28 06:47:16 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83730446 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.83730446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/42.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.358540518 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 2098373098108 ps |
| CPU time | 2479.02 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 07:03:02 PM UTC 24 |
| Peak memory | 202328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358540518 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.358540518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/8.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.2086682005 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 106917390523 ps |
| CPU time | 248.93 seconds |
| Started | Aug 28 06:49:24 PM UTC 24 |
| Finished | Aug 28 06:53:37 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086682005 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2086682005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/97.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.260413350 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 281282555 ps |
| CPU time | 3.98 seconds |
| Started | Aug 28 07:04:48 PM UTC 24 |
| Finished | Aug 28 07:04:53 PM UTC 24 |
| Peak memory | 200688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260413350 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.260413350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2651147112 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 49827323 ps |
| CPU time | 0.84 seconds |
| Started | Aug 28 07:04:46 PM UTC 24 |
| Finished | Aug 28 07:04:48 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651147112 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.2651147112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2421132355 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 55674744 ps |
| CPU time | 1.16 seconds |
| Started | Aug 28 07:04:49 PM UTC 24 |
| Finished | Aug 28 07:04:51 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2421132355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_cs r_mem_rw_with_rand_reset.2421132355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.4178233003 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 34148415 ps |
| CPU time | 0.81 seconds |
| Started | Aug 28 07:04:47 PM UTC 24 |
| Finished | Aug 28 07:04:49 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178233003 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.4178233003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.847569326 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 29767886 ps |
| CPU time | 0.85 seconds |
| Started | Aug 28 07:04:46 PM UTC 24 |
| Finished | Aug 28 07:04:48 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847569326 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.847569326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.673094247 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 112898540 ps |
| CPU time | 4.04 seconds |
| Started | Aug 28 07:04:39 PM UTC 24 |
| Finished | Aug 28 07:04:45 PM UTC 24 |
| Peak memory | 200740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=673094247 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.673094247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.169681160 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 154609689 ps |
| CPU time | 1.19 seconds |
| Started | Aug 28 07:04:55 PM UTC 24 |
| Finished | Aug 28 07:04:58 PM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169681160 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.169681160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1115680273 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 36083193 ps |
| CPU time | 0.79 seconds |
| Started | Aug 28 07:04:52 PM UTC 24 |
| Finished | Aug 28 07:04:54 PM UTC 24 |
| Peak memory | 198760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115680273 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.1115680273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.526504641 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 162615657 ps |
| CPU time | 0.94 seconds |
| Started | Aug 28 07:04:55 PM UTC 24 |
| Finished | Aug 28 07:04:58 PM UTC 24 |
| Peak memory | 198980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=526504641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr _mem_rw_with_rand_reset.526504641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.2597345855 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 113972599 ps |
| CPU time | 0.87 seconds |
| Started | Aug 28 07:04:53 PM UTC 24 |
| Finished | Aug 28 07:04:55 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597345855 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2597345855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.2368180892 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 42875825 ps |
| CPU time | 0.84 seconds |
| Started | Aug 28 07:04:52 PM UTC 24 |
| Finished | Aug 28 07:04:54 PM UTC 24 |
| Peak memory | 198476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368180892 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2368180892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.603779737 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 17189207 ps |
| CPU time | 1.04 seconds |
| Started | Aug 28 07:04:55 PM UTC 24 |
| Finished | Aug 28 07:04:58 PM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603779737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.603779737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.1064111327 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 371963455 ps |
| CPU time | 2.02 seconds |
| Started | Aug 28 07:04:50 PM UTC 24 |
| Finished | Aug 28 07:04:53 PM UTC 24 |
| Peak memory | 202796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064111327 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1064111327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1634832963 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 450491631 ps |
| CPU time | 1.69 seconds |
| Started | Aug 28 07:04:51 PM UTC 24 |
| Finished | Aug 28 07:04:54 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634832963 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.1634832963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.4006466328 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 58451242 ps |
| CPU time | 0.92 seconds |
| Started | Aug 28 07:05:28 PM UTC 24 |
| Finished | Aug 28 07:05:30 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4006466328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_c sr_mem_rw_with_rand_reset.4006466328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.422329163 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 24607911 ps |
| CPU time | 0.89 seconds |
| Started | Aug 28 07:05:28 PM UTC 24 |
| Finished | Aug 28 07:05:30 PM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422329163 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.422329163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.2908088702 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 17991270 ps |
| CPU time | 0.87 seconds |
| Started | Aug 28 07:05:28 PM UTC 24 |
| Finished | Aug 28 07:05:29 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908088702 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2908088702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/10.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2120793761 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 64580539 ps |
| CPU time | 0.94 seconds |
| Started | Aug 28 07:05:28 PM UTC 24 |
| Finished | Aug 28 07:05:30 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120793761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.2120793761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.3869363987 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2301015429 ps |
| CPU time | 3.44 seconds |
| Started | Aug 28 07:05:27 PM UTC 24 |
| Finished | Aug 28 07:05:31 PM UTC 24 |
| Peak memory | 200740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869363987 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3869363987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1336663618 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 71059960 ps |
| CPU time | 1.34 seconds |
| Started | Aug 28 07:05:27 PM UTC 24 |
| Finished | Aug 28 07:05:29 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336663618 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.1336663618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3595071873 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 82512551 ps |
| CPU time | 1.04 seconds |
| Started | Aug 28 07:05:30 PM UTC 24 |
| Finished | Aug 28 07:05:32 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3595071873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_c sr_mem_rw_with_rand_reset.3595071873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.34121105 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 11543507 ps |
| CPU time | 0.84 seconds |
| Started | Aug 28 07:05:30 PM UTC 24 |
| Finished | Aug 28 07:05:32 PM UTC 24 |
| Peak memory | 198484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34121105 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.34121105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.2169244178 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 17325815 ps |
| CPU time | 0.81 seconds |
| Started | Aug 28 07:05:30 PM UTC 24 |
| Finished | Aug 28 07:05:32 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169244178 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2169244178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/11.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.965832397 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 15992529 ps |
| CPU time | 0.99 seconds |
| Started | Aug 28 07:05:30 PM UTC 24 |
| Finished | Aug 28 07:05:32 PM UTC 24 |
| Peak memory | 198848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965832397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.965832397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.3465270781 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 36283744 ps |
| CPU time | 2.49 seconds |
| Started | Aug 28 07:05:29 PM UTC 24 |
| Finished | Aug 28 07:05:32 PM UTC 24 |
| Peak memory | 200748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465270781 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3465270781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.473664361 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 49484968 ps |
| CPU time | 1.06 seconds |
| Started | Aug 28 07:05:30 PM UTC 24 |
| Finished | Aug 28 07:05:32 PM UTC 24 |
| Peak memory | 198804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473664361 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.473664361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1308550390 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 26939558 ps |
| CPU time | 1.65 seconds |
| Started | Aug 28 07:05:33 PM UTC 24 |
| Finished | Aug 28 07:05:36 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1308550390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_c sr_mem_rw_with_rand_reset.1308550390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.1601872086 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 36355432 ps |
| CPU time | 0.84 seconds |
| Started | Aug 28 07:05:32 PM UTC 24 |
| Finished | Aug 28 07:05:34 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601872086 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1601872086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.395857633 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 26068360 ps |
| CPU time | 0.82 seconds |
| Started | Aug 28 07:05:32 PM UTC 24 |
| Finished | Aug 28 07:05:34 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395857633 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.395857633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/12.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1061266963 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 25828405 ps |
| CPU time | 0.89 seconds |
| Started | Aug 28 07:05:32 PM UTC 24 |
| Finished | Aug 28 07:05:34 PM UTC 24 |
| Peak memory | 198848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061266963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.1061266963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.452043116 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 990124267 ps |
| CPU time | 4.79 seconds |
| Started | Aug 28 07:05:31 PM UTC 24 |
| Finished | Aug 28 07:05:37 PM UTC 24 |
| Peak memory | 200748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452043116 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.452043116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1685351051 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 373228292 ps |
| CPU time | 1.91 seconds |
| Started | Aug 28 07:05:32 PM UTC 24 |
| Finished | Aug 28 07:05:35 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685351051 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.1685351051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2709061659 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 83656787 ps |
| CPU time | 1.08 seconds |
| Started | Aug 28 07:05:35 PM UTC 24 |
| Finished | Aug 28 07:05:37 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2709061659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_c sr_mem_rw_with_rand_reset.2709061659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.2118777520 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 24230978 ps |
| CPU time | 0.89 seconds |
| Started | Aug 28 07:05:35 PM UTC 24 |
| Finished | Aug 28 07:05:37 PM UTC 24 |
| Peak memory | 198820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118777520 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2118777520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.2235236114 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 38805154 ps |
| CPU time | 0.82 seconds |
| Started | Aug 28 07:05:34 PM UTC 24 |
| Finished | Aug 28 07:05:35 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235236114 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2235236114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/13.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.851719232 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 14150033 ps |
| CPU time | 0.87 seconds |
| Started | Aug 28 07:05:35 PM UTC 24 |
| Finished | Aug 28 07:05:37 PM UTC 24 |
| Peak memory | 198864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851719232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.851719232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.262079618 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 37813820 ps |
| CPU time | 2.64 seconds |
| Started | Aug 28 07:05:33 PM UTC 24 |
| Finished | Aug 28 07:05:37 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262079618 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.262079618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3703725424 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 213516133 ps |
| CPU time | 1.59 seconds |
| Started | Aug 28 07:05:34 PM UTC 24 |
| Finished | Aug 28 07:05:36 PM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703725424 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.3703725424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.870110719 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 22982055 ps |
| CPU time | 1.16 seconds |
| Started | Aug 28 07:05:37 PM UTC 24 |
| Finished | Aug 28 07:05:39 PM UTC 24 |
| Peak memory | 198848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=870110719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_cs r_mem_rw_with_rand_reset.870110719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.3799231848 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 24272098 ps |
| CPU time | 0.88 seconds |
| Started | Aug 28 07:05:37 PM UTC 24 |
| Finished | Aug 28 07:05:39 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799231848 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3799231848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.2573179526 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 38628552 ps |
| CPU time | 0.85 seconds |
| Started | Aug 28 07:05:37 PM UTC 24 |
| Finished | Aug 28 07:05:39 PM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573179526 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2573179526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/14.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1904020545 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 12905129 ps |
| CPU time | 0.88 seconds |
| Started | Aug 28 07:05:37 PM UTC 24 |
| Finished | Aug 28 07:05:39 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904020545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.1904020545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.2014721132 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 197421903 ps |
| CPU time | 3.79 seconds |
| Started | Aug 28 07:05:36 PM UTC 24 |
| Finished | Aug 28 07:05:41 PM UTC 24 |
| Peak memory | 200748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014721132 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2014721132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3124499085 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 437636862 ps |
| CPU time | 1.61 seconds |
| Started | Aug 28 07:05:36 PM UTC 24 |
| Finished | Aug 28 07:05:39 PM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124499085 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.3124499085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3688834433 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 132445473 ps |
| CPU time | 1.39 seconds |
| Started | Aug 28 07:05:39 PM UTC 24 |
| Finished | Aug 28 07:05:42 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3688834433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_c sr_mem_rw_with_rand_reset.3688834433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.4284743786 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 24795792 ps |
| CPU time | 0.84 seconds |
| Started | Aug 28 07:05:38 PM UTC 24 |
| Finished | Aug 28 07:05:40 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284743786 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.4284743786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.2446986832 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 237122491 ps |
| CPU time | 0.87 seconds |
| Started | Aug 28 07:05:38 PM UTC 24 |
| Finished | Aug 28 07:05:40 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446986832 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2446986832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/15.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3757489602 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 81347802 ps |
| CPU time | 0.92 seconds |
| Started | Aug 28 07:05:39 PM UTC 24 |
| Finished | Aug 28 07:05:41 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757489602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.3757489602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.2571971832 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 113198373 ps |
| CPU time | 4.04 seconds |
| Started | Aug 28 07:05:38 PM UTC 24 |
| Finished | Aug 28 07:05:43 PM UTC 24 |
| Peak memory | 200632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571971832 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2571971832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.904004260 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 230760360 ps |
| CPU time | 2.06 seconds |
| Started | Aug 28 07:05:38 PM UTC 24 |
| Finished | Aug 28 07:05:41 PM UTC 24 |
| Peak memory | 200888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904004260 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.904004260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.4130235092 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 69274750 ps |
| CPU time | 1.37 seconds |
| Started | Aug 28 07:05:41 PM UTC 24 |
| Finished | Aug 28 07:05:43 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4130235092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_c sr_mem_rw_with_rand_reset.4130235092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.1254108685 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 32022865 ps |
| CPU time | 0.85 seconds |
| Started | Aug 28 07:05:41 PM UTC 24 |
| Finished | Aug 28 07:05:43 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254108685 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1254108685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.3421120684 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 57698918 ps |
| CPU time | 0.88 seconds |
| Started | Aug 28 07:05:41 PM UTC 24 |
| Finished | Aug 28 07:05:42 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421120684 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3421120684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/16.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1094360164 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 51232900 ps |
| CPU time | 0.9 seconds |
| Started | Aug 28 07:05:41 PM UTC 24 |
| Finished | Aug 28 07:05:43 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094360164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.1094360164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.1719788566 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 200273059 ps |
| CPU time | 3.81 seconds |
| Started | Aug 28 07:05:39 PM UTC 24 |
| Finished | Aug 28 07:05:44 PM UTC 24 |
| Peak memory | 200876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719788566 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1719788566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.555414872 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 38816229 ps |
| CPU time | 2.41 seconds |
| Started | Aug 28 07:05:43 PM UTC 24 |
| Finished | Aug 28 07:05:47 PM UTC 24 |
| Peak memory | 200888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=555414872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_cs r_mem_rw_with_rand_reset.555414872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.1808430035 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 37396429 ps |
| CPU time | 0.83 seconds |
| Started | Aug 28 07:05:43 PM UTC 24 |
| Finished | Aug 28 07:05:45 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808430035 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1808430035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.509519896 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 12984471 ps |
| CPU time | 0.83 seconds |
| Started | Aug 28 07:05:42 PM UTC 24 |
| Finished | Aug 28 07:05:44 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509519896 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.509519896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/17.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2832559149 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 103844077 ps |
| CPU time | 1.2 seconds |
| Started | Aug 28 07:05:43 PM UTC 24 |
| Finished | Aug 28 07:05:45 PM UTC 24 |
| Peak memory | 198784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832559149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.2832559149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.2012703331 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 94580184 ps |
| CPU time | 1.85 seconds |
| Started | Aug 28 07:05:42 PM UTC 24 |
| Finished | Aug 28 07:05:45 PM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012703331 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2012703331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1363892876 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 148524310 ps |
| CPU time | 1.59 seconds |
| Started | Aug 28 07:05:42 PM UTC 24 |
| Finished | Aug 28 07:05:44 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363892876 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.1363892876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2127492438 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 96717070 ps |
| CPU time | 1.75 seconds |
| Started | Aug 28 07:05:45 PM UTC 24 |
| Finished | Aug 28 07:05:48 PM UTC 24 |
| Peak memory | 200956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2127492438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_c sr_mem_rw_with_rand_reset.2127492438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.2616287228 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 23380914 ps |
| CPU time | 0.82 seconds |
| Started | Aug 28 07:05:44 PM UTC 24 |
| Finished | Aug 28 07:05:46 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616287228 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2616287228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.1878815477 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 21760382 ps |
| CPU time | 0.81 seconds |
| Started | Aug 28 07:05:44 PM UTC 24 |
| Finished | Aug 28 07:05:46 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878815477 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1878815477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/18.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1336222218 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 33249321 ps |
| CPU time | 0.88 seconds |
| Started | Aug 28 07:05:44 PM UTC 24 |
| Finished | Aug 28 07:05:46 PM UTC 24 |
| Peak memory | 198848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336222218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.1336222218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.187596504 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 199635796 ps |
| CPU time | 3.06 seconds |
| Started | Aug 28 07:05:43 PM UTC 24 |
| Finished | Aug 28 07:05:47 PM UTC 24 |
| Peak memory | 200600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187596504 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.187596504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3770328926 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 233699728 ps |
| CPU time | 2.13 seconds |
| Started | Aug 28 07:05:44 PM UTC 24 |
| Finished | Aug 28 07:05:47 PM UTC 24 |
| Peak memory | 200760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770328926 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.3770328926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4083769452 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 37884603 ps |
| CPU time | 2.34 seconds |
| Started | Aug 28 07:05:47 PM UTC 24 |
| Finished | Aug 28 07:05:50 PM UTC 24 |
| Peak memory | 203060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4083769452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_c sr_mem_rw_with_rand_reset.4083769452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.227022181 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 17636046 ps |
| CPU time | 0.69 seconds |
| Started | Aug 28 07:05:46 PM UTC 24 |
| Finished | Aug 28 07:05:47 PM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227022181 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.227022181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.2192220277 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 13535729 ps |
| CPU time | 0.82 seconds |
| Started | Aug 28 07:05:46 PM UTC 24 |
| Finished | Aug 28 07:05:47 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192220277 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2192220277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/19.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2702745568 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 21228262 ps |
| CPU time | 1 seconds |
| Started | Aug 28 07:05:47 PM UTC 24 |
| Finished | Aug 28 07:05:49 PM UTC 24 |
| Peak memory | 198848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702745568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.2702745568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.1288919389 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 134313754 ps |
| CPU time | 2.99 seconds |
| Started | Aug 28 07:05:45 PM UTC 24 |
| Finished | Aug 28 07:05:50 PM UTC 24 |
| Peak memory | 200748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288919389 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1288919389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.4244819880 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 118383995 ps |
| CPU time | 1.17 seconds |
| Started | Aug 28 07:05:46 PM UTC 24 |
| Finished | Aug 28 07:05:48 PM UTC 24 |
| Peak memory | 198852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244819880 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.4244819880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2688101208 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 124656755 ps |
| CPU time | 0.94 seconds |
| Started | Aug 28 07:05:01 PM UTC 24 |
| Finished | Aug 28 07:05:03 PM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688101208 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.2688101208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.473757380 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 290096872 ps |
| CPU time | 3.79 seconds |
| Started | Aug 28 07:05:00 PM UTC 24 |
| Finished | Aug 28 07:05:05 PM UTC 24 |
| Peak memory | 200884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473757380 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.473757380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1770008375 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 16026514 ps |
| CPU time | 0.88 seconds |
| Started | Aug 28 07:04:59 PM UTC 24 |
| Finished | Aug 28 07:05:00 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770008375 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.1770008375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3548194776 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 69210549 ps |
| CPU time | 0.94 seconds |
| Started | Aug 28 07:05:02 PM UTC 24 |
| Finished | Aug 28 07:05:04 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3548194776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_cs r_mem_rw_with_rand_reset.3548194776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.3366065604 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 15794895 ps |
| CPU time | 0.87 seconds |
| Started | Aug 28 07:05:00 PM UTC 24 |
| Finished | Aug 28 07:05:02 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366065604 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3366065604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.1806083742 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 43103392 ps |
| CPU time | 0.86 seconds |
| Started | Aug 28 07:04:59 PM UTC 24 |
| Finished | Aug 28 07:05:01 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806083742 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1806083742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2187130973 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 49857222 ps |
| CPU time | 1.11 seconds |
| Started | Aug 28 07:05:01 PM UTC 24 |
| Finished | Aug 28 07:05:03 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187130973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.2187130973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.3308269615 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 83168575 ps |
| CPU time | 1.68 seconds |
| Started | Aug 28 07:04:57 PM UTC 24 |
| Finished | Aug 28 07:04:59 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308269615 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3308269615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3019817760 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 101139209 ps |
| CPU time | 1.41 seconds |
| Started | Aug 28 07:04:59 PM UTC 24 |
| Finished | Aug 28 07:05:01 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019817760 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.3019817760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.36791055 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 20054673 ps |
| CPU time | 0.8 seconds |
| Started | Aug 28 07:05:47 PM UTC 24 |
| Finished | Aug 28 07:05:49 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36791055 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.36791055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/20.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.2323227183 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 40922533 ps |
| CPU time | 0.82 seconds |
| Started | Aug 28 07:05:47 PM UTC 24 |
| Finished | Aug 28 07:05:49 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323227183 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2323227183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/21.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.138271006 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 31024078 ps |
| CPU time | 0.87 seconds |
| Started | Aug 28 07:05:48 PM UTC 24 |
| Finished | Aug 28 07:05:50 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138271006 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.138271006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/22.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.3559902867 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 14612171 ps |
| CPU time | 0.88 seconds |
| Started | Aug 28 07:05:48 PM UTC 24 |
| Finished | Aug 28 07:05:50 PM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559902867 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3559902867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/23.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.620323833 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 37405569 ps |
| CPU time | 0.77 seconds |
| Started | Aug 28 07:05:48 PM UTC 24 |
| Finished | Aug 28 07:05:50 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620323833 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.620323833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/24.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.3979882125 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 11756057 ps |
| CPU time | 0.83 seconds |
| Started | Aug 28 07:05:48 PM UTC 24 |
| Finished | Aug 28 07:05:50 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979882125 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3979882125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/25.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.2402637338 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 29443589 ps |
| CPU time | 0.82 seconds |
| Started | Aug 28 07:05:48 PM UTC 24 |
| Finished | Aug 28 07:05:50 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402637338 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2402637338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/26.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.954819201 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 25367523 ps |
| CPU time | 0.82 seconds |
| Started | Aug 28 07:05:49 PM UTC 24 |
| Finished | Aug 28 07:05:51 PM UTC 24 |
| Peak memory | 198712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954819201 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.954819201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/27.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.631033048 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 47087951 ps |
| CPU time | 0.84 seconds |
| Started | Aug 28 07:05:49 PM UTC 24 |
| Finished | Aug 28 07:05:51 PM UTC 24 |
| Peak memory | 198648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631033048 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.631033048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/28.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.1411881932 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 26151267 ps |
| CPU time | 0.86 seconds |
| Started | Aug 28 07:05:49 PM UTC 24 |
| Finished | Aug 28 07:05:51 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411881932 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1411881932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/29.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.4144525817 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 14415266 ps |
| CPU time | 1.08 seconds |
| Started | Aug 28 07:05:06 PM UTC 24 |
| Finished | Aug 28 07:05:08 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144525817 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.4144525817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1069122593 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 3083907577 ps |
| CPU time | 4.87 seconds |
| Started | Aug 28 07:05:06 PM UTC 24 |
| Finished | Aug 28 07:05:12 PM UTC 24 |
| Peak memory | 200820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069122593 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.1069122593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2395698693 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 36605144 ps |
| CPU time | 0.86 seconds |
| Started | Aug 28 07:05:05 PM UTC 24 |
| Finished | Aug 28 07:05:07 PM UTC 24 |
| Peak memory | 199036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395698693 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.2395698693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3610217438 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 24741025 ps |
| CPU time | 1.54 seconds |
| Started | Aug 28 07:05:07 PM UTC 24 |
| Finished | Aug 28 07:05:10 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3610217438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_cs r_mem_rw_with_rand_reset.3610217438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.1554459695 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 38496998 ps |
| CPU time | 0.83 seconds |
| Started | Aug 28 07:05:05 PM UTC 24 |
| Finished | Aug 28 07:05:07 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554459695 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1554459695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.3216975787 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 24277177 ps |
| CPU time | 0.83 seconds |
| Started | Aug 28 07:05:04 PM UTC 24 |
| Finished | Aug 28 07:05:06 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216975787 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3216975787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2488393668 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 29843400 ps |
| CPU time | 1.01 seconds |
| Started | Aug 28 07:05:07 PM UTC 24 |
| Finished | Aug 28 07:05:09 PM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488393668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.2488393668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.3520390276 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 128529594 ps |
| CPU time | 2.35 seconds |
| Started | Aug 28 07:05:02 PM UTC 24 |
| Finished | Aug 28 07:05:05 PM UTC 24 |
| Peak memory | 200812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520390276 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3520390276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1197893831 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 568358817 ps |
| CPU time | 2.08 seconds |
| Started | Aug 28 07:05:04 PM UTC 24 |
| Finished | Aug 28 07:05:07 PM UTC 24 |
| Peak memory | 200816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197893831 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.1197893831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.906629558 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 14891614 ps |
| CPU time | 0.81 seconds |
| Started | Aug 28 07:05:49 PM UTC 24 |
| Finished | Aug 28 07:05:51 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906629558 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.906629558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/30.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.561622144 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 45223250 ps |
| CPU time | 0.81 seconds |
| Started | Aug 28 07:05:49 PM UTC 24 |
| Finished | Aug 28 07:05:51 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561622144 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.561622144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/31.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.1457463750 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 42640727 ps |
| CPU time | 0.79 seconds |
| Started | Aug 28 07:05:50 PM UTC 24 |
| Finished | Aug 28 07:05:52 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457463750 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1457463750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/32.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.893473373 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 58457856 ps |
| CPU time | 0.83 seconds |
| Started | Aug 28 07:05:50 PM UTC 24 |
| Finished | Aug 28 07:05:52 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893473373 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.893473373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/33.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.890473988 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 29438178 ps |
| CPU time | 0.86 seconds |
| Started | Aug 28 07:05:51 PM UTC 24 |
| Finished | Aug 28 07:05:52 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890473988 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.890473988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/34.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.3954532323 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 50129534 ps |
| CPU time | 0.81 seconds |
| Started | Aug 28 07:05:51 PM UTC 24 |
| Finished | Aug 28 07:05:52 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954532323 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3954532323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/35.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.1111697644 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 26667141 ps |
| CPU time | 0.82 seconds |
| Started | Aug 28 07:05:51 PM UTC 24 |
| Finished | Aug 28 07:05:52 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111697644 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1111697644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/36.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.4217080978 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 17244526 ps |
| CPU time | 0.8 seconds |
| Started | Aug 28 07:05:51 PM UTC 24 |
| Finished | Aug 28 07:05:52 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217080978 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.4217080978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/37.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.2481529062 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 24129051 ps |
| CPU time | 0.81 seconds |
| Started | Aug 28 07:05:51 PM UTC 24 |
| Finished | Aug 28 07:05:52 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481529062 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2481529062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/38.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.3443016793 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 49269764 ps |
| CPU time | 0.84 seconds |
| Started | Aug 28 07:05:52 PM UTC 24 |
| Finished | Aug 28 07:05:54 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443016793 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3443016793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/39.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.96435381 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 17510343 ps |
| CPU time | 0.93 seconds |
| Started | Aug 28 07:05:13 PM UTC 24 |
| Finished | Aug 28 07:05:15 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96435381 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.96435381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.996397593 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 280521794 ps |
| CPU time | 4.81 seconds |
| Started | Aug 28 07:05:13 PM UTC 24 |
| Finished | Aug 28 07:05:19 PM UTC 24 |
| Peak memory | 200360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996397593 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.996397593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.192719662 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 15684078 ps |
| CPU time | 0.86 seconds |
| Started | Aug 28 07:05:11 PM UTC 24 |
| Finished | Aug 28 07:05:13 PM UTC 24 |
| Peak memory | 198872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192719662 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.192719662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.4019457827 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 29658295 ps |
| CPU time | 1.59 seconds |
| Started | Aug 28 07:05:14 PM UTC 24 |
| Finished | Aug 28 07:05:17 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4019457827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_cs r_mem_rw_with_rand_reset.4019457827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.1958209388 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 13111768 ps |
| CPU time | 0.85 seconds |
| Started | Aug 28 07:05:12 PM UTC 24 |
| Finished | Aug 28 07:05:14 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958209388 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1958209388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.1344998070 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 59993964 ps |
| CPU time | 0.85 seconds |
| Started | Aug 28 07:05:11 PM UTC 24 |
| Finished | Aug 28 07:05:13 PM UTC 24 |
| Peak memory | 198856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344998070 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1344998070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.681216413 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 37470756 ps |
| CPU time | 1.24 seconds |
| Started | Aug 28 07:05:14 PM UTC 24 |
| Finished | Aug 28 07:05:16 PM UTC 24 |
| Peak memory | 199064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681216413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.681216413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.1493610786 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 335953321 ps |
| CPU time | 2.86 seconds |
| Started | Aug 28 07:05:08 PM UTC 24 |
| Finished | Aug 28 07:05:12 PM UTC 24 |
| Peak memory | 200676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493610786 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1493610786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3755690622 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 166481049 ps |
| CPU time | 2.1 seconds |
| Started | Aug 28 07:05:10 PM UTC 24 |
| Finished | Aug 28 07:05:13 PM UTC 24 |
| Peak memory | 200684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755690622 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.3755690622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.3359880498 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 18906046 ps |
| CPU time | 0.85 seconds |
| Started | Aug 28 07:05:52 PM UTC 24 |
| Finished | Aug 28 07:05:54 PM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359880498 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3359880498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/40.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.222190227 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 112166929 ps |
| CPU time | 0.79 seconds |
| Started | Aug 28 07:05:52 PM UTC 24 |
| Finished | Aug 28 07:05:54 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222190227 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.222190227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/41.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.3801904999 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 22989608 ps |
| CPU time | 0.83 seconds |
| Started | Aug 28 07:05:52 PM UTC 24 |
| Finished | Aug 28 07:05:54 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801904999 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3801904999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/42.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.2632815265 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 34760940 ps |
| CPU time | 0.86 seconds |
| Started | Aug 28 07:05:52 PM UTC 24 |
| Finished | Aug 28 07:05:54 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632815265 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2632815265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/43.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.4252936571 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 14743386 ps |
| CPU time | 0.86 seconds |
| Started | Aug 28 07:05:53 PM UTC 24 |
| Finished | Aug 28 07:05:55 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252936571 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.4252936571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/44.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.2046418216 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 14707604 ps |
| CPU time | 0.84 seconds |
| Started | Aug 28 07:05:53 PM UTC 24 |
| Finished | Aug 28 07:05:55 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046418216 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2046418216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/45.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.1661579052 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 12346689 ps |
| CPU time | 0.75 seconds |
| Started | Aug 28 07:05:53 PM UTC 24 |
| Finished | Aug 28 07:05:55 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661579052 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1661579052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/46.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.3856769999 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 124425063 ps |
| CPU time | 0.83 seconds |
| Started | Aug 28 07:05:53 PM UTC 24 |
| Finished | Aug 28 07:05:55 PM UTC 24 |
| Peak memory | 198892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856769999 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3856769999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/47.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.1393314100 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 15205044 ps |
| CPU time | 0.83 seconds |
| Started | Aug 28 07:05:53 PM UTC 24 |
| Finished | Aug 28 07:05:55 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393314100 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1393314100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/48.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.2696353595 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 48677388 ps |
| CPU time | 0.81 seconds |
| Started | Aug 28 07:05:53 PM UTC 24 |
| Finished | Aug 28 07:05:55 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696353595 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2696353595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/49.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2668447822 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 113925337 ps |
| CPU time | 1.42 seconds |
| Started | Aug 28 07:05:16 PM UTC 24 |
| Finished | Aug 28 07:05:19 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2668447822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_cs r_mem_rw_with_rand_reset.2668447822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.3017957234 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 46983773 ps |
| CPU time | 0.76 seconds |
| Started | Aug 28 07:05:15 PM UTC 24 |
| Finished | Aug 28 07:05:17 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017957234 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3017957234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.2309205633 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 30792428 ps |
| CPU time | 0.78 seconds |
| Started | Aug 28 07:05:14 PM UTC 24 |
| Finished | Aug 28 07:05:16 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309205633 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2309205633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/5.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.851564480 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 88893022 ps |
| CPU time | 0.89 seconds |
| Started | Aug 28 07:05:15 PM UTC 24 |
| Finished | Aug 28 07:05:17 PM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851564480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.851564480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.3832186221 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 35858990 ps |
| CPU time | 1.27 seconds |
| Started | Aug 28 07:05:14 PM UTC 24 |
| Finished | Aug 28 07:05:16 PM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832186221 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3832186221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3350376889 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 351605637 ps |
| CPU time | 1.76 seconds |
| Started | Aug 28 07:05:14 PM UTC 24 |
| Finished | Aug 28 07:05:17 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350376889 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.3350376889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.149376891 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 304537112 ps |
| CPU time | 1.06 seconds |
| Started | Aug 28 07:05:19 PM UTC 24 |
| Finished | Aug 28 07:05:21 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=149376891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr _mem_rw_with_rand_reset.149376891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.2298034719 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 15032019 ps |
| CPU time | 0.77 seconds |
| Started | Aug 28 07:05:17 PM UTC 24 |
| Finished | Aug 28 07:05:19 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298034719 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2298034719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.946760392 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 13573243 ps |
| CPU time | 0.79 seconds |
| Started | Aug 28 07:05:17 PM UTC 24 |
| Finished | Aug 28 07:05:19 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946760392 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.946760392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/6.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3304811282 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 36494551 ps |
| CPU time | 1.13 seconds |
| Started | Aug 28 07:05:17 PM UTC 24 |
| Finished | Aug 28 07:05:20 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304811282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.3304811282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.2427929346 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 634492266 ps |
| CPU time | 2.62 seconds |
| Started | Aug 28 07:05:17 PM UTC 24 |
| Finished | Aug 28 07:05:21 PM UTC 24 |
| Peak memory | 200676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427929346 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2427929346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3918512173 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 122226147 ps |
| CPU time | 1.46 seconds |
| Started | Aug 28 07:05:17 PM UTC 24 |
| Finished | Aug 28 07:05:20 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918512173 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.3918512173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1928440408 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 113295409 ps |
| CPU time | 2.13 seconds |
| Started | Aug 28 07:05:21 PM UTC 24 |
| Finished | Aug 28 07:05:24 PM UTC 24 |
| Peak memory | 200808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1928440408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_cs r_mem_rw_with_rand_reset.1928440408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.2734816364 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 47886635 ps |
| CPU time | 0.87 seconds |
| Started | Aug 28 07:05:20 PM UTC 24 |
| Finished | Aug 28 07:05:22 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734816364 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2734816364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.3120519073 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 13432168 ps |
| CPU time | 0.85 seconds |
| Started | Aug 28 07:05:20 PM UTC 24 |
| Finished | Aug 28 07:05:22 PM UTC 24 |
| Peak memory | 198740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120519073 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3120519073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/7.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3685707838 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 16548503 ps |
| CPU time | 0.97 seconds |
| Started | Aug 28 07:05:21 PM UTC 24 |
| Finished | Aug 28 07:05:23 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685707838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.3685707838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.1873869238 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 43960192 ps |
| CPU time | 1.47 seconds |
| Started | Aug 28 07:05:20 PM UTC 24 |
| Finished | Aug 28 07:05:22 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873869238 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1873869238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.4165184185 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 73530985 ps |
| CPU time | 1.67 seconds |
| Started | Aug 28 07:05:20 PM UTC 24 |
| Finished | Aug 28 07:05:22 PM UTC 24 |
| Peak memory | 198740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165184185 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.4165184185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3601798326 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 117848512 ps |
| CPU time | 1.28 seconds |
| Started | Aug 28 07:05:23 PM UTC 24 |
| Finished | Aug 28 07:05:25 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3601798326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_cs r_mem_rw_with_rand_reset.3601798326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.722723623 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 169049547 ps |
| CPU time | 0.89 seconds |
| Started | Aug 28 07:05:23 PM UTC 24 |
| Finished | Aug 28 07:05:25 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722723623 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.722723623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.755868617 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 18026867 ps |
| CPU time | 0.85 seconds |
| Started | Aug 28 07:05:22 PM UTC 24 |
| Finished | Aug 28 07:05:24 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755868617 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.755868617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/8.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2133053230 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 35474067 ps |
| CPU time | 1.18 seconds |
| Started | Aug 28 07:05:23 PM UTC 24 |
| Finished | Aug 28 07:05:25 PM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133053230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.2133053230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.3957094625 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 22449154 ps |
| CPU time | 1.57 seconds |
| Started | Aug 28 07:05:22 PM UTC 24 |
| Finished | Aug 28 07:05:24 PM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957094625 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3957094625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1967755079 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 130604709 ps |
| CPU time | 2.22 seconds |
| Started | Aug 28 07:05:22 PM UTC 24 |
| Finished | Aug 28 07:05:25 PM UTC 24 |
| Peak memory | 200948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967755079 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.1967755079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2820278240 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 73075663 ps |
| CPU time | 1.27 seconds |
| Started | Aug 28 07:05:27 PM UTC 24 |
| Finished | Aug 28 07:05:29 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2820278240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_cs r_mem_rw_with_rand_reset.2820278240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.1148329806 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 35078760 ps |
| CPU time | 0.87 seconds |
| Started | Aug 28 07:05:25 PM UTC 24 |
| Finished | Aug 28 07:05:27 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148329806 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1148329806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.3178434764 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 13494494 ps |
| CPU time | 0.82 seconds |
| Started | Aug 28 07:05:25 PM UTC 24 |
| Finished | Aug 28 07:05:27 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178434764 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3178434764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/9.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2068598616 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 106505689 ps |
| CPU time | 1.13 seconds |
| Started | Aug 28 07:05:25 PM UTC 24 |
| Finished | Aug 28 07:05:28 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068598616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.2068598616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.304511966 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 28526456 ps |
| CPU time | 1.96 seconds |
| Started | Aug 28 07:05:24 PM UTC 24 |
| Finished | Aug 28 07:05:27 PM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304511966 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.304511966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3225993108 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 386221854 ps |
| CPU time | 1.57 seconds |
| Started | Aug 28 07:05:24 PM UTC 24 |
| Finished | Aug 28 07:05:27 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225993108 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.3225993108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.4129245534 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 135049649757 ps |
| CPU time | 77.49 seconds |
| Started | Aug 28 06:21:06 PM UTC 24 |
| Finished | Aug 28 06:22:26 PM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129245534 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.4129245534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.2338743703 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 179425245473 ps |
| CPU time | 219.49 seconds |
| Started | Aug 28 06:21:06 PM UTC 24 |
| Finished | Aug 28 06:24:49 PM UTC 24 |
| Peak memory | 202520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338743703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2338743703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.46870127 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 101427587 ps |
| CPU time | 1.12 seconds |
| Started | Aug 28 06:21:06 PM UTC 24 |
| Finished | Aug 28 06:21:08 PM UTC 24 |
| Peak memory | 199116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46870127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.46870127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all_with_rand_reset.2386798485 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 10392229479 ps |
| CPU time | 50.2 seconds |
| Started | Aug 28 06:21:06 PM UTC 24 |
| Finished | Aug 28 06:21:58 PM UTC 24 |
| Peak memory | 203832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2386798485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.rv_timer_stress_all_with_rand_reset.2386798485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.2241315853 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 57793024521 ps |
| CPU time | 135.89 seconds |
| Started | Aug 28 06:21:06 PM UTC 24 |
| Finished | Aug 28 06:23:25 PM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241315853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2241315853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.3398310565 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 181011969517 ps |
| CPU time | 127.84 seconds |
| Started | Aug 28 06:21:06 PM UTC 24 |
| Finished | Aug 28 06:23:17 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398310565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3398310565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.952371573 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 78490589 ps |
| CPU time | 1.01 seconds |
| Started | Aug 28 06:21:07 PM UTC 24 |
| Finished | Aug 28 06:21:09 PM UTC 24 |
| Peak memory | 230952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952371573 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.952371573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.2229297584 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 26026002311 ps |
| CPU time | 12.37 seconds |
| Started | Aug 28 06:21:15 PM UTC 24 |
| Finished | Aug 28 06:21:29 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229297584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2229297584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/10.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.1590609284 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 158794314 ps |
| CPU time | 0.95 seconds |
| Started | Aug 28 06:21:15 PM UTC 24 |
| Finished | Aug 28 06:21:17 PM UTC 24 |
| Peak memory | 198936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590609284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1590609284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/10.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.4058151353 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 133813638928 ps |
| CPU time | 52.2 seconds |
| Started | Aug 28 06:49:45 PM UTC 24 |
| Finished | Aug 28 06:50:39 PM UTC 24 |
| Peak memory | 199456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058151353 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.4058151353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/100.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.1843190275 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 33833624692 ps |
| CPU time | 370.86 seconds |
| Started | Aug 28 06:50:40 PM UTC 24 |
| Finished | Aug 28 06:56:56 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843190275 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1843190275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/104.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.3589600043 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 203329614171 ps |
| CPU time | 967.85 seconds |
| Started | Aug 28 06:50:44 PM UTC 24 |
| Finished | Aug 28 07:07:05 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589600043 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3589600043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/106.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.1966961740 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 44208989035 ps |
| CPU time | 94.58 seconds |
| Started | Aug 28 06:21:17 PM UTC 24 |
| Finished | Aug 28 06:22:53 PM UTC 24 |
| Peak memory | 199748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966961740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1966961740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/11.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.3055502101 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 162842139210 ps |
| CPU time | 180.54 seconds |
| Started | Aug 28 06:51:34 PM UTC 24 |
| Finished | Aug 28 06:54:38 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055502101 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3055502101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/110.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.3524988562 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 316668767512 ps |
| CPU time | 545.84 seconds |
| Started | Aug 28 06:52:16 PM UTC 24 |
| Finished | Aug 28 07:01:33 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524988562 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3524988562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/114.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.990678694 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 28012969688 ps |
| CPU time | 107.81 seconds |
| Started | Aug 28 06:53:35 PM UTC 24 |
| Finished | Aug 28 06:55:26 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990678694 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.990678694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/119.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.3374557349 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 143157959836 ps |
| CPU time | 287.74 seconds |
| Started | Aug 28 06:21:23 PM UTC 24 |
| Finished | Aug 28 06:26:14 PM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374557349 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.3374557349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.425922829 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 463803662811 ps |
| CPU time | 169.72 seconds |
| Started | Aug 28 06:21:21 PM UTC 24 |
| Finished | Aug 28 06:24:14 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425922829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.425922829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/12.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.3752868028 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 192429006568 ps |
| CPU time | 716.48 seconds |
| Started | Aug 28 06:21:19 PM UTC 24 |
| Finished | Aug 28 06:33:25 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752868028 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3752868028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/12.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.2267394018 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 4354716049 ps |
| CPU time | 11.67 seconds |
| Started | Aug 28 06:21:23 PM UTC 24 |
| Finished | Aug 28 06:21:35 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267394018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2267394018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/12.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.1596894989 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 108276554116 ps |
| CPU time | 138.76 seconds |
| Started | Aug 28 06:53:42 PM UTC 24 |
| Finished | Aug 28 06:56:04 PM UTC 24 |
| Peak memory | 199608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596894989 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1596894989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/121.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.1353368290 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 450903254414 ps |
| CPU time | 292.9 seconds |
| Started | Aug 28 06:53:53 PM UTC 24 |
| Finished | Aug 28 06:58:51 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353368290 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1353368290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/122.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.1825514476 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 8643857834 ps |
| CPU time | 15.08 seconds |
| Started | Aug 28 06:53:57 PM UTC 24 |
| Finished | Aug 28 06:54:14 PM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825514476 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1825514476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/123.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.3778696182 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 363394058121 ps |
| CPU time | 509.71 seconds |
| Started | Aug 28 06:54:27 PM UTC 24 |
| Finished | Aug 28 07:03:06 PM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778696182 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3778696182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/125.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.1079637750 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 179035538467 ps |
| CPU time | 265.47 seconds |
| Started | Aug 28 06:54:39 PM UTC 24 |
| Finished | Aug 28 06:59:09 PM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079637750 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1079637750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/126.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.1394310242 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 97995045405 ps |
| CPU time | 687.77 seconds |
| Started | Aug 28 06:54:42 PM UTC 24 |
| Finished | Aug 28 07:06:19 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394310242 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1394310242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/127.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.3421162181 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 121142020722 ps |
| CPU time | 67.41 seconds |
| Started | Aug 28 06:21:25 PM UTC 24 |
| Finished | Aug 28 06:22:34 PM UTC 24 |
| Peak memory | 199512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421162181 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.3421162181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.1140303907 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 48419525227 ps |
| CPU time | 64.99 seconds |
| Started | Aug 28 06:21:25 PM UTC 24 |
| Finished | Aug 28 06:22:31 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140303907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1140303907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/13.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.4191525352 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 794835440 ps |
| CPU time | 2.91 seconds |
| Started | Aug 28 06:21:25 PM UTC 24 |
| Finished | Aug 28 06:21:29 PM UTC 24 |
| Peak memory | 199392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191525352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.4191525352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/13.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.3714396925 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 441262066731 ps |
| CPU time | 184.49 seconds |
| Started | Aug 28 06:55:01 PM UTC 24 |
| Finished | Aug 28 06:58:09 PM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714396925 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3714396925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/130.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.1483600223 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 85381888789 ps |
| CPU time | 345.03 seconds |
| Started | Aug 28 06:55:10 PM UTC 24 |
| Finished | Aug 28 07:01:01 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483600223 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1483600223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/131.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.345074196 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 138193623233 ps |
| CPU time | 373.12 seconds |
| Started | Aug 28 06:55:26 PM UTC 24 |
| Finished | Aug 28 07:01:45 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345074196 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.345074196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/132.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.1501314461 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 63829800268 ps |
| CPU time | 166.98 seconds |
| Started | Aug 28 06:55:46 PM UTC 24 |
| Finished | Aug 28 06:58:37 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501314461 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1501314461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/133.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.168346674 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 208422722437 ps |
| CPU time | 159.82 seconds |
| Started | Aug 28 06:55:54 PM UTC 24 |
| Finished | Aug 28 06:58:37 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168346674 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.168346674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/134.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.3926899318 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 176026990134 ps |
| CPU time | 548.16 seconds |
| Started | Aug 28 06:55:57 PM UTC 24 |
| Finished | Aug 28 07:05:13 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926899318 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3926899318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/135.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.3705334897 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 467841180453 ps |
| CPU time | 580.52 seconds |
| Started | Aug 28 06:56:05 PM UTC 24 |
| Finished | Aug 28 07:05:54 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705334897 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3705334897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/136.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.1636184376 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 472747109551 ps |
| CPU time | 417.27 seconds |
| Started | Aug 28 06:56:22 PM UTC 24 |
| Finished | Aug 28 07:03:26 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636184376 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1636184376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/137.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.3561207352 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 86187329326 ps |
| CPU time | 144.51 seconds |
| Started | Aug 28 06:21:32 PM UTC 24 |
| Finished | Aug 28 06:23:59 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561207352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3561207352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/14.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.1945732779 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 27449646609 ps |
| CPU time | 44.78 seconds |
| Started | Aug 28 06:21:30 PM UTC 24 |
| Finished | Aug 28 06:22:16 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945732779 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1945732779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/14.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.4043344887 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 355835589926 ps |
| CPU time | 1647.35 seconds |
| Started | Aug 28 06:21:36 PM UTC 24 |
| Finished | Aug 28 06:49:29 PM UTC 24 |
| Peak memory | 202548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043344887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4043344887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/14.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.341306026 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 2565688535674 ps |
| CPU time | 654.36 seconds |
| Started | Aug 28 06:21:38 PM UTC 24 |
| Finished | Aug 28 06:32:41 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341306026 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.341306026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/14.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.2174915472 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 594442639375 ps |
| CPU time | 767.22 seconds |
| Started | Aug 28 06:57:00 PM UTC 24 |
| Finished | Aug 28 07:09:58 PM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174915472 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2174915472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/142.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.1876348682 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 154569846726 ps |
| CPU time | 125.97 seconds |
| Started | Aug 28 06:57:29 PM UTC 24 |
| Finished | Aug 28 06:59:38 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876348682 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1876348682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/143.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.401970670 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 4914686495 ps |
| CPU time | 6.72 seconds |
| Started | Aug 28 06:57:39 PM UTC 24 |
| Finished | Aug 28 06:57:47 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401970670 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.401970670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/144.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.4277871172 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 934424432972 ps |
| CPU time | 1272.4 seconds |
| Started | Aug 28 06:57:57 PM UTC 24 |
| Finished | Aug 28 07:19:28 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277871172 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.4277871172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/146.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.1094684714 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 277214765842 ps |
| CPU time | 356.74 seconds |
| Started | Aug 28 06:58:09 PM UTC 24 |
| Finished | Aug 28 07:04:11 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094684714 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1094684714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/147.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.2061534352 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 91869350145 ps |
| CPU time | 375.74 seconds |
| Started | Aug 28 06:58:19 PM UTC 24 |
| Finished | Aug 28 07:04:41 PM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061534352 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2061534352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/148.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.4153871528 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 126595381760 ps |
| CPU time | 280.8 seconds |
| Started | Aug 28 06:58:24 PM UTC 24 |
| Finished | Aug 28 07:03:10 PM UTC 24 |
| Peak memory | 199868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153871528 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.4153871528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/149.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.3216807392 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 88438848036 ps |
| CPU time | 64.88 seconds |
| Started | Aug 28 06:21:47 PM UTC 24 |
| Finished | Aug 28 06:22:54 PM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216807392 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.3216807392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.1184190636 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 120337287982 ps |
| CPU time | 177.91 seconds |
| Started | Aug 28 06:21:46 PM UTC 24 |
| Finished | Aug 28 06:24:47 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184190636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1184190636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/15.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.514516745 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 52687265441 ps |
| CPU time | 99.74 seconds |
| Started | Aug 28 06:21:44 PM UTC 24 |
| Finished | Aug 28 06:23:26 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514516745 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.514516745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/15.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.2002350797 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 551865273415 ps |
| CPU time | 380.76 seconds |
| Started | Aug 28 06:21:49 PM UTC 24 |
| Finished | Aug 28 06:28:16 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002350797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2002350797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/15.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.60871341 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 55831170877 ps |
| CPU time | 44.96 seconds |
| Started | Aug 28 06:58:39 PM UTC 24 |
| Finished | Aug 28 06:59:25 PM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60871341 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.60871341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/151.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.1591759588 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 570353439552 ps |
| CPU time | 1012.11 seconds |
| Started | Aug 28 06:58:43 PM UTC 24 |
| Finished | Aug 28 07:15:50 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591759588 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1591759588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/153.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.3603788357 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 65486058929 ps |
| CPU time | 51.54 seconds |
| Started | Aug 28 06:58:46 PM UTC 24 |
| Finished | Aug 28 06:59:39 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603788357 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3603788357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/154.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.1527300179 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 262696354609 ps |
| CPU time | 349.91 seconds |
| Started | Aug 28 06:58:52 PM UTC 24 |
| Finished | Aug 28 07:04:47 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527300179 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1527300179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/155.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.1572539041 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 788533855221 ps |
| CPU time | 549.26 seconds |
| Started | Aug 28 06:58:53 PM UTC 24 |
| Finished | Aug 28 07:08:11 PM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572539041 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1572539041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/156.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.1561687741 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 957989450924 ps |
| CPU time | 427.56 seconds |
| Started | Aug 28 06:22:33 PM UTC 24 |
| Finished | Aug 28 06:29:46 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561687741 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.1561687741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.2544169058 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 911690172355 ps |
| CPU time | 197.13 seconds |
| Started | Aug 28 06:22:26 PM UTC 24 |
| Finished | Aug 28 06:25:47 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544169058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2544169058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/16.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.241458224 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 38863298475 ps |
| CPU time | 89.28 seconds |
| Started | Aug 28 06:22:17 PM UTC 24 |
| Finished | Aug 28 06:23:49 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241458224 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.241458224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/16.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.2244603705 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 30385851550 ps |
| CPU time | 26.44 seconds |
| Started | Aug 28 06:22:34 PM UTC 24 |
| Finished | Aug 28 06:23:01 PM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244603705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2244603705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/16.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.403395146 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1232863003278 ps |
| CPU time | 676.2 seconds |
| Started | Aug 28 06:22:48 PM UTC 24 |
| Finished | Aug 28 06:34:15 PM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403395146 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.403395146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/16.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.801009891 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 75173767378 ps |
| CPU time | 150.47 seconds |
| Started | Aug 28 06:59:36 PM UTC 24 |
| Finished | Aug 28 07:02:09 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801009891 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.801009891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/161.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.2359238701 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 616432116273 ps |
| CPU time | 624.34 seconds |
| Started | Aug 28 06:59:38 PM UTC 24 |
| Finished | Aug 28 07:10:12 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359238701 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2359238701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/162.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.2705852231 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 125652108483 ps |
| CPU time | 295.38 seconds |
| Started | Aug 28 07:00:45 PM UTC 24 |
| Finished | Aug 28 07:05:45 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705852231 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2705852231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/166.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.112092454 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 79986364765 ps |
| CPU time | 55.94 seconds |
| Started | Aug 28 07:01:03 PM UTC 24 |
| Finished | Aug 28 07:02:01 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112092454 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.112092454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/168.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.70874830 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 128677118957 ps |
| CPU time | 91.88 seconds |
| Started | Aug 28 07:01:13 PM UTC 24 |
| Finished | Aug 28 07:02:47 PM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70874830 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.70874830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/169.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.2478881681 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 253469968696 ps |
| CPU time | 620.45 seconds |
| Started | Aug 28 06:22:54 PM UTC 24 |
| Finished | Aug 28 06:33:22 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478881681 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.2478881681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.3587405631 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 227485484220 ps |
| CPU time | 493.96 seconds |
| Started | Aug 28 06:22:54 PM UTC 24 |
| Finished | Aug 28 06:31:15 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587405631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3587405631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/17.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.1786689464 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 193206216325 ps |
| CPU time | 157.15 seconds |
| Started | Aug 28 06:22:52 PM UTC 24 |
| Finished | Aug 28 06:25:32 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786689464 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1786689464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/17.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all_with_rand_reset.1432998786 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 6822741132 ps |
| CPU time | 75.15 seconds |
| Started | Aug 28 06:23:02 PM UTC 24 |
| Finished | Aug 28 06:24:19 PM UTC 24 |
| Peak memory | 204024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1432998786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 17.rv_timer_stress_all_with_rand_reset.1432998786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/17.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.3135787826 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 78284726315 ps |
| CPU time | 383.81 seconds |
| Started | Aug 28 07:01:13 PM UTC 24 |
| Finished | Aug 28 07:07:44 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135787826 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3135787826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/170.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.1683697192 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 13605438169 ps |
| CPU time | 23.6 seconds |
| Started | Aug 28 07:01:19 PM UTC 24 |
| Finished | Aug 28 07:01:44 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683697192 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1683697192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/171.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.1850704297 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 62240052452 ps |
| CPU time | 101.74 seconds |
| Started | Aug 28 07:01:33 PM UTC 24 |
| Finished | Aug 28 07:03:18 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850704297 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1850704297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/172.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.228118121 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 1752083427200 ps |
| CPU time | 788.5 seconds |
| Started | Aug 28 07:01:54 PM UTC 24 |
| Finished | Aug 28 07:15:13 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228118121 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.228118121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/175.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.3197805004 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 34048395074 ps |
| CPU time | 50.68 seconds |
| Started | Aug 28 07:02:16 PM UTC 24 |
| Finished | Aug 28 07:03:08 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197805004 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3197805004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/178.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.3740333024 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 1586632016039 ps |
| CPU time | 1130.93 seconds |
| Started | Aug 28 06:23:27 PM UTC 24 |
| Finished | Aug 28 06:42:32 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740333024 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.3740333024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/18.rv_timer_disabled.4293174696 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 171764958681 ps |
| CPU time | 301.27 seconds |
| Started | Aug 28 06:23:26 PM UTC 24 |
| Finished | Aug 28 06:28:31 PM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293174696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.4293174696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/18.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.3392846453 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 916164169744 ps |
| CPU time | 2437.56 seconds |
| Started | Aug 28 06:23:25 PM UTC 24 |
| Finished | Aug 28 07:04:34 PM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392846453 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3392846453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/18.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.234748156 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 108152299335 ps |
| CPU time | 634.06 seconds |
| Started | Aug 28 06:23:43 PM UTC 24 |
| Finished | Aug 28 06:34:27 PM UTC 24 |
| Peak memory | 199912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234748156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.234748156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/18.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.3501367666 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 419090461292 ps |
| CPU time | 863.72 seconds |
| Started | Aug 28 06:23:46 PM UTC 24 |
| Finished | Aug 28 06:38:21 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501367666 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.3501367666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/18.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.742238981 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 57087209905 ps |
| CPU time | 200.19 seconds |
| Started | Aug 28 07:02:48 PM UTC 24 |
| Finished | Aug 28 07:06:12 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742238981 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.742238981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/181.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.74479208 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 746278085079 ps |
| CPU time | 566.38 seconds |
| Started | Aug 28 07:03:03 PM UTC 24 |
| Finished | Aug 28 07:12:38 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74479208 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.74479208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/183.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.2690987138 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 142106914005 ps |
| CPU time | 248.32 seconds |
| Started | Aug 28 07:03:06 PM UTC 24 |
| Finished | Aug 28 07:07:19 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690987138 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2690987138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/184.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.928207365 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 100010317122 ps |
| CPU time | 1710.69 seconds |
| Started | Aug 28 07:03:19 PM UTC 24 |
| Finished | Aug 28 07:32:12 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928207365 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.928207365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/188.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.2802178929 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 33683361473 ps |
| CPU time | 82.67 seconds |
| Started | Aug 28 07:03:21 PM UTC 24 |
| Finished | Aug 28 07:04:46 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802178929 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2802178929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/189.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.3306841417 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1712597520840 ps |
| CPU time | 1089.34 seconds |
| Started | Aug 28 06:23:58 PM UTC 24 |
| Finished | Aug 28 06:42:22 PM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306841417 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.3306841417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.3847089718 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 25225686534 ps |
| CPU time | 63.21 seconds |
| Started | Aug 28 06:23:57 PM UTC 24 |
| Finished | Aug 28 06:25:02 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847089718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3847089718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/19.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.3578692203 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 156899644647 ps |
| CPU time | 64.17 seconds |
| Started | Aug 28 06:23:50 PM UTC 24 |
| Finished | Aug 28 06:24:56 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578692203 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3578692203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/19.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.1115327406 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 96618328665 ps |
| CPU time | 164.55 seconds |
| Started | Aug 28 06:24:00 PM UTC 24 |
| Finished | Aug 28 06:26:47 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115327406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1115327406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/19.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.3805004099 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 555530351359 ps |
| CPU time | 1536.28 seconds |
| Started | Aug 28 06:24:20 PM UTC 24 |
| Finished | Aug 28 06:50:16 PM UTC 24 |
| Peak memory | 202356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805004099 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.3805004099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/19.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all_with_rand_reset.4131638898 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2245893722 ps |
| CPU time | 37.62 seconds |
| Started | Aug 28 06:24:14 PM UTC 24 |
| Finished | Aug 28 06:24:53 PM UTC 24 |
| Peak memory | 203964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4131638898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.rv_timer_stress_all_with_rand_reset.4131638898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/19.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.3973344931 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 694057203985 ps |
| CPU time | 2663.99 seconds |
| Started | Aug 28 07:03:27 PM UTC 24 |
| Finished | Aug 28 07:48:29 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973344931 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3973344931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/190.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.1796413352 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 360972507741 ps |
| CPU time | 2025.37 seconds |
| Started | Aug 28 07:03:31 PM UTC 24 |
| Finished | Aug 28 07:37:44 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796413352 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1796413352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/191.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.1739190803 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 334569723568 ps |
| CPU time | 305.82 seconds |
| Started | Aug 28 07:03:42 PM UTC 24 |
| Finished | Aug 28 07:08:53 PM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739190803 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1739190803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/192.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.4192090126 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 89679922206 ps |
| CPU time | 104.79 seconds |
| Started | Aug 28 07:03:52 PM UTC 24 |
| Finished | Aug 28 07:05:39 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192090126 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.4192090126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/193.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.3545752081 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 100757527620 ps |
| CPU time | 237.51 seconds |
| Started | Aug 28 07:04:00 PM UTC 24 |
| Finished | Aug 28 07:08:02 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545752081 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3545752081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/194.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.3434852386 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 195807805758 ps |
| CPU time | 364.75 seconds |
| Started | Aug 28 07:04:12 PM UTC 24 |
| Finished | Aug 28 07:10:23 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434852386 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3434852386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/195.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.1533416660 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 74174421595 ps |
| CPU time | 47.69 seconds |
| Started | Aug 28 07:04:24 PM UTC 24 |
| Finished | Aug 28 07:05:14 PM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533416660 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1533416660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/197.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.1977839937 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 55658974797 ps |
| CPU time | 595.49 seconds |
| Started | Aug 28 07:04:25 PM UTC 24 |
| Finished | Aug 28 07:14:30 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977839937 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1977839937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/198.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.3736964574 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 102741790609 ps |
| CPU time | 253.1 seconds |
| Started | Aug 28 07:04:35 PM UTC 24 |
| Finished | Aug 28 07:08:54 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736964574 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3736964574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/199.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.2769293655 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 93971782398 ps |
| CPU time | 203.66 seconds |
| Started | Aug 28 06:21:07 PM UTC 24 |
| Finished | Aug 28 06:24:33 PM UTC 24 |
| Peak memory | 199580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769293655 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.2769293655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.2356153468 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 433526684665 ps |
| CPU time | 284.58 seconds |
| Started | Aug 28 06:21:07 PM UTC 24 |
| Finished | Aug 28 06:25:55 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356153468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2356153468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.3417422156 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 75232983 ps |
| CPU time | 0.61 seconds |
| Started | Aug 28 06:21:07 PM UTC 24 |
| Finished | Aug 28 06:21:08 PM UTC 24 |
| Peak memory | 198944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417422156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3417422156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.3963445826 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 266582665 ps |
| CPU time | 0.93 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:21:11 PM UTC 24 |
| Peak memory | 230928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963445826 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3963445826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all_with_rand_reset.67833265 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 18520402921 ps |
| CPU time | 38.96 seconds |
| Started | Aug 28 06:21:08 PM UTC 24 |
| Finished | Aug 28 06:21:48 PM UTC 24 |
| Peak memory | 203896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=67833265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.67833265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.3227619955 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 156634300284 ps |
| CPU time | 150.58 seconds |
| Started | Aug 28 06:24:47 PM UTC 24 |
| Finished | Aug 28 06:27:21 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227619955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3227619955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/20.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.1332259314 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 978910434682 ps |
| CPU time | 811.05 seconds |
| Started | Aug 28 06:24:34 PM UTC 24 |
| Finished | Aug 28 06:38:17 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332259314 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1332259314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/20.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.2017032216 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 179819403679 ps |
| CPU time | 1324.76 seconds |
| Started | Aug 28 06:24:54 PM UTC 24 |
| Finished | Aug 28 06:47:16 PM UTC 24 |
| Peak memory | 202424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017032216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2017032216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/20.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.715578329 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 381500051745 ps |
| CPU time | 1046.57 seconds |
| Started | Aug 28 06:25:33 PM UTC 24 |
| Finished | Aug 28 06:43:12 PM UTC 24 |
| Peak memory | 199688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715578329 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.715578329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.2539070881 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 197635229081 ps |
| CPU time | 380.56 seconds |
| Started | Aug 28 06:25:03 PM UTC 24 |
| Finished | Aug 28 06:31:29 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539070881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2539070881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/21.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.246806754 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 38414497952 ps |
| CPU time | 126.64 seconds |
| Started | Aug 28 06:25:02 PM UTC 24 |
| Finished | Aug 28 06:27:11 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246806754 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.246806754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/21.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.268418345 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 39000202854 ps |
| CPU time | 108.33 seconds |
| Started | Aug 28 06:25:46 PM UTC 24 |
| Finished | Aug 28 06:27:37 PM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268418345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.268418345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/21.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.1885990208 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 121549256685 ps |
| CPU time | 237.21 seconds |
| Started | Aug 28 06:25:48 PM UTC 24 |
| Finished | Aug 28 06:29:49 PM UTC 24 |
| Peak memory | 199852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885990208 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.1885990208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/21.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.1329484939 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 737800862728 ps |
| CPU time | 642.75 seconds |
| Started | Aug 28 06:26:00 PM UTC 24 |
| Finished | Aug 28 06:36:52 PM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329484939 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.1329484939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.1309172973 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 141183232549 ps |
| CPU time | 69.15 seconds |
| Started | Aug 28 06:25:56 PM UTC 24 |
| Finished | Aug 28 06:27:07 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309172973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1309172973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/22.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.493730747 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 180801394792 ps |
| CPU time | 2415.27 seconds |
| Started | Aug 28 06:25:56 PM UTC 24 |
| Finished | Aug 28 07:06:44 PM UTC 24 |
| Peak memory | 202480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493730747 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.493730747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/22.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.1697943910 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 83605069204 ps |
| CPU time | 97.28 seconds |
| Started | Aug 28 06:26:05 PM UTC 24 |
| Finished | Aug 28 06:27:45 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697943910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1697943910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/22.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.2064502513 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 443757481162 ps |
| CPU time | 198.48 seconds |
| Started | Aug 28 06:26:11 PM UTC 24 |
| Finished | Aug 28 06:29:32 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064502513 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.2064502513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/22.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.477049287 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 305585852402 ps |
| CPU time | 793.01 seconds |
| Started | Aug 28 06:26:26 PM UTC 24 |
| Finished | Aug 28 06:39:50 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477049287 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.477049287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.2563450666 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 380442692757 ps |
| CPU time | 461.14 seconds |
| Started | Aug 28 06:26:37 PM UTC 24 |
| Finished | Aug 28 06:34:26 PM UTC 24 |
| Peak memory | 199692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563450666 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.2563450666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/23.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.1443003198 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 250788163905 ps |
| CPU time | 335.11 seconds |
| Started | Aug 28 06:26:50 PM UTC 24 |
| Finished | Aug 28 06:32:30 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443003198 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.1443003198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.1316823815 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 68846015450 ps |
| CPU time | 197.07 seconds |
| Started | Aug 28 06:26:56 PM UTC 24 |
| Finished | Aug 28 06:30:17 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316823815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1316823815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/24.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.2276234565 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 155753833870 ps |
| CPU time | 129.02 seconds |
| Started | Aug 28 06:27:12 PM UTC 24 |
| Finished | Aug 28 06:29:23 PM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276234565 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.2276234565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.2994928105 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 453834459973 ps |
| CPU time | 83.21 seconds |
| Started | Aug 28 06:27:08 PM UTC 24 |
| Finished | Aug 28 06:28:33 PM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994928105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2994928105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/25.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.91818554 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 45926104746 ps |
| CPU time | 127.19 seconds |
| Started | Aug 28 06:27:22 PM UTC 24 |
| Finished | Aug 28 06:29:31 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91818554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.91818554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/25.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.1156414125 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 371009694261 ps |
| CPU time | 825.16 seconds |
| Started | Aug 28 06:27:38 PM UTC 24 |
| Finished | Aug 28 06:41:35 PM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156414125 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.1156414125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/25.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.3365713619 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 103228429959 ps |
| CPU time | 154.67 seconds |
| Started | Aug 28 06:27:46 PM UTC 24 |
| Finished | Aug 28 06:30:23 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365713619 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.3365713619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.1251876195 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 161502188638 ps |
| CPU time | 375.71 seconds |
| Started | Aug 28 06:27:44 PM UTC 24 |
| Finished | Aug 28 06:34:05 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251876195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1251876195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/26.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.706875052 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 299595792 ps |
| CPU time | 2.02 seconds |
| Started | Aug 28 06:27:52 PM UTC 24 |
| Finished | Aug 28 06:27:55 PM UTC 24 |
| Peak memory | 199536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706875052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.706875052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/26.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all_with_rand_reset.4252778294 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2670025293 ps |
| CPU time | 13.94 seconds |
| Started | Aug 28 06:27:56 PM UTC 24 |
| Finished | Aug 28 06:28:11 PM UTC 24 |
| Peak memory | 201912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4252778294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.rv_timer_stress_all_with_rand_reset.4252778294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/26.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.757449913 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 960377399446 ps |
| CPU time | 1289.96 seconds |
| Started | Aug 28 06:28:32 PM UTC 24 |
| Finished | Aug 28 06:50:17 PM UTC 24 |
| Peak memory | 202328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757449913 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.757449913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.2461911789 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 27752076497 ps |
| CPU time | 73.75 seconds |
| Started | Aug 28 06:28:16 PM UTC 24 |
| Finished | Aug 28 06:29:32 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461911789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2461911789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/27.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.1300857577 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 122779792417 ps |
| CPU time | 817.46 seconds |
| Started | Aug 28 06:28:12 PM UTC 24 |
| Finished | Aug 28 06:42:03 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300857577 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1300857577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/27.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.616700655 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 91612376910 ps |
| CPU time | 651.92 seconds |
| Started | Aug 28 06:28:34 PM UTC 24 |
| Finished | Aug 28 06:39:35 PM UTC 24 |
| Peak memory | 199596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616700655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.616700655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/27.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.3924973485 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 59016451904 ps |
| CPU time | 36.28 seconds |
| Started | Aug 28 06:29:31 PM UTC 24 |
| Finished | Aug 28 06:30:09 PM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924973485 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.3924973485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.2955288709 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 334515681700 ps |
| CPU time | 136.98 seconds |
| Started | Aug 28 06:29:24 PM UTC 24 |
| Finished | Aug 28 06:31:43 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955288709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2955288709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/28.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.1418641604 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 26007027 ps |
| CPU time | 0.81 seconds |
| Started | Aug 28 06:29:32 PM UTC 24 |
| Finished | Aug 28 06:29:34 PM UTC 24 |
| Peak memory | 198936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418641604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1418641604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/28.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.3009291685 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 163301756907 ps |
| CPU time | 379.15 seconds |
| Started | Aug 28 06:29:33 PM UTC 24 |
| Finished | Aug 28 06:35:58 PM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009291685 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.3009291685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/28.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all_with_rand_reset.2038028389 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1882604387 ps |
| CPU time | 24.37 seconds |
| Started | Aug 28 06:29:33 PM UTC 24 |
| Finished | Aug 28 06:29:59 PM UTC 24 |
| Peak memory | 201948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2038028389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.rv_timer_stress_all_with_rand_reset.2038028389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/28.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.3823989966 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 823828869136 ps |
| CPU time | 1226.54 seconds |
| Started | Aug 28 06:29:49 PM UTC 24 |
| Finished | Aug 28 06:50:35 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823989966 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.3823989966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.3190358991 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 4214615167 ps |
| CPU time | 13.21 seconds |
| Started | Aug 28 06:29:46 PM UTC 24 |
| Finished | Aug 28 06:30:01 PM UTC 24 |
| Peak memory | 199532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190358991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3190358991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/29.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.771180343 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 59524227444 ps |
| CPU time | 150.64 seconds |
| Started | Aug 28 06:29:34 PM UTC 24 |
| Finished | Aug 28 06:32:08 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771180343 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.771180343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/29.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.1864611541 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 33642985625 ps |
| CPU time | 79.95 seconds |
| Started | Aug 28 06:29:59 PM UTC 24 |
| Finished | Aug 28 06:31:21 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864611541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1864611541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/29.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.252491612 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 2064695065865 ps |
| CPU time | 1532.68 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:47:00 PM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252491612 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.252491612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.1692981049 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 389828180130 ps |
| CPU time | 336.54 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:26:50 PM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692981049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1692981049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.3146207474 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 330149897067 ps |
| CPU time | 291.32 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:26:05 PM UTC 24 |
| Peak memory | 199748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146207474 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3146207474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.3936447843 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 13122811498 ps |
| CPU time | 14.01 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:21:24 PM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936447843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3936447843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.178625078 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 271268941 ps |
| CPU time | 0.79 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:21:11 PM UTC 24 |
| Peak memory | 230952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178625078 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.178625078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.4172452100 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 169646055314 ps |
| CPU time | 491.67 seconds |
| Started | Aug 28 06:30:18 PM UTC 24 |
| Finished | Aug 28 06:38:40 PM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172452100 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.4172452100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.3741676938 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 20931774300 ps |
| CPU time | 46.7 seconds |
| Started | Aug 28 06:30:13 PM UTC 24 |
| Finished | Aug 28 06:31:01 PM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741676938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3741676938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/30.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.1919274085 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 129444357644 ps |
| CPU time | 134.69 seconds |
| Started | Aug 28 06:30:10 PM UTC 24 |
| Finished | Aug 28 06:32:28 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919274085 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1919274085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/30.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.2458583650 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 18606939876 ps |
| CPU time | 46.77 seconds |
| Started | Aug 28 06:30:24 PM UTC 24 |
| Finished | Aug 28 06:31:12 PM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458583650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2458583650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/30.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.2352875158 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 312729370918 ps |
| CPU time | 878.03 seconds |
| Started | Aug 28 06:30:59 PM UTC 24 |
| Finished | Aug 28 06:45:49 PM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352875158 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.2352875158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/30.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.866384515 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 80197853280 ps |
| CPU time | 112.3 seconds |
| Started | Aug 28 06:31:15 PM UTC 24 |
| Finished | Aug 28 06:33:11 PM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866384515 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.866384515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.1717261838 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 244514105521 ps |
| CPU time | 290.69 seconds |
| Started | Aug 28 06:31:13 PM UTC 24 |
| Finished | Aug 28 06:36:08 PM UTC 24 |
| Peak memory | 199812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717261838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1717261838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/31.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.3655972916 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 122926695882 ps |
| CPU time | 193.63 seconds |
| Started | Aug 28 06:31:23 PM UTC 24 |
| Finished | Aug 28 06:34:40 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655972916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3655972916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/31.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.2229871065 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1063709975817 ps |
| CPU time | 734.65 seconds |
| Started | Aug 28 06:32:04 PM UTC 24 |
| Finished | Aug 28 06:44:29 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229871065 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.2229871065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.3803298924 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 532477752364 ps |
| CPU time | 345.3 seconds |
| Started | Aug 28 06:32:03 PM UTC 24 |
| Finished | Aug 28 06:37:53 PM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803298924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3803298924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/32.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.3513097242 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 248137566368 ps |
| CPU time | 170.64 seconds |
| Started | Aug 28 06:31:45 PM UTC 24 |
| Finished | Aug 28 06:34:38 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513097242 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3513097242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/32.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.602077881 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 53411664607 ps |
| CPU time | 129.52 seconds |
| Started | Aug 28 06:32:09 PM UTC 24 |
| Finished | Aug 28 06:34:21 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602077881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.602077881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/32.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.2449650690 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 839147219495 ps |
| CPU time | 818.41 seconds |
| Started | Aug 28 06:32:25 PM UTC 24 |
| Finished | Aug 28 06:46:14 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449650690 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.2449650690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/32.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all_with_rand_reset.1833017745 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 9622392717 ps |
| CPU time | 38.78 seconds |
| Started | Aug 28 06:32:11 PM UTC 24 |
| Finished | Aug 28 06:32:51 PM UTC 24 |
| Peak memory | 201912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1833017745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.rv_timer_stress_all_with_rand_reset.1833017745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/32.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.2675646170 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 687566551882 ps |
| CPU time | 1844.16 seconds |
| Started | Aug 28 06:32:33 PM UTC 24 |
| Finished | Aug 28 07:03:41 PM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675646170 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.2675646170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.278741712 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 948740482877 ps |
| CPU time | 239.29 seconds |
| Started | Aug 28 06:32:31 PM UTC 24 |
| Finished | Aug 28 06:36:35 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278741712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.278741712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/33.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.1832775992 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 65005949841 ps |
| CPU time | 454.59 seconds |
| Started | Aug 28 06:32:29 PM UTC 24 |
| Finished | Aug 28 06:40:11 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832775992 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1832775992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/33.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.1675430396 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 227860858 ps |
| CPU time | 0.85 seconds |
| Started | Aug 28 06:32:42 PM UTC 24 |
| Finished | Aug 28 06:32:44 PM UTC 24 |
| Peak memory | 198936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675430396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1675430396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/33.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.901975969 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 4329185054584 ps |
| CPU time | 1233.43 seconds |
| Started | Aug 28 06:32:50 PM UTC 24 |
| Finished | Aug 28 06:53:42 PM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901975969 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.901975969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/33.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.577134997 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 43907868855 ps |
| CPU time | 38.93 seconds |
| Started | Aug 28 06:33:12 PM UTC 24 |
| Finished | Aug 28 06:33:52 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577134997 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.577134997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.3859436983 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 85188381318 ps |
| CPU time | 200.12 seconds |
| Started | Aug 28 06:33:12 PM UTC 24 |
| Finished | Aug 28 06:36:36 PM UTC 24 |
| Peak memory | 199616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859436983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3859436983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/34.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.2259089534 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 174155920634 ps |
| CPU time | 1396.35 seconds |
| Started | Aug 28 06:33:23 PM UTC 24 |
| Finished | Aug 28 06:56:58 PM UTC 24 |
| Peak memory | 199608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259089534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2259089534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/34.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.2332086855 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 388031989733 ps |
| CPU time | 250.73 seconds |
| Started | Aug 28 06:33:53 PM UTC 24 |
| Finished | Aug 28 06:38:08 PM UTC 24 |
| Peak memory | 199620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332086855 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.2332086855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/34.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all_with_rand_reset.3192505851 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 7733770906 ps |
| CPU time | 58.65 seconds |
| Started | Aug 28 06:33:26 PM UTC 24 |
| Finished | Aug 28 06:34:26 PM UTC 24 |
| Peak memory | 203960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3192505851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.rv_timer_stress_all_with_rand_reset.3192505851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/34.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.237311254 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 58950387481 ps |
| CPU time | 154.97 seconds |
| Started | Aug 28 06:34:22 PM UTC 24 |
| Finished | Aug 28 06:37:01 PM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237311254 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.237311254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.1660563142 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 55180133125 ps |
| CPU time | 163.8 seconds |
| Started | Aug 28 06:34:16 PM UTC 24 |
| Finished | Aug 28 06:37:03 PM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660563142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1660563142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/35.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.1766931481 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 342102993741 ps |
| CPU time | 377.04 seconds |
| Started | Aug 28 06:34:06 PM UTC 24 |
| Finished | Aug 28 06:40:30 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766931481 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1766931481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/35.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.3135124411 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2796120008 ps |
| CPU time | 4.5 seconds |
| Started | Aug 28 06:34:27 PM UTC 24 |
| Finished | Aug 28 06:34:34 PM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135124411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3135124411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/35.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.1408659678 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 2265927738315 ps |
| CPU time | 1985.72 seconds |
| Started | Aug 28 06:34:27 PM UTC 24 |
| Finished | Aug 28 07:08:00 PM UTC 24 |
| Peak memory | 199616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408659678 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.1408659678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/35.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all_with_rand_reset.1683678602 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2575838532 ps |
| CPU time | 30.87 seconds |
| Started | Aug 28 06:34:27 PM UTC 24 |
| Finished | Aug 28 06:35:00 PM UTC 24 |
| Peak memory | 204024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1683678602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.rv_timer_stress_all_with_rand_reset.1683678602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/35.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.3011788221 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 71130024794 ps |
| CPU time | 152.21 seconds |
| Started | Aug 28 06:34:40 PM UTC 24 |
| Finished | Aug 28 06:37:15 PM UTC 24 |
| Peak memory | 199688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011788221 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.3011788221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.3727463266 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 373516129015 ps |
| CPU time | 230.05 seconds |
| Started | Aug 28 06:34:35 PM UTC 24 |
| Finished | Aug 28 06:38:28 PM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727463266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3727463266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/36.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.2305043576 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 85535749537 ps |
| CPU time | 213.95 seconds |
| Started | Aug 28 06:34:30 PM UTC 24 |
| Finished | Aug 28 06:38:07 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305043576 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2305043576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/36.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.2705574813 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 76012997093 ps |
| CPU time | 725.45 seconds |
| Started | Aug 28 06:34:41 PM UTC 24 |
| Finished | Aug 28 06:46:57 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705574813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2705574813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/36.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.963170012 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 50885659884 ps |
| CPU time | 82.81 seconds |
| Started | Aug 28 06:35:17 PM UTC 24 |
| Finished | Aug 28 06:36:42 PM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963170012 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.963170012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/36.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.583635464 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 19444257554 ps |
| CPU time | 61.93 seconds |
| Started | Aug 28 06:36:36 PM UTC 24 |
| Finished | Aug 28 06:37:41 PM UTC 24 |
| Peak memory | 199492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583635464 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.583635464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.3399815202 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 22806463537 ps |
| CPU time | 67.51 seconds |
| Started | Aug 28 06:36:09 PM UTC 24 |
| Finished | Aug 28 06:37:19 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399815202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3399815202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/37.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.355154153 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 52531891635 ps |
| CPU time | 113.69 seconds |
| Started | Aug 28 06:35:58 PM UTC 24 |
| Finished | Aug 28 06:37:55 PM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355154153 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.355154153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/37.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.680597292 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 89748003497 ps |
| CPU time | 196.55 seconds |
| Started | Aug 28 06:36:36 PM UTC 24 |
| Finished | Aug 28 06:39:57 PM UTC 24 |
| Peak memory | 199748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680597292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.680597292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/37.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.1200002293 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 266367409747 ps |
| CPU time | 194.05 seconds |
| Started | Aug 28 06:36:53 PM UTC 24 |
| Finished | Aug 28 06:40:10 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200002293 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.1200002293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/37.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.1566807356 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 478222138181 ps |
| CPU time | 1263.14 seconds |
| Started | Aug 28 06:37:04 PM UTC 24 |
| Finished | Aug 28 06:58:24 PM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566807356 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.1566807356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.1969940092 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 456713241038 ps |
| CPU time | 308.03 seconds |
| Started | Aug 28 06:37:02 PM UTC 24 |
| Finished | Aug 28 06:42:15 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969940092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1969940092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/38.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.2134112403 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 168291992992 ps |
| CPU time | 654.61 seconds |
| Started | Aug 28 06:36:57 PM UTC 24 |
| Finished | Aug 28 06:48:01 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134112403 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2134112403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/38.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.2275786222 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1416040537277 ps |
| CPU time | 881.23 seconds |
| Started | Aug 28 06:37:35 PM UTC 24 |
| Finished | Aug 28 06:52:29 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275786222 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.2275786222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/38.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.945109851 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 154380510141 ps |
| CPU time | 379.95 seconds |
| Started | Aug 28 06:37:54 PM UTC 24 |
| Finished | Aug 28 06:44:21 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945109851 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.945109851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.1692912012 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 284105088212 ps |
| CPU time | 319.97 seconds |
| Started | Aug 28 06:37:41 PM UTC 24 |
| Finished | Aug 28 06:43:06 PM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692912012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1692912012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/39.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.2152118679 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 89582214364 ps |
| CPU time | 290.32 seconds |
| Started | Aug 28 06:37:39 PM UTC 24 |
| Finished | Aug 28 06:42:34 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152118679 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2152118679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/39.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.2001496416 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 451603608 ps |
| CPU time | 2.37 seconds |
| Started | Aug 28 06:37:55 PM UTC 24 |
| Finished | Aug 28 06:37:59 PM UTC 24 |
| Peak memory | 199644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001496416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2001496416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/39.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.2880720540 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3102310236 ps |
| CPU time | 9.75 seconds |
| Started | Aug 28 06:38:08 PM UTC 24 |
| Finished | Aug 28 06:38:19 PM UTC 24 |
| Peak memory | 199472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880720540 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.2880720540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/39.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.2959488608 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 322087744237 ps |
| CPU time | 150.48 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:23:42 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959488608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2959488608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.685495243 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1598894516 ps |
| CPU time | 3.43 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:21:14 PM UTC 24 |
| Peak memory | 199396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685495243 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.685495243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.310910677 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 61488873 ps |
| CPU time | 0.87 seconds |
| Started | Aug 28 06:21:09 PM UTC 24 |
| Finished | Aug 28 06:21:11 PM UTC 24 |
| Peak memory | 228940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310910677 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.310910677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.846372623 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 181015498424 ps |
| CPU time | 436.75 seconds |
| Started | Aug 28 06:38:18 PM UTC 24 |
| Finished | Aug 28 06:45:40 PM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846372623 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.846372623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.1695732453 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 635385815808 ps |
| CPU time | 287.02 seconds |
| Started | Aug 28 06:38:15 PM UTC 24 |
| Finished | Aug 28 06:43:06 PM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695732453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1695732453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/40.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.1338214238 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 714890460 ps |
| CPU time | 1.39 seconds |
| Started | Aug 28 06:38:20 PM UTC 24 |
| Finished | Aug 28 06:38:22 PM UTC 24 |
| Peak memory | 198936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338214238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1338214238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/40.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.3324644006 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 1541035572104 ps |
| CPU time | 610.54 seconds |
| Started | Aug 28 06:38:29 PM UTC 24 |
| Finished | Aug 28 06:48:49 PM UTC 24 |
| Peak memory | 199656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324644006 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.3324644006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.2492983140 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 78996199249 ps |
| CPU time | 151.99 seconds |
| Started | Aug 28 06:38:29 PM UTC 24 |
| Finished | Aug 28 06:41:04 PM UTC 24 |
| Peak memory | 199516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492983140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2492983140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/41.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.598150236 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 67894011233 ps |
| CPU time | 153.43 seconds |
| Started | Aug 28 06:38:28 PM UTC 24 |
| Finished | Aug 28 06:41:05 PM UTC 24 |
| Peak memory | 199608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598150236 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.598150236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/41.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.4156864610 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 93928204813 ps |
| CPU time | 170.03 seconds |
| Started | Aug 28 06:38:41 PM UTC 24 |
| Finished | Aug 28 06:41:35 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156864610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.4156864610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/41.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.2070471088 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 23256621 ps |
| CPU time | 0.84 seconds |
| Started | Aug 28 06:39:40 PM UTC 24 |
| Finished | Aug 28 06:39:42 PM UTC 24 |
| Peak memory | 198880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070471088 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.2070471088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/41.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.1768570482 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 407859927083 ps |
| CPU time | 683.06 seconds |
| Started | Aug 28 06:39:51 PM UTC 24 |
| Finished | Aug 28 06:51:24 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768570482 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.1768570482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.3153622551 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 52302289948 ps |
| CPU time | 111.11 seconds |
| Started | Aug 28 06:39:44 PM UTC 24 |
| Finished | Aug 28 06:41:38 PM UTC 24 |
| Peak memory | 199912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153622551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3153622551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/42.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.1727404872 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 24225339735 ps |
| CPU time | 51.53 seconds |
| Started | Aug 28 06:39:58 PM UTC 24 |
| Finished | Aug 28 06:40:51 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727404872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1727404872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/42.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.2029057213 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 75375907 ps |
| CPU time | 0.96 seconds |
| Started | Aug 28 06:40:11 PM UTC 24 |
| Finished | Aug 28 06:40:13 PM UTC 24 |
| Peak memory | 198880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029057213 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.2029057213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/42.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.3701803554 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 24004846885 ps |
| CPU time | 70.54 seconds |
| Started | Aug 28 06:40:18 PM UTC 24 |
| Finished | Aug 28 06:41:31 PM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701803554 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.3701803554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.2846937612 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 37166824302 ps |
| CPU time | 91.12 seconds |
| Started | Aug 28 06:40:14 PM UTC 24 |
| Finished | Aug 28 06:41:47 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846937612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2846937612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/43.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.130162112 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 35004751846 ps |
| CPU time | 88.32 seconds |
| Started | Aug 28 06:40:12 PM UTC 24 |
| Finished | Aug 28 06:41:43 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130162112 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.130162112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/43.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.2637919906 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 66319481819 ps |
| CPU time | 139.92 seconds |
| Started | Aug 28 06:40:31 PM UTC 24 |
| Finished | Aug 28 06:42:54 PM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637919906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2637919906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/43.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.1585244268 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 1334496947726 ps |
| CPU time | 1404.1 seconds |
| Started | Aug 28 06:41:06 PM UTC 24 |
| Finished | Aug 28 07:04:47 PM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1585244268 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.1585244268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.416434529 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 828483121636 ps |
| CPU time | 305.05 seconds |
| Started | Aug 28 06:41:04 PM UTC 24 |
| Finished | Aug 28 06:46:15 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416434529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.416434529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/44.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.1040933571 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 108607251133 ps |
| CPU time | 256.86 seconds |
| Started | Aug 28 06:40:55 PM UTC 24 |
| Finished | Aug 28 06:45:17 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040933571 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1040933571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/44.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.992508240 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 53402288478 ps |
| CPU time | 541.53 seconds |
| Started | Aug 28 06:41:32 PM UTC 24 |
| Finished | Aug 28 06:50:41 PM UTC 24 |
| Peak memory | 199812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992508240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.992508240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/44.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.2483152038 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 112194200264 ps |
| CPU time | 278.72 seconds |
| Started | Aug 28 06:41:42 PM UTC 24 |
| Finished | Aug 28 06:46:25 PM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483152038 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.2483152038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.3317327965 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 52559083783 ps |
| CPU time | 37.96 seconds |
| Started | Aug 28 06:41:40 PM UTC 24 |
| Finished | Aug 28 06:42:19 PM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317327965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3317327965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/45.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.745912713 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 508830111171 ps |
| CPU time | 356.91 seconds |
| Started | Aug 28 06:41:39 PM UTC 24 |
| Finished | Aug 28 06:47:42 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745912713 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.745912713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/45.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.4126144018 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 13216286343 ps |
| CPU time | 29.9 seconds |
| Started | Aug 28 06:41:43 PM UTC 24 |
| Finished | Aug 28 06:42:14 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126144018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.4126144018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/45.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.938885828 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 603647374035 ps |
| CPU time | 431.44 seconds |
| Started | Aug 28 06:42:03 PM UTC 24 |
| Finished | Aug 28 06:49:21 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938885828 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.938885828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/45.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.3857071623 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 255204051317 ps |
| CPU time | 585.72 seconds |
| Started | Aug 28 06:42:20 PM UTC 24 |
| Finished | Aug 28 06:52:14 PM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857071623 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.3857071623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.1251058060 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 149754142069 ps |
| CPU time | 249.32 seconds |
| Started | Aug 28 06:42:16 PM UTC 24 |
| Finished | Aug 28 06:46:30 PM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251058060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1251058060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/46.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.4247539607 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 137354687753 ps |
| CPU time | 572.46 seconds |
| Started | Aug 28 06:42:15 PM UTC 24 |
| Finished | Aug 28 06:51:57 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247539607 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.4247539607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/46.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.3700439565 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2820014904 ps |
| CPU time | 8.83 seconds |
| Started | Aug 28 06:42:22 PM UTC 24 |
| Finished | Aug 28 06:42:32 PM UTC 24 |
| Peak memory | 199660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700439565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3700439565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/46.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.2275434817 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 468735913917 ps |
| CPU time | 264.94 seconds |
| Started | Aug 28 06:42:32 PM UTC 24 |
| Finished | Aug 28 06:47:02 PM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275434817 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.2275434817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/46.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all_with_rand_reset.1128914805 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1706067952 ps |
| CPU time | 28.47 seconds |
| Started | Aug 28 06:42:29 PM UTC 24 |
| Finished | Aug 28 06:42:59 PM UTC 24 |
| Peak memory | 203960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1128914805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.rv_timer_stress_all_with_rand_reset.1128914805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/46.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.2622560815 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 322898308736 ps |
| CPU time | 253.51 seconds |
| Started | Aug 28 06:42:35 PM UTC 24 |
| Finished | Aug 28 06:46:53 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622560815 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.2622560815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.1343714464 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 647402969817 ps |
| CPU time | 353.36 seconds |
| Started | Aug 28 06:42:34 PM UTC 24 |
| Finished | Aug 28 06:48:33 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343714464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1343714464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/47.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.2216322998 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 2386060190739 ps |
| CPU time | 852.61 seconds |
| Started | Aug 28 06:42:34 PM UTC 24 |
| Finished | Aug 28 06:56:59 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216322998 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2216322998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/47.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.3679569137 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 120315020 ps |
| CPU time | 1.4 seconds |
| Started | Aug 28 06:42:55 PM UTC 24 |
| Finished | Aug 28 06:42:57 PM UTC 24 |
| Peak memory | 198936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679569137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3679569137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/47.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.1777104199 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 851901012382 ps |
| CPU time | 469.06 seconds |
| Started | Aug 28 06:43:00 PM UTC 24 |
| Finished | Aug 28 06:50:57 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777104199 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.1777104199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/47.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.2597990960 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 478997722262 ps |
| CPU time | 369.85 seconds |
| Started | Aug 28 06:43:07 PM UTC 24 |
| Finished | Aug 28 06:49:23 PM UTC 24 |
| Peak memory | 199200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597990960 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.2597990960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.4202998635 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 77883570090 ps |
| CPU time | 163.43 seconds |
| Started | Aug 28 06:43:07 PM UTC 24 |
| Finished | Aug 28 06:45:54 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202998635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4202998635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/48.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.3121386068 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 70251657 ps |
| CPU time | 0.93 seconds |
| Started | Aug 28 06:43:08 PM UTC 24 |
| Finished | Aug 28 06:43:10 PM UTC 24 |
| Peak memory | 198936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121386068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3121386068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/48.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.3584910958 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 88972811985 ps |
| CPU time | 192.16 seconds |
| Started | Aug 28 06:43:12 PM UTC 24 |
| Finished | Aug 28 06:46:28 PM UTC 24 |
| Peak memory | 199692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584910958 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.3584910958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/48.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.1545470386 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 18376332822 ps |
| CPU time | 52.09 seconds |
| Started | Aug 28 06:44:08 PM UTC 24 |
| Finished | Aug 28 06:45:01 PM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545470386 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.1545470386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.1356420191 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 53216169424 ps |
| CPU time | 115.91 seconds |
| Started | Aug 28 06:43:35 PM UTC 24 |
| Finished | Aug 28 06:45:34 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356420191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1356420191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/49.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.1415770702 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 195080729932 ps |
| CPU time | 1054.64 seconds |
| Started | Aug 28 06:43:13 PM UTC 24 |
| Finished | Aug 28 07:01:03 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415770702 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1415770702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/49.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.2914225818 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 191662007616 ps |
| CPU time | 279.69 seconds |
| Started | Aug 28 06:44:19 PM UTC 24 |
| Finished | Aug 28 06:49:03 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914225818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2914225818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/49.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.3393607982 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 551897331162 ps |
| CPU time | 1125.8 seconds |
| Started | Aug 28 06:44:30 PM UTC 24 |
| Finished | Aug 28 07:03:30 PM UTC 24 |
| Peak memory | 199620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393607982 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.3393607982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/49.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.1219159984 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 261083866322 ps |
| CPU time | 365.68 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:27:22 PM UTC 24 |
| Peak memory | 199720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219159984 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.1219159984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.3152902269 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 189351132408 ps |
| CPU time | 95.39 seconds |
| Started | Aug 28 06:21:10 PM UTC 24 |
| Finished | Aug 28 06:22:47 PM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152902269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3152902269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/5.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.462592202 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 1249243554 ps |
| CPU time | 5.66 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:21:18 PM UTC 24 |
| Peak memory | 199644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462592202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.462592202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/5.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.609715758 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 432717686566 ps |
| CPU time | 280.87 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:25:56 PM UTC 24 |
| Peak memory | 199752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609715758 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.609715758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/5.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all_with_rand_reset.263373793 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2373463565 ps |
| CPU time | 31.1 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:21:43 PM UTC 24 |
| Peak memory | 203972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=263373793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.263373793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/5.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.2644989715 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 134808567837 ps |
| CPU time | 249.07 seconds |
| Started | Aug 28 06:44:38 PM UTC 24 |
| Finished | Aug 28 06:48:51 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644989715 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2644989715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/50.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.873499451 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 153430607373 ps |
| CPU time | 753.66 seconds |
| Started | Aug 28 06:44:53 PM UTC 24 |
| Finished | Aug 28 06:57:38 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873499451 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.873499451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/51.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.1747563520 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 495217922571 ps |
| CPU time | 178.46 seconds |
| Started | Aug 28 06:44:54 PM UTC 24 |
| Finished | Aug 28 06:47:56 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747563520 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1747563520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/52.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.2618962795 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 83908965561 ps |
| CPU time | 101.42 seconds |
| Started | Aug 28 06:45:02 PM UTC 24 |
| Finished | Aug 28 06:46:46 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618962795 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2618962795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/53.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.846208853 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 99521392151 ps |
| CPU time | 544.67 seconds |
| Started | Aug 28 06:45:13 PM UTC 24 |
| Finished | Aug 28 06:54:27 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846208853 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.846208853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/54.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.4100133918 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 59582955296 ps |
| CPU time | 232.98 seconds |
| Started | Aug 28 06:45:18 PM UTC 24 |
| Finished | Aug 28 06:49:15 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100133918 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.4100133918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/55.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.3489785374 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 118247900561 ps |
| CPU time | 211.83 seconds |
| Started | Aug 28 06:45:35 PM UTC 24 |
| Finished | Aug 28 06:49:11 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489785374 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3489785374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/56.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.3065223929 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 9853435574 ps |
| CPU time | 26.3 seconds |
| Started | Aug 28 06:45:41 PM UTC 24 |
| Finished | Aug 28 06:46:09 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065223929 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3065223929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/57.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.1399591791 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 931999011768 ps |
| CPU time | 2711.57 seconds |
| Started | Aug 28 06:45:50 PM UTC 24 |
| Finished | Aug 28 07:31:41 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399591791 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1399591791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/58.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.4233033933 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 239724294118 ps |
| CPU time | 333.54 seconds |
| Started | Aug 28 06:45:55 PM UTC 24 |
| Finished | Aug 28 06:51:34 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233033933 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.4233033933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/59.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.390442672 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 284904197983 ps |
| CPU time | 294.9 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:26:10 PM UTC 24 |
| Peak memory | 199584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390442672 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.390442672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.1289436310 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 126111272506 ps |
| CPU time | 332.36 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:26:48 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289436310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1289436310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/6.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.1673348845 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 576601823982 ps |
| CPU time | 485.67 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:29:23 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673348845 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.1673348845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/6.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.1598295528 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 199373131739 ps |
| CPU time | 150.89 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:23:45 PM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598295528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1598295528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/6.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.3114159814 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 349661347391 ps |
| CPU time | 1742.69 seconds |
| Started | Aug 28 06:46:10 PM UTC 24 |
| Finished | Aug 28 07:15:38 PM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114159814 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3114159814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/60.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.1673892452 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 15336431192 ps |
| CPU time | 34.73 seconds |
| Started | Aug 28 06:46:16 PM UTC 24 |
| Finished | Aug 28 06:46:52 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673892452 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1673892452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/62.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.1024592795 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 10205778751 ps |
| CPU time | 36.15 seconds |
| Started | Aug 28 06:46:27 PM UTC 24 |
| Finished | Aug 28 06:47:05 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024592795 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1024592795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/63.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.3918858770 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 239688092955 ps |
| CPU time | 183.28 seconds |
| Started | Aug 28 06:46:29 PM UTC 24 |
| Finished | Aug 28 06:49:36 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918858770 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3918858770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/64.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.1651559759 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 57196542572 ps |
| CPU time | 12.06 seconds |
| Started | Aug 28 06:46:31 PM UTC 24 |
| Finished | Aug 28 06:46:44 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651559759 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1651559759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/65.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.1577744286 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 123683138452 ps |
| CPU time | 478.85 seconds |
| Started | Aug 28 06:46:45 PM UTC 24 |
| Finished | Aug 28 06:54:52 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577744286 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1577744286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/66.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.1286104739 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 14273770979 ps |
| CPU time | 36.58 seconds |
| Started | Aug 28 06:46:47 PM UTC 24 |
| Finished | Aug 28 06:47:25 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286104739 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1286104739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/67.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.3404574399 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 222378332616 ps |
| CPU time | 709.2 seconds |
| Started | Aug 28 06:46:53 PM UTC 24 |
| Finished | Aug 28 06:58:52 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404574399 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3404574399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/68.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.2791503066 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 250454918600 ps |
| CPU time | 166.87 seconds |
| Started | Aug 28 06:46:54 PM UTC 24 |
| Finished | Aug 28 06:49:44 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791503066 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2791503066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/69.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.2845834764 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 278311402967 ps |
| CPU time | 148.38 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:23:42 PM UTC 24 |
| Peak memory | 199580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845834764 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.2845834764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.402090571 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 449858620846 ps |
| CPU time | 270.42 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:25:46 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402090571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.402090571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/7.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.1358823913 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 40671791 ps |
| CPU time | 0.79 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:21:13 PM UTC 24 |
| Peak memory | 198872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358823913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1358823913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/7.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.941206442 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 143384017314 ps |
| CPU time | 516.22 seconds |
| Started | Aug 28 06:47:01 PM UTC 24 |
| Finished | Aug 28 06:55:45 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941206442 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.941206442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/71.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.89300978 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 34199655819 ps |
| CPU time | 78.35 seconds |
| Started | Aug 28 06:47:02 PM UTC 24 |
| Finished | Aug 28 06:48:23 PM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89300978 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.89300978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/72.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.848476916 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 75831177910 ps |
| CPU time | 552.11 seconds |
| Started | Aug 28 06:47:17 PM UTC 24 |
| Finished | Aug 28 06:56:37 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848476916 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.848476916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/74.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.1347861414 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 127321824212 ps |
| CPU time | 362.67 seconds |
| Started | Aug 28 06:47:26 PM UTC 24 |
| Finished | Aug 28 06:53:34 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347861414 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1347861414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/76.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.4100991642 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 25110578324 ps |
| CPU time | 66.54 seconds |
| Started | Aug 28 06:47:33 PM UTC 24 |
| Finished | Aug 28 06:48:41 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100991642 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4100991642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/77.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.3246281961 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 513744576035 ps |
| CPU time | 342.16 seconds |
| Started | Aug 28 06:47:43 PM UTC 24 |
| Finished | Aug 28 06:53:31 PM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246281961 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3246281961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/78.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.3984456701 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 236603159137 ps |
| CPU time | 2650.3 seconds |
| Started | Aug 28 06:47:45 PM UTC 24 |
| Finished | Aug 28 07:32:35 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984456701 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3984456701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/79.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.371001142 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 548942613654 ps |
| CPU time | 320.09 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:26:36 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371001142 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.371001142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.619685511 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 185982859047 ps |
| CPU time | 162.57 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:23:57 PM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619685511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.619685511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/8.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.3993232061 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 160820946601 ps |
| CPU time | 1402.27 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:44:52 PM UTC 24 |
| Peak memory | 202456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993232061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3993232061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/8.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.2185808986 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 260968951279 ps |
| CPU time | 635.08 seconds |
| Started | Aug 28 06:47:57 PM UTC 24 |
| Finished | Aug 28 06:58:42 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185808986 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2185808986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/80.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.1391603874 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 550271941555 ps |
| CPU time | 903.38 seconds |
| Started | Aug 28 06:48:02 PM UTC 24 |
| Finished | Aug 28 07:03:20 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391603874 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1391603874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/81.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.3380829025 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 185649692737 ps |
| CPU time | 1455.87 seconds |
| Started | Aug 28 06:48:22 PM UTC 24 |
| Finished | Aug 28 07:12:59 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380829025 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3380829025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/82.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.106227930 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 31420299695 ps |
| CPU time | 20.09 seconds |
| Started | Aug 28 06:48:24 PM UTC 24 |
| Finished | Aug 28 06:48:46 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106227930 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.106227930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/83.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.3796956175 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 108897060943 ps |
| CPU time | 217.99 seconds |
| Started | Aug 28 06:48:34 PM UTC 24 |
| Finished | Aug 28 06:52:16 PM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796956175 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3796956175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/84.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.4123721587 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 17776649343 ps |
| CPU time | 12.71 seconds |
| Started | Aug 28 06:48:40 PM UTC 24 |
| Finished | Aug 28 06:48:54 PM UTC 24 |
| Peak memory | 199528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123721587 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.4123721587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/85.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.2728383155 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 515738698265 ps |
| CPU time | 993.32 seconds |
| Started | Aug 28 06:48:42 PM UTC 24 |
| Finished | Aug 28 07:05:31 PM UTC 24 |
| Peak memory | 199904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728383155 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2728383155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/86.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.898067196 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 135702065674 ps |
| CPU time | 377.05 seconds |
| Started | Aug 28 06:48:46 PM UTC 24 |
| Finished | Aug 28 06:55:09 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898067196 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.898067196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/87.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.880491511 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 328626422157 ps |
| CPU time | 110.9 seconds |
| Started | Aug 28 06:48:49 PM UTC 24 |
| Finished | Aug 28 06:50:43 PM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880491511 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.880491511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/88.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.3412083862 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 362399329226 ps |
| CPU time | 559.4 seconds |
| Started | Aug 28 06:48:50 PM UTC 24 |
| Finished | Aug 28 06:58:19 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412083862 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3412083862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/89.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.583112594 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 599522838120 ps |
| CPU time | 669.62 seconds |
| Started | Aug 28 06:21:14 PM UTC 24 |
| Finished | Aug 28 06:32:32 PM UTC 24 |
| Peak memory | 199340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583112594 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.583112594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.2041956791 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 133988524133 ps |
| CPU time | 302.55 seconds |
| Started | Aug 28 06:21:14 PM UTC 24 |
| Finished | Aug 28 06:26:21 PM UTC 24 |
| Peak memory | 199584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041956791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2041956791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/9.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.2394515638 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 894695425976 ps |
| CPU time | 1385.17 seconds |
| Started | Aug 28 06:21:11 PM UTC 24 |
| Finished | Aug 28 06:44:37 PM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394515638 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2394515638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/9.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.72827858 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 346242283 ps |
| CPU time | 1.05 seconds |
| Started | Aug 28 06:21:14 PM UTC 24 |
| Finished | Aug 28 06:21:16 PM UTC 24 |
| Peak memory | 198572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72827858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.72827858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/9.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.1151632950 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 348726920921 ps |
| CPU time | 707.53 seconds |
| Started | Aug 28 06:21:15 PM UTC 24 |
| Finished | Aug 28 06:33:11 PM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151632950 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.1151632950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/9.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.221473508 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1839398990720 ps |
| CPU time | 768.1 seconds |
| Started | Aug 28 06:48:53 PM UTC 24 |
| Finished | Aug 28 07:01:52 PM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221473508 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.221473508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/90.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.1573122825 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 178682625222 ps |
| CPU time | 987.55 seconds |
| Started | Aug 28 06:48:55 PM UTC 24 |
| Finished | Aug 28 07:05:38 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573122825 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1573122825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/91.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.3502462649 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 585533002920 ps |
| CPU time | 402.9 seconds |
| Started | Aug 28 06:49:04 PM UTC 24 |
| Finished | Aug 28 06:55:53 PM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502462649 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3502462649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/92.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.1267648595 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 479828080202 ps |
| CPU time | 91.21 seconds |
| Started | Aug 28 06:49:10 PM UTC 24 |
| Finished | Aug 28 06:50:43 PM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267648595 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1267648595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/93.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.2745763697 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 715337778405 ps |
| CPU time | 1060.02 seconds |
| Started | Aug 28 06:49:22 PM UTC 24 |
| Finished | Aug 28 07:07:18 PM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745763697 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2745763697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/96.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.1131752648 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 80262432716 ps |
| CPU time | 585.26 seconds |
| Started | Aug 28 06:49:29 PM UTC 24 |
| Finished | Aug 28 06:59:25 PM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131752648 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1131752648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/98.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.2008348560 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 385939875970 ps |
| CPU time | 640.37 seconds |
| Started | Aug 28 06:49:37 PM UTC 24 |
| Finished | Aug 28 07:00:27 PM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008348560 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_28/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2008348560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_28/rv_timer-sim-vcs/99.rv_timer_random/latest |
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