Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.70	99.36	99.04	100.00		100.00	100.00	99.77

Total test records in report: 579

T506	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2999520500	Sep 01 04:51:20 AM UTC 24	Sep 01 04:51:21 AM UTC 24	16053067 ps
T507	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.608410370	Sep 01 04:51:20 AM UTC 24	Sep 01 04:51:21 AM UTC 24	33491633 ps
T508	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3007763688	Sep 01 04:51:20 AM UTC 24	Sep 01 04:51:22 AM UTC 24	199795409 ps
T509	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.888175186	Sep 01 04:51:18 AM UTC 24	Sep 01 04:51:22 AM UTC 24	152031594 ps
T510	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.232771279	Sep 01 04:51:20 AM UTC 24	Sep 01 04:51:22 AM UTC 24	37387459 ps
T511	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2189341666	Sep 01 04:51:20 AM UTC 24	Sep 01 04:51:22 AM UTC 24	60742705 ps
T93	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1600752194	Sep 01 04:51:20 AM UTC 24	Sep 01 04:51:22 AM UTC 24	238866514 ps
T512	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.1353923978	Sep 01 04:51:21 AM UTC 24	Sep 01 04:51:23 AM UTC 24	11665163 ps
T75	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.2955545496	Sep 01 04:51:21 AM UTC 24	Sep 01 04:51:23 AM UTC 24	18056767 ps
T513	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3826496827	Sep 01 04:51:21 AM UTC 24	Sep 01 04:51:23 AM UTC 24	26382530 ps
T92	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2767270031	Sep 01 04:51:21 AM UTC 24	Sep 01 04:51:23 AM UTC 24	1278900590 ps
T514	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.3459492724	Sep 01 04:51:22 AM UTC 24	Sep 01 04:51:24 AM UTC 24	11399414 ps
T515	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1137415599	Sep 01 04:51:22 AM UTC 24	Sep 01 04:51:24 AM UTC 24	17387763 ps
T516	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.3300163505	Sep 01 04:51:21 AM UTC 24	Sep 01 04:51:24 AM UTC 24	373692074 ps
T517	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.178350587	Sep 01 04:51:22 AM UTC 24	Sep 01 04:51:24 AM UTC 24	135301371 ps
T94	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.432233334	Sep 01 04:51:22 AM UTC 24	Sep 01 04:51:24 AM UTC 24	72423589 ps
T518	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.436669287	Sep 01 04:51:20 AM UTC 24	Sep 01 04:51:24 AM UTC 24	379896991 ps
T519	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3441470205	Sep 01 04:51:22 AM UTC 24	Sep 01 04:51:25 AM UTC 24	144598411 ps
T520	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.4044556977	Sep 01 04:51:24 AM UTC 24	Sep 01 04:51:25 AM UTC 24	16042183 ps
T521	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.3481446136	Sep 01 04:51:24 AM UTC 24	Sep 01 04:51:25 AM UTC 24	46078474 ps
T522	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1650289919	Sep 01 04:51:23 AM UTC 24	Sep 01 04:51:25 AM UTC 24	27445408 ps
T523	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.411606339	Sep 01 04:51:24 AM UTC 24	Sep 01 04:51:25 AM UTC 24	86110039 ps
T524	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1817427728	Sep 01 04:51:24 AM UTC 24	Sep 01 04:51:26 AM UTC 24	78352041 ps
T525	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.570205607	Sep 01 04:51:22 AM UTC 24	Sep 01 04:51:26 AM UTC 24	263005937 ps
T526	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.3721358037	Sep 01 04:51:25 AM UTC 24	Sep 01 04:51:26 AM UTC 24	98358895 ps
T527	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1057689505	Sep 01 04:51:25 AM UTC 24	Sep 01 04:51:27 AM UTC 24	37629698 ps
T528	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.2545002662	Sep 01 04:51:23 AM UTC 24	Sep 01 04:51:27 AM UTC 24	253268433 ps
T529	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2178276677	Sep 01 04:51:25 AM UTC 24	Sep 01 04:51:27 AM UTC 24	126689148 ps
T530	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.640934152	Sep 01 04:51:26 AM UTC 24	Sep 01 04:51:28 AM UTC 24	11847713 ps
T531	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.4067843491	Sep 01 04:51:25 AM UTC 24	Sep 01 04:51:28 AM UTC 24	119591375 ps
T532	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1530771611	Sep 01 04:51:26 AM UTC 24	Sep 01 04:51:28 AM UTC 24	46326909 ps
T533	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.4085365246	Sep 01 04:51:26 AM UTC 24	Sep 01 04:51:28 AM UTC 24	13810710 ps
T534	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.610107077	Sep 01 04:51:26 AM UTC 24	Sep 01 04:51:28 AM UTC 24	14306792 ps
T535	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.431011580	Sep 01 04:51:26 AM UTC 24	Sep 01 04:51:28 AM UTC 24	58687781 ps
T536	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.562177786	Sep 01 04:51:26 AM UTC 24	Sep 01 04:51:29 AM UTC 24	950517092 ps
T537	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3479921299	Sep 01 04:51:27 AM UTC 24	Sep 01 04:51:29 AM UTC 24	42131399 ps
T538	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1803401698	Sep 01 04:51:27 AM UTC 24	Sep 01 04:51:29 AM UTC 24	20972957 ps
T539	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.904454606	Sep 01 04:51:26 AM UTC 24	Sep 01 04:51:29 AM UTC 24	178114809 ps
T540	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1867598587	Sep 01 04:51:27 AM UTC 24	Sep 01 04:51:30 AM UTC 24	113577111 ps
T541	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.1131418641	Sep 01 04:51:28 AM UTC 24	Sep 01 04:51:30 AM UTC 24	13795507 ps
T76	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.1427231406	Sep 01 04:51:28 AM UTC 24	Sep 01 04:51:30 AM UTC 24	54594716 ps
T542	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1415599819	Sep 01 04:51:29 AM UTC 24	Sep 01 04:51:30 AM UTC 24	37346869 ps
T543	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.2646478882	Sep 01 04:51:34 AM UTC 24	Sep 01 04:51:36 AM UTC 24	26259505 ps
T544	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3432663142	Sep 01 04:51:28 AM UTC 24	Sep 01 04:51:30 AM UTC 24	102874637 ps
T545	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.1756923861	Sep 01 04:51:29 AM UTC 24	Sep 01 04:51:30 AM UTC 24	159330626 ps
T546	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.1747316172	Sep 01 04:51:29 AM UTC 24	Sep 01 04:51:31 AM UTC 24	22108467 ps
T547	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.1526853619	Sep 01 04:51:27 AM UTC 24	Sep 01 04:51:31 AM UTC 24	384344807 ps
T548	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2884000499	Sep 01 04:51:29 AM UTC 24	Sep 01 04:51:31 AM UTC 24	104415536 ps
T549	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.3688907535	Sep 01 04:51:30 AM UTC 24	Sep 01 04:51:32 AM UTC 24	36477875 ps
T550	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.3638894517	Sep 01 04:51:30 AM UTC 24	Sep 01 04:51:32 AM UTC 24	26382618 ps
T551	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.330746644	Sep 01 04:51:30 AM UTC 24	Sep 01 04:51:32 AM UTC 24	45663757 ps
T552	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.877990264	Sep 01 04:51:30 AM UTC 24	Sep 01 04:51:32 AM UTC 24	19159682 ps
T553	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.3045452902	Sep 01 04:51:29 AM UTC 24	Sep 01 04:51:32 AM UTC 24	98657129 ps
T554	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3424114427	Sep 01 04:51:30 AM UTC 24	Sep 01 04:51:33 AM UTC 24	34730010 ps
T555	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.4112767824	Sep 01 04:51:31 AM UTC 24	Sep 01 04:51:33 AM UTC 24	14110905 ps
T556	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.1004073035	Sep 01 04:51:31 AM UTC 24	Sep 01 04:51:33 AM UTC 24	41218568 ps
T557	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1081029964	Sep 01 04:51:31 AM UTC 24	Sep 01 04:51:33 AM UTC 24	87791943 ps
T558	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.2773142751	Sep 01 04:51:31 AM UTC 24	Sep 01 04:51:33 AM UTC 24	15630475 ps
T559	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.3798634985	Sep 01 04:51:31 AM UTC 24	Sep 01 04:51:33 AM UTC 24	19436184 ps
T560	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.32216791	Sep 01 04:51:31 AM UTC 24	Sep 01 04:51:33 AM UTC 24	16025292 ps
T561	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.3618493518	Sep 01 04:51:31 AM UTC 24	Sep 01 04:51:33 AM UTC 24	60054588 ps
T562	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.3460119616	Sep 01 04:51:31 AM UTC 24	Sep 01 04:51:33 AM UTC 24	45004827 ps
T563	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.35130007	Sep 01 04:51:32 AM UTC 24	Sep 01 04:51:34 AM UTC 24	21050649 ps
T564	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.584202055	Sep 01 04:51:32 AM UTC 24	Sep 01 04:51:34 AM UTC 24	37980944 ps
T565	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.1467008283	Sep 01 04:51:33 AM UTC 24	Sep 01 04:51:34 AM UTC 24	13328250 ps
T566	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.356583414	Sep 01 04:51:33 AM UTC 24	Sep 01 04:51:35 AM UTC 24	28911604 ps
T567	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.319275570	Sep 01 04:51:33 AM UTC 24	Sep 01 04:51:35 AM UTC 24	16003345 ps
T568	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.3375741747	Sep 01 04:51:33 AM UTC 24	Sep 01 04:51:35 AM UTC 24	19614791 ps
T569	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.2325786448	Sep 01 04:51:34 AM UTC 24	Sep 01 04:51:36 AM UTC 24	29439866 ps
T570	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.2432561103	Sep 01 04:51:34 AM UTC 24	Sep 01 04:51:36 AM UTC 24	51810902 ps
T571	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.4137433012	Sep 01 04:51:34 AM UTC 24	Sep 01 04:51:36 AM UTC 24	34364929 ps
T572	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.34553328	Sep 01 04:51:34 AM UTC 24	Sep 01 04:51:36 AM UTC 24	14068800 ps
T573	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.1981756263	Sep 01 04:51:34 AM UTC 24	Sep 01 04:51:36 AM UTC 24	13536563 ps
T574	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.2735432511	Sep 01 04:51:34 AM UTC 24	Sep 01 04:51:36 AM UTC 24	42141403 ps
T575	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.2688096525	Sep 01 04:51:34 AM UTC 24	Sep 01 04:51:36 AM UTC 24	13825674 ps
T576	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.466310227	Sep 01 04:51:34 AM UTC 24	Sep 01 04:51:36 AM UTC 24	15873452 ps
T577	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.770925715	Sep 01 04:51:35 AM UTC 24	Sep 01 04:51:37 AM UTC 24	39805518 ps
T578	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.1727198209	Sep 01 04:51:35 AM UTC 24	Sep 01 04:51:37 AM UTC 24	12178663 ps
T579	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.60726270	Sep 01 04:51:36 AM UTC 24	Sep 01 04:51:37 AM UTC 24	68366996 ps

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all_with_rand_reset.632498812
Short name	T10
Test name
Test status
Simulation time	4663007746 ps
CPU time	53.88 seconds
Started	Sep 01 04:51:43 AM UTC 24
Finished	Sep 01 04:52:38 AM UTC 24
Peak memory	203896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=632498812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.632498812
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.786271682
Short name	T98
Test name
Test status
Simulation time	149741170674 ps
CPU time	317.48 seconds
Started	Sep 01 04:52:39 AM UTC 24
Finished	Sep 01 04:58:02 AM UTC 24
Peak memory	199608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786271682 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.786271682
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.2118335055
Short name	T1
Test name
Test status
Simulation time	961233055 ps
CPU time	1.05 seconds
Started	Sep 01 04:51:37 AM UTC 24
Finished	Sep 01 04:51:39 AM UTC 24
Peak memory	229300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118335055 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2118335055
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.2423215130
Short name	T257
Test name
Test status
Simulation time	4543336490910 ps
CPU time	5910.61 seconds
Started	Sep 01 05:04:55 AM UTC 24
Finished	Sep 01 06:44:33 AM UTC 24
Peak memory	202488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423215130 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.2423215130
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/29.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.3626100207
Short name	T55
Test name
Test status
Simulation time	639240347962 ps
CPU time	1342.89 seconds
Started	Sep 01 04:58:44 AM UTC 24
Finished	Sep 01 05:21:21 AM UTC 24
Peak memory	202456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626100207 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.3626100207
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/17.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.1571357422
Short name	T277
Test name
Test status
Simulation time	4295208031620 ps
CPU time	6745.89 seconds
Started	Sep 01 05:06:54 AM UTC 24
Finished	Sep 01 07:00:32 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571357422 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.1571357422
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/32.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.4123549837
Short name	T150
Test name
Test status
Simulation time	175222513619 ps
CPU time	662.86 seconds
Started	Sep 01 04:57:52 AM UTC 24
Finished	Sep 01 05:09:03 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123549837 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.4123549837
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/10.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.1546639599
Short name	T196
Test name
Test status
Simulation time	1222845475462 ps
CPU time	1618.57 seconds
Started	Sep 01 05:10:07 AM UTC 24
Finished	Sep 01 05:37:24 AM UTC 24
Peak memory	202484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546639599 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.1546639599
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/37.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.909784083
Short name	T64
Test name
Test status
Simulation time	249527865 ps
CPU time	2.8 seconds
Started	Sep 01 04:50:48 AM UTC 24
Finished	Sep 01 04:50:52 AM UTC 24
Peak memory	200492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909784083 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.909784083
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.565553758
Short name	T237
Test name
Test status
Simulation time	266513603480 ps
CPU time	1035.55 seconds
Started	Sep 01 04:58:10 AM UTC 24
Finished	Sep 01 05:15:38 AM UTC 24
Peak memory	202328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565553758 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.565553758
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/13.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.164687989
Short name	T241
Test name
Test status
Simulation time	1257116578726 ps
CPU time	1016.97 seconds
Started	Sep 01 05:06:22 AM UTC 24
Finished	Sep 01 05:23:30 AM UTC 24
Peak memory	202588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164687989 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.164687989
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/31.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.1163373498
Short name	T178
Test name
Test status
Simulation time	3173953167813 ps
CPU time	1947.78 seconds
Started	Sep 01 04:51:37 AM UTC 24
Finished	Sep 01 05:24:28 AM UTC 24
Peak memory	202448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163373498 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.1163373498
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.160758593
Short name	T119
Test name
Test status
Simulation time	232335654611 ps
CPU time	457.68 seconds
Started	Sep 01 04:52:09 AM UTC 24
Finished	Sep 01 04:59:54 AM UTC 24
Peak memory	199776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160758593 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.160758593
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.4078825729
Short name	T90
Test name
Test status
Simulation time	432786905 ps
CPU time	1.61 seconds
Started	Sep 01 04:51:09 AM UTC 24
Finished	Sep 01 04:51:12 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078825729 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.4078825729
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.4220845231
Short name	T147
Test name
Test status
Simulation time	203551975783 ps
CPU time	521.09 seconds
Started	Sep 01 04:57:56 AM UTC 24
Finished	Sep 01 05:06:45 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220845231 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4220845231
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/12.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.2980913138
Short name	T278
Test name
Test status
Simulation time	2095871932851 ps
CPU time	4713.52 seconds
Started	Sep 01 05:01:42 AM UTC 24
Finished	Sep 01 06:21:11 AM UTC 24
Peak memory	202448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980913138 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.2980913138
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/22.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.1291225957
Short name	T116
Test name
Test status
Simulation time	480196647306 ps
CPU time	1693.72 seconds
Started	Sep 01 04:53:11 AM UTC 24
Finished	Sep 01 05:21:43 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291225957 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.1291225957
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.3238743340
Short name	T210
Test name
Test status
Simulation time	1006224402391 ps
CPU time	921.75 seconds
Started	Sep 01 05:13:59 AM UTC 24
Finished	Sep 01 05:29:32 AM UTC 24
Peak memory	202488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238743340 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.3238743340
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/45.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.2184263998
Short name	T151
Test name
Test status
Simulation time	260309258800 ps
CPU time	489.24 seconds
Started	Sep 01 05:05:37 AM UTC 24
Finished	Sep 01 05:13:52 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184263998 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2184263998
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/31.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3280202704
Short name	T30
Test name
Test status
Simulation time	28486495 ps
CPU time	0.9 seconds
Started	Sep 01 04:50:49 AM UTC 24
Finished	Sep 01 04:50:50 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280202704 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.3280202704
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.2926632972
Short name	T45
Test name
Test status
Simulation time	1534326978177 ps
CPU time	875.19 seconds
Started	Sep 01 04:51:37 AM UTC 24
Finished	Sep 01 05:06:23 AM UTC 24
Peak memory	202448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2926632972 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.2926632972
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.3203648072
Short name	T107
Test name
Test status
Simulation time	317618196221 ps
CPU time	667.92 seconds
Started	Sep 01 04:58:19 AM UTC 24
Finished	Sep 01 05:09:35 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203648072 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3203648072
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/15.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all.2792005504
Short name	T368
Test name
Test status
Simulation time	742489929645 ps
CPU time	2837.17 seconds
Started	Sep 01 05:00:27 AM UTC 24
Finished	Sep 01 05:48:19 AM UTC 24
Peak memory	202448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792005504 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.2792005504
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/20.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.2160495147
Short name	T95
Test name
Test status
Simulation time	112685551676 ps
CPU time	243.95 seconds
Started	Sep 01 04:51:36 AM UTC 24
Finished	Sep 01 04:55:44 AM UTC 24
Peak memory	202444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160495147 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2160495147
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.2397135554
Short name	T190
Test name
Test status
Simulation time	665294143148 ps
CPU time	1405.42 seconds
Started	Sep 01 05:02:48 AM UTC 24
Finished	Sep 01 05:26:29 AM UTC 24
Peak memory	202488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397135554 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.2397135554
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/25.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.1849671225
Short name	T54
Test name
Test status
Simulation time	1664697679117 ps
CPU time	877.29 seconds
Started	Sep 01 05:05:34 AM UTC 24
Finished	Sep 01 05:20:21 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849671225 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.1849671225
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/30.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.838942534
Short name	T282
Test name
Test status
Simulation time	2228557414087 ps
CPU time	3231.86 seconds
Started	Sep 01 05:09:06 AM UTC 24
Finished	Sep 01 06:03:34 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838942534 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.838942534
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/35.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.2950698506
Short name	T356
Test name
Test status
Simulation time	382456224440 ps
CPU time	569.74 seconds
Started	Sep 01 05:34:26 AM UTC 24
Finished	Sep 01 05:44:03 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950698506 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2950698506
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/194.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.2733285581
Short name	T164
Test name
Test status
Simulation time	143895025390 ps
CPU time	348.57 seconds
Started	Sep 01 05:22:43 AM UTC 24
Finished	Sep 01 05:28:36 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733285581 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2733285581
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/106.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.1563936811
Short name	T236
Test name
Test status
Simulation time	157756273577 ps
CPU time	1822.8 seconds
Started	Sep 01 05:23:18 AM UTC 24
Finished	Sep 01 05:54:02 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563936811 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1563936811
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/111.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.704756368
Short name	T188
Test name
Test status
Simulation time	1041549320698 ps
CPU time	1042.49 seconds
Started	Sep 01 04:59:55 AM UTC 24
Finished	Sep 01 05:17:29 AM UTC 24
Peak memory	202616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704756368 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.704756368
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/19.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.1207782781
Short name	T156
Test name
Test status
Simulation time	90727668658 ps
CPU time	452.99 seconds
Started	Sep 01 05:01:47 AM UTC 24
Finished	Sep 01 05:09:26 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207782781 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1207782781
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/23.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.343079103
Short name	T239
Test name
Test status
Simulation time	441661658904 ps
CPU time	5132.78 seconds
Started	Sep 01 05:04:26 AM UTC 24
Finished	Sep 01 06:30:56 AM UTC 24
Peak memory	202524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343079103 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.343079103
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/28.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/110.rv_timer_random.4288190322
Short name	T255
Test name
Test status
Simulation time	333541407349 ps
CPU time	420.48 seconds
Started	Sep 01 05:23:17 AM UTC 24
Finished	Sep 01 05:30:23 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288190322 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.4288190322
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/110.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.1341160448
Short name	T302
Test name
Test status
Simulation time	176695810610 ps
CPU time	804.42 seconds
Started	Sep 01 05:30:34 AM UTC 24
Finished	Sep 01 05:44:09 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341160448 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1341160448
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/169.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.3612077274
Short name	T202
Test name
Test status
Simulation time	1754703513024 ps
CPU time	1307.47 seconds
Started	Sep 01 05:14:44 AM UTC 24
Finished	Sep 01 05:36:47 AM UTC 24
Peak memory	202460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612077274 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.3612077274
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.3702316333
Short name	T227
Test name
Test status
Simulation time	377374494674 ps
CPU time	1530.35 seconds
Started	Sep 01 05:15:59 AM UTC 24
Finished	Sep 01 05:41:47 AM UTC 24
Peak memory	202488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702316333 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.3702316333
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/49.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.3260582885
Short name	T199
Test name
Test status
Simulation time	1814071400808 ps
CPU time	1131.56 seconds
Started	Sep 01 04:58:02 AM UTC 24
Finished	Sep 01 05:17:06 AM UTC 24
Peak memory	202424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260582885 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.3260582885
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/12.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.1306973456
Short name	T219
Test name
Test status
Simulation time	477722930176 ps
CPU time	374.44 seconds
Started	Sep 01 05:28:37 AM UTC 24
Finished	Sep 01 05:34:56 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306973456 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1306973456
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/152.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.245446368
Short name	T319
Test name
Test status
Simulation time	324514280100 ps
CPU time	543.69 seconds
Started	Sep 01 05:30:11 AM UTC 24
Finished	Sep 01 05:39:21 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245446368 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.245446368
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/165.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.2169718055
Short name	T295
Test name
Test status
Simulation time	344968109614 ps
CPU time	529.43 seconds
Started	Sep 01 05:33:56 AM UTC 24
Finished	Sep 01 05:42:52 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169718055 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2169718055
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/189.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.1802211485
Short name	T132
Test name
Test status
Simulation time	225900008541 ps
CPU time	173.28 seconds
Started	Sep 01 05:00:30 AM UTC 24
Finished	Sep 01 05:03:26 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802211485 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1802211485
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/21.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.1258570286
Short name	T162
Test name
Test status
Simulation time	643674619541 ps
CPU time	1220.9 seconds
Started	Sep 01 05:14:22 AM UTC 24
Finished	Sep 01 05:34:56 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258570286 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.1258570286
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/46.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.1247451978
Short name	T343
Test name
Test status
Simulation time	282507519739 ps
CPU time	166.67 seconds
Started	Sep 01 05:22:19 AM UTC 24
Finished	Sep 01 05:25:08 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247451978 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1247451978
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/101.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.3829427309
Short name	T189
Test name
Test status
Simulation time	158931379677 ps
CPU time	450.03 seconds
Started	Sep 01 05:28:15 AM UTC 24
Finished	Sep 01 05:35:51 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829427309 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3829427309
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/149.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.2401885027
Short name	T256
Test name
Test status
Simulation time	184067656670 ps
CPU time	922.46 seconds
Started	Sep 01 05:31:24 AM UTC 24
Finished	Sep 01 05:46:59 AM UTC 24
Peak memory	202548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401885027 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2401885027
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/171.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.2333800842
Short name	T167
Test name
Test status
Simulation time	650869378134 ps
CPU time	936.37 seconds
Started	Sep 01 05:12:26 AM UTC 24
Finished	Sep 01 05:28:14 AM UTC 24
Peak memory	202448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333800842 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.2333800842
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/41.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.2640029578
Short name	T204
Test name
Test status
Simulation time	105425409676 ps
CPU time	391.47 seconds
Started	Sep 01 05:17:20 AM UTC 24
Finished	Sep 01 05:23:57 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640029578 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2640029578
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/63.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.1043538424
Short name	T20
Test name
Test status
Simulation time	126487217275 ps
CPU time	82.27 seconds
Started	Sep 01 04:51:37 AM UTC 24
Finished	Sep 01 04:53:01 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043538424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1043538424
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.2613172489
Short name	T370
Test name
Test status
Simulation time	113964836543 ps
CPU time	520.89 seconds
Started	Sep 01 05:34:01 AM UTC 24
Finished	Sep 01 05:42:49 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613172489 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2613172489
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/191.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.820561056
Short name	T177
Test name
Test status
Simulation time	249900573487 ps
CPU time	648.21 seconds
Started	Sep 01 05:04:05 AM UTC 24
Finished	Sep 01 05:15:01 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820561056 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.820561056
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/28.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.1833641732
Short name	T122
Test name
Test status
Simulation time	105129933085 ps
CPU time	337.25 seconds
Started	Sep 01 04:52:06 AM UTC 24
Finished	Sep 01 04:57:49 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833641732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1833641732
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.4019621964
Short name	T163
Test name
Test status
Simulation time	265123330370 ps
CPU time	500.24 seconds
Started	Sep 01 05:10:43 AM UTC 24
Finished	Sep 01 05:19:10 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019621964 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.4019621964
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/39.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.2429738062
Short name	T317
Test name
Test status
Simulation time	213561323795 ps
CPU time	148.41 seconds
Started	Sep 01 05:11:05 AM UTC 24
Finished	Sep 01 05:13:36 AM UTC 24
Peak memory	199852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429738062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2429738062
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/39.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.3002746041
Short name	T77
Test name
Test status
Simulation time	125114841 ps
CPU time	0.95 seconds
Started	Sep 01 04:50:50 AM UTC 24
Finished	Sep 01 04:50:52 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002746041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.3002746041
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.2777034625
Short name	T128
Test name
Test status
Simulation time	418495347543 ps
CPU time	321.78 seconds
Started	Sep 01 04:57:50 AM UTC 24
Finished	Sep 01 05:03:16 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777034625 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2777034625
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/10.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.3425675795
Short name	T335
Test name
Test status
Simulation time	420110549966 ps
CPU time	464.78 seconds
Started	Sep 01 05:23:33 AM UTC 24
Finished	Sep 01 05:31:24 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425675795 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3425675795
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/113.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.3644309464
Short name	T330
Test name
Test status
Simulation time	818953870000 ps
CPU time	604.8 seconds
Started	Sep 01 05:24:29 AM UTC 24
Finished	Sep 01 05:34:41 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644309464 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3644309464
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/122.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.1439767254
Short name	T198
Test name
Test status
Simulation time	293198828219 ps
CPU time	842.22 seconds
Started	Sep 01 05:26:17 AM UTC 24
Finished	Sep 01 05:40:30 AM UTC 24
Peak memory	199784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439767254 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1439767254
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/136.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.2499436905
Short name	T353
Test name
Test status
Simulation time	146674356983 ps
CPU time	2199.22 seconds
Started	Sep 01 05:27:17 AM UTC 24
Finished	Sep 01 06:04:21 AM UTC 24
Peak memory	202544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499436905 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2499436905
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/142.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.2546710596
Short name	T249
Test name
Test status
Simulation time	166911752092 ps
CPU time	675.08 seconds
Started	Sep 01 05:27:46 AM UTC 24
Finished	Sep 01 05:39:09 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546710596 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2546710596
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/145.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.157325272
Short name	T110
Test name
Test status
Simulation time	343082815169 ps
CPU time	136.81 seconds
Started	Sep 01 04:58:22 AM UTC 24
Finished	Sep 01 05:00:42 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157325272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.157325272
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/15.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.158091832
Short name	T333
Test name
Test status
Simulation time	299299366287 ps
CPU time	2986.57 seconds
Started	Sep 01 05:28:53 AM UTC 24
Finished	Sep 01 06:19:14 AM UTC 24
Peak memory	202612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158091832 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.158091832
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/155.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.453866249
Short name	T379
Test name
Test status
Simulation time	801895140435 ps
CPU time	876.73 seconds
Started	Sep 01 05:30:16 AM UTC 24
Finished	Sep 01 05:45:03 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453866249 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.453866249
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/167.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.1166283032
Short name	T205
Test name
Test status
Simulation time	205938108212 ps
CPU time	1008.83 seconds
Started	Sep 01 05:32:10 AM UTC 24
Finished	Sep 01 05:49:12 AM UTC 24
Peak memory	202440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166283032 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1166283032
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/177.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.2389073078
Short name	T280
Test name
Test status
Simulation time	137194809709 ps
CPU time	613.09 seconds
Started	Sep 01 05:02:52 AM UTC 24
Finished	Sep 01 05:13:13 AM UTC 24
Peak memory	199680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389073078 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2389073078
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/26.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.3626407397
Short name	T279
Test name
Test status
Simulation time	1523147489656 ps
CPU time	587.49 seconds
Started	Sep 01 05:13:37 AM UTC 24
Finished	Sep 01 05:23:32 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626407397 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.3626407397
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.278669541
Short name	T288
Test name
Test status
Simulation time	217035976627 ps
CPU time	374.73 seconds
Started	Sep 01 05:16:56 AM UTC 24
Finished	Sep 01 05:23:16 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278669541 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.278669541
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/58.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.1018016060
Short name	T42
Test name
Test status
Simulation time	912175690557 ps
CPU time	517.46 seconds
Started	Sep 01 04:57:01 AM UTC 24
Finished	Sep 01 05:05:46 AM UTC 24
Peak memory	202332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018016060 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.1018016060
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.2400533246
Short name	T299
Test name
Test status
Simulation time	180034084580 ps
CPU time	1822.02 seconds
Started	Sep 01 05:17:29 AM UTC 24
Finished	Sep 01 05:48:14 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400533246 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2400533246
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/66.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.2324441048
Short name	T218
Test name
Test status
Simulation time	219869628780 ps
CPU time	286.38 seconds
Started	Sep 01 05:17:39 AM UTC 24
Finished	Sep 01 05:22:30 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324441048 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2324441048
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/67.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.2970658044
Short name	T222
Test name
Test status
Simulation time	586526185466 ps
CPU time	548.17 seconds
Started	Sep 01 05:19:16 AM UTC 24
Finished	Sep 01 05:28:30 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970658044 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2970658044
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/78.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1600752194
Short name	T93
Test name
Test status
Simulation time	238866514 ps
CPU time	1.7 seconds
Started	Sep 01 04:51:20 AM UTC 24
Finished	Sep 01 04:51:22 AM UTC 24
Peak memory	198848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600752194 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.1600752194
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.4293058374
Short name	T372
Test name
Test status
Simulation time	1743545339664 ps
CPU time	1231.72 seconds
Started	Sep 01 05:22:30 AM UTC 24
Finished	Sep 01 05:43:16 AM UTC 24
Peak memory	202440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293058374 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.4293058374
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/104.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.63066753
Short name	T169
Test name
Test status
Simulation time	109877319288 ps
CPU time	678.54 seconds
Started	Sep 01 05:23:38 AM UTC 24
Finished	Sep 01 05:35:05 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63066753 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.63066753
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/114.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.1309039109
Short name	T251
Test name
Test status
Simulation time	255527601422 ps
CPU time	343.06 seconds
Started	Sep 01 05:23:48 AM UTC 24
Finished	Sep 01 05:29:36 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309039109 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1309039109
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/115.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.159679541
Short name	T161
Test name
Test status
Simulation time	750267536147 ps
CPU time	398.32 seconds
Started	Sep 01 05:25:57 AM UTC 24
Finished	Sep 01 05:32:41 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159679541 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.159679541
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/134.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.2434643058
Short name	T338
Test name
Test status
Simulation time	78278833157 ps
CPU time	199.4 seconds
Started	Sep 01 05:26:08 AM UTC 24
Finished	Sep 01 05:29:31 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434643058 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2434643058
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/135.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.3341022967
Short name	T168
Test name
Test status
Simulation time	449384818922 ps
CPU time	386.23 seconds
Started	Sep 01 05:26:30 AM UTC 24
Finished	Sep 01 05:33:02 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341022967 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3341022967
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/138.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.688837190
Short name	T369
Test name
Test status
Simulation time	123269352631 ps
CPU time	243.58 seconds
Started	Sep 01 05:27:19 AM UTC 24
Finished	Sep 01 05:31:26 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688837190 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.688837190
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/143.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.1010811951
Short name	T324
Test name
Test status
Simulation time	275750889102 ps
CPU time	932.27 seconds
Started	Sep 01 05:28:08 AM UTC 24
Finished	Sep 01 05:43:52 AM UTC 24
Peak memory	202544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010811951 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1010811951
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/146.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.4005095012
Short name	T371
Test name
Test status
Simulation time	59374000945 ps
CPU time	101.62 seconds
Started	Sep 01 05:28:26 AM UTC 24
Finished	Sep 01 05:30:09 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005095012 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.4005095012
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/150.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.2164291365
Short name	T357
Test name
Test status
Simulation time	77955413840 ps
CPU time	44.2 seconds
Started	Sep 01 05:28:31 AM UTC 24
Finished	Sep 01 05:29:17 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164291365 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2164291365
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/151.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.1211077609
Short name	T334
Test name
Test status
Simulation time	445985660012 ps
CPU time	422.66 seconds
Started	Sep 01 05:29:37 AM UTC 24
Finished	Sep 01 05:36:46 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211077609 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1211077609
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/164.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.1582525035
Short name	T176
Test name
Test status
Simulation time	162808519074 ps
CPU time	163.17 seconds
Started	Sep 01 05:31:26 AM UTC 24
Finished	Sep 01 05:34:12 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582525035 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1582525035
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/172.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.2377642502
Short name	T124
Test name
Test status
Simulation time	342337722511 ps
CPU time	956.93 seconds
Started	Sep 01 04:58:47 AM UTC 24
Finished	Sep 01 05:14:55 AM UTC 24
Peak memory	199776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377642502 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2377642502
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/18.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.174062788
Short name	T378
Test name
Test status
Simulation time	173015486033 ps
CPU time	389.93 seconds
Started	Sep 01 05:33:37 AM UTC 24
Finished	Sep 01 05:40:12 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174062788 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.174062788
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/186.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.103637376
Short name	T297
Test name
Test status
Simulation time	955105890990 ps
CPU time	770.06 seconds
Started	Sep 01 05:33:51 AM UTC 24
Finished	Sep 01 05:46:51 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103637376 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.103637376
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/188.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.3208841925
Short name	T39
Test name
Test status
Simulation time	468082712965 ps
CPU time	224.31 seconds
Started	Sep 01 05:01:24 AM UTC 24
Finished	Sep 01 05:05:12 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208841925 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.3208841925
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.2998738840
Short name	T108
Test name
Test status
Simulation time	121910015600 ps
CPU time	530.22 seconds
Started	Sep 01 05:02:28 AM UTC 24
Finished	Sep 01 05:11:25 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998738840 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2998738840
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/25.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.2289915007
Short name	T298
Test name
Test status
Simulation time	303393957165 ps
CPU time	544.83 seconds
Started	Sep 01 05:04:36 AM UTC 24
Finished	Sep 01 05:13:47 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289915007 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.2289915007
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.2927781192
Short name	T217
Test name
Test status
Simulation time	693965205022 ps
CPU time	1652.97 seconds
Started	Sep 01 05:04:59 AM UTC 24
Finished	Sep 01 05:32:51 AM UTC 24
Peak memory	202484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927781192 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2927781192
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/30.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.4098613397
Short name	T182
Test name
Test status
Simulation time	559699470714 ps
CPU time	298.25 seconds
Started	Sep 01 05:06:24 AM UTC 24
Finished	Sep 01 05:11:26 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098613397 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4098613397
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/32.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.1304579613
Short name	T271
Test name
Test status
Simulation time	103182174951 ps
CPU time	209.57 seconds
Started	Sep 01 05:07:44 AM UTC 24
Finished	Sep 01 05:11:18 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304579613 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1304579613
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/34.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.3614920418
Short name	T230
Test name
Test status
Simulation time	157152730519 ps
CPU time	1433.91 seconds
Started	Sep 01 05:09:55 AM UTC 24
Finished	Sep 01 05:34:05 AM UTC 24
Peak memory	202620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614920418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3614920418
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/37.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.881964644
Short name	T200
Test name
Test status
Simulation time	244104101442 ps
CPU time	232.03 seconds
Started	Sep 01 05:14:15 AM UTC 24
Finished	Sep 01 05:18:10 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881964644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.881964644
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/46.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.1650712977
Short name	T300
Test name
Test status
Simulation time	53797670598 ps
CPU time	139.95 seconds
Started	Sep 01 05:19:21 AM UTC 24
Finished	Sep 01 05:21:43 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650712977 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1650712977
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/79.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.635229304
Short name	T18
Test name
Test status
Simulation time	53226858 ps
CPU time	0.64 seconds
Started	Sep 01 04:50:47 AM UTC 24
Finished	Sep 01 04:50:49 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635229304 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.635229304
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1481441075
Short name	T31
Test name
Test status
Simulation time	38914788 ps
CPU time	0.93 seconds
Started	Sep 01 04:50:51 AM UTC 24
Finished	Sep 01 04:50:53 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1481441075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_cs r_mem_rw_with_rand_reset.1481441075
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.3691033468
Short name	T19
Test name
Test status
Simulation time	32075739 ps
CPU time	0.72 seconds
Started	Sep 01 04:50:48 AM UTC 24
Finished	Sep 01 04:50:50 AM UTC 24
Peak memory	198680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691033468 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3691033468
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.4146143815
Short name	T462
Test name
Test status
Simulation time	22596765 ps
CPU time	0.65 seconds
Started	Sep 01 04:50:46 AM UTC 24
Finished	Sep 01 04:50:48 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146143815 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.4146143815
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.3172345449
Short name	T461
Test name
Test status
Simulation time	102536567 ps
CPU time	1.62 seconds
Started	Sep 01 04:50:43 AM UTC 24
Finished	Sep 01 04:50:45 AM UTC 24
Peak memory	200164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172345449 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3172345449
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2186193828
Short name	T15
Test name
Test status
Simulation time	278989683 ps
CPU time	1.33 seconds
Started	Sep 01 04:50:44 AM UTC 24
Finished	Sep 01 04:50:46 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186193828 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.2186193828
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.901817548
Short name	T65
Test name
Test status
Simulation time	116457955 ps
CPU time	0.83 seconds
Started	Sep 01 04:50:56 AM UTC 24
Finished	Sep 01 04:50:58 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901817548 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.901817548
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3568901285
Short name	T32
Test name
Test status
Simulation time	128200999 ps
CPU time	1.88 seconds
Started	Sep 01 04:50:55 AM UTC 24
Finished	Sep 01 04:50:58 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568901285 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.3568901285
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1981008085
Short name	T85
Test name
Test status
Simulation time	19571075 ps
CPU time	0.7 seconds
Started	Sep 01 04:50:54 AM UTC 24
Finished	Sep 01 04:50:56 AM UTC 24
Peak memory	199040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981008085 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.1981008085
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4073278869
Short name	T33
Test name
Test status
Simulation time	65804493 ps
CPU time	0.91 seconds
Started	Sep 01 04:50:56 AM UTC 24
Finished	Sep 01 04:50:58 AM UTC 24
Peak memory	198960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4073278869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_cs r_mem_rw_with_rand_reset.4073278869
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.2657935054
Short name	T86
Test name
Test status
Simulation time	53674199 ps
CPU time	0.66 seconds
Started	Sep 01 04:50:55 AM UTC 24
Finished	Sep 01 04:50:57 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657935054 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2657935054
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.568708770
Short name	T463
Test name
Test status
Simulation time	29568754 ps
CPU time	0.66 seconds
Started	Sep 01 04:50:53 AM UTC 24
Finished	Sep 01 04:50:54 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568708770 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.568708770
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3550858869
Short name	T66
Test name
Test status
Simulation time	19174085 ps
CPU time	0.88 seconds
Started	Sep 01 04:50:56 AM UTC 24
Finished	Sep 01 04:50:58 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550858869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.3550858869
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.813431188
Short name	T464
Test name
Test status
Simulation time	367031064 ps
CPU time	2.61 seconds
Started	Sep 01 04:50:52 AM UTC 24
Finished	Sep 01 04:50:55 AM UTC 24
Peak memory	200676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=813431188 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.813431188
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3065016880
Short name	T16
Test name
Test status
Simulation time	244526555 ps
CPU time	1.27 seconds
Started	Sep 01 04:50:53 AM UTC 24
Finished	Sep 01 04:50:55 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065016880 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.3065016880
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2802078676
Short name	T502
Test name
Test status
Simulation time	102947943 ps
CPU time	0.9 seconds
Started	Sep 01 04:51:18 AM UTC 24
Finished	Sep 01 04:51:20 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2802078676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_c sr_mem_rw_with_rand_reset.2802078676
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.3151133511
Short name	T494
Test name
Test status
Simulation time	28736782 ps
CPU time	0.69 seconds
Started	Sep 01 04:51:17 AM UTC 24
Finished	Sep 01 04:51:19 AM UTC 24
Peak memory	199040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151133511 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3151133511
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.781766430
Short name	T495
Test name
Test status
Simulation time	17398443 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:17 AM UTC 24
Finished	Sep 01 04:51:19 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781766430 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.781766430
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/10.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4194419356
Short name	T496
Test name
Test status
Simulation time	137440925 ps
CPU time	0.68 seconds
Started	Sep 01 04:51:17 AM UTC 24
Finished	Sep 01 04:51:19 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194419356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.4194419356
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.3163092375
Short name	T49
Test name
Test status
Simulation time	126216365 ps
CPU time	1.39 seconds
Started	Sep 01 04:51:17 AM UTC 24
Finished	Sep 01 04:51:19 AM UTC 24
Peak memory	199096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163092375 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3163092375
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.554790378
Short name	T497
Test name
Test status
Simulation time	96652083 ps
CPU time	0.96 seconds
Started	Sep 01 04:51:17 AM UTC 24
Finished	Sep 01 04:51:19 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554790378 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.554790378
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3007763688
Short name	T508
Test name
Test status
Simulation time	199795409 ps
CPU time	1.1 seconds
Started	Sep 01 04:51:20 AM UTC 24
Finished	Sep 01 04:51:22 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3007763688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_c sr_mem_rw_with_rand_reset.3007763688
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.694362810
Short name	T499
Test name
Test status
Simulation time	36071650 ps
CPU time	0.66 seconds
Started	Sep 01 04:51:18 AM UTC 24
Finished	Sep 01 04:51:20 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694362810 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.694362810
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.1104329456
Short name	T501
Test name
Test status
Simulation time	62007694 ps
CPU time	0.67 seconds
Started	Sep 01 04:51:18 AM UTC 24
Finished	Sep 01 04:51:20 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104329456 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1104329456
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/11.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2999520500
Short name	T506
Test name
Test status
Simulation time	16053067 ps
CPU time	0.8 seconds
Started	Sep 01 04:51:20 AM UTC 24
Finished	Sep 01 04:51:21 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999520500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.2999520500
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.888175186
Short name	T509
Test name
Test status
Simulation time	152031594 ps
CPU time	2.44 seconds
Started	Sep 01 04:51:18 AM UTC 24
Finished	Sep 01 04:51:22 AM UTC 24
Peak memory	200684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888175186 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.888175186
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1746437659
Short name	T503
Test name
Test status
Simulation time	85328561 ps
CPU time	1.34 seconds
Started	Sep 01 04:51:18 AM UTC 24
Finished	Sep 01 04:51:21 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746437659 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.1746437659
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2189341666
Short name	T511
Test name
Test status
Simulation time	60742705 ps
CPU time	1.19 seconds
Started	Sep 01 04:51:20 AM UTC 24
Finished	Sep 01 04:51:22 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2189341666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_c sr_mem_rw_with_rand_reset.2189341666
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.608410370
Short name	T507
Test name
Test status
Simulation time	33491633 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:20 AM UTC 24
Finished	Sep 01 04:51:21 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608410370 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.608410370
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.2424863101
Short name	T504
Test name
Test status
Simulation time	25071464 ps
CPU time	0.68 seconds
Started	Sep 01 04:51:20 AM UTC 24
Finished	Sep 01 04:51:21 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424863101 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2424863101
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/12.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.232771279
Short name	T510
Test name
Test status
Simulation time	37387459 ps
CPU time	0.95 seconds
Started	Sep 01 04:51:20 AM UTC 24
Finished	Sep 01 04:51:22 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232771279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.232771279
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.436669287
Short name	T518
Test name
Test status
Simulation time	379896991 ps
CPU time	3.85 seconds
Started	Sep 01 04:51:20 AM UTC 24
Finished	Sep 01 04:51:24 AM UTC 24
Peak memory	200884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436669287 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.436669287
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3441470205
Short name	T519
Test name
Test status
Simulation time	144598411 ps
CPU time	1.83 seconds
Started	Sep 01 04:51:22 AM UTC 24
Finished	Sep 01 04:51:25 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3441470205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_c sr_mem_rw_with_rand_reset.3441470205
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.2955545496
Short name	T75
Test name
Test status
Simulation time	18056767 ps
CPU time	0.64 seconds
Started	Sep 01 04:51:21 AM UTC 24
Finished	Sep 01 04:51:23 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955545496 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2955545496
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.1353923978
Short name	T512
Test name
Test status
Simulation time	11665163 ps
CPU time	0.62 seconds
Started	Sep 01 04:51:21 AM UTC 24
Finished	Sep 01 04:51:23 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353923978 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1353923978
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/13.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3826496827
Short name	T513
Test name
Test status
Simulation time	26382530 ps
CPU time	0.8 seconds
Started	Sep 01 04:51:21 AM UTC 24
Finished	Sep 01 04:51:23 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826496827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.3826496827
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.3300163505
Short name	T516
Test name
Test status
Simulation time	373692074 ps
CPU time	2.26 seconds
Started	Sep 01 04:51:21 AM UTC 24
Finished	Sep 01 04:51:24 AM UTC 24
Peak memory	200752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300163505 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3300163505
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2767270031
Short name	T92
Test name
Test status
Simulation time	1278900590 ps
CPU time	1.18 seconds
Started	Sep 01 04:51:21 AM UTC 24
Finished	Sep 01 04:51:23 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767270031 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.2767270031
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1650289919
Short name	T522
Test name
Test status
Simulation time	27445408 ps
CPU time	0.86 seconds
Started	Sep 01 04:51:23 AM UTC 24
Finished	Sep 01 04:51:25 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1650289919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_c sr_mem_rw_with_rand_reset.1650289919
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1137415599
Short name	T515
Test name
Test status
Simulation time	17387763 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:22 AM UTC 24
Finished	Sep 01 04:51:24 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137415599 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1137415599
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.3459492724
Short name	T514
Test name
Test status
Simulation time	11399414 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:22 AM UTC 24
Finished	Sep 01 04:51:24 AM UTC 24
Peak memory	198844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459492724 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3459492724
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/14.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.178350587
Short name	T517
Test name
Test status
Simulation time	135301371 ps
CPU time	0.96 seconds
Started	Sep 01 04:51:22 AM UTC 24
Finished	Sep 01 04:51:24 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178350587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.178350587
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.570205607
Short name	T525
Test name
Test status
Simulation time	263005937 ps
CPU time	2.54 seconds
Started	Sep 01 04:51:22 AM UTC 24
Finished	Sep 01 04:51:26 AM UTC 24
Peak memory	202700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570205607 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.570205607
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.432233334
Short name	T94
Test name
Test status
Simulation time	72423589 ps
CPU time	1.25 seconds
Started	Sep 01 04:51:22 AM UTC 24
Finished	Sep 01 04:51:24 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432233334 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.432233334
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1057689505
Short name	T527
Test name
Test status
Simulation time	37629698 ps
CPU time	1.07 seconds
Started	Sep 01 04:51:25 AM UTC 24
Finished	Sep 01 04:51:27 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1057689505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_c sr_mem_rw_with_rand_reset.1057689505
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.3481446136
Short name	T521
Test name
Test status
Simulation time	46078474 ps
CPU time	0.67 seconds
Started	Sep 01 04:51:24 AM UTC 24
Finished	Sep 01 04:51:25 AM UTC 24
Peak memory	198848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481446136 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3481446136
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.4044556977
Short name	T520
Test name
Test status
Simulation time	16042183 ps
CPU time	0.68 seconds
Started	Sep 01 04:51:24 AM UTC 24
Finished	Sep 01 04:51:25 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044556977 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.4044556977
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/15.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.411606339
Short name	T523
Test name
Test status
Simulation time	86110039 ps
CPU time	0.82 seconds
Started	Sep 01 04:51:24 AM UTC 24
Finished	Sep 01 04:51:25 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411606339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.411606339
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.2545002662
Short name	T528
Test name
Test status
Simulation time	253268433 ps
CPU time	2.7 seconds
Started	Sep 01 04:51:23 AM UTC 24
Finished	Sep 01 04:51:27 AM UTC 24
Peak memory	200740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545002662 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2545002662
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1817427728
Short name	T524
Test name
Test status
Simulation time	78352041 ps
CPU time	1.16 seconds
Started	Sep 01 04:51:24 AM UTC 24
Finished	Sep 01 04:51:26 AM UTC 24
Peak memory	199084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817427728 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.1817427728
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.431011580
Short name	T535
Test name
Test status
Simulation time	58687781 ps
CPU time	0.87 seconds
Started	Sep 01 04:51:26 AM UTC 24
Finished	Sep 01 04:51:28 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=431011580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_cs r_mem_rw_with_rand_reset.431011580
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.640934152
Short name	T530
Test name
Test status
Simulation time	11847713 ps
CPU time	0.66 seconds
Started	Sep 01 04:51:26 AM UTC 24
Finished	Sep 01 04:51:28 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640934152 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.640934152
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.3721358037
Short name	T526
Test name
Test status
Simulation time	98358895 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:25 AM UTC 24
Finished	Sep 01 04:51:26 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721358037 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3721358037
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/16.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1530771611
Short name	T532
Test name
Test status
Simulation time	46326909 ps
CPU time	0.8 seconds
Started	Sep 01 04:51:26 AM UTC 24
Finished	Sep 01 04:51:28 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530771611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.1530771611
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.4067843491
Short name	T531
Test name
Test status
Simulation time	119591375 ps
CPU time	1.83 seconds
Started	Sep 01 04:51:25 AM UTC 24
Finished	Sep 01 04:51:28 AM UTC 24
Peak memory	201144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067843491 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.4067843491
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2178276677
Short name	T529
Test name
Test status
Simulation time	126689148 ps
CPU time	1.57 seconds
Started	Sep 01 04:51:25 AM UTC 24
Finished	Sep 01 04:51:27 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178276677 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.2178276677
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1803401698
Short name	T538
Test name
Test status
Simulation time	20972957 ps
CPU time	0.79 seconds
Started	Sep 01 04:51:27 AM UTC 24
Finished	Sep 01 04:51:29 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1803401698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_c sr_mem_rw_with_rand_reset.1803401698
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.610107077
Short name	T534
Test name
Test status
Simulation time	14306792 ps
CPU time	0.63 seconds
Started	Sep 01 04:51:26 AM UTC 24
Finished	Sep 01 04:51:28 AM UTC 24
Peak memory	199040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610107077 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.610107077
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.4085365246
Short name	T533
Test name
Test status
Simulation time	13810710 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:26 AM UTC 24
Finished	Sep 01 04:51:28 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085365246 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.4085365246
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/17.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3479921299
Short name	T537
Test name
Test status
Simulation time	42131399 ps
CPU time	0.73 seconds
Started	Sep 01 04:51:27 AM UTC 24
Finished	Sep 01 04:51:29 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479921299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.3479921299
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.904454606
Short name	T539
Test name
Test status
Simulation time	178114809 ps
CPU time	2.08 seconds
Started	Sep 01 04:51:26 AM UTC 24
Finished	Sep 01 04:51:29 AM UTC 24
Peak memory	200680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904454606 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.904454606
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.562177786
Short name	T536
Test name
Test status
Simulation time	950517092 ps
CPU time	1.58 seconds
Started	Sep 01 04:51:26 AM UTC 24
Finished	Sep 01 04:51:29 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562177786 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.562177786
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1415599819
Short name	T542
Test name
Test status
Simulation time	37346869 ps
CPU time	0.75 seconds
Started	Sep 01 04:51:29 AM UTC 24
Finished	Sep 01 04:51:30 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1415599819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_c sr_mem_rw_with_rand_reset.1415599819
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.1427231406
Short name	T76
Test name
Test status
Simulation time	54594716 ps
CPU time	0.68 seconds
Started	Sep 01 04:51:28 AM UTC 24
Finished	Sep 01 04:51:30 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427231406 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1427231406
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.1131418641
Short name	T541
Test name
Test status
Simulation time	13795507 ps
CPU time	0.64 seconds
Started	Sep 01 04:51:28 AM UTC 24
Finished	Sep 01 04:51:30 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131418641 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1131418641
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/18.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3432663142
Short name	T544
Test name
Test status
Simulation time	102874637 ps
CPU time	0.83 seconds
Started	Sep 01 04:51:28 AM UTC 24
Finished	Sep 01 04:51:30 AM UTC 24
Peak memory	198900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432663142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.3432663142
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.1526853619
Short name	T547
Test name
Test status
Simulation time	384344807 ps
CPU time	2.47 seconds
Started	Sep 01 04:51:27 AM UTC 24
Finished	Sep 01 04:51:31 AM UTC 24
Peak memory	200680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526853619 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1526853619
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1867598587
Short name	T540
Test name
Test status
Simulation time	113577111 ps
CPU time	1.61 seconds
Started	Sep 01 04:51:27 AM UTC 24
Finished	Sep 01 04:51:30 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867598587 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.1867598587
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3424114427
Short name	T554
Test name
Test status
Simulation time	34730010 ps
CPU time	1.61 seconds
Started	Sep 01 04:51:30 AM UTC 24
Finished	Sep 01 04:51:33 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3424114427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_c sr_mem_rw_with_rand_reset.3424114427
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.1747316172
Short name	T546
Test name
Test status
Simulation time	22108467 ps
CPU time	0.67 seconds
Started	Sep 01 04:51:29 AM UTC 24
Finished	Sep 01 04:51:31 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747316172 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1747316172
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.1756923861
Short name	T545
Test name
Test status
Simulation time	159330626 ps
CPU time	0.71 seconds
Started	Sep 01 04:51:29 AM UTC 24
Finished	Sep 01 04:51:30 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756923861 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1756923861
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/19.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.877990264
Short name	T552
Test name
Test status
Simulation time	19159682 ps
CPU time	0.9 seconds
Started	Sep 01 04:51:30 AM UTC 24
Finished	Sep 01 04:51:32 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877990264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.877990264
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.3045452902
Short name	T553
Test name
Test status
Simulation time	98657129 ps
CPU time	2.32 seconds
Started	Sep 01 04:51:29 AM UTC 24
Finished	Sep 01 04:51:32 AM UTC 24
Peak memory	200680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045452902 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3045452902
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2884000499
Short name	T548
Test name
Test status
Simulation time	104415536 ps
CPU time	1.23 seconds
Started	Sep 01 04:51:29 AM UTC 24
Finished	Sep 01 04:51:31 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884000499 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.2884000499
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1336426418
Short name	T69
Test name
Test status
Simulation time	17985921 ps
CPU time	0.97 seconds
Started	Sep 01 04:51:01 AM UTC 24
Finished	Sep 01 04:51:03 AM UTC 24
Peak memory	199040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336426418 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.1336426418
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.283058712
Short name	T468
Test name
Test status
Simulation time	61911268 ps
CPU time	2.6 seconds
Started	Sep 01 04:51:01 AM UTC 24
Finished	Sep 01 04:51:04 AM UTC 24
Peak memory	200680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283058712 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.283058712
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.4116271350
Short name	T67
Test name
Test status
Simulation time	58188265 ps
CPU time	0.71 seconds
Started	Sep 01 04:50:58 AM UTC 24
Finished	Sep 01 04:51:00 AM UTC 24
Peak memory	199036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116271350 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.4116271350
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.989011089
Short name	T466
Test name
Test status
Simulation time	57674095 ps
CPU time	0.93 seconds
Started	Sep 01 04:51:01 AM UTC 24
Finished	Sep 01 04:51:03 AM UTC 24
Peak memory	198844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=989011089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr _mem_rw_with_rand_reset.989011089
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.1033906329
Short name	T35
Test name
Test status
Simulation time	59421442 ps
CPU time	0.71 seconds
Started	Sep 01 04:50:59 AM UTC 24
Finished	Sep 01 04:51:01 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033906329 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1033906329
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.3299659168
Short name	T465
Test name
Test status
Simulation time	34266011 ps
CPU time	0.62 seconds
Started	Sep 01 04:50:58 AM UTC 24
Finished	Sep 01 04:51:00 AM UTC 24
Peak memory	198604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299659168 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3299659168
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4049957524
Short name	T68
Test name
Test status
Simulation time	58884255 ps
CPU time	0.86 seconds
Started	Sep 01 04:51:01 AM UTC 24
Finished	Sep 01 04:51:03 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049957524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.4049957524
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.64400810
Short name	T34
Test name
Test status
Simulation time	578056191 ps
CPU time	2.79 seconds
Started	Sep 01 04:50:57 AM UTC 24
Finished	Sep 01 04:51:01 AM UTC 24
Peak memory	200752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64400810 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.64400810
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3745131698
Short name	T17
Test name
Test status
Simulation time	168599799 ps
CPU time	0.97 seconds
Started	Sep 01 04:50:58 AM UTC 24
Finished	Sep 01 04:51:00 AM UTC 24
Peak memory	198824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745131698 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.3745131698
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.3638894517
Short name	T550
Test name
Test status
Simulation time	26382618 ps
CPU time	0.68 seconds
Started	Sep 01 04:51:30 AM UTC 24
Finished	Sep 01 04:51:32 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638894517 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3638894517
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/20.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.3688907535
Short name	T549
Test name
Test status
Simulation time	36477875 ps
CPU time	0.6 seconds
Started	Sep 01 04:51:30 AM UTC 24
Finished	Sep 01 04:51:32 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688907535 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3688907535
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/21.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.330746644
Short name	T551
Test name
Test status
Simulation time	45663757 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:30 AM UTC 24
Finished	Sep 01 04:51:32 AM UTC 24
Peak memory	198900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330746644 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.330746644
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/22.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.4112767824
Short name	T555
Test name
Test status
Simulation time	14110905 ps
CPU time	0.64 seconds
Started	Sep 01 04:51:31 AM UTC 24
Finished	Sep 01 04:51:33 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112767824 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.4112767824
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/23.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.1004073035
Short name	T556
Test name
Test status
Simulation time	41218568 ps
CPU time	0.67 seconds
Started	Sep 01 04:51:31 AM UTC 24
Finished	Sep 01 04:51:33 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004073035 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1004073035
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/24.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.1081029964
Short name	T557
Test name
Test status
Simulation time	87791943 ps
CPU time	0.64 seconds
Started	Sep 01 04:51:31 AM UTC 24
Finished	Sep 01 04:51:33 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081029964 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1081029964
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/25.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.3798634985
Short name	T559
Test name
Test status
Simulation time	19436184 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:31 AM UTC 24
Finished	Sep 01 04:51:33 AM UTC 24
Peak memory	198900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798634985 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3798634985
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/26.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.32216791
Short name	T560
Test name
Test status
Simulation time	16025292 ps
CPU time	0.63 seconds
Started	Sep 01 04:51:31 AM UTC 24
Finished	Sep 01 04:51:33 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32216791 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.32216791
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/27.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.2773142751
Short name	T558
Test name
Test status
Simulation time	15630475 ps
CPU time	0.63 seconds
Started	Sep 01 04:51:31 AM UTC 24
Finished	Sep 01 04:51:33 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773142751 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2773142751
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/28.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.3460119616
Short name	T562
Test name
Test status
Simulation time	45004827 ps
CPU time	0.62 seconds
Started	Sep 01 04:51:31 AM UTC 24
Finished	Sep 01 04:51:33 AM UTC 24
Peak memory	198948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460119616 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3460119616
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/29.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.811928955
Short name	T71
Test name
Test status
Simulation time	44041253 ps
CPU time	0.86 seconds
Started	Sep 01 04:51:04 AM UTC 24
Finished	Sep 01 04:51:06 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811928955 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.811928955
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.320115735
Short name	T470
Test name
Test status
Simulation time	101302333 ps
CPU time	1.75 seconds
Started	Sep 01 04:51:03 AM UTC 24
Finished	Sep 01 04:51:06 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320115735 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.320115735
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2378488284
Short name	T70
Test name
Test status
Simulation time	148094501 ps
CPU time	0.67 seconds
Started	Sep 01 04:51:03 AM UTC 24
Finished	Sep 01 04:51:05 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378488284 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.2378488284
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2074414749
Short name	T473
Test name
Test status
Simulation time	50266300 ps
CPU time	1.19 seconds
Started	Sep 01 04:51:06 AM UTC 24
Finished	Sep 01 04:51:08 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2074414749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_cs r_mem_rw_with_rand_reset.2074414749
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.303841517
Short name	T469
Test name
Test status
Simulation time	13925448 ps
CPU time	0.66 seconds
Started	Sep 01 04:51:03 AM UTC 24
Finished	Sep 01 04:51:05 AM UTC 24
Peak memory	198952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303841517 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.303841517
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.3717472561
Short name	T467
Test name
Test status
Simulation time	12666798 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:02 AM UTC 24
Finished	Sep 01 04:51:04 AM UTC 24
Peak memory	198804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717472561 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3717472561
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.915205279
Short name	T78
Test name
Test status
Simulation time	20365472 ps
CPU time	0.98 seconds
Started	Sep 01 04:51:05 AM UTC 24
Finished	Sep 01 04:51:07 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915205279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.915205279
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.1805151262
Short name	T47
Test name
Test status
Simulation time	151992681 ps
CPU time	3.11 seconds
Started	Sep 01 04:51:01 AM UTC 24
Finished	Sep 01 04:51:05 AM UTC 24
Peak memory	202728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805151262 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1805151262
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1563764455
Short name	T88
Test name
Test status
Simulation time	117771322 ps
CPU time	1.56 seconds
Started	Sep 01 04:51:02 AM UTC 24
Finished	Sep 01 04:51:05 AM UTC 24
Peak memory	198836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563764455 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.1563764455
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.3618493518
Short name	T561
Test name
Test status
Simulation time	60054588 ps
CPU time	0.62 seconds
Started	Sep 01 04:51:31 AM UTC 24
Finished	Sep 01 04:51:33 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618493518 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3618493518
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/30.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.584202055
Short name	T564
Test name
Test status
Simulation time	37980944 ps
CPU time	0.59 seconds
Started	Sep 01 04:51:32 AM UTC 24
Finished	Sep 01 04:51:34 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584202055 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.584202055
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/31.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.35130007
Short name	T563
Test name
Test status
Simulation time	21050649 ps
CPU time	0.59 seconds
Started	Sep 01 04:51:32 AM UTC 24
Finished	Sep 01 04:51:34 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35130007 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.35130007
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/32.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.1467008283
Short name	T565
Test name
Test status
Simulation time	13328250 ps
CPU time	0.61 seconds
Started	Sep 01 04:51:33 AM UTC 24
Finished	Sep 01 04:51:34 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467008283 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1467008283
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/33.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.356583414
Short name	T566
Test name
Test status
Simulation time	28911604 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:33 AM UTC 24
Finished	Sep 01 04:51:35 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356583414 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.356583414
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/34.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.3375741747
Short name	T568
Test name
Test status
Simulation time	19614791 ps
CPU time	0.66 seconds
Started	Sep 01 04:51:33 AM UTC 24
Finished	Sep 01 04:51:35 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375741747 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3375741747
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/35.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.319275570
Short name	T567
Test name
Test status
Simulation time	16003345 ps
CPU time	0.62 seconds
Started	Sep 01 04:51:33 AM UTC 24
Finished	Sep 01 04:51:35 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319275570 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.319275570
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/36.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.2432561103
Short name	T570
Test name
Test status
Simulation time	51810902 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:34 AM UTC 24
Finished	Sep 01 04:51:36 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432561103 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2432561103
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/37.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.34553328
Short name	T572
Test name
Test status
Simulation time	14068800 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:34 AM UTC 24
Finished	Sep 01 04:51:36 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34553328 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.34553328
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/38.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.4137433012
Short name	T571
Test name
Test status
Simulation time	34364929 ps
CPU time	0.68 seconds
Started	Sep 01 04:51:34 AM UTC 24
Finished	Sep 01 04:51:36 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137433012 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4137433012
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/39.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2771013193
Short name	T72
Test name
Test status
Simulation time	33299097 ps
CPU time	0.98 seconds
Started	Sep 01 04:51:08 AM UTC 24
Finished	Sep 01 04:51:10 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771013193 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.2771013193
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3921326364
Short name	T475
Test name
Test status
Simulation time	412042603 ps
CPU time	4.14 seconds
Started	Sep 01 04:51:07 AM UTC 24
Finished	Sep 01 04:51:12 AM UTC 24
Peak memory	200932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921326364 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.3921326364
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.934456346
Short name	T472
Test name
Test status
Simulation time	186262848 ps
CPU time	0.74 seconds
Started	Sep 01 04:51:06 AM UTC 24
Finished	Sep 01 04:51:07 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934456346 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.934456346
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.864854622
Short name	T37
Test name
Test status
Simulation time	58854443 ps
CPU time	0.74 seconds
Started	Sep 01 04:51:08 AM UTC 24
Finished	Sep 01 04:51:10 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=864854622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr _mem_rw_with_rand_reset.864854622
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.2184978117
Short name	T48
Test name
Test status
Simulation time	14074289 ps
CPU time	0.71 seconds
Started	Sep 01 04:51:07 AM UTC 24
Finished	Sep 01 04:51:08 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184978117 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2184978117
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.1387560376
Short name	T471
Test name
Test status
Simulation time	64082192 ps
CPU time	0.67 seconds
Started	Sep 01 04:51:06 AM UTC 24
Finished	Sep 01 04:51:07 AM UTC 24
Peak memory	198844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387560376 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1387560376
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2635391251
Short name	T79
Test name
Test status
Simulation time	100605421 ps
CPU time	0.71 seconds
Started	Sep 01 04:51:08 AM UTC 24
Finished	Sep 01 04:51:10 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635391251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.2635391251
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.3814469882
Short name	T36
Test name
Test status
Simulation time	284801514 ps
CPU time	1.22 seconds
Started	Sep 01 04:51:06 AM UTC 24
Finished	Sep 01 04:51:08 AM UTC 24
Peak memory	199100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814469882 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3814469882
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1278480832
Short name	T89
Test name
Test status
Simulation time	196433814 ps
CPU time	1.63 seconds
Started	Sep 01 04:51:06 AM UTC 24
Finished	Sep 01 04:51:08 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278480832 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.1278480832
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.1981756263
Short name	T573
Test name
Test status
Simulation time	13536563 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:34 AM UTC 24
Finished	Sep 01 04:51:36 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981756263 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1981756263
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/40.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.3650453056
Short name	T505
Test name
Test status
Simulation time	35713503 ps
CPU time	0.62 seconds
Started	Sep 01 04:51:34 AM UTC 24
Finished	Sep 01 04:51:36 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650453056 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3650453056
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/41.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.2735432511
Short name	T574
Test name
Test status
Simulation time	42141403 ps
CPU time	0.64 seconds
Started	Sep 01 04:51:34 AM UTC 24
Finished	Sep 01 04:51:36 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735432511 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2735432511
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/42.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.2646478882
Short name	T543
Test name
Test status
Simulation time	26259505 ps
CPU time	0.69 seconds
Started	Sep 01 04:51:34 AM UTC 24
Finished	Sep 01 04:51:36 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646478882 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2646478882
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/43.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.2325786448
Short name	T569
Test name
Test status
Simulation time	29439866 ps
CPU time	0.64 seconds
Started	Sep 01 04:51:34 AM UTC 24
Finished	Sep 01 04:51:36 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325786448 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2325786448
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/44.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.466310227
Short name	T576
Test name
Test status
Simulation time	15873452 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:34 AM UTC 24
Finished	Sep 01 04:51:36 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466310227 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.466310227
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/45.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.2688096525
Short name	T575
Test name
Test status
Simulation time	13825674 ps
CPU time	0.64 seconds
Started	Sep 01 04:51:34 AM UTC 24
Finished	Sep 01 04:51:36 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688096525 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2688096525
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/46.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.770925715
Short name	T577
Test name
Test status
Simulation time	39805518 ps
CPU time	0.64 seconds
Started	Sep 01 04:51:35 AM UTC 24
Finished	Sep 01 04:51:37 AM UTC 24
Peak memory	198964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770925715 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.770925715
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/47.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.1727198209
Short name	T578
Test name
Test status
Simulation time	12178663 ps
CPU time	0.67 seconds
Started	Sep 01 04:51:35 AM UTC 24
Finished	Sep 01 04:51:37 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727198209 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1727198209
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/48.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.60726270
Short name	T579
Test name
Test status
Simulation time	68366996 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:36 AM UTC 24
Finished	Sep 01 04:51:37 AM UTC 24
Peak memory	198968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60726270 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.60726270
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/49.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2967921464
Short name	T479
Test name
Test status
Simulation time	21476502 ps
CPU time	1.23 seconds
Started	Sep 01 04:51:10 AM UTC 24
Finished	Sep 01 04:51:13 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2967921464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_cs r_mem_rw_with_rand_reset.2967921464
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.3590417408
Short name	T73
Test name
Test status
Simulation time	13317466 ps
CPU time	0.63 seconds
Started	Sep 01 04:51:09 AM UTC 24
Finished	Sep 01 04:51:11 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590417408 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3590417408
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.3650190695
Short name	T474
Test name
Test status
Simulation time	19200303 ps
CPU time	0.65 seconds
Started	Sep 01 04:51:09 AM UTC 24
Finished	Sep 01 04:51:11 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650190695 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3650190695
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/5.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2636954894
Short name	T80
Test name
Test status
Simulation time	82200362 ps
CPU time	0.97 seconds
Started	Sep 01 04:51:09 AM UTC 24
Finished	Sep 01 04:51:11 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636954894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.2636954894
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.978483093
Short name	T477
Test name
Test status
Simulation time	159039826 ps
CPU time	3.04 seconds
Started	Sep 01 04:51:08 AM UTC 24
Finished	Sep 01 04:51:12 AM UTC 24
Peak memory	200748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978483093 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.978483093
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.388343071
Short name	T482
Test name
Test status
Simulation time	95153447 ps
CPU time	1.4 seconds
Started	Sep 01 04:51:12 AM UTC 24
Finished	Sep 01 04:51:14 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=388343071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr _mem_rw_with_rand_reset.388343071
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.2594099464
Short name	T481
Test name
Test status
Simulation time	17293715 ps
CPU time	0.66 seconds
Started	Sep 01 04:51:12 AM UTC 24
Finished	Sep 01 04:51:13 AM UTC 24
Peak memory	199044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594099464 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2594099464
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.801062007
Short name	T476
Test name
Test status
Simulation time	39613745 ps
CPU time	0.67 seconds
Started	Sep 01 04:51:11 AM UTC 24
Finished	Sep 01 04:51:12 AM UTC 24
Peak memory	198972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801062007 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.801062007
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/6.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2977851755
Short name	T81
Test name
Test status
Simulation time	40841064 ps
CPU time	0.72 seconds
Started	Sep 01 04:51:12 AM UTC 24
Finished	Sep 01 04:51:14 AM UTC 24
Peak memory	198912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977851755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.2977851755
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.654027316
Short name	T480
Test name
Test status
Simulation time	577419256 ps
CPU time	1.8 seconds
Started	Sep 01 04:51:11 AM UTC 24
Finished	Sep 01 04:51:13 AM UTC 24
Peak memory	199100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654027316 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.654027316
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.462935862
Short name	T478
Test name
Test status
Simulation time	90872005 ps
CPU time	0.98 seconds
Started	Sep 01 04:51:11 AM UTC 24
Finished	Sep 01 04:51:13 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462935862 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.462935862
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.484257991
Short name	T484
Test name
Test status
Simulation time	27154088 ps
CPU time	0.85 seconds
Started	Sep 01 04:51:13 AM UTC 24
Finished	Sep 01 04:51:15 AM UTC 24
Peak memory	198844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=484257991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr _mem_rw_with_rand_reset.484257991
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.3732328394
Short name	T74
Test name
Test status
Simulation time	80108582 ps
CPU time	0.71 seconds
Started	Sep 01 04:51:13 AM UTC 24
Finished	Sep 01 04:51:15 AM UTC 24
Peak memory	199032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732328394 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3732328394
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.1783167884
Short name	T483
Test name
Test status
Simulation time	12957081 ps
CPU time	0.63 seconds
Started	Sep 01 04:51:13 AM UTC 24
Finished	Sep 01 04:51:15 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783167884 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1783167884
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/7.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2077950377
Short name	T82
Test name
Test status
Simulation time	132609777 ps
CPU time	0.91 seconds
Started	Sep 01 04:51:13 AM UTC 24
Finished	Sep 01 04:51:15 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077950377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.2077950377
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.3063017918
Short name	T486
Test name
Test status
Simulation time	253054836 ps
CPU time	2.75 seconds
Started	Sep 01 04:51:12 AM UTC 24
Finished	Sep 01 04:51:16 AM UTC 24
Peak memory	200756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063017918 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3063017918
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1512590563
Short name	T485
Test name
Test status
Simulation time	295187936 ps
CPU time	1.76 seconds
Started	Sep 01 04:51:13 AM UTC 24
Finished	Sep 01 04:51:16 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512590563 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.1512590563
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2283734096
Short name	T493
Test name
Test status
Simulation time	327634021 ps
CPU time	0.94 seconds
Started	Sep 01 04:51:16 AM UTC 24
Finished	Sep 01 04:51:18 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2283734096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_cs r_mem_rw_with_rand_reset.2283734096
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.3473871533
Short name	T488
Test name
Test status
Simulation time	14594541 ps
CPU time	0.7 seconds
Started	Sep 01 04:51:14 AM UTC 24
Finished	Sep 01 04:51:16 AM UTC 24
Peak memory	198908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473871533 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3473871533
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.2131365773
Short name	T487
Test name
Test status
Simulation time	16082798 ps
CPU time	0.67 seconds
Started	Sep 01 04:51:14 AM UTC 24
Finished	Sep 01 04:51:16 AM UTC 24
Peak memory	198904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131365773 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2131365773
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/8.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.189122549
Short name	T83
Test name
Test status
Simulation time	23941977 ps
CPU time	0.78 seconds
Started	Sep 01 04:51:16 AM UTC 24
Finished	Sep 01 04:51:17 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189122549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.189122549
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.600325323
Short name	T489
Test name
Test status
Simulation time	34840989 ps
CPU time	1.79 seconds
Started	Sep 01 04:51:13 AM UTC 24
Finished	Sep 01 04:51:16 AM UTC 24
Peak memory	201148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600325323 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.600325323
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.958683502
Short name	T490
Test name
Test status
Simulation time	94898373 ps
CPU time	1.35 seconds
Started	Sep 01 04:51:14 AM UTC 24
Finished	Sep 01 04:51:17 AM UTC 24
Peak memory	199104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958683502 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.958683502
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1796634970
Short name	T498
Test name
Test status
Simulation time	28303335 ps
CPU time	1.29 seconds
Started	Sep 01 04:51:17 AM UTC 24
Finished	Sep 01 04:51:19 AM UTC 24
Peak memory	198976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1796634970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_cs r_mem_rw_with_rand_reset.1796634970
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.2837952358
Short name	T492
Test name
Test status
Simulation time	14312928 ps
CPU time	0.7 seconds
Started	Sep 01 04:51:16 AM UTC 24
Finished	Sep 01 04:51:17 AM UTC 24
Peak memory	198888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837952358 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2837952358
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.1712088062
Short name	T491
Test name
Test status
Simulation time	14626066 ps
CPU time	0.71 seconds
Started	Sep 01 04:51:16 AM UTC 24
Finished	Sep 01 04:51:17 AM UTC 24
Peak memory	198800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712088062 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1712088062
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/9.rv_timer_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1518700433
Short name	T84
Test name
Test status
Simulation time	18931177 ps
CPU time	0.68 seconds
Started	Sep 01 04:51:17 AM UTC 24
Finished	Sep 01 04:51:19 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518700433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.1518700433
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.1028075903
Short name	T500
Test name
Test status
Simulation time	63128760 ps
CPU time	3.13 seconds
Started	Sep 01 04:51:16 AM UTC 24
Finished	Sep 01 04:51:20 AM UTC 24
Peak memory	200680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028075903 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1028075903
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1869141124
Short name	T91
Test name
Test status
Simulation time	173341109 ps
CPU time	0.99 seconds
Started	Sep 01 04:51:16 AM UTC 24
Finished	Sep 01 04:51:18 AM UTC 24
Peak memory	199108 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869141124 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.1869141124
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.2185673784
Short name	T118
Test name
Test status
Simulation time	221830202388 ps
CPU time	389.3 seconds
Started	Sep 01 04:51:36 AM UTC 24
Finished	Sep 01 04:58:11 AM UTC 24
Peak memory	202584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185673784 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.2185673784
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.1968189344
Short name	T4
Test name
Test status
Simulation time	5627327334 ps
CPU time	11.74 seconds
Started	Sep 01 04:51:36 AM UTC 24
Finished	Sep 01 04:51:49 AM UTC 24
Peak memory	199600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968189344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1968189344
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all_with_rand_reset.453526836
Short name	T5
Test name
Test status
Simulation time	2506468332 ps
CPU time	29.58 seconds
Started	Sep 01 04:51:37 AM UTC 24
Finished	Sep 01 04:52:08 AM UTC 24
Peak memory	204032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=453526836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.453526836
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.2063999204
Short name	T332
Test name
Test status
Simulation time	7849948094675 ps
CPU time	2245.89 seconds
Started	Sep 01 04:51:37 AM UTC 24
Finished	Sep 01 05:29:30 AM UTC 24
Peak memory	202324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063999204 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.2063999204
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.2054501185
Short name	T8
Test name
Test status
Simulation time	123945085615 ps
CPU time	52.63 seconds
Started	Sep 01 04:51:37 AM UTC 24
Finished	Sep 01 04:52:31 AM UTC 24
Peak memory	199848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054501185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2054501185
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.239787670
Short name	T233
Test name
Test status
Simulation time	242197190295 ps
CPU time	1039.72 seconds
Started	Sep 01 04:51:37 AM UTC 24
Finished	Sep 01 05:09:10 AM UTC 24
Peak memory	202400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239787670 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.239787670
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.1005445082
Short name	T11
Test name
Test status
Simulation time	42360557101 ps
CPU time	90.48 seconds
Started	Sep 01 04:51:37 AM UTC 24
Finished	Sep 01 04:53:10 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005445082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1005445082
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.563648299
Short name	T2
Test name
Test status
Simulation time	42438154 ps
CPU time	0.91 seconds
Started	Sep 01 04:51:38 AM UTC 24
Finished	Sep 01 04:51:40 AM UTC 24
Peak memory	230928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563648299 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.563648299
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.1900631553
Short name	T61
Test name
Test status
Simulation time	47178967440 ps
CPU time	77.21 seconds
Started	Sep 01 04:57:51 AM UTC 24
Finished	Sep 01 04:59:10 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900631553 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.1900631553
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.2554412398
Short name	T392
Test name
Test status
Simulation time	172173074456 ps
CPU time	163.38 seconds
Started	Sep 01 04:57:51 AM UTC 24
Finished	Sep 01 05:00:37 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554412398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2554412398
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/10.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.42371763
Short name	T390
Test name
Test status
Simulation time	282534569 ps
CPU time	1.39 seconds
Started	Sep 01 04:57:52 AM UTC 24
Finished	Sep 01 04:57:54 AM UTC 24
Peak memory	198880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42371763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.42371763
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/10.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all_with_rand_reset.1387731160
Short name	T24
Test name
Test status
Simulation time	5805395523 ps
CPU time	35.92 seconds
Started	Sep 01 04:57:52 AM UTC 24
Finished	Sep 01 04:58:29 AM UTC 24
Peak memory	203820 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1387731160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.rv_timer_stress_all_with_rand_reset.1387731160
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/10.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.448321622
Short name	T352
Test name
Test status
Simulation time	179849976996 ps
CPU time	548.23 seconds
Started	Sep 01 05:22:08 AM UTC 24
Finished	Sep 01 05:31:23 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448321622 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.448321622
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/100.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.3473008250
Short name	T314
Test name
Test status
Simulation time	108799103871 ps
CPU time	146.76 seconds
Started	Sep 01 05:22:22 AM UTC 24
Finished	Sep 01 05:24:51 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3473008250 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3473008250
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/102.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.3507104042
Short name	T289
Test name
Test status
Simulation time	271230595098 ps
CPU time	238.98 seconds
Started	Sep 01 05:22:26 AM UTC 24
Finished	Sep 01 05:26:29 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507104042 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3507104042
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/103.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.2684920273
Short name	T269
Test name
Test status
Simulation time	111883670645 ps
CPU time	333.57 seconds
Started	Sep 01 05:22:35 AM UTC 24
Finished	Sep 01 05:28:13 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684920273 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2684920273
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/105.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.482293156
Short name	T449
Test name
Test status
Simulation time	187305224603 ps
CPU time	166.75 seconds
Started	Sep 01 05:22:50 AM UTC 24
Finished	Sep 01 05:25:40 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482293156 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.482293156
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/107.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.55645374
Short name	T293
Test name
Test status
Simulation time	377762796696 ps
CPU time	513.72 seconds
Started	Sep 01 05:23:14 AM UTC 24
Finished	Sep 01 05:31:55 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55645374 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.55645374
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/108.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.3031876375
Short name	T303
Test name
Test status
Simulation time	140113167119 ps
CPU time	230.45 seconds
Started	Sep 01 05:23:17 AM UTC 24
Finished	Sep 01 05:27:11 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031876375 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3031876375
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/109.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.252072418
Short name	T158
Test name
Test status
Simulation time	1067312518734 ps
CPU time	907.61 seconds
Started	Sep 01 04:57:54 AM UTC 24
Finished	Sep 01 05:13:13 AM UTC 24
Peak memory	202464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252072418 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.252072418
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.3641319214
Short name	T398
Test name
Test status
Simulation time	296089094084 ps
CPU time	270.77 seconds
Started	Sep 01 04:57:53 AM UTC 24
Finished	Sep 01 05:02:27 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641319214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3641319214
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/11.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.903621092
Short name	T117
Test name
Test status
Simulation time	376751559116 ps
CPU time	416.19 seconds
Started	Sep 01 04:57:52 AM UTC 24
Finished	Sep 01 05:04:54 AM UTC 24
Peak memory	199640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903621092 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.903621092
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/11.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.1957441561
Short name	T152
Test name
Test status
Simulation time	50928596082 ps
CPU time	124.13 seconds
Started	Sep 01 04:57:55 AM UTC 24
Finished	Sep 01 05:00:02 AM UTC 24
Peak memory	199852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957441561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1957441561
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/11.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.3144420383
Short name	T292
Test name
Test status
Simulation time	395669937841 ps
CPU time	1344.43 seconds
Started	Sep 01 04:57:55 AM UTC 24
Finished	Sep 01 05:20:34 AM UTC 24
Peak memory	202448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144420383 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.3144420383
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/11.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all_with_rand_reset.1807853247
Short name	T26
Test name
Test status
Simulation time	3896764789 ps
CPU time	41.3 seconds
Started	Sep 01 04:57:55 AM UTC 24
Finished	Sep 01 04:58:38 AM UTC 24
Peak memory	203960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1807853247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.rv_timer_stress_all_with_rand_reset.1807853247
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/11.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.800042577
Short name	T170
Test name
Test status
Simulation time	485542832285 ps
CPU time	1149.75 seconds
Started	Sep 01 05:23:31 AM UTC 24
Finished	Sep 01 05:42:55 AM UTC 24
Peak memory	202584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800042577 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.800042577
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/112.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.4063723846
Short name	T385
Test name
Test status
Simulation time	230474945649 ps
CPU time	629.36 seconds
Started	Sep 01 05:23:52 AM UTC 24
Finished	Sep 01 05:34:29 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063723846 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.4063723846
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/116.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.3101059186
Short name	T448
Test name
Test status
Simulation time	24160870628 ps
CPU time	83.23 seconds
Started	Sep 01 05:23:57 AM UTC 24
Finished	Sep 01 05:25:22 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101059186 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3101059186
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/117.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.1753890386
Short name	T358
Test name
Test status
Simulation time	138911787092 ps
CPU time	390.5 seconds
Started	Sep 01 05:23:57 AM UTC 24
Finished	Sep 01 05:30:33 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753890386 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1753890386
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/118.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.154805590
Short name	T375
Test name
Test status
Simulation time	116537534921 ps
CPU time	3161.75 seconds
Started	Sep 01 05:24:03 AM UTC 24
Finished	Sep 01 06:17:22 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154805590 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.154805590
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/119.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.691807116
Short name	T201
Test name
Test status
Simulation time	242488131229 ps
CPU time	667.68 seconds
Started	Sep 01 04:58:00 AM UTC 24
Finished	Sep 01 05:09:16 AM UTC 24
Peak memory	199588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691807116 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.691807116
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.1731674629
Short name	T403
Test name
Test status
Simulation time	153467019808 ps
CPU time	348.31 seconds
Started	Sep 01 04:57:58 AM UTC 24
Finished	Sep 01 05:03:52 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731674629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1731674629
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/12.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.191740172
Short name	T129
Test name
Test status
Simulation time	157423725511 ps
CPU time	132.86 seconds
Started	Sep 01 04:58:00 AM UTC 24
Finished	Sep 01 05:00:15 AM UTC 24
Peak memory	199596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191740172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.191740172
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/12.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.3782351854
Short name	T450
Test name
Test status
Simulation time	525708555994 ps
CPU time	160.65 seconds
Started	Sep 01 05:24:06 AM UTC 24
Finished	Sep 01 05:26:49 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782351854 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3782351854
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/120.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.3680955864
Short name	T341
Test name
Test status
Simulation time	244131186081 ps
CPU time	1730.95 seconds
Started	Sep 01 05:24:26 AM UTC 24
Finished	Sep 01 05:53:36 AM UTC 24
Peak memory	202544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680955864 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3680955864
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/121.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.1739891763
Short name	T195
Test name
Test status
Simulation time	167268382296 ps
CPU time	409.42 seconds
Started	Sep 01 05:24:36 AM UTC 24
Finished	Sep 01 05:31:31 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739891763 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1739891763
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/123.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.2877241312
Short name	T208
Test name
Test status
Simulation time	317831679426 ps
CPU time	1289.82 seconds
Started	Sep 01 05:24:36 AM UTC 24
Finished	Sep 01 05:46:21 AM UTC 24
Peak memory	202448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877241312 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2877241312
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/124.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.492142520
Short name	T267
Test name
Test status
Simulation time	49388883251 ps
CPU time	140.86 seconds
Started	Sep 01 05:24:52 AM UTC 24
Finished	Sep 01 05:27:16 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492142520 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.492142520
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/125.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.3050316398
Short name	T206
Test name
Test status
Simulation time	71623690495 ps
CPU time	414.42 seconds
Started	Sep 01 05:25:09 AM UTC 24
Finished	Sep 01 05:32:09 AM UTC 24
Peak memory	199840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050316398 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3050316398
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/126.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.1806188005
Short name	T350
Test name
Test status
Simulation time	300151003115 ps
CPU time	212.14 seconds
Started	Sep 01 05:25:23 AM UTC 24
Finished	Sep 01 05:28:59 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806188005 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1806188005
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/127.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.1753709121
Short name	T367
Test name
Test status
Simulation time	21313919227 ps
CPU time	50.29 seconds
Started	Sep 01 05:25:24 AM UTC 24
Finished	Sep 01 05:26:16 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753709121 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1753709121
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/128.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.649316759
Short name	T451
Test name
Test status
Simulation time	127628790193 ps
CPU time	82.27 seconds
Started	Sep 01 05:25:26 AM UTC 24
Finished	Sep 01 05:26:51 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649316759 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.649316759
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/129.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.625687752
Short name	T155
Test name
Test status
Simulation time	693781659320 ps
CPU time	407.25 seconds
Started	Sep 01 04:58:06 AM UTC 24
Finished	Sep 01 05:04:59 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625687752 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.625687752
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.3016893792
Short name	T96
Test name
Test status
Simulation time	126488141755 ps
CPU time	198.22 seconds
Started	Sep 01 04:58:02 AM UTC 24
Finished	Sep 01 05:01:23 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016893792 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3016893792
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/13.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.113002276
Short name	T125
Test name
Test status
Simulation time	99107121286 ps
CPU time	126.43 seconds
Started	Sep 01 04:58:06 AM UTC 24
Finished	Sep 01 05:00:15 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113002276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.113002276
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/13.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all_with_rand_reset.3009585948
Short name	T25
Test name
Test status
Simulation time	1386367825 ps
CPU time	21.89 seconds
Started	Sep 01 04:58:07 AM UTC 24
Finished	Sep 01 04:58:31 AM UTC 24
Peak memory	201812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3009585948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 13.rv_timer_stress_all_with_rand_reset.3009585948
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/13.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.1975519775
Short name	T453
Test name
Test status
Simulation time	347863348050 ps
CPU time	163.6 seconds
Started	Sep 01 05:25:39 AM UTC 24
Finished	Sep 01 05:28:25 AM UTC 24
Peak memory	199716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975519775 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1975519775
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/130.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.2017276612
Short name	T340
Test name
Test status
Simulation time	3242579454 ps
CPU time	5.92 seconds
Started	Sep 01 05:25:41 AM UTC 24
Finished	Sep 01 05:25:48 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017276612 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2017276612
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/131.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.2733899208
Short name	T373
Test name
Test status
Simulation time	95523695532 ps
CPU time	754.61 seconds
Started	Sep 01 05:25:49 AM UTC 24
Finished	Sep 01 05:38:32 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733899208 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2733899208
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/132.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.3692031732
Short name	T376
Test name
Test status
Simulation time	563538793849 ps
CPU time	662.36 seconds
Started	Sep 01 05:25:51 AM UTC 24
Finished	Sep 01 05:37:02 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692031732 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3692031732
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/133.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.2370634608
Short name	T214
Test name
Test status
Simulation time	1736712477197 ps
CPU time	584.89 seconds
Started	Sep 01 05:26:29 AM UTC 24
Finished	Sep 01 05:36:21 AM UTC 24
Peak memory	199904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370634608 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2370634608
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/137.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.2225202404
Short name	T286
Test name
Test status
Simulation time	21753855865 ps
CPU time	76.19 seconds
Started	Sep 01 05:26:50 AM UTC 24
Finished	Sep 01 05:28:08 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225202404 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2225202404
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/139.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.2053991842
Short name	T354
Test name
Test status
Simulation time	735138193375 ps
CPU time	1726.49 seconds
Started	Sep 01 04:58:13 AM UTC 24
Finished	Sep 01 05:27:18 AM UTC 24
Peak memory	202452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053991842 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.2053991842
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.3425836845
Short name	T401
Test name
Test status
Simulation time	179123504270 ps
CPU time	264.19 seconds
Started	Sep 01 04:58:12 AM UTC 24
Finished	Sep 01 05:02:40 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425836845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3425836845
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/14.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.2299449459
Short name	T146
Test name
Test status
Simulation time	119671233087 ps
CPU time	305.33 seconds
Started	Sep 01 04:58:12 AM UTC 24
Finished	Sep 01 05:03:21 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299449459 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2299449459
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/14.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.4230755240
Short name	T104
Test name
Test status
Simulation time	33807985697 ps
CPU time	74.29 seconds
Started	Sep 01 04:58:13 AM UTC 24
Finished	Sep 01 04:59:29 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230755240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4230755240
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/14.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.4031135437
Short name	T50
Test name
Test status
Simulation time	66640204 ps
CPU time	0.82 seconds
Started	Sep 01 04:58:19 AM UTC 24
Finished	Sep 01 04:58:21 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031135437 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.4031135437
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/14.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.2303856707
Short name	T193
Test name
Test status
Simulation time	316141678804 ps
CPU time	378.56 seconds
Started	Sep 01 05:26:52 AM UTC 24
Finished	Sep 01 05:33:15 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303856707 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2303856707
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/140.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.3663726224
Short name	T306
Test name
Test status
Simulation time	33307593366 ps
CPU time	57.25 seconds
Started	Sep 01 05:27:12 AM UTC 24
Finished	Sep 01 05:28:11 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663726224 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3663726224
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/141.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.3001352406
Short name	T454
Test name
Test status
Simulation time	42381306117 ps
CPU time	107.51 seconds
Started	Sep 01 05:27:25 AM UTC 24
Finished	Sep 01 05:29:15 AM UTC 24
Peak memory	199460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001352406 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3001352406
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/144.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.1283984090
Short name	T191
Test name
Test status
Simulation time	132273885300 ps
CPU time	846.65 seconds
Started	Sep 01 05:28:11 AM UTC 24
Finished	Sep 01 05:42:28 AM UTC 24
Peak memory	199772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283984090 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1283984090
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/147.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.4111861941
Short name	T339
Test name
Test status
Simulation time	48112141501 ps
CPU time	382.96 seconds
Started	Sep 01 05:28:14 AM UTC 24
Finished	Sep 01 05:34:42 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111861941 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.4111861941
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/148.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.478347198
Short name	T139
Test name
Test status
Simulation time	269504258119 ps
CPU time	358.7 seconds
Started	Sep 01 04:58:21 AM UTC 24
Finished	Sep 01 05:04:25 AM UTC 24
Peak memory	199660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478347198 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.478347198
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.2509760576
Short name	T62
Test name
Test status
Simulation time	68985595411 ps
CPU time	51.76 seconds
Started	Sep 01 04:58:21 AM UTC 24
Finished	Sep 01 04:59:15 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509760576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2509760576
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/15.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.2728025817
Short name	T272
Test name
Test status
Simulation time	754779770722 ps
CPU time	2282.79 seconds
Started	Sep 01 04:58:26 AM UTC 24
Finished	Sep 01 05:36:55 AM UTC 24
Peak memory	202488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728025817 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.2728025817
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/15.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all_with_rand_reset.787445965
Short name	T27
Test name
Test status
Simulation time	4246957477 ps
CPU time	75.45 seconds
Started	Sep 01 04:58:24 AM UTC 24
Finished	Sep 01 04:59:41 AM UTC 24
Peak memory	204068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=787445965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.787445965
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/15.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.2649382195
Short name	T380
Test name
Test status
Simulation time	95003639088 ps
CPU time	1886.45 seconds
Started	Sep 01 05:28:40 AM UTC 24
Finished	Sep 01 06:00:28 AM UTC 24
Peak memory	202548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649382195 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2649382195
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/153.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.3494658743
Short name	T459
Test name
Test status
Simulation time	93224615163 ps
CPU time	1547.76 seconds
Started	Sep 01 05:28:48 AM UTC 24
Finished	Sep 01 05:54:54 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494658743 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3494658743
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/154.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.2414496851
Short name	T211
Test name
Test status
Simulation time	102296724237 ps
CPU time	291.33 seconds
Started	Sep 01 05:28:59 AM UTC 24
Finished	Sep 01 05:33:55 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414496851 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2414496851
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/156.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.585753222
Short name	T311
Test name
Test status
Simulation time	303342529391 ps
CPU time	275.27 seconds
Started	Sep 01 05:29:10 AM UTC 24
Finished	Sep 01 05:33:50 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585753222 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.585753222
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/157.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.3927433449
Short name	T296
Test name
Test status
Simulation time	965792835501 ps
CPU time	305.15 seconds
Started	Sep 01 05:29:16 AM UTC 24
Finished	Sep 01 05:34:25 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927433449 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3927433449
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/158.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.2556260280
Short name	T460
Test name
Test status
Simulation time	141855991152 ps
CPU time	1586 seconds
Started	Sep 01 05:29:18 AM UTC 24
Finished	Sep 01 05:56:03 AM UTC 24
Peak memory	202404 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556260280 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2556260280
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/159.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.1980283258
Short name	T60
Test name
Test status
Simulation time	17436192062 ps
CPU time	32.86 seconds
Started	Sep 01 04:58:30 AM UTC 24
Finished	Sep 01 04:59:04 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980283258 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.1980283258
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.1058506466
Short name	T412
Test name
Test status
Simulation time	196411753726 ps
CPU time	549.66 seconds
Started	Sep 01 04:58:27 AM UTC 24
Finished	Sep 01 05:07:44 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058506466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1058506466
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/16.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.596000554
Short name	T148
Test name
Test status
Simulation time	150311329641 ps
CPU time	191.71 seconds
Started	Sep 01 04:58:26 AM UTC 24
Finished	Sep 01 05:01:41 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596000554 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.596000554
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/16.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.1995884029
Short name	T391
Test name
Test status
Simulation time	35335683242 ps
CPU time	116.69 seconds
Started	Sep 01 04:58:30 AM UTC 24
Finished	Sep 01 05:00:29 AM UTC 24
Peak memory	199852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995884029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1995884029
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/16.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.3285157738
Short name	T212
Test name
Test status
Simulation time	764714474407 ps
CPU time	726.84 seconds
Started	Sep 01 04:58:33 AM UTC 24
Finished	Sep 01 05:10:49 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285157738 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.3285157738
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/16.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.1345256279
Short name	T362
Test name
Test status
Simulation time	1412390523865 ps
CPU time	264.11 seconds
Started	Sep 01 05:29:31 AM UTC 24
Finished	Sep 01 05:33:59 AM UTC 24
Peak memory	199904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345256279 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1345256279
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/160.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.3295791747
Short name	T287
Test name
Test status
Simulation time	14426128545 ps
CPU time	41.52 seconds
Started	Sep 01 05:29:32 AM UTC 24
Finished	Sep 01 05:30:15 AM UTC 24
Peak memory	199868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295791747 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3295791747
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/161.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.1844419167
Short name	T455
Test name
Test status
Simulation time	372299111677 ps
CPU time	264.47 seconds
Started	Sep 01 05:29:32 AM UTC 24
Finished	Sep 01 05:34:00 AM UTC 24
Peak memory	199904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844419167 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1844419167
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/162.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.636503503
Short name	T273
Test name
Test status
Simulation time	88174092069 ps
CPU time	213.62 seconds
Started	Sep 01 05:29:33 AM UTC 24
Finished	Sep 01 05:33:10 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636503503 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.636503503
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/163.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.291662179
Short name	T216
Test name
Test status
Simulation time	141801996215 ps
CPU time	796.27 seconds
Started	Sep 01 05:30:11 AM UTC 24
Finished	Sep 01 05:43:36 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291662179 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.291662179
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/166.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.1580245717
Short name	T281
Test name
Test status
Simulation time	575358422249 ps
CPU time	313.09 seconds
Started	Sep 01 05:30:24 AM UTC 24
Finished	Sep 01 05:35:41 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580245717 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1580245717
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/168.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.486766328
Short name	T275
Test name
Test status
Simulation time	636893521282 ps
CPU time	680.95 seconds
Started	Sep 01 04:58:41 AM UTC 24
Finished	Sep 01 05:10:10 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486766328 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.486766328
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.3591115661
Short name	T59
Test name
Test status
Simulation time	9756222804 ps
CPU time	13.02 seconds
Started	Sep 01 04:58:40 AM UTC 24
Finished	Sep 01 04:58:54 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591115661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3591115661
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/17.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.2555103596
Short name	T140
Test name
Test status
Simulation time	380799992305 ps
CPU time	491.78 seconds
Started	Sep 01 04:58:37 AM UTC 24
Finished	Sep 01 05:06:55 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555103596 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2555103596
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/17.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.1391997779
Short name	T121
Test name
Test status
Simulation time	25567912297 ps
CPU time	72.82 seconds
Started	Sep 01 04:58:42 AM UTC 24
Finished	Sep 01 04:59:57 AM UTC 24
Peak memory	199916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391997779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1391997779
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/17.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.2587093852
Short name	T160
Test name
Test status
Simulation time	24105902918 ps
CPU time	153.92 seconds
Started	Sep 01 05:30:53 AM UTC 24
Finished	Sep 01 05:33:30 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587093852 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2587093852
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/170.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.3909392787
Short name	T322
Test name
Test status
Simulation time	171781696543 ps
CPU time	469.94 seconds
Started	Sep 01 05:31:27 AM UTC 24
Finished	Sep 01 05:39:23 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909392787 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3909392787
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/173.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.1635457087
Short name	T284
Test name
Test status
Simulation time	124754601168 ps
CPU time	117.64 seconds
Started	Sep 01 05:31:32 AM UTC 24
Finished	Sep 01 05:33:32 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635457087 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1635457087
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/174.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.2491743917
Short name	T345
Test name
Test status
Simulation time	88691962842 ps
CPU time	192.95 seconds
Started	Sep 01 05:31:56 AM UTC 24
Finished	Sep 01 05:35:12 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491743917 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2491743917
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/175.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.3157440625
Short name	T276
Test name
Test status
Simulation time	68009531457 ps
CPU time	93.51 seconds
Started	Sep 01 05:32:00 AM UTC 24
Finished	Sep 01 05:33:35 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157440625 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3157440625
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/176.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.1418507810
Short name	T456
Test name
Test status
Simulation time	51458545456 ps
CPU time	101.29 seconds
Started	Sep 01 05:32:41 AM UTC 24
Finished	Sep 01 05:34:25 AM UTC 24
Peak memory	199868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418507810 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1418507810
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/178.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.461854431
Short name	T359
Test name
Test status
Simulation time	269873468286 ps
CPU time	585.29 seconds
Started	Sep 01 05:32:52 AM UTC 24
Finished	Sep 01 05:42:45 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461854431 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.461854431
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/179.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.946893895
Short name	T145
Test name
Test status
Simulation time	86574478296 ps
CPU time	181.4 seconds
Started	Sep 01 04:58:55 AM UTC 24
Finished	Sep 01 05:01:59 AM UTC 24
Peak memory	199724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946893895 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.946893895
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/18.rv_timer_disabled.3574677767
Short name	T394
Test name
Test status
Simulation time	62849509447 ps
CPU time	174.61 seconds
Started	Sep 01 04:58:55 AM UTC 24
Finished	Sep 01 05:01:52 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574677767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3574677767
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/18.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.105069151
Short name	T265
Test name
Test status
Simulation time	73878284657 ps
CPU time	573.1 seconds
Started	Sep 01 04:59:06 AM UTC 24
Finished	Sep 01 05:08:46 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105069151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.105069151
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/18.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.425712430
Short name	T301
Test name
Test status
Simulation time	562435678795 ps
CPU time	620.29 seconds
Started	Sep 01 05:33:03 AM UTC 24
Finished	Sep 01 05:43:31 AM UTC 24
Peak memory	199872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425712430 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.425712430
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/180.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.3057073988
Short name	T336
Test name
Test status
Simulation time	678280723773 ps
CPU time	1704.88 seconds
Started	Sep 01 05:33:10 AM UTC 24
Finished	Sep 01 06:01:56 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057073988 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3057073988
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/181.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.1696300107
Short name	T458
Test name
Test status
Simulation time	142467415835 ps
CPU time	518.22 seconds
Started	Sep 01 05:33:11 AM UTC 24
Finished	Sep 01 05:41:57 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696300107 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1696300107
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/182.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.3669257782
Short name	T384
Test name
Test status
Simulation time	306181642094 ps
CPU time	545.41 seconds
Started	Sep 01 05:33:16 AM UTC 24
Finished	Sep 01 05:42:29 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669257782 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3669257782
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/183.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.3258190654
Short name	T355
Test name
Test status
Simulation time	100493600979 ps
CPU time	99.92 seconds
Started	Sep 01 05:33:30 AM UTC 24
Finished	Sep 01 05:35:13 AM UTC 24
Peak memory	199868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258190654 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3258190654
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/184.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.4123716906
Short name	T225
Test name
Test status
Simulation time	72081486601 ps
CPU time	282.47 seconds
Started	Sep 01 05:33:32 AM UTC 24
Finished	Sep 01 05:38:19 AM UTC 24
Peak memory	199868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123716906 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.4123716906
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/185.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.1250484958
Short name	T252
Test name
Test status
Simulation time	2178982304469 ps
CPU time	700.16 seconds
Started	Sep 01 05:33:43 AM UTC 24
Finished	Sep 01 05:45:31 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250484958 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1250484958
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/187.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.4085975097
Short name	T46
Test name
Test status
Simulation time	869677561825 ps
CPU time	422.17 seconds
Started	Sep 01 04:59:30 AM UTC 24
Finished	Sep 01 05:06:38 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085975097 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.4085975097
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.738406849
Short name	T396
Test name
Test status
Simulation time	70506706167 ps
CPU time	156.06 seconds
Started	Sep 01 04:59:22 AM UTC 24
Finished	Sep 01 05:02:01 AM UTC 24
Peak memory	199788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738406849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.738406849
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/19.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.1660504554
Short name	T154
Test name
Test status
Simulation time	722688234576 ps
CPU time	293.67 seconds
Started	Sep 01 04:59:17 AM UTC 24
Finished	Sep 01 05:04:15 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660504554 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1660504554
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/19.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.502087321
Short name	T307
Test name
Test status
Simulation time	59273884372 ps
CPU time	106.92 seconds
Started	Sep 01 04:59:42 AM UTC 24
Finished	Sep 01 05:01:31 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502087321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.502087321
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/19.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.2977798587
Short name	T381
Test name
Test status
Simulation time	133372494313 ps
CPU time	920.78 seconds
Started	Sep 01 05:33:59 AM UTC 24
Finished	Sep 01 05:49:31 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977798587 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2977798587
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/190.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.1300274144
Short name	T203
Test name
Test status
Simulation time	10325375338 ps
CPU time	20.03 seconds
Started	Sep 01 05:34:06 AM UTC 24
Finished	Sep 01 05:34:28 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300274144 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1300274144
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/192.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.1651722101
Short name	T243
Test name
Test status
Simulation time	108400324923 ps
CPU time	239.16 seconds
Started	Sep 01 05:34:12 AM UTC 24
Finished	Sep 01 05:38:15 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651722101 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1651722101
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/193.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.1418390286
Short name	T347
Test name
Test status
Simulation time	171217757055 ps
CPU time	198.5 seconds
Started	Sep 01 05:34:26 AM UTC 24
Finished	Sep 01 05:37:47 AM UTC 24
Peak memory	199776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418390286 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1418390286
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/195.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.2678593774
Short name	T457
Test name
Test status
Simulation time	35915354398 ps
CPU time	104.77 seconds
Started	Sep 01 05:34:29 AM UTC 24
Finished	Sep 01 05:36:17 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678593774 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2678593774
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/196.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.2960116186
Short name	T325
Test name
Test status
Simulation time	294061583841 ps
CPU time	673.81 seconds
Started	Sep 01 05:34:30 AM UTC 24
Finished	Sep 01 05:45:53 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960116186 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2960116186
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/197.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.4231586971
Short name	T364
Test name
Test status
Simulation time	127593561729 ps
CPU time	683.25 seconds
Started	Sep 01 05:34:42 AM UTC 24
Finished	Sep 01 05:46:15 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231586971 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4231586971
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/198.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.869052632
Short name	T304
Test name
Test status
Simulation time	32528365728 ps
CPU time	112.02 seconds
Started	Sep 01 05:34:43 AM UTC 24
Finished	Sep 01 05:36:38 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869052632 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.869052632
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/199.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.2599852390
Short name	T99
Test name
Test status
Simulation time	590710112015 ps
CPU time	384.17 seconds
Started	Sep 01 04:51:39 AM UTC 24
Finished	Sep 01 04:58:10 AM UTC 24
Peak memory	202324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599852390 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.2599852390
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.3756598219
Short name	T87
Test name
Test status
Simulation time	178524423287 ps
CPU time	170.71 seconds
Started	Sep 01 04:51:38 AM UTC 24
Finished	Sep 01 04:54:32 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756598219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3756598219
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.2717021112
Short name	T103
Test name
Test status
Simulation time	208250910072 ps
CPU time	513.7 seconds
Started	Sep 01 04:51:38 AM UTC 24
Finished	Sep 01 05:00:19 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717021112 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2717021112
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.6332972
Short name	T97
Test name
Test status
Simulation time	68425717154 ps
CPU time	630.43 seconds
Started	Sep 01 04:51:41 AM UTC 24
Finished	Sep 01 05:02:21 AM UTC 24
Peak memory	202432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6332972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_S EQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.6332972
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.2466541922
Short name	T3
Test name
Test status
Simulation time	81582826 ps
CPU time	0.92 seconds
Started	Sep 01 04:51:46 AM UTC 24
Finished	Sep 01 04:51:48 AM UTC 24
Peak memory	230928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466541922 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2466541922
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.2638926708
Short name	T187
Test name
Test status
Simulation time	1247919228273 ps
CPU time	1414.54 seconds
Started	Sep 01 04:51:43 AM UTC 24
Finished	Sep 01 05:15:34 AM UTC 24
Peak memory	202484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638926708 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.2638926708
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/2.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.426003046
Short name	T213
Test name
Test status
Simulation time	1806722933296 ps
CPU time	640 seconds
Started	Sep 01 05:00:16 AM UTC 24
Finished	Sep 01 05:11:04 AM UTC 24
Peak memory	199660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426003046 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.426003046
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.3023971867
Short name	T393
Test name
Test status
Simulation time	40252538769 ps
CPU time	56.82 seconds
Started	Sep 01 05:00:06 AM UTC 24
Finished	Sep 01 05:01:04 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023971867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3023971867
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/20.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.4028362864
Short name	T149
Test name
Test status
Simulation time	232706508933 ps
CPU time	135.71 seconds
Started	Sep 01 04:59:58 AM UTC 24
Finished	Sep 01 05:02:16 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028362864 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.4028362864
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/20.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.3622181909
Short name	T126
Test name
Test status
Simulation time	29502835621 ps
CPU time	9.44 seconds
Started	Sep 01 05:00:16 AM UTC 24
Finished	Sep 01 05:00:26 AM UTC 24
Peak memory	199788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622181909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3622181909
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/20.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.724563877
Short name	T143
Test name
Test status
Simulation time	3424266582 ps
CPU time	9.69 seconds
Started	Sep 01 05:00:42 AM UTC 24
Finished	Sep 01 05:00:53 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724563877 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.724563877
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.1601239593
Short name	T404
Test name
Test status
Simulation time	181958004763 ps
CPU time	193.59 seconds
Started	Sep 01 05:00:38 AM UTC 24
Finished	Sep 01 05:03:55 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601239593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1601239593
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/21.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.3282528223
Short name	T101
Test name
Test status
Simulation time	113886045288 ps
CPU time	176.94 seconds
Started	Sep 01 05:00:52 AM UTC 24
Finished	Sep 01 05:03:53 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282528223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3282528223
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/21.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.1879015186
Short name	T41
Test name
Test status
Simulation time	108856402481 ps
CPU time	272.02 seconds
Started	Sep 01 05:01:00 AM UTC 24
Finished	Sep 01 05:05:35 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879015186 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.1879015186
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/21.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all_with_rand_reset.2072005720
Short name	T28
Test name
Test status
Simulation time	751364091 ps
CPU time	6.63 seconds
Started	Sep 01 05:00:54 AM UTC 24
Finished	Sep 01 05:01:02 AM UTC 24
Peak memory	201912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2072005720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.rv_timer_stress_all_with_rand_reset.2072005720
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/21.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.1533408707
Short name	T397
Test name
Test status
Simulation time	25901836703 ps
CPU time	71.75 seconds
Started	Sep 01 05:01:05 AM UTC 24
Finished	Sep 01 05:02:18 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533408707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1533408707
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/22.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.2994909970
Short name	T131
Test name
Test status
Simulation time	82074916355 ps
CPU time	418.56 seconds
Started	Sep 01 05:01:03 AM UTC 24
Finished	Sep 01 05:08:07 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994909970 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2994909970
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/22.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.2763778005
Short name	T137
Test name
Test status
Simulation time	15742338298 ps
CPU time	13.55 seconds
Started	Sep 01 05:01:32 AM UTC 24
Finished	Sep 01 05:01:47 AM UTC 24
Peak memory	199816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763778005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2763778005
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/22.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.3521479486
Short name	T290
Test name
Test status
Simulation time	541620470315 ps
CPU time	468.98 seconds
Started	Sep 01 05:02:00 AM UTC 24
Finished	Sep 01 05:09:55 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521479486 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.3521479486
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.4129296171
Short name	T406
Test name
Test status
Simulation time	403987434644 ps
CPU time	189.05 seconds
Started	Sep 01 05:01:52 AM UTC 24
Finished	Sep 01 05:05:05 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129296171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.4129296171
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/23.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.531921416
Short name	T138
Test name
Test status
Simulation time	197990948199 ps
CPU time	120.95 seconds
Started	Sep 01 05:02:01 AM UTC 24
Finished	Sep 01 05:04:04 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531921416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.531921416
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/23.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.439136836
Short name	T400
Test name
Test status
Simulation time	12755019014 ps
CPU time	29.55 seconds
Started	Sep 01 05:02:02 AM UTC 24
Finished	Sep 01 05:02:33 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439136836 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.439136836
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/23.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.2139156795
Short name	T111
Test name
Test status
Simulation time	795720160085 ps
CPU time	478.57 seconds
Started	Sep 01 05:02:16 AM UTC 24
Finished	Sep 01 05:10:20 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139156795 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.2139156795
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.1117319372
Short name	T153
Test name
Test status
Simulation time	180586251975 ps
CPU time	143.82 seconds
Started	Sep 01 05:02:05 AM UTC 24
Finished	Sep 01 05:04:31 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117319372 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1117319372
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/24.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.2218129910
Short name	T274
Test name
Test status
Simulation time	20215080572 ps
CPU time	14.38 seconds
Started	Sep 01 05:02:19 AM UTC 24
Finished	Sep 01 05:02:35 AM UTC 24
Peak memory	199604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218129910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2218129910
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/24.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.2514901989
Short name	T408
Test name
Test status
Simulation time	873685008610 ps
CPU time	263.95 seconds
Started	Sep 01 05:02:24 AM UTC 24
Finished	Sep 01 05:06:52 AM UTC 24
Peak memory	199908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514901989 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.2514901989
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/24.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.3213545735
Short name	T181
Test name
Test status
Simulation time	309209711367 ps
CPU time	699.46 seconds
Started	Sep 01 05:02:34 AM UTC 24
Finished	Sep 01 05:14:21 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213545735 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.3213545735
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.3135504590
Short name	T402
Test name
Test status
Simulation time	243052231789 ps
CPU time	56.36 seconds
Started	Sep 01 05:02:32 AM UTC 24
Finished	Sep 01 05:03:29 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135504590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3135504590
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/25.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.2139598367
Short name	T327
Test name
Test status
Simulation time	36301192606 ps
CPU time	487.62 seconds
Started	Sep 01 05:02:36 AM UTC 24
Finished	Sep 01 05:10:50 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139598367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2139598367
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/25.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.205376113
Short name	T123
Test name
Test status
Simulation time	559037418991 ps
CPU time	251.11 seconds
Started	Sep 01 05:02:58 AM UTC 24
Finished	Sep 01 05:07:13 AM UTC 24
Peak memory	199660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205376113 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.205376113
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.1693863758
Short name	T407
Test name
Test status
Simulation time	311711252385 ps
CPU time	227.06 seconds
Started	Sep 01 05:02:55 AM UTC 24
Finished	Sep 01 05:06:45 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693863758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1693863758
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/26.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.3132108847
Short name	T120
Test name
Test status
Simulation time	55898009214 ps
CPU time	80.55 seconds
Started	Sep 01 05:03:17 AM UTC 24
Finished	Sep 01 05:04:40 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132108847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3132108847
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/26.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.3097046337
Short name	T432
Test name
Test status
Simulation time	308950741049 ps
CPU time	630.7 seconds
Started	Sep 01 05:03:27 AM UTC 24
Finished	Sep 01 05:14:05 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097046337 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.3097046337
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/26.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.4015975197
Short name	T326
Test name
Test status
Simulation time	784543440885 ps
CPU time	425.61 seconds
Started	Sep 01 05:03:53 AM UTC 24
Finished	Sep 01 05:11:04 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015975197 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.4015975197
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.323827835
Short name	T409
Test name
Test status
Simulation time	518308617033 ps
CPU time	218.91 seconds
Started	Sep 01 05:03:31 AM UTC 24
Finished	Sep 01 05:07:13 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323827835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.323827835
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/27.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.2371200709
Short name	T43
Test name
Test status
Simulation time	55934304598 ps
CPU time	159.31 seconds
Started	Sep 01 05:03:31 AM UTC 24
Finished	Sep 01 05:06:13 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371200709 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2371200709
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/27.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.4138639321
Short name	T114
Test name
Test status
Simulation time	126206353060 ps
CPU time	530.59 seconds
Started	Sep 01 05:03:54 AM UTC 24
Finished	Sep 01 05:12:51 AM UTC 24
Peak memory	199716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138639321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.4138639321
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/27.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.793252713
Short name	T53
Test name
Test status
Simulation time	1663888433052 ps
CPU time	895.13 seconds
Started	Sep 01 05:04:01 AM UTC 24
Finished	Sep 01 05:19:06 AM UTC 24
Peak memory	199700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793252713 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.793252713
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/27.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.1302365097
Short name	T135
Test name
Test status
Simulation time	11028271579 ps
CPU time	16.65 seconds
Started	Sep 01 05:04:16 AM UTC 24
Finished	Sep 01 05:04:34 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302365097 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.1302365097
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.2108615882
Short name	T44
Test name
Test status
Simulation time	272537425770 ps
CPU time	123.76 seconds
Started	Sep 01 05:04:11 AM UTC 24
Finished	Sep 01 05:06:17 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108615882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2108615882
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/28.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.209803362
Short name	T405
Test name
Test status
Simulation time	188828675 ps
CPU time	1.2 seconds
Started	Sep 01 05:04:23 AM UTC 24
Finished	Sep 01 05:04:26 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209803362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.209803362
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/28.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.1355813348
Short name	T410
Test name
Test status
Simulation time	254416134653 ps
CPU time	174.85 seconds
Started	Sep 01 05:04:35 AM UTC 24
Finished	Sep 01 05:07:32 AM UTC 24
Peak memory	199872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355813348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1355813348
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/29.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.2131483674
Short name	T106
Test name
Test status
Simulation time	43378717561 ps
CPU time	134.28 seconds
Started	Sep 01 05:04:33 AM UTC 24
Finished	Sep 01 05:06:50 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131483674 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2131483674
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/29.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.2853590304
Short name	T40
Test name
Test status
Simulation time	68296948709 ps
CPU time	50.13 seconds
Started	Sep 01 05:04:41 AM UTC 24
Finished	Sep 01 05:05:32 AM UTC 24
Peak memory	199852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853590304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2853590304
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/29.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all_with_rand_reset.1064506561
Short name	T29
Test name
Test status
Simulation time	1868914385 ps
CPU time	23.77 seconds
Started	Sep 01 05:04:43 AM UTC 24
Finished	Sep 01 05:05:08 AM UTC 24
Peak memory	203824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1064506561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 29.rv_timer_stress_all_with_rand_reset.1064506561
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/29.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.934973600
Short name	T12
Test name
Test status
Simulation time	147785031020 ps
CPU time	156.25 seconds
Started	Sep 01 04:52:04 AM UTC 24
Finished	Sep 01 04:54:44 AM UTC 24
Peak memory	199740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934973600 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.934973600
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.792697630
Short name	T22
Test name
Test status
Simulation time	84304385005 ps
CPU time	146.49 seconds
Started	Sep 01 04:51:49 AM UTC 24
Finished	Sep 01 04:54:19 AM UTC 24
Peak memory	199880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792697630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.792697630
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.1661287755
Short name	T6
Test name
Test status
Simulation time	8189715652 ps
CPU time	18.7 seconds
Started	Sep 01 04:51:49 AM UTC 24
Finished	Sep 01 04:52:09 AM UTC 24
Peak memory	199688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661287755 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1661287755
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.2702741748
Short name	T9
Test name
Test status
Simulation time	268549472 ps
CPU time	0.96 seconds
Started	Sep 01 04:52:31 AM UTC 24
Finished	Sep 01 04:52:33 AM UTC 24
Peak memory	228940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702741748 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2702741748
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all_with_rand_reset.2706986182
Short name	T7
Test name
Test status
Simulation time	3881224132 ps
CPU time	20.29 seconds
Started	Sep 01 04:52:08 AM UTC 24
Finished	Sep 01 04:52:30 AM UTC 24
Peak memory	203932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2706986182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.rv_timer_stress_all_with_rand_reset.2706986182
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/3.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.2210722217
Short name	T263
Test name
Test status
Simulation time	422768159104 ps
CPU time	397.79 seconds
Started	Sep 01 05:05:09 AM UTC 24
Finished	Sep 01 05:11:53 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210722217 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.2210722217
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.4033602509
Short name	T416
Test name
Test status
Simulation time	164562125685 ps
CPU time	247.34 seconds
Started	Sep 01 05:05:05 AM UTC 24
Finished	Sep 01 05:09:16 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033602509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.4033602509
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/30.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.3316910225
Short name	T316
Test name
Test status
Simulation time	309205750008 ps
CPU time	473.39 seconds
Started	Sep 01 05:05:09 AM UTC 24
Finished	Sep 01 05:13:09 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316910225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3316910225
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/30.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.778436761
Short name	T323
Test name
Test status
Simulation time	544444655912 ps
CPU time	679.07 seconds
Started	Sep 01 05:05:47 AM UTC 24
Finished	Sep 01 05:17:14 AM UTC 24
Peak memory	199608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778436761 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.778436761
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/31.rv_timer_disabled.3317191877
Short name	T427
Test name
Test status
Simulation time	314252205664 ps
CPU time	430.72 seconds
Started	Sep 01 05:05:44 AM UTC 24
Finished	Sep 01 05:13:00 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317191877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3317191877
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/31.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.4095779120
Short name	T226
Test name
Test status
Simulation time	76991158480 ps
CPU time	210.17 seconds
Started	Sep 01 05:06:14 AM UTC 24
Finished	Sep 01 05:09:48 AM UTC 24
Peak memory	199616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095779120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.4095779120
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/31.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.2905810231
Short name	T318
Test name
Test status
Simulation time	177697562300 ps
CPU time	403.75 seconds
Started	Sep 01 05:06:45 AM UTC 24
Finished	Sep 01 05:13:34 AM UTC 24
Peak memory	199712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905810231 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.2905810231
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.2648169808
Short name	T433
Test name
Test status
Simulation time	518424015801 ps
CPU time	451.79 seconds
Started	Sep 01 05:06:38 AM UTC 24
Finished	Sep 01 05:14:16 AM UTC 24
Peak memory	199908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648169808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2648169808
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/32.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.1164214056
Short name	T331
Test name
Test status
Simulation time	129963203918 ps
CPU time	111.46 seconds
Started	Sep 01 05:06:46 AM UTC 24
Finished	Sep 01 05:08:40 AM UTC 24
Peak memory	199852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164214056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1164214056
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/32.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all_with_rand_reset.175597122
Short name	T413
Test name
Test status
Simulation time	11242264735 ps
CPU time	65.14 seconds
Started	Sep 01 05:06:51 AM UTC 24
Finished	Sep 01 05:07:57 AM UTC 24
Peak memory	203896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=175597122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.175597122
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/32.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.3673794583
Short name	T141
Test name
Test status
Simulation time	62747996349 ps
CPU time	117.97 seconds
Started	Sep 01 05:07:14 AM UTC 24
Finished	Sep 01 05:09:14 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673794583 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.3673794583
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.1647518876
Short name	T411
Test name
Test status
Simulation time	12487688925 ps
CPU time	40.46 seconds
Started	Sep 01 05:07:01 AM UTC 24
Finished	Sep 01 05:07:43 AM UTC 24
Peak memory	199908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647518876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1647518876
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/33.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.3736514408
Short name	T308
Test name
Test status
Simulation time	216874446235 ps
CPU time	552.34 seconds
Started	Sep 01 05:06:56 AM UTC 24
Finished	Sep 01 05:16:15 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736514408 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3736514408
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/33.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.3305262932
Short name	T305
Test name
Test status
Simulation time	62136659831 ps
CPU time	38.21 seconds
Started	Sep 01 05:07:14 AM UTC 24
Finished	Sep 01 05:07:54 AM UTC 24
Peak memory	199816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305262932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3305262932
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/33.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.1691773159
Short name	T415
Test name
Test status
Simulation time	28001126694 ps
CPU time	79.65 seconds
Started	Sep 01 05:07:43 AM UTC 24
Finished	Sep 01 05:09:05 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691773159 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.1691773159
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/33.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.1993454943
Short name	T220
Test name
Test status
Simulation time	32644761944 ps
CPU time	99.22 seconds
Started	Sep 01 05:07:55 AM UTC 24
Finished	Sep 01 05:09:36 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993454943 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.1993454943
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.1795972811
Short name	T424
Test name
Test status
Simulation time	422090211972 ps
CPU time	293.72 seconds
Started	Sep 01 05:07:44 AM UTC 24
Finished	Sep 01 05:12:42 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795972811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1795972811
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/34.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.3337474670
Short name	T414
Test name
Test status
Simulation time	46629870 ps
CPU time	0.94 seconds
Started	Sep 01 05:07:58 AM UTC 24
Finished	Sep 01 05:08:00 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337474670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3337474670
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/34.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.2772631308
Short name	T434
Test name
Test status
Simulation time	2273875308361 ps
CPU time	401.54 seconds
Started	Sep 01 05:08:01 AM UTC 24
Finished	Sep 01 05:14:48 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772631308 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.2772631308
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/34.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.3021152319
Short name	T321
Test name
Test status
Simulation time	1037894989595 ps
CPU time	714.85 seconds
Started	Sep 01 05:08:44 AM UTC 24
Finished	Sep 01 05:20:47 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021152319 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.3021152319
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.3028802136
Short name	T418
Test name
Test status
Simulation time	77342203613 ps
CPU time	152.72 seconds
Started	Sep 01 05:08:41 AM UTC 24
Finished	Sep 01 05:11:16 AM UTC 24
Peak memory	199660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028802136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3028802136
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/35.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.4130725314
Short name	T270
Test name
Test status
Simulation time	292410579998 ps
CPU time	115.26 seconds
Started	Sep 01 05:08:08 AM UTC 24
Finished	Sep 01 05:10:06 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130725314 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.4130725314
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/35.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.3903611506
Short name	T157
Test name
Test status
Simulation time	65873962939 ps
CPU time	94.65 seconds
Started	Sep 01 05:08:47 AM UTC 24
Finished	Sep 01 05:10:24 AM UTC 24
Peak memory	199752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903611506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3903611506
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/35.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.125283616
Short name	T209
Test name
Test status
Simulation time	848000137899 ps
CPU time	563.66 seconds
Started	Sep 01 05:09:17 AM UTC 24
Finished	Sep 01 05:18:48 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125283616 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.125283616
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.3851696489
Short name	T439
Test name
Test status
Simulation time	203804817518 ps
CPU time	442.89 seconds
Started	Sep 01 05:09:15 AM UTC 24
Finished	Sep 01 05:16:43 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851696489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3851696489
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/36.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.3430067076
Short name	T134
Test name
Test status
Simulation time	482371457156 ps
CPU time	443.7 seconds
Started	Sep 01 05:09:12 AM UTC 24
Finished	Sep 01 05:16:41 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430067076 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3430067076
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/36.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.2663036816
Short name	T254
Test name
Test status
Simulation time	52854232922 ps
CPU time	182.39 seconds
Started	Sep 01 05:09:17 AM UTC 24
Finished	Sep 01 05:12:23 AM UTC 24
Peak memory	199616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663036816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2663036816
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/36.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.206469280
Short name	T419
Test name
Test status
Simulation time	151625740121 ps
CPU time	115.92 seconds
Started	Sep 01 05:09:36 AM UTC 24
Finished	Sep 01 05:11:35 AM UTC 24
Peak memory	199616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206469280 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.206469280
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/36.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.3314044396
Short name	T253
Test name
Test status
Simulation time	758879541159 ps
CPU time	418.8 seconds
Started	Sep 01 05:09:48 AM UTC 24
Finished	Sep 01 05:16:52 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314044396 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.3314044396
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.2048385192
Short name	T435
Test name
Test status
Simulation time	151743946280 ps
CPU time	301.52 seconds
Started	Sep 01 05:09:44 AM UTC 24
Finished	Sep 01 05:14:50 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048385192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2048385192
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/37.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.117259097
Short name	T337
Test name
Test status
Simulation time	45662387288 ps
CPU time	87.84 seconds
Started	Sep 01 05:09:37 AM UTC 24
Finished	Sep 01 05:11:07 AM UTC 24
Peak memory	199680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117259097 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.117259097
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/37.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.1229858186
Short name	T360
Test name
Test status
Simulation time	377597088271 ps
CPU time	212.63 seconds
Started	Sep 01 05:10:21 AM UTC 24
Finished	Sep 01 05:13:57 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229858186 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.1229858186
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.1398123032
Short name	T422
Test name
Test status
Simulation time	42198842802 ps
CPU time	120.73 seconds
Started	Sep 01 05:10:13 AM UTC 24
Finished	Sep 01 05:12:16 AM UTC 24
Peak memory	199716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398123032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1398123032
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/38.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.2522857309
Short name	T197
Test name
Test status
Simulation time	508023846464 ps
CPU time	734.18 seconds
Started	Sep 01 05:10:11 AM UTC 24
Finished	Sep 01 05:22:34 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522857309 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2522857309
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/38.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.24520607
Short name	T159
Test name
Test status
Simulation time	81828807687 ps
CPU time	197.83 seconds
Started	Sep 01 05:10:25 AM UTC 24
Finished	Sep 01 05:13:46 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24520607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.24520607
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/38.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.4064830748
Short name	T234
Test name
Test status
Simulation time	1372501971405 ps
CPU time	522.69 seconds
Started	Sep 01 05:10:35 AM UTC 24
Finished	Sep 01 05:19:24 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064830748 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.4064830748
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/38.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.1588190649
Short name	T183
Test name
Test status
Simulation time	249777184937 ps
CPU time	262.8 seconds
Started	Sep 01 05:10:51 AM UTC 24
Finished	Sep 01 05:15:17 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588190649 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.1588190649
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.3699257966
Short name	T430
Test name
Test status
Simulation time	288710071237 ps
CPU time	181.01 seconds
Started	Sep 01 05:10:49 AM UTC 24
Finished	Sep 01 05:13:53 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699257966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3699257966
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/39.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.4030119563
Short name	T417
Test name
Test status
Simulation time	55694687 ps
CPU time	0.89 seconds
Started	Sep 01 05:11:08 AM UTC 24
Finished	Sep 01 05:11:10 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030119563 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.4030119563
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/39.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all_with_rand_reset.2922141681
Short name	T421
Test name
Test status
Simulation time	2575387409 ps
CPU time	40.73 seconds
Started	Sep 01 05:11:05 AM UTC 24
Finished	Sep 01 05:11:47 AM UTC 24
Peak memory	203924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2922141681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 39.rv_timer_stress_all_with_rand_reset.2922141681
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/39.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.653011949
Short name	T21
Test name
Test status
Simulation time	21975487832 ps
CPU time	35.28 seconds
Started	Sep 01 04:52:34 AM UTC 24
Finished	Sep 01 04:53:10 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653011949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.653011949
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.1946064765
Short name	T172
Test name
Test status
Simulation time	389163473652 ps
CPU time	1862.44 seconds
Started	Sep 01 04:52:32 AM UTC 24
Finished	Sep 01 05:23:56 AM UTC 24
Peak memory	202408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946064765 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1946064765
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.1686412827
Short name	T14
Test name
Test status
Simulation time	156799230 ps
CPU time	0.86 seconds
Started	Sep 01 04:53:15 AM UTC 24
Finished	Sep 01 04:53:20 AM UTC 24
Peak memory	230928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686412827 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1686412827
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.3355573883
Short name	T185
Test name
Test status
Simulation time	219188309584 ps
CPU time	628.66 seconds
Started	Sep 01 05:11:18 AM UTC 24
Finished	Sep 01 05:21:55 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355573883 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.3355573883
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.1186852868
Short name	T425
Test name
Test status
Simulation time	43175343747 ps
CPU time	94.49 seconds
Started	Sep 01 05:11:17 AM UTC 24
Finished	Sep 01 05:12:54 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186852868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1186852868
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/40.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.1324544306
Short name	T112
Test name
Test status
Simulation time	83886063550 ps
CPU time	229.54 seconds
Started	Sep 01 05:11:11 AM UTC 24
Finished	Sep 01 05:15:04 AM UTC 24
Peak memory	199684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324544306 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1324544306
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/40.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.4822686
Short name	T171
Test name
Test status
Simulation time	446461033820 ps
CPU time	354.11 seconds
Started	Sep 01 05:11:26 AM UTC 24
Finished	Sep 01 05:17:25 AM UTC 24
Peak memory	199788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4822686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_S EQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.4822686
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/40.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.2193421821
Short name	T420
Test name
Test status
Simulation time	70653778 ps
CPU time	0.8 seconds
Started	Sep 01 05:11:35 AM UTC 24
Finished	Sep 01 05:11:37 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193421821 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.2193421821
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/40.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all_with_rand_reset.2354732786
Short name	T423
Test name
Test status
Simulation time	5408215956 ps
CPU time	56.5 seconds
Started	Sep 01 05:11:27 AM UTC 24
Finished	Sep 01 05:12:25 AM UTC 24
Peak memory	203960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2354732786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 40.rv_timer_stress_all_with_rand_reset.2354732786
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/40.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.3909220143
Short name	T109
Test name
Test status
Simulation time	76503072058 ps
CPU time	128.79 seconds
Started	Sep 01 05:11:54 AM UTC 24
Finished	Sep 01 05:14:05 AM UTC 24
Peak memory	199792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909220143 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.3909220143
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/41.rv_timer_disabled.822343194
Short name	T431
Test name
Test status
Simulation time	68883899111 ps
CPU time	127.05 seconds
Started	Sep 01 05:11:48 AM UTC 24
Finished	Sep 01 05:13:57 AM UTC 24
Peak memory	199680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822343194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.822343194
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/41.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.2259482166
Short name	T133
Test name
Test status
Simulation time	61791806596 ps
CPU time	59.6 seconds
Started	Sep 01 05:11:39 AM UTC 24
Finished	Sep 01 05:12:40 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259482166 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2259482166
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/41.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.3598541852
Short name	T179
Test name
Test status
Simulation time	206580911709 ps
CPU time	728.03 seconds
Started	Sep 01 05:12:17 AM UTC 24
Finished	Sep 01 05:24:35 AM UTC 24
Peak memory	199788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598541852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3598541852
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/41.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.2057264077
Short name	T374
Test name
Test status
Simulation time	2625615504383 ps
CPU time	996.24 seconds
Started	Sep 01 05:12:43 AM UTC 24
Finished	Sep 01 05:29:30 AM UTC 24
Peak memory	202452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057264077 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.2057264077
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/42.rv_timer_disabled.2190895521
Short name	T437
Test name
Test status
Simulation time	659263779756 ps
CPU time	160.14 seconds
Started	Sep 01 05:12:41 AM UTC 24
Finished	Sep 01 05:15:24 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190895521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2190895521
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/42.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.1114114035
Short name	T130
Test name
Test status
Simulation time	593518714624 ps
CPU time	155.08 seconds
Started	Sep 01 05:12:40 AM UTC 24
Finished	Sep 01 05:15:18 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114114035 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1114114035
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/42.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.2151934817
Short name	T426
Test name
Test status
Simulation time	627915254 ps
CPU time	0.93 seconds
Started	Sep 01 05:12:52 AM UTC 24
Finished	Sep 01 05:12:54 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151934817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2151934817
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/42.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.2748845492
Short name	T52
Test name
Test status
Simulation time	37723719 ps
CPU time	0.87 seconds
Started	Sep 01 05:12:56 AM UTC 24
Finished	Sep 01 05:12:58 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748845492 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.2748845492
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/42.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.4239719463
Short name	T192
Test name
Test status
Simulation time	273125390712 ps
CPU time	504.69 seconds
Started	Sep 01 05:13:10 AM UTC 24
Finished	Sep 01 05:21:40 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239719463 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.4239719463
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.1377376137
Short name	T445
Test name
Test status
Simulation time	267561200358 ps
CPU time	344.72 seconds
Started	Sep 01 05:13:01 AM UTC 24
Finished	Sep 01 05:18:50 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377376137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1377376137
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/43.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.3544117011
Short name	T166
Test name
Test status
Simulation time	192752968998 ps
CPU time	358.68 seconds
Started	Sep 01 05:12:59 AM UTC 24
Finished	Sep 01 05:19:02 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544117011 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3544117011
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/43.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.1400666427
Short name	T428
Test name
Test status
Simulation time	995507620 ps
CPU time	1.35 seconds
Started	Sep 01 05:13:12 AM UTC 24
Finished	Sep 01 05:13:14 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400666427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1400666427
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/43.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.2095594778
Short name	T264
Test name
Test status
Simulation time	1056629350414 ps
CPU time	526.16 seconds
Started	Sep 01 05:13:14 AM UTC 24
Finished	Sep 01 05:22:07 AM UTC 24
Peak memory	199620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095594778 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.2095594778
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/43.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.1485840852
Short name	T438
Test name
Test status
Simulation time	78271462628 ps
CPU time	141.02 seconds
Started	Sep 01 05:13:34 AM UTC 24
Finished	Sep 01 05:15:58 AM UTC 24
Peak memory	199908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485840852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1485840852
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/44.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.2594094127
Short name	T266
Test name
Test status
Simulation time	87170876438 ps
CPU time	477.36 seconds
Started	Sep 01 05:13:15 AM UTC 24
Finished	Sep 01 05:21:19 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594094127 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2594094127
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/44.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.121189514
Short name	T429
Test name
Test status
Simulation time	1083698792 ps
CPU time	1.14 seconds
Started	Sep 01 05:13:47 AM UTC 24
Finished	Sep 01 05:13:49 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121189514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.121189514
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/44.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.3319627332
Short name	T56
Test name
Test status
Simulation time	281904118908 ps
CPU time	593.36 seconds
Started	Sep 01 05:13:50 AM UTC 24
Finished	Sep 01 05:23:51 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319627332 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.3319627332
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/44.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.350327618
Short name	T320
Test name
Test status
Simulation time	659054909184 ps
CPU time	497.46 seconds
Started	Sep 01 05:13:57 AM UTC 24
Finished	Sep 01 05:22:21 AM UTC 24
Peak memory	199724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350327618 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.350327618
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.1295538930
Short name	T442
Test name
Test status
Simulation time	162596910748 ps
CPU time	201.68 seconds
Started	Sep 01 05:13:54 AM UTC 24
Finished	Sep 01 05:17:19 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295538930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1295538930
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/45.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.2930753126
Short name	T180
Test name
Test status
Simulation time	1572522783 ps
CPU time	3.79 seconds
Started	Sep 01 05:13:53 AM UTC 24
Finished	Sep 01 05:13:58 AM UTC 24
Peak memory	199396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930753126 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2930753126
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/45.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.409042733
Short name	T165
Test name
Test status
Simulation time	119094271131 ps
CPU time	122.02 seconds
Started	Sep 01 05:13:58 AM UTC 24
Finished	Sep 01 05:16:03 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409042733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.409042733
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/45.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.2625773866
Short name	T207
Test name
Test status
Simulation time	2882834013760 ps
CPU time	1317.31 seconds
Started	Sep 01 05:14:07 AM UTC 24
Finished	Sep 01 05:36:20 AM UTC 24
Peak memory	202332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625773866 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.2625773866
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.2688277449
Short name	T443
Test name
Test status
Simulation time	102664141556 ps
CPU time	210.36 seconds
Started	Sep 01 05:14:05 AM UTC 24
Finished	Sep 01 05:17:39 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688277449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2688277449
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/46.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.743880004
Short name	T346
Test name
Test status
Simulation time	39037033294 ps
CPU time	35.49 seconds
Started	Sep 01 05:14:05 AM UTC 24
Finished	Sep 01 05:14:43 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743880004 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.743880004
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/46.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.3645274988
Short name	T444
Test name
Test status
Simulation time	829478341783 ps
CPU time	228.87 seconds
Started	Sep 01 05:14:43 AM UTC 24
Finished	Sep 01 05:18:35 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645274988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3645274988
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/47.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.3315146080
Short name	T194
Test name
Test status
Simulation time	813691407036 ps
CPU time	684.91 seconds
Started	Sep 01 05:14:23 AM UTC 24
Finished	Sep 01 05:25:56 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315146080 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.3315146080
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/47.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.992972417
Short name	T436
Test name
Test status
Simulation time	90458913 ps
CPU time	1.25 seconds
Started	Sep 01 05:14:48 AM UTC 24
Finished	Sep 01 05:14:50 AM UTC 24
Peak memory	198876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992972417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.992972417
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/47.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.3842981463
Short name	T440
Test name
Test status
Simulation time	137136911958 ps
CPU time	125.59 seconds
Started	Sep 01 05:14:51 AM UTC 24
Finished	Sep 01 05:16:59 AM UTC 24
Peak memory	199684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842981463 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.3842981463
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/47.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.1420822399
Short name	T232
Test name
Test status
Simulation time	75394131274 ps
CPU time	49.94 seconds
Started	Sep 01 05:15:05 AM UTC 24
Finished	Sep 01 05:15:56 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420822399 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.1420822399
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.4128106299
Short name	T441
Test name
Test status
Simulation time	100177440066 ps
CPU time	125.46 seconds
Started	Sep 01 05:15:02 AM UTC 24
Finished	Sep 01 05:17:09 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128106299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4128106299
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/48.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.2470207019
Short name	T310
Test name
Test status
Simulation time	759416368767 ps
CPU time	1079.88 seconds
Started	Sep 01 05:14:57 AM UTC 24
Finished	Sep 01 05:33:09 AM UTC 24
Peak memory	202520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470207019 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2470207019
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/48.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.611713257
Short name	T268
Test name
Test status
Simulation time	54647855659 ps
CPU time	121.59 seconds
Started	Sep 01 05:15:18 AM UTC 24
Finished	Sep 01 05:17:22 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611713257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.611713257
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/48.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.1384173998
Short name	T452
Test name
Test status
Simulation time	769862107684 ps
CPU time	732.62 seconds
Started	Sep 01 05:15:25 AM UTC 24
Finished	Sep 01 05:27:46 AM UTC 24
Peak memory	199612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384173998 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.1384173998
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/48.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.3646943737
Short name	T228
Test name
Test status
Simulation time	13643780244 ps
CPU time	43.34 seconds
Started	Sep 01 05:15:39 AM UTC 24
Finished	Sep 01 05:16:24 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646943737 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.3646943737
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.3471346986
Short name	T446
Test name
Test status
Simulation time	298819627834 ps
CPU time	369.88 seconds
Started	Sep 01 05:15:35 AM UTC 24
Finished	Sep 01 05:21:50 AM UTC 24
Peak memory	199724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471346986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3471346986
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/49.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.3131216786
Short name	T186
Test name
Test status
Simulation time	597537817890 ps
CPU time	432.43 seconds
Started	Sep 01 05:15:31 AM UTC 24
Finished	Sep 01 05:22:49 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131216786 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3131216786
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/49.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.4140474180
Short name	T312
Test name
Test status
Simulation time	87902804566 ps
CPU time	207.96 seconds
Started	Sep 01 05:15:53 AM UTC 24
Finished	Sep 01 05:19:25 AM UTC 24
Peak memory	199852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140474180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.4140474180
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/49.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.2213421126
Short name	T13
Test name
Test status
Simulation time	60350955642 ps
CPU time	41.29 seconds
Started	Sep 01 04:54:33 AM UTC 24
Finished	Sep 01 04:55:16 AM UTC 24
Peak memory	199592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213421126 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.2213421126
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.729096648
Short name	T387
Test name
Test status
Simulation time	97546454373 ps
CPU time	157.44 seconds
Started	Sep 01 04:54:19 AM UTC 24
Finished	Sep 01 04:57:00 AM UTC 24
Peak memory	199816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729096648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.729096648
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/5.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.4032740787
Short name	T127
Test name
Test status
Simulation time	368697233492 ps
CPU time	450.8 seconds
Started	Sep 01 04:53:21 AM UTC 24
Finished	Sep 01 05:00:59 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032740787 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.4032740787
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/5.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.1446782759
Short name	T63
Test name
Test status
Simulation time	35451095184 ps
CPU time	72.89 seconds
Started	Sep 01 04:54:45 AM UTC 24
Finished	Sep 01 04:55:59 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446782759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1446782759
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/5.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.1494883333
Short name	T51
Test name
Test status
Simulation time	340853880018 ps
CPU time	502.97 seconds
Started	Sep 01 04:55:31 AM UTC 24
Finished	Sep 01 05:04:00 AM UTC 24
Peak memory	202448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494883333 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.1494883333
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/5.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.765533235
Short name	T247
Test name
Test status
Simulation time	81045689647 ps
CPU time	289.5 seconds
Started	Sep 01 05:16:04 AM UTC 24
Finished	Sep 01 05:20:57 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765533235 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.765533235
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/50.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.2561244660
Short name	T348
Test name
Test status
Simulation time	14966832713 ps
CPU time	41.27 seconds
Started	Sep 01 05:16:12 AM UTC 24
Finished	Sep 01 05:16:55 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561244660 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2561244660
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/51.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.3172919138
Short name	T175
Test name
Test status
Simulation time	1503858858787 ps
CPU time	583.68 seconds
Started	Sep 01 05:16:16 AM UTC 24
Finished	Sep 01 05:26:07 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172919138 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3172919138
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/52.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.3315959313
Short name	T349
Test name
Test status
Simulation time	46972300506 ps
CPU time	125.64 seconds
Started	Sep 01 05:16:25 AM UTC 24
Finished	Sep 01 05:18:33 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315959313 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3315959313
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/53.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.2527529707
Short name	T315
Test name
Test status
Simulation time	209301925804 ps
CPU time	156.79 seconds
Started	Sep 01 05:16:35 AM UTC 24
Finished	Sep 01 05:19:15 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527529707 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2527529707
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/54.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.3306988344
Short name	T250
Test name
Test status
Simulation time	567855245065 ps
CPU time	466.94 seconds
Started	Sep 01 05:16:42 AM UTC 24
Finished	Sep 01 05:24:35 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306988344 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3306988344
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/55.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.918994839
Short name	T242
Test name
Test status
Simulation time	243029599897 ps
CPU time	706.69 seconds
Started	Sep 01 05:16:44 AM UTC 24
Finished	Sep 01 05:28:39 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918994839 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.918994839
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/56.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.2634071325
Short name	T383
Test name
Test status
Simulation time	1076137885426 ps
CPU time	1842.16 seconds
Started	Sep 01 05:16:54 AM UTC 24
Finished	Sep 01 05:47:57 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634071325 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2634071325
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/57.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.1569145442
Short name	T309
Test name
Test status
Simulation time	44161129986 ps
CPU time	73.1 seconds
Started	Sep 01 05:17:00 AM UTC 24
Finished	Sep 01 05:18:14 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569145442 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1569145442
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/59.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.676906932
Short name	T57
Test name
Test status
Simulation time	183358928062 ps
CPU time	361.06 seconds
Started	Sep 01 04:56:00 AM UTC 24
Finished	Sep 01 05:02:06 AM UTC 24
Peak memory	199716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676906932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.676906932
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/6.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.3241375367
Short name	T100
Test name
Test status
Simulation time	89703606247 ps
CPU time	212.52 seconds
Started	Sep 01 04:55:45 AM UTC 24
Finished	Sep 01 04:59:21 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241375367 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3241375367
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/6.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.367494519
Short name	T388
Test name
Test status
Simulation time	204608722 ps
CPU time	0.99 seconds
Started	Sep 01 04:57:31 AM UTC 24
Finished	Sep 01 04:57:33 AM UTC 24
Peak memory	198880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367494519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.367494519
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/6.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.1451146529
Short name	T38
Test name
Test status
Simulation time	51014105491 ps
CPU time	447.73 seconds
Started	Sep 01 04:57:34 AM UTC 24
Finished	Sep 01 05:05:08 AM UTC 24
Peak memory	202584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451146529 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.1451146529
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/6.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.175250530
Short name	T238
Test name
Test status
Simulation time	708312706225 ps
CPU time	492.83 seconds
Started	Sep 01 05:17:07 AM UTC 24
Finished	Sep 01 05:25:25 AM UTC 24
Peak memory	199872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175250530 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.175250530
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/60.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.67799449
Short name	T283
Test name
Test status
Simulation time	33150649854 ps
CPU time	100.67 seconds
Started	Sep 01 05:17:10 AM UTC 24
Finished	Sep 01 05:18:53 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67799449 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.67799449
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/61.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.2886640862
Short name	T363
Test name
Test status
Simulation time	36247282385 ps
CPU time	122.9 seconds
Started	Sep 01 05:17:14 AM UTC 24
Finished	Sep 01 05:19:19 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886640862 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2886640862
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/62.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.2397444725
Short name	T245
Test name
Test status
Simulation time	746723372254 ps
CPU time	227.51 seconds
Started	Sep 01 05:17:22 AM UTC 24
Finished	Sep 01 05:21:13 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397444725 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2397444725
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/64.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.2970655253
Short name	T342
Test name
Test status
Simulation time	49344969886 ps
CPU time	376.68 seconds
Started	Sep 01 05:17:26 AM UTC 24
Finished	Sep 01 05:23:48 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970655253 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2970655253
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/65.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.344413863
Short name	T285
Test name
Test status
Simulation time	120755289161 ps
CPU time	108.95 seconds
Started	Sep 01 05:18:11 AM UTC 24
Finished	Sep 01 05:20:02 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344413863 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.344413863
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/68.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.633516060
Short name	T174
Test name
Test status
Simulation time	77333454438 ps
CPU time	210.49 seconds
Started	Sep 01 05:18:16 AM UTC 24
Finished	Sep 01 05:21:50 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633516060 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.633516060
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/69.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.100233665
Short name	T102
Test name
Test status
Simulation time	388668420283 ps
CPU time	256.89 seconds
Started	Sep 01 04:57:43 AM UTC 24
Finished	Sep 01 05:02:04 AM UTC 24
Peak memory	199724 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100233665 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.100233665
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.1989682034
Short name	T399
Test name
Test status
Simulation time	376383521655 ps
CPU time	289.92 seconds
Started	Sep 01 04:57:37 AM UTC 24
Finished	Sep 01 05:02:31 AM UTC 24
Peak memory	199664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989682034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1989682034
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/7.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.1952160326
Short name	T144
Test name
Test status
Simulation time	92952256918 ps
CPU time	611.81 seconds
Started	Sep 01 04:57:37 AM UTC 24
Finished	Sep 01 05:07:57 AM UTC 24
Peak memory	202448 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952160326 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1952160326
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/7.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.3004694643
Short name	T389
Test name
Test status
Simulation time	1995202194 ps
CPU time	4.58 seconds
Started	Sep 01 04:57:45 AM UTC 24
Finished	Sep 01 04:57:50 AM UTC 24
Peak memory	199680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004694643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3004694643
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/7.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.635020062
Short name	T244
Test name
Test status
Simulation time	2661003961686 ps
CPU time	3959.27 seconds
Started	Sep 01 04:57:46 AM UTC 24
Finished	Sep 01 06:04:27 AM UTC 24
Peak memory	202580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635020062 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.635020062
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/7.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.2505374937
Short name	T231
Test name
Test status
Simulation time	728432245776 ps
CPU time	2151.95 seconds
Started	Sep 01 05:18:34 AM UTC 24
Finished	Sep 01 05:54:51 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505374937 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2505374937
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/70.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.665958333
Short name	T291
Test name
Test status
Simulation time	252287913262 ps
CPU time	199.27 seconds
Started	Sep 01 05:18:36 AM UTC 24
Finished	Sep 01 05:21:59 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665958333 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.665958333
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/71.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.1266274134
Short name	T224
Test name
Test status
Simulation time	104100288655 ps
CPU time	612.7 seconds
Started	Sep 01 05:18:49 AM UTC 24
Finished	Sep 01 05:29:10 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266274134 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1266274134
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/72.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.3748964355
Short name	T246
Test name
Test status
Simulation time	231218778071 ps
CPU time	387.02 seconds
Started	Sep 01 05:18:51 AM UTC 24
Finished	Sep 01 05:25:23 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748964355 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3748964355
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/73.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.4034058379
Short name	T361
Test name
Test status
Simulation time	84362917410 ps
CPU time	259.58 seconds
Started	Sep 01 05:18:53 AM UTC 24
Finished	Sep 01 05:23:17 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034058379 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.4034058379
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/74.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.3820530777
Short name	T240
Test name
Test status
Simulation time	282546934834 ps
CPU time	199.14 seconds
Started	Sep 01 05:19:03 AM UTC 24
Finished	Sep 01 05:22:25 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820530777 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3820530777
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/75.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.3507277938
Short name	T261
Test name
Test status
Simulation time	368627634554 ps
CPU time	397.9 seconds
Started	Sep 01 05:19:06 AM UTC 24
Finished	Sep 01 05:25:50 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507277938 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3507277938
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/76.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.1597928657
Short name	T382
Test name
Test status
Simulation time	62544584762 ps
CPU time	574.5 seconds
Started	Sep 01 05:19:10 AM UTC 24
Finished	Sep 01 05:28:52 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597928657 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1597928657
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/77.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.3982701226
Short name	T113
Test name
Test status
Simulation time	142493141712 ps
CPU time	390.72 seconds
Started	Sep 01 04:57:47 AM UTC 24
Finished	Sep 01 05:04:23 AM UTC 24
Peak memory	199676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982701226 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.3982701226
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.3021878418
Short name	T58
Test name
Test status
Simulation time	109811779041 ps
CPU time	56.24 seconds
Started	Sep 01 04:57:46 AM UTC 24
Finished	Sep 01 04:58:44 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021878418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3021878418
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/8.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.889413251
Short name	T105
Test name
Test status
Simulation time	158497891635 ps
CPU time	250.34 seconds
Started	Sep 01 04:57:46 AM UTC 24
Finished	Sep 01 05:02:00 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889413251 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.889413251
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/8.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.358254847
Short name	T386
Test name
Test status
Simulation time	22589576173 ps
CPU time	25 seconds
Started	Sep 01 04:57:47 AM UTC 24
Finished	Sep 01 04:58:13 AM UTC 24
Peak memory	199748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358254847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.358254847
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/8.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.1287584739
Short name	T294
Test name
Test status
Simulation time	452705080470 ps
CPU time	1003.05 seconds
Started	Sep 01 04:57:47 AM UTC 24
Finished	Sep 01 05:14:43 AM UTC 24
Peak memory	202352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287584739 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.1287584739
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/8.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all_with_rand_reset.3287026533
Short name	T23
Test name
Test status
Simulation time	1544344412 ps
CPU time	7.22 seconds
Started	Sep 01 04:57:47 AM UTC 24
Finished	Sep 01 04:57:55 AM UTC 24
Peak memory	203880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3287026533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.rv_timer_stress_all_with_rand_reset.3287026533
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/8.rv_timer_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.2708738711
Short name	T366
Test name
Test status
Simulation time	14740416973 ps
CPU time	129.46 seconds
Started	Sep 01 05:19:25 AM UTC 24
Finished	Sep 01 05:21:37 AM UTC 24
Peak memory	199780 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708738711 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2708738711
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/80.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.1072609079
Short name	T262
Test name
Test status
Simulation time	192686717902 ps
CPU time	129.59 seconds
Started	Sep 01 05:19:26 AM UTC 24
Finished	Sep 01 05:21:38 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072609079 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1072609079
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/81.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.4055732006
Short name	T260
Test name
Test status
Simulation time	85292380131 ps
CPU time	237.07 seconds
Started	Sep 01 05:20:02 AM UTC 24
Finished	Sep 01 05:24:03 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055732006 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.4055732006
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/82.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.3975548971
Short name	T229
Test name
Test status
Simulation time	252451298019 ps
CPU time	416.23 seconds
Started	Sep 01 05:20:22 AM UTC 24
Finished	Sep 01 05:27:24 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975548971 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3975548971
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/83.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.2025151565
Short name	T248
Test name
Test status
Simulation time	53021557417 ps
CPU time	297.99 seconds
Started	Sep 01 05:20:35 AM UTC 24
Finished	Sep 01 05:25:38 AM UTC 24
Peak memory	199672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025151565 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2025151565
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/84.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.1639905166
Short name	T377
Test name
Test status
Simulation time	3587889753 ps
CPU time	13.26 seconds
Started	Sep 01 05:20:48 AM UTC 24
Finished	Sep 01 05:21:03 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639905166 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1639905166
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/85.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.1917650763
Short name	T329
Test name
Test status
Simulation time	131419844952 ps
CPU time	77.46 seconds
Started	Sep 01 05:20:58 AM UTC 24
Finished	Sep 01 05:22:18 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917650763 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1917650763
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/86.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.33231244
Short name	T221
Test name
Test status
Simulation time	43656308228 ps
CPU time	97.25 seconds
Started	Sep 01 05:21:03 AM UTC 24
Finished	Sep 01 05:22:43 AM UTC 24
Peak memory	199804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33231244 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.33231244
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/87.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.1538546320
Short name	T328
Test name
Test status
Simulation time	510870621228 ps
CPU time	637.82 seconds
Started	Sep 01 05:21:14 AM UTC 24
Finished	Sep 01 05:31:59 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538546320 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1538546320
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/88.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.633835718
Short name	T344
Test name
Test status
Simulation time	217172184992 ps
CPU time	1607.76 seconds
Started	Sep 01 05:21:20 AM UTC 24
Finished	Sep 01 05:48:26 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633835718 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.633835718
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/89.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.2623823756
Short name	T115
Test name
Test status
Simulation time	1302630674141 ps
CPU time	765.73 seconds
Started	Sep 01 04:57:48 AM UTC 24
Finished	Sep 01 05:10:43 AM UTC 24
Peak memory	202452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623823756 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.2623823756
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.266013359
Short name	T395
Test name
Test status
Simulation time	165762901583 ps
CPU time	248.47 seconds
Started	Sep 01 04:57:48 AM UTC 24
Finished	Sep 01 05:02:00 AM UTC 24
Peak memory	199728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266013359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.266013359
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/9.rv_timer_disabled/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.536189690
Short name	T142
Test name
Test status
Simulation time	11480322932 ps
CPU time	20.82 seconds
Started	Sep 01 04:57:48 AM UTC 24
Finished	Sep 01 04:58:10 AM UTC 24
Peak memory	199596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536189690 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.536189690
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/9.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.1991691583
Short name	T136
Test name
Test status
Simulation time	151564032299 ps
CPU time	747.43 seconds
Started	Sep 01 04:57:48 AM UTC 24
Finished	Sep 01 05:10:25 AM UTC 24
Peak memory	202648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991691583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1991691583
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/9.rv_timer_random_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.1870581945
Short name	T184
Test name
Test status
Simulation time	275225915767 ps
CPU time	1113.72 seconds
Started	Sep 01 04:57:48 AM UTC 24
Finished	Sep 01 05:16:35 AM UTC 24
Peak memory	202412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870581945 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.1870581945
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/9.rv_timer_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.2547264889
Short name	T223
Test name
Test status
Simulation time	582423395299 ps
CPU time	563.75 seconds
Started	Sep 01 05:21:22 AM UTC 24
Finished	Sep 01 05:30:53 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547264889 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2547264889
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/90.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.1822378005
Short name	T259
Test name
Test status
Simulation time	414002733985 ps
CPU time	423.88 seconds
Started	Sep 01 05:21:38 AM UTC 24
Finished	Sep 01 05:28:47 AM UTC 24
Peak memory	199744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822378005 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1822378005
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/91.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.2155883033
Short name	T365
Test name
Test status
Simulation time	288002122340 ps
CPU time	1014.05 seconds
Started	Sep 01 05:21:39 AM UTC 24
Finished	Sep 01 05:38:45 AM UTC 24
Peak memory	202444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155883033 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2155883033
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/92.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.302436404
Short name	T313
Test name
Test status
Simulation time	227098325064 ps
CPU time	141.4 seconds
Started	Sep 01 05:21:41 AM UTC 24
Finished	Sep 01 05:24:05 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302436404 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.302436404
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/93.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.3597852781
Short name	T215
Test name
Test status
Simulation time	44942753545 ps
CPU time	157.82 seconds
Started	Sep 01 05:21:44 AM UTC 24
Finished	Sep 01 05:24:25 AM UTC 24
Peak memory	199668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597852781 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3597852781
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/94.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.1756715268
Short name	T351
Test name
Test status
Simulation time	23686466992 ps
CPU time	87.22 seconds
Started	Sep 01 05:21:44 AM UTC 24
Finished	Sep 01 05:23:13 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756715268 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1756715268
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/95.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.2788802870
Short name	T258
Test name
Test status
Simulation time	27412485129 ps
CPU time	104.16 seconds
Started	Sep 01 05:21:50 AM UTC 24
Finished	Sep 01 05:23:37 AM UTC 24
Peak memory	199808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788802870 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2788802870
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/96.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.2537970986
Short name	T235
Test name
Test status
Simulation time	89689047445 ps
CPU time	701.98 seconds
Started	Sep 01 05:21:51 AM UTC 24
Finished	Sep 01 05:33:42 AM UTC 24
Peak memory	199708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537970986 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2537970986
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/97.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.310239221
Short name	T173
Test name
Test status
Simulation time	70365554670 ps
CPU time	487.83 seconds
Started	Sep 01 05:21:55 AM UTC 24
Finished	Sep 01 05:30:09 AM UTC 24
Peak memory	199704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310239221 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.310239221
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/98.rv_timer_random/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.4009595752
Short name	T447
Test name
Test status
Simulation time	73683253505 ps
CPU time	74.42 seconds
Started	Sep 01 05:22:00 AM UTC 24
Finished	Sep 01 05:23:16 AM UTC 24
Peak memory	199844 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009595752 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_31/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.4009595752
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/rv_timer-sim-vcs/99.rv_timer_random/latest