| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.64 | 99.36 | 99.04 | 100.00 | 100.00 | 100.00 | 99.43 |
| T506 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2384834388 | Sep 03 11:37:38 PM UTC 24 | Sep 03 11:37:40 PM UTC 24 | 54570064 ps | ||
| T507 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1272115 | Sep 03 11:37:38 PM UTC 24 | Sep 03 11:37:41 PM UTC 24 | 28363905 ps | ||
| T80 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2598444593 | Sep 03 11:37:38 PM UTC 24 | Sep 03 11:37:41 PM UTC 24 | 120097430 ps | ||
| T508 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1609946551 | Sep 03 11:37:39 PM UTC 24 | Sep 03 11:37:41 PM UTC 24 | 36592442 ps | ||
| T509 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.1380618591 | Sep 03 11:37:40 PM UTC 24 | Sep 03 11:37:41 PM UTC 24 | 12845325 ps | ||
| T510 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.3561636128 | Sep 03 11:37:38 PM UTC 24 | Sep 03 11:37:41 PM UTC 24 | 163061069 ps | ||
| T511 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1077392803 | Sep 03 11:37:40 PM UTC 24 | Sep 03 11:37:41 PM UTC 24 | 29725997 ps | ||
| T512 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.2410900778 | Sep 03 11:37:38 PM UTC 24 | Sep 03 11:37:42 PM UTC 24 | 323661159 ps | ||
| T513 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1732912493 | Sep 03 11:37:40 PM UTC 24 | Sep 03 11:37:42 PM UTC 24 | 125618279 ps | ||
| T514 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.839159879 | Sep 03 11:37:40 PM UTC 24 | Sep 03 11:37:42 PM UTC 24 | 33837887 ps | ||
| T515 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.41610321 | Sep 03 11:37:40 PM UTC 24 | Sep 03 11:37:42 PM UTC 24 | 102129246 ps | ||
| T516 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.2425766721 | Sep 03 11:37:38 PM UTC 24 | Sep 03 11:37:42 PM UTC 24 | 203671140 ps | ||
| T517 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3903686529 | Sep 03 11:37:40 PM UTC 24 | Sep 03 11:37:42 PM UTC 24 | 408638945 ps | ||
| T518 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.2533121797 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:43 PM UTC 24 | 27040659 ps | ||
| T519 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2286742454 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:43 PM UTC 24 | 22857334 ps | ||
| T520 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.2413927107 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:43 PM UTC 24 | 44308006 ps | ||
| T521 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1222375581 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:43 PM UTC 24 | 27758102 ps | ||
| T58 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1814684021 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:43 PM UTC 24 | 40610858 ps | ||
| T522 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.2376561470 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:43 PM UTC 24 | 58705187 ps | ||
| T523 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.3339268480 | Sep 03 11:37:40 PM UTC 24 | Sep 03 11:37:43 PM UTC 24 | 98313270 ps | ||
| T524 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.3954175696 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:43 PM UTC 24 | 31037033 ps | ||
| T525 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1699618889 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:43 PM UTC 24 | 55997573 ps | ||
| T526 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.609945892 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:43 PM UTC 24 | 14608721 ps | ||
| T56 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.1690005872 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:43 PM UTC 24 | 56978215 ps | ||
| T527 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3967508649 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:43 PM UTC 24 | 48337352 ps | ||
| T528 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.1829269915 | Sep 03 11:37:40 PM UTC 24 | Sep 03 11:37:43 PM UTC 24 | 69034042 ps | ||
| T529 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1974364649 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:44 PM UTC 24 | 174511663 ps | ||
| T530 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.4215788074 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:44 PM UTC 24 | 237231813 ps | ||
| T531 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.3610514856 | Sep 03 11:37:41 PM UTC 24 | Sep 03 11:37:44 PM UTC 24 | 36747678 ps | ||
| T532 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1918850030 | Sep 03 11:37:42 PM UTC 24 | Sep 03 11:37:44 PM UTC 24 | 156668557 ps | ||
| T533 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.384199491 | Sep 03 11:37:48 PM UTC 24 | Sep 03 11:37:49 PM UTC 24 | 54401565 ps | ||
| T534 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.1289763792 | Sep 03 11:37:43 PM UTC 24 | Sep 03 11:37:44 PM UTC 24 | 84040387 ps | ||
| T535 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.2334457449 | Sep 03 11:37:48 PM UTC 24 | Sep 03 11:37:49 PM UTC 24 | 21435551 ps | ||
| T59 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.881932574 | Sep 03 11:37:43 PM UTC 24 | Sep 03 11:37:44 PM UTC 24 | 18994535 ps | ||
| T57 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.2283239673 | Sep 03 11:37:43 PM UTC 24 | Sep 03 11:37:45 PM UTC 24 | 23559099 ps | ||
| T536 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.2838904684 | Sep 03 11:37:43 PM UTC 24 | Sep 03 11:37:45 PM UTC 24 | 36204144 ps | ||
| T537 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1334967948 | Sep 03 11:37:43 PM UTC 24 | Sep 03 11:37:45 PM UTC 24 | 361132411 ps | ||
| T538 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3111472480 | Sep 03 11:37:43 PM UTC 24 | Sep 03 11:37:45 PM UTC 24 | 72859759 ps | ||
| T539 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3165385693 | Sep 03 11:37:43 PM UTC 24 | Sep 03 11:37:45 PM UTC 24 | 71238143 ps | ||
| T540 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.1255162403 | Sep 03 11:37:43 PM UTC 24 | Sep 03 11:37:45 PM UTC 24 | 47004066 ps | ||
| T541 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.143699982 | Sep 03 11:37:43 PM UTC 24 | Sep 03 11:37:45 PM UTC 24 | 53921862 ps | ||
| T542 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.597768377 | Sep 03 11:37:43 PM UTC 24 | Sep 03 11:37:45 PM UTC 24 | 179921548 ps | ||
| T543 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2595556795 | Sep 03 11:37:43 PM UTC 24 | Sep 03 11:37:45 PM UTC 24 | 543779489 ps | ||
| T544 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.2716243346 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:46 PM UTC 24 | 24922917 ps | ||
| T545 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.735880834 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:46 PM UTC 24 | 19216538 ps | ||
| T546 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.602204733 | Sep 03 11:37:43 PM UTC 24 | Sep 03 11:37:46 PM UTC 24 | 96703521 ps | ||
| T547 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3436466804 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 52058145 ps | ||
| T548 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.682672181 | Sep 03 11:37:44 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 65499255 ps | ||
| T549 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.2840016401 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 17111602 ps | ||
| T550 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.3509131353 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 53848529 ps | ||
| T551 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2549551920 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 20480860 ps | ||
| T552 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.1411383577 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 31237873 ps | ||
| T553 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2014230065 | Sep 03 11:37:44 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 182164416 ps | ||
| T554 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1972878418 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 15128028 ps | ||
| T555 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.2327593026 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 14279641 ps | ||
| T556 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.552288310 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 24719685 ps | ||
| T557 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.3485834010 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 12767970 ps | ||
| T558 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.844072427 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 38005543 ps | ||
| T559 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1011831238 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 40959100 ps | ||
| T560 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1361134059 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:47 PM UTC 24 | 27007100 ps | ||
| T561 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2547056484 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 518527628 ps | ||
| T562 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.3489122449 | Sep 03 11:37:44 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 44282675 ps | ||
| T563 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.843054012 | Sep 03 11:37:46 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 32282624 ps | ||
| T564 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.1257656843 | Sep 03 11:37:46 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 56492481 ps | ||
| T565 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.1204466100 | Sep 03 11:37:46 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 20483211 ps | ||
| T566 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.3482320006 | Sep 03 11:37:46 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 28831800 ps | ||
| T567 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.821282024 | Sep 03 11:37:46 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 13377639 ps | ||
| T568 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.174914542 | Sep 03 11:37:46 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 14944102 ps | ||
| T569 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.558729709 | Sep 03 11:37:46 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 23127238 ps | ||
| T570 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.921709669 | Sep 03 11:37:46 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 38869591 ps | ||
| T571 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.3037935351 | Sep 03 11:37:46 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 50123307 ps | ||
| T572 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.3557293574 | Sep 03 11:37:46 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 13626689 ps | ||
| T573 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.3543181042 | Sep 03 11:37:46 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 38162481 ps | ||
| T574 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.2106739546 | Sep 03 11:37:45 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 254509413 ps | ||
| T575 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.2657832939 | Sep 03 11:37:46 PM UTC 24 | Sep 03 11:37:48 PM UTC 24 | 58345286 ps | ||
| T576 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.971934035 | Sep 03 11:37:47 PM UTC 24 | Sep 03 11:37:49 PM UTC 24 | 109876069 ps | ||
| T577 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.1320878391 | Sep 03 11:37:48 PM UTC 24 | Sep 03 11:37:49 PM UTC 24 | 41840626 ps | ||
| T578 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.285837079 | Sep 03 11:37:48 PM UTC 24 | Sep 03 11:37:49 PM UTC 24 | 48292771 ps | ||
| T579 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.897607685 | Sep 03 11:37:48 PM UTC 24 | Sep 03 11:37:49 PM UTC 24 | 13947568 ps | ||
| T580 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.1412458264 | Sep 03 11:37:48 PM UTC 24 | Sep 03 11:37:49 PM UTC 24 | 21292265 ps | ||
| T581 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.631248190 | Sep 03 11:37:48 PM UTC 24 | Sep 03 11:37:49 PM UTC 24 | 17502359 ps | ||
| T582 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.1960603071 | Sep 03 11:37:48 PM UTC 24 | Sep 03 11:37:49 PM UTC 24 | 13109308 ps | ||
| T583 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1932180316 | Sep 03 11:37:48 PM UTC 24 | Sep 03 11:37:49 PM UTC 24 | 16643389 ps | ||
| T584 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.1623693143 | Sep 03 11:37:48 PM UTC 24 | Sep 03 11:37:50 PM UTC 24 | 25760998 ps | ||
| T585 | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.2209409615 | Sep 03 11:37:48 PM UTC 24 | Sep 03 11:37:50 PM UTC 24 | 47880503 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all_with_rand_reset.1901784376 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3793198315 ps |
| CPU time | 26.11 seconds |
| Started | Sep 03 11:57:54 PM UTC 24 |
| Finished | Sep 03 11:58:21 PM UTC 24 |
| Peak memory | 203892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1901784376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 1.rv_timer_stress_all_with_rand_reset.1901784376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/4.rv_timer_cfg_update_on_fly.58229723 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 82946544334 ps |
| CPU time | 158.7 seconds |
| Started | Sep 03 11:58:02 PM UTC 24 |
| Finished | Sep 04 12:00:44 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58229723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_cfg_update_on_fly.58229723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3380588600 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 120235987 ps |
| CPU time | 1.41 seconds |
| Started | Sep 03 11:37:22 PM UTC 24 |
| Finished | Sep 03 11:37:24 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380588600 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_intg_err.3380588600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/44.rv_timer_stress_all.1859662226 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 866402968744 ps |
| CPU time | 4847.99 seconds |
| Started | Sep 04 12:13:27 AM UTC 24 |
| Finished | Sep 04 01:35:06 AM UTC 24 |
| Peak memory | 202328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859662226 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.1859662226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/44.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/1.rv_timer_cfg_update_on_fly.2753230281 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 192710409117 ps |
| CPU time | 132 seconds |
| Started | Sep 03 11:57:54 PM UTC 24 |
| Finished | Sep 04 12:00:08 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753230281 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_cfg_update_on_fly.2753230281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/7.rv_timer_stress_all.2526897098 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 994448940442 ps |
| CPU time | 2427.51 seconds |
| Started | Sep 03 11:59:04 PM UTC 24 |
| Finished | Sep 04 12:39:56 AM UTC 24 |
| Peak memory | 202464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526897098 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.2526897098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/7.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all.765758423 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 391509420742 ps |
| CPU time | 1084.43 seconds |
| Started | Sep 04 12:03:18 AM UTC 24 |
| Finished | Sep 04 12:21:34 AM UTC 24 |
| Peak memory | 202352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765758423 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.765758423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/19.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/5.rv_timer_stress_all.378074799 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1548403482471 ps |
| CPU time | 1362.03 seconds |
| Started | Sep 03 11:58:27 PM UTC 24 |
| Finished | Sep 04 12:21:24 AM UTC 24 |
| Peak memory | 202444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378074799 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.378074799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/5.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/6.rv_timer_stress_all.3324425876 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 237276209219 ps |
| CPU time | 431.05 seconds |
| Started | Sep 03 11:58:47 PM UTC 24 |
| Finished | Sep 04 12:06:03 AM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324425876 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.3324425876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/6.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/48.rv_timer_stress_all.3635128053 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 1355026655392 ps |
| CPU time | 3617.48 seconds |
| Started | Sep 04 12:15:42 AM UTC 24 |
| Finished | Sep 04 01:16:37 AM UTC 24 |
| Peak memory | 202424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635128053 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.3635128053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/48.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2111843681 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 195347890 ps |
| CPU time | 1.11 seconds |
| Started | Sep 03 11:37:26 PM UTC 24 |
| Finished | Sep 03 11:37:28 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111843681 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasing.2111843681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all.3862144180 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 4808298570478 ps |
| CPU time | 3862.26 seconds |
| Started | Sep 04 12:05:47 AM UTC 24 |
| Finished | Sep 04 01:10:50 AM UTC 24 |
| Peak memory | 202452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862144180 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.3862144180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/25.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/0.rv_timer_sec_cm.2558888087 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 354459777 ps |
| CPU time | 1.08 seconds |
| Started | Sep 03 11:57:53 PM UTC 24 |
| Finished | Sep 03 11:57:56 PM UTC 24 |
| Peak memory | 229300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558888087 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2558888087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/17.rv_timer_stress_all.2596015835 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 254993845817 ps |
| CPU time | 479.74 seconds |
| Started | Sep 04 12:02:27 AM UTC 24 |
| Finished | Sep 04 12:10:33 AM UTC 24 |
| Peak memory | 199684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596015835 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.2596015835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/17.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all.1523646686 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 1101748484862 ps |
| CPU time | 970 seconds |
| Started | Sep 04 12:04:01 AM UTC 24 |
| Finished | Sep 04 12:20:21 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523646686 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.1523646686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/21.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all.2861650358 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 644844136188 ps |
| CPU time | 1938.11 seconds |
| Started | Sep 04 12:04:14 AM UTC 24 |
| Finished | Sep 04 12:36:53 AM UTC 24 |
| Peak memory | 202424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861650358 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.2861650358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/22.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/33.rv_timer_stress_all.4124730681 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 937616457534 ps |
| CPU time | 1911.16 seconds |
| Started | Sep 04 12:08:45 AM UTC 24 |
| Finished | Sep 04 12:40:59 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124730681 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.4124730681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/33.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/6.rv_timer_random.593576422 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 64179503170 ps |
| CPU time | 281.32 seconds |
| Started | Sep 03 11:58:35 PM UTC 24 |
| Finished | Sep 04 12:03:21 AM UTC 24 |
| Peak memory | 199872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593576422 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.593576422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/6.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/83.rv_timer_random.4093655513 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 815415199679 ps |
| CPU time | 384.69 seconds |
| Started | Sep 04 12:20:24 AM UTC 24 |
| Finished | Sep 04 12:26:54 AM UTC 24 |
| Peak memory | 199748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093655513 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.4093655513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/83.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all.3517948024 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 1270730560167 ps |
| CPU time | 772.82 seconds |
| Started | Sep 04 12:00:35 AM UTC 24 |
| Finished | Sep 04 12:13:36 AM UTC 24 |
| Peak memory | 202456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517948024 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.3517948024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/12.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/31.rv_timer_random.1989225292 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 332491286650 ps |
| CPU time | 382.71 seconds |
| Started | Sep 04 12:07:39 AM UTC 24 |
| Finished | Sep 04 12:14:06 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1989225292 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1989225292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/31.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all.3239535402 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 1018227976937 ps |
| CPU time | 1540.37 seconds |
| Started | Sep 04 12:08:23 AM UTC 24 |
| Finished | Sep 04 12:34:20 AM UTC 24 |
| Peak memory | 202412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239535402 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.3239535402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/32.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all.3658616277 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 202293863504 ps |
| CPU time | 743.05 seconds |
| Started | Sep 04 12:13:01 AM UTC 24 |
| Finished | Sep 04 12:25:32 AM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658616277 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.3658616277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/43.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all.3233182222 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2199273421797 ps |
| CPU time | 1905.39 seconds |
| Started | Sep 04 12:14:21 AM UTC 24 |
| Finished | Sep 04 12:46:27 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233182222 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.3233182222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/46.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/14.rv_timer_random.3098075140 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 389058875405 ps |
| CPU time | 221.57 seconds |
| Started | Sep 04 12:01:07 AM UTC 24 |
| Finished | Sep 04 12:04:51 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098075140 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3098075140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/14.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all.2784612858 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 657064227848 ps |
| CPU time | 716.43 seconds |
| Started | Sep 04 12:15:25 AM UTC 24 |
| Finished | Sep 04 12:27:29 AM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784612858 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.2784612858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/47.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/87.rv_timer_random.3364437028 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 104226445654 ps |
| CPU time | 202.56 seconds |
| Started | Sep 04 12:20:51 AM UTC 24 |
| Finished | Sep 04 12:24:16 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364437028 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3364437028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/87.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/99.rv_timer_random.3736497861 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 683107270632 ps |
| CPU time | 373.49 seconds |
| Started | Sep 04 12:23:42 AM UTC 24 |
| Finished | Sep 04 12:30:00 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736497861 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3736497861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/99.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/166.rv_timer_random.3814981221 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 86452550098 ps |
| CPU time | 169.77 seconds |
| Started | Sep 04 12:31:24 AM UTC 24 |
| Finished | Sep 04 12:34:16 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814981221 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3814981221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/166.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/177.rv_timer_random.4067115599 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 194618128698 ps |
| CPU time | 842.98 seconds |
| Started | Sep 04 12:32:50 AM UTC 24 |
| Finished | Sep 04 12:47:03 AM UTC 24 |
| Peak memory | 202580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067115599 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.4067115599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/177.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/18.rv_timer_stress_all.3830524839 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 2631998502468 ps |
| CPU time | 1367.53 seconds |
| Started | Sep 04 12:02:48 AM UTC 24 |
| Finished | Sep 04 12:25:49 AM UTC 24 |
| Peak memory | 202584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830524839 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all.3830524839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/18.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/193.rv_timer_random.4286230328 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1280500060644 ps |
| CPU time | 1495.94 seconds |
| Started | Sep 04 12:34:52 AM UTC 24 |
| Finished | Sep 04 01:00:05 AM UTC 24 |
| Peak memory | 202440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286230328 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.4286230328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/193.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/93.rv_timer_random.1586943528 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 456038937483 ps |
| CPU time | 257.16 seconds |
| Started | Sep 04 12:22:20 AM UTC 24 |
| Finished | Sep 04 12:26:40 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586943528 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1586943528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/93.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/98.rv_timer_random.4086777354 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 117362931773 ps |
| CPU time | 813.89 seconds |
| Started | Sep 04 12:23:28 AM UTC 24 |
| Finished | Sep 04 12:37:11 AM UTC 24 |
| Peak memory | 202412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086777354 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.4086777354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/98.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/113.rv_timer_random.2505116181 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 627431167940 ps |
| CPU time | 547.04 seconds |
| Started | Sep 04 12:25:00 AM UTC 24 |
| Finished | Sep 04 12:34:13 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505116181 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2505116181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/113.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/185.rv_timer_random.1865435773 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 106736616889 ps |
| CPU time | 2957.42 seconds |
| Started | Sep 04 12:34:14 AM UTC 24 |
| Finished | Sep 04 01:24:02 AM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865435773 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1865435773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/185.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/2.rv_timer_random.1278557536 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 681706514679 ps |
| CPU time | 281.68 seconds |
| Started | Sep 03 11:57:54 PM UTC 24 |
| Finished | Sep 04 12:02:40 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278557536 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1278557536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/24.rv_timer_stress_all.426313457 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 6598747424584 ps |
| CPU time | 1955.53 seconds |
| Started | Sep 04 12:05:18 AM UTC 24 |
| Finished | Sep 04 12:38:14 AM UTC 24 |
| Peak memory | 202352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426313457 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.426313457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/24.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/42.rv_timer_cfg_update_on_fly.1200072797 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 297510678915 ps |
| CPU time | 703.55 seconds |
| Started | Sep 04 12:12:09 AM UTC 24 |
| Finished | Sep 04 12:24:01 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200072797 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_cfg_update_on_fly.1200072797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/42.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/48.rv_timer_random.2769236478 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 332222718192 ps |
| CPU time | 432.46 seconds |
| Started | Sep 04 12:15:35 AM UTC 24 |
| Finished | Sep 04 12:22:53 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769236478 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2769236478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/48.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/120.rv_timer_random.909157607 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 589729919662 ps |
| CPU time | 344.08 seconds |
| Started | Sep 04 12:25:46 AM UTC 24 |
| Finished | Sep 04 12:31:35 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909157607 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.909157607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/120.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/129.rv_timer_random.2553363864 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 96880973893 ps |
| CPU time | 232.55 seconds |
| Started | Sep 04 12:26:20 AM UTC 24 |
| Finished | Sep 04 12:30:16 AM UTC 24 |
| Peak memory | 199700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553363864 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2553363864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/129.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/167.rv_timer_random.2614103251 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 126737398120 ps |
| CPU time | 498.1 seconds |
| Started | Sep 04 12:31:32 AM UTC 24 |
| Finished | Sep 04 12:39:57 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614103251 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2614103251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/167.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/17.rv_timer_random.368400530 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 170206980528 ps |
| CPU time | 452.82 seconds |
| Started | Sep 04 12:01:55 AM UTC 24 |
| Finished | Sep 04 12:09:34 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368400530 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.368400530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/17.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/191.rv_timer_random.2204507664 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 327767353432 ps |
| CPU time | 522.38 seconds |
| Started | Sep 04 12:34:36 AM UTC 24 |
| Finished | Sep 04 12:43:25 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204507664 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2204507664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/191.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/20.rv_timer_random.907447991 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 956827398367 ps |
| CPU time | 783.96 seconds |
| Started | Sep 04 12:03:18 AM UTC 24 |
| Finished | Sep 04 12:16:31 AM UTC 24 |
| Peak memory | 202584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907447991 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.907447991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/20.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/40.rv_timer_random.3693566321 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 137643341875 ps |
| CPU time | 876.76 seconds |
| Started | Sep 04 12:10:58 AM UTC 24 |
| Finished | Sep 04 12:25:45 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693566321 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3693566321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/40.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/72.rv_timer_random.3238109922 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 293691727739 ps |
| CPU time | 331.43 seconds |
| Started | Sep 04 12:19:13 AM UTC 24 |
| Finished | Sep 04 12:24:49 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238109922 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3238109922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/72.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/0.rv_timer_cfg_update_on_fly.420694111 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 12180777756 ps |
| CPU time | 20.67 seconds |
| Started | Sep 03 11:57:52 PM UTC 24 |
| Finished | Sep 03 11:58:14 PM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420694111 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_cfg_update_on_fly.420694111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/0.rv_timer_random.1593600712 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 188864923821 ps |
| CPU time | 745.68 seconds |
| Started | Sep 03 11:57:52 PM UTC 24 |
| Finished | Sep 04 12:10:26 AM UTC 24 |
| Peak memory | 202484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593600712 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1593600712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/1.rv_timer_stress_all.4093352748 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 755783723605 ps |
| CPU time | 644.08 seconds |
| Started | Sep 03 11:57:54 PM UTC 24 |
| Finished | Sep 04 12:08:45 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093352748 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.4093352748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/121.rv_timer_random.2560652143 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 115399308945 ps |
| CPU time | 358.51 seconds |
| Started | Sep 04 12:25:50 AM UTC 24 |
| Finished | Sep 04 12:31:54 AM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560652143 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2560652143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/121.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/150.rv_timer_random.282562504 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 343699423716 ps |
| CPU time | 756.58 seconds |
| Started | Sep 04 12:29:18 AM UTC 24 |
| Finished | Sep 04 12:42:04 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282562504 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.282562504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/150.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/170.rv_timer_random.2160673362 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 171395722610 ps |
| CPU time | 355.58 seconds |
| Started | Sep 04 12:31:54 AM UTC 24 |
| Finished | Sep 04 12:37:55 AM UTC 24 |
| Peak memory | 199840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160673362 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2160673362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/170.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/49.rv_timer_random.1185560925 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 89502799351 ps |
| CPU time | 224.39 seconds |
| Started | Sep 04 12:15:49 AM UTC 24 |
| Finished | Sep 04 12:19:36 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185560925 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1185560925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/49.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/57.rv_timer_random.3578951851 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 225400295649 ps |
| CPU time | 519.79 seconds |
| Started | Sep 04 12:17:06 AM UTC 24 |
| Finished | Sep 04 12:25:53 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578951851 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3578951851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/57.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/64.rv_timer_random.3021809297 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 142238326787 ps |
| CPU time | 525.46 seconds |
| Started | Sep 04 12:18:17 AM UTC 24 |
| Finished | Sep 04 12:27:09 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021809297 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3021809297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/64.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/71.rv_timer_random.1754999138 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 481079001924 ps |
| CPU time | 518.82 seconds |
| Started | Sep 04 12:19:09 AM UTC 24 |
| Finished | Sep 04 12:27:54 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754999138 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1754999138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/71.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.917497216 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 79119198 ps |
| CPU time | 0.7 seconds |
| Started | Sep 03 11:37:26 PM UTC 24 |
| Finished | Sep 03 11:37:27 PM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917497216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_same_csr_outstanding.917497216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/10.rv_timer_random.1587152278 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 56586966189 ps |
| CPU time | 121.23 seconds |
| Started | Sep 03 11:59:30 PM UTC 24 |
| Finished | Sep 04 12:01:34 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587152278 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1587152278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/10.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/10.rv_timer_random_reset.3879223979 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 29436657278 ps |
| CPU time | 32.03 seconds |
| Started | Sep 03 11:59:49 PM UTC 24 |
| Finished | Sep 04 12:00:22 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879223979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3879223979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/10.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/100.rv_timer_random.3902302994 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 754947697974 ps |
| CPU time | 1047.22 seconds |
| Started | Sep 04 12:23:54 AM UTC 24 |
| Finished | Sep 04 12:41:34 AM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902302994 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3902302994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/100.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/103.rv_timer_random.393253012 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 100390458664 ps |
| CPU time | 197.79 seconds |
| Started | Sep 04 12:24:09 AM UTC 24 |
| Finished | Sep 04 12:27:30 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393253012 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.393253012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/103.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/11.rv_timer_random.2881972811 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 217305689135 ps |
| CPU time | 160.69 seconds |
| Started | Sep 04 12:00:00 AM UTC 24 |
| Finished | Sep 04 12:02:44 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881972811 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2881972811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/11.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/12.rv_timer_cfg_update_on_fly.3759294245 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 176730629932 ps |
| CPU time | 409.15 seconds |
| Started | Sep 04 12:00:29 AM UTC 24 |
| Finished | Sep 04 12:07:24 AM UTC 24 |
| Peak memory | 199784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759294245 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_cfg_update_on_fly.3759294245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/12.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/12.rv_timer_random.4083363233 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 459911224784 ps |
| CPU time | 359.97 seconds |
| Started | Sep 04 12:00:23 AM UTC 24 |
| Finished | Sep 04 12:06:28 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083363233 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4083363233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/12.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/13.rv_timer_cfg_update_on_fly.883263821 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 394628507099 ps |
| CPU time | 243.16 seconds |
| Started | Sep 04 12:01:01 AM UTC 24 |
| Finished | Sep 04 12:05:08 AM UTC 24 |
| Peak memory | 199660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883263821 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_cfg_update_on_fly.883263821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/13.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/153.rv_timer_random.468859474 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 421156605111 ps |
| CPU time | 221.63 seconds |
| Started | Sep 04 12:29:35 AM UTC 24 |
| Finished | Sep 04 12:33:20 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468859474 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.468859474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/153.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/155.rv_timer_random.1768197839 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 1154550351668 ps |
| CPU time | 409.65 seconds |
| Started | Sep 04 12:29:54 AM UTC 24 |
| Finished | Sep 04 12:36:49 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768197839 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1768197839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/155.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/161.rv_timer_random.4037895096 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 304090113569 ps |
| CPU time | 823.99 seconds |
| Started | Sep 04 12:31:08 AM UTC 24 |
| Finished | Sep 04 12:45:03 AM UTC 24 |
| Peak memory | 202644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037895096 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.4037895096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/161.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/169.rv_timer_random.3128936490 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 30778998930 ps |
| CPU time | 63.21 seconds |
| Started | Sep 04 12:31:35 AM UTC 24 |
| Finished | Sep 04 12:32:40 AM UTC 24 |
| Peak memory | 199700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128936490 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3128936490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/169.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/26.rv_timer_random.2899867795 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 176573581113 ps |
| CPU time | 1042.54 seconds |
| Started | Sep 04 12:05:52 AM UTC 24 |
| Finished | Sep 04 12:23:27 AM UTC 24 |
| Peak memory | 202584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899867795 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2899867795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/26.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/28.rv_timer_random.963281719 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 683552319041 ps |
| CPU time | 738.38 seconds |
| Started | Sep 04 12:06:28 AM UTC 24 |
| Finished | Sep 04 12:18:55 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963281719 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.963281719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/28.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/65.rv_timer_random.203771846 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 329168812062 ps |
| CPU time | 147.37 seconds |
| Started | Sep 04 12:18:20 AM UTC 24 |
| Finished | Sep 04 12:20:50 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203771846 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.203771846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/65.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/78.rv_timer_random.2631948720 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 206622313717 ps |
| CPU time | 697.08 seconds |
| Started | Sep 04 12:19:38 AM UTC 24 |
| Finished | Sep 04 12:31:23 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631948720 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2631948720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/78.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/8.rv_timer_random.2015938012 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 91777701410 ps |
| CPU time | 291.57 seconds |
| Started | Sep 03 11:59:06 PM UTC 24 |
| Finished | Sep 04 12:04:01 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015938012 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2015938012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/8.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/91.rv_timer_random.797182313 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 337543933943 ps |
| CPU time | 197.91 seconds |
| Started | Sep 04 12:21:35 AM UTC 24 |
| Finished | Sep 04 12:24:56 AM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797182313 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.797182313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/91.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4126214158 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 84077660 ps |
| CPU time | 1.21 seconds |
| Started | Sep 03 11:37:26 PM UTC 24 |
| Finished | Sep 03 11:37:28 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126214158 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg_err.4126214158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/1.rv_timer_random.2101604037 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 307849542305 ps |
| CPU time | 686.39 seconds |
| Started | Sep 03 11:57:53 PM UTC 24 |
| Finished | Sep 04 12:09:28 AM UTC 24 |
| Peak memory | 202548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101604037 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2101604037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/101.rv_timer_random.4108465868 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 61624885185 ps |
| CPU time | 622.5 seconds |
| Started | Sep 04 12:23:58 AM UTC 24 |
| Finished | Sep 04 12:34:29 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108465868 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.4108465868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/101.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/114.rv_timer_random.3222146533 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 45569220001 ps |
| CPU time | 169.17 seconds |
| Started | Sep 04 12:25:08 AM UTC 24 |
| Finished | Sep 04 12:28:00 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222146533 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3222146533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/114.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/123.rv_timer_random.1726622313 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 219769623654 ps |
| CPU time | 241.58 seconds |
| Started | Sep 04 12:25:54 AM UTC 24 |
| Finished | Sep 04 12:30:00 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726622313 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1726622313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/123.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/126.rv_timer_random.3657235473 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 359729200004 ps |
| CPU time | 185.17 seconds |
| Started | Sep 04 12:26:03 AM UTC 24 |
| Finished | Sep 04 12:29:11 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657235473 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3657235473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/126.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/131.rv_timer_random.1808421601 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1769405084824 ps |
| CPU time | 961.07 seconds |
| Started | Sep 04 12:26:35 AM UTC 24 |
| Finished | Sep 04 12:42:47 AM UTC 24 |
| Peak memory | 202544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808421601 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1808421601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/131.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/135.rv_timer_random.1964667627 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 855275651297 ps |
| CPU time | 425.13 seconds |
| Started | Sep 04 12:26:55 AM UTC 24 |
| Finished | Sep 04 12:34:05 AM UTC 24 |
| Peak memory | 199700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964667627 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1964667627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/135.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/14.rv_timer_cfg_update_on_fly.282016684 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 163471710664 ps |
| CPU time | 206.7 seconds |
| Started | Sep 04 12:01:08 AM UTC 24 |
| Finished | Sep 04 12:04:38 AM UTC 24 |
| Peak memory | 199660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282016684 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_cfg_update_on_fly.282016684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/14.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/140.rv_timer_random.2398738879 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 238446557815 ps |
| CPU time | 880.77 seconds |
| Started | Sep 04 12:27:35 AM UTC 24 |
| Finished | Sep 04 12:42:26 AM UTC 24 |
| Peak memory | 202544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398738879 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2398738879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/140.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/144.rv_timer_random.3017846986 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1316246391178 ps |
| CPU time | 253.26 seconds |
| Started | Sep 04 12:28:15 AM UTC 24 |
| Finished | Sep 04 12:32:32 AM UTC 24 |
| Peak memory | 199868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017846986 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3017846986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/144.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/17.rv_timer_random_reset.3528642742 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 25960185509 ps |
| CPU time | 23.61 seconds |
| Started | Sep 04 12:02:13 AM UTC 24 |
| Finished | Sep 04 12:02:37 AM UTC 24 |
| Peak memory | 199916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528642742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3528642742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/17.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/178.rv_timer_random.4025151204 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 191213954424 ps |
| CPU time | 541.75 seconds |
| Started | Sep 04 12:33:20 AM UTC 24 |
| Finished | Sep 04 12:42:29 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025151204 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.4025151204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/178.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/179.rv_timer_random.3764603293 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 152535239827 ps |
| CPU time | 186.42 seconds |
| Started | Sep 04 12:33:44 AM UTC 24 |
| Finished | Sep 04 12:36:53 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764603293 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3764603293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/179.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/182.rv_timer_random.3744133798 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 37024911229 ps |
| CPU time | 111.98 seconds |
| Started | Sep 04 12:34:07 AM UTC 24 |
| Finished | Sep 04 12:36:01 AM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744133798 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3744133798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/182.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/195.rv_timer_random.1467956902 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 395427816128 ps |
| CPU time | 304.42 seconds |
| Started | Sep 04 12:35:10 AM UTC 24 |
| Finished | Sep 04 12:40:18 AM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467956902 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1467956902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/195.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/21.rv_timer_cfg_update_on_fly.4282459741 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 140923992035 ps |
| CPU time | 92.17 seconds |
| Started | Sep 04 12:03:53 AM UTC 24 |
| Finished | Sep 04 12:05:28 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282459741 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_cfg_update_on_fly.4282459741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/21.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/23.rv_timer_random_reset.3474886316 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 57445796466 ps |
| CPU time | 321.63 seconds |
| Started | Sep 04 12:04:27 AM UTC 24 |
| Finished | Sep 04 12:09:53 AM UTC 24 |
| Peak memory | 199852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474886316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3474886316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/23.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/27.rv_timer_random.1276410451 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 191736628608 ps |
| CPU time | 167.25 seconds |
| Started | Sep 04 12:06:09 AM UTC 24 |
| Finished | Sep 04 12:08:59 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276410451 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1276410451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/27.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/28.rv_timer_random_reset.1625408668 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 36007924138 ps |
| CPU time | 150.62 seconds |
| Started | Sep 04 12:06:36 AM UTC 24 |
| Finished | Sep 04 12:09:09 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625408668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1625408668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/28.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/32.rv_timer_random.1264958568 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 98108447810 ps |
| CPU time | 1035.89 seconds |
| Started | Sep 04 12:08:03 AM UTC 24 |
| Finished | Sep 04 12:25:31 AM UTC 24 |
| Peak memory | 202412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264958568 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1264958568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/32.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/40.rv_timer_random_reset.1384970467 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 48417123387 ps |
| CPU time | 106.43 seconds |
| Started | Sep 04 12:11:05 AM UTC 24 |
| Finished | Sep 04 12:12:53 AM UTC 24 |
| Peak memory | 199852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384970467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1384970467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/40.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/41.rv_timer_random.1442538865 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 306483787587 ps |
| CPU time | 160.82 seconds |
| Started | Sep 04 12:11:13 AM UTC 24 |
| Finished | Sep 04 12:13:57 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442538865 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1442538865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/41.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/41.rv_timer_stress_all.689694201 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 987741534279 ps |
| CPU time | 2700.13 seconds |
| Started | Sep 04 12:11:35 AM UTC 24 |
| Finished | Sep 04 12:57:02 AM UTC 24 |
| Peak memory | 202356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689694201 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.689694201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/41.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/45.rv_timer_random.2221630881 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 1162072301652 ps |
| CPU time | 678.61 seconds |
| Started | Sep 04 12:13:33 AM UTC 24 |
| Finished | Sep 04 12:24:59 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221630881 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2221630881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/45.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/53.rv_timer_random.4043094275 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 176574774182 ps |
| CPU time | 396.69 seconds |
| Started | Sep 04 12:16:45 AM UTC 24 |
| Finished | Sep 04 12:23:26 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043094275 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.4043094275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/53.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/85.rv_timer_random.1691488469 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 259995907948 ps |
| CPU time | 655.89 seconds |
| Started | Sep 04 12:20:28 AM UTC 24 |
| Finished | Sep 04 12:31:31 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691488469 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1691488469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/85.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3336211907 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 200217248 ps |
| CPU time | 2.98 seconds |
| Started | Sep 03 11:37:26 PM UTC 24 |
| Finished | Sep 03 11:37:30 PM UTC 24 |
| Peak memory | 200816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336211907 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_bash.3336211907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3623759878 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 40647623 ps |
| CPU time | 0.78 seconds |
| Started | Sep 03 11:37:25 PM UTC 24 |
| Finished | Sep 03 11:37:27 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623759878 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_reset.3623759878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1088845754 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 18571418 ps |
| CPU time | 0.93 seconds |
| Started | Sep 03 11:37:26 PM UTC 24 |
| Finished | Sep 03 11:37:28 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1088845754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_cs r_mem_rw_with_rand_reset.1088845754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_csr_rw.2876799372 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 15019180 ps |
| CPU time | 0.73 seconds |
| Started | Sep 03 11:37:26 PM UTC 24 |
| Finished | Sep 03 11:37:27 PM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876799372 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2876799372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_intr_test.3570594006 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 210325636 ps |
| CPU time | 0.76 seconds |
| Started | Sep 03 11:37:22 PM UTC 24 |
| Finished | Sep 03 11:37:23 PM UTC 24 |
| Peak memory | 199824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570594006 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3570594006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/0.rv_timer_tl_errors.361703576 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 528803861 ps |
| CPU time | 2.52 seconds |
| Started | Sep 03 11:37:22 PM UTC 24 |
| Finished | Sep 03 11:37:25 PM UTC 24 |
| Peak memory | 202728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361703576 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.361703576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3783556541 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 110399960 ps |
| CPU time | 0.94 seconds |
| Started | Sep 03 11:37:28 PM UTC 24 |
| Finished | Sep 03 11:37:30 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783556541 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_aliasing.3783556541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2127945485 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2361146516 ps |
| CPU time | 3.38 seconds |
| Started | Sep 03 11:37:28 PM UTC 24 |
| Finished | Sep 03 11:37:32 PM UTC 24 |
| Peak memory | 200804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127945485 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_bash.2127945485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3091204531 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 50108193 ps |
| CPU time | 0.69 seconds |
| Started | Sep 03 11:37:26 PM UTC 24 |
| Finished | Sep 03 11:37:28 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091204531 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_reset.3091204531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2446762172 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 27984229 ps |
| CPU time | 1.51 seconds |
| Started | Sep 03 11:37:28 PM UTC 24 |
| Finished | Sep 03 11:37:31 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2446762172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_cs r_mem_rw_with_rand_reset.2446762172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_csr_rw.1467010001 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 43010891 ps |
| CPU time | 0.75 seconds |
| Started | Sep 03 11:37:26 PM UTC 24 |
| Finished | Sep 03 11:37:28 PM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467010001 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1467010001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_intr_test.1765494562 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 40214547 ps |
| CPU time | 0.72 seconds |
| Started | Sep 03 11:37:26 PM UTC 24 |
| Finished | Sep 03 11:37:28 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765494562 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1765494562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.535814522 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 131232113 ps |
| CPU time | 0.84 seconds |
| Started | Sep 03 11:37:28 PM UTC 24 |
| Finished | Sep 03 11:37:30 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535814522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_same_csr_outstanding.535814522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/1.rv_timer_tl_errors.2912964091 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 268598646 ps |
| CPU time | 2.98 seconds |
| Started | Sep 03 11:37:26 PM UTC 24 |
| Finished | Sep 03 11:37:30 PM UTC 24 |
| Peak memory | 200684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912964091 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2912964091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1272115 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 28363905 ps |
| CPU time | 0.97 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:41 PM UTC 24 |
| Peak memory | 198896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1272115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_ mem_rw_with_rand_reset.1272115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/10.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_csr_rw.727356095 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 11886203 ps |
| CPU time | 0.61 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:40 PM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727356095 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.727356095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/10.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_intr_test.2005598309 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 12900922 ps |
| CPU time | 0.58 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:40 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005598309 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2005598309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/10.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2384834388 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 54570064 ps |
| CPU time | 0.76 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:40 PM UTC 24 |
| Peak memory | 198840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384834388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_same_csr_outstanding.2384834388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/10.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_errors.3561636128 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 163061069 ps |
| CPU time | 2.46 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:41 PM UTC 24 |
| Peak memory | 200676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561636128 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3561636128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/10.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/10.rv_timer_tl_intg_err.970036625 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 1927069166 ps |
| CPU time | 1.24 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:40 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970036625 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_intg_err.970036625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/10.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.839159879 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 33837887 ps |
| CPU time | 1.05 seconds |
| Started | Sep 03 11:37:40 PM UTC 24 |
| Finished | Sep 03 11:37:42 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=839159879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_cs r_mem_rw_with_rand_reset.839159879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/11.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_csr_rw.997321497 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 38206157 ps |
| CPU time | 0.61 seconds |
| Started | Sep 03 11:37:39 PM UTC 24 |
| Finished | Sep 03 11:37:41 PM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997321497 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.997321497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/11.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_intr_test.289617519 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 17859428 ps |
| CPU time | 0.55 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:40 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289617519 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.289617519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/11.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1609946551 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 36592442 ps |
| CPU time | 0.8 seconds |
| Started | Sep 03 11:37:39 PM UTC 24 |
| Finished | Sep 03 11:37:41 PM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609946551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_same_csr_outstanding.1609946551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/11.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_errors.2410900778 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 323661159 ps |
| CPU time | 1.86 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:42 PM UTC 24 |
| Peak memory | 201144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410900778 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2410900778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/11.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2598444593 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 120097430 ps |
| CPU time | 1.3 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:41 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598444593 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_intg_err.2598444593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/11.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1077392803 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 29725997 ps |
| CPU time | 0.67 seconds |
| Started | Sep 03 11:37:40 PM UTC 24 |
| Finished | Sep 03 11:37:41 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1077392803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_c sr_mem_rw_with_rand_reset.1077392803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/12.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_csr_rw.34627832 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 48343314 ps |
| CPU time | 0.64 seconds |
| Started | Sep 03 11:37:40 PM UTC 24 |
| Finished | Sep 03 11:37:41 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34627832 -assert nopostproc +UVM_TESTNAME=rv_ti mer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.34627832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/12.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_intr_test.1380618591 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 12845325 ps |
| CPU time | 0.65 seconds |
| Started | Sep 03 11:37:40 PM UTC 24 |
| Finished | Sep 03 11:37:41 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380618591 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1380618591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/12.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1732912493 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 125618279 ps |
| CPU time | 0.84 seconds |
| Started | Sep 03 11:37:40 PM UTC 24 |
| Finished | Sep 03 11:37:42 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732912493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_same_csr_outstanding.1732912493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/12.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_errors.1829269915 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 69034042 ps |
| CPU time | 2.81 seconds |
| Started | Sep 03 11:37:40 PM UTC 24 |
| Finished | Sep 03 11:37:43 PM UTC 24 |
| Peak memory | 200724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829269915 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1829269915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/12.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3903686529 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 408638945 ps |
| CPU time | 1.49 seconds |
| Started | Sep 03 11:37:40 PM UTC 24 |
| Finished | Sep 03 11:37:42 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903686529 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_intg_err.3903686529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/12.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2286742454 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 22857334 ps |
| CPU time | 0.67 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:43 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2286742454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_c sr_mem_rw_with_rand_reset.2286742454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/13.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_csr_rw.2533121797 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 27040659 ps |
| CPU time | 0.62 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:43 PM UTC 24 |
| Peak memory | 199048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533121797 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2533121797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/13.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_intr_test.2413927107 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 44308006 ps |
| CPU time | 0.74 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:43 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413927107 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2413927107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/13.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1222375581 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 27758102 ps |
| CPU time | 0.76 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:43 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222375581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_same_csr_outstanding.1222375581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/13.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_errors.3339268480 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 98313270 ps |
| CPU time | 2.06 seconds |
| Started | Sep 03 11:37:40 PM UTC 24 |
| Finished | Sep 03 11:37:43 PM UTC 24 |
| Peak memory | 200672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339268480 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3339268480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/13.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/13.rv_timer_tl_intg_err.41610321 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 102129246 ps |
| CPU time | 0.78 seconds |
| Started | Sep 03 11:37:40 PM UTC 24 |
| Finished | Sep 03 11:37:42 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41610321 -assert nopostproc +UVM_TESTN AME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_intg_err.41610321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/13.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1699618889 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 55997573 ps |
| CPU time | 0.73 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:43 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1699618889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_c sr_mem_rw_with_rand_reset.1699618889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/14.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_csr_rw.1814684021 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 40610858 ps |
| CPU time | 0.67 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:43 PM UTC 24 |
| Peak memory | 199048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814684021 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1814684021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/14.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_intr_test.2376561470 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 58705187 ps |
| CPU time | 0.61 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:43 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376561470 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2376561470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/14.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.609945892 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 14608721 ps |
| CPU time | 0.84 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:43 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609945892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_same_csr_outstanding.609945892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/14.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_errors.4215788074 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 237231813 ps |
| CPU time | 1.41 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:44 PM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215788074 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.4215788074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/14.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1974364649 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 174511663 ps |
| CPU time | 1.41 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:44 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974364649 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_intg_err.1974364649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/14.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3111472480 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 72859759 ps |
| CPU time | 1.01 seconds |
| Started | Sep 03 11:37:43 PM UTC 24 |
| Finished | Sep 03 11:37:45 PM UTC 24 |
| Peak memory | 199292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3111472480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_c sr_mem_rw_with_rand_reset.3111472480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/15.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_csr_rw.1690005872 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 56978215 ps |
| CPU time | 0.68 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:43 PM UTC 24 |
| Peak memory | 198664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690005872 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1690005872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/15.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_intr_test.3954175696 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 31037033 ps |
| CPU time | 0.63 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:43 PM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954175696 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3954175696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/15.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1918850030 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 156668557 ps |
| CPU time | 0.81 seconds |
| Started | Sep 03 11:37:42 PM UTC 24 |
| Finished | Sep 03 11:37:44 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918850030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_same_csr_outstanding.1918850030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/15.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_errors.3610514856 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 36747678 ps |
| CPU time | 1.58 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:44 PM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610514856 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3610514856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/15.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3967508649 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 48337352 ps |
| CPU time | 0.87 seconds |
| Started | Sep 03 11:37:41 PM UTC 24 |
| Finished | Sep 03 11:37:43 PM UTC 24 |
| Peak memory | 198704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967508649 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_intg_err.3967508649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/15.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.143699982 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 53921862 ps |
| CPU time | 0.91 seconds |
| Started | Sep 03 11:37:43 PM UTC 24 |
| Finished | Sep 03 11:37:45 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=143699982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_cs r_mem_rw_with_rand_reset.143699982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/16.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_csr_rw.881932574 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 18994535 ps |
| CPU time | 0.62 seconds |
| Started | Sep 03 11:37:43 PM UTC 24 |
| Finished | Sep 03 11:37:44 PM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881932574 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.881932574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/16.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_intr_test.1289763792 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 84040387 ps |
| CPU time | 0.57 seconds |
| Started | Sep 03 11:37:43 PM UTC 24 |
| Finished | Sep 03 11:37:44 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289763792 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1289763792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/16.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3165385693 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 71238143 ps |
| CPU time | 0.95 seconds |
| Started | Sep 03 11:37:43 PM UTC 24 |
| Finished | Sep 03 11:37:45 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165385693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_same_csr_outstanding.3165385693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/16.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_errors.2838904684 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 36204144 ps |
| CPU time | 0.96 seconds |
| Started | Sep 03 11:37:43 PM UTC 24 |
| Finished | Sep 03 11:37:45 PM UTC 24 |
| Peak memory | 199088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838904684 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2838904684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/16.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1334967948 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 361132411 ps |
| CPU time | 1.07 seconds |
| Started | Sep 03 11:37:43 PM UTC 24 |
| Finished | Sep 03 11:37:45 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334967948 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_intg_err.1334967948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/16.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.682672181 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 65499255 ps |
| CPU time | 0.97 seconds |
| Started | Sep 03 11:37:44 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=682672181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_cs r_mem_rw_with_rand_reset.682672181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/17.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_csr_rw.2283239673 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 23559099 ps |
| CPU time | 0.61 seconds |
| Started | Sep 03 11:37:43 PM UTC 24 |
| Finished | Sep 03 11:37:45 PM UTC 24 |
| Peak memory | 199048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283239673 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2283239673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/17.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_intr_test.1255162403 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 47004066 ps |
| CPU time | 0.77 seconds |
| Started | Sep 03 11:37:43 PM UTC 24 |
| Finished | Sep 03 11:37:45 PM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255162403 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1255162403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/17.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2595556795 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 543779489 ps |
| CPU time | 0.86 seconds |
| Started | Sep 03 11:37:43 PM UTC 24 |
| Finished | Sep 03 11:37:45 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595556795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_same_csr_outstanding.2595556795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/17.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_errors.602204733 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 96703521 ps |
| CPU time | 2.29 seconds |
| Started | Sep 03 11:37:43 PM UTC 24 |
| Finished | Sep 03 11:37:46 PM UTC 24 |
| Peak memory | 202996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602204733 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.602204733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/17.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/17.rv_timer_tl_intg_err.597768377 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 179921548 ps |
| CPU time | 0.91 seconds |
| Started | Sep 03 11:37:43 PM UTC 24 |
| Finished | Sep 03 11:37:45 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597768377 -assert nopostproc +UVM_TEST NAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_intg_err.597768377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/17.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1011831238 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 40959100 ps |
| CPU time | 1.02 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1011831238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_c sr_mem_rw_with_rand_reset.1011831238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/18.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_csr_rw.735880834 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 19216538 ps |
| CPU time | 0.56 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:46 PM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735880834 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.735880834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/18.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_intr_test.2716243346 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 24922917 ps |
| CPU time | 0.53 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:46 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716243346 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2716243346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/18.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3436466804 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 52058145 ps |
| CPU time | 0.67 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436466804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_same_csr_outstanding.3436466804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/18.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_errors.3489122449 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 44282675 ps |
| CPU time | 2.03 seconds |
| Started | Sep 03 11:37:44 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 202660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489122449 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3489122449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/18.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2014230065 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 182164416 ps |
| CPU time | 1.18 seconds |
| Started | Sep 03 11:37:44 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014230065 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_intg_err.2014230065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/18.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1361134059 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 27007100 ps |
| CPU time | 0.79 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1361134059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_c sr_mem_rw_with_rand_reset.1361134059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/19.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_csr_rw.2840016401 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 17111602 ps |
| CPU time | 0.6 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840016401 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2840016401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/19.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_intr_test.3509131353 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 53848529 ps |
| CPU time | 0.52 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509131353 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3509131353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/19.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2549551920 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 20480860 ps |
| CPU time | 0.64 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549551920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_same_csr_outstanding.2549551920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/19.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_errors.2106739546 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 254509413 ps |
| CPU time | 2.33 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 200872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106739546 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2106739546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/19.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2547056484 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 518527628 ps |
| CPU time | 1.4 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547056484 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_intg_err.2547056484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/19.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1519343200 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 118740087 ps |
| CPU time | 1.04 seconds |
| Started | Sep 03 11:37:30 PM UTC 24 |
| Finished | Sep 03 11:37:33 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519343200 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasing.1519343200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.942556292 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 69042904 ps |
| CPU time | 1.42 seconds |
| Started | Sep 03 11:37:30 PM UTC 24 |
| Finished | Sep 03 11:37:33 PM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942556292 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_bash.942556292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2115714865 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 25143022 ps |
| CPU time | 0.77 seconds |
| Started | Sep 03 11:37:30 PM UTC 24 |
| Finished | Sep 03 11:37:32 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115714865 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_reset.2115714865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3019669054 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 59534267 ps |
| CPU time | 1.03 seconds |
| Started | Sep 03 11:37:30 PM UTC 24 |
| Finished | Sep 03 11:37:33 PM UTC 24 |
| Peak memory | 198704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3019669054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_cs r_mem_rw_with_rand_reset.3019669054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_csr_rw.2005386610 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 52049063 ps |
| CPU time | 0.78 seconds |
| Started | Sep 03 11:37:30 PM UTC 24 |
| Finished | Sep 03 11:37:32 PM UTC 24 |
| Peak memory | 198848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005386610 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2005386610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_intr_test.2571685032 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 13757937 ps |
| CPU time | 0.74 seconds |
| Started | Sep 03 11:37:30 PM UTC 24 |
| Finished | Sep 03 11:37:32 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571685032 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2571685032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2012793022 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 26879757 ps |
| CPU time | 0.71 seconds |
| Started | Sep 03 11:37:30 PM UTC 24 |
| Finished | Sep 03 11:37:32 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012793022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_same_csr_outstanding.2012793022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_errors.3102976544 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 216662214 ps |
| CPU time | 2.93 seconds |
| Started | Sep 03 11:37:30 PM UTC 24 |
| Finished | Sep 03 11:37:34 PM UTC 24 |
| Peak memory | 200680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102976544 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3102976544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3577783350 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 42818882 ps |
| CPU time | 0.84 seconds |
| Started | Sep 03 11:37:30 PM UTC 24 |
| Finished | Sep 03 11:37:32 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577783350 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_intg_err.3577783350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/20.rv_timer_intr_test.3485834010 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 12767970 ps |
| CPU time | 0.64 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485834010 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3485834010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/20.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/21.rv_timer_intr_test.1972878418 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 15128028 ps |
| CPU time | 0.57 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972878418 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1972878418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/21.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/22.rv_timer_intr_test.1411383577 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 31237873 ps |
| CPU time | 0.53 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411383577 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1411383577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/22.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/23.rv_timer_intr_test.844072427 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 38005543 ps |
| CPU time | 0.59 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844072427 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.844072427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/23.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/24.rv_timer_intr_test.552288310 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 24719685 ps |
| CPU time | 0.51 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552288310 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.552288310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/24.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/25.rv_timer_intr_test.2327593026 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 14279641 ps |
| CPU time | 0.52 seconds |
| Started | Sep 03 11:37:45 PM UTC 24 |
| Finished | Sep 03 11:37:47 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327593026 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2327593026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/25.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/26.rv_timer_intr_test.1257656843 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 56492481 ps |
| CPU time | 0.56 seconds |
| Started | Sep 03 11:37:46 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257656843 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1257656843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/26.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/27.rv_timer_intr_test.1204466100 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 20483211 ps |
| CPU time | 0.59 seconds |
| Started | Sep 03 11:37:46 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204466100 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1204466100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/27.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/28.rv_timer_intr_test.843054012 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 32282624 ps |
| CPU time | 0.52 seconds |
| Started | Sep 03 11:37:46 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 198856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843054012 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.843054012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/28.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/29.rv_timer_intr_test.821282024 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 13377639 ps |
| CPU time | 0.56 seconds |
| Started | Sep 03 11:37:46 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821282024 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.821282024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/29.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2002818823 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 77555022 ps |
| CPU time | 0.75 seconds |
| Started | Sep 03 11:37:32 PM UTC 24 |
| Finished | Sep 03 11:37:34 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002818823 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_aliasing.2002818823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1236914290 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 706453560 ps |
| CPU time | 2.25 seconds |
| Started | Sep 03 11:37:31 PM UTC 24 |
| Finished | Sep 03 11:37:34 PM UTC 24 |
| Peak memory | 200944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236914290 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_bash.1236914290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.595428488 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 52653918 ps |
| CPU time | 0.62 seconds |
| Started | Sep 03 11:37:31 PM UTC 24 |
| Finished | Sep 03 11:37:32 PM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595428488 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_reset.595428488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2677796572 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 160006138 ps |
| CPU time | 0.95 seconds |
| Started | Sep 03 11:37:33 PM UTC 24 |
| Finished | Sep 03 11:37:35 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2677796572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_cs r_mem_rw_with_rand_reset.2677796572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_csr_rw.3086597229 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 46164946 ps |
| CPU time | 0.73 seconds |
| Started | Sep 03 11:37:31 PM UTC 24 |
| Finished | Sep 03 11:37:33 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086597229 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3086597229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_intr_test.4211507207 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 37130874 ps |
| CPU time | 0.59 seconds |
| Started | Sep 03 11:37:31 PM UTC 24 |
| Finished | Sep 03 11:37:32 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211507207 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.4211507207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3291239039 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 74173182 ps |
| CPU time | 0.95 seconds |
| Started | Sep 03 11:37:33 PM UTC 24 |
| Finished | Sep 03 11:37:35 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291239039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_same_csr_outstanding.3291239039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_errors.4272136002 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 147886591 ps |
| CPU time | 1.56 seconds |
| Started | Sep 03 11:37:30 PM UTC 24 |
| Finished | Sep 03 11:37:33 PM UTC 24 |
| Peak memory | 198720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272136002 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.4272136002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2348782333 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 150756534 ps |
| CPU time | 1.4 seconds |
| Started | Sep 03 11:37:31 PM UTC 24 |
| Finished | Sep 03 11:37:33 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348782333 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_intg_err.2348782333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/30.rv_timer_intr_test.3482320006 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 28831800 ps |
| CPU time | 0.54 seconds |
| Started | Sep 03 11:37:46 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482320006 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3482320006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/30.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/31.rv_timer_intr_test.558729709 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 23127238 ps |
| CPU time | 0.56 seconds |
| Started | Sep 03 11:37:46 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 198872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558729709 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.558729709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/31.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/32.rv_timer_intr_test.174914542 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 14944102 ps |
| CPU time | 0.51 seconds |
| Started | Sep 03 11:37:46 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 198856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174914542 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.174914542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/32.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/33.rv_timer_intr_test.3037935351 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 50123307 ps |
| CPU time | 0.6 seconds |
| Started | Sep 03 11:37:46 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037935351 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3037935351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/33.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/34.rv_timer_intr_test.921709669 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 38869591 ps |
| CPU time | 0.51 seconds |
| Started | Sep 03 11:37:46 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 198516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921709669 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.921709669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/34.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/35.rv_timer_intr_test.2657832939 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 58345286 ps |
| CPU time | 0.61 seconds |
| Started | Sep 03 11:37:46 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657832939 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2657832939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/35.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/36.rv_timer_intr_test.3543181042 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 38162481 ps |
| CPU time | 0.56 seconds |
| Started | Sep 03 11:37:46 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543181042 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3543181042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/36.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/37.rv_timer_intr_test.3557293574 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 13626689 ps |
| CPU time | 0.53 seconds |
| Started | Sep 03 11:37:46 PM UTC 24 |
| Finished | Sep 03 11:37:48 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557293574 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3557293574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/37.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/38.rv_timer_intr_test.971934035 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 109876069 ps |
| CPU time | 0.56 seconds |
| Started | Sep 03 11:37:47 PM UTC 24 |
| Finished | Sep 03 11:37:49 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971934035 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.971934035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/38.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/39.rv_timer_intr_test.2334457449 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 21435551 ps |
| CPU time | 0.68 seconds |
| Started | Sep 03 11:37:48 PM UTC 24 |
| Finished | Sep 03 11:37:49 PM UTC 24 |
| Peak memory | 198600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334457449 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2334457449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/39.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3439836598 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 140200631 ps |
| CPU time | 0.68 seconds |
| Started | Sep 03 11:37:34 PM UTC 24 |
| Finished | Sep 03 11:37:36 PM UTC 24 |
| Peak memory | 198432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439836598 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasing.3439836598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1969614331 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 278682877 ps |
| CPU time | 3.29 seconds |
| Started | Sep 03 11:37:33 PM UTC 24 |
| Finished | Sep 03 11:37:37 PM UTC 24 |
| Peak memory | 200420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969614331 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bash.1969614331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3746540586 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 17660484 ps |
| CPU time | 0.81 seconds |
| Started | Sep 03 11:37:33 PM UTC 24 |
| Finished | Sep 03 11:37:35 PM UTC 24 |
| Peak memory | 199040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746540586 -assert nopostproc +UVM_TESTNA ME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_reset.3746540586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.982776103 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 89913949 ps |
| CPU time | 1.29 seconds |
| Started | Sep 03 11:37:34 PM UTC 24 |
| Finished | Sep 03 11:37:36 PM UTC 24 |
| Peak memory | 198428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=982776103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr _mem_rw_with_rand_reset.982776103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_csr_rw.423706316 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 51648693 ps |
| CPU time | 0.75 seconds |
| Started | Sep 03 11:37:33 PM UTC 24 |
| Finished | Sep 03 11:37:35 PM UTC 24 |
| Peak memory | 198768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423706316 -assert nopostproc +UVM_TESTNAME=rv_t imer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.423706316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_intr_test.818398301 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 42777089 ps |
| CPU time | 0.6 seconds |
| Started | Sep 03 11:37:33 PM UTC 24 |
| Finished | Sep 03 11:37:34 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818398301 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.818398301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1673412765 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 113084257 ps |
| CPU time | 0.91 seconds |
| Started | Sep 03 11:37:34 PM UTC 24 |
| Finished | Sep 03 11:37:36 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673412765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_same_csr_outstanding.1673412765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_errors.750520092 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 217106269 ps |
| CPU time | 3.12 seconds |
| Started | Sep 03 11:37:33 PM UTC 24 |
| Finished | Sep 03 11:37:37 PM UTC 24 |
| Peak memory | 202724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750520092 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.750520092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1812748796 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 533428010 ps |
| CPU time | 0.82 seconds |
| Started | Sep 03 11:37:33 PM UTC 24 |
| Finished | Sep 03 11:37:34 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812748796 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_intg_err.1812748796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/40.rv_timer_intr_test.897607685 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 13947568 ps |
| CPU time | 0.66 seconds |
| Started | Sep 03 11:37:48 PM UTC 24 |
| Finished | Sep 03 11:37:49 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897607685 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.897607685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/40.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/41.rv_timer_intr_test.384199491 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 54401565 ps |
| CPU time | 0.56 seconds |
| Started | Sep 03 11:37:48 PM UTC 24 |
| Finished | Sep 03 11:37:49 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384199491 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.384199491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/41.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/42.rv_timer_intr_test.1320878391 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 41840626 ps |
| CPU time | 0.55 seconds |
| Started | Sep 03 11:37:48 PM UTC 24 |
| Finished | Sep 03 11:37:49 PM UTC 24 |
| Peak memory | 198900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320878391 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1320878391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/42.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/43.rv_timer_intr_test.285837079 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 48292771 ps |
| CPU time | 0.62 seconds |
| Started | Sep 03 11:37:48 PM UTC 24 |
| Finished | Sep 03 11:37:49 PM UTC 24 |
| Peak memory | 198948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285837079 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.285837079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/43.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/44.rv_timer_intr_test.1412458264 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 21292265 ps |
| CPU time | 0.53 seconds |
| Started | Sep 03 11:37:48 PM UTC 24 |
| Finished | Sep 03 11:37:49 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412458264 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.1412458264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/44.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/45.rv_timer_intr_test.1932180316 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 16643389 ps |
| CPU time | 0.57 seconds |
| Started | Sep 03 11:37:48 PM UTC 24 |
| Finished | Sep 03 11:37:49 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932180316 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1932180316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/45.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/46.rv_timer_intr_test.631248190 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 17502359 ps |
| CPU time | 0.55 seconds |
| Started | Sep 03 11:37:48 PM UTC 24 |
| Finished | Sep 03 11:37:49 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631248190 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.631248190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/46.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/47.rv_timer_intr_test.2209409615 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 47880503 ps |
| CPU time | 0.69 seconds |
| Started | Sep 03 11:37:48 PM UTC 24 |
| Finished | Sep 03 11:37:50 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209409615 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2209409615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/47.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/48.rv_timer_intr_test.1960603071 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 13109308 ps |
| CPU time | 0.53 seconds |
| Started | Sep 03 11:37:48 PM UTC 24 |
| Finished | Sep 03 11:37:49 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960603071 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1960603071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/48.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/49.rv_timer_intr_test.1623693143 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 25760998 ps |
| CPU time | 0.48 seconds |
| Started | Sep 03 11:37:48 PM UTC 24 |
| Finished | Sep 03 11:37:50 PM UTC 24 |
| Peak memory | 198968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623693143 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1623693143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/49.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3946530176 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 38817407 ps |
| CPU time | 1.02 seconds |
| Started | Sep 03 11:37:34 PM UTC 24 |
| Finished | Sep 03 11:37:36 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3946530176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_cs r_mem_rw_with_rand_reset.3946530176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/5.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_csr_rw.2430070634 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 40631520 ps |
| CPU time | 0.82 seconds |
| Started | Sep 03 11:37:34 PM UTC 24 |
| Finished | Sep 03 11:37:36 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430070634 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2430070634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/5.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_intr_test.2873495135 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 24496980 ps |
| CPU time | 0.62 seconds |
| Started | Sep 03 11:37:34 PM UTC 24 |
| Finished | Sep 03 11:37:36 PM UTC 24 |
| Peak memory | 198648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873495135 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2873495135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/5.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.830136099 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 22541578 ps |
| CPU time | 0.86 seconds |
| Started | Sep 03 11:37:34 PM UTC 24 |
| Finished | Sep 03 11:37:36 PM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830136099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_same_csr_outstanding.830136099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/5.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_errors.720952575 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 196047197 ps |
| CPU time | 2.09 seconds |
| Started | Sep 03 11:37:34 PM UTC 24 |
| Finished | Sep 03 11:37:37 PM UTC 24 |
| Peak memory | 200616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720952575 -assert nopostproc +UVM_TESTNAME=rv_time r_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.720952575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/5.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3289687068 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 46646177 ps |
| CPU time | 0.93 seconds |
| Started | Sep 03 11:37:34 PM UTC 24 |
| Finished | Sep 03 11:37:36 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289687068 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_intg_err.3289687068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/5.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2136255379 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 167892042 ps |
| CPU time | 1.05 seconds |
| Started | Sep 03 11:37:36 PM UTC 24 |
| Finished | Sep 03 11:37:38 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2136255379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_cs r_mem_rw_with_rand_reset.2136255379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/6.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_csr_rw.3645841332 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 26449449 ps |
| CPU time | 0.7 seconds |
| Started | Sep 03 11:37:35 PM UTC 24 |
| Finished | Sep 03 11:37:36 PM UTC 24 |
| Peak memory | 198908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645841332 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3645841332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/6.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_intr_test.38809389 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 13569199 ps |
| CPU time | 0.68 seconds |
| Started | Sep 03 11:37:34 PM UTC 24 |
| Finished | Sep 03 11:37:36 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38809389 -assert nopostproc +UVM_TESTNAME=rv_timer _base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.38809389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/6.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1024640106 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 13649720 ps |
| CPU time | 0.76 seconds |
| Started | Sep 03 11:37:35 PM UTC 24 |
| Finished | Sep 03 11:37:36 PM UTC 24 |
| Peak memory | 198912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024640106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_same_csr_outstanding.1024640106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/6.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_errors.1128246657 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 131600546 ps |
| CPU time | 1.51 seconds |
| Started | Sep 03 11:37:34 PM UTC 24 |
| Finished | Sep 03 11:37:37 PM UTC 24 |
| Peak memory | 199100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128246657 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1128246657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/6.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2561285246 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 115793083 ps |
| CPU time | 1.39 seconds |
| Started | Sep 03 11:37:34 PM UTC 24 |
| Finished | Sep 03 11:37:37 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561285246 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_intg_err.2561285246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/6.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3655603596 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 36010631 ps |
| CPU time | 0.94 seconds |
| Started | Sep 03 11:37:36 PM UTC 24 |
| Finished | Sep 03 11:37:38 PM UTC 24 |
| Peak memory | 198972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3655603596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_cs r_mem_rw_with_rand_reset.3655603596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/7.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_csr_rw.3517180274 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 12651187 ps |
| CPU time | 0.69 seconds |
| Started | Sep 03 11:37:36 PM UTC 24 |
| Finished | Sep 03 11:37:38 PM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517180274 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3517180274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/7.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_intr_test.4256229024 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 34597259 ps |
| CPU time | 0.66 seconds |
| Started | Sep 03 11:37:36 PM UTC 24 |
| Finished | Sep 03 11:37:38 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256229024 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.4256229024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/7.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3796394464 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 18230852 ps |
| CPU time | 0.72 seconds |
| Started | Sep 03 11:37:36 PM UTC 24 |
| Finished | Sep 03 11:37:38 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796394464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_same_csr_outstanding.3796394464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/7.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_errors.2102443845 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 105275287 ps |
| CPU time | 1.94 seconds |
| Started | Sep 03 11:37:36 PM UTC 24 |
| Finished | Sep 03 11:37:39 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102443845 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2102443845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/7.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3462431094 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 188824276 ps |
| CPU time | 1.41 seconds |
| Started | Sep 03 11:37:36 PM UTC 24 |
| Finished | Sep 03 11:37:39 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462431094 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_intg_err.3462431094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/7.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2358359331 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 78911925 ps |
| CPU time | 0.73 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:40 PM UTC 24 |
| Peak memory | 198904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2358359331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_cs r_mem_rw_with_rand_reset.2358359331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/8.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_csr_rw.1434846635 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 13584119 ps |
| CPU time | 0.6 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:39 PM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434846635 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1434846635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/8.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_intr_test.2115188798 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 16653110 ps |
| CPU time | 0.52 seconds |
| Started | Sep 03 11:37:36 PM UTC 24 |
| Finished | Sep 03 11:37:38 PM UTC 24 |
| Peak memory | 198584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115188798 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2115188798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/8.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2029560150 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 22107291 ps |
| CPU time | 0.67 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:39 PM UTC 24 |
| Peak memory | 199108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029560150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_same_csr_outstanding.2029560150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/8.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_errors.1969682398 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 78494187 ps |
| CPU time | 1.66 seconds |
| Started | Sep 03 11:37:36 PM UTC 24 |
| Finished | Sep 03 11:37:39 PM UTC 24 |
| Peak memory | 200800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969682398 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1969682398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/8.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3587488486 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 126581901 ps |
| CPU time | 1.43 seconds |
| Started | Sep 03 11:37:36 PM UTC 24 |
| Finished | Sep 03 11:37:39 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587488486 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg_err.3587488486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/8.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2580795385 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 62324056 ps |
| CPU time | 1.18 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:40 PM UTC 24 |
| Peak memory | 198948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2580795385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_cs r_mem_rw_with_rand_reset.2580795385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/9.rv_timer_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_csr_rw.1460382016 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 14620058 ps |
| CPU time | 0.56 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:39 PM UTC 24 |
| Peak memory | 199044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460382016 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1460382016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/9.rv_timer_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_intr_test.3733192655 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 14508060 ps |
| CPU time | 0.7 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:40 PM UTC 24 |
| Peak memory | 198976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733192655 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3733192655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/9.rv_timer_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1198229094 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 20508025 ps |
| CPU time | 0.89 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:40 PM UTC 24 |
| Peak memory | 198852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198229094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_same_csr_outstanding.1198229094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/9.rv_timer_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_errors.2425766721 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 203671140 ps |
| CPU time | 3.13 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:42 PM UTC 24 |
| Peak memory | 202732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425766721 -assert nopostproc +UVM_TESTNAME=rv_tim er_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2425766721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/9.rv_timer_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1088112275 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 313108530 ps |
| CPU time | 0.86 seconds |
| Started | Sep 03 11:37:38 PM UTC 24 |
| Finished | Sep 03 11:37:40 PM UTC 24 |
| Peak memory | 199104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088112275 -assert nopostproc +UVM_TES TNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_intg_err.1088112275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/9.rv_timer_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/0.rv_timer_disabled.2609950558 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 128449958784 ps |
| CPU time | 189.11 seconds |
| Started | Sep 03 11:57:52 PM UTC 24 |
| Finished | Sep 04 12:01:04 AM UTC 24 |
| Peak memory | 199812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609950558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2609950558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/0.rv_timer_random_reset.3626514841 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 548122128593 ps |
| CPU time | 190.54 seconds |
| Started | Sep 03 11:57:53 PM UTC 24 |
| Finished | Sep 04 12:01:07 AM UTC 24 |
| Peak memory | 199584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626514841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3626514841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/0.rv_timer_stress_all.1734750848 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 413619077185 ps |
| CPU time | 215.18 seconds |
| Started | Sep 03 11:57:53 PM UTC 24 |
| Finished | Sep 04 12:01:32 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734750848 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.1734750848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/0.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/1.rv_timer_disabled.1348641256 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 191035845120 ps |
| CPU time | 177.91 seconds |
| Started | Sep 03 11:57:53 PM UTC 24 |
| Finished | Sep 04 12:00:54 AM UTC 24 |
| Peak memory | 199812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348641256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1348641256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/1.rv_timer_random_reset.4128566254 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 89485060646 ps |
| CPU time | 138.95 seconds |
| Started | Sep 03 11:57:54 PM UTC 24 |
| Finished | Sep 04 12:00:15 AM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128566254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.4128566254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/1.rv_timer_sec_cm.3001363992 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1539255583 ps |
| CPU time | 1.43 seconds |
| Started | Sep 03 11:57:54 PM UTC 24 |
| Finished | Sep 03 11:57:56 PM UTC 24 |
| Peak memory | 228936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001363992 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3001363992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/1.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/10.rv_timer_cfg_update_on_fly.31451165 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 125194978496 ps |
| CPU time | 267.41 seconds |
| Started | Sep 03 11:59:45 PM UTC 24 |
| Finished | Sep 04 12:04:17 AM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31451165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_cfg_update_on_fly.31451165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/10.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/10.rv_timer_disabled.3137779868 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 65792966694 ps |
| CPU time | 48.69 seconds |
| Started | Sep 03 11:59:38 PM UTC 24 |
| Finished | Sep 04 12:00:28 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137779868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3137779868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/10.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/10.rv_timer_stress_all.3078324469 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 496847210002 ps |
| CPU time | 249.67 seconds |
| Started | Sep 04 12:00:00 AM UTC 24 |
| Finished | Sep 04 12:04:13 AM UTC 24 |
| Peak memory | 199684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078324469 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.3078324469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/10.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/102.rv_timer_random.2143782226 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 81770280098 ps |
| CPU time | 80.78 seconds |
| Started | Sep 04 12:24:01 AM UTC 24 |
| Finished | Sep 04 12:25:24 AM UTC 24 |
| Peak memory | 199700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143782226 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2143782226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/102.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/104.rv_timer_random.3756012531 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 84022095138 ps |
| CPU time | 158.22 seconds |
| Started | Sep 04 12:24:15 AM UTC 24 |
| Finished | Sep 04 12:26:56 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756012531 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3756012531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/104.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/105.rv_timer_random.212039846 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 30467859705 ps |
| CPU time | 111 seconds |
| Started | Sep 04 12:24:18 AM UTC 24 |
| Finished | Sep 04 12:26:11 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212039846 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.212039846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/105.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/106.rv_timer_random.2206261450 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 12978561359 ps |
| CPU time | 46.15 seconds |
| Started | Sep 04 12:24:20 AM UTC 24 |
| Finished | Sep 04 12:25:08 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206261450 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2206261450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/106.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/107.rv_timer_random.1289776757 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 42901283688 ps |
| CPU time | 88.71 seconds |
| Started | Sep 04 12:24:23 AM UTC 24 |
| Finished | Sep 04 12:25:54 AM UTC 24 |
| Peak memory | 199868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289776757 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1289776757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/107.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/108.rv_timer_random.2069432593 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 728922324863 ps |
| CPU time | 1044.98 seconds |
| Started | Sep 04 12:24:36 AM UTC 24 |
| Finished | Sep 04 12:42:13 AM UTC 24 |
| Peak memory | 202612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069432593 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2069432593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/108.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/109.rv_timer_random.3124303077 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 381800464827 ps |
| CPU time | 311.93 seconds |
| Started | Sep 04 12:24:37 AM UTC 24 |
| Finished | Sep 04 12:29:54 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124303077 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3124303077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/109.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/11.rv_timer_cfg_update_on_fly.4268875284 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 978093349402 ps |
| CPU time | 506.83 seconds |
| Started | Sep 04 12:00:15 AM UTC 24 |
| Finished | Sep 04 12:08:48 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268875284 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_cfg_update_on_fly.4268875284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/11.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/11.rv_timer_disabled.1031880725 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 83451684633 ps |
| CPU time | 107.5 seconds |
| Started | Sep 04 12:00:09 AM UTC 24 |
| Finished | Sep 04 12:01:59 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031880725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1031880725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/11.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/11.rv_timer_random_reset.4090934220 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 23956387687 ps |
| CPU time | 196.18 seconds |
| Started | Sep 04 12:00:16 AM UTC 24 |
| Finished | Sep 04 12:03:36 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090934220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.4090934220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/11.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/11.rv_timer_stress_all.1306946051 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 108542100844 ps |
| CPU time | 102.28 seconds |
| Started | Sep 04 12:00:22 AM UTC 24 |
| Finished | Sep 04 12:02:06 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306946051 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.1306946051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/11.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/111.rv_timer_random.2095624240 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 36542931798 ps |
| CPU time | 63.78 seconds |
| Started | Sep 04 12:24:50 AM UTC 24 |
| Finished | Sep 04 12:25:55 AM UTC 24 |
| Peak memory | 199700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095624240 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2095624240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/111.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/112.rv_timer_random.4291325944 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 286278533721 ps |
| CPU time | 100.2 seconds |
| Started | Sep 04 12:24:57 AM UTC 24 |
| Finished | Sep 04 12:26:39 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291325944 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.4291325944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/112.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/115.rv_timer_random.2582674556 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 335323722216 ps |
| CPU time | 1048.04 seconds |
| Started | Sep 04 12:25:13 AM UTC 24 |
| Finished | Sep 04 12:42:54 AM UTC 24 |
| Peak memory | 202544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582674556 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2582674556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/115.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/116.rv_timer_random.3284842394 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 72220532937 ps |
| CPU time | 73.67 seconds |
| Started | Sep 04 12:25:18 AM UTC 24 |
| Finished | Sep 04 12:26:34 AM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284842394 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3284842394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/116.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/117.rv_timer_random.4177360531 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 272097855564 ps |
| CPU time | 166.81 seconds |
| Started | Sep 04 12:25:24 AM UTC 24 |
| Finished | Sep 04 12:28:14 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177360531 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4177360531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/117.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/118.rv_timer_random.1870556045 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 177091697837 ps |
| CPU time | 120.33 seconds |
| Started | Sep 04 12:25:32 AM UTC 24 |
| Finished | Sep 04 12:27:34 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870556045 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1870556045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/118.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/119.rv_timer_random.929461700 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 405961241228 ps |
| CPU time | 1141.41 seconds |
| Started | Sep 04 12:25:34 AM UTC 24 |
| Finished | Sep 04 12:44:48 AM UTC 24 |
| Peak memory | 202548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929461700 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.929461700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/119.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/12.rv_timer_disabled.7716974 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 130143159391 ps |
| CPU time | 132.79 seconds |
| Started | Sep 04 12:00:26 AM UTC 24 |
| Finished | Sep 04 12:02:41 AM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7716974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_S EQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.7716974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/12.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/12.rv_timer_random_reset.1809134762 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 1010938659 ps |
| CPU time | 3.4 seconds |
| Started | Sep 04 12:00:29 AM UTC 24 |
| Finished | Sep 04 12:00:34 AM UTC 24 |
| Peak memory | 199476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809134762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1809134762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/12.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/12.rv_timer_stress_all_with_rand_reset.3317474893 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2511170406 ps |
| CPU time | 28.58 seconds |
| Started | Sep 04 12:00:32 AM UTC 24 |
| Finished | Sep 04 12:01:03 AM UTC 24 |
| Peak memory | 204088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3317474893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 12.rv_timer_stress_all_with_rand_reset.3317474893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/12.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/122.rv_timer_random.253898479 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1634097461 ps |
| CPU time | 6.09 seconds |
| Started | Sep 04 12:25:54 AM UTC 24 |
| Finished | Sep 04 12:26:01 AM UTC 24 |
| Peak memory | 199532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253898479 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.253898479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/122.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/124.rv_timer_random.192999490 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 218269914017 ps |
| CPU time | 148.25 seconds |
| Started | Sep 04 12:25:56 AM UTC 24 |
| Finished | Sep 04 12:28:27 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192999490 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.192999490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/124.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/125.rv_timer_random.3216730082 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 23274749989 ps |
| CPU time | 42.73 seconds |
| Started | Sep 04 12:25:59 AM UTC 24 |
| Finished | Sep 04 12:26:44 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216730082 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3216730082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/125.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/127.rv_timer_random.3612223511 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 45503491494 ps |
| CPU time | 108.43 seconds |
| Started | Sep 04 12:26:12 AM UTC 24 |
| Finished | Sep 04 12:28:02 AM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612223511 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3612223511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/127.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/128.rv_timer_random.3125708448 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 375620049236 ps |
| CPU time | 143.89 seconds |
| Started | Sep 04 12:26:19 AM UTC 24 |
| Finished | Sep 04 12:28:45 AM UTC 24 |
| Peak memory | 199700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125708448 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3125708448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/128.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/13.rv_timer_disabled.3258134429 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 121656999157 ps |
| CPU time | 175.22 seconds |
| Started | Sep 04 12:00:55 AM UTC 24 |
| Finished | Sep 04 12:03:53 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258134429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3258134429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/13.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/13.rv_timer_random.2294510198 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 48843399188 ps |
| CPU time | 21.33 seconds |
| Started | Sep 04 12:00:45 AM UTC 24 |
| Finished | Sep 04 12:01:07 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294510198 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2294510198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/13.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/13.rv_timer_random_reset.1931413653 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 225467174 ps |
| CPU time | 1.66 seconds |
| Started | Sep 04 12:01:03 AM UTC 24 |
| Finished | Sep 04 12:01:06 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931413653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1931413653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/13.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/13.rv_timer_stress_all.300244649 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 438226398529 ps |
| CPU time | 757.25 seconds |
| Started | Sep 04 12:01:04 AM UTC 24 |
| Finished | Sep 04 12:13:51 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300244649 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.300244649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/13.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/130.rv_timer_random.346464994 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 73768199998 ps |
| CPU time | 254.68 seconds |
| Started | Sep 04 12:26:34 AM UTC 24 |
| Finished | Sep 04 12:30:52 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346464994 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.346464994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/130.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/132.rv_timer_random.583542723 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 74965031489 ps |
| CPU time | 170.89 seconds |
| Started | Sep 04 12:26:40 AM UTC 24 |
| Finished | Sep 04 12:29:34 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583542723 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.583542723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/132.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/133.rv_timer_random.2179262955 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 895496309065 ps |
| CPU time | 474.87 seconds |
| Started | Sep 04 12:26:41 AM UTC 24 |
| Finished | Sep 04 12:34:42 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179262955 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2179262955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/133.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/134.rv_timer_random.1911109778 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 116480618032 ps |
| CPU time | 285.24 seconds |
| Started | Sep 04 12:26:45 AM UTC 24 |
| Finished | Sep 04 12:31:34 AM UTC 24 |
| Peak memory | 199868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911109778 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1911109778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/134.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/136.rv_timer_random.1228884360 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 27505099573 ps |
| CPU time | 154.04 seconds |
| Started | Sep 04 12:26:57 AM UTC 24 |
| Finished | Sep 04 12:29:33 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228884360 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1228884360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/136.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/137.rv_timer_random.189973378 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 198788550245 ps |
| CPU time | 148.05 seconds |
| Started | Sep 04 12:27:10 AM UTC 24 |
| Finished | Sep 04 12:29:40 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189973378 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.189973378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/137.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/138.rv_timer_random.1098885312 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 229089373471 ps |
| CPU time | 224.81 seconds |
| Started | Sep 04 12:27:30 AM UTC 24 |
| Finished | Sep 04 12:31:18 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098885312 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1098885312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/138.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/139.rv_timer_random.4150166768 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 144218757828 ps |
| CPU time | 226.83 seconds |
| Started | Sep 04 12:27:31 AM UTC 24 |
| Finished | Sep 04 12:31:22 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150166768 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.4150166768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/139.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/14.rv_timer_disabled.134760093 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 42416607930 ps |
| CPU time | 77.11 seconds |
| Started | Sep 04 12:01:07 AM UTC 24 |
| Finished | Sep 04 12:02:26 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134760093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.134760093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/14.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/14.rv_timer_random_reset.3653915647 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 595980441 ps |
| CPU time | 1.27 seconds |
| Started | Sep 04 12:01:08 AM UTC 24 |
| Finished | Sep 04 12:01:10 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653915647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3653915647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/14.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/14.rv_timer_stress_all.4272142493 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 531429506613 ps |
| CPU time | 729.41 seconds |
| Started | Sep 04 12:01:14 AM UTC 24 |
| Finished | Sep 04 12:13:32 AM UTC 24 |
| Peak memory | 202352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272142493 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.4272142493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/14.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/141.rv_timer_random.4040158590 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 1457186632453 ps |
| CPU time | 605.96 seconds |
| Started | Sep 04 12:27:55 AM UTC 24 |
| Finished | Sep 04 12:38:08 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040158590 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.4040158590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/141.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/142.rv_timer_random.2088055378 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 216237456321 ps |
| CPU time | 361.9 seconds |
| Started | Sep 04 12:28:01 AM UTC 24 |
| Finished | Sep 04 12:34:07 AM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088055378 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2088055378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/142.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/143.rv_timer_random.3965738141 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 444972508563 ps |
| CPU time | 424.44 seconds |
| Started | Sep 04 12:28:03 AM UTC 24 |
| Finished | Sep 04 12:35:12 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965738141 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3965738141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/143.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/145.rv_timer_random.2354129309 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 103695367537 ps |
| CPU time | 334.12 seconds |
| Started | Sep 04 12:28:16 AM UTC 24 |
| Finished | Sep 04 12:33:55 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354129309 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2354129309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/145.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/146.rv_timer_random.3537606449 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 839145432757 ps |
| CPU time | 371.29 seconds |
| Started | Sep 04 12:28:17 AM UTC 24 |
| Finished | Sep 04 12:34:33 AM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537606449 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3537606449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/146.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/147.rv_timer_random.1654477178 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 189995339086 ps |
| CPU time | 117.6 seconds |
| Started | Sep 04 12:28:28 AM UTC 24 |
| Finished | Sep 04 12:30:28 AM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654477178 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1654477178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/147.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/148.rv_timer_random.2020014578 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 125612906461 ps |
| CPU time | 184 seconds |
| Started | Sep 04 12:28:46 AM UTC 24 |
| Finished | Sep 04 12:31:53 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020014578 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2020014578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/148.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/149.rv_timer_random.2044568296 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 83942576791 ps |
| CPU time | 470.44 seconds |
| Started | Sep 04 12:29:12 AM UTC 24 |
| Finished | Sep 04 12:37:08 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044568296 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2044568296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/149.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/15.rv_timer_cfg_update_on_fly.1482974585 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 1071641497335 ps |
| CPU time | 661.88 seconds |
| Started | Sep 04 12:01:27 AM UTC 24 |
| Finished | Sep 04 12:12:36 AM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482974585 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_cfg_update_on_fly.1482974585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/15.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/15.rv_timer_disabled.2469562905 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 102259818901 ps |
| CPU time | 146.16 seconds |
| Started | Sep 04 12:01:22 AM UTC 24 |
| Finished | Sep 04 12:03:51 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469562905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2469562905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/15.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/15.rv_timer_random.3541143250 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 186857994905 ps |
| CPU time | 288.23 seconds |
| Started | Sep 04 12:01:19 AM UTC 24 |
| Finished | Sep 04 12:06:11 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541143250 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3541143250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/15.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/15.rv_timer_random_reset.2466522082 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 12746970609 ps |
| CPU time | 107.2 seconds |
| Started | Sep 04 12:01:27 AM UTC 24 |
| Finished | Sep 04 12:03:16 AM UTC 24 |
| Peak memory | 199788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466522082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.2466522082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/15.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/15.rv_timer_stress_all.4162975542 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 288715426487 ps |
| CPU time | 567.42 seconds |
| Started | Sep 04 12:01:30 AM UTC 24 |
| Finished | Sep 04 12:11:05 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162975542 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.4162975542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/15.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/151.rv_timer_random.1039940770 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 327524574336 ps |
| CPU time | 553.85 seconds |
| Started | Sep 04 12:29:25 AM UTC 24 |
| Finished | Sep 04 12:38:45 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039940770 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1039940770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/151.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/152.rv_timer_random.2421344110 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 334289060776 ps |
| CPU time | 798.02 seconds |
| Started | Sep 04 12:29:34 AM UTC 24 |
| Finished | Sep 04 12:43:01 AM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421344110 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2421344110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/152.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/154.rv_timer_random.58997671 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 51839267209 ps |
| CPU time | 445.1 seconds |
| Started | Sep 04 12:29:41 AM UTC 24 |
| Finished | Sep 04 12:37:12 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58997671 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.58997671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/154.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/156.rv_timer_random.840263895 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 158963344885 ps |
| CPU time | 304.53 seconds |
| Started | Sep 04 12:30:00 AM UTC 24 |
| Finished | Sep 04 12:35:09 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840263895 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.840263895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/156.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/157.rv_timer_random.1749602592 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 188765902643 ps |
| CPU time | 437.5 seconds |
| Started | Sep 04 12:30:02 AM UTC 24 |
| Finished | Sep 04 12:37:25 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749602592 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1749602592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/157.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/158.rv_timer_random.43042625 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 55042492747 ps |
| CPU time | 149.87 seconds |
| Started | Sep 04 12:30:17 AM UTC 24 |
| Finished | Sep 04 12:32:50 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43042625 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.43042625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/158.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/159.rv_timer_random.1599571799 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 412411758956 ps |
| CPU time | 2062.12 seconds |
| Started | Sep 04 12:30:29 AM UTC 24 |
| Finished | Sep 04 01:05:14 AM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599571799 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1599571799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/159.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/16.rv_timer_cfg_update_on_fly.955999195 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 176359082262 ps |
| CPU time | 379.01 seconds |
| Started | Sep 04 12:01:34 AM UTC 24 |
| Finished | Sep 04 12:07:58 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955999195 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_cfg_update_on_fly.955999195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/16.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/16.rv_timer_disabled.2284958188 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 189095648553 ps |
| CPU time | 436.76 seconds |
| Started | Sep 04 12:01:34 AM UTC 24 |
| Finished | Sep 04 12:08:56 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284958188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2284958188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/16.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/16.rv_timer_random.93442205 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 187036851776 ps |
| CPU time | 691.39 seconds |
| Started | Sep 04 12:01:33 AM UTC 24 |
| Finished | Sep 04 12:13:12 AM UTC 24 |
| Peak memory | 199912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93442205 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.93442205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/16.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/16.rv_timer_random_reset.1990073303 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 339398045435 ps |
| CPU time | 236.9 seconds |
| Started | Sep 04 12:01:46 AM UTC 24 |
| Finished | Sep 04 12:05:46 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990073303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1990073303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/16.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/16.rv_timer_stress_all.1669021112 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 864641523197 ps |
| CPU time | 286.17 seconds |
| Started | Sep 04 12:01:54 AM UTC 24 |
| Finished | Sep 04 12:06:44 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669021112 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.1669021112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/16.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/160.rv_timer_random.1060503853 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 55779840678 ps |
| CPU time | 430.79 seconds |
| Started | Sep 04 12:30:53 AM UTC 24 |
| Finished | Sep 04 12:38:09 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060503853 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1060503853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/160.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/162.rv_timer_random.1900410389 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 108859036445 ps |
| CPU time | 419.51 seconds |
| Started | Sep 04 12:31:15 AM UTC 24 |
| Finished | Sep 04 12:38:21 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900410389 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1900410389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/162.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/163.rv_timer_random.311676657 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 24087814535 ps |
| CPU time | 259.41 seconds |
| Started | Sep 04 12:31:15 AM UTC 24 |
| Finished | Sep 04 12:35:39 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311676657 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.311676657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/163.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/164.rv_timer_random.218840299 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 849006207378 ps |
| CPU time | 729.81 seconds |
| Started | Sep 04 12:31:19 AM UTC 24 |
| Finished | Sep 04 12:43:37 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218840299 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.218840299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/164.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/165.rv_timer_random.3924503477 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 134791994210 ps |
| CPU time | 205.45 seconds |
| Started | Sep 04 12:31:23 AM UTC 24 |
| Finished | Sep 04 12:34:52 AM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924503477 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3924503477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/165.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/168.rv_timer_random.1176839369 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 244247878318 ps |
| CPU time | 467.92 seconds |
| Started | Sep 04 12:31:34 AM UTC 24 |
| Finished | Sep 04 12:39:28 AM UTC 24 |
| Peak memory | 199740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176839369 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1176839369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/168.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/17.rv_timer_cfg_update_on_fly.3036231293 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 703464546461 ps |
| CPU time | 362.85 seconds |
| Started | Sep 04 12:02:07 AM UTC 24 |
| Finished | Sep 04 12:08:14 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036231293 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_cfg_update_on_fly.3036231293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/17.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/17.rv_timer_disabled.821252569 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 275265248244 ps |
| CPU time | 234.15 seconds |
| Started | Sep 04 12:01:59 AM UTC 24 |
| Finished | Sep 04 12:05:57 AM UTC 24 |
| Peak memory | 199816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821252569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.821252569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/17.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/171.rv_timer_random.2519996389 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 50056927910 ps |
| CPU time | 106.44 seconds |
| Started | Sep 04 12:31:54 AM UTC 24 |
| Finished | Sep 04 12:33:43 AM UTC 24 |
| Peak memory | 199608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519996389 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2519996389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/171.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/172.rv_timer_random.3850430404 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 112291048883 ps |
| CPU time | 177.95 seconds |
| Started | Sep 04 12:32:04 AM UTC 24 |
| Finished | Sep 04 12:35:04 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850430404 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3850430404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/172.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/173.rv_timer_random.801775876 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 76956243193 ps |
| CPU time | 1309.53 seconds |
| Started | Sep 04 12:32:17 AM UTC 24 |
| Finished | Sep 04 12:54:21 AM UTC 24 |
| Peak memory | 202484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801775876 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.801775876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/173.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/174.rv_timer_random.4130203616 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 46263572491 ps |
| CPU time | 92.01 seconds |
| Started | Sep 04 12:32:32 AM UTC 24 |
| Finished | Sep 04 12:34:06 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130203616 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.4130203616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/174.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/175.rv_timer_random.1258337254 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 39729906668 ps |
| CPU time | 114.84 seconds |
| Started | Sep 04 12:32:32 AM UTC 24 |
| Finished | Sep 04 12:34:29 AM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258337254 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1258337254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/175.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/176.rv_timer_random.3445991212 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 363760559775 ps |
| CPU time | 218.2 seconds |
| Started | Sep 04 12:32:41 AM UTC 24 |
| Finished | Sep 04 12:36:22 AM UTC 24 |
| Peak memory | 199700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445991212 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3445991212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/176.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/18.rv_timer_cfg_update_on_fly.2233756498 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 111443590914 ps |
| CPU time | 55.92 seconds |
| Started | Sep 04 12:02:41 AM UTC 24 |
| Finished | Sep 04 12:03:39 AM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233756498 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_cfg_update_on_fly.2233756498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/18.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/18.rv_timer_disabled.753189986 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 641690471240 ps |
| CPU time | 264.65 seconds |
| Started | Sep 04 12:02:40 AM UTC 24 |
| Finished | Sep 04 12:07:08 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753189986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.753189986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/18.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/18.rv_timer_random.1922666702 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 73150219758 ps |
| CPU time | 149.47 seconds |
| Started | Sep 04 12:02:38 AM UTC 24 |
| Finished | Sep 04 12:05:10 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922666702 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1922666702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/18.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/18.rv_timer_random_reset.2002523698 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 205616476875 ps |
| CPU time | 76.2 seconds |
| Started | Sep 04 12:02:42 AM UTC 24 |
| Finished | Sep 04 12:04:00 AM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002523698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2002523698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/18.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/180.rv_timer_random.742462049 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 42318818172 ps |
| CPU time | 122.25 seconds |
| Started | Sep 04 12:33:56 AM UTC 24 |
| Finished | Sep 04 12:36:00 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742462049 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.742462049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/180.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/181.rv_timer_random.2018867136 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2057925989650 ps |
| CPU time | 928.06 seconds |
| Started | Sep 04 12:34:06 AM UTC 24 |
| Finished | Sep 04 12:49:47 AM UTC 24 |
| Peak memory | 202404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018867136 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2018867136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/181.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/183.rv_timer_random.2308233170 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 3642010858 ps |
| CPU time | 3.12 seconds |
| Started | Sep 04 12:34:08 AM UTC 24 |
| Finished | Sep 04 12:34:12 AM UTC 24 |
| Peak memory | 199804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308233170 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2308233170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/183.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/184.rv_timer_random.1870372855 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 642457376524 ps |
| CPU time | 673.81 seconds |
| Started | Sep 04 12:34:13 AM UTC 24 |
| Finished | Sep 04 12:45:36 AM UTC 24 |
| Peak memory | 199616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870372855 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1870372855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/184.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/186.rv_timer_random.3837235820 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 265335463010 ps |
| CPU time | 667.89 seconds |
| Started | Sep 04 12:34:17 AM UTC 24 |
| Finished | Sep 04 12:45:33 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837235820 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3837235820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/186.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/187.rv_timer_random.1560190974 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 222277618065 ps |
| CPU time | 1751.94 seconds |
| Started | Sep 04 12:34:21 AM UTC 24 |
| Finished | Sep 04 01:03:51 AM UTC 24 |
| Peak memory | 202480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560190974 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1560190974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/187.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/188.rv_timer_random.3214313969 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 46097460929 ps |
| CPU time | 73.07 seconds |
| Started | Sep 04 12:34:30 AM UTC 24 |
| Finished | Sep 04 12:35:45 AM UTC 24 |
| Peak memory | 199700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214313969 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3214313969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/188.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/189.rv_timer_random.4119820170 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 133454077781 ps |
| CPU time | 290.01 seconds |
| Started | Sep 04 12:34:30 AM UTC 24 |
| Finished | Sep 04 12:39:24 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119820170 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.4119820170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/189.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/19.rv_timer_cfg_update_on_fly.2600393404 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1627927313427 ps |
| CPU time | 1038.39 seconds |
| Started | Sep 04 12:02:58 AM UTC 24 |
| Finished | Sep 04 12:20:27 AM UTC 24 |
| Peak memory | 202452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600393404 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_cfg_update_on_fly.2600393404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/19.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/19.rv_timer_disabled.928395231 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 450510501952 ps |
| CPU time | 166.31 seconds |
| Started | Sep 04 12:02:56 AM UTC 24 |
| Finished | Sep 04 12:05:44 AM UTC 24 |
| Peak memory | 199816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928395231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.928395231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/19.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/19.rv_timer_random.2524540167 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 402828691285 ps |
| CPU time | 674.23 seconds |
| Started | Sep 04 12:02:52 AM UTC 24 |
| Finished | Sep 04 12:14:14 AM UTC 24 |
| Peak memory | 199776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524540167 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2524540167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/19.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/19.rv_timer_random_reset.4173987371 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 53849421395 ps |
| CPU time | 156.64 seconds |
| Started | Sep 04 12:03:12 AM UTC 24 |
| Finished | Sep 04 12:05:51 AM UTC 24 |
| Peak memory | 199880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173987371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.4173987371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/19.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/19.rv_timer_stress_all_with_rand_reset.1218993328 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 28173082043 ps |
| CPU time | 47.79 seconds |
| Started | Sep 04 12:03:16 AM UTC 24 |
| Finished | Sep 04 12:04:05 AM UTC 24 |
| Peak memory | 204024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1218993328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.rv_timer_stress_all_with_rand_reset.1218993328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/19.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/190.rv_timer_random.1815207051 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 45962365535 ps |
| CPU time | 148.21 seconds |
| Started | Sep 04 12:34:34 AM UTC 24 |
| Finished | Sep 04 12:37:05 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815207051 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1815207051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/190.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/192.rv_timer_random.4075161172 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 159755320832 ps |
| CPU time | 106.6 seconds |
| Started | Sep 04 12:34:43 AM UTC 24 |
| Finished | Sep 04 12:36:32 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075161172 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.4075161172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/192.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/194.rv_timer_random.3352690349 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 26376561319 ps |
| CPU time | 83.35 seconds |
| Started | Sep 04 12:35:05 AM UTC 24 |
| Finished | Sep 04 12:36:30 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352690349 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3352690349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/194.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/196.rv_timer_random.2986113778 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 78385825236 ps |
| CPU time | 87.49 seconds |
| Started | Sep 04 12:35:13 AM UTC 24 |
| Finished | Sep 04 12:36:42 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986113778 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2986113778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/196.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/197.rv_timer_random.612623916 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 482396308948 ps |
| CPU time | 1339.45 seconds |
| Started | Sep 04 12:35:40 AM UTC 24 |
| Finished | Sep 04 12:58:15 AM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612623916 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.612623916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/197.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/198.rv_timer_random.3320641425 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 544741287168 ps |
| CPU time | 405.39 seconds |
| Started | Sep 04 12:35:46 AM UTC 24 |
| Finished | Sep 04 12:42:37 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320641425 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3320641425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/198.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/199.rv_timer_random.2235954834 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 126974958076 ps |
| CPU time | 60.42 seconds |
| Started | Sep 04 12:36:01 AM UTC 24 |
| Finished | Sep 04 12:37:03 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235954834 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2235954834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/199.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/2.rv_timer_cfg_update_on_fly.693722770 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 183799501893 ps |
| CPU time | 194.22 seconds |
| Started | Sep 03 11:57:55 PM UTC 24 |
| Finished | Sep 04 12:01:13 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693722770 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_cfg_update_on_fly.693722770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/2.rv_timer_disabled.89920331 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 114060012300 ps |
| CPU time | 70.99 seconds |
| Started | Sep 03 11:57:54 PM UTC 24 |
| Finished | Sep 03 11:59:07 PM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89920331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_ SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.89920331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/2.rv_timer_random_reset.555300383 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 27713363198 ps |
| CPU time | 44.23 seconds |
| Started | Sep 03 11:57:55 PM UTC 24 |
| Finished | Sep 03 11:58:41 PM UTC 24 |
| Peak memory | 199544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555300383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.555300383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/2.rv_timer_sec_cm.289112023 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 89709444 ps |
| CPU time | 1.2 seconds |
| Started | Sep 03 11:57:56 PM UTC 24 |
| Finished | Sep 03 11:57:58 PM UTC 24 |
| Peak memory | 230928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289112023 -assert nopostproc +UVM_TESTNAME=rv_ timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.289112023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/2.rv_timer_stress_all.1455987829 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 350799968229 ps |
| CPU time | 527.84 seconds |
| Started | Sep 03 11:57:56 PM UTC 24 |
| Finished | Sep 04 12:06:50 AM UTC 24 |
| Peak memory | 199624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455987829 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.1455987829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/2.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/20.rv_timer_cfg_update_on_fly.1883407527 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 657886039220 ps |
| CPU time | 219.79 seconds |
| Started | Sep 04 12:03:25 AM UTC 24 |
| Finished | Sep 04 12:07:08 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883407527 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_cfg_update_on_fly.1883407527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/20.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/20.rv_timer_disabled.3046780383 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 14226181518 ps |
| CPU time | 36.11 seconds |
| Started | Sep 04 12:03:22 AM UTC 24 |
| Finished | Sep 04 12:03:59 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046780383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3046780383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/20.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/20.rv_timer_random_reset.2695406951 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 228525097015 ps |
| CPU time | 208.56 seconds |
| Started | Sep 04 12:03:36 AM UTC 24 |
| Finished | Sep 04 12:07:08 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695406951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2695406951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/20.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/20.rv_timer_stress_all_with_rand_reset.4031267613 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 1649648424 ps |
| CPU time | 29.54 seconds |
| Started | Sep 04 12:03:37 AM UTC 24 |
| Finished | Sep 04 12:04:08 AM UTC 24 |
| Peak memory | 201912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4031267613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 20.rv_timer_stress_all_with_rand_reset.4031267613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/20.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/21.rv_timer_disabled.2537221127 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 310380773825 ps |
| CPU time | 138.07 seconds |
| Started | Sep 04 12:03:53 AM UTC 24 |
| Finished | Sep 04 12:06:14 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537221127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2537221127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/21.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/21.rv_timer_random.3096011472 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 515194225468 ps |
| CPU time | 112.38 seconds |
| Started | Sep 04 12:03:51 AM UTC 24 |
| Finished | Sep 04 12:05:46 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096011472 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3096011472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/21.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/21.rv_timer_random_reset.1991992899 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 73380265475 ps |
| CPU time | 76.83 seconds |
| Started | Sep 04 12:03:59 AM UTC 24 |
| Finished | Sep 04 12:05:17 AM UTC 24 |
| Peak memory | 199620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991992899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1991992899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/21.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/21.rv_timer_stress_all_with_rand_reset.1549854235 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1625220041 ps |
| CPU time | 18.7 seconds |
| Started | Sep 04 12:04:01 AM UTC 24 |
| Finished | Sep 04 12:04:21 AM UTC 24 |
| Peak memory | 203896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1549854235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.rv_timer_stress_all_with_rand_reset.1549854235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/21.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/22.rv_timer_cfg_update_on_fly.2530339653 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 398627255194 ps |
| CPU time | 231.79 seconds |
| Started | Sep 04 12:04:06 AM UTC 24 |
| Finished | Sep 04 12:08:02 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530339653 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_cfg_update_on_fly.2530339653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/22.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/22.rv_timer_disabled.2558287728 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 279960027258 ps |
| CPU time | 320.67 seconds |
| Started | Sep 04 12:04:04 AM UTC 24 |
| Finished | Sep 04 12:09:30 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558287728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2558287728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/22.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/22.rv_timer_random.1975242320 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 463068845532 ps |
| CPU time | 71.05 seconds |
| Started | Sep 04 12:04:02 AM UTC 24 |
| Finished | Sep 04 12:05:15 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975242320 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1975242320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/22.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/22.rv_timer_random_reset.2843578753 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 27183227289 ps |
| CPU time | 47.97 seconds |
| Started | Sep 04 12:04:08 AM UTC 24 |
| Finished | Sep 04 12:04:57 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843578753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2843578753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/22.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/22.rv_timer_stress_all_with_rand_reset.4260993106 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1001042380 ps |
| CPU time | 16.35 seconds |
| Started | Sep 04 12:04:09 AM UTC 24 |
| Finished | Sep 04 12:04:27 AM UTC 24 |
| Peak memory | 203996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4260993106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.rv_timer_stress_all_with_rand_reset.4260993106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/22.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/23.rv_timer_cfg_update_on_fly.2581160403 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 60294627273 ps |
| CPU time | 167.75 seconds |
| Started | Sep 04 12:04:24 AM UTC 24 |
| Finished | Sep 04 12:07:15 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581160403 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_cfg_update_on_fly.2581160403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/23.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/23.rv_timer_disabled.2364695517 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 292092263078 ps |
| CPU time | 193.03 seconds |
| Started | Sep 04 12:04:21 AM UTC 24 |
| Finished | Sep 04 12:07:38 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364695517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2364695517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/23.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/23.rv_timer_random.3394974185 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 259743013661 ps |
| CPU time | 154.16 seconds |
| Started | Sep 04 12:04:17 AM UTC 24 |
| Finished | Sep 04 12:06:54 AM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394974185 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3394974185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/23.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/23.rv_timer_stress_all.3144989264 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 343803334387 ps |
| CPU time | 748.25 seconds |
| Started | Sep 04 12:04:53 AM UTC 24 |
| Finished | Sep 04 12:17:29 AM UTC 24 |
| Peak memory | 199660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144989264 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.3144989264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/23.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/24.rv_timer_cfg_update_on_fly.2401856475 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 83025613283 ps |
| CPU time | 38.73 seconds |
| Started | Sep 04 12:05:11 AM UTC 24 |
| Finished | Sep 04 12:05:51 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401856475 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_cfg_update_on_fly.2401856475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/24.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/24.rv_timer_disabled.3968411938 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 32987031626 ps |
| CPU time | 49.31 seconds |
| Started | Sep 04 12:05:09 AM UTC 24 |
| Finished | Sep 04 12:06:00 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968411938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3968411938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/24.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/24.rv_timer_random.2598768835 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 203755812650 ps |
| CPU time | 94.76 seconds |
| Started | Sep 04 12:04:59 AM UTC 24 |
| Finished | Sep 04 12:06:35 AM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598768835 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2598768835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/24.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/24.rv_timer_random_reset.145642803 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 572004594644 ps |
| CPU time | 341.85 seconds |
| Started | Sep 04 12:05:11 AM UTC 24 |
| Finished | Sep 04 12:10:57 AM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145642803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.145642803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/24.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/25.rv_timer_cfg_update_on_fly.987503471 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 363715166358 ps |
| CPU time | 665.45 seconds |
| Started | Sep 04 12:05:37 AM UTC 24 |
| Finished | Sep 04 12:16:50 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987503471 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_cfg_update_on_fly.987503471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/25.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/25.rv_timer_disabled.880790268 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 586755675604 ps |
| CPU time | 174.4 seconds |
| Started | Sep 04 12:05:28 AM UTC 24 |
| Finished | Sep 04 12:08:25 AM UTC 24 |
| Peak memory | 199852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880790268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.880790268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/25.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/25.rv_timer_random.1136472895 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 74032153464 ps |
| CPU time | 34.67 seconds |
| Started | Sep 04 12:05:21 AM UTC 24 |
| Finished | Sep 04 12:05:57 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136472895 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1136472895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/25.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/25.rv_timer_random_reset.2702030168 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 57255115005 ps |
| CPU time | 56.62 seconds |
| Started | Sep 04 12:05:45 AM UTC 24 |
| Finished | Sep 04 12:06:43 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702030168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2702030168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/25.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/25.rv_timer_stress_all_with_rand_reset.128664261 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 6678759968 ps |
| CPU time | 19.8 seconds |
| Started | Sep 04 12:05:47 AM UTC 24 |
| Finished | Sep 04 12:06:08 AM UTC 24 |
| Peak memory | 204096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=128664261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.128664261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/25.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/26.rv_timer_cfg_update_on_fly.1796163881 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 42814328322 ps |
| CPU time | 136.72 seconds |
| Started | Sep 04 12:05:57 AM UTC 24 |
| Finished | Sep 04 12:08:17 AM UTC 24 |
| Peak memory | 199596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796163881 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_cfg_update_on_fly.1796163881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/26.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/26.rv_timer_disabled.1900725315 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 38852195451 ps |
| CPU time | 85.78 seconds |
| Started | Sep 04 12:05:52 AM UTC 24 |
| Finished | Sep 04 12:07:20 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900725315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1900725315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/26.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/26.rv_timer_random_reset.2003219656 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 10017570546 ps |
| CPU time | 31.53 seconds |
| Started | Sep 04 12:05:58 AM UTC 24 |
| Finished | Sep 04 12:06:31 AM UTC 24 |
| Peak memory | 199468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003219656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2003219656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/26.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/26.rv_timer_stress_all.1046903371 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 692390017726 ps |
| CPU time | 1543.8 seconds |
| Started | Sep 04 12:06:04 AM UTC 24 |
| Finished | Sep 04 12:32:03 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046903371 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.1046903371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/26.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/27.rv_timer_cfg_update_on_fly.2707440359 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 94218922348 ps |
| CPU time | 203.07 seconds |
| Started | Sep 04 12:06:15 AM UTC 24 |
| Finished | Sep 04 12:09:41 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707440359 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_cfg_update_on_fly.2707440359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/27.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/27.rv_timer_disabled.1457131637 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 176640724029 ps |
| CPU time | 226.36 seconds |
| Started | Sep 04 12:06:12 AM UTC 24 |
| Finished | Sep 04 12:10:01 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457131637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1457131637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/27.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/27.rv_timer_random_reset.4192666456 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 12198432385 ps |
| CPU time | 6.04 seconds |
| Started | Sep 04 12:06:16 AM UTC 24 |
| Finished | Sep 04 12:06:23 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192666456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.4192666456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/27.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all.2017936456 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1473855728054 ps |
| CPU time | 1004.22 seconds |
| Started | Sep 04 12:06:24 AM UTC 24 |
| Finished | Sep 04 12:23:20 AM UTC 24 |
| Peak memory | 202352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017936456 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.2017936456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/27.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/27.rv_timer_stress_all_with_rand_reset.695518883 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1198394057 ps |
| CPU time | 14.12 seconds |
| Started | Sep 04 12:06:20 AM UTC 24 |
| Finished | Sep 04 12:06:35 AM UTC 24 |
| Peak memory | 204032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=695518883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.695518883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/27.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/28.rv_timer_cfg_update_on_fly.4096958629 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 292768088116 ps |
| CPU time | 244.13 seconds |
| Started | Sep 04 12:06:32 AM UTC 24 |
| Finished | Sep 04 12:10:40 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096958629 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_cfg_update_on_fly.4096958629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/28.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/28.rv_timer_disabled.3308264743 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 170440871713 ps |
| CPU time | 334.42 seconds |
| Started | Sep 04 12:06:29 AM UTC 24 |
| Finished | Sep 04 12:12:08 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308264743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3308264743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/28.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/28.rv_timer_stress_all.2334468138 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 872606780762 ps |
| CPU time | 1760.17 seconds |
| Started | Sep 04 12:06:44 AM UTC 24 |
| Finished | Sep 04 12:36:22 AM UTC 24 |
| Peak memory | 202352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334468138 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.2334468138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/28.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/29.rv_timer_cfg_update_on_fly.207317130 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 67907320258 ps |
| CPU time | 56.84 seconds |
| Started | Sep 04 12:06:51 AM UTC 24 |
| Finished | Sep 04 12:07:49 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207317130 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_cfg_update_on_fly.207317130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/29.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/29.rv_timer_disabled.4221479356 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 319734695550 ps |
| CPU time | 248.87 seconds |
| Started | Sep 04 12:06:51 AM UTC 24 |
| Finished | Sep 04 12:11:03 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221479356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.4221479356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/29.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/29.rv_timer_random.1819853193 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 254113469186 ps |
| CPU time | 332.71 seconds |
| Started | Sep 04 12:06:45 AM UTC 24 |
| Finished | Sep 04 12:12:22 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819853193 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1819853193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/29.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/29.rv_timer_random_reset.2460537923 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 106571643346 ps |
| CPU time | 71.1 seconds |
| Started | Sep 04 12:06:55 AM UTC 24 |
| Finished | Sep 04 12:08:08 AM UTC 24 |
| Peak memory | 199820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460537923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2460537923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/29.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all.1016197094 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 65797144249 ps |
| CPU time | 193.43 seconds |
| Started | Sep 04 12:07:09 AM UTC 24 |
| Finished | Sep 04 12:10:26 AM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016197094 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.1016197094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/29.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/29.rv_timer_stress_all_with_rand_reset.3702290726 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1513261991 ps |
| CPU time | 26.65 seconds |
| Started | Sep 04 12:07:09 AM UTC 24 |
| Finished | Sep 04 12:07:37 AM UTC 24 |
| Peak memory | 203824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3702290726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 29.rv_timer_stress_all_with_rand_reset.3702290726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/29.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/3.rv_timer_cfg_update_on_fly.1579965299 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 599711223067 ps |
| CPU time | 506.27 seconds |
| Started | Sep 03 11:57:56 PM UTC 24 |
| Finished | Sep 04 12:06:29 AM UTC 24 |
| Peak memory | 199728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579965299 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_cfg_update_on_fly.1579965299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/3.rv_timer_disabled.4015536885 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 405969977041 ps |
| CPU time | 226.1 seconds |
| Started | Sep 03 11:57:56 PM UTC 24 |
| Finished | Sep 04 12:01:45 AM UTC 24 |
| Peak memory | 199684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015536885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.4015536885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/3.rv_timer_random.2634352935 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 135931082527 ps |
| CPU time | 77.44 seconds |
| Started | Sep 03 11:57:56 PM UTC 24 |
| Finished | Sep 03 11:59:15 PM UTC 24 |
| Peak memory | 199532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634352935 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2634352935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/3.rv_timer_random_reset.157631850 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 512142036 ps |
| CPU time | 1.15 seconds |
| Started | Sep 03 11:57:56 PM UTC 24 |
| Finished | Sep 03 11:57:58 PM UTC 24 |
| Peak memory | 198880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157631850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.157631850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/3.rv_timer_sec_cm.1398439117 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 104476465 ps |
| CPU time | 1.38 seconds |
| Started | Sep 03 11:57:59 PM UTC 24 |
| Finished | Sep 03 11:58:02 PM UTC 24 |
| Peak memory | 230928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398439117 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1398439117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/3.rv_timer_stress_all.1017493752 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1700466084653 ps |
| CPU time | 355.75 seconds |
| Started | Sep 03 11:57:57 PM UTC 24 |
| Finished | Sep 04 12:03:57 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017493752 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.1017493752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/3.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/30.rv_timer_cfg_update_on_fly.2157932677 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 319493410665 ps |
| CPU time | 707.14 seconds |
| Started | Sep 04 12:07:21 AM UTC 24 |
| Finished | Sep 04 12:19:16 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157932677 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_cfg_update_on_fly.2157932677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/30.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/30.rv_timer_disabled.2712691793 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 72908917254 ps |
| CPU time | 65.11 seconds |
| Started | Sep 04 12:07:15 AM UTC 24 |
| Finished | Sep 04 12:08:22 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712691793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2712691793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/30.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/30.rv_timer_random.512982191 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 48805061144 ps |
| CPU time | 97.69 seconds |
| Started | Sep 04 12:07:09 AM UTC 24 |
| Finished | Sep 04 12:08:49 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512982191 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.512982191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/30.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/30.rv_timer_random_reset.1348146487 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 415093283 ps |
| CPU time | 1.93 seconds |
| Started | Sep 04 12:07:24 AM UTC 24 |
| Finished | Sep 04 12:07:27 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348146487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1348146487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/30.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/30.rv_timer_stress_all.3544849888 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 759910130990 ps |
| CPU time | 408.26 seconds |
| Started | Sep 04 12:07:37 AM UTC 24 |
| Finished | Sep 04 12:14:31 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544849888 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.3544849888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/30.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/31.rv_timer_cfg_update_on_fly.3723602 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 93794325561 ps |
| CPU time | 212.61 seconds |
| Started | Sep 04 12:07:50 AM UTC 24 |
| Finished | Sep 04 12:11:26 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_cfg_update_on_fly.3723602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/31.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/31.rv_timer_random_reset.2399883904 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 210860842337 ps |
| CPU time | 189.19 seconds |
| Started | Sep 04 12:07:50 AM UTC 24 |
| Finished | Sep 04 12:11:03 AM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399883904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2399883904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/31.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all.303524299 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 559435836041 ps |
| CPU time | 298.37 seconds |
| Started | Sep 04 12:07:59 AM UTC 24 |
| Finished | Sep 04 12:13:01 AM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303524299 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.303524299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/31.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/31.rv_timer_stress_all_with_rand_reset.1565361548 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 9417489700 ps |
| CPU time | 29.06 seconds |
| Started | Sep 04 12:07:51 AM UTC 24 |
| Finished | Sep 04 12:08:22 AM UTC 24 |
| Peak memory | 203896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1565361548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.rv_timer_stress_all_with_rand_reset.1565361548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/31.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/32.rv_timer_cfg_update_on_fly.3265698999 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 608827871236 ps |
| CPU time | 949.88 seconds |
| Started | Sep 04 12:08:15 AM UTC 24 |
| Finished | Sep 04 12:24:14 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265698999 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_cfg_update_on_fly.3265698999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/32.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/32.rv_timer_disabled.3198708733 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 110474653321 ps |
| CPU time | 89.18 seconds |
| Started | Sep 04 12:08:09 AM UTC 24 |
| Finished | Sep 04 12:09:40 AM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198708733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3198708733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/32.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/32.rv_timer_random_reset.1546197159 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 14292306324 ps |
| CPU time | 20.26 seconds |
| Started | Sep 04 12:08:18 AM UTC 24 |
| Finished | Sep 04 12:08:39 AM UTC 24 |
| Peak memory | 199852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546197159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1546197159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/32.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/32.rv_timer_stress_all_with_rand_reset.324255991 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 4500680975 ps |
| CPU time | 53.86 seconds |
| Started | Sep 04 12:08:23 AM UTC 24 |
| Finished | Sep 04 12:09:18 AM UTC 24 |
| Peak memory | 203968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=324255991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.324255991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/32.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/33.rv_timer_cfg_update_on_fly.654412527 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 96941494218 ps |
| CPU time | 171.04 seconds |
| Started | Sep 04 12:08:30 AM UTC 24 |
| Finished | Sep 04 12:11:24 AM UTC 24 |
| Peak memory | 199724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654412527 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_cfg_update_on_fly.654412527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/33.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/33.rv_timer_disabled.4030279162 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 122472367132 ps |
| CPU time | 222.89 seconds |
| Started | Sep 04 12:08:29 AM UTC 24 |
| Finished | Sep 04 12:12:15 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030279162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.4030279162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/33.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/33.rv_timer_random.246748252 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 601312043 ps |
| CPU time | 1.3 seconds |
| Started | Sep 04 12:08:26 AM UTC 24 |
| Finished | Sep 04 12:08:28 AM UTC 24 |
| Peak memory | 198872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246748252 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.246748252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/33.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/33.rv_timer_random_reset.3888496178 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 195653857865 ps |
| CPU time | 81.13 seconds |
| Started | Sep 04 12:08:40 AM UTC 24 |
| Finished | Sep 04 12:10:03 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888496178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3888496178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/33.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/34.rv_timer_cfg_update_on_fly.3272752391 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 13094793430 ps |
| CPU time | 40.87 seconds |
| Started | Sep 04 12:08:53 AM UTC 24 |
| Finished | Sep 04 12:09:35 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272752391 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_cfg_update_on_fly.3272752391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/34.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/34.rv_timer_disabled.344792076 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 135439287137 ps |
| CPU time | 272.55 seconds |
| Started | Sep 04 12:08:50 AM UTC 24 |
| Finished | Sep 04 12:13:26 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344792076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.344792076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/34.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/34.rv_timer_random.1281015503 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 70697331547 ps |
| CPU time | 1330.94 seconds |
| Started | Sep 04 12:08:49 AM UTC 24 |
| Finished | Sep 04 12:31:14 AM UTC 24 |
| Peak memory | 202484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281015503 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1281015503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/34.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/34.rv_timer_random_reset.285058071 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 14061752638 ps |
| CPU time | 38.72 seconds |
| Started | Sep 04 12:08:58 AM UTC 24 |
| Finished | Sep 04 12:09:38 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285058071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.285058071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/34.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all.393880389 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 20412526025 ps |
| CPU time | 54.48 seconds |
| Started | Sep 04 12:09:10 AM UTC 24 |
| Finished | Sep 04 12:10:06 AM UTC 24 |
| Peak memory | 199616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393880389 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.393880389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/34.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/34.rv_timer_stress_all_with_rand_reset.1725012200 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 7287363550 ps |
| CPU time | 46.57 seconds |
| Started | Sep 04 12:09:00 AM UTC 24 |
| Finished | Sep 04 12:09:48 AM UTC 24 |
| Peak memory | 203828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1725012200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.rv_timer_stress_all_with_rand_reset.1725012200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/34.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/35.rv_timer_cfg_update_on_fly.328089622 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 3312629086 ps |
| CPU time | 4.33 seconds |
| Started | Sep 04 12:09:30 AM UTC 24 |
| Finished | Sep 04 12:09:36 AM UTC 24 |
| Peak memory | 199584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328089622 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_cfg_update_on_fly.328089622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/35.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/35.rv_timer_disabled.2219058368 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 663125581559 ps |
| CPU time | 244.16 seconds |
| Started | Sep 04 12:09:28 AM UTC 24 |
| Finished | Sep 04 12:13:36 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219058368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2219058368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/35.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/35.rv_timer_random.2498111659 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 13523780145 ps |
| CPU time | 54.78 seconds |
| Started | Sep 04 12:09:19 AM UTC 24 |
| Finished | Sep 04 12:10:16 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498111659 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2498111659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/35.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/35.rv_timer_random_reset.780007772 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 93467326101 ps |
| CPU time | 95.91 seconds |
| Started | Sep 04 12:09:34 AM UTC 24 |
| Finished | Sep 04 12:11:12 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780007772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.780007772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/35.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all.1198141719 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 22627706 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 12:09:36 AM UTC 24 |
| Finished | Sep 04 12:09:38 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198141719 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.1198141719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/35.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/35.rv_timer_stress_all_with_rand_reset.4111980061 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 2268054290 ps |
| CPU time | 35.91 seconds |
| Started | Sep 04 12:09:36 AM UTC 24 |
| Finished | Sep 04 12:10:14 AM UTC 24 |
| Peak memory | 199964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4111980061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.rv_timer_stress_all_with_rand_reset.4111980061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/35.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/36.rv_timer_cfg_update_on_fly.783486266 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 246502373786 ps |
| CPU time | 418.25 seconds |
| Started | Sep 04 12:09:41 AM UTC 24 |
| Finished | Sep 04 12:16:43 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783486266 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_cfg_update_on_fly.783486266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/36.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/36.rv_timer_disabled.3455445510 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 578362826131 ps |
| CPU time | 365.88 seconds |
| Started | Sep 04 12:09:40 AM UTC 24 |
| Finished | Sep 04 12:15:50 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455445510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3455445510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/36.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/36.rv_timer_random.2808991404 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 240103579551 ps |
| CPU time | 326.01 seconds |
| Started | Sep 04 12:09:38 AM UTC 24 |
| Finished | Sep 04 12:15:09 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808991404 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2808991404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/36.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/36.rv_timer_random_reset.4007063411 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 185902108 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 12:09:42 AM UTC 24 |
| Finished | Sep 04 12:09:44 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007063411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.4007063411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/36.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/36.rv_timer_stress_all.2609047929 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 268765805963 ps |
| CPU time | 256.66 seconds |
| Started | Sep 04 12:09:49 AM UTC 24 |
| Finished | Sep 04 12:14:09 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609047929 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.2609047929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/36.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/37.rv_timer_cfg_update_on_fly.2686471855 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1059124875 ps |
| CPU time | 3.63 seconds |
| Started | Sep 04 12:10:02 AM UTC 24 |
| Finished | Sep 04 12:10:07 AM UTC 24 |
| Peak memory | 199400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686471855 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_cfg_update_on_fly.2686471855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/37.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/37.rv_timer_disabled.1552896410 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 446412958949 ps |
| CPU time | 170.26 seconds |
| Started | Sep 04 12:09:54 AM UTC 24 |
| Finished | Sep 04 12:12:47 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552896410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1552896410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/37.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/37.rv_timer_random.1275869450 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 154100499074 ps |
| CPU time | 549.53 seconds |
| Started | Sep 04 12:09:52 AM UTC 24 |
| Finished | Sep 04 12:19:08 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275869450 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1275869450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/37.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/37.rv_timer_random_reset.514013754 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 143062538100 ps |
| CPU time | 134.19 seconds |
| Started | Sep 04 12:10:02 AM UTC 24 |
| Finished | Sep 04 12:12:19 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514013754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.514013754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/37.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/37.rv_timer_stress_all.3554228039 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 7171794434229 ps |
| CPU time | 1669.73 seconds |
| Started | Sep 04 12:10:07 AM UTC 24 |
| Finished | Sep 04 12:38:14 AM UTC 24 |
| Peak memory | 202448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554228039 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.3554228039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/37.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/38.rv_timer_cfg_update_on_fly.257768707 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 33622618945 ps |
| CPU time | 22.21 seconds |
| Started | Sep 04 12:10:16 AM UTC 24 |
| Finished | Sep 04 12:10:40 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257768707 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_cfg_update_on_fly.257768707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/38.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/38.rv_timer_disabled.2979321869 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 52599468837 ps |
| CPU time | 37.05 seconds |
| Started | Sep 04 12:10:14 AM UTC 24 |
| Finished | Sep 04 12:10:53 AM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979321869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2979321869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/38.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/38.rv_timer_random.452789844 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 8712633939 ps |
| CPU time | 23.37 seconds |
| Started | Sep 04 12:10:07 AM UTC 24 |
| Finished | Sep 04 12:10:32 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452789844 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.452789844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/38.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/38.rv_timer_random_reset.115204762 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 142306263130 ps |
| CPU time | 304.73 seconds |
| Started | Sep 04 12:10:27 AM UTC 24 |
| Finished | Sep 04 12:15:36 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115204762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.115204762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/38.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all.3466115051 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 106393408669 ps |
| CPU time | 375.2 seconds |
| Started | Sep 04 12:10:33 AM UTC 24 |
| Finished | Sep 04 12:16:53 AM UTC 24 |
| Peak memory | 199684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466115051 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.3466115051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/38.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/38.rv_timer_stress_all_with_rand_reset.4073041598 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2144416736 ps |
| CPU time | 26.43 seconds |
| Started | Sep 04 12:10:27 AM UTC 24 |
| Finished | Sep 04 12:10:54 AM UTC 24 |
| Peak memory | 203828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4073041598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.rv_timer_stress_all_with_rand_reset.4073041598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/38.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/39.rv_timer_cfg_update_on_fly.4183297410 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 36271740731 ps |
| CPU time | 73.84 seconds |
| Started | Sep 04 12:10:42 AM UTC 24 |
| Finished | Sep 04 12:11:57 AM UTC 24 |
| Peak memory | 199688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183297410 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_cfg_update_on_fly.4183297410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/39.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/39.rv_timer_disabled.3400907718 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 96966152423 ps |
| CPU time | 159.86 seconds |
| Started | Sep 04 12:10:42 AM UTC 24 |
| Finished | Sep 04 12:13:24 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400907718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3400907718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/39.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/39.rv_timer_random.3915578479 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 32524428155 ps |
| CPU time | 43.96 seconds |
| Started | Sep 04 12:10:34 AM UTC 24 |
| Finished | Sep 04 12:11:19 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915578479 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3915578479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/39.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/39.rv_timer_random_reset.3528431114 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 164294879999 ps |
| CPU time | 804.2 seconds |
| Started | Sep 04 12:10:46 AM UTC 24 |
| Finished | Sep 04 12:24:19 AM UTC 24 |
| Peak memory | 199816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528431114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3528431114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/39.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/39.rv_timer_stress_all.2728810834 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 62509628495 ps |
| CPU time | 131.63 seconds |
| Started | Sep 04 12:10:56 AM UTC 24 |
| Finished | Sep 04 12:13:10 AM UTC 24 |
| Peak memory | 199748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728810834 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.2728810834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/39.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/4.rv_timer_disabled.2138639746 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 135312040017 ps |
| CPU time | 197.29 seconds |
| Started | Sep 03 11:58:01 PM UTC 24 |
| Finished | Sep 04 12:01:21 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138639746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2138639746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/4.rv_timer_random.3224414803 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 241199634077 ps |
| CPU time | 333.05 seconds |
| Started | Sep 03 11:57:59 PM UTC 24 |
| Finished | Sep 04 12:03:37 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224414803 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3224414803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/4.rv_timer_random_reset.1140493037 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 850204509 ps |
| CPU time | 3.49 seconds |
| Started | Sep 03 11:58:08 PM UTC 24 |
| Finished | Sep 03 11:58:13 PM UTC 24 |
| Peak memory | 199468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140493037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1140493037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/4.rv_timer_sec_cm.3982871949 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 370217525 ps |
| CPU time | 1.26 seconds |
| Started | Sep 03 11:58:15 PM UTC 24 |
| Finished | Sep 03 11:58:17 PM UTC 24 |
| Peak memory | 230928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982871949 -assert nopostproc +UVM_TESTNAME=rv _timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3982871949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all.1099543737 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 626531330878 ps |
| CPU time | 273.73 seconds |
| Started | Sep 03 11:58:14 PM UTC 24 |
| Finished | Sep 04 12:02:51 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099543737 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.1099543737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/4.rv_timer_stress_all_with_rand_reset.3791670211 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2694383862 ps |
| CPU time | 32.46 seconds |
| Started | Sep 03 11:58:13 PM UTC 24 |
| Finished | Sep 03 11:58:47 PM UTC 24 |
| Peak memory | 201848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3791670211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.rv_timer_stress_all_with_rand_reset.3791670211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/4.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/40.rv_timer_cfg_update_on_fly.1385072119 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 225037764448 ps |
| CPU time | 115.22 seconds |
| Started | Sep 04 12:11:05 AM UTC 24 |
| Finished | Sep 04 12:13:02 AM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385072119 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_cfg_update_on_fly.1385072119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/40.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/40.rv_timer_disabled.2503891499 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 103208621118 ps |
| CPU time | 198.84 seconds |
| Started | Sep 04 12:10:58 AM UTC 24 |
| Finished | Sep 04 12:14:20 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503891499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2503891499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/40.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/40.rv_timer_stress_all.896556068 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 224949148240 ps |
| CPU time | 436.99 seconds |
| Started | Sep 04 12:11:13 AM UTC 24 |
| Finished | Sep 04 12:18:35 AM UTC 24 |
| Peak memory | 199688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896556068 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.896556068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/40.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/41.rv_timer_cfg_update_on_fly.4028135705 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 17178553086 ps |
| CPU time | 51.65 seconds |
| Started | Sep 04 12:11:21 AM UTC 24 |
| Finished | Sep 04 12:12:15 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028135705 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_cfg_update_on_fly.4028135705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/41.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/41.rv_timer_random_reset.864138065 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 292405234877 ps |
| CPU time | 335.6 seconds |
| Started | Sep 04 12:11:25 AM UTC 24 |
| Finished | Sep 04 12:17:06 AM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864138065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.864138065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/41.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/42.rv_timer_random.898851677 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 111546399558 ps |
| CPU time | 489.83 seconds |
| Started | Sep 04 12:11:54 AM UTC 24 |
| Finished | Sep 04 12:20:09 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898851677 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.898851677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/42.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/42.rv_timer_random_reset.422453605 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 1761902964 ps |
| CPU time | 1.5 seconds |
| Started | Sep 04 12:12:15 AM UTC 24 |
| Finished | Sep 04 12:12:18 AM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422453605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.422453605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/42.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all.4144962753 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 833950556277 ps |
| CPU time | 2489.61 seconds |
| Started | Sep 04 12:12:18 AM UTC 24 |
| Finished | Sep 04 12:54:15 AM UTC 24 |
| Peak memory | 202352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144962753 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.4144962753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/42.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/42.rv_timer_stress_all_with_rand_reset.3384377860 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 14594766817 ps |
| CPU time | 65.73 seconds |
| Started | Sep 04 12:12:16 AM UTC 24 |
| Finished | Sep 04 12:13:24 AM UTC 24 |
| Peak memory | 206072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3384377860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 42.rv_timer_stress_all_with_rand_reset.3384377860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/42.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/43.rv_timer_cfg_update_on_fly.2944407009 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 892179656661 ps |
| CPU time | 710.73 seconds |
| Started | Sep 04 12:12:37 AM UTC 24 |
| Finished | Sep 04 12:24:36 AM UTC 24 |
| Peak memory | 199664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944407009 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_cfg_update_on_fly.2944407009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/43.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/43.rv_timer_disabled.2666891551 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 156228976948 ps |
| CPU time | 360.94 seconds |
| Started | Sep 04 12:12:23 AM UTC 24 |
| Finished | Sep 04 12:18:28 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666891551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2666891551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/43.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/43.rv_timer_random.484358146 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 66004809536 ps |
| CPU time | 713.39 seconds |
| Started | Sep 04 12:12:19 AM UTC 24 |
| Finished | Sep 04 12:24:22 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484358146 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.484358146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/43.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/43.rv_timer_random_reset.232686391 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 51334670134 ps |
| CPU time | 220.63 seconds |
| Started | Sep 04 12:12:48 AM UTC 24 |
| Finished | Sep 04 12:16:32 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232686391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.232686391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/43.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/43.rv_timer_stress_all_with_rand_reset.998907305 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 4965614194 ps |
| CPU time | 56.34 seconds |
| Started | Sep 04 12:12:54 AM UTC 24 |
| Finished | Sep 04 12:13:52 AM UTC 24 |
| Peak memory | 204032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=998907305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.998907305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/43.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/44.rv_timer_cfg_update_on_fly.2397433454 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 214031408661 ps |
| CPU time | 530.03 seconds |
| Started | Sep 04 12:13:13 AM UTC 24 |
| Finished | Sep 04 12:22:10 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397433454 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_cfg_update_on_fly.2397433454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/44.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/44.rv_timer_disabled.3113931604 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 296676661202 ps |
| CPU time | 253.75 seconds |
| Started | Sep 04 12:13:11 AM UTC 24 |
| Finished | Sep 04 12:17:28 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113931604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3113931604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/44.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/44.rv_timer_random.2985514252 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 44263365849 ps |
| CPU time | 99.1 seconds |
| Started | Sep 04 12:13:03 AM UTC 24 |
| Finished | Sep 04 12:14:44 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985514252 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2985514252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/44.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/44.rv_timer_random_reset.2951049082 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 108266002574 ps |
| CPU time | 131.09 seconds |
| Started | Sep 04 12:13:25 AM UTC 24 |
| Finished | Sep 04 12:15:38 AM UTC 24 |
| Peak memory | 199716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951049082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2951049082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/44.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/45.rv_timer_cfg_update_on_fly.1080908296 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 363031394422 ps |
| CPU time | 231.89 seconds |
| Started | Sep 04 12:13:37 AM UTC 24 |
| Finished | Sep 04 12:17:32 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080908296 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_cfg_update_on_fly.1080908296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/45.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/45.rv_timer_disabled.1836157923 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 257326349484 ps |
| CPU time | 220.96 seconds |
| Started | Sep 04 12:13:36 AM UTC 24 |
| Finished | Sep 04 12:17:20 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836157923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1836157923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/45.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/45.rv_timer_random_reset.1725311987 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 230487069913 ps |
| CPU time | 169.63 seconds |
| Started | Sep 04 12:13:51 AM UTC 24 |
| Finished | Sep 04 12:16:44 AM UTC 24 |
| Peak memory | 199816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725311987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1725311987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/45.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/45.rv_timer_stress_all.583032391 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 54425404980 ps |
| CPU time | 39.76 seconds |
| Started | Sep 04 12:13:57 AM UTC 24 |
| Finished | Sep 04 12:14:39 AM UTC 24 |
| Peak memory | 199612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583032391 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.583032391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/45.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/46.rv_timer_cfg_update_on_fly.826397828 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 135546418053 ps |
| CPU time | 82.44 seconds |
| Started | Sep 04 12:14:10 AM UTC 24 |
| Finished | Sep 04 12:15:34 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826397828 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_cfg_update_on_fly.826397828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/46.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/46.rv_timer_disabled.2941726406 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 94551280963 ps |
| CPU time | 163.69 seconds |
| Started | Sep 04 12:14:10 AM UTC 24 |
| Finished | Sep 04 12:16:56 AM UTC 24 |
| Peak memory | 199588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941726406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2941726406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/46.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/46.rv_timer_random.3863026655 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 221737824 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 12:14:07 AM UTC 24 |
| Finished | Sep 04 12:14:09 AM UTC 24 |
| Peak memory | 198872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863026655 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3863026655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/46.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/46.rv_timer_random_reset.1468256986 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 28835818062 ps |
| CPU time | 67.73 seconds |
| Started | Sep 04 12:14:15 AM UTC 24 |
| Finished | Sep 04 12:15:24 AM UTC 24 |
| Peak memory | 199852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468256986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1468256986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/46.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/46.rv_timer_stress_all_with_rand_reset.2589141802 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 9136955879 ps |
| CPU time | 77.31 seconds |
| Started | Sep 04 12:14:21 AM UTC 24 |
| Finished | Sep 04 12:15:41 AM UTC 24 |
| Peak memory | 203996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2589141802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.rv_timer_stress_all_with_rand_reset.2589141802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/46.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/47.rv_timer_cfg_update_on_fly.4220718891 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 4837119327028 ps |
| CPU time | 1803.62 seconds |
| Started | Sep 04 12:14:39 AM UTC 24 |
| Finished | Sep 04 12:45:03 AM UTC 24 |
| Peak memory | 202332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220718891 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_cfg_update_on_fly.4220718891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/47.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/47.rv_timer_disabled.2151947346 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 531373338760 ps |
| CPU time | 289.42 seconds |
| Started | Sep 04 12:14:31 AM UTC 24 |
| Finished | Sep 04 12:19:25 AM UTC 24 |
| Peak memory | 199908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151947346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2151947346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/47.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/47.rv_timer_random.2536974083 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 379952769636 ps |
| CPU time | 350.75 seconds |
| Started | Sep 04 12:14:28 AM UTC 24 |
| Finished | Sep 04 12:20:24 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536974083 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2536974083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/47.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/47.rv_timer_random_reset.134978633 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 56736955732 ps |
| CPU time | 169.74 seconds |
| Started | Sep 04 12:14:46 AM UTC 24 |
| Finished | Sep 04 12:17:38 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134978633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.134978633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/47.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/47.rv_timer_stress_all_with_rand_reset.1021323077 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 4393422613 ps |
| CPU time | 28.4 seconds |
| Started | Sep 04 12:15:10 AM UTC 24 |
| Finished | Sep 04 12:15:39 AM UTC 24 |
| Peak memory | 204000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1021323077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.rv_timer_stress_all_with_rand_reset.1021323077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/47.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/48.rv_timer_cfg_update_on_fly.3180611363 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 3843975516 ps |
| CPU time | 14.27 seconds |
| Started | Sep 04 12:15:39 AM UTC 24 |
| Finished | Sep 04 12:15:55 AM UTC 24 |
| Peak memory | 199792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180611363 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_cfg_update_on_fly.3180611363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/48.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/48.rv_timer_disabled.3356973869 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 401548533434 ps |
| CPU time | 228.9 seconds |
| Started | Sep 04 12:15:37 AM UTC 24 |
| Finished | Sep 04 12:19:29 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356973869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3356973869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/48.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/48.rv_timer_random_reset.3877729441 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 78595621654 ps |
| CPU time | 256.07 seconds |
| Started | Sep 04 12:15:40 AM UTC 24 |
| Finished | Sep 04 12:20:00 AM UTC 24 |
| Peak memory | 199852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877729441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3877729441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/48.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/49.rv_timer_cfg_update_on_fly.1380742566 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 719510282737 ps |
| CPU time | 326.39 seconds |
| Started | Sep 04 12:15:56 AM UTC 24 |
| Finished | Sep 04 12:21:26 AM UTC 24 |
| Peak memory | 199592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380742566 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_cfg_update_on_fly.1380742566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/49.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/49.rv_timer_disabled.2821085493 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 52698443540 ps |
| CPU time | 142.66 seconds |
| Started | Sep 04 12:15:51 AM UTC 24 |
| Finished | Sep 04 12:18:16 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821085493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2821085493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/49.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/49.rv_timer_random_reset.1642100930 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 64527607377 ps |
| CPU time | 124.09 seconds |
| Started | Sep 04 12:16:13 AM UTC 24 |
| Finished | Sep 04 12:18:20 AM UTC 24 |
| Peak memory | 199712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642100930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1642100930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/49.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/49.rv_timer_stress_all.258864249 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 20887602 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 12:16:33 AM UTC 24 |
| Finished | Sep 04 12:16:35 AM UTC 24 |
| Peak memory | 198872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258864249 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.258864249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/49.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/5.rv_timer_cfg_update_on_fly.3616471127 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 1396914944196 ps |
| CPU time | 600.44 seconds |
| Started | Sep 03 11:58:21 PM UTC 24 |
| Finished | Sep 04 12:08:29 AM UTC 24 |
| Peak memory | 202332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616471127 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_cfg_update_on_fly.3616471127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/5.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/5.rv_timer_disabled.3271331278 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 223217204496 ps |
| CPU time | 185.1 seconds |
| Started | Sep 03 11:58:18 PM UTC 24 |
| Finished | Sep 04 12:01:26 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271331278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3271331278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/5.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/5.rv_timer_random.329161060 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 117069839774 ps |
| CPU time | 116.6 seconds |
| Started | Sep 03 11:58:17 PM UTC 24 |
| Finished | Sep 04 12:00:16 AM UTC 24 |
| Peak memory | 199872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329161060 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.329161060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/5.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/5.rv_timer_random_reset.807593112 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 519278914 ps |
| CPU time | 1.5 seconds |
| Started | Sep 03 11:58:22 PM UTC 24 |
| Finished | Sep 03 11:58:24 PM UTC 24 |
| Peak memory | 198880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807593112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.807593112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/5.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/50.rv_timer_random.2555033879 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 157669730787 ps |
| CPU time | 944.39 seconds |
| Started | Sep 04 12:16:36 AM UTC 24 |
| Finished | Sep 04 12:32:31 AM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555033879 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2555033879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/50.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/51.rv_timer_random.1822679364 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 220236337668 ps |
| CPU time | 223.23 seconds |
| Started | Sep 04 12:16:38 AM UTC 24 |
| Finished | Sep 04 12:20:24 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822679364 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1822679364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/51.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/52.rv_timer_random.992971994 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 34677432567 ps |
| CPU time | 87.82 seconds |
| Started | Sep 04 12:16:45 AM UTC 24 |
| Finished | Sep 04 12:18:14 AM UTC 24 |
| Peak memory | 199596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992971994 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.992971994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/52.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/54.rv_timer_random.3538032563 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 97242523632 ps |
| CPU time | 499.68 seconds |
| Started | Sep 04 12:16:51 AM UTC 24 |
| Finished | Sep 04 12:25:17 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538032563 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3538032563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/54.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/55.rv_timer_random.2560407131 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 130083387486 ps |
| CPU time | 428.39 seconds |
| Started | Sep 04 12:16:54 AM UTC 24 |
| Finished | Sep 04 12:24:08 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560407131 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2560407131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/55.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/56.rv_timer_random.1410418759 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 163445306890 ps |
| CPU time | 104.05 seconds |
| Started | Sep 04 12:16:57 AM UTC 24 |
| Finished | Sep 04 12:18:43 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410418759 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1410418759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/56.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/58.rv_timer_random.652300564 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 107851592875 ps |
| CPU time | 206.29 seconds |
| Started | Sep 04 12:17:21 AM UTC 24 |
| Finished | Sep 04 12:20:51 AM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652300564 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.652300564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/58.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/59.rv_timer_random.86159546 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 226236775417 ps |
| CPU time | 1013.56 seconds |
| Started | Sep 04 12:17:30 AM UTC 24 |
| Finished | Sep 04 12:34:35 AM UTC 24 |
| Peak memory | 202544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86159546 -assert nopostproc +UVM_TESTNAME= rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.86159546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/59.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/6.rv_timer_cfg_update_on_fly.3748564589 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 246374138453 ps |
| CPU time | 542.14 seconds |
| Started | Sep 03 11:58:42 PM UTC 24 |
| Finished | Sep 04 12:07:50 AM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748564589 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_cfg_update_on_fly.3748564589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/6.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/6.rv_timer_disabled.1025711718 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 888058323513 ps |
| CPU time | 452.38 seconds |
| Started | Sep 03 11:58:41 PM UTC 24 |
| Finished | Sep 04 12:06:19 AM UTC 24 |
| Peak memory | 199876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025711718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.1025711718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/6.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/6.rv_timer_random_reset.2139792044 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 37764080234 ps |
| CPU time | 73.36 seconds |
| Started | Sep 03 11:58:44 PM UTC 24 |
| Finished | Sep 04 12:00:00 AM UTC 24 |
| Peak memory | 199708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139792044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2139792044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/6.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/60.rv_timer_random.579405390 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 46567571956 ps |
| CPU time | 70.66 seconds |
| Started | Sep 04 12:17:30 AM UTC 24 |
| Finished | Sep 04 12:18:42 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579405390 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.579405390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/60.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/61.rv_timer_random.390710046 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 69349486011 ps |
| CPU time | 108.74 seconds |
| Started | Sep 04 12:17:33 AM UTC 24 |
| Finished | Sep 04 12:19:23 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390710046 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.390710046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/61.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/62.rv_timer_random.2231083968 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 157946768088 ps |
| CPU time | 373.57 seconds |
| Started | Sep 04 12:17:39 AM UTC 24 |
| Finished | Sep 04 12:23:57 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231083968 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2231083968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/62.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/63.rv_timer_random.920771409 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 297974902818 ps |
| CPU time | 320.97 seconds |
| Started | Sep 04 12:18:15 AM UTC 24 |
| Finished | Sep 04 12:23:41 AM UTC 24 |
| Peak memory | 199780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920771409 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.920771409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/63.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/66.rv_timer_random.3630870581 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 22389805040 ps |
| CPU time | 66.23 seconds |
| Started | Sep 04 12:18:28 AM UTC 24 |
| Finished | Sep 04 12:19:36 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630870581 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3630870581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/66.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/67.rv_timer_random.3793560177 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 55715202078 ps |
| CPU time | 1252.08 seconds |
| Started | Sep 04 12:18:36 AM UTC 24 |
| Finished | Sep 04 12:39:43 AM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793560177 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3793560177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/67.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/68.rv_timer_random.1311031466 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 165810207621 ps |
| CPU time | 212.88 seconds |
| Started | Sep 04 12:18:43 AM UTC 24 |
| Finished | Sep 04 12:22:19 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311031466 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1311031466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/68.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/69.rv_timer_random.3097089216 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 176384724162 ps |
| CPU time | 117.89 seconds |
| Started | Sep 04 12:18:44 AM UTC 24 |
| Finished | Sep 04 12:20:44 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097089216 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3097089216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/69.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/7.rv_timer_cfg_update_on_fly.1632050688 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 997208840410 ps |
| CPU time | 299.04 seconds |
| Started | Sep 03 11:58:50 PM UTC 24 |
| Finished | Sep 04 12:03:53 AM UTC 24 |
| Peak memory | 199600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632050688 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_cfg_update_on_fly.1632050688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/7.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/7.rv_timer_disabled.295202945 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 488580819905 ps |
| CPU time | 257.88 seconds |
| Started | Sep 03 11:58:50 PM UTC 24 |
| Finished | Sep 04 12:03:11 AM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295202945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST _SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.295202945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/7.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/7.rv_timer_random.2698322638 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 119841514430 ps |
| CPU time | 262.22 seconds |
| Started | Sep 03 11:58:50 PM UTC 24 |
| Finished | Sep 04 12:03:16 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698322638 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2698322638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/7.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/7.rv_timer_random_reset.3187180700 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 81573469 ps |
| CPU time | 0.88 seconds |
| Started | Sep 03 11:58:50 PM UTC 24 |
| Finished | Sep 03 11:58:52 PM UTC 24 |
| Peak memory | 198876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187180700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3187180700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/7.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/70.rv_timer_random.3273128796 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 73756851919 ps |
| CPU time | 86.59 seconds |
| Started | Sep 04 12:18:56 AM UTC 24 |
| Finished | Sep 04 12:20:24 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273128796 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3273128796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/70.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/73.rv_timer_random.666870543 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 102369083514 ps |
| CPU time | 592.8 seconds |
| Started | Sep 04 12:19:17 AM UTC 24 |
| Finished | Sep 04 12:29:17 AM UTC 24 |
| Peak memory | 199680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666870543 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.666870543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/73.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/74.rv_timer_random.2568822844 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 522326042975 ps |
| CPU time | 408.69 seconds |
| Started | Sep 04 12:19:24 AM UTC 24 |
| Finished | Sep 04 12:26:18 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568822844 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2568822844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/74.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/75.rv_timer_random.1736271538 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 156081178804 ps |
| CPU time | 524.5 seconds |
| Started | Sep 04 12:19:25 AM UTC 24 |
| Finished | Sep 04 12:28:17 AM UTC 24 |
| Peak memory | 199808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736271538 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1736271538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/75.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/76.rv_timer_random.389887240 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 483660754794 ps |
| CPU time | 259.44 seconds |
| Started | Sep 04 12:19:31 AM UTC 24 |
| Finished | Sep 04 12:23:53 AM UTC 24 |
| Peak memory | 199744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389887240 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.389887240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/76.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/77.rv_timer_random.412680010 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 394744224184 ps |
| CPU time | 1901.02 seconds |
| Started | Sep 04 12:19:37 AM UTC 24 |
| Finished | Sep 04 12:51:39 AM UTC 24 |
| Peak memory | 202484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412680010 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.412680010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/77.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/79.rv_timer_random.3087374650 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 199580512985 ps |
| CPU time | 172.2 seconds |
| Started | Sep 04 12:20:01 AM UTC 24 |
| Finished | Sep 04 12:22:56 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087374650 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3087374650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/79.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/8.rv_timer_cfg_update_on_fly.3004172403 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2310816767 ps |
| CPU time | 4.98 seconds |
| Started | Sep 03 11:59:08 PM UTC 24 |
| Finished | Sep 03 11:59:14 PM UTC 24 |
| Peak memory | 199688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004172403 -assert nopostpr oc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_cfg_update_on_fly.3004172403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/8.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/8.rv_timer_disabled.3829824311 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 500423001102 ps |
| CPU time | 217.65 seconds |
| Started | Sep 03 11:59:06 PM UTC 24 |
| Finished | Sep 04 12:02:46 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829824311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3829824311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/8.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/8.rv_timer_random_reset.2714838696 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 242463853758 ps |
| CPU time | 137.38 seconds |
| Started | Sep 03 11:59:10 PM UTC 24 |
| Finished | Sep 04 12:01:29 AM UTC 24 |
| Peak memory | 199848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714838696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2714838696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/8.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/8.rv_timer_stress_all.2012319876 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 756974571910 ps |
| CPU time | 1190 seconds |
| Started | Sep 03 11:59:10 PM UTC 24 |
| Finished | Sep 04 12:19:12 AM UTC 24 |
| Peak memory | 202352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012319876 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.2012319876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/8.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/80.rv_timer_random.1069183219 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 140527378759 ps |
| CPU time | 718.17 seconds |
| Started | Sep 04 12:20:10 AM UTC 24 |
| Finished | Sep 04 12:32:16 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069183219 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1069183219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/80.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/81.rv_timer_random.633444583 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 897340683842 ps |
| CPU time | 644.6 seconds |
| Started | Sep 04 12:20:22 AM UTC 24 |
| Finished | Sep 04 12:31:14 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633444583 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.633444583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/81.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/82.rv_timer_random.293767437 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 186284331952 ps |
| CPU time | 2094.66 seconds |
| Started | Sep 04 12:20:24 AM UTC 24 |
| Finished | Sep 04 12:55:43 AM UTC 24 |
| Peak memory | 202408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293767437 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.293767437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/82.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/84.rv_timer_random.2343149886 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 235792151915 ps |
| CPU time | 329.15 seconds |
| Started | Sep 04 12:20:26 AM UTC 24 |
| Finished | Sep 04 12:25:59 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343149886 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2343149886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/84.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/86.rv_timer_random.1034459818 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 45043527083 ps |
| CPU time | 1417.36 seconds |
| Started | Sep 04 12:20:45 AM UTC 24 |
| Finished | Sep 04 12:44:37 AM UTC 24 |
| Peak memory | 202612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034459818 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1034459818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/86.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/88.rv_timer_random.4129281609 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 530311650345 ps |
| CPU time | 221.38 seconds |
| Started | Sep 04 12:20:51 AM UTC 24 |
| Finished | Sep 04 12:24:35 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129281609 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.4129281609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/88.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/89.rv_timer_random.6604068 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 109390150860 ps |
| CPU time | 406.01 seconds |
| Started | Sep 04 12:21:24 AM UTC 24 |
| Finished | Sep 04 12:28:16 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6604068 -assert nopostproc +UVM_TESTNAME=r v_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.6604068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/89.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/9.rv_timer_cfg_update_on_fly.539770929 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 581916557294 ps |
| CPU time | 303.51 seconds |
| Started | Sep 03 11:59:16 PM UTC 24 |
| Finished | Sep 04 12:04:24 AM UTC 24 |
| Peak memory | 199660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabl ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539770929 -assert nopostpro c +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_cfg_update_on_fly.539770929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/9.rv_timer_cfg_update_on_fly/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/9.rv_timer_disabled.3050197018 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 108468926789 ps |
| CPU time | 184.82 seconds |
| Started | Sep 03 11:59:16 PM UTC 24 |
| Finished | Sep 04 12:02:24 AM UTC 24 |
| Peak memory | 199676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050197018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3050197018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/9.rv_timer_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/9.rv_timer_random.2075571672 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 564035306724 ps |
| CPU time | 638.75 seconds |
| Started | Sep 03 11:59:15 PM UTC 24 |
| Finished | Sep 04 12:10:01 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075571672 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2075571672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/9.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/9.rv_timer_random_reset.2286945240 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 451034188 ps |
| CPU time | 0.93 seconds |
| Started | Sep 03 11:59:21 PM UTC 24 |
| Finished | Sep 03 11:59:24 PM UTC 24 |
| Peak memory | 198872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286945240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TES T_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2286945240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/9.rv_timer_random_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all.827048372 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 333841660303 ps |
| CPU time | 551.95 seconds |
| Started | Sep 03 11:59:25 PM UTC 24 |
| Finished | Sep 04 12:08:43 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827048372 -assert nopostproc +UVM_TESTNAME =rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.827048372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/9.rv_timer_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/9.rv_timer_stress_all_with_rand_reset.3396453317 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2616376457 ps |
| CPU time | 33.96 seconds |
| Started | Sep 03 11:59:24 PM UTC 24 |
| Finished | Sep 03 11:59:59 PM UTC 24 |
| Peak memory | 203968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3396453317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.rv_timer_stress_all_with_rand_reset.3396453317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/9.rv_timer_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/90.rv_timer_random.3835422966 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 112992852573 ps |
| CPU time | 221.15 seconds |
| Started | Sep 04 12:21:27 AM UTC 24 |
| Finished | Sep 04 12:25:12 AM UTC 24 |
| Peak memory | 199872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835422966 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3835422966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/90.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/92.rv_timer_random.3163964773 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 504042801748 ps |
| CPU time | 260.01 seconds |
| Started | Sep 04 12:22:11 AM UTC 24 |
| Finished | Sep 04 12:26:34 AM UTC 24 |
| Peak memory | 199704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163964773 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3163964773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/92.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/94.rv_timer_random.1305026526 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 828972680622 ps |
| CPU time | 384.52 seconds |
| Started | Sep 04 12:22:54 AM UTC 24 |
| Finished | Sep 04 12:29:24 AM UTC 24 |
| Peak memory | 199672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305026526 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1305026526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/94.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/95.rv_timer_random.3822823469 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 107608418802 ps |
| CPU time | 484.38 seconds |
| Started | Sep 04 12:22:56 AM UTC 24 |
| Finished | Sep 04 12:31:07 AM UTC 24 |
| Peak memory | 199668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822823469 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3822823469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/95.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/96.rv_timer_random.2474835929 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 132557062996 ps |
| CPU time | 77.89 seconds |
| Started | Sep 04 12:23:21 AM UTC 24 |
| Finished | Sep 04 12:24:40 AM UTC 24 |
| Peak memory | 199456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474835929 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2474835929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/96.rv_timer_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/coverage/default/97.rv_timer_random.2985593000 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 142966308199 ps |
| CPU time | 170.04 seconds |
| Started | Sep 04 12:23:27 AM UTC 24 |
| Finished | Sep 04 12:26:20 AM UTC 24 |
| Peak memory | 199844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985593000 -assert nopostproc +UVM_TESTNAM E=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/rv_timer-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2985593000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/rv_timer-sim-vcs/97.rv_timer_random/latest |
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